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Switching dual-band reconfigurable microwave amplifiers for flexible communication systems

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ABSTRACT
Title of Dissertation:
SWITCHING DUAL-BAND RECONFIGURABLE
MICROWAVE AMPLIFIERS FOR FLEXIBLE
COMMUNICATION SYSTEMS
Duane St. M. Harvey, D.Eng. May 2012
Dissertation Chair:
Dr. Carl White, Ph.D.
Associate Dean, Electrical Engineering
The convergence of information, ideas and people in today’s modern world lends
itself largely to the evolution of modern communication systems. With the drive for rapid
and efficient integration of competing communication standards comes the need for
development of innovative circuits required to build innovative communication systems
hardware; this hardware being the backbone of integrated communication systems. This
dissertation involves the development of switchable dual-band reconfigurable microwave
amplifiers for application to flexible communication systems. The predominant benefit of
this achievement is reduction of the system cost, power consumption, size and weight of
mobile, wireless, and satellite communication systems. A novel design technique for
developing reconfigurable microwave power amplifiers is explored, based on
developments of more traditional amplifier designs and Transmit/Receive (T/R) module
switching technology. First, a Monolithic Microwave Integrated Circuit (MMIC) based
dual-band reconfigurable power amplifier was developed in the Triquint 0.5-um
MESFET foundry process using two independent power amplifiers operating at 5.5 GHz
(C-band) and 8.5 GHz (X-band) controlled by a high performance Radio Frequency (RF)
switch. The output power achieved by the C-band and X-band MMIC power amplifiers
was 12-dBm and 11-dBm, respectively for approximately 0-dBm of input power. The
broadband RF switch achieved an insertion loss of between 1.2- and 1.5-dB, with port-toport isolation of better than 25dB. Next, a Microwave Integrated Circuit (MIC)
reconfigurable low-noise amplifier (LNA) was developed based on the switching
reconfigurable architecture of the MMIC power amplifier, though implemented as a
printed circuit board (PCB) design. The MIC reconfigurable LNA utilizes two
independent amplifiers operating at L-band and S-band, which are selected independently
using a MIC RF switch. Both the L-band and S-band amplifiers achieved a gain of 18-dB
and noise figure of 2-dB. The broadband RF switch achieved an insertion loss of 4dB and
switch-to-switch isolation of 13.7dB for switch #1 operation, while switch #2 had less
stellar performance of 8dB insertion loss and -21dB isolation.
SWITCHING DUAL-BAND RECONFIGURABLE MICROWAVE AMPLIFIERS FOR
FLEXIBLE COMMUNICATION SYSTEMS
by
Duane St. Michael Harvey
A Dissertation Submitted in Partial Fulfillment of the Requirements for the Degree
Doctor of Engineering
MORGAN STATE UNIVERSITY
May 2012
UMI Number: 3516871
All rights reserved
INFORMATION TO ALL USERS
The quality of this reproduction is dependent on the quality of the copy submitted.
In the unlikely event that the author did not send a complete manuscript
and there are missing pages, these will be noted. Also, if material had to be removed,
a note will indicate the deletion.
UMI 3516871
Copyright 2012 by ProQuest LLC.
All rights reserved. This edition of the work is protected against
unauthorized copying under Title 17, United States Code.
ProQuest LLC.
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P.O. Box 1346
Ann Arbor, MI 48106 - 1346
SWITCHING DUAL-BAND RECONFIGURABLE MICROWAVE AMPLIFIERS FOR
FLEXIBLE COMMUNICATION SYSTEMS
by
Duane St. Michael Harvey
has been approved
February 2012
DISSERTATION COMMITTEE APPROVAL:
___________________________, Chair
Dr. Carl White, Ph. D.
___________________________, Co-Chair
Dr. Michel Reece, D. Eng.
___________________________
Dr. Jeyasingh Nithianandam, Ph. D.
___________________________
Dr. Gregory Wilkins, Ph. D.
ii
DEDICATION
To my loving family, who has endured and supported me through my many years of
personal growth, pursuits in academia, and many long days chasing professional
challenges.
To the younger generation of Scientists, Technologists, Mathematicians and Engineers
that will arrive in their own time.
To all of the people who mentored me through learning to appreciate and apply my
intellect and knowledge.
iii
ACKNOWLEDGEMENT
I would like to express my sincere and supreme thanks to appreciation to my co-advisers
Dr. Carl White and Dr. Michel Reece for the constant support and encouragement
spanning many years while I pursued this work. I would like to extend special thanks to
Dr. Gregory Wilkins and Dr. Jeyasingh Nithianandam for accepting my committee
positions and for giving me valuable feedback that contributed well to this body of work.
Thanks to Dr. Eric Chikando and Mrs. Caroline Waiyaki for the peer support and
feedback during the educational phase of this project as well as moral support during
many of the late nights and weekends involved. I would like to thank my good lifelong
friend and colleague Mr. Maurice Clennon for being there at every turn, always giving
good feedback and advice as well as entertaining countless discussions on just about
every aspect of this subject. I am grateful for the support of the Center of Microwave,
Satellite and RF Engineering (COMSARE) at Morgan State University for providing the
resources and research opportunities via the NASA University Research Consortium
(URC) grant, without which this work would not have been possible. Special thanks to
Mr. John Penn of The Johns Hopkins University for his support and resources for
completing the MMIC work. Last, but most important of all, I would like to thank my
wife Mrs. Teresa Harvey and my parents Mr. and Mrs. Lester Harvey for their constant
support and encouragement to find the drive to complete this doctorate work. Special
thanks to my brothers, sisters, daughters, nieces and nephews for providing the
inspiration to lay a foundational example on which they can build and to which I hope
they surpass. All my family have truly been a blessing, a monumental achievement by
our creator to whom I give the greatest thanks.
iv
TABLE OF CONTENTS
DEDICATION .............................................................................................................. iii
ACKNOWLEDGEMENT ................................................................................................. iv
LIST OF FIGURES .......................................................................................................... vii
LIST OF TABLES .............................................................................................................. x
CHAPTER 1
INTRODUCTION ................................................................................. 1
1.1.
Motivation ............................................................................................. 1
1.2.
State of the Art ....................................................................................... 2
1.3.
Thesis Outline ........................................................................................ 8
CHAPTER 2
PURPOSE OF RESEARCH................................................................ 10
CHAPTER 3
LITERATURE REVIEW .................................................................... 11
3.1.
Review of Current Adaptive Communication Systems ....................... 11
3.1.1.
Reconfigurable System and Applications............................................ 11
3.1.2.
Reconfigurable Transceivers and Receiver Front-Ends ...................... 15
3.2.
Review of Reconfigurable Amplifier Technology .............................. 17
3.3.
Review of RF Switch Technology....................................................... 24
3.3.1.
Diode Switches .................................................................................... 25
3.3.2.
FET Switches ....................................................................................... 28
3.3.3.
RF MEMS Switches ............................................................................ 30
CHAPTER 4
RESEARCH METHODOLOGY ........................................................ 31
4.1.
Dual-Band Reconfigurable Power Amplifier (RPA)........................... 31
4.1.1.
PA Design Specifications .................................................................... 31
4.1.2.
PA Design Approach ........................................................................... 32
4.1.2.1.
Biasing Network and Stability............................................................. 33
4.1.2.2.
Output Matching Network (OMN) ...................................................... 35
4.1.2.3.
Input Matching Network (IMN) .......................................................... 37
4.2.
FET RF Switch .................................................................................... 42
4.2.1.
RF Switch Design Approach ............................................................... 42
4.2.2.
FET RF Switch Design Notes ............................................................. 44
4.3.
Dual-Band Reconfigurable Low-Noise Amplifier (RLNA) ................ 44
4.3.1.
LNA Design Specifications ................................................................. 46
4.3.2.
LNA Design Approach ........................................................................ 46
4.3.2.1.
DC Biasing .......................................................................................... 47
4.3.2.2.
Stabilizing the FET .............................................................................. 48
4.3.2.3.
LNA Noise/Input Matching ................................................................. 50
4.3.2.4.
LNA Output Matching......................................................................... 53
CHAPTER 5
DESIGN EVALUATION AND MEASURMENTS ........................... 55
5.1.
Small-Signal RF Measurements .......................................................... 55
5.2.
RF Noise Figure Measurements .......................................................... 56
5.3.
RF Power Measurements ..................................................................... 56
CHAPTER 6
SCOPE AND LIMITATIONS OF STUDY ........................................ 58
6.1.
Scope of Project ................................................................................... 58
6.2.
Limitations of Study ............................................................................ 59
CHAPTER 7
MMIC C/X-BAND RECONFIGURABLE AMPLIFIER ................... 60
7.1.
C/X-Band Reconfigurable Power Amplifier (RPA) ............................ 60
v
7.1.1.
C-Band PA ........................................................................................... 63
7.1.1.1.
C-Band PA Design .............................................................................. 63
7.1.1.2.
C-Band PA Fabrication and Characterization ..................................... 65
7.1.2.
X-Band PA .......................................................................................... 68
7.1.2.1.
X-Band PA Design .............................................................................. 68
7.1.2.2.
X-Band PA Fabrication and Characterization ..................................... 70
7.1.3.
Broad-Band MMIC RF FET Switch ................................................... 72
7.1.3.1.
Broad-Band MMIC RF FET Switch Design ....................................... 72
7.1.3.2.
Broad-Band MMIC Switch Fabrication and Characterization ............ 75
CHAPTER 8
MIC L/S-BAND RECONFIGURABLE AMPLIFIER ....................... 77
8.1.
Switched-Based L/S-Band Reconfigurable LNA ................................ 77
8.1.1.
RLNA Specifications and Architecture ............................................... 77
8.1.2.
L-Band LNA ........................................................................................ 81
8.1.3.
L-Band LNA Design ........................................................................... 81
8.1.4.
L-Band LNA Fabrication and Characterization .................................. 84
8.1.5.
S-Band LNA ........................................................................................ 86
8.1.6.
S-Band LNA Design ............................................................................ 87
8.1.7.
S-Band LNA Fabrication and Characterization................................... 90
8.1.8.
Broad-Band MIC RF FET Switch ....................................................... 92
8.1.9.
Broad-Band MIC RF FET Switch Design ........................................... 93
8.1.10.
Broad-Band MIC Switch Fabrication and Characterization................ 96
8.1.11.
RLNA Issues and Challenges .............................................................. 98
CHAPTER 9
ALTERNATIVE TOPLOGIES FOR FUTER INVESTIGATION .. 100
9.1.
L-Band Dual-Mode Coupled Resonator Band Pass Filter (CR-BPF) 100
9.1.1.
CR-BPF Design ................................................................................. 100
9.1.2.
CR-BPF Fabrication and Characterization ........................................ 102
9.2.
RLNA Topology for Future Investigation ......................................... 103
9.3.
Coupled Resonator Filter Based L/S-Band Reconfigurable LNA..... 103
9.3.1.
CR-RLNA Specifications .................................................................. 104
9.3.2.
CR-LNA Topology ............................................................................ 105
CHAPTER 10
CONCLUSION ................................................................................. 106
BIBLIOGRAPHY ........................................................................................................... 108
APPENDIX I.
MIC RLNA Board Layouts ............................................................... 112
APPENDIX II. MIC RLNA Bill of Materials ............................................................ 113
vi
LIST OF FIGURES
Figure 1: Interoperable Networks for Next-Gen Communication [4] ................................ 2
Figure 2: Typical Amplifier Topology [4] .......................................................................... 3
Figure 3: Typical Reconfigurable Amplifier Design Architectures [4] .............................. 4
Figure 4: Wireless Systems Frequency Allocation [26] ..................................................... 6
Figure 5: Concept of Interoperable Next-Gen Communication System ........................... 12
Figure 6: Wireless Systems and Service Areas [26] ......................................................... 13
Figure 7: SDR Receiver Block Diagram [9] ..................................................................... 14
Figure 8: General Transceiver Block Diagram [10] ......................................................... 15
Figure 9: Traditional Receiver Architectures [13] ............................................................ 16
Figure 10: Example Zero/Low-IF Multi-Standard Receiver [25]..................................... 17
Figure 11: Example Direct Conversion Multi-Standard Transmitter [25]........................ 17
Figure 12: Unit-Selection Reconfigurable Amplifier [4].................................................. 18
Figure 13: Broadband-Matching reconfigurable Amplifier [4] ........................................ 19
Figure 14: Variable-Matching Reconfigurable Amplifier [4] .......................................... 19
Figure 15: Band-Switchable Matching Network Operation ............................................. 20
Figure 16: Muti-Band Band-Switchable Amplifier [4] .................................................... 21
Figure 17: MEMS Based Class-E Reconfigurable PA [7]................................................ 21
Figure 18: Lu-Peroulis MEMS Class-AB Amplifier [6] .................................................. 22
Figure 19: Yao Reconfigurable LNA Block Diagram [3] ................................................ 23
Figure 20: Yao Common-Source LNA [5] ....................................................................... 23
Figure 21: Yao Switchable Differential Inductor [3][5] ................................................... 24
Figure 22: Illustration of Absorptive Switch [29]............................................................. 25
Figure 23: PIN Diode SPST Switches [29]....................................................................... 26
Figure 24: PIN Diode SPDT Switches [29] ...................................................................... 27
Figure 25: PIN Diode T/R Switches [30] ......................................................................... 27
Figure 26: Simplified Single-FET SPST Switch [30]....................................................... 28
Figure 27: Single Positive Control Voltage FET SPST Switch [30] ................................ 29
Figure 28: T/R SPDT FET Switch [30] ............................................................................ 29
Figure 29: Single-Stage PA Architecture ......................................................................... 32
Figure 30: Biased and Stabilized FET .............................................................................. 33
Figure 31: Simulated Stability Test Result ....................................................................... 34
Figure 32: I-V Curve and DC Load-Line of Stable FET .................................................. 34
Figure 33: Gain, Stable gain and Max Gain of Stabilized FET ........................................ 35
Figure 34: Cripps RC Network for 5.5GHz PA................................................................ 36
Figure 35: Output Match for 5.5GHz Cripps RC Network .............................................. 36
Figure 36: Cripps RC Network for 8.5GHz PA................................................................ 36
Figure 37: Output Match for 8.5GHz Cripps RC Network .............................................. 37
Figure 38: RPA OMNs for 5.5GHz PA (a) and 8.5GHz PA (b) ...................................... 37
Figure 39: 5.5GHz PA Output Match in Circuit ............................................................... 38
Figure 40: Optimum Reflection for 5.5 GHz IMN ........................................................... 38
Figure 41: IMN for 5.5GHz PA ........................................................................................ 38
Figure 42: 5.5GHz PA Design .......................................................................................... 39
Figure 43: S-Parameter and Power Simulation for 5.5GHz PA ....................................... 39
Figure 44: 8.5GHz PA Output Match in Circuit ............................................................... 40
Figure 45: Optimum Reflection for 8.5 GHz IMN ........................................................... 40
vii
Figure 46: IMN for 8.5GHz PA ........................................................................................ 41
Figure 47: 8.5GHz PA Design .......................................................................................... 41
Figure 48: S-Parameter and Power Simulation for 8.5GHz PA ....................................... 41
Figure 49: GaAs FET RF Switch ...................................................................................... 43
Figure 50: Distortion Slopes (2nd/3rd - Order) ................................................................ 45
Figure 51: 1-dB Compression Point ................................................................................. 45
Figure 52: Single-Stage LNA Topology ........................................................................... 47
Figure 53: FET Self-Biasing Network .............................................................................. 48
Figure 54: Output resistive Loading Topology................................................................. 49
Figure 55: LNA Input Noise Match .................................................................................. 51
Figure 56: TXLINE Microstrip Line Calculator ............................................................... 52
Figure 57: L-Band Input Matching Network .................................................................... 52
Figure 58: L-Band LNA with Computed IMN and OMN ................................................ 54
Figure 59: S-Band LNA with Computed IMN and OMN ................................................ 54
Figure 60: VNA Setup for Small Signal RF Measurements ............................................. 55
Figure 61: NF Measurement Setup ................................................................................... 56
Figure 62: RF Power Measurement Test Bench ............................................................... 57
Figure 63: RPA Block Diagram ........................................................................................ 58
Figure 64: RLNA Block Diagram..................................................................................... 59
Figure 65: C/X-Band RPA Block Diagram ...................................................................... 60
Figure 66: C/X-Band RPA Block Diagram with Pads...................................................... 61
Figure 67: Final C/X-Band MMIC RPA Layout .............................................................. 62
Figure 68: Simulated RPA Small-Signal S-Parameters .................................................... 62
Figure 69: Schematic of 5.5GHz Power Amplifier .......................................................... 63
Figure 70: Layout Topology of the 5.5GHz Power Amplifier ......................................... 64
Figure 71: Final Layout of the 5.5GHz Power Amplifier................................................ 64
Figure 72: Simulated RF Performance of the 5.5GHz Power Amplifier.......................... 65
Figure 73: Padded Layout for the 5.5GHz Power Amplifier ............................................ 65
Figure 74: Layout of Testing RPA.................................................................................... 66
Figure 75: S-Parameter Measurements for the 5.5GHz Power Amplifier ........................ 67
Figure 76: Power Measurements for 5.5GHz Power Amplifier ....................................... 67
Figure 77: X-Band Power Amplifier Schematic ............................................................... 68
Figure 78: Microstrip Circuit Layout of the 8.5GHz Power Amplifier ............................ 69
Figure 79: Unpadded Layout for 8.5GHz Power Amplifier ............................................. 69
Figure 80: S-Parameter and Power Simulations for 8.5GHz PA ...................................... 70
Figure 81: Padded Layout of the 8.5GHz Power Amplifier ............................................. 70
Figure 82: Measure S-Parameters for the 8.5GHz PA...................................................... 71
Figure 83: Power Measurements for the 8.5GHz PA ....................................................... 71
Figure 84: Broad-Band MMIC RF FET Switch Design ................................................... 72
Figure 85: Broad-Band MMIC RF FET Switch Circuit Layout ....................................... 73
Figure 86: Unpadded Broad-Band MMIC RF Switch Layout.......................................... 74
Figure 87: Broad-Band MMIC RF Switch S-Parameter Simulation ................................ 74
Figure 88: Padded Layout of Broad-Band MMIC RF FET Switch .................................. 75
Figure 89: Broad-Band MMIC RF FET Switch S-Parameter Measurements .................. 76
Figure 90: L/S-Band LNA ................................................................................................ 78
Figure 91: L/S-Band RLNA Layout ................................................................................. 79
Figure 92: Milled L/S-Band RLNA Circuit ...................................................................... 80
Figure 93: Fabricated L/S-Band RLNA Wired in Test Fixture ........................................ 80
viii
Figure 94: L-Band LNA Schematic .................................................................................. 81
Figure 95: L-Band LNA Layout ....................................................................................... 82
Figure 96: L-Band LNA Placement and Etching Artwork ............................................... 82
Figure 97: L-Band LNA Simulated S-Parameters ............................................................ 83
Figure 98: L-Band LNA Simulated Noise Figure............................................................. 83
Figure 99: Milled L-Band LNA Circuit ............................................................................ 84
Figure 100: L-Band LNA Mounted in Test Fixture ......................................................... 84
Figure 101: L-Band LNA Measured vs. Simulated S-Parameters .................................... 85
Figure 102: L-Band LNA Measured Gain and Noise Figure ........................................... 86
Figure 103: S-Band LNA Schematic ................................................................................ 87
Figure 104: S-Band LNA Layout ..................................................................................... 88
Figure 105: S-Band LNA Placement and Etching Artwork ............................................. 88
Figure 106: S-Band LNA Simulated S-Parameters .......................................................... 89
Figure 107: L-Band LNA Simulated Noise Figure........................................................... 89
Figure 108: Milled S-Band LNA Circuit .......................................................................... 90
Figure 109: S-Band LNA Mounted in Test Fixture .......................................................... 90
Figure 110: S-Band LNA Measured vs. Simulated S-Parameters .................................... 91
Figure 111: S-Band LNA Measured Gain and Noise Figure ............................................ 92
Figure 112: L/S-Band FET RF Switch Schematic............................................................ 93
Figure 113: L/S-Band MIC RF Switch Layout................................................................. 94
Figure 114: L/S-Band MIC RF Switch Placement and Etching Artwork ........................ 95
Figure 115: L/S-Band MIC RF Switch S-Parameters ...................................................... 95
Figure 116: Milled Broad-Band MIC Switch Circuit ....................................................... 96
Figure 117: MIC RF Switch Mounted in Test Fixture ..................................................... 96
Figure 118: MIC RF Switch - Measured Switch #1 S-Parameters ................................... 97
Figure 119: MIC RF Switch - Measured Switch #2 S-Parameters ................................... 98
Figure 120: L-Band Dual Mode BPF Design ................................................................. 101
Figure 121: BPF Simulated S-Parameters ...................................................................... 101
Figure 122: Fabricated BPG on RT/Duroid .................................................................... 102
Figure 123: Measured S-Parameters for Fabricated BPF ............................................... 103
Figure 124: Coupled Resonator Element ........................................................................ 104
Figure 125: Cross-Coupled Split-Ring Resonator Array ................................................ 104
Figure 126: Couple Resonator Reconfigurable LNA Topology ..................................... 105
Figure 127: L/S-Band RLNA Layouts ............................................................................ 112
ix
LIST OF TABLES
Table 1: Common Satellite Frequency Bands .................................................................... 7
Table 2: Wireless Communication Standards [13] ........................................................... 12
Table 3: Receiver Architecture Characteristics [13] ......................................................... 16
Table 4: PIN Diode Switch Characteristic Equations [29] ............................................... 26
Table 5: IL and ISOL for Single FET Switch ................................................................... 28
Table 6: Comparison of PIN Diode vs. FETs for Switching Applications [30] ............... 30
Table 7: Advantages and Disadvantages of RF MEMS Switches .................................... 30
Table 8: C/X-Band RPA Specifications ........................................................................... 31
Table 9: FET RF Switch State Table ................................................................................ 43
Table 10: LNA Design Specifications .............................................................................. 46
Table 11: Project Limitations............................................................................................ 59
Table 12: RLNA Minimum Specifications ....................................................................... 78
x
CHAPTER 1 INTRODUCTION
1.1. Motivation
Modern communication systems have evolved into a complex network of
transmitters, receivers, switches, relays and peripheral devices capable of supporting high
speed delivery of information destined for use in worldwide military, commercial,
educational, scientific and entertainment sectors. At the heart of such systems are various
digital, radio frequency (RF), microwave and optical circuits that enable efficient
operation of these constantly evolving communication systems.
Traditionally, these various systems are developed using an application specific
design methodology, requiring unique and specific design skill sets for an amalgamation
of engineers with focused individual specialties. Consequently, this approach presents a
challenging need for systems engineers to integrate increasingly complex systems that
often contain technologically repetitive or redundant components. This is especially true
for systems of similar function and implementation, often separated by mere differences
in frequency, bandwidth or power requirements. The obvious derivative of this approach
is repetitive circuit and system designs, hence leading to higher input costs to the
underlying application or business model.
1
Figure 1: Interoperable Networks for Next-Gen Communication [4]
It is imperative that new design concepts be utilized to address the growing need for
advanced communication systems and the interoperability of mobile and ubiquitous
networks such as the ones illustrated in Figure 1.
1.2. State of the Art
In recent years, circuit fabrication and design techniques have evolved to support
a new paradigm in systems engineering and design. That is, the idea of technology and
design re-use at every possible level from conception, through implementation, to
deployment. This approach naturally inspires flexibility, not simply for implementation,
but in concept and strategy for a new class of circuit and system design. The resulting
thoughts, ideas, experimentation and creativity is paving the way for the era of
reconfigurable circuits and systems, offering communication system flexibility through
dynamic control of frequency, bandwidth and power. Subsequently, many new systems
can be implemented using the same basic circuit components. Development of
reconfigurable circuits presents new and interesting challenges, but various design
techniques have been and is being developed to address technical obstacles to make these
2
new robust systems a reality. Among these new systems are multiband transceivers,
reconfigurable transceivers, software defined radios (SDR) and cognitive radios. Many of
these systems utilize architectures heavily dependent on multi-mode frequency
generation and multiband or reconfigurable amplifiers. Multi-mode frequency generation
techniques are well developed and often use a combination of mixing and phase locked
loop (PLL) techniques. However, reconfigurable amplifiers present some unique
challenges requiring varying design techniques to achieve multiband or band selectable
operation. One common scheme of designing reconfigurable amplifiers is to control the
scheme of the input and output matching networks which presents the desired respective
impedance to the input and output of the transistor. Figure 2 below illustrates this typical
arrangement.
Figure 2: Typical Amplifier Topology [4]
Of the new design techniques employed in reconfigurable amplifier design there
are basically three classes with the central strategy of altering the amplifier matching
networks: multi-unit switching/selecting amplifier, reconfigurable or tunable matching
networks based amplifier and broadband matching networks based amplifier with filter
banks. Figure 3 illustrates the conceptual differences in architecture of these three design
approaches.
3
Figure 3: Typical Reconfigurable Amplifier Design Architectures [4]
The unit-selection type in Figure 3(a) is by far the easiest approach for a multistandard transceiver design, which essentially uses different amplifier units for each
supported standard. The amplifier of Figure 3(b) is most often implemented as a multistage design involving two or more transistors with inter-stage matching networks
between each transistor. Conceptually, for this broadband approach, a filter bank would
be needed to select the right operating frequency within the designed bandwidth of the
amplifier. The most exotic of the three approaches, Figure 3(c), involves tunable
matching networks which can be implemented with switches and digital control logic as
described in [6], [7], and [12].
It is important to realize that the choice of architecture for a reconfigurable
amplifier design will be impacted by the type of amplifier and its intended application.
Some common types of amplifiers are Differential (DA), Gain (GA), Low-Noise (LNA)
and Power (PA) Amplifiers. Most often, reconfigurable design techniques are employed
4
for low-noise amplifiers in receiver designs and power amplifiers for transmitter designs.
Currently, the majority of radios utilized in commercial and military communication
systems use separate transceivers for each frequency band of operation, unless multiple
bands are close enough to be accommodated by a single broad-band transceiver design.
This traditional architecture tends to result in a more expensive (both in terms of
fabrication and power consumption) and larger radio (increased transceiver die size)
when optimized to operate over multiple frequency bands to suit network security and
flexibility requirements. Additionally, more complex timing and control circuits are
required for seamless and robust operation.
Nowhere is this problem more evident than in the commercial wireless
communication space where there are many different standards for various applications.
Some of these standards include Global System for Mobile Communications (GSM),
Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access
(WCDMA), Enhanced Data rates for GSM Evolution (EDGE), Universal Mobile
Telecommunications System (UMTS) and Time Division Synchronous Code Division
Multiple Access (TD-SCDMA) for mobile phone applications as well as IEEE
802.11a/b/g/n (WiFi) and IEEE 802.16d/e (Fixed/Mobile WiMAX) for wireless local
area network (WLAN) applications.
5
Figure 4: Wireless Systems Frequency Allocation [26]
To lower production cost of multi-mode communication devices and ease switching
between different communications standards, traditional design approaches are
insufficient and reconfigurable transceivers that can support more than one standard has
recently emerged as the best solution [25]. “Multi-mode, multi-band operation is one of
the key requirements for reconfigurable wireless transceivers” [5].
In addition to the established communication standards, there are tremendous
advanced research activities in the scientific, government and commercial satellite
communications (SATCOM) space involving frequency re-use of lower frequency
systems as well as new systems based on higher operating frequencies.
6
Table 1: Common Satellite Frequency Bands
Band
Uplink
Downlink
L/S
1.610 to 1.625 GHz
2.483 to 2.50 GHz
C
3.7 to 4.2 GHz
5.924 to 6.425 GHz
Ku
11.7 to 12.2 GHz
14.0 to 14.5 GHz
Ka
17.7 to 21.7 GHz
27.5 to 30.5 GHz
Most of the traditional satellite communication systems were developed for use between
frequencies of 1GHz to 30 GHz, corresponding to their respective bands as illustrated in
Table 1. L-band SATCOM systems such as Inmarsat and Iridium offer limited capacity
and is often used for first responder or extremely remote voice/data communication
applications. Re-banding or new frequency re-use equipment designs are part of ongoing
activities to sustain growing capacity requirements in this band. L-band frequencies are
also quite often used for reliable terrestrial communications between satellite equipment,
after down-conversion from higher frequencies used by more advance SATCOM
systems. There are many satellites that transmit at S-band frequencies which include a
significant number of Scientific, DoD and military satellites in low earth orbit (LEO),
geosynchronous orbit (GEO) and in inclined, highly eccentric orbit (HEO). C-band was
the first frequency band that was allocated for commercial telecommunications via
satellites and typically have only 24 radio transponders spaced 20 MHz apart, but with
the adjacent transponders on opposite polarizations to maximize capacity while
minimizing interference. One of the most notably Ku-band satellites is NASA's Tracking
Data Relay Satellite (TDRS) used for both space shuttle and International Space Station
(ISS) communications. Ku-band satellites are also used for backhauls and particularly for
satellite from remote locations back to a television network's studio for editing and
7
broadcasting. Since the Ku-band is split into multiple segments that vary by geographical
region by the International Telecommunication Union (ITU), future capacity is an
anticipated issue currently being addressed. As the satellite communications market
grows there is increased difficulty in assigning frequency resources in the commonly
used C/Ku frequency bands. Thus, there’s a growing demand for Ka-band satellites for
future satellite communication links. At higher Ka-band frequencies, however, ice, clouds
and rain can drastically reduce the received power level requiring appropriate system
design considerations.
The common issue between terrestrial and space-based communication systems is
that the demand for high-speed, high-capacity, reliable and mobile services are increasing
at a pace that demands more efficient use of the frequency spectrum. As a result all
communication equipment will eventually need to have a flexible or reconfigurable
architecture to better address such needs. This is true for commercial, military and
civilian applications.
1.3. Thesis Outline
The purpose of this research is stated in chapter 3, followed by a thorough the
assessment of current technologies and a discussion of various reconfigurable circuit
configurations and topologies through examination of literature search of relevant work
as presented in chapter 4. Chapter 5 discusses the fundamental research methodology and
approaches to developing the technology on which this thesis stands, followed by the
examination of the methods of testing and evaluation of the success criteria for this work,
detailed in chapter 6. The results of the research design and testing for the C/X-band
reconfigurable power amplifier and the L/S-band reconfigurable low noise amplifier are
8
presented in chapters 8 and 9, respectively. Lastly, alternate topologies and consideration
for future work are presented in chapter 10.
9
CHAPTER 2 PURPOSE OF RESEARCH
The goal of this research effort is to implement a new architecture based on T/R
module switching for multi-band amplifier circuits capable of operating over a prescribed
narrow band-width for non-neighboring center frequencies. The main focus of the design
effort is to demonstrate the successful performance of a Low-Noise Amplifier and Power
Amplifier that are switchable between at least two center frequencies, while meeting
established baseline performance criteria such as gain, power, noise and efficiency. The
capability of frequency switching by use of bias control of the transistors within the
switch will be demonstrated and all operating modes of the amplifier circuits will be
characterized. For this work the unit-selection approach of Figure 3(a) is employed for
both the dual-band PA design as well as the dual-band LNA design, based on its
historical use in complex communication systems. The tradeoff, of course, is that it
requires a low-loss switch with good port-to-port isolation.
10
CHAPTER 3 LITERATURE REVIEW
There have been and continues to be a great deal of work in the area of
reconfigurable circuits and communication systems done by many engineers in academia
and industry for both research and production. Before the designs described within this
work were conceived and implemented, a careful study of the existing literature was
performed to understand the existing state of the technology. Within the context of
adaptive and reconfigurable communication systems, particular attention was given to
reconfigurable amplifiers, both power amplifiers as well as low noise amplifiers. This
literature review was the basis for deriving the merits and justification for the design
approach undertaken for this work.
3.1. Review of Current Adaptive Communication Systems
Currently, new architectures for modern communication systems targets
autonomous adaptation to communication network configuration, which itself is
becoming increasingly reconfigurable in nature based on efficiency and security concerns
being addressed.
3.1.1. Reconfigurable System and Applications
Perhaps one of the most driving forces behind the development of reconfigurable
systems is the need for next-generation terminals, 4G and beyond. 4G involves
integration of many standards including Wireless Local Area Network (WLAN) and
Wireless Metropolitan Area Network (WMAN), among others illustrated in Table 2.
Such systems being proposed today are targeted to address one of three main
development directions: (a) provide coverage and accessibility to people traveling
11
between continents, (b) provide temporary solutions until new standards are fully
developed and accepted in the marketplace, (c) implementation of complementary
communication standards [1].
Table 2: Wireless Communication Standards [13]
Standards Frequency Band (MHz) Channel Bandwidth (MHz)
GSM
890 – 915
0.2
935 – 960
WCDMA
1920 – 1980
3.84
2110 – 2170
802.11a
5150 – 5250
20
5250 – 5350
5725 – 5825
802.11b
2400 – 2483.5
22
802.11g
2400 – 2483.5
22
WiMAX
2000 – 11000
1.25 – 28
GPS
1575.42
Bluetooth
2400 – 2483.5
1
“The wireless industry is at a crossroads. To meet the basic requirement for universal
coverage, the number of cellular providers is growing smaller while the size of their
networks is growing larger” [14]. Figure 5 shows the basic idea behind a near-universal
interoperable communication system where users access a unified wireless network
where each node access and support various technologies.
Figure 5: Concept of Interoperable Next-Gen Communication System
12
One of the challenges facing the military platforms today is to increase the
number of onboard RF functions, including radar, electronic warfare, communication and
navigation/positioning, without degrading their stealth capabilities. There is a drive to
develop a robust universal radio that serves military and DoD needs while capable of
being used for certain civilian uses such as law enforcement and disaster management.
These extraneous uses will require interoperability with commercial communication
systems across many service areas from Personal Area Network (PAN) to Mobile
Wireless Access (MWA), as illustrated in Figure 6.
Figure 6: Wireless Systems and Service Areas [26]
One of the challenges to interoperability is the inability to simultaneous achieve highspeed and wide-area communications. As a result many systems are developed to target
one of the following:
•
High speeds, short distances
•
Wide area, low speeds
13
With this conventional strategy, usable frequencies are allocated for specific service
formats [26] as illustrated in Figure 4. Ultimately, the desired end result is the
development and deployment of multi-standard front-end transceivers (radios) based on
reconfigurable functional RF subsystem and circuit blocks. Some of the key sought-after
features include multi-in/multi-out (MIMO) access techniques, MAC/PHY layer
cooperative communication and dynamic spectrum allocation (DSA). The latter requires
frequency agility and is most achievable through the use of software defined radios
(SDR) or cognitive radios (CR), with the majority of components implemented digitally
using intensive computing and processing.
Figure 7: SDR Receiver Block Diagram [9]
Figure 7 shows an example of a simplified SDR receiver block diagram implemented
with digital control of the reconfigurable front-end. Development of usable SDR and CR
are not without challenges. SDR, for example, are limited to narrowband systems due to
power consumption and the trade-off between spectrum flexibility and platform
space/power requirements [14]. A CR based system is similar to the SDR, but utilize
radio nodes capable of reconfiguring transceiver parameters based on interaction with the
network. So it makes perfect sense that the communication industry is migrating to a
14
system model that utilize the benefits of SDR and CR while leveraging the traditional
advantages of analog communication circuits at RF. As it turns out, one of the limits of
SDR is the unavailability of an adequate analog-to-digital converter (ADC) at baseband.
For the ideal SDR with an ADC right after the antenna, 6GHz bandwidth and greater than
14-bit resolution would be required. This combination of requirements is not currently
feasible so digitalization of the signal has to be performed at baseband [13].
3.1.2. Reconfigurable Transceivers and Receiver Front-Ends
Transceivers today are comprised of two components, a digital baseband
component and an analog RF front-end component, for both the receiver and the
transmitter as illustrated in Figure 8.
Figure 8: General Transceiver Block Diagram [10]
Traditionally many, if not all, receivers are developed around one of the four
architectures illustrated in Figure 9 – (a) Superheterodyne, (b) Zero-IF, (c) Low-IF and
(d) Wideband IF double conversion.
15
Figure 9: Traditional Receiver Architectures [13]
There are numerous advantages and disadvantages for each of these architectures, but
clearly from Table 3 the Zero-IF architecture has the most advantages for multi-standard
implementation.
Table 3: Receiver Architecture Characteristics [13]
Architecture
Discrete
Integration Multi-Standard
Filters
Level
Ability
Superheterodyne RF, IR, IF
Low
Low
Power
High
Zero-IF
RF
High
High
Low
Low-IF
RF
High
Medium
Medium
Wideband-IF
RF
High
High
Medium
To reduce the cost, increase functionality and increase flexibility in
communication systems designers are developing solutions involving multi-standard
transceivers [2]. “In order to realize global roaming, both for voice and data applications,
all of these standards need to be included in a multi-service radio terminal” [25]. One
possible direct-conversion receiver implementation based on the Zero-IF architecture for
16
UMTS/WLAN and the Low-IF architecture for GSM is shown in Figure 10. The
complementary direct conversion transmitter is presented in Figure 11.
Figure 10: Example Zero/Low-IF Multi-Standard Receiver [25]
Figure 11: Example Direct Conversion Multi-Standard Transmitter [25]
3.2. Review of Reconfigurable Amplifier Technology
There are many researchers today that have undertaken the task of developing
reconfigurable amplifiers for many applications. Among these are the most prominent
designs, the power amplifier (PA) and the low-noise amplifier (LNA). While the designs
of the PA and the LNA involve very different techniques there are many commonalities
with the strategies used to make these amplifiers reconfigurable. The focus here is not so
much to detail the design of PAs and LNAs, but rather to examine the adaptability
17
techniques currently in use. Essentially, there are three basic ways to achieve amplifier
multi-band operation and these are outlined in Figure 3.
The most common of these approaches seems to be the Unit-Selection type shown
in Figure 12, which consist of a set of amplifier units each corresponding to a different
frequency band.
Figure 12: Unit-Selection Reconfigurable Amplifier [4]
When a particular amplifier unit is desired, it is selected by a Single-Pole-n-Throw
(SPnT) switch that connects the input and output terminals of that unit [4]. The design of
each unit is similar, thereby making overall design simple and easily achievable.
Consequently, the performance characteristics of the multi-band amplifier are thus
dictated by the performance of the selected unit designed for a specific frequency band.
The downside to this approach is obviously that the die area of the multi-band amplifier
increases proportionally to the required number of frequency bands. Therefore, it may not
be practical for greater than two or three different operating bands. Another issue worth
noting is that achievement of the often required low insertion loss and good isolation
specifications depends heavily on the SPnT switch and may be difficult at microwave
frequencies [4].
18
Another approach to the design of a multi-band amplifier is the use of the
Broadband-Matching type illustrated in Figure 13, where the matching networks are
configured so that the amplifier has a wideband response covering the desired frequencies
of operation.
Figure 13: Broadband-Matching reconfigurable Amplifier [4]
Such a design is usually intended to operate simultaneously over all the frequencies (ƒ1,
ƒ2,…,ƒn). The con to this design strategy is that high efficiency and high output power is
difficult to achieve when upper and lower frequency limits are farther apart [4]. So, it
stands to reason that this approach may not be suited for a multi-band PA, but may work
for a Variable Gain Amplifier (VGA) or an LNA. Also, non-simultaneous frequency
operation would require additional filtering circuits which would impact the amplifier
overall performance.
Probably the most researched approach to multi-band amplifier design is the
Variable-Matching type shown in Figure 14, which has a similar architecture as the
Broadband-Matching type except that the matching networks are variable
Figure 14: Variable-Matching Reconfigurable Amplifier [4]
19
This amplifier can be design to operate at discrete frequency bands like the UnitSelection type. Consequently, all the benefits of the Unit-Selection type such as a highefficiency, high-power amplifier is achievable, even if the number of frequency bands
increase. This approach also can eliminate redundant sections in the circuit and achieve a
smaller design area than the Unit-Selection type [4]. The most significant downside to
this design type is that it requires low-loss variable devices to vary the matching. These
include Varactors and Micro-Electro-Mechanical Systems (MEMS) switches.
Technically, this type of amplifier is classified as Band-Switchable amplifiers.
Figure 15: Band-Switchable Matching Network Operation
Figure 15 from [4] shows the configuration of the band-switchable matching network.
MN-1, the matching network for ƒ1, is designed such that Z(ƒ1) matches Z0, and itself has
a characteristic impedance of Z0. When the switch is open, as shown in Figure 15(a),
Zout(ƒ1) matches Z0 and the amplifier operates at ƒ1. At this point, if ƒ1 is far enough from
ƒ2 then Z(ƒ2) will not match Z0. When the switch is closed, as shown in Figure 15(b),
Zout(ƒ2) matches Z0 and the amplifier operates at ƒ2. At this point, if ƒ1 is far enough from
20
ƒ2 then Z(ƒ1) will not match Z0. Extrapolating this architecture leads to muti-band
operation at conceptually many frequencies, as illustrated in Figure 16.
Figure 16: Muti-Band Band-Switchable Amplifier [4]
It is important to realize that true ON/OFF switch states in a practical design is not ideal
and that the switch isolation and insertion loss will affect amplifier loss based on this
configuration. Therefore, a low ON-state insertion loss switch is desirable.
In [7], Larcher et al. demonstrate a quad-band class-E PA utilizing a MEMS
network to realize a series L-C filter and the output matching network, shown in Figure
17.
Figure 17: MEMS Based Class-E Reconfigurable PA [7]
21
A reconfigurable shunt capacitor is realized using M3 to switch C3 to ground, which
allows the drain capacitances of M2 and M3 to be leveraged to provide a capacitive shorts
Csh,L at 900MHz and Csh,H at 1800MHz. For the MEMS network, L2 is kept constant over
both frequency bands while C2 is reconfigured by SW1, shorting C2” such that
C2,H=C2’+C2” and C2,L=C2’. So at 900MHz SW2 is ON and Cm2=Cm2’+Cm2”.
Lu, Peroulis, et al. showed clearly in [6] the basic implementation of MEMS
matching networks based on double-stub tuners to match a Class-AB amplifier at 6 and 8
GHz.
Figure 18: Lu-Peroulis MEMS Class-AB Amplifier [6]
The input and output matching networks of [6] shown in Figure 18 (a) and (b),
respectively, are implemented with MIM capacitors and MEMS capacitive switches. The
capacitor of the switch is varied between Cup and Cdown by activating the switch, since the
22
switch behaves like a shunt capacitor between the center conductor of the CPW line and
ground [6].
Though most multi-band amplifiers involve the use of MEMS or other types of
switches to achieve a reconfigurable matching network, there have been several
researchers and designers that employed switchable differential inductors to achieve
similar results. In [3] and [5] Yao, et al. demonstrated a low-power MMIC reconfigurable
direct-conversion receiver RF front-end based on such a concept. The basic architecture
shown in Figure 19 is implemented as a common-gate amplifier illustrated in Figure 20.
Figure 19: Yao Reconfigurable LNA Block Diagram [3]
Figure 20: Yao Common-Source LNA [5]
23
In this implementation, the feedback loop realizes a switchable input impedance and
output load resonance at the same time. Stage 1 is reconfigurable while stage 2 is
essentially a wideband gain amplifier.
Figure 21: Yao Switchable Differential Inductor [3][5]
M3/M4 is a cross-coupling pair allowing the switchable inductor (L1) shown in Figure 21
to resonate with the node parasitic capacitances to provide near 50Ω impedance at two
frequencies, depending on the state of the switch.
3.3. Review of RF Switch Technology
RF/Microwave switches are an essential component in modern communication
systems and are used mainly to control signal flow and select signal sources, among other
applications [29]. For the application of interest, these switches are employed to either
allow a signal to propagate in one direction or block the signal from that path. These
switches are usually implemented as reflective (open circuit cascaded with signal path) or
absorptive (isolation created using ZL matched to Z0 of across a transmission line). The
absorptive type is shown in Figure 22.
24
Figure 22: Illustration of Absorptive Switch [29]
Switches are implemented in a variety of configurations described in terms of the number
of poles (signal paths) and the number of throws (possible placements for each pole). In
terms of performance there are two main characterization measures for RF/Microwave
switches:
•
Insertion Loss (IL) – small amount of incident signal absorbed by the switch
•
Isolation (ISOL) – small amount of energy that propagates past the switch in
OFF state
For today’s high frequency applications RF/Microwave switches are implemented using
three main technologies: PIN Diode switches, FET switches and MEMS switches. These
will be examined in subsequent sections.
3.3.1. Diode Switches
PIN diodes are used quite often to design high frequency switches, in either a
series or shunt configuration. Single-pole-single-throw (SPST) implementations are
illustrated in Figure 23.
25
Figure 23: PIN Diode SPST Switches [29]
The series configuration is usually used when minimum IL is required over a broad band,
while the shunt configuration is normally used when high isolation over a broad band is
required. Ideally the insertion loss and the isolation for these two types can be
summarized according to Table 4.
Table 4: PIN Diode Switch Characteristic Equations [29]
Series Switch
Shunt Switch
Insertion Loss IL = 20 ∗ log [1 + ( Rs )]
IL = 10 ∗ log10 [1 + (π * f * C * Z 0 ) 2 ]
10
Isolation
ISOL = 10 ∗ log 10 [1 +
2 Z0
1
( 4*π *C *Z 0 ) 2
]
ISOL = 20 ∗ log 10 [1 + ( 2ZRs0 )]
The SPST switches can be combined to form single-pole-double-throw (SPDT)
implementations shown in Figure 24, which are more useful for multi-device control. For
both the SPST and the SPDT implementations the PIN diode “is in a ‘pass power’
condition when it is forward biased and presents a low forward resistance between the RF
generator and the load. For the ‘stop power’ condition, the diode is at zero or reverse bias
so that it presents high impedance between the source and the load” [29].
26
Figure 24: PIN Diode SPDT Switches [29]
For transmit-receive (T/R) modules a class of the PIN diode switches were developed to
connect the antenna to the transmitter in the transmit mode of a transceiver and to the
receiver in receive mode. There are two basic PIN diode variations for T/R switches: the
narrowband and the broadband. These are illustrated in Figure 25.
Figure 25: PIN Diode T/R Switches [30]
Operationally, one PIN diode is connected in series to the transmitter and a shunt PIN
diode is connected at λ/4 from the antenna-Tx-Rx node. When in Tx mode each diode is
forward biased, enabling the series diode to appear as low-Z to the signal directed to the
antenna while the shunt diode shorts the Rx port. [30]
27
3.3.2. FET Switches
A switching field effect transistor (FET) takes advantage of the channel between
the source and the drain ports that forms a conduction path for the RF signal and the gate
port regulates whether the RF signal passes. This switching FET is configured in
depletion mode where the channel is normally at a low-Z state at zero gate voltage and in
a high-Z, pinched-off state when negative gate voltage is applied. [30] A basic single
FET SPST switch is shown in Figure 26.
Figure 26: Simplified Single-FET SPST Switch [30]
When the FET switch is in its “ON” state the insertion loss is impacted by the channel
resistance (low Rs = low IL) and in the “OFF” state the drain-source capacitance (Cds, aka
Coff) limits isolation. Computation of these properties is illustrated in Table 5.
Table 5: IL and ISOL for Single FET Switch
Series FET Switch
Insertion Loss IL = 20 ∗ log [1 + ( Rs )]
10
Isolation
2 Z0
ISOL = 20 ∗ log 10 [1 + ( 2XcZ 0 )]
Isolation can be improved at higher frequencies by adding a shunt FET following the
series FET. This creates a situation where one FET must be “ON” while the other is
“OFF” and a negative gate voltage is required. “A solution to this problem is the addition
28
of two capacitors applied to the shunt FET which provide DC blocks to the RF path and
allow the gate port of the shunt FET to be grounded” [30].
Figure 27: Single Positive Control Voltage FET SPST Switch [30]
Adding a reference voltage port solves the negative supply problem, as illustrated in
Figure 27. Now only a single positive voltage needs to be applied to the switch.
Figure 28: T/R SPDT FET Switch [30]
Figure 28 shows a typical configuration adopted for use as a T/R switch as an alternative
to the PIN diode based T/R switch. These two technologies have relative advantages and
disadvantages to each other for switching applications [30].
29
Table 6 summarizes this nicely.
Table 6: Comparison of PIN Diode vs. FETs for Switching Applications [30]
Attribute
PIN Diode
FET
Poor
Excellent
“Integratability” with
other components
Very high (to greater than 1 Moderate (10 W CW or
Power handling
kW CW)
less)
A few tens of nanoseconds
Tens to a few hundred of
Switching time
to several microseconds
nanoseconds
Up to 100 milliamps
Less than 100 micro-amps
Control current
Input third order
Distortion performance Input third order intercepts
in the +45 dBm or higher
intercepts in the +30 to
range
low +40’s dBm range
3.3.3. RF MEMS Switches
With the maturation of RF MEMS technology, MEMS switches present a new
choice for some applications. However at this point there are significant disadvantages to
this technology that prohibits routine use in modern communication systems applications.
Several advantages and disadvantages are presented by Rebeiz in [32]. A summary is
provided in Table 7 below.
Table 7: Advantages and Disadvantages of RF MEMS Switches
Advantages
Disadvantages
Near-Zero Power Consumption
Relatively Slow Switching Speeds
Very High Isolation
High Voltage/Current Drive
Very Low Insertion Loss
Poor Power Handling
High Linearity
Low Reliability
Low Intermodulation Products
High Packaging (Hermetic) Cost
Potential for Low Cost
High Manufacturing Costs
30
CHAPTER 4 RESEARCH METHODOLOGY
The primary goal of this research is to design, fabricate and evaluate a bandswitchable power amplifier as well as a low noise amplifier that can be used in the design
of flexible or adaptable communication systems, particularly in microwave receivers and
transmitters. Based on the extensive literature search performed it is believed that using
an ultra-low-loss FET switch, modified from T/R module applications, at the center of
the multi-band amplifier designs will help to mitigate the disadvantages relative to other
design approaches. With the development cost and time being critical factors, the
switchable multi-band approach is the most feasible. Both the power amplifier and the
low-noise amplifier will utilize this general approach. However, the power amplifier will
be implemented as a MMIC circuit while the low noise amplifier will be implemented as
a MIC.
4.1. Dual-Band Reconfigurable Power Amplifier (RPA)
The RPA will be designed using two independent power amplifiers (PA)
operating at 5.5GHz and 8.5GHz controlled by a FET RF switch.
4.1.1. PA Design Specifications
The goal of the RPA is to demonstrate the switching capability of the design.
Therefore, high performance for the two power amplifiers is not critical, but their
operation should be adequately demonstrated at their respective band of operation.
Table 8: C/X-Band RPA Specifications
Parameters
Frequency
Bandwidth
Gain
Specification
5.5/8.5 GHz
>500 MHz
>13 dB
31
Gain Ripple
Output Power
Efficiency
VSWR
Supply Voltage
Size
+/- 0.25 dB
>+20 dBm @ 1dB Compression
>20% @1dB Compression
<1.5:1 (input, output)
+/- 5 volts
</= 60 x 60 mil
Table 8 outlines the basic set of target specifications for the two RPA amplifiers.
4.1.2. PA Design Approach
A single-stage C/X-Band MMIC Class-AB reconfigurable power amplifier (RPA)
is designed and implemented with the Triquint Oregon TQTRx 0.5-um MESFET process.
A class AB design was adopted because it was a good choice to meet all the design goals
listed in Table 8. For each of the power amplifiers in the RPA, the 6x50-um FET was
chose for the single-stage design architecture illustrated in Figure 29.
Figure 29: Single-Stage PA Architecture
Incidentally, Figure 29 shows the sub-circuit components of the amplifier, which when
designed individually, eases the challenge of laying out the amplifier in a MMIC
implementation. This approach also simplifies the design optimization process
tremendously. In Figure 29, FET1 represents the 300-um FET. The biasing networks
utilize individual bias supply for the gate and drain of the FET.
32
4.1.2.1.
Biasing Network and Stability
The bias point for the FET was chosen to balance gain, power and efficiency.
Another subtle goal was to allow for bias tuning. So, drain voltages between 3-volts and
4-volts should require only slight tweaking to determine best performance. The biasing
network is combined with elements used to stabilize the FET as shown in Figure 30.
BIASTEE
ID=X1
PORT
P=1
Z=50 Ohm
2
RF 1
&
DC
RF
1
DC
3
RES
ID=R1
R=100 Ohm
2 TQPED_PHSS
ID=T1
W=50
NG=6
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
BIASTEE
ID=X2
1 RF
&
DC
RF
2
PORT
P=2
Z=50 Ohm
DC
3
3
DCVS
ID=V1
V=-0.05 V
DCVS
ID=V2
V=3 V
TQPED_SVIA
ID=V3
W=90 um
L=90 um
TQPED_SVIA
ID=V4
W=90 um
L=90 um
Figure 30: Biased and Stabilized FET
Each Bias-Tee contains a series-shunt capacitor-inductor pair, where the blocking
capacitor connects the RF source while the choke inductor connects the DC supply. The
capacitor protects the RF source by blocking DC voltage while the inductor provides the
necessary RF short. The shunt resistor on the gate helps to stabilize the device, with
negligible sacrifice in Available Gain (GAV) of the FET.
33
DSFET Stability
4
B1()
K()
FET Stabilization
FET Stabilization
3
2
1
0
1
6
11
16
Frequency (GHz)
21
25
Figure 31: Simulated Stability Test Result
Figure 31 shows the simulated results of the stability test for the network of Figure 30.
The DC I-V curves and load-line plot is shown in Figure 32.
p1: Vstep = -1 V
DpHEMT DCIV
300
p2: Vstep = -0.8 V
IVCurve() (mA)
DpHEMT DCIV
p3: Vstep = -0.6 V
IVDLL(TQPED_PHSS.T1@2,TQPED_PHSS.T1@2)[*,*] (mA)
DpHEMT Load_Line
p4: Vstep = -0.4 V
200
p11
p10
p5: Vstep = -0.2 V
p9
p6: Vstep = 0 V
p8
p7
100
p7: Vstep = 0.2 V
p6
0
p5
p8: Vstep = 0.4 V
p4
p13p12
p3
p2
p1
p9: Vstep = 0.6 V
p10: Vstep = 0.8 V
p11: Vstep = 1 V
-100
0
2
4
Voltage (V)
6
p12: Freq = 1 GHz
Pwr = 0 dBm
p13: Freq = 2 GHz
Pwr = 0 dBm
Figure 32: I-V Curve and DC Load-Line of Stable FET
To verify that the device is capable of meeting the Gain specification for the design the
Maximum Available Gain (MAG) and the Maximum Stable Gain (MSG) are measured.
34
Gain Test
30
5.5 GHz
19.84 dB
5.5 GHz
17.75 dB
25
8.5 GHz
18.02 dB
20
8.5 GHz
14.45 dB
DB(GMax())
FET Stabilization
DB(MSG())
FET Stabilization
DB(|S(2,1)|)
FET Stabilization
15
10
5.5 GHz
12.07 dB
5
8.5 GHz
9.29 dB
0
1
6
11
16
Frequency (GHz)
21
25
Figure 33: Gain, Stable gain and Max Gain of Stabilized FET
Figure 33 shows the simulated Gain checks for the stabilized device. This determines that
the device is suitable for the design.
4.1.2.2.
Output Matching Network (OMN)
The OMN was the first of the matching networks to be designed. The procedure is
based on the Cripps technique described in [33]. To accurately match the output
impedance for maximum linearity and power a resistor-capacitor pair (RCRIPPS-CDS) is
determined. RCRIPPS was determined from the DC load line plotted with the IV-Curves of
the device shown in Figure 32. An RC network was then tuned to model S22 from which
CDS could be determined. The network for the 5.5-GHz PA is illustrated in Figure 34 and
a plot of the output match (1.83-j1.69) at 5.5 GHz is shown in Figure 35.
35
PORT
P=1
Z=50 Ohm
PORT
P=2
Z=50 Ohm
CAP
ID=C1
C=0.1575 pF
RES
ID=R1
R=170 Ohm
CAP
ID=C2
C=0.1575 pF
RES
ID=R2
R=R_opt Ohm
Figure 34: Cripps RC Network for 5.5GHz PA
0.8
1.0
Cripps Output Match1
S(2,2)
Swp Max
25GHz
S(2,2)
2.
0
0.
6
Cripps RC Network_Match1
FET Stabilization
S(1,1)
Cripps RC Network_Match1
0.
4
0
3.
4.
0
5.0
0.2
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0
0.2
10.0
5.5 GHz
r 1.83176
x -1.69489
-10.0
2
-0.
-4
.0
-5.
0
5.5 GHz
r 1.82957
x -1.69501
-3
.0
-1.0
-0.8
-0
.6
.0
-2
.4
-0
Swp Min
1GHz
Figure 35: Output Match for 5.5GHz Cripps RC Network
Similarly for the 8.5-GHz PA the Cripps RC network and its corresponding output match
(1.51-j1.42) are shown in Figure 36 and Figure 37, respectively.
PORT
P=1
Z=50 Ohm
PORT
P=2
Z=50 Ohm
RES
ID=R1
R=142.7 Ohm
CAP
ID=C1
C=0.1235 pF
CAP
ID=C2
C=0.1235 pF
RES
ID=R2
R=R_opt Ohm
Figure 36: Cripps RC Network for 8.5GHz PA
36
0.8
1.0
Cripps Output Match2
S(2,2)
Cripps RC Network_Match2
Swp Max
25GHz
2.
0
6
0.
S(2,2)
FET Stabilization
S(1,1)
Cripps RC Network_Match2
0.
4
0
3.
0
4.
5.0
10.0
5.0
4.0
10.0
3.0
2.0
1.0
0.8
0.6
0.4
0
0.2
0.2
8.5 GHz
r 1.51125
x -1.42698
-10.
0
2
-0.
8.5 GHz
r 1.51334
x -1.42439
-4
.0
-5.
0
-3
.0
.0
-2
-1.0
-0.8
-0
.6
.4
-0
Swp Min
1GHz
Figure 37: Output Match for 8.5GHz Cripps RC Network
For both the 5.5GHz and 8.5GHz PA, the reflection coefficient at port 1 of the RC
networks on the left of Figure 34 and Figure 36 determines the optimum power match
point for their respective center frequencies.
Figure 38: RPA OMNs for 5.5GHz PA (a) and 8.5GHz PA (b)
4.1.2.3.
Input Matching Network (IMN)
Ideally, the IMN was designed for a relatively narrow band (i.e. shortest path
from generator to load). However multiple paths exist, but the path that included a shunt
inductor was desired and used since this inductor can be used as the DC feed for the FET
gate bias since it is large enough to also provide a convenient RF short.
37
Figure 39: 5.5GHz PA Output Match in Circuit
Figure 40 illustrates the desired input matching point at 5.5 GHz when the corresponding
output matching network is loaded to the stabilized FET as shown in Figure 39.
Swp Max
25GHz
2.
0
6
0.
0.8
1.0
Input_to_Match_5p5GHz
0.
4
3.
0
0
4.
S(1,1)
5p5_GHz_OutMatch
5.0
0.2
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
0
2
-10.0
-0.
5.5 GHz
r 0.200742
x -0.418668
-5.
0.2
10.0
0
-4
.0
0
-2
-1.0
-0.8
-0
.6
.0
-3
.
.4
-0
Swp Min
1GHz
Figure 40: Optimum Reflection for 5.5 GHz IMN
By applying a conjugate matching technique the resulting IMN of Figure 41 can be
derived.
IND
ID=L2
L=0.0301 nH
IND
ID=L3
L=0.7212 nH
Figure 41: IMN for 5.5GHz PA
38
Upon connection of the IMN to the stabilized FET and corresponding OMN, the
completed 5.5 GHz PA is achieved. The final lumped element implementation of the
5.5GHz PA is shown in Figure 42.
PORT_PS1
P=1
Z=50 Ohm
PStart=-20 dBm
PStop=15 dBm
PStep=1 dB
BIASTEE
ID=X1
IND
ID=L4
L=0.0301 nH
2
RF
&
DC
RF
1
DC
IND
ID=L5
L=0.7212 nH
3
1
2 TQPED_PHSS
ID=T1
W=50
NG=6
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
CAP
ID=C1
C=0.374 pF
BIASTEE
ID=X2
1 RF
&
DC
RF
PORT
P=2
Z=50 Ohm
2
DC
3
IND
ID=L1
L=2 nH
3
RES
ID=R1
R=100 Ohm
DCVS
ID=V1
V=-0.05 V
DCVS
ID=V2
V=3 V
TQPED_SVIA
ID=V3
W=90 um
L=90 um
TQPED_SVIA
ID=V4
W=90 um
L=90 um
Figure 42: 5.5GHz PA Design
The lumped element implementation of the 5.5GHz PA is then simulated to evaluate
Gain, reflection and Power performance. The results are shown in for Figure 43.
Figure 43: S-Parameter and Power Simulation for 5.5GHz PA
Similar to the procedure used in development of the 5.5GHz PA, the optimum IMN for
the 8.5GHz was determined by measuring the reflection at the input of the circuit shown
in Figure 44.
39
BIASTEE
ID=X1
PORT
P=1
Z=50 Ohm
RF
&
DC
2
RF
1
2 TQPED_PHSS
ID=T1
W=50
NG=6
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
1
DC
3
CAP
ID=C1
C=0.274 pF
BIASTEE
ID=X2
1 RF
PORT
P=2
Z=50 Ohm
2
&
DC
RF
DC
3
IND
ID=L1
L=1.2 nH
3
RES
ID=R1
R=100 Ohm
DCVS
ID=V1
V=-0.05 V
DCVS
ID=V2
V=3 V
TQPED_SVIA
ID=V3
W=90 um
L=90 um
TQPED_SVIA
ID=V4
W=90 um
L=90 um
Figure 44: 8.5GHz PA Output Match in Circuit
A plot of S11 for the 8.5GHz FET/OMN circuit is shown in Figure 45. This represents the
matching point to determine the IMN.
Input_to_Match_8p5GHz
2.
0
6
0.
0.8
1.0
Swp Max
25GHz
0.
S(1,1)
8p5_GHz_OutMatch
0
3.
0
4.
4
5.0
0.2
-0.
10.0
5.0
4.0
3.0
2.0
1.0
0.8
0.6
0.4
8.5 GHz
r 0.173196
x -0.27868
2
-10.0
0
0.2
10.0
-4
.0
-5.
0
-3
.0
.0
-2
4
-1.0
-0.8
-0
.6
.
-0
Swp Min
1GHz
Figure 45: Optimum Reflection for 8.5 GHz IMN
The resulting IMN for the 8.5GHz PA is shown in Figure 46 and the complete PA is
shown in Figure 47.
40
IND
ID=L2
L=0.732 nH
IND
ID=L3
L=0.718 nH
Figure 46: IMN for 8.5GHz PA
PORT_PS1
P=1
Z=50 Ohm
PStart=-20 dBm
PStop=15 dBm
PStep=1 dB
IND
ID=L4
L=0.732 nH
CAP
ID=C2
C=1.7 pF
BIASTEE
ID=X1
2
RF
&
DC
RF
1
DC
IND
ID=L5
L=0.718 nH
3
1
2 TQPED_PHSS
ID=T1
W=50
NG=6
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
CAP
ID=C1
C=0.274 pF
BIASTEE
ID=X2
1
RF
&
DC
RF
PORT
P=2
Z=50 Ohm
2
DC
3
IND
ID=L1
L=1.2 nH
3
RES
ID=R1
R=100 Ohm
DCVS
ID=V1
V=-0.05 V
DCVS
ID=V2
V=3 V
TQPED_SVIA
ID=V3
W=90 um
L=90 um
TQPED_SVIA
ID=V4
W=90 um
L=90 um
Figure 47: 8.5GHz PA Design
Again the completed amplifier is simulated to characterize the performance of the
8.5GHz PA. The simulated S-Parameter and Power measurement results are shown in
Figure 48.
Figure 48: S-Parameter and Power Simulation for 8.5GHz PA
41
Each sub-circuit was converted to an equivalent circuit using the TQTRx elements from
the design kit and connected using microstrip lines, tees and crosses. Microstrip bends
were modeled using a quasi-electromagnetic microstrip trace element capable of arbitrary
routing. This eliminated the need for including bends in the circuit. Each converted
TQTRx sub-circuit is then compared to the corresponding lumped element sub-circuit
used in the initial design, to ensure original performance is preserved.
4.2. FET RF Switch
RF switches are often employed to perform various important switching tasks in
RF communications systems, particularly in RF transceivers. For this application, they
are used to switch between the transmitter and receiver sections of the circuit. One
benefit of current mobile communication systems is the evolution of RF switch design
from PIN diode based implementations to ones using FETs and CMOS; the advantage
being low power consumption, lower supply voltage and better design integration with
transmitter and receiver circuits. The concept and design approach for this
transmit/receive (T/R) module switch is adopted for the RPA design and is used to select
either the 5.5GHz or the 8.5GHz PA on demand.
4.2.1. RF Switch Design Approach
The implementation of the RF switch will utilize Gallium Arsenide (GaAs) FETs
available in the TQTRx foundry process. Figure 49 shows the topology of the RF switch
used for this design.
42
Figure 49: GaAs FET RF Switch
Note that the terminals of the switch have labels indicating how the T/R switch is adopted
for the dual power amplifier application. Table 9 shows the state of each FET when the
switch is operating in one of two possible modes.
Table 9: FET RF Switch State Table
VG1
VG2
F1
F2
0
(-)
Short
Open
Tx (PA1)
(-)
0
Open
Short
Rx (PA2
F3
Short
Open
F4
Open
Short
When in Tx mode, RF signal flows from the ANT/RFIN port to the Tx/PA1 port and when
in Rx mode RF signal flows from the ANT/RFIN port to the Rx/PA2 port. The Tx/PA1
and Rx/PA2 ports are isolated in both modes of operation.
43
4.2.2. FET RF Switch Design Notes
The design of the FET RF switch assumes that the FET is capable of achieving a
perfect off state. In reality, however, GaAs FETs cannot achieve that state, but can be
modeled using a finite on-resistance (RON) when conducting and a finite off-capacitance
(COFF) when in cut-off mode. Hence, as the widths of F1 and F2 of Figure 49 increases,
RON decreases and COFF increases. As RON decreases, the insertion loss in the switch also
decreases while increasing COFF lowers the isolation between the Tx/PA1 and Rx/PA2
ports. So, as a consequence of such a trade-off between insertion loss and isolation, the
choice of transistor size for F1 and F2 is important. It is crucial to be mindful that for this
FET switch design the power handling capability is relatively low. For switch FET pinchoff voltage (VPO), off-state FET control voltage (VC) and system characteristic impedance
(Z0) the maximum transmit power (PMAX) delivered to the switch should not exceed the
value defined in equation 1.
PMAX = 2 ⋅ (VC - VPO ) 2 / Z 0
(1)
4.3. Dual-Band Reconfigurable Low-Noise Amplifier (RLNA)
The dual-band RLNA will be designed to operate at two discrete bands, with two
independent Low-Noise Amplifiers (LNAs) offering high performance suitable for
operation in a state-of-the-art receiver. The main function of the LNAs, and consequently
the RLNA, is to amplify extremely low signals coming from the antenna while adding
only minimal noise, thus preserving the required Signal-to-Noise Ratio (SNR) of the
system at extremely low power levels. Additionally, low distortion and unconditional
stability will be key requirements for each LNA so as to minimize possible channel
interference and eliminate oscillations within the design bandwidths. Each LNA will
44
operate in Class AB mode (~15-20% of IMAX) to achieve good dynamic range (Max PREC
– Min PREC). Because of the nature of the LNA design process it will be necessary to
make trade-offs among key performance metrics such as Gain, Noise Figure (NF),
Stability, and Linearity Error! Reference source not found..
Figure 50: Distortion Slopes (2nd/3rd - Order)
Achieving good linearity will require good Third-Order Intercept (IP3) for a good 1-dB
compression (P1dB) output match, as illustrated in Figure 50 and Figure 51, respectively.
Figure 51: 1-dB Compression Point
45
Perhaps the most fundamental step to achieving good LNA performance is the proper
choice of transistor. A FET will be chosen that exhibit high Gain, low NF, and high IP3
performance at the lowest possible current consumption.
4.3.1. LNA Design Specifications
The design specifications are shown in Table 10below.
Table 10: LNA Design Specifications
Parameters
Center Frequencies (fc)
3dB Bandwidth
Stop Band Rejection
Gain
Noise Figure
Flatness
Input/output VSWR
Input/output Impedance
Reverse Isolation
Specification
2.05/2.25-GHz
+/- 50MHz @ each fc
25dB +/- 200MHz
20 dB
1.5 dB
+/- .5 dB
1.5/1.7
50 Ohms
> 30dB
There may be other specifications to consider, though not critical, which may be
important to consider to achieve overall good performance.
4.3.2. LNA Design Approach
Each LNA within the RLNA will be designed using the topology of Figure 52,
which should be adequate to achieve the specifications of Table 10. If necessary, a Balun
can be used to combine two LNA sections to form a balanced design capable of
producing higher Gain.
46
Figure 52: Single-Stage LNA Topology
Once biased and stabilized, a noise match will be computed for the input of the transistor
while an output match is computed for good trade-off between Gain and Compression.
4.3.2.1.
DC Biasing
There are basically three ways of biasing the FET to operate at the desired
quiescent point (Q-point).
•
Separate Gate and Drain Bias – perhaps the most obvious with the gate supply
being adjustable and source directly grounded
•
Active Bias – an active analog circuit designed to provide the right gate voltage,
but offers no manual adjustment of the Q-point.
•
Self-Bias – a resistor of a strategic value is placed between the source and the
ground so the gate voltage is either held at a fixed voltage or grounded.
For this LNA design, separate gate and drain biasing networks were chosen because it
allows for tuning the transistors’ operating points independently, thus enabling
maximizing performance once the amplifier is powered up. For future designs, a selfbiasing architecture can be utilized for circuit size reduction and simplicity once the
optimum bias configuration can be determined. Figure 53 illustrates the topology of the
self-biasing network.
47
Figure 53: FET Self-Biasing Network
More specifically, the gate bias is a raised gate bias where the gate bias is raised above
ground. When drain current flows through the FET and then through the source resistor,
the source voltage rises above ground. This results in a fixed negative gate-source
voltage. For this biasing network design, resistor RS will need to be bypassed with a
capacitor so that the FET source connection sees a 0-Ω connection to ground at the
operating frequency.
4.3.2.2.
Stabilizing the FET
The goal of the stability network of the LNA circuit is to achieve unconditional
stability over the range of frequencies where the device has high Gain. This is done in a
way such that with any load presented to the output of the device the circuit will not
become unstable nor will it oscillate. There are several ways to potentially stabilize the
device:
•
Input Resistive Loading – improves the stability of the circuit, but degrades the
noise of the LNA.
48
•
Output Resistive Loading – improves the stability, but may lower Gain and P1dB
/IP3 points.
•
Drain-Gate Resistor-Inductor-Capacitor (RLC) Feedback – improves the stability
by lowering the Gain at the lower frequencies of the circuit.
•
Output Filter Matching – improves stability by decreasing the Gain at specific
narrow bandwidth frequencies, usually high above the band of operation.
•
Source Feedback Inductor – improves stability using a small inductor to make the
circuit more stable at higher frequencies.
For this design, the Output Resistive Loading technique was employed because it limits
the impact on the noise figure because of its drain-side location and it limits the impact
on the gain.
SUBCKT
RES
ID=S2
ID=R1
NET="NE3509M04_v124"
R=70 Ohm
UgwNew=0.4
NfgNew=1
BIASTEE
ID=X1
PORT
P=1
Z=50 Ohm
2
RF
&
DC
RF
0 mA
DC
2
9.41 mA
BIASTEE
ID=X2
1 RF
&
DCmA
9.41
RF
2
0 mA
DC
PORT
P=2
Z=50 Ohm
3
1
1
9.41 mA
0 mA
DCVS
ID=V2
V=2.5 V
3
3
0 mA
DCVS
ID=V1
V=-0.236 V
Figure 54: Output resistive Loading Topology
Upon stabilization using the technique described and illustrated in Figure 54, the stability
will be evaluated by measuring the Stability Factor (K-Factor) from low frequency,
49
through the operating frequency range, to high frequency. The K-Factor is defined in
equation 2.
2
k=
2
1 + ∆ − S11 − S 22
4.3.2.3.
2 ⋅ S 21 ⋅ S12
2
, where ∆ = S11 ⋅ S 22 - S 21⋅ S12
(2)
LNA Noise/Input Matching
Typically, the LNA’s input matching network is designed to terminate the input
of the transistor with the conjugate of the optimum noise reflection (ΓOPT), which
represents the terminating impedance of the transistor for the best noise match. In many
cases, however, this means that the input return loss (RLIN) of the LNA will be sacrificed.
The optimal RLIN can only be achieved when the input matching network (IMN)
terminates the device with a conjugate of S11 ( S11* ), which in many cases is different from
*
the conjugate of ΓOPT ( ΓOPT
). Obviously, there needs to be a trade-off approach to
determine the appropriate source reflection (ΓS) for the LNA such that good Gain, Noise
Figure (NF) and RLIN are achieved. The procedure for such an approach follows:
•
Calculate the unilateral figure of merit to choose a unilateral or bilateral design
scheme.
•
Calculate or determine the minimum noise figure (NFMIN) and ΓOPT of the
transistor and choose the desired NF above NFMIN.
•
Calculate the center and radius of the noise circle. Plot the noise circle on the
Smith Chart for the ΓIN -plane.
•
For a unilateral design, use the constant Gain circles for the specified Gain. For
the bilateral design case, use the Available Power gain circle for the specified
50
Gain. In either case, plot the Gain circles in the same ΓIN -plane as the noise
circles.
•
Choose a ΓS value in the stable region that is encircled by both the Noise and Gain
circles, which satisfy the specifications.
•
Compute the corresponding source impedance (ZS) from ΓS.
Once ZS is determined the IMN can be designed using the Smith Chart by transforming
Z0 to ZS. The IMN will be implemented using microstrip lines.
Figure 55: LNA Input Noise Match
The computed noise match for the LNAs is shown in Figure 55 above. Using the
conjugate of ZOPT from ΓOPT the input matching network is developed using ideal
transmission lines. Ideal transmission lines in all cases were converted to real
transmission lines for the Rogers 3010 substrate chosen using the TXLine utility in
Microwave Office. A typical calculation is shown in Figure 56.
51
Figure 56: TXLINE Microstrip Line Calculator
The L-Band input matching network was computed and implemented as shown in Figure
57.
MSUB
Er=10.2
H=0.25 mm
T=0.017 mm
Rho=1
Tand=0
ErNom=10.2
Name=SUB1
SUBCKT
RES
ID=S2
NET="NE3509M04_v124" ID=R1
R=70 Ohm
UgwNew=0.4
NfgNew=1
PORT
P=1
Z=50 Ohm
2
RF
&
DC
RF
1
MLIN
ID=TL1
W=0.22 mm
L=6.98 mm
BIASTEE
ID=X1
1
BIASTEE
ID=X2
2
RF
&
DC
RF
2
DC
PORT
P=2
Z=50 Ohm
3
1
DC
3
MLSC
ID=TL2
W=0.22 mm
L=9.04 mm
3
DCVS
ID=V2
V=2.5 V
DCVS
ID=V1
V=-0.236 V
Figure 57: L-Band Input Matching Network
Since the S-Band frequency is so close to the L-Band design the L-Band IMN of Figure
57 was tuned slightly for performance at S-Band.
52
4.3.2.4.
LNA Output Matching
Since the optimal Gain (GOPT) impedance does not match the optimal IP3 point,
the design of the LNA circuit is typically matched at the point where the Gain does not
degrade as much, and the IP3 is still respectable. Basically any point on a straight line
between GOPT and IP3 impedance points will represent a good area of trade-off, with the
ends representing the two respective optimal points. P1dB can be estimated from IP3 using
equation 3.
IP3 = P1dB + 10 [dBm]
(3)
With this in mind the output matching network (OMN can be designed as follows:
•
Calculate the corresponding load reflection (ΓL) based on ΓS and P1dB/ IP3
specifications.
•
Compute the corresponding load impedance (ZL) from ΓL.
Once ZL is determined the OMN can be designed using the Smith Chart by transforming
ZL to Z0. Similar to the IMN, the OMN was implemented using micro-strip lines. Figure
58 and Figure 59 show the completed amplifier with OMN for the L-Band and S-Band
LNA, respectively.
53
MSUB
Er=10.2
H=0.25 mm
T=0.017 mm
Rho=1
Tand=0
ErNom=10.2
Name=SUB1
SUBCKT
RES
ID=S2
NET="NE3509M04_v124" ID=R1
R=70 Ohm
UgwNew=0.4
NfgNew=1
MLIN
ID=TL1
W=0.22 mm
L=3.08 mm
BIASTEE
ID=X1
PORT
P=1
Z=50 Ohm
2
RF
&
DC
RF
MLIN
ID=TL3
W=0.22 mm
L=6.51 mm
BIASTEE
ID=X2
1 RF
&
DC
2
PORT
P=2
Z=50 Ohm
2
RF
DC
3
1
MLSC
ID=TL4
W=0.22 mm
L=5.09 mm
1
DC
DCVS
ID=V2
V=2.5 V
3
MLSC
ID=TL2
W=0.22 mm
L=4.04 mm
3
DCVS
ID=V1
V=-0.236 V
Figure 58: L-Band LNA with Computed IMN and OMN
MSUB
Er=10.2
H=0.25 mm
T=0.017 mm
Rho=1
Tand=0
ErNom=10.2
Name=SUB1
SUBCKT
RES
ID=S2
NET="NE3509M04_v124" ID=R1
R=70 Ohm
UgwNew=0.4
NfgNew=1
PORT
P=1
Z=50 Ohm
RF
&
DC
2
RF
1
BIASTEE
ID=X2
1
MLIN
ID=TL1
W=0.22 mm
L=1.88 mm
BIASTEE
ID=X1
MLIN
ID=TL3
W=0.22 mm
L=6.27 mm
2
RF
&
DC
2
DC
3
MLSC
ID=TL4
W=0.22 mm
L=4.7 mm
1
DC
DCVS
ID=V2
V=2.5 V
3
MLSC
ID=TL2
W=0.22 mm
L=3.83 mm
RF
3
DCVS
ID=V1
V=-0.236 V
Figure 59: S-Band LNA with Computed IMN and OMN
54
PORT
P=2
Z=50 Ohm
CHAPTER 5 DESIGN EVALUATION AND MEASURMENTS
5.1. Small-Signal RF Measurements
In order to measure small-signal s-parameters, Coplanar Waveguide (CPW) RF
probes are required for the input and output RF ports of each amplifier circuit, the device
under test (DUT) shown in Figure 60.
Figure 60: VNA Setup for Small Signal RF Measurements
Therefore, each amplifier includes ground-signal-ground (GSG) pads for each RF port as
well as single pads for the supply of direct current (DC) biasing. Each amplifier will be
biased as designed and s-parameters will be measured, under bias, over the design
frequency range. These s-parameters will then be compared to the corresponding
simulated s-parameters to evaluate performance success.
55
5.2. RF Noise Figure Measurements
For each Low-Noise Amplifier (LNA) the small-signal RF noise characteristics
will be evaluated by measuring the noise figure over the design bandwidth.
Figure 61: NF Measurement Setup
The setup in Figure 61 will be used for this measurement. Once the NF Receiver is
calibrated, the NF and Gain measured by the NF Receiver is recorded for each amplifier
(the DUT) as the frequency is varied (incremented) over the design bandwidth.
5.3. RF Power Measurements
For each power amplifier (PA) a basic power measurement, Output Power (Pout)
vs. Input Power (Pin), will be performed by using the test bench shown in Figure 62. Note
that the PA is the DUT. Once the test bench is calibrated Pout is measured as Pin is varied,
at the fixed center frequency of the design. The power added efficiency (PAE) of each PA
can then be computed from Pin, Pout, and DC power (Pdc).
56
Figure 62: RF Power Measurement Test Bench
57
CHAPTER 6 SCOPE AND LIMITATIONS OF STUDY
The pursuit of an ideal or all-encompassing reconfigurable amplifier suitable for a
vast range of applications is not practical and it is not the goal or intention of this study.
Subsequently, the scope of the study will be narrowed to a few considerations pertinent to
some areas of research relevant to on-going projects. However, the technology involved
in the implementation of the designs of this study can readily be leveraged to scenarios or
applications not addressed in this study.
6.1. Scope of Project
This study will address two design concepts for reconfigurable amplifiers. First, a
C/X-band Reconfigurable Power Amplifier (RPA) will be designed using a switching
architecture capable of selectively operating at two independent center frequencies, as
shown in Figure 63.
Figure 63: RPA Block Diagram
This RPA will be implemented as a Monolithic Microwave Integrated Circuit (MMIC) in
the Triquint Semiconductor 0.5-um foundry process. The RPA will be fabricated and
characterized to evaluate overall small-signal and power performance. Next an L/S-band
Reconfigurable Low Noise Amplifier (RLNA) will be designed using a switching
architecture similar to that of the RPA, as shown in Figure 64.
58
Figure 64: RLNA Block Diagram
The RLNA, however, was implemented as a printed circuit board (PCB)
microstrip design. The RLNA will be fabricated and measured to evaluate noise and RF
performance. A brief description and results of preliminary work for an alternate RLNA
design will be discussed that utilize matching networks of cross-coupled dual-band filters
implemented using split ring resonators. This will demonstrate a future path to innovative
architectures that promises to potentially improve this current body of work.
6.2. Limitations of Study
Due to the available resources and time constraint of this work there will be
several limitations to the research effort. Some of these limitations, their causes and
respective mitigating actions to address them are outlined in Table 11.
Table 11: Project Limitations
Limitations
Causes
Mitigations
Cannot fabricate alternative
Power Amplifier MMICs to
improve the design.
Limited number of MMIC
Foundry runs available.
Experiment with similar switched
LNA technology using MICs.
Cannot currently fabricate more
MICs for improving current
design
Substrate material too thin for inhouse milling.
Explain any discrepancies
between design and fabrication
59
CHAPTER 7 MMIC C/X-BAND RECONFIGURABLE AMPLIFIER
The first phase of the concept under investigation involved the design of a
reconfigurable power amplifier. This amplifier was designed to operate over two different
bands (C- and X-band) which are sufficiently far apart in frequency and selectable via a
Field Effect Transistor (FET) microwave switch. The design was then implemented in a
Monolithic Microwave Integrated Circuit (MMIC) Foundry process provided by Triquint
Semiconductor.
7.1. C/X-Band Reconfigurable Power Amplifier (RPA)
The RPA was designed and implemented in the Triquint Semiconductor (Oregon,
USA) 0.5-um MESFET process. Essentially the RPA is comprised of two MMIC power
amplifiers with respective center frequencies at 5.5GHz and 8.5GHz, controlled by the
MMIC FET Switch.
SUBCKT
ID=S2
NET="5p5_GHz_TQNT_Amp"
1
2
1
PORT
P=1
Z=50 Ohm
PORT
P=2
Z=50 Ohm
SUBCKT
ID=S1
NET="FET Switch MMIC"
3
2
1
2
PORT
P=3
Z=50 Ohm
SUBCKT
ID=S3
NET="8p5_GHz_TQNT_Amp"
Figure 65: C/X-Band RPA Block Diagram
Figure 65 shows the basic block configuration of the RPA. It is important to note that for
this design the RPA does not operate in both bands simultaneously (i.e. no dual-band
60
operation). In order for this RPA to have connectivity to characterization instrumentation
pads were added to the RPA block as shown in Figure 66.
TQPED_SVIA
ID=V4
W=90 um
L=90 um
1
SUBCKT
ID=S2
NET="5p5_GHz_TQNT_Amp"
1
2
TQPED_SVIA
ID=V1
W=90 um
L=90 um
TQPED_PAD
MTRACE2 ID=P6
ID=X2
W=10 um
TQPED_PAD
L=75 um
ID=P4
BType=2
M=1
1
TQPED_PAD
ID=P5
1
1
TQPED_PAD
ID=P2
TQPED_SVIA
ID=V3
W=90 um
L=90 um
1
1
MTRACE2
ID=X1
TQPED_PAD
W=10 um
ID=P1
L=30 um
BType=2
TQPED_PAD M=1
ID=P3
SUBCKT
ID=S1
NET="FET Switch MMIC"
3
2
1
TQPED_PAD
MTRACE2 ID=P9
ID=X3
W=10 um
TQPED_PAD
L=51.9 um
ID=P7
BType=2
M=1
1
TQPED_SVIA
ID=V2
W=90 um
L=90 um
TQPED_SVIA
ID=V6
W=90 um
L=90 um
1
2
1
SUBCKT
ID=S3
NET="8p5_GHz_TQNT_Amp"
TQPED_PAD
ID=P8
1
TQPED_SVIA
ID=V5
W=90 um
L=90 um
Figure 66: C/X-Band RPA Block Diagram with Pads
The layout of the final RPA was adjusted while maintaining performance that meets the
design specifications and the final fabricated layout was ultimately achieved as shown in
Figure 67.
61
Figure 67: Final C/X-Band MMIC RPA Layout
The simulated small-signal performance of the RPA was achieved by essentially flipping
the RF switch and measuring the two-port S-Parameters for each amplifier in two
separate measurements as shown in Figure 68.
Figure 68: Simulated RPA Small-Signal S-Parameters
These simulated S-parameter measurements were then compared to the measured Sparameters for each power amplifier in absence of the RF switch to confirm correct
62
performance of the assembled RPA. More detailed simulation and measurements for each
amplifier and the RF switch are presented and discussed in subsequent sections of this
chapter.
7.1.1. C-Band PA
The C-Band power amplifier of the RFA was designed for a center frequency of
5.5GHz. This band of operation has applications ranging from direct broadcast satellite
service to scientific communications research.
7.1.1.1.
C-Band PA Design
The C-band PA was first designed and simulated by computing biasing and
stabilization components as well as input and output matching networks as shown in
Figure 69 below.
Figure 69: Schematic of 5.5GHz Power Amplifier
63
Next the layout of each circuit components used from the Triquint (TQNT) MMIC
foundry library was implemented in a microstrip topology.
Figure 70: Layout Topology of the 5.5GHz Power Amplifier
The final un-padded realized layout is shown in Figure 71 for the microstrip topology in
Figure 70.
Figure 71: Final Layout of the 5.5GHz Power Amplifier
The simulated small-signal s-parameters and power measurements were simulated to
verify that specifications were met.
64
Figure 72: Simulated RF Performance of the 5.5GHz Power Amplifier
Overall the performance of the simulated microstrip 5.5GHz power amplifier was similar
to that of the circuit prior to layout (Figure 72).
7.1.1.2.
C-Band PA Fabrication and Characterization
In addition to the C-band amplifier layout in Figure 71 for inclusion in the RPA,
an additional layout of the amplifier which includes pads for probing was also created for
characterization.
Figure 73: Padded Layout for the 5.5GHz Power Amplifier
65
The padded C-band power amplifier shown in Figure 73 was combined with remaining
RPA components in a special layout with additional pads designed for independent
characterization of each power amplifier and the switch in situ, as shown in Figure 74.
Figure 74: Layout of Testing RPA
The performance of the 5.5GHz power amplifier was measured and characterized for the
RPA switched to the C-band amplifier. The small-signal s-parameter measurements are
shown in Figure 75.
66
Figure 75: S-Parameter Measurements for the 5.5GHz Power Amplifier
Although the magnitude of the s-parameters were in line with expected results the center
frequency shifted by 600MHz. Because of the frequency shift the power measurements
were performed at 5.5GHz and 5.8GHz as shown below.
Figure 76: Power Measurements for 5.5GHz Power Amplifier
67
As the Pout-vs.-Pin and Power Added efficiency (PAE) measurements of Figure 76
indicate, it is a reasonable assumption that power performance at 5.5GHz was degraded
by the frequency shift.
7.1.2. X-Band PA
The X-Band power amplifier of the RFA was designed for a center frequency of
8.5GHz.
7.1.2.1.
X-Band PA Design
The X-band PA was designed and simulated similar to the 5.5GHz power
amplifier, with appropriate input and output matching networks for operation at the new
frequency range. The power amplifier circuit with setup for small-signal s-parameter and
power measurements is shown in Figure 77 below.
Figure 77: X-Band Power Amplifier Schematic
68
The layout of the 8.5GHz power amplifier circuit components used from the TQNT
MMIC foundry library implemented in a microstrip is shown in Figure 78.
PORT
P=1
Z=50 Ohm
MLIN
ID=TL10
W=50 um
L=50 um
MTRACE2
ID=X3
W=10 um
L=113.4 um
BType=2
M=1
TQPED_MRIND
ID=L1
W=10 um
S=5 um
N=10
L1=82 um
L2=82 um
LVS_IND="LVS_Value"
MLIN
ID=TL13
W=10 um
L=20 um
MLIN
ID=TL8
W=10 um
L=20 um
MTEE
ID=TL7
W1=W@1 um
W2=W@2 um
W3=W@3 um
1
MLIN
ID=TL9
W=10 um
L=20 um
TQPED_HF_CAP
ID=C1
C=1.7 pF
W=50 um
MLIN
ID=TL19
W=10 um
L=20 um
TQPED_HF_CAP
ID=C5
C=10 pF
W=100 um
MLIN
ID=TL17
W=10 um
L=20 um
2
MTEE
ID=TL18
W1=W@1 um
W2=W@2 um
W3=W@3 um
1
3
MLIN
ID=TL5
W=10 um
L=20 um
2
MTEE
ID=TL2
W1=W@1 um
W2=W@2 um
W3=W@3 um
1
3
MCTRACE
ID=TL1
W=10 um
L=40 um
R=20 um
2
MTEE
ID=TL14
W1=W@1 um
W2=W@2 um
W3=W@3 um
1
1
3
2 TQPED_PHSS
ID=T1
W=50
NG=6
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
3
MSUB
Er=12.9
H=100 um
T=4 um
Rho=1.2
Tand=0.004
ErNom=12.9
Name=SUB1
MLIN
ID=TL6
W=10 um
L=61.4 um
MLIN
ID=TL15
W=10 um
L=98.7 um
TQPED_MRIND
ID=L5
W=10 um
S=5 um
N=10
L1=82 um
L2=82 um
LVS_IND="LVS_Value"
TQPED_MRIND
ID=L2
W=10 um
S=5 um
N=18
L1=232 um
L2=232 um
LVS_IND="LVS_Value"
DCVS
ID=V1
V=-0.05 V
TQPED_SVIA
ID=V3
W=90 um
L=90 um
MCTRACE
ID=TL3
W=10 um
L=40 um
R=20 um
TQPED_SVIA
ID=V4
W=90 um
L=90 um
MCTRACE
ID=TL4
W=10 um
L=79.92 um
R=20 um
MLIN
ID=TL11
W=10 um
L=20 um
TQPED_HF_CAP
ID=C4
C=0.274 pF
W=20 um
MTRACE2
ID=X4
W=10 um
L=40 um
BType=2
M=1
2
3
MLIN
ID=TL12
W=10 um
L=67.1 um
TQPED_MRIND
ID=L6
W=10 um
S=5 um
N=14
L1=114 um
L2=114 um
LVS_IND="LVS_Value"
DCVS
ID=V2
V=3 V
TQPED_HF_RESW
ID=R2
R=100 Ohm
W=5 um
TYPE=NiCr
Figure 78: Microstrip Circuit Layout of the 8.5GHz Power Amplifier
The final 8.5GHz power amplifier layout is shown in Figure 79. For simulation purposes,
RF ports replaces contact pads for obvious reasons.
Figure 79: Unpadded Layout for 8.5GHz Power Amplifier
The s-parameter and power simulations for the 8.5GHz showed similar performance as
the 5.5GHz counterpart, as shown in Figure 80.
69
TQPED_HF_CAP
ID=C3
C=10 pF
W=100 um
MLIN
ID=TL16
W=50 um
L=50 um
PORT
P=2
Z=50 Ohm
Figure 80: S-Parameter and Power Simulations for 8.5GHz PA
7.1.2.2.
X-Band PA Fabrication and Characterization
Similar to the C-band amplifier, the ultimate padded layout of the 8.5GHz power
amplifier was created as shown in Figure 81.
Figure 81: Padded Layout of the 8.5GHz Power Amplifier
The 8.5GHz power amplifier was measured and characterized for the RPA switched to
the X-band power amplifier. The small-signal s-parameter measurements are shown
below in Figure 82.
70
Figure 82: Measure S-Parameters for the 8.5GHz PA
Once again, the measured results exhibit a shift of the designed center frequency, which
most severely affected the input and output return loss of the power amplifier.
Figure 83: Power Measurements for the 8.5GHz PA
71
The power measurements were performed at the design frequency and the results are
shown in Figure 83. Compared to the simulated results the Pout-vs.-Pin and PAE
measurements indicate poor performance because of the frequency shift issue, but
nonetheless should suffice for the overall goal of the project.
7.1.3. Broad-Band MMIC RF FET Switch
The FET RF switch is essentially a single-pole double-throw type designed to
operate over a frequency range covering 5.5GHz and 8.5GHz in one of two modes. The
switch cannot operate in both modes simultaneously.
7.1.3.1.
Broad-Band MMIC RF FET Switch Design
The switch is designed using four transistors with crossed power supplies as
shown in Figure 84.
PORT
P=3
Z=50 Ohm
TQPED_HF_CAP
ID=C3
C=20 pF
W=20 um
TQPED_PHSS
ID=T1
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
TQPED_HF_CAP
ID=C1
C=20 pF
W=20 um
PORT
P=1
Z=50 Ohm
TQPED_RESW
ID=R1
R=200 Ohm
W=5 um
TYPE=NiCr
2
TQPED_RESW
ID=R2
R=200 Ohm
W=5 um
TYPE=NiCr
1
2
1
3
TQPED_PHSS
ID=T2
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
3
V_PROBE
ID=VP1
V_PROBE
ID=VP2
TQPED_PHSS
ID=T3
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
3
2
TQPED_PHSS
ID=T4
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
V_PROBE
ID=VP3
3
1
TQPED_HF_CAP
ID=C4
C=4 pF
W=20 um
PORT
P=2
Z=50 Ohm
2
1
TQPED_RESW
ID=R3
R=100 Ohm
W=5 um
TYPE=NiCr
TQPED_HF_CAP
ID=C2
C=20 pF
W=20 um
V_PROBE
ID=VP4
TQPED_RESW
ID=R4
R=100 Ohm
W=5 um
TYPE=NiCr
DCVS
ID=V2
V=0 V
DCVS
ID=V1
V=-2 V
TQPED_HF_CAP
ID=C5
C=4 pF
W=20 um
Figure 84: Broad-Band MMIC RF FET Switch Design
72
For 5.5GHz PA mode of operation: VG2 is 0V and VG1 is negative. This causes FET1 and
FET4 to be short-circuited while FET2 and FET3 are open-circuited. RF signal can now
flow between Port 1 and Port 3 while allowing Port 1 to be isolated from Port 2.
For 8.5GHz PA mode of operation: VG2 is negative and VG1 is 0V. This causes FET1 and
FET4 to be open-circuited while FET2 and FET3 are short-circuited. RF signal now flow
between Port 2 and Port 3 while Port 1 and Port 2 are isolated.
PORT
P=3
Z=50 Ohm
MTRACE2
ID=X17
W=10 um
L=20 um
BType=2
M=1
TQPED_HF_CAP
ID=C3
C=5 pF
W=75 um
MLIN
ID=TL3
W=10 um
L=20 um
MTRACE2
ID=X5
W=10 um
L=274.7 um
BType=2
M=1
3
2
MTRACE2
ID=X6
W =10 um
L=271.7 um
BType=2
M=1
TQPED_PHSS
ID=T1
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
1
MTEEX
ID=MT3
W1=W @1 um
W2=W @2 um
W3=W @3 um
TQPED_RESW
ID=R1
R=200 Ohm
W=5 um
TYPE=NiCr
2
TQPED_RESW
ID=R2
R=200 Ohm
W=5 um
TYPE=NiCr
2
1
1
3
TQPED_PHSS
ID=T2
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
3
V_PROBE
ID=VP1
V_PROBE
ID=VP2
MTRACE2
ID=X1
W=10 um
L=33.2 um
BType=2
M=1
MTRACE2
ID=X3
W =10 um
L=40 um
BType=2
M=1
TQPED_HF_CAP
ID=C1
C=5 pF
W=75 um
PORT
P=1
Z=50 Ohm
3
MTRACE2
ID=X15
W =10 um
L=203 um
BType=2
M=1
MLIN
ID=TL1
W=10 um
L=45.5 um
MTRACE2
ID=X12
W=10 um
L=556.1 um
BType=2
M=1
1 MTEEX
ID=MT1
W1=W@1 um
W2=W@2 um
2 W3=W@3 um
MTRACE2
ID=X2
W=10 um
L=360.4 um
BType=2
M=1
2
TQPED_PHSS
ID=T3
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
3
TQPED_SVIA
ID=V5
W=90 um
L=90 um
TQPED_SVIA
ID=V6
W =90 um
L=90 um
MTRACE2
ID=X11
W=10 um
L=613.9 um
BType=2
M=1
TQPED_SVIA
ID=V7
W=90 um
L=90 um
MTEEX
ID=MT2
W1=W@1 um
W2=W@2 um
W3=W@3 um
3
MTRACE2
ID=X8
W=10 um
L=190.1 um
BType=2
M=1
TQPED_RESW
ID=R3
R=100 Ohm
W=5 um
TYPE=NiCr
TQPED_RESW
ID=R4
R=100 Ohm
W=5 um
TYPE=NiCr
MLIN
ID=TL4
W=10 um
L=20 um
MLIN
ID=TL6
W=10 um
L=20 um
MCROSSX
ID=MX2
W1=W@1 um
W2=W@2 um
W4=W@4 um
1
2
MCROSSX
ID=MX1
W1=W@1 um
W2=W@2 um
W4=W@4 um
4
TQPED_SVIA
ID=V3
W=90 um
L=90 um
PORT
P=2
Z=50 Ohm
MLIN
ID=TL2
W=10 um
L=34.5 um
2
1
MTRACE2
ID=X7
W=10 um
L=197.6 um
BType=2
M=1
TQPED_HF_CAP
ID=C4
C=4 pF
W=73.23 um
MTRACE2
ID=X16
W=10 um
L=247.8 um
BType=2
M=1
2
1
MTRACE2
ID=X9
W=10 um
L=40 um
BType=2
M=1
3
MTRACE2
ID=X4
W=10 um
L=294.2 um
BType=2
M=1
TQPED_PHSS
ID=T4
W=50
NG=4
dVp=0 V
TEMP=25 DegC
TQ_TOM3_MB=PHSS
TQPED_SVIA
ID=V8
W=90 um
L=90 um
TQPED_HF_CAP
ID=C2
C=5 pF
W =75 um
1
3
MTRACE2
ID=X10
W=10 um
L=40 um
BType=2
M=1
1
2
4
3
MTRACE2
ID=X13
W=10 um
L=82 um
BType=2
M=1
1
TQPED_HF_CAP
ID=C5
C=4 pF
W=77.95 um
MTRACE2
ID=X14
W =10 um
L=80.7 um
BType=2
M=1
1
TQPED_SVIA
ID=V4
W =90 um
L=90 um
DCVS
ID=V2
V=-2 V
DCVS
ID=V1
V=0 V
TQPED_PAD
ID=P1
TQPED_PAD
ID=P2
Figure 85: Broad-Band MMIC RF FET Switch Circuit Layout
The microstrip circuit for the switch is shown in Figure 85 and Figure 86 shows the
unpadded layout in the TQNT process.
73
Figure 86: Unpadded Broad-Band MMIC RF Switch Layout
Figure 87 illustrates the simulated performance of the switch in both modes of operation
and indicating minimal insertion loss and good isolation.
Figure 87: Broad-Band MMIC RF Switch S-Parameter Simulation
74
7.1.3.2.
Broad-Band MMIC Switch Fabrication and Characterization
The full padded layout of the FET RF switch is shown in Figure 88. The configuration is
arranged such that three probes can be connected simultaneously to characterize the
switch.
Figure 88: Padded Layout of Broad-Band MMIC RF FET Switch
In addition to the RF probes, two direct current (DC) probes are necessary to bias the
FETs to control switching.
75
Figure 89: Broad-Band MMIC RF FET Switch S-Parameter Measurements
The fabricated switch was measured and the results are shown in Figure 89 above. The
measured insertion is less than or equal to 1.6 dB while return loss was less than -12 dB.
76
CHAPTER 8 MIC L/S-BAND RECONFIGURABLE AMPLIFIER
One of the key research limitations in pursuing the challenges and solving the
issues encountered during evaluation of the RPA is the availability of resources for future
MMIC fabrication runs in the TQNT 0.5-um process. To overcome this, a reconfigurable
low-noise amplifier (RLNA) is developed with architecture similar to that of the RPA,
however, using PCB MIC technology.
8.1. Switched-Based L/S-Band Reconfigurable LNA
A microstrip dual-band switchable LNA design was implemented on 10-mil thick
Rogers 3010 substrate, using an architecture similar to the MMIC implementation of the
RPA. The unique approach to using the 3010 substrate is that its thin substrate height
made it possible to implement a more compact design. This is important because of the
weight constraint for future space applications. There are several contentious issues to
solve, however, chief of which are die size and fabrication inconsistencies. At L/S-band
microstrip circuits are larger and because the lines are milled, achieving proper line
widths may prove difficult. However, successful development is achievable because
fabrication time is greatly reduced and the required commercial off-the-shelf (COTS)
circuit components are relatively cheap. This makes multi-run fabrication a useful and
practical aid.
8.1.1. RLNA Specifications and Architecture
Table 12 below highlights the important design specifications for the RLNA.
Although size is not highlighted in the specifications list, it is inherently a major concern
of the design.
77
Table 12: RLNA Minimum Specifications
Parameters
Center Frequencies (fc)
3dB Bandwidth
Stop Band Rejection
Gain
Noise Figure
Flatness
Input/output VSWR
Input/output Impedance
Reverse Isolation
Specification
2.05/2.25-GHz
+/- 50MHz @ each fc
25dB +/- 200MHz From Band Center
20 dB
1.5 dB
+/- .5 dB
1.5/1.7
50 Ohms
> 30dB
As previously stated, the RLNA was designed and implemented in as a microwave
integrated circuit (MIC) using commercial off-the-shelf (COTS) components. Essentially,
the RLNA is comprised of two MIC low-noise amplifiers with respective center
frequencies at 2.05GHz and 2.25GHz, controlled by the MIC FET Switch. Figure 90
shows the basic topology of the RLNA.
Figure 90: L/S-Band LNA
Since the MIC RLNA utilizes components soldered onto a microstrip substrate it was
important to consider the losses associated with interconnects of such components. For
78
that reason, the Rogers 3010 substrate was chosen for its dielectric properties to facilitate
a design incorporating shorter lines to achieve characteristic impedance (Z0) of 50Ω.
Figure 91: L/S-Band RLNA Layout
The final layout of the RLNA shown in Figure 91 was arranged so that the input from
each amplifier on both sides of the switch opposes the output of the switch for convenient
mounting in a test fixture, while the bias lines for the amplifiers are on the outer
perimeter of the circuit for easy connection access.
79
Figure 92: Milled L/S-Band RLNA Circuit
Because of the relatively thin substrate the milled circuit, shown in Figure 92, required a
mounting plate for proper handling. For practical fabrication this plate would be replaced
by a sized package.
Figure 93: Fabricated L/S-Band RLNA Wired in Test Fixture
The fabricated L/S-Band RLNA, shown in Figure 93, was mounted on a metal block test
rig using indium tape on the backside for proper RF ground contact and held in place
with the center pins of two coax connectors (silver left/right). The three gold-plated SMA
connectors from left to right are the L-Band LNA input, RF Switch output, and S-Band
LNA input, respectively. DC voltages are applied using clip-lead connectors screwed into
the perimeter of the block as needed.
80
8.1.2. L-Band LNA
The L-Band power amplifier of the RLNA was designed to operate at a center
frequency of 2.05GHz with very sharp roll-off outside the 100MHz pass-band. It is
important to realize that this narrow band of operation is challenging to achieve, but if
successful greatly simplifies the architecture of the overall RLNA.
8.1.3. L-Band LNA Design
A two-stage design approach was selected to achieve the Gain specified in Table
12. The matching network was designed to achieve lowest noise possible for stable
operation and good return loss. The schematic of the L-Band amplifier is shown in Figure
94.
Figure 94: L-Band LNA Schematic
The L-Band LNA was realized using a microstrip micro-strip lines and separate bias lines
for each gate and drain of the transistors. This implementation offers more tuning options
to maximize performance after fabrication. Figure 95 shows the layout for the L-Band
LNA.
81
Figure 95: L-Band LNA Layout
In order to fabricate the amplifier it was necessary to generate the Gerber image of the
micro-strip lines of the circuit.
Figure 96: L-Band LNA Placement and Etching Artwork
The required placement artwork and corresponding Gerber image are shown in Figure 96.
The required vias for RF ground is also shown in the artwork. Precise fabrication of the
vias is critical for accurate amplifier performance. The simulated s-parameters of the LBand LNA are shown in Figure 97 while the simulated noise figure is shown in Figure
98.
82
Figure 97: L-Band LNA Simulated S-Parameters
Figure 98: L-Band LNA Simulated Noise Figure
83
8.1.4. L-Band LNA Fabrication and Characterization
The L-Band LNA was fabricated by milling the Gerber artwork shown in Figure 96 and
vias were formed using corresponding Drill files, which has dimensions and locations of
the vias (red circles) illustrated in Figure 96. The milled L-Band LNA circuit is shown in
Figure 99. As illustrated, this amplifier is small relative to its operating frequency. This is
a direct result of the substrate chosen for the design.
Figure 99: Milled L-Band LNA Circuit
Once the L-band amplifier was milled it was mounted on a test fixture block for easier
handling and measurement. The mounted amplifier is shown in Figure 100.
Figure 100: L-Band LNA Mounted in Test Fixture
84
The L-Band LNA was tested using a shared bias source for both transistor gates and a
separate shared bias source for both transistor drains. Bias was optimized to maximize
gain and minimize noise figure. The s-parameters were measured using a vector network
analyzer (VNA), calibrated over the operating frequency range of the LNA.
DB(|S(2,1)|)
DB(|S(2,1)|)
L_Band_LNA_Module_Layout l_band_2p0v
DB(|S(1,1)|)
DB(|S(1,1)|)
L_Band_LNA_Module_Layout l_band_2p0v
DB(|S(2,2)|)
L_Band_LNA_Module_Layout
DB(|S(2,1)|)
l_band_1p6v
DB(|S(2,1)|)
l_band_2p5v
DB(|S(1,1)|)
l_band_1p6v
DB(|S(1,1)|)
l_band_2p5v
DB(|S(2,2)|)
l_band_1p6v
DB(|S(2,1)|)
l_band_1p8v
DB(|S(2,1)|)
l_band_2p8v
DB(|S(1,1)|)
l_band_1p8v
DB(|S(1,1)|)
l_band_2p8v
L_Band_LNA_Test
40
2204 MHz
16.8 dB
20
0
-20
-40
-60
500
2500
4500
6500
Frequency (MHz)
8500
10000
Figure 101: L-Band LNA Measured vs. Simulated S-Parameters
Figure 101 shows plots of the measured s-parameters plotted with the simulated sparameters. The measured response was approximately 7dB less than predicted with a
small rightward shift in frequency.
85
Figure 102: L-Band LNA Measured Gain and Noise Figure
The noise figure (along with gain), shown in Figure 102, was measured using a noise
figure meter and is approximately 1.2dB higher than expected. This difference is most
likely a result of the difference in bias condition between the data used in the design
process and the current drive at test to maximize gain. Though still a respectable
performance, this is somewhat disappointing. One silver lining here is that gain measured
using the noise figure meter is approximately 2dB higher than was measured using the
VNA. The source of this discrepancy is unknown, though most likely a result in
calibration difference between the two instruments.
8.1.5. S-Band LNA
The S-Band power amplifier of the RLNA was designed to operate at a center
frequency of 2.25GHz with very sharp roll-off outside the 100MHz pass-band. Similar to
its L-Band counterpart, the S-Band LNA had a challenging narrow band operation
86
requirement. Hence the L-Band amplifier was simply tuned and optimized to achieve a
similar level of performance at merely a small shift in frequency.
8.1.6. S-Band LNA Design
Once again a two-stage design approach was chose to achieve performance
specifications outlined in Table 12. The matching network was designed to achieve
lowest noise possible for stable operation and good return loss. The schematic of the LBand amplifier is shown in Figure 103.
Figure 103: S-Band LNA Schematic
The S-Band LNA, similar to the L-Band design, was realized using a microstrip microstrip lines and separate bias lines for each gate and drain of the transistors thereby
maximizing post-fabrication tuning options. Figure 104 shows the layout for the L-Band
LNA.
87
Figure 104: S-Band LNA Layout
The associated placement drawing and fabrication Gerber artwork is shown in Figure
105. Upon comparing the two amplifier artwork, it may be readily noticed that the most
significant difference between the L-Band and S-Band designs are the line lengths in the
matching networks.
Figure 105: S-Band LNA Placement and Etching Artwork
The simulated s-parameters of the S-Band LNA is shown in Figure 97 while the
simulated noise figure is shown in Figure 98.
88
Figure 106: S-Band LNA Simulated S-Parameters
Figure 107: L-Band LNA Simulated Noise Figure
89
8.1.7. S-Band LNA Fabrication and Characterization
Similar to the L-Band LNA, the S-Band LNA was milled using the Gerber artwork
shown in Figure 105 and vias formed using corresponding Drill files. The milled S-Band
LNA circuit is shown in Figure 108. This amplifier, like its L-band counterpart, is small
relative to the operating frequency.
Figure 108: Milled S-Band LNA Circuit
Figure 109: S-Band LNA Mounted in Test Fixture
90
Figure 109 shows the S-Band LNA mounted on the test fixture block for measurements.
The LNA was tested using a shared bias source for both transistor gate terminals and
correspondingly a separate shared bias source for transistor drain terminals.
DB(|S(2,1)|)
S_Band_LNA_Module_Layout
DB(|S(2,1)|)
s_band_2p25v
DB(|S(1,1)|)
s_band_2p5v
DB(|S(1,1)|)
s_band_1p5v
DB(|S(2,1)|)
s_band_1p5v
DB(|S(2,1)|)
s_band_2p5v
DB(|S(1,1)|)
s_band_2p25v
DB(|S(2,2)|)
S_Band_LNA_Module_Layout
DB(|S(2,1)|)
s_band_2p0v
DB(|S(1,1)|)
S_Band_LNA_Module_Layout
DB(|S(1,1)|)
s_band_2p0v
DB(|S(2,2)|)
s_band_1p5v
S_Band_LNA_Test
40
2126.9 MHz
17.6 dB
20
0
-20
-40
-60
500
2500
4500
6500
Frequency (MHz)
8500
10000
Figure 110: S-Band LNA Measured vs. Simulated S-Parameters
Figure 110 show plots of the measured s-parameters plotted with the simulated sparameters, with the measured response being approximately 6dB less than simulated and
shifted slightly left of the designed center frequency.
91
Figure 111: S-Band LNA Measured Gain and Noise Figure
The measured noise figure and gain are shown in Figure 111, with noise figure being
approximately 1.2dB higher than expected and gain 2dB higher than was measured on the
VNA. The explanation for these discrepancies offered for the L-Band design holds true
for the S-Band LNA as well.
8.1.8. Broad-Band MIC RF FET Switch
The MIC FET RF switch, a single-pole double-throw type similar to that of the
MMIC C/X-Band version, was designed to operate over a broad-band frequency range
including the L- and S-band frequency interval of the two amplifiers (2.0-GHz to 2.3GHz). Hence the switch is able to operate in one of two frequency modes and not both
simultaneously.
92
8.1.9. Broad-Band MIC RF FET Switch Design
The switch was designed using the same FETs as the amplifiers, thereby
exploiting the low-noise capabilities of the device. In order to minimize size of the
switch, and subsequently insertion loss, a thinner substrate material was chosen for this
and other RLNA components. The schematic of the switch is shown in Figure 112.
w1=0.25
PORT
P=3
Z=50 Ohm
0 mA
MSUB
Er=10.2
H=0.254 mm
T=0.017 mm
Rho=0.7
Tand=0.0035
ErNom=10.2
Name=RO/RO1
MLIN
ID=TL3
W=1.2 mm
L=1.5 mm
0 mA
SUBCKT
ID=S9
NET="R07C120_meas"
0 mA
MLIN
ID=TL2
W=0.6 mm
L=0.5 mm
MTRACE2
ID=TL5
W=w1 mm
L=1.527 mm
BType=2
M=1
MSTEPX$
ID=MS3
Offset=0 mm
MTRACE2
ID=TL4
W=w1 mm
L=1.899 mm
BType=2
M=1
0 mA
3
2
0 mA
MSTEPX$
ID=MS4
Offset=0 mm
1
0 mA
0 mA
0 mA
0 mA
MTEEX$
ID=MT1
0 mA
0 mA
MLIN
ID=TL6
W=0.6 mm
L=1.2 mm
MLIN
ID=TL7
W=0.6 mm
L=1.2 mm
MLIN
ID=TL11
W=0.6 mm
L=1.2 mm
0 mA
2
SUBCKT
ID=S1
NET="NE3509M04_v124"
UgwNew=0.4
NfgNew=1
SUBCKT
ID=S7
NET="ERJ2GEJ181"
MLIN
ID=TL24
W=0.6 mm
L=0.6 mm
MLIN
ID=TL25
W=0.6 mm
L=0.6 mm
MSTEPX$
ID=MS1
Offset=0 mm
SUBCKT
ID=S8
NET="ERJ2GEJ181"
MLIN
ID=TL1
W=0.6 mm
L=1.2 mm
SUBCKT
ID=S2
NET="NE3509M04_v124"
UgwNew=0.4
NfgNew=1
1
0 mA
0 mA
2.65e-6 mA
2.44e-6 mA 0 mA
0 mA
0 mA
0 mA
0 mA
MSTEPX$
ID=MS2
Offset=0 mm
3
0 mA
2
1
3
0 mA
0 mA
0 mA
MTRACE2
ID=X2
W=w1 mm
L=9.62 mm
MLIN
ID=TL21
W=0.6 mm
L=1.2 mm
MLIN
ID=TL12
W=0.6 mm
L=1.2 mm
2.46e-6 mA
BType=2
M=1
MTRACE2
ID=X1
W=w1 mm
L=3.527 mm
BType=2
M=1
MSTEPX$
ID=MS5
Offset=0 mm
MSTEPX$
ID=MS10
Offset=0 mm
0 mA
0 mA
0 mA
0 mA
MTRACE2
ID=TL18
W=w1 mm
L=3.1 mm
BType=2
M=1
PORT
P=1
Z=50 Ohm
MLIN
ID=TL10
W=1.2 mm
L=1.5 mm
SUBCKT
ID=S10
NET="R07C120_meas"
0 mA
0 mA
0 mA
1
0 mA
0 mA
MLIN
ID=TL9
W=0.6 mm
L=1.2 mm
MTEEX$
ID=MT3
2
MLIN
ID=X10
W=w1 mm
L=1 mm
MSTEPX$
ID=MS7
Offset=0 mm
3
0 mA
3
02
mA
MLIN
ID=TL23
W=0.6 mm
L=1 mm
0 mA
0 mA
MLIN
ID=TL15
W=0.6 mm
L=0.945 mm
0 mA
0 mA
PORT
P=2
Z=50 Ohm
MTRACE2
ID=X4
W=w1 mm
L=1.771 mm
BType=2
M=1
SUBCKT
ID=S4
0 mA
MVIA1P
ID=V7
D=0.4 mm
H=0.254 mm
T=0.017 mm
W=0.6 mm
RHO=1
MLIN
ID=TL36
W=0.6 mm
L=0.945 mm
MVIA1P
ID=V3
D=0.4 mm
H=0.254 mm
T=0.017 mm
W=0.6 mm
RHO=1
1
0 mA
0 mA
0 mA
MVIA1P
ID=V8
D=0.4 mm
H=0.254 mm
T=0.017 mm
W=0.6 mm
RHO=1
MLIN
ID=TL35
W=0.6 mm
L=1.2 mm
SUBCKT
ID=S3
NET="NE3509M04_v124"
0 mA
UgwNew=0.4
NfgNew=1
0 mA
0 mA
MLIN
ID=TL13
W=0.6 mm
L=0.8 mm
2
0 mA
MLIN
ID=TL20
W=1.2 mm
L=1.5 mm
SUBCKT
ID=S11
NET="R07C120_meas"
1
MTEEX$
ID=MT2
3
0 mA
MTRACE2
ID=TL33
W=w1 mm
L=3.152 mm
BType=2
M=1
0 mA
MVIA1P
ID=V4
D=0.4 mm
H=0.254 mm
T=0.017 mm
W=0.6 mm
RHO=1
0 mA
MSTEPX$
ID=MS6
Offset=0 mm
UgwNew=0.4
NfgNew=1
0 3mA
2
0 mA
MLIN
ID=TL22
W=0.6 mm
L=0.9 mm
1
0 mA
MLIN
ID=TL14
W=0.6 mm
L=1.2 mm
0 mA
NET="NE3509M04_v124"
0 mA
0 mA
MLIN
ID=TL37
W=0.6 mm
L=1.2 mm
MTRACE2
ID=TL34
W=0.6 mm
L=1.9 mm
BType=1
M=1
0 mA
0 mA
2.46e-6 mA
SUBCKT
ID=S5
NET="ERJ2GEJ101"
ABRIDGE
ID=TL28
W=w1 mm
L=1.6 mm
D=0.04 mm
H=0.04 mm
Er=1
MLIN
ID=TL26
W=0.3 mm
L=0.3 mm
SUBCKT
ID=S6
NET="ERJ2GEJ101"
0 mA
0 mA
2.46e-6 mA
MLIN
ID=TL16
W=0.6 mm
L=0.6 mm
MLIN
ID=TL17
W=0.6 mm
L=0.5 mm
0 mA
0 mA
3
2
3
1
0 mA
2
0 mA
MSTEPX$
ID=MS8
Offset=0 mm
0 mA
9.93e-5 mA
MLIN
ID=TL27
W=0.3 mm
L=0.3 mm
MTRACE2
ID=X6
W=w1 mm
L=4.444 mm
BType=2
M=1
MTRACE2
ID=X7
W=w1 mm
L=1.479 mm
BType=2
M=1
0 mA
9.93e-5 mA
2
0 mA
MTEEX$
ID=MT6
2
3
3
0 mA
2.45e-6 mA
2.46e-6
MTRACE2
ID=X9
W=w1 mm
L=1.9 mm
BType=2
M=1
1
MLIN
ID=TL29
W=0.6 mm
L=0.6 mm
0 mA
MLIN
ID=TL8
W=1.2 mm
L=2 mm
0 mA
SUBCKT
ID=S12
NET="R07C4R3_meas"
0.000102 mA
0 mA
0 mA
MTEEX$
ID=MT7
1
MLIN
ID=TL19
W=1.2 mm
L=2 mm
DCVS
ID=V2
V=-1 V
MLIN
ID=TL31
W=1.2 mm
L=1.5 mm
0.0001 mA
MTRACE2
ID=X8
W=w1 mm
L=1.037 mm
BType=2
M=1
0.0001 mA
MSTEPX$
ID=MS9
Offset=0 mm
0.0001 mA
MLIN
ID=TL30
W=0.6 mm
L=0.6 mm
0.0001 mA
0.000102 mA
DCVS
ID=V1
V=0 V
0.0001 mA
MTEEX$
ID=MT5
2.46e-6 mA
0 mA
MTRACE2
ID=X5
W=w1 mm
L=3.714 mm
BType=2
M=1
1
9.93e-5 mA
MTEEX$
ID=MT4
0 mA
SUBCKT
ID=S13
NET="R07C4R3_meas"
0 mA
MLIN
ID=TL32
W=1.2 mm
L=1.5 mm
Figure 112: L/S-Band FET RF Switch Schematic
Unlike its MMIC counterpart, the crossover bias scheme for the center transistors of the
MIC technology does not allow for a convenient air-bridge method of jumping lines. For
93
this reason a microstrip ribbon was used and modeled as a wide bond wire. The following
summarizes the switch operation:
• L-Band operation mode: VG2 = 0V, VG1 =-1V.
This shorts FET1 and FET4 while FET2 and FET3 are open, causing RF signal to
flow between Port 1 and Port 3 while isolating Port 1 from Port 2.
• S-Band operation mode: VG2 = -1V, VG1 = 0V.
This opens FET1 and FET4 while shorting FET2 and FET3, causing RF signal to
flow between Port 2 and Port 3 while isolating Port 1 from Port 2.
Figure 113 below shows the final layout for the MIC RF switch. It is important to note
the gap in the bias line of the left image. The micro-strip ribbon will be solder in after
fabrication as outlined in the right image.
Figure 113: L/S-Band MIC RF Switch Layout
Similar to the L- and S-band amplifier circuits the associated placement drawing and
fabrication Gerber artwork for the MIC RF switch is shown in Figure 114.
94
Figure 114: L/S-Band MIC RF Switch Placement and Etching Artwork
Unlike the MMIC RPA, the MIC RLNA will require soldering of all components.
As a result it is anticipated that some RF loss will be associated with this process, but this
shortcoming is not expected to significantly impact the overall amplifier gain and noise
figure.
Figure 115: L/S-Band MIC RF Switch S-Parameters
95
The simulated s-parameters for the MIC RF Switch are shown in Figure 115.
8.1.10. Broad-Band MIC Switch Fabrication and Characterization
The MIC RF Switch was milled using the Gerber artwork shown in Figure 114
and vias formed using corresponding Drill files. The milled RF Switch circuit is shown in
Figure 116. This switch is very small, roughly the size of a U.S. dime, and should do
nicely for a variety of applications
.
Figure 116: Milled Broad-Band MIC Switch Circuit
Figure 117: MIC RF Switch Mounted in Test Fixture
96
Figure 117 shows the MIC RF switch mounted on the test fixture. The MIC switch was
tested using separate bias supplies for the toggle lines. The s-parameters were measured
using a VNA and the forward transmission characteristic for the left switch is shown in
Figure 118. The insertion loss of the switch #1 (port 1 to port 3) is approximately 4dB,
1.5dB higher than previously simulated.
Sw13_On_Sw23_Off
0
2250 MHz
-4.01 dB
-10
-20
2250 MHz
-13.67 dB
-30
DB(|S(2,1)|)
DB(|S(2,1)|)
sw13_v1_m1_v2_0_Ib_0mA sw23_v1_m1_v2_0_Ib_0mA
-40
500
1500
2500
3500
Frequency (MHz)
4500
5000
Figure 118: MIC RF Switch - Measured Switch #1 S-Parameters
The measured forward transmission s-parameter for the right switch is shown in Figure
119. The insertion loss of the switch #2 (port 2 to port 3) is approximately 8dB, 5.5dB
higher than previously simulated.
97
Sw23_On_Sw13_Off
0
-10
2250 MHz
-7.919 dB
-20
-30
2250 MHz
-21.02 dB
-40
DB(|S(2,1)|)
sw13_v1_0_v2_m1_Ib_12mA
DB(|S(2,1)|)
sw23_v1_0_v2_m1_Ib_12mA
-50
500
1500
2500
3500
Frequency (MHz)
4500
5000
Figure 119: MIC RF Switch - Measured Switch #2 S-Parameters
The isolation between the two switches when switch #1 is operating is
approximately 13.7dB, while the isolation in the switch #2 mode is -21dB. Unfortunately,
in the switch #2-mode there was significantly more loss than in the switch #1-mode. This
was attributed to inaccuracies in the transistor model used for the FET switch design.
Additionally, the ribbon used as an air-bridge in the VG1 path may have had a negative
impact on transmission losses.
8.1.11. RLNA Issues and Challenges
One of the key challenges during fabrication was the delicate nature of the
substrate. A small sacrifice in size for a thicker substrate would ensure proper via contact
and easier handling. It was also realized that after soldering directly to the bias pads of
the circuits the weight of the wires used caused lifting of some pads and lines towards the
98
end of the test. Therefore a strategy to use thinner mag wires running parallel to the board
to pins inserted into the test fixture block proved to be a better approach. The integration
of the MIC RF Switch with the test fixture block was difficult because a custom sized
block could not be readily fabricated. As a result it was necessary to use longer than
desired ribbons to connect to the RF ports, as illustrated in Figure 117. Furthermore, the
ribbon used as an air-bridge for the VG1 pad may have contributed to the additional
insertion loss shown in Figure 119. Overall, the insertion loss of the switch in both L- and
S-Band modes were higher than predicted, but improved fabrication and integration
coupled with minor design tweaks should improve performance.
99
CHAPTER 9 ALTERNATIVE TOPLOGIES FOR FUTER INVESTIGATION
It is strongly believed that future design strategies should involve coupled line
structures which promise to significantly improve the out-of-band frequency roll-off
thereby enabling better amplifier performance. Based on a preliminary advanced study of
this technique, a coupled-resonator band-pass filter was developed to study the potential
frequency roll-off effect of this topology. The results are presented in subsequent
sections.
9.1.
L-Band Dual-Mode Coupled Resonator Band Pass Filter (CR-BPF)
In the early phase of the research it was believed that alternative matching
structures should be investigated for application to multi-band amplifier designs.
However it was discovered that such designs would require extensive investigation into
using a matrix-based matching network to accomplish multi-band matching. It is believed
that this work shows great promise based on the preliminary design success achieved.
This work will form the basis for future work in this area, but will not be treated as the
design approach for this work. An L-band microstrip band-pass filter (BPF) using
degenerate modes of a meander loop resonator was developed to exploit the significant
reduction in physical size.
9.1.1. CR-BPF Design
The BPF was designed on RT/Duroid substrate (εR=10.2) for a total area of
22.75mm x 16.6mm. For the planar microstrip BPF structure shown in Figure 120,
electromagnetic (EM) analysis was performed to simulate its RF characteristics.
100
Port1
Port2
Figure 120: L-Band Dual Mode BPF Design
The s-parameter simulation results for the EM analysis shown in Figure 121 illustrates
good insertion and return loss performance over the design frequency range.
Figure 121: BPF Simulated S-Parameters
101
9.1.2. CR-BPF Fabrication and Characterization
The dual-mode BPF was successfully milled, as seen in Figure 122, and sparameter measurements were performed to determine insertion loss and isolation
properties of the filter.
Figure 122: Fabricated BPG on RT/Duroid
The measured results of the filter compared well with the simulated data. One notable
issue was the fact that return loss (isolation) and harmonic suppression could be
improved.
102
Filter Results_Design_OpBand
0
-10
1.41 GHz
-1.853 dB
1.408 GHz
-9.968 dB
-20
-30
-40
DB(|S(1,1)|)
Filter_OpBand
-50
DB(|S(2,1)|)
Filter_OpBand
DB(|S(2,2)|)
Filter_OpBand
-60
0.5
1
1.5
Frequency (GHz)
2
2.5
Figure 123: Measured S-Parameters for Fabricated BPF
A theoretical way to overcome these two issues is by adding more poles (cascade 2 or
more filters) to the design. The filter construction was completed by adding SMA
connectors for interface with other subsystem components. The filter exhibited minimal
loss of 1.85 dB with a return loss of about 10dB.
9.2. RLNA Topology for Future Investigation
The topology of the proposed PCB RLNA is shown in Figure 64. This promises
to be a feasible extension of the preliminary work presented in 9.1. This work shall be
pursued as a post-doctoral extension to the switchable multi-band amplifier development.
9.3.
Coupled Resonator Filter Based L/S-Band Reconfigurable LNA
Concerning the future exploratory research for the RLNA, a microstrip design
based on coupled resonator matching networks implemented on PCB will be employed.
A resonator of the type shown in Figure 124 will be used as the unit of an array at the
input and output of the FET.
103
Figure 124: Coupled Resonator Element
Essentially each array will contain n x n units which will be optimally tapped to present
the right impedance required to match the transistors at the right operating frequency and
DC bias. A preliminary proposed topology of such an array is shown in Figure 125.
Figure 125: Cross-Coupled Split-Ring Resonator Array
9.3.1. CR-RLNA Specifications
The minimum specifications for the proposed PCB CR-RLNA are shown in Table
12. It is important to note that there may be a substantial difference in size due to the
coupling structures required. However, for now there is no size limit imposed on the
design.
104
9.3.2. CR-LNA Topology
The proposed preliminary topology of the proposed future PCB CR-RLNA to
extend the development of reconfigurable amplifier technology is shown in Figure 126.
Figure 126: Couple Resonator Reconfigurable LNA Topology
105
CHAPTER 10 CONCLUSION
The ever increasing demand by consumers for greater speed and capacity for an
array of communication devices and methods drives the need for more flexible
communications systems, given the limitation of available bandwidth. This clearly poses
a challenge to communications systems engineers and circuit designers tasked to reinvent
the way data channels are shared among network users. Regardless of the medium, wired,
terrestrial wireless or satellite, the job at hand is the same; more power with more
bandwidth at reduced cost of operation.
This dissertation presented a method of combining multiple amplifiers based on
the design concept of a low-loss transmit-receive switch. First, a switchable dual-band
power amplifier was designed for use at C and X bands for use in SATCOM based
transmitters. This power amplifier was designed using a MESFET MMIC technology.
This technology offered low-loss high speed transistors making possible a robust design
that is easily reproducible for volume production. Next, a switchable low-noise amplifier
was developed for use in both terrestrial and space applications at L and S bands. The
LNA, unlike the MMIC PA, use a hybrid MIC technology based on a printed circuit
board. The fabrication technique was exploited to explore the possibility of an ultra-low
cost design. Both the PA and LNA designs had some challenges that given reasonable
continued development efforts could seriously revolutionize modern communication
system design. Finally, a novel circuit design technique based on coupled resonators was
proposed and was explored in an infant phase by developing a coupled-line resonator
filter. This technique should enable very novel reconfigurable matching networks.
106
The LNA and RLNA circuits of APPENDIX I can be fabricated using GDSII
or Gerber files supplied by the author for milling or etching the printed circuit boards.
The electrical components listed in APPENDIX II can be purchased from the
NewarkInOne or the DigiKey online stores. Circuit design files can also be obtained
from the author for further analysis. The author can be contacted at
dsharvey@ieee.org.
107
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111
APPENDIX I.
MIC RLNA Board Layouts
This appendix includes the artwork for LNA and RLNA circuits.
Figure 127: L/S-Band RLNA Layouts
112
APPENDIX II.
MIC RLNA Bill of Materials
L-Band LNA Bill of Materials
L_Band_LNA_Module_Layout
Quantity
Schematic ID
2
S2
S3
4
S9
S4
S6
S5
4
S10
S8
S7
S1
2
S12
S11
Component Type
SUBCKT - Netlist
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
Value
NE3509M04_v124
18-nH
18-nH
18-nH
18-nH
18-nH
12-pF
12-pF
12-pF
12-pF
12-pF
68-Ohm
68-Ohm
68-Ohm
Part Number
NE3509M04
NE3509M04
NE3509M04
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ680
Manufacturer
NEC Devices
NEC Devices
NEC Devices
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Panasonic
Panasonic
Panasonic
Package Type
M04
M04
M04
402
402
402
402
402
402
402
402
402
402
R1005
R1005
R1005
Description
FET
FET
FET
Inductor
Inductor
Inductor
Inductor
Inductor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
S-Band LNA Bill of Materials
S_Band_LNA_Module_Layout
Quantity
Schematic ID
2
S2
S3
4
S9
S4
S6
S5
4
S10
S8
S7
S1
2
S12
S11
Component Type
SUBCKT - Netlist
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
Value
NE3509M04_v124
18-nH
18-nH
18-nH
18-nH
18-nH
12-pF
12-pF
12-pF
12-pF
12-pF
68-Ohm
68-Ohm
68-Ohm
Part Number
NE3509M04
NE3509M04
NE3509M04
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ680
MIC RF Switch Bill of Materials
113
Manufacturer
NEC Devices
NEC Devices
NEC Devices
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Panasonic
Panasonic
Panasonic
Package Type
M04
M04
M04
402
402
402
402
402
402
402
402
402
402
R1005
R1005
R1005
Description
FET
FET
FET
Inductor
Inductor
Inductor
Inductor
Inductor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
RF_Switch_Layout
Quantity
Schematic ID
4
S1
S2
S3
S4
2
S5
S6
2
S7
S8
3
S9
S10
S11
2
S12
S13
Component Type
SUBCKT - Netlist
SUBCKT
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
SUBCKT
SUBCKT - Data File
SUBCKT
SUBCKT
Value
Part Number
NE3509M04_v124
100-Ohm
100-Ohm
100-Ohm
180-Ohm
180-Ohm
180-Ohm
12-pF
12-pF
12-pF
12-pF
4.3-pF
4.3-pF
4.3-pF
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
ERJ2GEJ101
ERJ2GEJ101
ERJ2GEJ101
ERJ2GEJ181
ERJ2GEJ181
ERJ2GEJ181
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C4R3XX4
250R07C4R3XX4
250R07C4R3XX4
Manufacturer
Package Type
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Description
M04
M04
M04
M04
M04
R1005
R1005
R1005
R1005
R1005
R1005
402
402
402
402
402
402
402
FET
FET
FET
FET
FET
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
L/S-Band RLNA Bill of Materials
L/S-Band RLNA _Layout
Quantity
Schematic ID
Value
Part Number
8
NE3509M04_v124
8
18-nH
18-nH
18-nH
18-nH
18-nH
18-nH
18-nH
18-nH
18-nH
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
12-pF
68-Ohm
68-Ohm
68-Ohm
68-Ohm
68-Ohm
100-Ohm
100-Ohm
100-Ohm
180-Ohm
180-Ohm
180-Ohm
4.3-pF
4.3-pF
4.3-pF
8
4
2
2
2
Manufacturer
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
NE3509M04
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
L-07C18NXV4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
250R07C120XX4
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ680
ERJ2GEJ101
ERJ2GEJ101
ERJ2GEJ101
ERJ2GEJ181
ERJ2GEJ181
ERJ2GEJ181
250R07C4R3XX4
250R07C4R3XX4
250R07C4R3XX4
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
NEC Devices
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Johanson Industries
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
Johanson Industries
Johanson Industries
Johanson Industries
114
Package Type
M04
M04
M04
M04
M04
M04
M04
M04
M04
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
402
R1005
R1005
R1005
R1005
R1005
R1005
R1005
R1005
R1005
R1005
R1005
402
402
402
Description
FET
FET
FET
FET
FET
FET
FET
FET
FET
Inductor
Inductor
Inductor
Inductor
Inductor
Inductor
Inductor
Inductor
Inductor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Capacitor
Capacitor
Capacitor
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