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A Microwave Phased Array with
Variable and Controllable
Magnitudes and Phases
Paul R. Aiken
Submitted in partial fulfillment of the
requirements for the degree
of Doctor of Philosophy
in the Graduate School o f Arts and Sciences
COLUMBIA UNIVERSITY
2004
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UMI Number: 3120655
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Abstract
A Microwave Phased Array with Variable and
Controllable Magnitudes and Phases
Paul R. Aiken
This thesis describes the design and
construction o f a computer
controlled 1 GHz phased array device. The device is capable of varying and
controlling the phases and magnitudes of its output RF signals over a range
of 360 degrees and 30 dB, respectively. This device could be used for the
experimental verification of a newly proposed concept of electromagnetic
radiation from an array o f patch antennas.
The design, construction and testing of a 3 x 4 phased array driver is
presented.
It
uses transmission line phase
shifters and voltage-variable
attenuators to achieve the desired phase and magnitude
variations. The
results obtained from various tests of this device are not consistent with its
design specifications and was therefore replaced by another phased array
design that uses a different architecture.
The new device is designed to drive a 4 x 4 patch antenna array. Its
design, construction, and measurements are presented. A single driver is first
designed and
its architecture is applied to the design o f a 16 channel
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computer-controlled 1 GHz phased array driver. This device is capable of
varying and controlling the magnitudes and phases of its output RF signals.
The
outputs
are
computer
controlled
and
accuracy
is maintained
by
comparing feedback phase and magnitude values with pre-calibrated ones.
Any desired relative phase shift may be obtained at the outputs with up to 30
dB o f magnitude variation, having an accuracy of ± 5° and ± 0.5 dB,
respectively. Its 16 channels consume 20.4 watts of power from a 17 Vdc
supply.
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Table of Contents
1.
2.
Introduction
1
1.1
Project conceptualization
............................................................
3
1.2
Thesis overview ..............................................................................
5
Phased array antenna systems
7
2.1
Types o f phased array ...................................................................
7
2.2
Beam steering .................................................................................
9
2.3
Phase shifters .................................................................................
12
2.3.1
Analog implementation ..........................................................
2.3.1.1
15
Analog phase shifters .......................................................
15
Reflection type phase shifter ......................................
15
Transmission line type phase shifter ...........................
18
Active phase shifter using variable resonant circuit ... 22
2.3.2
Digital implementation ..........................................................
2.3.2.1
24
Digital phase shifters........................................................
25
Switched-line ...............................................................
25
Switched filter ..............................................................
26
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2.4
Microstrip patch antennas ..............................................................
27
2.4.1
Analysis techniques for microstrip arrays ............................. 28
2.4.2
Mutual coupling ....................................................................... 33
2.4.3 Patch element design ...............................................................
34
2.4.4 Feeding methods ........................................................................ 35
2.4.5
Array configuration design .....................................................
36
2.5 Summary ............................................................................................... 36
3.
A New Concept for Radiation from Patch Antenna Arrays and the
Requirements for Practical Implementation
3.1
3.2
New concept of radiation from patch antenna arrays...................
39
39
Requirements for practical implementation .................................. 41
3.2.1
Printed circuit boards ..............................................................
41
PCB substrates ...................................................................... 42
3.2.2
Microstrip transmission line ...................................................... 43
Realization of micro strips .................................................... 45
3.2.3
Stripline ....................................................................................
3.2.4
Slotline ...................................................................................... 48
3.2.5 Coplananar line ..........................................................................
47
50
3.2.6 Impedance matching and the Smith ch art................................. 52
3.2.7 Practical tools for microwave circuit design ...........................
Artwork ........................................................................................
55
55
Schematic capture and layout ................................................... 56
Passive micro strip components ...............................................
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57
Lumped components ................................................................ 58
Soldering ...................................................................................
59
3.3 Choice o f design .............................................................................
59
4. A 3 x 4 Phased Array Antenna Device
61
4.1 Device architecture .........................................................................
61
4.2 RF input signal splitter ...................................................................
64
4.3 Phase shifter ....................................................................................
65
4.4 Antenna driver circuit .....................................................................
68
4.5 Parallel port driver ..........................................................................
71
4.6 Computer interface board ..............................................................
71
4.7
The controller program ..................................................................
74
4.8
PCB designs ...................................................................................
74
4.9 Measurements and results ..............................................................
76
4.10
80
Conclusion ...................................................................................
4.10.1
A complete redesign ...........................................................
5. Design Stages of a Single Antenna Driver
Voltage variable phase shifter .......................................................
5.1
5.1.1
5.2
Test circuit .....................................................................................
81
83
84
85
5.1.2
Test setup .................................................................................
86
5.1.3
Measurement and discussion .................................................
87
5-bit Digital attenuator ....................................................................
88
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5.2.1
Test circuit .............................................................................
89
5.2.2 Test setup ................................................................................
90
5.2.3 Measurements and discussion ...............................................
91
Phase and gain comparator ..........................................................
93
5.3
5.3.1
General Description of the AD8302 Integrated Circuit ....
93
5.3.2
Test circuit .............................................................................
95
5.3.3
Test setup ...............................................................................
96
5.4.4
Measurements and discussion ...............................................
98
5.4 RF directional coupler ..................................................................
5.4.1 Test setup and measurement ...................................................
5.5 Single antenna driver.....................................................................
100
101
102
5.5.1
Architecture .........................................................................
102
5.5.2
Test setup ...........................................................................
105
5.5.3
Results and discussion ..........................................................
105
5.6 Conclusion .....................................................................................
108
6. Design and Construction of a 4 x 4 Phased Array
109
6.1
Architecture of the 4 x 4 phased array ...................................... 109
6.2
RF distribution network ............................................................. 114
6.3
The antenna design .....................................................................
6.3.1
115
Tuning the patch antennas ....................................................... 116
6.4
Board designs and device construction ....................................
117
6.5
The 4 x 4 phased array device ...................................................
123
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7.
6.6
The antenna probe ......................................................................
125
6.7
The controller program .............................................................
126
6.8
Conclusion ..................................................................................
129
Device Specifications, Calibration and Test Measurements
7.1
Device characteristics ...............................................................
131
7.1.1
Determination of input signal power ................................
7.1.2
Total power consumption ..................................................
136
7.2
Calibration ...................................................................................
136
7.3
Setting the outputs ....................................................................
139
7.3.1
Setting output magnitude ...................................................
145
7.3.2
Setting output phase ...........................................................
146
Measurements and results ......................................................
148
7.4.1
Testing with 50 ohm terminators connected to theoutputs
148
7.4.2
Testing with the Antennas connected tothe outputs ............ 153
7.4
7.5
8.
131
Measurement with the RF probe ............................................
133
155
Compensating for Mutual Coupling
156
8.1
Coupling between two patch antenna elements.....................
157
8.2
Compensating for magnitude and phase variations................ 159
8.2.1
Compensating for magnitude variations............................ 160
8.2.2
Compensating for phase variations..................................... 161
8.3
Measurements and results.........................................................
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161
8.4
9.
Conclusion.................................................................................
Conclusion
9.1
164
165
Future work ............................................................................... 169
Bibliography
171
A.
176
The Controller Program
VI
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List of Figures
2.1
Phased array types: (a) Conventional (b) Adaptive ...............................
8
2.2
Linear phased array ..................................................................................
10
2.3
Spherical coordinate system for planar array .........................................
11
2.4
Frequency characteristics of a true phase shifter: (a) Insertion phase; (b)
Relative phase shift; (c) Group delay ......................................................
2.5
13
Frequency characteristics of a true delay line: (a) Insertion phase; (b)
Relative phase shift; (c) Group delay.......................................................
14
2.6
Generic reflection topology of the analog building blocks ..................
16
2.7
Equivalent circuit o f a section o f a lossless transmission line .............
19
2.8
(a) Schematic o f a distributed phase shifter circuit, (b) Equivalent circuit
for the varactor diode load line; (c) Synthetic transmission line with
voltage dependent characteristic impedance (Zt(V)) and phase velocity,
V p h a se (V )
........................................................................................................ 20
2.9
Circuit configuration of active phase shifter .......................................... 22
2.10
Schematic diagram of a switched-line delay line ................................... 25
2.11
A conventional switched-filter phase shifter .......................................... 26
2.12
Rectangular patch antenna ........................................................................ 28
2.13
Measured and calculated input impedance of an aperture stacked
micro strip antenna ....................................................................................
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32
2.14
Feeding methods for patch antenna elements: (a) Probe feed; (b)
Miscrodtrip-line feed ...............................................................................
35
2.15
Microstrip transmission line quarter-wave impedance transformer .... 36
2.16
Microstrip array configuration: (a) Series feed; (b) Parallel feed; (c) Row
fed by opposite phases and orientations .................................................
3.1
37
Assumed field pattern for two adjacent patch antenna elements with
V, > V 2......................................................................................................... 40
3.2
(a) Microstrip geometry; (b) Field pattern in microstrip ....................... 44
3.3
Field pattern in strip line ........................................................................... 47
3.4
Slotline: (a) Cross-sectional view; (b) E field pattern; (c) H field pattern 49
3.5
Coplanar waveguide on a finite thickness dielectric substrate .............. 51
3.6
Example o f impedance points on the Smith c h art................................... 54
4.1
Block diagram o f phased array device .................................................... 62
4.2
RF divider network..................................................................................... 65
4.3
Transmission line analog phase shifter (a and b),(c) Characteristic curve of
varactor diode............................................................................................
66
4.4
A single driver circuit schematic ............................................................
69
4.5
I2C-Parallel Port Driver ........................................................................... 71
4.6
Computer Interface .................................................................................
4.7
Pictures o f some of the PCB boards constructed for the device: (a)
72
Distribution board (top); (b) Distribution board (bottom); (c) Parallel port
driver; (d) Computer interface board (top); (e) Computer interface board
(bottom); (i) Antenna driver circuits ....................................................
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75
4.8
Plot o f relative phase and magnitude versus varactor bias voltage with
attenuator control set to 0 Volts................................................................. 77
4.9
Test setup for phase and magnitude measurements ................................ 78
4.10
Different views o f pictures o f the completed device .............................. 79
4.11
Phase (bold line) and magnitude (thin line) versus control voltage for two
MIC phase shifters connected in series.....................................................
81
5.1
(a) Schematic o f voltage variable phase shifter (b) constructed module 85
5.2
Test Setup for phase shifter module ........................................................
5.3
Polar plot o f relative phase shift with gain variation ............................
5.4
(a) Schematic o f attenuator test circuit (b) constructed module ........... 90
5.5
Attenuation versus bit setting .................................................................. 91
5.6
Functional block diagram o f the AD8302 ............................................. 93
5.7
(a) Schematic o f phase and gain comparator test circuit (b) PCB layout (c)
86
87
Constructed module .................................................................................. 95
5.8
Test setup for comparator module ........................................................... 97
5.9
(a) Vphs versus relative input phase (b) Vmag versus relative input
magnitudes................................................................................................... 98
5.10
(a) Symbolic representation of directional coupler, (b) inverting coupler,
and (c) non-inverting coupler.................................................................... 100
5.11
Architecture o f single antenna driver circuit ........................................ 103
5.12
(a) PCB o f single channel, and (b) Single channel prototype ..........
5.13
Magnitude plots (a) Comparators Vmag output versus attenuation and (b)
Attenuation versus attenuator control bit settings................................
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104
106
5.14
Relative phase plots: (a) With op amp saturation (b) Without op amp
saturation .................................................................................................
107
6.1
Functional block diagram of 4 x 4 phased array ...................................
110
6.2
Distribution o f SDA and SCLI2C bus lines ........................................
113
6.3
RF Distribution Network ........................................................................
114
6.4
Center fed patch antennas ......................................................................
115
6.5
Setup for tuning patch element ..............................................................
117
6.6
Layout o f antenna driver circuits, board l o f 4 ...................................
118
6.7
Modifications to channel 1 ....................................................................
119
6.8
Input distribution board: (a) Bottom layer (when viewed through the top
layer); (b) Top layer ..............................................................................
6.9
120
Top distribution board: (a) Bottom layer (viewed from top);
(b) Top layer ........................................................................................
122
6.10 (a) Multiplexer board; (b) Variable regulator board .............................. 123
6.11
The 4 x 4 phased array: (a) Not encased; (b) Encased withantennas
connected ................................................................................................
124
6.12 Antenna probe: (a) Illustration; (b) Actual probe; (c) Probewith RF and
6.13
DC line feeds .......................................................................................
125
Flow chart o f controller program .........................................................
128
6.14 An example o f a GTK+ window with horizontal and vertical scales
129
7.1
RF path through the device ....................................................................
134
7.2
Plots o f magnitude and phase calibration values for channels 2 and 6: (a)
Magnitude and phase plots for channel 2 calibration values; (i) Magnitude
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feedback versus relative output magnitude; (ii) Phase feedback versus
relative output phase; (b) Magnitude and phase plots for channel 6
calibration values; (i) Magnitude feedback versus relative output
magnitude;
(ii)
Phase
feedback
versus
relative
output
phase.
........................................................................................................................ 138
7.3
An example o f the input X-window ...................................................... 142
7.4
Test results for Channel 2 relative to the reference:
(a) Input magnitude versus its measured output (b) Inputphase versus its
measured output......................................................................................... 150
7.5
Test results for Channel 2 relative to the reference:
(a) Feedback magnitude versus its measured output; (b)Feedback phase
versus its measured output................................................................
7.6
152
Screen shot o f input and output phase and magnitude measurements with
all antennas connected. The dotted lines are drawn in to show each input
(small block) output pair for the corresponding channel number (in
parentheses)...............................................................................................
8.1
154
Magnitude and phase deviations at the antenna connected to channel 2
whenever the magnitude and phase o f its adjacent antenna is varied in steps
o f 5 dB and 45 degrees, respectively: (a) Magnitude is varied over 30 dB
while phase remained fixed at 0°; (b) Magnitude is fixed at 18 dB while
phase is varied over 360°; (c) Magnitude is fixed at -10 dB while phase is
8.2
varied; (d) Magnitude is varied while phase is fixed at 180°................
158
Flow chart o f program algorithm for setting output values..................
160
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List of Tables
3.1
Examples o f impedances normalized to a 50 Q termination and their
reflection coefficient as measured from the Smith chart
in Figure 3.7............................................................................................
55
3.2
Capacitor power loss/disspation at 500 MHz .....................................
57
5.1
Truth table for 5-bit digital attenuator ................................................
88
7.1
Discrete component characteristics at room temperature .................
132
7.2
RF gain for each stage .........................................................................
135
7.3
Magnitude and phase calibration values for channel 6:
8.1
(a) Magnitude calibration values;.......................................................
140
(b) Phase calibration values ...............................................................
141
Deviation measurements while setting the outputs...........................
162
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Acknowledgments
I would like to thank my advisor, Professor Paul Diament, for his
continuous guidance and encouragements. When our funding was discontinued
and all seemed lost, he managed to redirect the project so that it survived on
negligible funding. I also want to express my sincerest gratitude to Professor
Yannis Tsividis, whom I consider to be my second advisor, for his continuous
advice and willingness to help. He was very instrumental in securing some small,
but well-needed funds from the Electrical Engineering Department, to assist us in
securing components for our final design.
I am very thankful to Professor Ann McDermott of the Department of
Chemistry, for granting me unlimited access to her laboratory workshop facilities,
particularly for the continuous loan of her network analyzer, handsaws, drills, and
many other well-needed tools. I must also thank her past and present graduate
students, Alex, Tatyana I, Tatyana P, Sharon, Ben, Nick, Stephan, Justin, Tijana,
Krisztina and Lei, for rearranging their lab schedules to accommodate my many
instrument loan requests. Thank you all.
I would like to thank Dr. John Decatur, my immediate supervisor in the
NMR facility o f the Chemistry Department, for allowing me to exercise great
flexibility in carrying out my job duties. This made it possible for me to combine
work and study.
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I am very grateful to my friend and colleague, Kirk Spence, for all his
assistance in the development of the device programs. His unwavering patience
and understanding helped me to build a solid foundation in C programming.
Many thanks to Sanjeev Ranganathan for his assistance in installing the GTK Xwindow program. I would also like to thank him and the other members of
Professor Tsividis research group for making their laboratory resources available
to me, particularly for the loan o f a 1 GHz signal generator.
My many PCB constructions and micro-soldering would not have been
possible without the help of John Kazana, the undergraduate laboratory manager
in the EE Department, who made the resources o f the EE lab available to me.
Many thanks to the administrative staffs of the Electrical Engineering
Department, Marlene Mansfield, Elsa Sanchez, John Baldi, Lourdes de la Paz,
Betsy Arias, and Azlyn Smith for their assistance over the years.
I thank my wife, Michele and my daughter, Samanthia, for their
continuous love, support and understanding. I also thank my brother, Kenneth for
his continuous interest in my well being and progress.
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To my wife, Michele
who made it possible
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1
Chapter 1
Introduction
Phased array antennas are formed from a collection o f basic antennas,
each o f which is called an antenna element or, simply, an element. The antenna
element may be o f any of the following types: horn, helix, yagi, dipole,
microstrip, slotted waveguide, or parabolic reflector (dish). These elements are
also referred to as discrete radiators or receivers. During standard operation o f a
phased array each element is individually excited. In general, the excitation of an
array is achieved by having a defined or discrete amplitude and phase at each
element. This discrete distribution is often called aperture distribution, where the
discrete array is the aperture [1].
The principles o f phased arrays were first applied to radar technology
during World War II. Theoretical and technological advances were made in the
nineteen-fifties and early sixties. However, their practical application did not start
until late in the sixties and seventies, following the development o f fast phase
shifters and the application o f computer technology to phase control. The early
application o f phased array to radar was tremendously expensive. However, the
development o f integrated circuits (ICs) and much faster and more powerful
computers has significantly lowered the developmental cost of phased array
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2
systems. Phased arrays have also driven the development o f microwave
monolithic integrated circuits (MMIC) since its ultra-small microstrip antennas
may be easily integrated into standard microwave chip packages.
Today, phased array antenna systems are increasingly being used in
wireless and satellite communications networks, smart weapons, automobile and
airplane radar, and radio astronomy. There are two main reasons for its growing
popularity: (1) its beam steering ability, sometimes referred to as “beam agility,”
and (2) its use o f microstrip antennas. Beam agility is particularly useful in radar
when there are multiple simultaneous scanning functions to be performed. It
replaces the much slower mechanical adjustments. Beam steering is achieved by
linearly varying the phase between adjacent elements of an antenna array [2].
Phase variations may be achieved by either varying the operating
frequency [3], or by using electronic phase shifters with a fixed operating
frequency [4, 5]. Variation o f the operating frequency is highly undesirable and
very uncharacteristic o f today’s transceivers. Recently, phase shifters using
photonic band gap techniques have been successfully implemented [6].
Most
phased array systems in use today implement electronic phase shifters.
Microstrip antenna technology has undergone very rapid development
over the past twenty years and has been successfully applied to personal
communication systems (PCS), wireless local area networks (WLANs), direct
broadcast television, intelligent vehicle highway systems, and many other areas
where the application o f phased array systems are desired. Although they have
proven to be a significant advance in the field o f antenna technology, it is their
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3
non-electrical characteristics that make microstrip antennas preferred over other
types o f radiators. Micro strip antennas have low profile and are light in weight.
They can be made conformal and are ideally suited to integration with microwave
integrated circuits. The characteristics of microstrip antennas, particularly the
patch antenna, and its application to phased array systems will be further
discussed in Chapter 3.
1.1
PROJECT CONCEPTUALIZATION
A special application requires the design and implementation of a phased
array antenna device that is capable of performing beam steering and scanning at
microwave frequencies, and must have a very small beam-angle resolution. The
device must be as small as technologically possible. This means that its circuits
must be integrated wherever possible. Such integration requires the use of
monolithic microwave integrated chip technology. Because of their ease of
integration, microstrip patch antennas were the obvious choice o f antenna
elements.
The requirement for small beam-angle resolution had led to an intense
literature search on the present state o f the art in microwave phase shifters and the
theory o f radiation from patch antennas and antenna arrays. Many phase shifter
circuits were investigated and are described in Chapter 2. During the literature
search on radiation from patch antennas, we discovered that all the theoretical and
practical implementation o f patches are based on the assumption that radiation
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4
only occurs from the edges of the patch elements, and that mutual coupling
between adjacent elements was undesirable.
During an in-depth analysis of the electromagnetic radiation from patch
antennas in an array, it was discovered that there is a significant amount of
radiation caused by mutual coupling between the patches [7]. This is in total
contradiction to conventional theory that is being taught in many major
microwave antenna textbooks and antenna handbooks [2], [8]-[12], and thus
requires rigorous theoretical and experimental verification.
In the conventional phased array systems, the antennas are driven by a
fixed-frequency signal o f fixed amplitude and variable phase. The variable phase
is required for beam steering, while the fixed amplitude creates negligible
differential voltages between antenna elements. In the newly proposed radiation
concept, all methods o f increasing mutual coupling are highly encouraged. This
means that the antenna elements (patches) must be driven differentially.
This caused the project to be divided into two main parts. Part 1 was
assigned to be a theoretical analysis of the electromagnetic radiation from patches
due to their mutual coupling, leading to the actual design o f a patch antenna array
with 50-ohm input impedance. The other part was assigned as the design and
construction o f a device that would provide controlled signals to these patches.
Such a device requires as many channels as there are antenna elements and each
channel must offer variable and controllable output magnitudes and phases. Over
360° o f relative phase shift with less than 1° o f resolution, and a minimum of 30
dB o f magnitude variation were required.
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5
An initial market search was done for the availability of any such device
either in chip form or otherwise. No such device was found. This was expected,
however, since there was no previous application that requires simultaneous
variation in magnitudes and phases, especially having a 360° phase shift range
with a resolution o f 1°.
This thesis describes the work done in fulfilling the task o f the second part
of the project. It outlines the design, construction, calibration and testing of a
microwave phased array driver with variable and controllable phases and
magnitudes. The device is designed to operate at a frequency o f 1 GHz because of
the availability o f test equipments and low-cost discrete microwave components.
A summary o f the design and testing o f this device is published in the IEEE
Transaction on Microwave Theory and Techniques [13].
1.2
THESIS OVERVIEW
Chapter 2 gives an overview o f the basic structure o f a phased array
system and how beam steering is achieved. Various types of microwave phase
shifter circuits are presented with the view of applying one of them to the design
of the device. Some o f the properties o f microstrip patch antennas are also
outlined.
A very brief overview of the proposed new concept of radiation from
patch antenna arrays is presented in Chapter 3, along with the requirements for
designing a microwave phased array device that we hope to used to test this new
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6
concept. Here, an overview of basic microwave circuit design techniques is
presented.
The design, construction and testing o f a 3 x 4 phased array antenna that
uses transmission line phase shifters is presented in chapter 4. The performance of
this device did not meet the required specification, so a new designed was
required. Chapter 5 outlines the design, construction and testing of the stages
leading up to the design of a single channel of a phased array driver.
The successful tests o f the single channel led to the design o f a 4 x 4
phased array device. Its design details are outlined in Chapter 6. Chapter 7 is a
report o f its characteristics, calibrations and measurements. The technique used to
compensate for the effects of mutual coupling between the patch antenna
elements is described in Chapter 8. Finally, a discussion of all the designs and
results is presented in Chapter 9, along with suggested future applications.
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7
Chapter 2
Phased Array Antenna Systems
This chapter will examine the basic structure of phase arrays systems and
two o f its major components: phase shifters and microstrip antennas. Two main
types o f phase shifter designs are presented: analog and digital. The analysis,
design, and application o f microstrip patch antennas are outlined. Because phased
arrays are mainly designed for application at microwave frequencies, all antennas
and circuit designs must follow strict microwave design rules, especially for
impedance matching, antenna efficiency and power consumption. Some of these
design rules are addressed in Chapter 3.
2.1
TYPES OF PHASED ARRAYS
There are two main types of phased arrays; namely, the fixed and the
adaptive beam-forming networks. Figure 2.1 compares a conventional satellite
transmitter using fixed beam-forming networks with a solid-state transmitter
using adaptive beam forming [1],
The conventional phased array in Figure 2.1(a) consists o f a single high
power amplifier transmitting through a beam-forming network into individual
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8
Antenna
Feeds
Power
Amplifier
Fixed Beam-Forming Network
(a)
PA
Phase Shifter
Attenuator
Phase Shifter
Attenuator
Phase Shifter
Attenuator
[X
Antenna
Feeds
Adaptive beam-forming network
Figure 2.1
Phased array types: (a) Conventional (b) Adaptive
antenna feeds. A traveling-wave tube (TWT) amplifier may be used for such high
power applications and has been successfully used on major communication
satellites. The beam-forming network is required to shape the transmitted beam. It
is usually made from carefully designed waveguide plumbing for really high
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9
power application. These systems are quite large and their nonlinear power
amplifiers have limited reliability and lifetime.
The adaptive phased array system in Figure 2.1(b) has a cascade of
variable phase shifters, attenuators and fixed power amplifiers driving each
antenna.
Since each antenna has its own feed network, much smaller power
amplification is required, facilitating the use of solid-state amplifiers. This means
an improved lifetime and reliability, low voltage supplies, and excellent linearity.
In addition, there is a large degree o f redundancy in the arrangement. Since the
phase and amplitude o f the signal at each antenna are individually controlled the
antenna beam can now be steered electronically. In radar systems, this means that
the beam can be steered electronically very quickly and can track fast moving and
multiple targets in a fashion that is impossible with traditional rotating-dish
radars.
2.2
BEAM STEERING
Before discussing the components of the phased array, let’s pause for a
minute to discuss how beams are actually steered. It is because o f this ability that
phased arrays are attractive alternatives to existing aperture-type systems. Beams
are formed and steered by applying complex weights to each element within the
array. Conventionally, steering is achieved by variation in the phases o f the
antenna driver signals, while keeping the amplitudes fixed. A simple view of how
beam steering is achieved may be obtained by investigating how the signals are
received in the array [1].
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10
Figure 2.2 shows a one-dimensional, phased receiving array. It consists of
a line o f antenna elements with common spacing d. The inter-element distance is
typically one-half the wavelength. Each element drives a phase shifter, the outputs
of which are summed to form the input to the receiver. The plane wave arriving at
incident
beam
antenna
elements
phase
shifters
to receiver
Figure 2.2
Linear phased array
angle Go from the array normal travels a distance that increases incrementally by
dsmOo to each successive element. The phase shift across the array due to the
plane wave is kndsin&o, where nd defines the element location. The function of
the bank o f phase shifters is to compensate for this linear phase progression across
the array. The phase shift for a source at angle do to the normal and at distance po
is:
= - k nd sin 0Q-
n d
/,
2 7
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(2.1)
11
The same principle applies for a two-dimensional array. However, as shown in
Figure 2.3, a polar geometry is now used and the plane-wave arrives from
direction d o and
where d o and (/>o are the beam pointing angles [14].
array.
*>y
Figure 2.3
Spherical coordinate system for planar array
In this case the required phase correction is:
= - k ndx sin dQcos^0 + md sin d0 sin (f>{) -
n 2d l + m 2d 2 ^
(2 .2)
2 Po
where n and m are the element indices along the x and y axes, and the inter­
element spacing along these axes are dx and dy respectively. The quadratic terms
in Equations 2.1 and 2.2 are necessary when the source is in the near field.
For most pencil-beam applications, the array excitations are symmetric
[14], so that the pattern given by summing over only half the elements along each
axis is:
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12
N/2M/2
F ( u , v ) = Y a Y j A ™ C0S
n =1 m - 1
(
n ----o kd ru cos m ----- kd y v
I
2;
I
2;
f
X
(2.3)
where u and v are direction cosine plane variables:
u = sin 9cos<f> - sin 90 cos^0,
(2.4)
v = sin 9 sin ^ - sin 0Osin <j>0.
The inter-element phase shifts needed to scan the beam are:
<E>„ = kdxu0 = kdx sin 0Ocos^0,
(2.5)
O v = k d v Q= kd sin 6>0 sin
.
For a phased array the beamwidth and gain can be estimated from the
number o f elements. With the elements spaced by half-wavelengths to avoid the
generation o f grating lobes (multiple beams), the number of radiating elements N
for a pencil beam is related to the half-power (or 3 dB) beamwidth by
N & 10,000/(0 BW)2 , where 0BW is the half-power beamwidth in degrees. The
corresponding antenna array gain is G « rj7tN, where rj is the efficiency.
2.3
PHASE SHIFTERS
A phase shifter is simply a device or circuit that varies the phase of its
output signal with respect to its input. There are two main generic types o f phase
shifters; (1) the true phase shifter and (2) the true delay line [15]. A true phase
shifter may be defined as a control device that has a flat group delay frequency
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13
response within its defined bandwidth o f operation. It has a flat relative phase
shift frequency response at all levels of relative phase shift. Because of its
constant group delay, the timing o f an input RF pulse will not change. These
frequency characteristics may be expressed in the graphs o f Figure 2.4.
co
Relative*
Phase
shift
0
Insertion
phase
CO
(b)
Reference
Groupf
delay
0
(a)
(C)
CO
Figure 2.4
Frequency characteristics of a true phase shifter: (a) Insertion
phase; (b) Relative phase shift; (c) Group delay
True phase shifters are usually employed in multiple space diversity
receiver-combiners for aligning RF signals within a pulse envelope without
changing the timing o f the pulse edges. However, when applied to wideband
beam-forming networks for large phased array antennas, a significant amount of
phase squinting and pulse stretching occurs. Phase squinting is the discontinuity
in small ranges o f phase values.
A true delay line or time shifter, may be defined as a control device that
has a flat group delay frequency response within its defined bandwidth of
operation, and whose level changes with its insertion phase. As a result, the
timing o f an input RF pulse envelope changes as well. It also has a linear relative
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14
phase shift frequency response with a gradient that changes as the value o f the
relative phase shift varies. Its frequency characteristics are illustrated in Figure
2.5. The true delay may be expressed as:
Ar = AZ‘M ^
co
(2.6)
where AZ S U(co) is the relative phase shift at co, and co is the angular frequency.
0
©
Relative,
phase
shift
reference
Insertion
phase
►
CO
(b)
referem
Group
reference
delay
“►co
(a)
(C)
Figure 2.5
Frequency characteristics o f a true delay line: (a) Insertion phase;
(b) Relative phase shift; (c) Group delay.
True delay lines are mainly used in general microwave signal processing
applications, such as beam-forming networks for large-aperture phased array
antennas. It must be noted that when the non-idealities o f the circuit elements are
included in the design, an ideal true phase shifter circuit may have the frequency
characteristics o f a true delay line, and vice versa. These phase shifters may be
implemented by analog or digital means.
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15
2.3.1 Analog Implementation
When compared with a purely digital implementation, analog control
phase shifters have the following advantages:
1. They require only one control wire per device.
2. No special foundry processes are required to realize high quality switches.
3. Can produce less that 1 degree of resolution.
4. They require very little control power since most of their circuits are
generally passive.
5. They do not suffer from quantization errors.
6. Since the phase variation is continuous, any degradation in performance
attributed to fabrication process variation or adverse conditions can be easily
corrected.
7. Calibration corrections can be performed after integration into a system.
As a result o f these significant advantages, analog control devices are ideal for
large adaptive phased arrays and high performance microwave signal processing
applications. Analog phase shifters are ideal for applications that require less than
one degree o f resolution.
2.3.1.1
Analog Phase Shifters
Reflection Type Phase Shifter:
The basic topology of a single stage reflection type phase shifter [16], [17]
is shown in Figure 2.6. For simplicity, the directional coupler is assumed to be
lossless, perfectly matched, and to have infinite isolation.
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16
3 dB quadrature
directional
Innut Port
7 -o
4 Couplet^
Iso lated Po^t
•irect Port
S 4
■ Port ^ ^ 2
L.
identical reflection terminals
Figure 2.6
Generic reflection topology o f the analog building blocks
The operation of the coupler may be expressed analytically as:
S » = P r K
(2.7)
+s;,
where S u is the input reflection coefficient of the control device; p T is the
voltage reflection coefficient of the reflection termination;
voltage transmission coefficient o f the coupler, and
is the coupled
is the direct voltage
transmission coefficient o f the coupler.
It can be seen from Eq.(2.7) that if there is an equal power split and phase
quadrature between the coupled and direct ports, then the voltage wave emerging
from the input port will have zero amplitude. Whenever this happens, the input
and output impedance will be perfectly matched. Also,
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17
$2\ - 2Sclxp TSlx
( 2 .8)
where S 2] is the forward voltage transmission coefficient o f the control device.
Eq. 2.8 indicates that thevoltage wave emerging from the isolation portwill have
its amplitude equal to that of the one entering the input port, resulting in zero
insertion loss. The insertion phase o f the control device may be written as:
zs2l =zsc2i+zPr+zs;,
(2.9)
When quadrature coupling is maintained the expression becomes:
Z S 2 l= Z p T + 2 Z S I +90°
(2.10)
and with an ideal quarter wavelength transmission line coupler, it becomes
(2 . 11)
Z S 2X = Z C + 90 . 1 - 2
7o0 /
where / is the frequency and /„ is the center frequency.
The voltage reflection coefficient, p r , of the reflection termination is:
/
Pt
/
0
(2 . 12)
Z j + Z§
and
Z j —RT + j X j
(2.13)
where Xr = X/, + Xc, and X L = coL, the reactance of the inductor and X c
-1
----- ,
(oC
the reactance o f the capacitor. Zo is the reference input impedance. So:
r R2t ■z 0 + x ;
\Pt \
(R .+Zj+X 2
+
2 Z0X T
\2
U r t + z J + x ':t j
and,
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(2.14)
18
Z -P T — tan
'IZ qX j
-l
( r t + z 0)2 + x T.2
(2.15)
It can be seen from Eq. (2.15) that by varying the values of L and C, hence
X t,
up to 90° o f phase shift may be obtained. A true wideband analog 180° phase
shifter with low phase error performance and constant group delay may be
implemented using two cascaded-matched reflection-type phase shifters [18].
360° phase shift may be achieved by cascading four 90° blocks.
The more traditional single stage reflection topology o f Figure 2.6 is not
an ideal phase shifter because its phase error performance is usually very poor
across wide frequency ranges. As a result, group delay can vary significantly for
different levels o f relative phase shift. By using Lange couplers with capacitive
reflection terminations a level o f phase error proportional to the bandwidth may
be achieved [19].
Transmission Line Type Phase Shifter:
The phase velocity vp, of a transmission line is:
v' =
^
(Z 1 6 )
where L and C are its distributed inductance and capacitance. These values are
obtained from the equivalent circuit model for a lossless transmission line shown
in Figure 2.7.
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19
Figure 2.7
Equivalent circuit o f a section o f a lossless transmission line
Each transmission line has characteristic impedance Zo, of
z . = ^
(2-17)
The values o f L and C depend on the physical and electrical properties of the
transmission line. Based on the equivalent circuit model, it is possible to vary the
phase velocity o f a transmission line by loading it with evenly-spaced capacitors.
A change in phase velocity means a change in the relative phase o f the input and
output signals. If voltage-variable capacitors (varactors diodes) are used, the
output phase may be made to vary with the bias voltage of the varactors [20], In
the linear (small signal) regime the diode-loaded line behaves like a synthetic
transmission line with voltage-variable phase velocity and can, therefore, be used
as a time-delay/phase-shift element [21], [22].
The distributed phase shifter circuit, shown in Figure 2.8(a), is comprised
of a high-impedance (Z,) transmission line periodically loaded with varactor
diodes (Cvar) spaced lsect apart. A unit cell of this periodic structure is defined as
that section o f the transmission line indicated by length lsect and includes a shunt
variable capacitor to ground. Lt and Ch in Figure 2.8(b), are lumped
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20
z,, V
(a)
Ct
Lt
Lt
Lt
4 * Cvar(V)
Ct;
4* cvar(v)
Ct -
tF
Cv
(b)
Z,(V),
vphase(V)
L to ta l
(C)
Figure 2.8
(a) Schematic o f a distributed phase shifter circuit, (b) Equivalent
circuit for the varactor diode load line; (c) Synthetic transmission line with
voltage dependent characteristic impedance (Z/,(V)) and phase velocity, vPhase (V).
approximations o f the inductance and capacitance within one unit cell. The
periodically loaded line may be treated as a synthetic transmission line, as
illustrated in Figure 2.8(c). The capacitance per unit length has been increased due
to the periodic capacitive loading, while its inductance remains unchanged. Since
the loading capacitors are voltage dependent, the characteristic impedance and
phase velocity o f this synthetic transmission line are also voltage dependent. This
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21
means that the phase shift can be made to vary with voltage. This is the essential
principle behind the distributed phase shifter circuit. Its impedance and phase
characteristics may be approximated as:
(2.18)
1
^ phase
(2.19)
where
L, = — , and C, = —
v,
Z,v,
(2.20)
The line inductance, Lj, and the line capacitance, C), are normalized to unit length.
The varactor capacitance will vary from a maximum to a minimum value with a
certain range o f applied bias voltage. This means that the line impedance and
phase will vary from a maximum to a minimum value. If Z/ is set to be 50 ohms in
the maximum capacitance state, then
Z t = 50Vl + x
(2 .21)
and x, the loading factor is:
max
c ;var
X =
/
c,
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(2.22)
22
This indicates that for larger loading factors, the unloaded line impedance must be
higher in order to ensure 50-ohm impedance when the line is loaded. At any
given frequency f
the maximum possible differential phase shift that may be
obtained from a single section is:
5 (j) = I t #
I.
v,
Cl
■ s/l + x —
1+ X
V
y-rmax
var
(2.23)
J
The number o f sections, nsect, required for 360 phase shift at frequency /is :
n,.
2n
5(j)
(2.24)
Active Phase Shifter using Variable Resonant Circuit:
Figure 2.9 shows the circuit configuration o f an active phase shifter [23].
C2
03
C5
11
r
-<
Input
>-
I
C3
Q1
HI— C
jO utput
Q2
1
Z ,'02
parallel resonant circuit
Figure 2.9
Circuit configuration o f active phase shifter
FETs Q1 and Q2 are cascaded and have a parallel Lk, Ck, Rk circuit inserted
between them. Q3 is connected in parallel to Q1 and Q2. If the FET equivalent
circuit is assumed to be a combination o f transconductance (gm) and the gate-to-
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23
source capacitance, Cgs, all having the same cut off frequency, f r = g J2 nC zs, then
the admittance matrix for the circuit may be written as:
Yn ( s ) = ~
4 ^ .
+ C g*3 ) + ( g m1 + g m3 )
Yn (s) = d - = 0
1
gm\g m2 _ J
g, „3
Y2l(S) = y
R
= -gm 3
s2+
1
k
1
(2.25)
1
^ + c ^ ) I + i T ? ', + c I,3
The condition that only the phase may change while the amplitude remains
constant even with change in central angular frequency is expressed as:
1
1
2q
— = — , therefore, Rk = Sm3
g m\gm2
g m3
g m j , g m 2,
R k
R k
(2.26)
gm \gm l
and g m3 are the transconductances of FETs Qi,
Q 2,
and
Q 3,
respectively.
The magnitude may be expressed as:
2 -g»
M
g ml
=
+
1
jZoiZo
(2.27)
gn
\ 2
f
\ 2
J
\ a T
J
+ z„
01
g m l + g m2
where
o>T = 27cfT =
= the cutoff frequency.
The phase relation is:
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24
COj
tan
AS
—
^ 01
A—
&ml
co
- 2 tan 1
+ z 01
R, V1
S m3
(2 .28 )
(‘ .
Thus for a fixed Rr, the phase may be varied by varying the value o f Cr and/or Lr.
Additionally,
Z01oc
input
impedance
matching
may
be
achieved
by
setting
1
Sm\ "t"
2.3.2 Digital Implementations
The primary goal in the design of multi-bit digital phase shifters is to meet
the required relative phase shift for each discrete phase change, across the desired
frequency range. Good input and output return losses are required in order to
avoid ripples in the insertion phase and insertion loss responses when they are
cascaded with other components such as attenuators and amplifiers. Moreover,
good impedance matches are required for each individual phase shifter stage (or
bit), in order to minimize inter-stage reflections.
There are four main types of digital phase shifters. They are switched-line,
reflection-type, loaded-line, and switched-filter. The reflection-type and loadedline digital phase shifters are very similar to their analog counterpart. However,
instead o f having fixed loads with varying impedance, they employ switched load
techniques [15].
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25
2.3.2.1 Digital Phase Shifters
Switched-line:
A simplified switched-line phase shifter is illustrated schematically in
Figure 2.10. Pin diodes or switching MESFETS [24], [25] are used to route the
input RF signal into an appropriate length of matched transmission line. Ideally
the amount o f induced group delay is directly proportional to the difference in the
physical lengths o f the selected line and the reference line. This approach is more
accurately described as a switched-line variable delay line.
Delay lines
In
Out
o-
Switch control
Figure 2.10
Schematic diagram of a switched-line delay line
This type o f purely digital implementation can achieve a very wide
bandwidth, but the size o f its implementation is dependent on the center
frequency o f operation and the number o f bits.
The satisfactory operation of a single-pole double-throw switch (SPDT) is
essential for the performance of the variable delay line. A resonating inductor is
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26
usually placed between the drain and the source terminals of the switching-FET,
in order to tune out the off-state drain-source capacitance [26].
Switched-filter:
A conventional switched-filter phase shifter is illustrated in Figure 2.11.
Two SPDT switches are used to switch the RF signal path between a high pass
filter and a low-pass filter. For this reason, this approach is also known as a highpass/low-pass phase shifter. This technique is similar to that o f the switched-line
phase shifter but with the transmission lines replaced by filters.
RF o u t
RF i n
J“ ° .
Figure 2.11
A conventional switched-filter phase shifter
A low-pass filter consisting of series inductors and shunt capacitors provides
phase lag (or delay) to signals passing through it. Likewise, a high pass filter
consisting o f series capacitors and shunt inductors provides phase lead (or
advance) to signals passing through it. Both filters are matched for insertion loss
at the operating frequency but have different insertion phases. Therefore, when
the signal path is switched between the two filters the desired change in insertion
phase may be achieved without any significant change in insertion loss. The
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27
bandwidth o f this phase shifter depends on the characteristics o f the two filters
and the SPDT switches.
When implemented in ICs [27]—[31], the overall chip size of the switchedfilter phase shifter is considerable smaller that o f an equivalent switched-line,
reflection type or loaded-line implementation, because the long distributed
transmission lines are replaced by much smaller lumped elements. For this reason
it is the most popular type of MMIC phase shifter for low microwave frequency
application.
2.4
MICROSTRIP PATCH ANTENNAS
Microstrip patch antennas are widely used in military, space, and
commercial applications. They offer outstanding performances relative to other
antennas [32]-[34], as they are highly efficient, structurally compact, have a low
profile and conformability, and low manufacturing cost. In spite o f these
advantages, patch antennas suffer serious drawbacks because they have small
bandwidth (generally less than 5 %), relatively high feed line loss, and low power
handling capability. To minimize these effects, accurate analysis techniques,
optimum design methods, and innovative array concepts are used for successful
development o f microstrip array antennas.
Figure 2.12 shows a typical rectangular patch antenna with width W and
length L over a grounded dielectric substrate with dielectric constant er. Ideally,
the ground plane on the underside o f the substrate is o f infinite extent. Normally
the thickness o f the dielectric substrate, h, is designed to be < 0.02Xg, where Xg is
the wavelength in the dielectric.
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28
Microstrip patch antenna
h
Metal ground plane
Figure 2.12
Rectangular patch antenna
2.4.1 Analysis Techniques for Microstrip Arrays
Flexible, accurate and computationally efficient analysis techniques are
necessary for antenna array designs in order to replace the costly and timeconsuming experimental cut-and-try design techniques. This type o f analysis also
provides a more complete understanding of the antennas’ operation and can aid in
optimizing their performance or determining their limitations.
The majority o f microstrip arrays are designed as fixed-beam broadside
antennas, often with the feed network located coplanar with the array element
because o f its simplicity and low design cost. The design procedures normally
involve element design, array layout and spacing, and feed design. Consideration
must be given to bandwidth and polarization specifications when designing
radiating elements. The grid layout, the number, and the spacing of the array
elements are determined by the required principal plane beamwidths, or the gain,
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29
o f the array. The feed network is a function o f the amplitude tapers required for
the sidelobe specification, impedance matching to the elements, and the array
bandwidth. It may take the form o f a series feed or corporate feed. In the design o f
fixed beam microstrip arrays, mutual coupling is normally ignored and the
elements and their excitation are treated as if they were isolated.
The design and analysis of scanning phased microstrip arrays (adaptive
arrays) also requires rigorous and versatile CAD software. Such antennas are
usually very expensive because of the phase shifter and/or transmit/receive
module cost per element, so it is critical that antenna performance be analyzed
and optimized thoroughly and accurately. Accurate CAD models provide
information on important effects such as scan blindness, impedance mismatch,
losses, random errors, sidelobe levels, and cross-polarization as a function of any
design parameter. Unlike fixed beam arrays, scanning array analysis requires the
inclusion
o f mutual
coupling
and
feed
network
effects
for
complete
characterization o f the array.
Microstrip patch antenna analysis is complicated because of the presence
of the dielectric inhomogeneity, a narrow-impedance bandwidth characteristic,
and a wide variety o f patch, feed, and substrate configuration. Analysis models
are either categorized as (a) simplified (or reduced) analysis that maintain
simplicity at the expense of accuracy and versatility, or (b) full-wave models that
maintain accuracy and rigor at the expense o f computational efficiency.
Reduced analysis methods include (a) the transmission line model [35][38] and (b) the cavity model [35], [36], [38]-[40]. The transmission line model is
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30
based on the fact that rectangular patches are simply very wide transmission lines
terminated by the radiation impedance. This model can only make approximate
predictions about the properties, since its core formulas were derived from
approximation in microstrip transmission line characteristics or empirically fit
data. The cavity model assumes the rectangular patch to be essentially a closed
resonant cavity with magnetic walls. This model can make very accurate
predictions, but only at the expense o f an inordinate amount of computer effort.
These models were the first to be developed for microstrip antennas and
have proven to be very useful for practical designs as well as providing an
intuitive explanation for the operation of the microstrip element, particularly for
those that are probe-fed and line-fed. They generally give good results for
antennas on thin, low-dielectric-constant substrates. However, the inclusion of
multi-layer substrate requires more rigorous analytical techniques.
The increase in computer power has led to the development o f more
powerful analysis techniques by applying finite element and finite difference time
domain (FDTD) methods. Such methods are very versatile and are becoming
available in CAD packages. One such technique is the full-wave moment method
of analysis, which involves the use of the exact Green’s function for the dielectric
substrate. This technique enforces the boundary conditions at the air-dielectric
interface and accurately accounts for the contributions o f space waves, surface
waves, dielectric loss, and coupling to external structures. The conducting patch
elements may be replaced with equivalent electric surface currents derived from
the equivalence theorem. This enforces the continuity of electric fields at the
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31
patch elements and leads to the derivation o f a moment method solution. The
fields from these current elements are found using the exact Green’s function for
the substrate geometry [36], [38], The most critical step in this procedure is the
evaluation of the impedance matrix elements having the general form
1i}= J J 11 LLJi(x’ ^ •'G{k*’ky) J1(x° ’ y°)e~JkAx~X
o)
x; T,- Xj yj
(2.29)
•e~jky(y~n) dk ydk xdy 0dx0dydx
where ./, and J, are the expansion and test mode currents, and G is the dyadic
Green’s function for the substrate geometry. This six-fold integration involves
surface wave poles, a slowly converging integrand, and singularities associated
with the source point. Its evaluation requires great attention to details.
One method o f analysis o f Eq. (2.29) is to take the Fourier transform of
the expansion and test modes. The rectangular spectral variables kx and ky are
transformed
to
polar
coordinates,
fi
and
a , where
kx - /?cosar and
ky = (3 sin a. Eq. (2.29) now reduces to
Z» =
J
l F , ( k „ k , ) G (k „ k y) F ,( k x,k y)dad/)
(2.30)
which is in a convenient form for numerical evaluation. However, there is still a
surface wave pole associated with the TMo surface wave [41].
Alternatively, the spectral variables in Eq. (2.29) can be transformed to
polar form, and the a integration done in closed form, to yield:
z * = [ J . f . f f . J i (x, y) ■H (x, y, x0, y 0,fi)- J j (x0, y 0)d/3dy0dx0dydx
*t y>xj yj
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(2.31)
32
This is normally referred to as the space domain approach because o f the
remaining integrations over the space coordinates. Several efficient numerical
techniques for integrating over f3 are given by Mosig, et al. [42]. Recent work in
this area has focused on the mixed potential approach [43], which expresses the
Green’s function in a form that facilitates the evaluation of the source singularity
terms.
Impedance - Measured
-o - Impedance - Calculated
F1 = 16 GHz
F2 = 26 GHz
dF = 1
Figure 2.13
Measured and calculated input impedance of an aperture stacked
microstrip antenna. (From reference 44)
An example o f the measured and calculated input impedance of an
aperture-coupled stacked microstrip antenna element operating at K band [44] is
shown in Figure 2.13. The analysis o f this antenna involves the treatment of three
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33
dielectric layers, a ground plane, two rectangular patches, and a coupling slot. The
calculated impedance locus is in good agreement with the measured data.
2.4.2 Mutual Coupling
Mutual coupling effects are generally negligible on microstrip arrays
because the antenna elements are normally mounted on electrically thin, grounded
substrate. This is also the primary reason for their narrow impedance bandwidth.
However, there are many cases where the mutual coupling effect is significant
and therefore, must be accounted for. Some of these cases are scanning phased
arrays, arrays on electrically thick substrate, arrays with main beams far off
broadside, and arrays that have elements at different voltage. Coupling was
actually measured for some o f these cases [45]. Generally, coupling increases
with substrate thickness and dielectric constant. The presence of a cover-layer
over the antennas also increases their mutual coupling. Mutual coupling analysis
is best done using the full-wave moment method.
A general method for including mutual coupling in array design is to treat
the N-element array as an N-port network and use microwave network theory to
find the element amplitudes, phases and the input reflection coefficients for
various excitations. Thus, for an N-element array, having N feed ports fed with
matched voltage generators, V}, the reflection coefficient at the j th port can be
expressed as:
s ,v '
r , =
j
i= l
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<2-32>
34
where Sy is the scattering parameter between the ith and j th elements. In the
absence o f mutual coupling, where Sy = 0 for i ^ j (a diagonal scattering matrix),
Eq. (2.32) reduces to:
r .j = -y+
^ = S au
v(2.33)'
which is the expected result for isolated elements.
2.4.3 Patch Element Design
Patch antenna elements have many different shapes. They may be
rectangular, square, circular, annular ring, triangular, pentagonal, and a square or
circular with perturbed truncations. These different shapes are often used to meet
various challenging requirements. For example, the rectangular patch, used for
linearly polarized applications, can achieve slightly wider bandwidth than the
square or circular patch. However, the square or circular patch, unlike the
rectangular patch, can be excited orthogonally by two feeds to achieve circular
polarization. In some cases, this may be achieved with just a single feed.
For the fundamental mode rectangular patch, the first-order design
equation [46] is given by:
c
/ =
(2.34)
where f is the resonant frequency, c is the speed of light, L is the patch resonant
length, h is the substrate height, and eeff is the effective dielectric constant
(explained in Chapter 3, section 3.2.2).
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35
This expression is accurate to within 2 %. More accurate results may be
obtained by using full-wave analysis techniques.
2.4.4 Feeding Methods
Patch antennas can be fed in many different ways [47]. Figure 2.14 shows
the probe feed and microstrip-line edge feed methods. Probe feed and microstripline edge feed are the most common feed methods. The probe feed method is
simple and is generally applicable to discrete systems, while the edge feed method
is more attractive from a fabrication point of view.
Patch element
Coaxial cable
(a)
(b)
Figure 2.14 Feeding methods for patch antenna elements: (a) Probe feed; (b)
Miscrostrip-line feed.
Impedance matching on the probe feed element is generally achieved by
placing the probe off-center [14]. A microstrip transmission-line quarter-wave
impedance transformer, shown in Figure 2.15, may be used to match the
microstrip feed element to its feed circuit. Zi,
Z2 =
Z 2
and
Z 3
can be calculated from
x Z3 .
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36
Z i
Z 2
Z 3
1
----------------------- 1
Figure 2.15
Microstrip transmission line quarter-wave impedance transformer
2.4.5 Array Configuration Design
It is critical to lay out the most suitable array configuration for a particular
application as the first stage of designing a phased array system. Viable array
configurations include series-fed or parallel-fed [48]-[50], hybrid series/parallel
[51], single layer versus multiple layer, with variables such as substrate thickness,
dielectric constant, array size, patch element shape, element spacing, etc. The
selection o f the configuration depend on the desired antenna gain, bandwidth,
insertion loss, beam angle, grating/sidelobe level, polarization, power handling
capability, and other considerations.
Figure 2.16 shows sketches o f different array configurations.
2.5
SUMMARY
A review o f phased array systems and its major components has been
presented. Beam steering o f the emitted beam is achieved by controlling the phase
of the signal at each antenna element, while the received beams are summed inphase before reaching the receiver circuits.
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Patch element
(a) Series feed
(b) Parallel feed
0°
180 '
180 '
(c) Row fed by opposite phases and orientations
Figure 2.16
Microstrip array configuration
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38
The design and analysis o f analog and digital phase shifters have also been
discussed. The basic design principles of three main types of analog phase
shifters, namely reflection type, transmission line type and active design using
variable resonant circuits, have been compared to that of their digital counterparts.
Analog phase shifters require only one control line and can produce less that 1
degree o f phase shift. On the other hand, digital phase shifters may be easily
integrated into standard IC fabrication processes.
A review o f microstrip patch antennas was also presented. Their design
and analysis may be done using one o f two techniques: the reduce method or the
full wave method. The reduced method provides intuitive understanding and uses
approximations to calculate the various antenna parameters, while the full-wave
method is more o f an exact analysis requiring extensive computer effort. The
effect o f mutual coupling between the elements of a phased array has been
mentioned. A simple first-order design and various feed techniques for patch
antennas were also discussed. Finally, some examples of array configurations
were briefly presented.
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39
Chapter 3
A New Concept for Radiation from Patch
Antenna Arrays and the Requirements for
Practical Implementation
3.1
NEW CONCEPT FOR RADIATION FROM PATCH
ANTENNA ARRAYS
A new concept for electromagnetic radiation from microstrip patch
antennas has been proposed by P. Diament [7]. It has long been presumed that
microstrip patch antennas can only radiate from their edges. As such, many offcenter feed techniques have been developed to optimize this edge radiation. Offcenter feeds create higher order transverse electromagnetic modes (TEM) and
reduce signal cancellation by neighboring antennas. In patch antenna arrays, as
applied to phased array systems, each patch is normally fed from separate variable
phase and fixed magnitude control circuitry. Variations in excitations introduce a
high level o f mutual coupling between the patches, significantly degrading the
efficiency o f the antenna array. Many techniques have been developed to
overcome this problem [45].
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40
In the newly proposed concept, mutual coupling is encouraged and
exploited. The actual radiation from the patch elements is created from the
displacement current along the coupling field lines. By feeding the elements with
signals of different magnitudes, high levels of mutual coupling are achieved.
Other methods o f increasing coupling are the use of electrically thick substrate,
high dielectric constant, and placing a cover-layer over the antenna elements.
Figure 3.1 shows the coupling fields that exist between two adjacent probe-centerfeed patch elements.
Coupled E fields
Air
Ground plane
Probe feeds
to center of patch
element
Figure 3.1.
Assumed field pattern for two adjacent patch antenna elements
with Vj > V 2 .
Theoretical results show that there is a significant amount of radiation
generated from the coupling fields of patch antennas. An array of N patch
elements exhibits N(N-l)/2 radiators that mutually couple the N patches.
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41
3.2
REQUIREMENTS FOR PRACTICAL IMPLEMENTATION
A method o f testing the above concept was required. Such a test requires
the design o f a small phased array device with variable and controllable phases
and magnitudes at each o f its patch antenna elements. The relative phase must be
variable over a 360° range with less that 1° o f resolution, and a 30 dB range was
acceptable for magnitude variations. The actual design and construction of this
device is the task o f this thesis and is thoroughly outlined in subsequent chapters.
However, this is a device operating at microwave frequencies, and as such,
requires special microwave design techniques. For example, at 1GHz, a track on a
printed circuit board (PCB) becomes a transmission line with characteristic
impedance, Z0.
The rest o f this chapter will attempt to highlight some o f these design
requirements. We will start by examining the copper clad printed circuit board
and its behavior at high frequencies, followed by a discussion of planar
transmission lines, and impedance matching using the Smith chart. The method
by which PCBs are generally made for microwave circuits is also outlined. Then
finally, we will present a design concept for a small phased array system.
3.2.1 Printed Circuit Boards
The most basic printed circuit board has one side of a dielectric material
coated by a single layer of a conducting metal, usually copper. The required
circuit pattern is etched within the metal and components are mounted from the
other side o f the board. This design is suitable for DC and very low frequency
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42
applications. At microwave frequencies, an additional ground plane is usually
required. This plane is normally placed on the other side of the dielectric material,
making a double-sided metal-clad board. The type o f dielectric material used
depends on the application o f the PCB.
A standard PCB that is cheap and easily available is made from FR4 (fiber
reinforced grade 4) dielectric material. It has a relative dielectric constant of 4.5 at
1 GHz. It’s important to state the frequency since, at microwave frequencies, the
dielectric constant depends significantly on frequency [52]. Standard boards are
1/32-inch or 1/16-inch thick with a single or double-sided copper layer. The
actual amount o f the copper is measured in ounce and the standard is ‘A ounce or
1 ounce. Our design for 1 GHz application will use double sided copper clad
PCBs with
ounce copper.
There are four main types o f transmission lines that are generally made on
PCBs. They are the microstrip, stripline, slotline and the coplanar line. These are
called planar transmission lines.
PCB Substrates:
Substrates used in microwave circuit designs require special properties
that are not found in the more popular printed circuit boards such as FR4. Normal
substrates lack the mechanical and electrical characteristics required for reliable
microwave operation and circuit fabrication. Over the years material research into
microwave substrates has led to the development of high quality substrates with
the following properties:
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43
1.
2
low loss tangent;
. uniform dielectric contstant;
3. extremely flat sheets;
4. no post etch warpage;
5. good peel strength;
6
. high batch uniformity
7. inert to chemicals;
8
. high mechanical strength;
9. easily machined, cut and drilled;
10.
very small variation in board thickness;
11.
long term stability;
12.
high heat resistance.
Some o f the more popular brand names of microwave substrate are
RT/Duroid, Oak, Rexolite, Polyguide, Epsilam, Superstrate and CuFlon. Substrate
dielectric constants range from 2.1 (CuFlon) to 10.3 (Epsilam) and are available
over a wide range o f thickness.
3.2.2 Microstrip transmission line
Microstrip is one o f the most frequently used planar transmission line
because o f the ease with which components may be mounted on its structure, and
its ease o f fabrication and integration. The microstrip geometry and crosssectional field patterns are shown in Figure 3.2.
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44
Microstrip pattern
D ielectric er
Ground plane
(a)
E
(b)
Figure 3.2
(a) Microstrip geometry; (b) Field pattern in microstrip
This transmission line consists of a dielectric substrate that has a ground
plane on one side and a strip pattern on the other, hence the name microstrip. Note
from Figure 3.2(b) that the electromagnetic field distribution is asymmetrical. The
lower half is contained between the strip and the ground plane, while the upper
half radiates into the air. Although this feature is exploited in microstrip antennas,
radiation and its associated losses are considered a drawback of microstrip. Most
of the electromagnetic energy may be confined to the vicinity of the microstrip if
the dielectric constant o f the substrate is high, and the whole circuit is enclosed in
a grounded metal casing. Mathematical analyses of microstrips are very difficult
because o f the mixed dielectric media (air and the substrate). For the same reason,
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45
the microstrip line cannot support a pure TEM wave, since the phase velocity of
TEM fields in the dielectric region would be c j J i T , and that in air would be c.
Thus a phase match at the air-dielectric interface would be impossible to achieve.
In actuality, the exact fields o f the microstrip line constitute a hybrid TM-TE
wave, and require more advanced analysis techniques [53]-[55].
Realization of Microstrips:
The characteristic impedance, Zo, of a microstrip depends on its substrate
dielectric constant, sr, and thickness, h, and on the line width, w. In most practical
application, Zo, sr and h are given and w must be determined. Because the
dispersion o f narrow lines is much greater than that of wide lines, two sets of
equations are frequently used to achieve reasonable accuracy in line width
determination [56], One set is used for so-called narrow line where the w/h ratio is
small, and the other set is used for wide lines with large w/h ratios. Because of the
dispersion characteristics, related to the two dielectric media, an effective
permittivity, seff is used in microstrip calculations, where 1 < seff < er. This
effective dielectric constant is generally expressed as:
s.
£*ff ”
e -\
+1
—
+
—
----------
The phase velocity and propagation constant are now given as:
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Q.2)
46
phase
Cff
(3.2)
P = ktj
eff
Given the dimensions o f a microstrip line, the characteristic impedance can be
calculated as:
r
60
In
/ 8h + w}
\ w Ah j
for w/h < 1
(3.4)
Z„ = <
120x
w
+ 1.393 +0.667 In
+ 1.44
h
h
for w/h > 1
\
For a given characteristic impedance, Zo, and dielectric constant sr, the w/h
ratio can be found as:
r
8e'
for w/h <2
e2A - 2
W /
(3.5)
K
B - 1 - ln(25 - 1)+
- Jln(5 - 1)+ 0.39 - —
2e„
s.
for w/h > 2 ,
where
60 V
B
2
0.23 +
f f , +l v
0.11
21171
22^0
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47
Apart from the w/h ratio, a microstrip line may be considered narrow when
Zo > (44 - 2er), and wide when Zo < (44 - 2er) [56].
3.2.3 Stripline
A stripline is a three-conductor transmission line and looks like a
sandwich. The central strip is embedded in a dielectric substrate between two
ground planes, as shown in its field pattern sketch in Figure 3.3. The stripline is
thus enclosed in a symmetrical structure with literally no radiation loss. As
attractive as this is, it becomes very difficult, if not impossible, to mount surface
mount components.
Figure 3.3
Field pattern in strip line
Any drilling o f holes or other recesses would affect predicted stripline circuit
performance.
Striplines are ideal structures for passive circuits such as filters, power
dividers and couplers. They operate in TEM mode with seff = sr due to the
uniform dielectric filling. Its characteristics impedance is found from the line
capacitance using conformal mapping [57], [58]:
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48
30n K (k)
(3.6)
V^7 * ( * ')
where
k' = tanh^"
w
2b
K(k)/K(l'{) can be approximated by the following expressions:
\+ 4 k
*< * > .= I * , 2 +
K (k ') n
i -V *
K(k')
n
-In
1+ sfk''
for 0.7 < k < 1
(3.7)
for 0 < k < 0.7
(3.8)
1- V F
K(k) represents the complete elliptic integral of the first kind and K(j/) is its
complementary function. Other characteristics of striplines, such as losses, can be
found elsewhere [59], [60].
3.2.4
Slotline
Slotline can be considered as the dual o f microstrip line. It is usually used
as a complement to microstrip by providing a circuit on the microstrip ground
plane. Figure 3.4 shows a cross sectional view and field pattern of the slotline. It
is a non-TEM uniplanar transmission line and is usually etched into a dielectric
supported layer without a backside ground plane.
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(C )
Figure 3.4
pattern
Slotline: (a) Cross-sectional view; (b) E field pattern; (c) H field
There are two empirical expressions for its characteristic impedance [59],
[61] and they both depend on the value o f the w/h ratio.
For 0.02 < w/h < 0.2:
/ h
(3.9)
X
and for
0 .2
11.4-2.636 In e,
< w/h <
1 .0
:
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50
Z0 = 113.19 —23.257 In
+1.25 w
/ h (l 14.59-22.531 In s r)
(3.10)
- [0.15 + 0.1 In er + w/h ( - 0.79 + 0.899 In er )]
x{l0.25-2.1711n£r + w /h { 2 \.- 0 .6 n \n e r) - h / A 0 xlO 2]2}
where
hjA0= 0 . 2 5 / - 1 .
The impedance of a slotline increases with its slot width. Therefore,
slotlines are very useful in circuits requiring high-impedance lines, series stubs,
short circuit ends, etc. It is usually very difficult to make high impedance lines in
microstrip. Since the two slotline conductors he in one plane it offers itself for
shunt mounting o f microwave components. The most suitable location for
mounting any component is governed by the electromagnetic field configuration
along the slot. Slotlines may be combined with microstrips and coplanar lines for
many circuit applications. This type of hybrid combination allows a great deal of
flexibility in MIC and MMIC designs.
3.2.5 Coplanar Line
Coplanar Line, or more popularly called coplanar waveguide (CPW),
shown in Figure 3.5, consist of three metal conductors in one plane. The two
ground planes run parallel to the microstrip center conductor. The coplanar line
combines some o f the positive features of microstrip and slotline structure.
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51
2
b
Ground plane
Ground plane
Figure 3.5
Coplanar waveguide on a finite thickness dielectric substrate
If the width o f the dielectric substrate is assumed to be infinite, then the
quasistatic parameters o f this transmission line are [62]:
30n K (k )
^ 7
K(k)
(3.11)
e r - \ K( k ' ) K{kx)
2 K(k) K(k[)
where
k' =
i t - - -
k~bt
sinh
ky =
sinh
V l- k 1
CUT
V2b
'b i t '
\!a j
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52
where 2 a is the width and 2b is the separation of the ground planes, as shown in
Figure 3.6. The values for K(k)/K(k;) and K( kl) / K ( k /)a re already given in
Eq.(3.6) and (3.7).
3.2.6 Impedance Matching and the Smith Chart
In RF and microwave circuits there is always the need to match the
different impedances o f the interconnected blocks, such as amplifiers to antennas,
filters to amplifiers, VCOs to mixers, etc. Matched components are required for
proper transfer o f signal and energy from the “source” to a “load”.
At microwave frequencies, the spurious elements,
such as wire
inductances, parasitic capacitances, etc, have a significant impact on the matching
network. Whenever theoretical calculations and simulations are insufficient, RF
lab measurements, along with tuning work, are considered for determining the
proper circuit values.
Some o f the ways used to achieve impedance matching are computer
simulations, manual computations, instinct, and the Smith chart. Computer
simulations are complex and may not be accurately modeled for microwave
frequencies. Because o f their usefulness in the design of microwave ICs, more
accurate models are always being sought. Manual computations are just too
tedious and extremely time consuming; just look at some of those equations used
to calculate characteristics impedances (see sections 3.2.2 to 3.2.5).
Instinct can be acquired only after many years o f devotion to the RF
industry. In short, this should be left to the specialists in the field. The Smith chart
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53
method, however, rules supreme; it is still considered the basic tool for
determining transmission line impedances. Although there are other impedance
and reflection charts that are used to solve transmission line problems [63], the
Smith chart is probably the best known and most widely used.
P. H. Smith invented the Smith chart in 1939, while working at Bell
Laboratories. It is a graphical representation of the impedance transformation
property o f a length of transmission line, and as such avoids tedious
computations. Besides being an integral part of computer aided design (CAD)
software and test equipment for microwave design (for example, the network
analyzer), the Smith chart provides an extremely useful way of visualizing
transmission line phenomena. A microwave engineer can develop intuition about
transmission line and impedance matching by learning to think in terms of the
Smith chart.
The Smith chart is essentially a polar plot o f the voltage reflection
coefficient, T. The reflection coefficient may be expressed in a magnitude and
phase (polar) form as T = \T\e!e. A plot can be made of the magnitude as a radius
(|T| < 1 ) from the center o f the chart, and the angle
0
(-180° <
0
< 180°) is
measured from the right-hand side of the horizontal diameter. Any passively
realizable reflection coefficient may then be plotted as a unique point on the
Smith chart.
The Smith chart can be used to convert from reflection coefficients to
normalized impedances (or admittances), and vice versa, using the impedance
circles printed on the chart. The impedances measured on the Smith chart are
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54
normalized values. The normalization constant is usually the characteristic
impedance o f the transmission line. Thus z = TJZo represents the normalized
version o f the impedance Z. Some examples of this are shown on the Smith chart
in Figure 3.6. Impedances Z\ to Zg are normalized with respect to a 50-ohm
terminating load and are shown in Table 3.1.
V*.
Jz
Figure 3.6
Example of impedance points on the Smith chart
Look carefully at the values of Z\ and
Z 3
with respect to
Z 2
and
Z g
and
compare their respective representations on the Smith chart. Note that Z\ and
are located in the upper half o f the circle, while
half.
Z i
and
Z 2
Z 2
and
are inductive values (+j terms) while
Z g
Z 3
Z 3
are located in the lower
and
Z g
are capacitive (-j
terms). From this, it is immediately seen that net inductive impedances will be
displayed in the top half o f the Smith chart, while net capacitive impedances will
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55
Table 3.1
Examples of impedances normalized to a 50 Q termination and
their reflection coefficient as measured from the Smith chart in Figure 3.7.
Impedances
Zi
=
100
+
j 50
Q.
zi =
T 1 = 0.4 + 0 .2 j
2 +j
T 2 = 0.51 - 0 . 4 j
a
Z3 = j4
r 3 = 0.875 + 0.48j
Q
Z4 = 3
r 4 = 0.5
z5
8
r 5= 1
Z6 = 0
r 6 = -i
z7 =l
r7= o
Q
<N
0
0
II
N
Z4
=
150
Z5
=
oc (open circuit)
(short circuit)
Z 7 =50
Reflection coefficients
z2 = 1 .5 -j2
Z2 = 75 -jlOO
Z& = 0
Normalized impedances
Q
=
a
0
0
•'—,
1
00
OO
II
N
Z 8=
3.68
—
jl 8 S
T 8 = 0 .9 6 - 0 .1 j
be displayed in the bottom half. Purely resistive values like Z4 and
Z 7
are on the
horizontal line. These observations are very useful when tuning circuit elements,
such as an antenna. More information on using the Smith chart is given elsewhere
[63], [64],
3.2.7 Practical Tools for Microwave Circuit Design
Artwork:
Microwave circuit design, at least up to the X-band (8-12 GHz), is widely
used and the technology and production techniques are fairly well understood.
The high demand for microwave circuit designs has led to the development of
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56
advanced CAD tools and artwork. Originally, the drawings required for making
microwave circuits in planar transmission lines were done by hand. This, of
course, has many limitations, especially in making fine lines, narrow gaps and
repeatable designs. Eventually, CAD for microwave and their artwork generation
were coordinated in a commercial environment. Nowadays, artwork generation
for PCBs is usually automated and uses a fraction of the time that was required
for manual layout. Three main methods are used in the automatic generation of
artwork: coordinatographs, photoplotters and pattern generators [56].
Coordinatograph looks like an x-y plotter where the drawing pen is
replaced by a cutting edge. A computer controls the cutting pattern in films placed
on the base plate. In a Photoplotter, a light source directly exposes a film so that
the artwork pattern may be produced as x-y inputs to a controller computer. After
the exposure, the film is developed to give a negative that can be used to produce
microwave circuit patterns.
Pattern generators are similar to photoplotters and use a microprocessor as
a data base. Rectangular shapes of varying dimensions are directly flashed onto a
photo sensisitive glassplate to create a one-to-one size pattern. Pattern generators
are usually reserve for high-density artwork, such as those required for integrated
circuits. Today, very advanced lithographic techniques are used in the
construction o f microwave monolithic integrated circuits (MMIC).
Schematic Capture and Layout:
There are many circuit schematic and capture tools available. The most
popular ones used for microwave circuit designs are WaveMaker and Mircowave
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57
Office. Allegro and Oread from Cadence may also be used for low microwave
frequency schematic designs.
Passive Microstrip Components:
In order to optimize RF and microwave circuits, it is essential to choose
the appropriate active devices and passive components such as capacitors and
inductors.
For these applications, capacitors are best characterized in terms of their
dielectric loss or loss tangent, tan 8. These losses are due to the dielectric material
of the capacitor. The loss tangent, equivalent resistance, and heat generation all
increase with dielectric loss. Ideally, a loss tangent of zero is desired. On the other
hand, poor capacitor quality can result in overheating and circuit failure. To
illustrate this point, Table 3.2 compares the properties o f glass epoxy with
alumina capacitors, both having a 10 pF value and operating at 500 MHz.
Table 3.2
Parameter
Capacitor power loss/disspation at 500 MHz
Glass epoxy
Alumina
C
10 pF
10 pF
tan 8
0.05
0.001
20
1000
X50o = 1/ 271/C
32 Q
32 Q
Rdiss ='X500/Q
1.6
0.032
I
10mA
10 mA
P = I 2Rdiss
0.16 mW
3.2 uW
Q
- 1/tan 8
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58
Q is the quality factor, / is the current, P is the power dissipation, X is the
reactance at 500 MHz, and R is the resistance of the dielectric. It is easily seen
from the table that the lowest possible loss tangent value is normally preferable.
Chip capacitors are widely used in microwave circuits. Although they
have no leads, they still exhibit some amount of inductance by virtue of their
physical length. This creates self-resonance within the capacitor.
It is very
important to use capacitors whose self-resonance is far away from the operating
frequency o f the circuit, otherwise unwanted oscillations can occur. In some
cases, at extremely high frequencies, the equivalent circuit for the capacitor is
predominantly inductive, especially if it has a high quality factor, Q. In certain
circumstances a capacitor may be used as an inductive element. A capacitor
operating in this mode represents a low-cost high-Q inductor with an additional
advantage o f a built-in DC block, by virtue o f its capacitance.
Lumped Components:
In microwave circuits, a strip o f transmission line can be used to make a
capacitor or inductor. A straight section of wire or transmission line, especially if
its width is very small, will exhibit inductance. In the same way, a wide
microstrip will exhibit capacitance. The inductance for a straight copper track
may be approximated as:
\
(3.12)
/
where L is inductance in milli-Henry, and /, w, and t are the length, width and
thickness o f the track, respectively.
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59
Soldering:
A soldering operation requires that the parts to be soldered together be free
from any contamination. These contaminations are mainly from metal oxides and
finger oils. Handling the components with bare hands should be minimized and
gloves, plastic tweezers and finger cots should be used whenever possible.
During manual soldering, care must be taken not to overheat the components.
Proper soldering requires a lot of experience.
3.3
CHOICE OF DESIGN: Device Conceptualization
We decided to design a prototype 1 GHz phased array driver with the
capability to drive at least 12 or 16 patch antenna elements, making up a 3 x 4 or a
4 x 4 array. The patch elements must be fed from separate driver circuits that will
have variable and controllable phases and magnitudes. The phase must be variable
over 360° with at least 1° resolution, while the magnitude may be varied over 30
dB with 1 dB resolution. Because of limited financial resources the most cost
effective designs were sought.
The requirement of the phase shifter immediately dismissed the use of
digital phase shifters, since a 9-bit digital phase shifter would be required for 1°
resolution. Therefore, one of the three analog phase shifters presented in Chapter
2 was chosen for the design. Since the ultimate application of our design is at the
Ka frequency band o f 26 - 40 GHz, any circuit designs we use must be frequency
scalable to Ka band frequencies. Thus, the transmission line phase shifter was the
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60
ideal choice, since its dimension scales with wavelength. Also, it was relatively
simple to construct for 1 GHz application.
All circuits will be constructed on FR4 PCBs using both chemical etching
and machine milling techniques. Microstrip and coplanar transmission lines will
be used. As already discussed, FR4 is not ideal for microwave application and as
such, a higher percentage of signal loss will occur. This, however, is not
important at this time since we are only interested in the relative phase and
magnitude measurements at the antenna elements, and not its actual radiation.
Also, absolute magnitudes and power are not important at this stage. Similarly, no
special noise reduction or low noise techniques will be used.
The design, construction and testing of such a device is detailed in the rest
o f this thesis. The microwave design techniques outlined in Chapters 2 and 3 will
be used wherever possible.
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61
Chapter 4
A 3 x 4 Phased Array Antenna Device
This chapter describes the design, construction and testing of a 3 x 4
phased array antenna device. This device uses transmission line phase shifters to
provide a voltage variable 0 to 360 degree phase shift. A GaAs MMIC voltagevariable attenuator was used to provide over 30 dB range of attenuation. The
device was designed to operate at 1 GHz.
The performance of this device did not meet our required specifications;
therefore, only the essential design aspects are discussed. Another device, a 4 x 4
phased array antenna, was constructed and extensively tested. Its design and
measurements are outlined in later chapters.
4.1
DEVICE ARCHITECTURE
Figure 4.1 shows a block diagram of the phased array device. For clarity,
only one antenna circuit is shown. A 1 GHz input signal is divided into two sets
of
12
output signals o f equal magnitude by using one two way splitter followed by
two twelve way splitters. One set of the 12 output signals is used as the RF inputs
o f the antenna driver circuits while the other is used as the reference signal for
each o f the feedback circuits.
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62
12-Way
Splitter
1 of 12 RF Reference
1 GHz i/p
2 -W ay
Splitter
1 of 12 antenna driver circuits
\ 1
Variable
Attenuator
(0 - 30 dB)
Variable
Phase
Shifter
(0 - 360°)
12-Way
Splitter
Antenna
Fixed
Amplifier
Feedback from Antenna
Phase & Magn
Comparator
Phase
1-12
Computer
o/p f
Phase
Control
Ref
Magnitude
i-i:
f o/p
Magnitude
Control
8-Bit
ADC
8-Bit
ADC
Parallel Port
Driver
Computer Interface Board
Figure 4.1
Block diagram of phased array device
Each o f the 12 input signals to the antenna driver circuits gets amplified
by a fixed 15 dB linear amplifier, phase shifted by a voltage variable 0 to 360°
varactor loaded transmission line phase shifter, and attenuated by a 0 - 30 dB
voltage variable attenuator, before being applied to the antenna. A portion of this
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63
signal at the antenna is fed back into a phase-gain comparator circuit. Here, its
phase and magnitude are compared to those of the reference RF signal. Their
differences are indicated by a 0 - 1.8 Vdc voltage at the ‘phase’ and ‘magnitude’
output pins respectively. These voltages are converted to
8 -bit
digital signals by
the analog-to-digital converters on the computer interface board. They are then
sent to the computer via the inter-integrated circuit (I2 C) bus.
The phase control circuits of the computer interface board are used to set
the actual phases at the antennas. They do this by varying the dc bias voltages of
the phase shifters. The phase shifter circuits are designed so that a bias voltage
variation o f 0 to 10 volts produces a phase shift of 0 to 360 degrees. Similarly, the
magnitude control circuits o f the computer interface board control the amount of
signal attenuation. By varying the bias voltages of the voltage variable attenuators
from -4 to 0 Vdc, up to 30 dB signal attenuation is achieved. The actual bias
voltages sent out by the phase and magnitude control circuits are determined via
software.
Before operating the device, the desired relative phases and magnitudes
were entered into the computer program, written specifically to control this
device. This controller program is written in the C-programming language and is
installed under the LINUX operating system. The desired signals are sent through
the parallel port and parallel port driver to the computer interface board by use of
Phillips I2C BUS communication technique. The computer interface converts
these bus signals into the desired voltage value for the phase shifters and
attenuators. To ensure the correct phase and magnitude at each antenna, feedback
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64
dc signals from phase-magnitude comparators are compared against pre-calibrated
values (stored in the computer). These calibrated values were obtained from
actual measurements taken by a Hewlett Packard 1.2 GHz network analyzer.
A brief description of the design and operation of the individual stages of
the device will now follow. The circuit designs were done using discrete
components and low-priced integrated circuit chips bought from various
manufacturers. Before using these ICs, simple test circuits were built and used to
verily the manufacturers’ specifications. We discovered that the biasing of the
attenuator chip (as recommended by its manufacturers) for constant input and
output impedances did not work as specified, and modifications had to be made.
4.2
RF INPUT SIGNAL SPLITTER
Figure 4.2 shows the printed circuit board (pcb) layout pattern (not drawn
to scale) used to obtain equal magnitude (but not necessarily equal phase at
microwave frequencies) for the 1 GHz input and reference signals. Once the
spacing between the driver circuits inputs (and the references) was determined,
the signal points 1 to 12 were connected in the ‘H’ formation shown with 50-ohm
•
microstrips. These tracks were made 3.2 mm wide on a 1/16
th
inch thick FR4
circuit board (see Chapter 3 for calculations of track width).
Note that from the single input point, the signal travels the same distance
to each output point. Thus, the signal path losses are the same, making the
magnitude o f the signal at each of the outputs the same. It was later discovered
that this is an age-old technique used to distribute clock signals in digital
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65
integrated microprocessor circuits. O f course, in the low frequency applications,
the outputs were all in phase, as is required for synchronous clocking.
1
2
3
4
RF Input
Figure 4.2
4.3
RF divider network.
PHASE SHIFTER
A varactor loaded transmission line type phase shifter design was used. Its
schematic is shown in Figure 4.3(a) and 4.3(b). A full analysis of this type of
phase shifter was given in Chapter 2, section 2.3.2. Some o f its major design
features are outlined below.
Transmission lines may be modeled as a distributed network of
inductances and capacitances as shown in Figures 4.3(a) and 4.3(b). It has been
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66
Lsec t
Zi
ZL
VI
Zi
VI
Cvar
Cvar
Lt
Lt
JT Y Y V
VI
Cvar
Lt
J'YVV\_
Cfc -
c tC v a r (V)
ct ■
C v a r ('V'j
C v a r ('V;
(b)
Capacitance (pF)
10
ZM V 930
1
10
1
Reversed biased voltage (Vdc)
(c)
Figure 4.3
Transmission line analog phase shifter (a and b),(c) Characteristic
curve o f varactor diode.
shown [17] that if capacitors are placed at equal distances, lsech the maximum
possible phase shift per single section is
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67
S<f>=
(4.1)
- ^ + xy)
P
where
x=
max
p
i
sec /
max
Zi and vp are the unloaded impedance (no added capacitors) and phase velocity
respectively. Cmax and Cmm are the maximum and minimum values of the
capacitance loads. FR4 pcb has an approximate dielectric constant o f 4.5So at
1GHz making vp = 0.47c, where c is the speed of light.
The total number of sections required to realize a 360-degree phase shift is
= lo(p
r
(4 -2)
Values o f x, y and Lsect were chosen based on the tradeoffs in phase shift per
section (hence number o f sectors required for 360 degree) and line impedance
variations. Obviously we would like the impedance variations and the total length
of the transmission line to be as small as possible. But, smaller impedance
variations mean smaller phase change per section and longer transmission line.
Another factor in choosing ‘y ’ is the availability of discrete microwave voltagevariable capacitors (varactor diodes).
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68
The first stage o f the design involved sourcing a varactor diode that works
well at 1 GHz and requires a voltage control range of 0 to 10 Vdc. Such a large
voltage range will reduce phase errors due to small voltage fluctuations. The
ZMV930 silicon hyperabrupt variable capacitance diode was obtained from
Digikey Electronics. It has the characteristic curve shown in Figure 4.3(c.) Its
capacitance varies from 1.2 to 10 pF for a reverse bias voltage range o f 0 to 10
Vdc.
Such a large capacitance range makes iy ' very small thus increasing the
phase shift per section and reducing the length of the transmission line. It also
makes ‘x ’ very large, which drastically increases the variation o f the line
impedance with phase. So once again, tradeoffs are needed. By placing a 1.5 p F
capacitor in series with the varactor its capacitance range is reduced to 0 .67 p F to
1.3 p F making Cmax =1 . 3 p F instead o f 10 pF. Theoretically, this is good, but
may be very difficult to implement since these values may be comparable to the
parasitic capacitances o f the nearby tracks on the PCB board, x was chosen to be
15, Z l = 50 ohms, making Z, = 100 ohms. A 100-ohm micro strip transmission line
requires a track width o f 0.72 mm on the 1/16th inch thick, FR4 printed circuit
board (calculated from Eq. 3.5).
4.4
ANTENNA DRIVER CIRCUIT
Figure 4.4 is a schematic drawing o f a single antenna driver circuit (1 of
12). The 1 GHz RF input is coupled though capacitor Cl into a GAL-33 InGaP
HBT microwave amplifier. The amplifier has a gain o f 15 dB at 1 GHz when
biased with 12 volts dc across resistor Rbias. Its input and output impedances are
50 ohms. The amplified 1 GHz signal is fed through dc blocking capacitor C2 into
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69
the transmission line phase shifter. For our application, the trasmission line was
made 20 cm long at 0.72 mm wide (100 ohm line). C and Cvar form dc variable
capacitance loads and are spaced 1 cm apart. Inductors, L, acts as a RF choke, and
was chosen to be 1 uH. The parallel combination of L and C, which was already
chosen to be 1.5 pF, has a resonant frequency that is far away from our operating
frequency. The phase control voltage,
V Ph a s e ,
is connected to the transmission line
via Lp and Cp. Lp and Cp block the RF signal from leaking into the dc circuits.
R b ia s
12V
RF
Input
0.72 mm wide transmission line
GAL-33
L
RF 1 RF2
GNDGND
V2
VI
I
N/C
up to 20
attenuator
Vphase (set phase)
<ZD—
1
Vmagn (set gain)
Feedback Magnitude
100
<ZD—
M F IT
GNO
IN A
VMAG
MSET
0F S A
ohm s
- v / V ' ---------
T
VDD
VREF
Feedback Phase
100 ohms
---
<=>
OFSB
4=
PSET
VPHS
PFLT
INB
GND
Phase/Gain comparatoi
Figure 4.4
A single driver circuit schematic
After being phase shifted, the signal is attenuated by variable attenuator
HMC346 (from Hittite Semiconductor) and fed to the antenna. The biasing o f the
attenuator is such that its input and output impedances vary with its gain control
voltage, Vmag. Variable impedances are not desirable but it was the only working
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70
configuration we had for this chip. The suggested manufacturer’s op amp biasing
did not work.
Some o f the signal at the antenna is fed back into IN A (pin 2) of the
phase-gain comparator AD8302 (Analog Devices), so that its phase and
magnitude may be compared with those o f the reference signal at IN B (pin 6 ).
The differences are expressed as output dc voltages of 0 to 1.8 volts at Vmag and
Vphs pins. The chip is biased so that 0 to 1.8 volts at Vmag represents 0 to 30 dB
o f gain difference, and 0 to 1.8 to 0 volts at Vphs represents -180° to 0° to +180°
of phase difference. The magnitude and phase signals are output to the analog to
digital converters (ADC) o f the computer interface board.
The AD8302 Phase-Gain comparator greatly minimized the complexity of
our circuit. Initially, designs o f phase comparators using mixers were considered.
Similarly, amplitude detector circuits were designed using schottky diodes and
logarithmic amplifiers. For proper device operation, all driver circuits must be
identical. That is, the same value of control voltage must produce identical phase
shifts and attenuations in each circuit. It is very difficult to find matching active
discrete components. Therefore, there is an inherent mismatch between all circuits
made from discrete components only. Because of this, a single chip that combines
phase and gain comparison was sought and found. The AD8302 was ideal for our
needs.
It turned out that the AD8302 uses the same concept of log amplification
for its gain comparison, but exclusive OR gates are used to obtain phase
differences.
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71
4.5
PARALLEL PORT DRIVER
A TTL open collector inverter chip (LM74LS05) was connected as shown
in Figure 4.5, and provides the required current and voltage drive levels for the
I2C bus. LED D1 indicates when the line is active. This is plugged into the
parallel port o f the computer via connector J2.
R5
R3
R6
R7
U1
C1
U1A
12
7404
15
16
18
20
7404
23
24
JO,
7404
Figure 4.5
4.6
7404
I2 C-Parallel Port Driver
COMPUTER INTERFACE BOARD
The computer interface board is used to convert the serial TTL data
signals o f the I2C bus to output variable voltage for phase and gain control, and to
convert the feedback phase and magnitude signals to I2C signals. The general
'S
schematic for this interface is shown in Figure 4.6 below. I C bus consists of a
serial clock line (SCL), a serial data line (SDA), a ground and a 5 volt line. This
serial data is routed via three 8 -bit input/output (I/O) expanders PCF8574 (from
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72
Phillips Semiconductors) to the twelve phase and gain control circuits. Three
expanders are needed to provide 24 data i/o lines.
SDA
SCL
PCF8S74 P
VDD
V phase_1 of 12
Vmagnltude_1 o f 12
-S V
I/O Expander
M agnitude feed b a c k
l/D £ D/A converter
(1 of 6!
Figure 4.6
Computer Interface
As shown in Figure 4.6, each chip has
8
outputs, PO to P7. The first 12
outputs (PO to P7 and PO to P3 of the first two chips) are converted to a 0 - 10
volts dc signal.
This is used to bias the varactors o f the phase shifters in the
transmitter circuit. Signal conversion is achieved by feeding each of the 12 data
outputs to separate op amp converter circuits. For simplicity, only one such circuit
is shown in the figure. The first op amp is connected as a level shifter to convert
the input +5 V TTL pulse to a +12 V pulse. This pulse charges up Cl trough R1
before being buffered by a second op amp. The values o f R1 and Cl are chosen so
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73
that the charging occurs slowly, producing a ramping dc voltage at the input of
the voltage follower stage. The final voltage across Cl is determined by the
duration o f the TTL pulse and is controlled by the computer’s software. Note that
the op amp is biased with +12 V and ground to ensure positive output at all times.
The other 12 outputs of the I/O expanders (P4 to P7 and PO to P7 of the
2nd and 3rd chip) are converted to a —4 to 0 volt varying dc signal. This is use to
control the attenuation o f the RF signals in the transmitter. The same type of op
amp circuit is used, but the op amps are now biased with +5 and -5 volts and the
TTL signal is on the inverting input. In this way the +5 volt TTL pulse is
converted to a -5 volt pulse, which then charges up C2. C2 polarity is reversed so
as to facilitate negative voltage charging. A Diode D was placed across C2 (not
shown in Fig. 4.6) to prevent the voltage from going positive when C2 is
discharged. R l, R2 and C l, C2 are chosen to be 100 kQ and 100 pF respectively.
The feedback phase and magnitude dc signals are connected directly to the
analog inputs (AINs) o f the analog-to-digital converter, as shown in the figure.
2.5 Vdc was used for the converter’s reference voltage. Once again, for
simplicity, only one A/D connection is shown. The input dc signals are converted
to serial TTL pulses and are sent via the SDA and SCL lines o f the I2C bus to the
computer for processing.
One extra A/D chip was used for conversion of the feedback signals from
an extra phase-gain comparator. Its RF input is taken from an external probe
(feedback probe). This probe is manually connected to the antennas and the
signals obtained are compared with the reference RF signal.
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74
The AO, A l, and A2 address pins of each I/O expander and A/D chip are
set to different logic states. This is combined with the chip’s internal address
markers to create unique addresses for each chip. The internal addresses of the I/O
expanders are different from those of the A/Ds. In this way, each chip is
individually accessible by the computer.
4.7
THE CONTROLLER PROGRAM
A standard PC running the Linux operating system was used. The
controller program was written in the C programming language. Its operation is
such that whenever twelve predetermined magnitude and phase signals are
entered at the keyboard, they are converted to the required digital signals and send
to the computer interface board via the parallel port and the I2C bus. The accuracy
of these output signals is determined from a comparison of the feedback signals
with the pre-calibrated values. The pre-calibrated values are obtained from actual
phase and magnitude measurements of a network analyzer.
During operation, the actual measured value from the feedback probe may
be displayed with the desired values. In this way a visual check of the accuracy of
the system is readily available.
4.8
PCB DESIGNS
All PCB layouts were done using IsoPro software from T-Tech Company.
The tracks and pads were isolated within this software and etched out by the
Quick Circuit milling machine (also from T-Tech). The requirements for PCB
layouts for the driver circuit boards were consistent with those o f microwave PCB
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(a) Distribution board (top)
m
(d) Computer interface board (top)
if H II
f :l
|
fi
II
(b) Distribution board (bottom)
2 I
*'
ii
l■'HIP
l i t !
•■»
H
H
Ji f f 11 ! I U i!
if
• ji.
II
w w w
H
v: *..*
| | w w w v:
i|
I f f t }I
;;
(e) Computer interface board (bottom)
in***
1
fc fc » *. % Sv
« & B .«
(c) Parallel port driver
(f) Antenna driver circuits
Figure 4.7
Pictures o f some of the PCB boards constructed for the device: (a)
Distribution board (top); (b) Distribution board (bottom); (c) Parallel port driver;
(d) Computer interface board (top); (e) Computer interface board (bottom); (1)
Antenna driver circuits
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76
designs as discussed in Chapter 3. Figure 4.7 shows some pictures of the actual
boards that were designed.
Manual layouts are very tedious and time consuming. The standard
method o f PCB construction is to draw the circuit schematic and design its PCB
layout within a CAD package (such as Allegro or ORCAD Cad tools from
Cadence Company) to create a Gerber file. This Gerber file may be (1) exported
to IsoPro to be processed for milling, or (2) sent to a PCB manufacturing
company for construction. O f course, the latter option can be very expensive and
is mainly recommended for mass production.
4.9
MEASUREMENTS AND RESULTS
Individual stages of the phased array driver circuits were first constructed
and tested. All except the attenuator worked as expected. The attenuator’s biasing
was modified so that over 30 dB attenuation was obtained with a -4 to 0 control
voltage variation. However, the input and output impedance also vary with phase.
These tests also serve to verily the manufacturers specifications.
A single driver circuit was then constructed using T-Techs tools. The
antennas were chemically etched with ferric chloride solution. The phase and
magnitude variation for the single driver circuit was observed with a Hewlett
Packard 1.2 GHz network analyzer. A plot of the actual output phase (thick line)
versus phase control voltage is shown in Figure 4.8. During these measurements
the attenuation control voltage, Vmagn, was set to
0
volts. Because of the inherent
impedance variations o f the phase shifter, the output magnitude o f the signal
varies with phase. This is shown in the plot (thin line).
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77
400
300 ■
1
2
3
4
5
6
7
8
9
10
Varactor control voltage (Vdc)
Figure 4.8
Plot o f relative phase (thick line) and magnitude (thin line) versus
varactor bias voltage with attenuator control set to 0 Volts.
This seemed promising so the full 12-transmitter array was constructed,
encased and tested with the network analyzer. Figure 4.9 shows a block diagram
of the test setup and Figure 4.10 presents some pictorial views of the actual
device. The power supply sources were constructed using standard fixed- and
variable-voltage regulators. The driver circuit for antenna 1 was used for testing
and calibration. Its 0 to 10 and -4 to 0 Vdc control voltage lines from the computer
interface were broken and placed across 2-way switches (SPDT). In one position,
the switches connect the interface to the transmitter circuit and in the other they
connect the applied test voltages. Its feedback voltage line was also tapped and
the voltage readings were obtained by the voltmeters. The phase and magnitude
variation were measured when the test voltages were varied.
Phase measurements varied between 0 and 180 degrees, while the
attenuation was extremely erratic. This is totally unacceptable and various
unsuccessful attempts were made to improve these results. Different driver
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78
circuits (2, 3 etc) were tested but the same poor results were obtained. Shielding
the circuits with thin copper sheets barely made any improvements.
821
Network
Analyzer
Port 1
Port 2
Probe
Patch antennas
1
RF in
1
1
3x4
Phased Array
Device
Feedback voltages
Phase adjust
r c bus
Gain Adjust
Power
□— C x
Voltmeters
0-10 Vdc
- 4 - 0 Vdc
Manual Voltage Adjust
Computer
(Linux)
Figure 4.9
Parallel
Port Driver
DC Voltage Supply
+12, +5, -5, +2.5, gnd
Test setup for phase and magnitude measurements
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Figure 4.10
Different views of the completed device
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80
4.10 CONCLUSION
A 3 x 4 phased array was designed and tested for 1 GHz operation.
Undesirable results were obtained despite all efforts to modify the existing
circuits. These poor results may have been caused from:
1.
Too wide an impedance variation with phase
of the
transmission line phase shifter.
2.
Variation o f the input and output impedances
of the
attenuator.
3.
Impedance mismatch between the phase shifter
and the
attenuator.
4.
Improper sampling of antenna signals for feedback purposes.
5.
Coupling between adjacent circuits.
6
.
Cross talk and RF pickup in wire connectors from the
computer interface board to the antenna driver circuits.
All efforts to improve the results failed and the only remaining option was
to totally redesign the device. It turned out that the transmission line phase shifter
design was not the best choice of phase shifters for 1 GHz application, because of
the inherent large impedance variation for practical transmission line lengths.
They were chosen for this design because they are the only ones that can be easily
scaled up to much higher microwave frequencies.
At this point, however, it became very important to demonstrate a proper
working device at 1 GHz operating frequency. To this end, new phase shifter
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81
designs were considered, even if they were not scalable to higher microwave
frequencies.
4.10.1
A Complete Redesign
At about the time of testing the device, Mini Circuits of New York placed
a new voltage-variable phase shifter on the market. It has a control voltage range
of 0 to 15 volts dc and gives a phase shift of 0 to 180 degrees at 1 GHz. It was
reasonably priced and packaged as a microwave integrated circuit (MIC).
400
g> 300 -
200
-
4
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Control Voltage (V dc)
Figure 4.11 Phase (bold line) and magnitude (thin line) versus control voltage
for two MIC phase shifters connected in series.
Three phase shifters were immediately bought from Mini Circuits and test
circuits were quickly developed. They worked perfectly. Figure 4.11 shows a plot
o f phase and magnitude versus control voltage. When the control voltage was
varied over its full range, phase shifts in excess of 360° were obtained with a
magnitude variation o f less than 2 dB (compared to 10 dB change for the
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82
transmission line phase shifter). This was perfect for our application and the
phased array device was completely redesigned. The details of its design are
outlined in the following chapters.
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83
Chapter 5
Design Stages of a Single Antenna Driver
This chapter describes the many design and test stages o f a single antenna
driver circuit. We developed the architecture for a single channel and have
successfully applied it to the development o f a 4 x 4 phased array antenna device.
The description and operation of the 4 x 4 array is detailed in Chapter
6
.
Compared to the 3 x 4 array described in Chapter 4, a more sophisticated design
approach was used. Special steps were taken to eliminate or minimized the flaws
o f the previous design (outlined in section 4.10). Some o f these steps are:
1. The use o f variable phase shifter and attenuator packages with fixed
50-ohm input and output
impedances to
eliminate unwanted
magnitude variations.
2. Each channel in the array has its own digital control circuits. This
eliminates the need for long interconnects between boards and allows
proper grounded shielding between channels.
3. The use o f co-planar waveguides. They are more suited to the etching
process o f the Quick Circuit milling machine.
4. The use o f directional couplers for signal sampling.
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84
Each stage was separately designed, packaged in grounded casing and
thoroughly tested. The test results were compared against those of the
manufacturers to ensure proper operation of each component. The first test circuit
designed was that o f the phase shifters, followed by the 5-bit digital attenuator,
phase-gain comparator and finally the directional coupler. Operation of the
amplifier, the input/output expanders, and the analog-to-digital converters were
already verified from the previous design (Chapter 4). Also, the focus was mainly
on the phase shifter and attenuator, especially on their input and output impedance
variations. Once all tests were completed and satisfactory results were obtained, a
single channel o f the 4 x 4 phased array device was designed and tested. It was
properly characterized and its architecture was applied to the development of a
full 4 x 4 phased array.
The outline o f this chapter follows the actual steps used in designing the
single antenna driver circuit. First, the design, construction, and measurement of
each RF component module are presented, followed by the design o f a single
antenna driver circuit.
As with the 3 x 3 device, IsoPro and Quick Circuit were used to design
and etch all PCBs. These processes have already been described in the previous
chapter, only their results will be presented here.
5.1
VOLTAGE VARIABLE PHASE SHIFTER
At about the time o f the testing of the 3 x 4 phased array, Mini Circuits, a
RF and microwave components manufacturer, placed a new voltage-variable
phase shifter on the market, model JSPHS-1000. This phase shifter was designed
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85
for operation within the 850 to 1000 MHz range and provides a 0 to 180 degrees
phase shift when its control voltage is varied from 0 to 15 Vdc. It promises a
constant input/output impedance of 50 ohms, an insertion loss of 1.2 dB and a
voltage standing wave ratio (VSWR) o f 1.2. We decided to test this new
component and see how well we could apply it to our design.
5.1.1 Test Circuit
Figure 5.1(a) shows the schematic of the phase shifter test circuit. A 1
GHz input signal at -20dBm is amplified by U l, a GAL-33 amplifier, before
being fed into the cascaded phase shifters U2 and U3. R1 biases the amplifier for
a gain o f 12 dB when Vcc equals 12 V. C5 and the RFC (radio frequency choke)
isolate the RF signal from the power supply circuit.
U2
RF Input I
">■
R F i/p
R F of p
<
Ir f out
(a)
(b)
Fig 5.1
(a) Schematic o f voltage-variable phase shifter (b) constructed module
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86
Phase shifters U2 and U3 are connected in series so that the phase shift is
doubled for the same control voltage. Capacitors C l, C2, C3 and C4 ac coupled
each stage. This circuit was constructed on a FR4 pcb and enclosed in a metal
case. Input, output, +12 Vdc and the 0-15 Vdc control voltage ports were added.
A picture o f the enclosed test circuit is shown in Figure 5.1(b).
5.1.2 Test Setup
Figure 5.2 shows a sketch of the setup used for testing the phase shifters.
The network analyzer simultaneously supplied the input and measured the output
1 GHz signals. A variable voltage supply was used to sweep the control voltage
from 0 to 15 Vdc, while supplying a fixed 12 Vdc for amplifier bias.
Network
Analyzer
Port 1
Port 2
50 Q
50-ohm BNC cables
Phase Shifter
Input
Output
(D U T )
Control Voltage
0*15 Vdc
+ 12 Vdc
+12 Vdc
Power Supply
Figure 5.2
Test setup for phase shifter module
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87
5.1.3 Measurements and Discussion
Using the setup in Figure 5.2 above, both phase and gain changes were
measured for every change in control voltage. Figure 5.3 below shows a polar plot
o f the relative phase shift with gain variation. Throughout all RF measurements,
the phase shift and the signal losses in the 50-ohm coaxial cables were taken into
consideration.
..A.
2-
MifcosP
Figure 5.3
Polar plot of relative phase shift with gain variation
It can be seen that there is very little variation in magnitude as the phase is
varied over 360°. The ideal case would have been a perfect circle. This slight
magnitude variation resulted from the slight variation in input and output
impedances o f the phase shifters. This result was already given in section 3.10
and was the main motivating factor for redesigning the device. The circuit has a
maximum gain o f 9 dB. Since the amplifier provides 12 dB of gain and 0.6 dB is
lost in the cables, then 2.4 dB must have been lost across the phase shifters
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88
(taking other circuit losses as being negligible). That is, each phase shifter has an
insertion loss o f 1.2 dB, as claimed by its manufacturer.
This test has confirmed the manufacturer’s specifications for the phase
shifters and convinced us to use them in our new design.
5.2
5-BIT DIGITAL ATTENUATOR
Because the voltage-variable attenuator used in the first design produced
unsatisfactory results, we decided to try a different type of attenuator. A 5-bit, 0 to
Table 5.1
Truth table for 5-bit digital attenuator
Control Voltage Input (Bits settings)
Attenuation
Setting
o/p - i/p
VI
16 dB
8
V2
dB
V3
4 dB
V4
2 dB
V5
1 dB
High
High
High
High
High
High
High
High
High
Low
Reference
Insertion loss
1 dB
High
High
High
Low
High
2 dB
High
High
Low
High
High
4 dB
High
Low
High
High
High
8
Low
High
High
High
High
16 dB
Low
Low
Low
Low
Low
31 dB
max. atten.
dB
Any combination o f the above states will provide attenuation approximately
equal to the sum o f the bits selected.
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89
30 dB attenuator, HMC273MS10G, supplied by Hittite Semiconductor, was
bought and tested. It is a broadband 5-bit positive control GaAs IC digital
attenuator housed in a 10 pin MSOP plastic package. Its operating frequency
ranges from 0.7 to 3.7 GHz and has an insertion loss of less than 2 dB. Its bit
values starting from the least significant bit (LSB) are 1, 2, 4, 8 , and 16 dB for a
total attenuation o f 31 dB. It also has an accuracy of +/- 0.5 dB and an IIP3 (third
order intercept) o f up to 48 dBm. The 5 bits may be controlled by TTL type
voltages, that is, 0 volt for “Low” and 3 to 5 volts for “High”. It requires a single
supply voltage o f +3 to +5 volts applied across a 5K ohm resistor. Table 4.1
shows the relationship between the control bit settings and the amount o f
attenuation.
As with the phase shifter, a test circuit was designed to verify the
manufacturer’s specifications.
5.2.1 Test Circuit
The schematic circuit for testing the attenuator is shown in Figure 5.4
below. The input RF signal is fed directly into attenuator U l, via the ac coupling
capacitor, C l. After leaving the attenuator, it gets amplified by the GaAs
amplifier, U2. The configuration of this amplifier is the same as that in the phase
shifter circuit o f Figure 5.1. The control voltage inputs to the 5 control bits are
connected so that they may be manually switched from high to low via resistor
pack R1 and switch SW1. In this way, inputs from binary 1 1 1 1 1 to 0 0 0 0 0
may be entered. This corresponds to decimal 31 to 0. The gain at the output was
measured.
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90
5.2.2 Test Setup
The test setup used is the same as that of the phase shifters in Figure 5.2.
This time the device under test (DUT) is the attenuator module. The same input
signal
ui
C3
RF input
U2
Out
|R F OUT
R2
5K
+5 V
R3
+5 V
SW 1
+12 V
(a)
'nuUor
(b)
Figure 5.4
(a) Schematic of attenuator test circuit (b) constructed module
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91
of 1 GHz at -20 dBm was used. However, a fixed +12 volts and +5 volts power
supply was utilzed. The control inputs were varied from 0 0 0 0 0 to 1 1 1 1 1
through 32 steps and the output magnitude was plotted against the decimal control
value ( 0 -3 1 ).
5.2.3 Measurements and Discussion
Figure 5.5 shows a plot of output magnitude (-gain) versus decimal input.
The decimal value o f 0 - 31 represents the 5-bit binary range of 00000 to 11111.
We see that a maximum attenuation of 31 dB is obtained for an input of decimal 0
(or binary 0 0 0 0 0) while 0 dB is obtained for an input of decimal 31. The
insertion loss o f the attenuator was not included in these measurements. It was
separately measured to be 2.2 dB.
D ecim al (0-31) bit setting
10
-5 -
§
15
20
25
♦ ♦ ♦
-10
/■—"s
c
0
'■
3S -15
c
<D
1 -20
8 -25-30
-35
Figure 5.5
Attenuation versus bit setting
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35
92
Notice that the data points on the plot are not joined to form a single line. This is
because they represent discrete values. A line would indicate that any value along
the range is possible and this would be incorrect. Another interesting observation
may be made in the range between decimal 15 and 25. Notice the slight
randomness o f the points. These are random behavior and are due to the RF
pickup along the ribbon cable connecting the externally placed switches to the RF
board. This ribbon cable is visible in the picture of Figure 5.4(b) (coming out of
the metal box). Most o f the kink disappeared after grounded copper foil was
wrapped around the connecting cables. Better plots of attenuation were obtained
when a single channel, with all circuits enclosed within a grounded casing, was
tested. This will be discussed later.
Another point o f interest in this design is the use of an attenuator followed
by a fixed gain amplifier. Why not just use a variable gain amplifier? Well, firstly,
it’s cheaper this way, since variable gain amplifiers can be rather expensive.
Secondly, in most variable gain amplifiers, the input and output impedances
(along with other characteristics) tend to vary with the gain when used at
microwave frequencies. Remember that we are dealing with microwave
frequencies. Most variable gain amplifiers are actually an integration of an
attenuator with a fixed amplifer.
Our test results for the HMC273MS10G attenuator matches those of its
manufacturer. It was therefore chosen as part o f our final design.
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93
5.3
PHASE AND GAIN COMPARATOR
5.3.1 General Description of the AD8302 Integrated Circuit
As already discussed in Chapetr 3, the AD8203 phase frequency
comparator chip was obtained from Analog Devices. The AD8302 is a fully
integrated system for measuring relative gain/loss and phase in numerous
transmit, receive and instrumentation applications. It achieves this with just a few
external components and a single voltage supply of 2.7 to 5.5 volts. It has an
input dynamic range from -60 dBm to 0 dBm in a 50 ohm environment and a
maximum frequency o f operation of 2.7 GHz. Its outputs provide an accurate
measurement o f either gain or loss over a ± 30 dB range scaled to 30 mV/dB, and
a phase difference o f 0 ° - 180° scaled to 10 mV/degree.
Figure 5.6 shows a functional block diagram o f the AD8302. This chip
comprises two identical logarithmic amplifiers (log amps), each having a cascade
o f linear/limiting gain stages producing a total gain o f 60 dB. Log amps provide a
VM G
P8ET
5) par
VPOfll
Figure 5.6
Devices)
11V
Functional block diagram o f the AD8302 (courtesy of Analog
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94
logarithmic compression function that converts a large range of input signal levels
to a compact decibel-scaled output. By taking the difference of their outputs, a
measurement o f the magnitude ratio or relative gain between the two inputs (on
INA and INB) is readily obtainable. This is available as a 0 - 1.8 Vdc voltage at
Vmag corresponding to a 0 - 60 dB relative gain.
An important attribute o f the two-log-amp architecture is that if both
channels are at the same frequency and have the same input network, then
impedance mismatches and reflection losses become essentially common mode
and hence do not impact the relative gain and phase measurements. However,
mismatches in their external circuits can result in measurement errors. At
moderate frequencies (say 100 MHz) the input impedance network may be
approximated by a shunt 3 kQ resistor in parallel with a 2 pF capacitor. At higher
frequencies, the shunt resistance decreases to about 500 Q. For our application at
1 GHz, the shunt resistor has an approximate value of 2 kQ. A broadband
resistive termination on the signal inputs, just before any coupling capacitors, can
be used to match the impedance of the source.
The output o f the final stage of the log amp is a fully limited signal over
most o f the input dynamic range. The limited outputs from both log amps drive an
exclusive-OR style digital phase detector. Operating strictly on the relative zerocrossings o f the limited signals, the extracted phase difference is independent of
the original input signal levels. The phase detector output is converted to a 0 - 1.8
Vdc and is available at the Vphs pin. An excursion of 0 to 1. 8 to 0 volts represents
a phase difference o f -180° to 0° to +180°. This means that one Vphs value
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95
corresponds to two different phase values. Therefore extreme care must be taken
when measuring phase differences greater than 180 degrees. Both phase and
magnitude outputs are simultaneously available. For more information on the
theory of operation for the AD8302 see the Anolog Devices web page [65].
5.3.2 Test Circuit
Samples o f AD8302 chip were obtained from Analog Devices and the test
circuit o f Figure 5.7(a) was designed. Figures 5.7(b) and 5.7(c) are the PCB
layout and the constructed module, respectively. Inputs RF1 and RF2 are
5V
Inp A
Ofs A
Vmag
Mset
AD8302
(b)
(c)
Figure 5.7
(a) Schematic of phase and gain comparator test circuit (b) PCB
layout (c) Constructed module
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96
terminated with 50 Q resistors, R1 and R2. In this way, the high impedance input
of the comparator will sample the input signal voltages only. Note that this is not
proper impedance matching, but is adequate for our purposes, as long as both
channels are balanced. Capacitors Cl and C2 are chosen to offer very little
impedance to our input signal. C3 and C4 provide ac grounding and set the high
pass comer frequency for the internal compensation. LI, C5 and C6 form a lowpass network that easily allows the power supply voltage to pass while preventing
the signal (1 GHz for our application) from feeding into the power supply. Vmag,
Mset and Vphs and Pset are connected as shown and set the slopes of the output
plots of relative gain versus Vmag and relative phase versus Vphs, respectively.
R4 and R5 are current limiters; they prevent overloading of the output circuits.
The circuit was laid out and the PCB board etched (Figure 5.7(b)). It was
soldered and packaged in a grounded metal casing, as shown on Figure 5.7(c).
5.3.3 Test Setup
Figure 5.8 shows a sketch of the test setup for measuring the output
magnitude and phase values of the AD8302 phase-gain comparator. No power
supply connections are shown. A network analyzer was used to provide a 1 GHz,
-20 dBm signal. This signal was divided into two by a 2-way splitter. Actually we
used a T-BNC connector. One of the outputs was phase shifted, attenuated and
fed to the comparator module as its input A signal. The other output was used as
the reference signal and fed to input B o f the comparator. Variable phase and gain
were obtained from the previously made phase shifter and attenuator modules.
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97
For phase measurement, the attenuator was set for zero attenuation and the
phase was varied through its full 360 degrees range. In this way, the phase of the
signal at input A was varied while that at input B remained fixed. The AD8302
Network
Analyzer
Port 1
Port 2
50 Q
1 GHz at -20dBm
2 -way
Splitter
out
out
1
2
in
Phase Shifter
And
Attenuator
out
Signal
in
(DUT)
Phase and Gain
Comparator
Vmag
Figure 5.8
Ref in
Vphs
Test setup for comparator module
module compares the inputs phases and express their difference as dc voltages on
its Vphs output pin. The attenuator was then varied through its 30 dB range while
keeping the phase fixed. This time, the module compared the magnitude of the
inputs and expressed their difference as a dc voltage on its Vmag output. The
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98
values obtained for Vphs and Vmag were plotted against the relative phase and
magnitude inputs, respectively.
5.3.4 Measurements and Discussion
Figure 5.9(a) shows a plot of output dc voltage, Vphs versus relative phase
and Figure 5.9(b) shows a plot of output dc voltages, Vmag versus relative
magnitude.
0
5
0.8
1
0.6
>
0.4 -
0.2
-
100
0
200
300
400
Relative Phase (degrees)
(a)
1.05
1
0.95
0.9 -
5
o(0>
E
>
***
0.85 -
0.8
0.75 0.7
******
0.65
0.6
10
20
30
40
Relative Gain (dB)
(b)
Figure 5.9 (a) Vphs versus relative phase shift (b) Vmag versus relative
magnitudes.
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99
These results do not match the manufacturer’s specifications. We expected
Vphs to change linearly with phase for the first 180 degrees, then, reverse its
direction o f change for the next 180 degrees. That is, we expect some sort of
triangular-shaped plot with each Vphs value corresponding to two different phase
values. Instead, we got something that looks like a clipped off inverted V-shape.
For the Magnitude, we expected Vmag points to vary linearly over a 0.9 V
range for 30 dB o f magnitude change. The full range of the AD8302 comparator
is 1.8 volt for 60 dB gain range. Our plot does show a somewhat linear variation,
but over a much smaller range o f 0.3 volt. What could have caused this?
It turned out that these measurements were taken when the phase shifter
and attenuator modules had connecting wires protruding from their cases. This
subjected the circuits to all kinds of RF pick-up and disturbances. Additionally, it
could also mean that the reference signal was not stable. This was not the case,
however, since the reference signal was actually checked by connecting it to port
2 o f the network analyzer, while varying the magnitude and phase. It remained at
a fixed value throughout this variation. This test also demonstrates the high level
o f input-output isolation (reverse isolation) o f the phase shifter and attenuator
circuits.
We decided to go ahead and use the AD8302 in our design. Later on,
when a single antenna channel was built, we re-measured Vmag and Vphs and the
results were extremely good.
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100
5.4
RF DIRECTIONAL COUPLER
We believe that one of the reasons for the poor results o f the first phased
array design (Chapter 4) was improper sampling of the RF signals. We need a
sampling method that does not disturb the circuit being sampled. Directional
couplers are ideally suited for this kind of application.
Directional couplers separate signals based on the direction of propagation
and are generally represented by Figure 5.10(a). These devices are used to split
Port A
Port B
PortC ▼
(a)
Port A
Port B
Port A
Port B
(Input)
Input)
T2
T2
R4
R4
(matching
Port C
Port C
Coupled
180 degrees
Coupled
In phase
(b)
(0 degree)
(c)
Figure 5.10 (a) Symbolic representation o f directional coupler, (b) inverting
coupler, and (c) non-inverting coupler.
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101
the signal flowing in the main line unequally and to pass the signal flowing in the
opposite direction fully. Ports B and C are isolated, so that signals flowing into
Port B will feed through to Port A only. A RF directional coupler may be realized
with a two-transformer circuit, connected as shown in Figure 5.10(b) or 5.10(c),
depending on whether inverting or non-inverting coupling is desired. Directional
couplers o f this type are impedanceless, in that they become the impedance to
which their ports are connected. For example, 50-ohm impedances are obtained
by matching all ports to 50 Q. Usually R4 sets the impedance of the coupled port.
We obtained a broadband, non-inverting directional coupler, ADC-6-13,
from Mini Circuits. It has a coupled loss of 6.3 dB and a main line loss of 2 dB.
Its operating frequency range is 200 - 1300 MHz and has dimensions of
6
mm with just
6
8
mm by
pins.
5.4.1 Test Setup and Measurement
We directly soldered 50-ohm coaxial cables to the Ports A, B, and C o f the
ADC-6-13. A 50-ohm resistor was soldered across Port D and ground, thus setting
Port C to 50 ohm. Two measurements were made: (1) the magnitude at Port B
with respect to Port A, and (2) the magnitude at the coupled port. The first
measurement was obtained by connecting the coupled port to 50 ohms and
sending a 1 GHz signal into Port A, while measuring the output at Port B with a
network analyzer. The signal at Port B was 2.1 dB less than the input signal,
telling us that the main line loss is 2.1 dB.
The second measurement was made after connecting Port B to 50 ohms
and measuring the signal strength and phase at Port C, the coupled port. The 1
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102
GHz input signal was still at Port A. The signal loss at Port C was
6
dB and was
in phase with the input signal. These measurements are in total agreement with
the manufacturer’s specifications. In our application, Port C will be used for
sampling the signal.
5.5
A SINGLE ANTENNA DRIVER
5.5.1 Architecture
Figure 5.11 shows a block diagram of the architecture used in the design
o f a single driver circuit. A 1 GHz, -20 dBm signal was sampled by a ADC-6-13
directional coupler to provide a reference signal. The main signal output was
phased shifted by two cascaded
0
-180° voltage variable phase shifters, attenuated
by a 0 - 31 dB 5-bit digital attenuator, amplified by a fixed 15 dB amplifier and
again sampled by another directional coupler.
The sampled output of the first
coupler is used as a 1 GHz reference signal for the phase-gain comparator. On the
other hand, the sampled output of the second coupler provides a feedback RF
signal for testing. Within the phase-gain comparator, the feedback signal is
compared against the reference and their phase and magnitude differences are
expressed as dc output voltages ranging from 0 to
1 .8
volts.
The two 0 - 1 . 8 Vdc outputs of the comparator are level shifted to 0 - 5
volts by two operational amplifiers (op amp) configured for a gain of 2.8. The two
op amps are actually part of a LM324 quad op amp SOIC (surface mount)
package. Their outputs are converted to digital data by a PCF8591 analog-to-
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103
digital converter, and sent to the computer for processing via the bi-directional
SDA and SCL lines o f the I2C bus.
1GHz RF Input (-5 to -20 dBm)
BNC cable
RF Referenci
D ire c tio n a l
C o u p le r
RF
out
Variable
Phase shifter
2 x 0 °-1 8 0 °
5-bit digital
attenuator
(30dB)
RF Amp
Directional
Coupler
Sampled RF o/p
Op Amp
t (gain=3.7)
12-bit
serial
DAC
8 - bit
I/O expander
To Computer
RF
SDA
Parallel
Port
Driver
8-bit
ADC
R e f in
Phase/Magn
Comparator
SCL
Figure 5.11
Architecture of single antenna driver circuit
The 0 - 1 5 Vdc control voltages for the phase shifters are obtained from a
12-bit digital-to-analog converter (DAC), which is in turn controled by three
output lines o f the input/output expander (i/o expander). Actually, the DAC
output ranges from 0.1 to 4.1 volts and is level shifted by an op amp to 0.1 - 15
volts. To do this, the op amp was configured for a gain of 3.7 and has a supply
voltage o f 17 volts. A 12-bit DAC was chosen to provide less than 1° resolution of
the phase. That is, the control voltage is varied from 0 to 15 volts in steps o f 3.6
mV. This was obtained by dividing the voltage range by 212. This was previously
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104
determined from the shape o f the relative phase shift curve in Figure 5.3 and was
calculated from the steepest region of the plot. The steepest region of the slope
occurs when the control voltage was varied from
6
to
8
volts, producing a phase
shift from 100° to 250°. Therefore, the change in control voltage required to
produce a phase shift o f 1° is ( 8 -6 )/ (250-100) = 13.3 mV. Thus, a 12-bit DAC is
more than adequate. Note that an 8 -bit DAC would have had voltage steps of 58.6
mV (15/28), which would not provide the required phase resolution.
Ref out
RF input
5 Vdc
/
RF out
18 Vdc
Ref in
To parallel port driver
(a)
Figure 5.12
(b)
(a) PCB o f single channel, and (b) Single channel prototype
The other five outputs of the
8
-bit i/o expander are used to control the
attenuator. It is connected in such a way that by sending a binary count of 00000
to
11111
on the five lines to the control inputs of the attenuator, the attenuation
will be varied from 31 dB to 0 dB. Again, the i/o expander is controlled from the
SDA and SCL lines. The SDA (serial data) and SCL (serial clock) are part of the
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105
I2C bus that interfaced through the parallel port driver to the computer. This was
previously discussed in Chapter 4.
The prototype for this single channel was designed and tested. Figure 12
shows (a) the printed circuit board, and (b) the encased module.
5.5.2 Test Setup
A network analyzer was used to provide a 1 GHz, -20 dBm signal at the
RF input port o f the single channel prototype (shown in Figure 5.12(b)), while
simultaneously measuring its output. The analyzer was set up to observe
magnitude and phase changes simultaneously. Ref out was connected to Ref in by
a 50-ohm BNC cable. +5 V and +18 V power supply voltages were connected.
Finally the parallel port driver was plugged into the DB9 port of the module and
its other end was connected to the parallel port o f the computer.
The computer was booted up in Linux and a previously written test
program was loaded. During operation, the program will step the phase through
360° while keeping the magnitude constant, then step the magnitude through 31
dB while keeping the phase constant. After each step, it would pause to allow the
operator to record the output values, and continue after hitting the return key on
the keyboard. The measurements taken from the network analyzer were used to
plot the relative output phases and magnitudes.
5.5.3 Results and Discussion
Figure 5.13 below show two magnitude plots. Figure 5.13(a) has two
different plots o f the comparator’s magnitude output voltage (after amplification
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106
o f 2.8 by op amp), versus the measured attenuation. The dotted line represents the
first set o f data collected. The flattened section at the top, at about 3.75 volts, was
totally unexpected. It was actually caused by clipping of the level shifting op
35
4.5
30
♦
♦
<
1.5
10
0.5 10
10I
20
Attenuation (dB)
30
40
15
20
25
30
35
5 bit digital value (0 to 31)
(a)
(b)
Figure 5.13
Magnitude plots (a) Comparators Vmag output versus attenuation
and (b) Attenuation versus attenuator control bit settings.
amps. This clipping occurred because the op amps were accidentally connected to
the 5 volts supply instead o f the 17 volts supply. Therefore its output was driven
to saturation at 3.75 volts. This error was corrected and the output was re­
measured. The new results were plotted on the same graph and are shown with the
diamond-shaped markers. Notice that the comparator’s Vmag output now varies
from 1.66 to 4.31 volts, a range of 2.66 volt. Since the op amps were configured
for a gain o f 2.8, it means that its input values were 0.6 - 1.54 volt, corresponding
to a range o f 0.95 volt. This was the actual range for Vmag, the magnitude voltage
output o f the phase gain comparator. This now corresponds to the manufacturer’s
specifications. Recall that in the previous comparator test circuit, we were not
getting the correct range due to RF pickup (see section 5.3.4).
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107
As a calibration test, we compare the actual measured attenuation with the
control bits setting and plot the results in Figure 5.13 (b). An almost one to one
match was obtained, indicating the accuracy of the control bits. The results for the
magnitude tests were totally satisfactory.
Figures 5.14 (a) and 5.14(b) are the plots of the relative output phase
versus the amplified comparator’s output phase voltage, Vphs. Once again, the
first set o f measurements in 5.14(a) were clipped due to the 5 V power supply on
the op amp. Figure 5.14(b) shows the second set of data after the power supply
problem was resolved. This time, a distinct inverted V-shape was obtained, with
Vmag spanning the full 0 to 1.8 Vdc range. Actually, the start and end points of
the Y-shape depends on the phase of the reference signal. Notice that one Vphs
value corresponds to two different phase values. This means that phase changes
must be properly tracked for correct phase settings. The technique used to do this
will be presented in Chapter 7.
CO
CO
oi
CN
X
o'
3
0)
X
o'
3
(0
JZ
-C
Q_
Q_
>
>
0 .5 -
-180
-120
-60
0
60
120
180
-180
-120
-60
0
60
120
180
Relative ph ase (degrees)
Relative P h a se (degrees)
Figure 5.14
Relative phase plots: (a) With op amp saturation (b) Without op
amp saturation
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108
5.6
CONCLUSION
We designed, constructed, and tested circuits for a voltage-variable phase
shifter, 5-bit digital attenuator, and a phase gain comparator. Their performances
matched their manufacturer’s specifications. After these confirmatory tests, a
single antenna driver circuit was built and tested. The results were extremely
satisfactory with both phase and gain variations meeting all our requirements.
With this assurance, we then extended the single channel design to the design of a
4 x 4 array system. Its design details are presented in the next chapter.
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109
Chapter 6
Design and Construction of a 4 x 4 Phased
Array
6.1
ARCHITECTURE OF THE 4 x 4 PHASED ARRAY
A 4 x 4 phased array antenna system was designed by interconnecting 16
of the single antenna driver circuits previously designed. In this application, the
input direction coupler was eliminated and the RF was sent directly to the phase
shifters. The RF reference signal was generated from channel 1. Figure 6.1 shows
a functional block diagram for this device. A 1 GHz RF input signal was divided
to create the inputs for the 16 single antenna drivers. For simplicity, only 4 output
connections are shown. Each signal is phase shifted, attenuated, and matched to
its respective antenna element. The phase shifting and attenuation are controlled
by software via the SDA and SCL lines. The 17 Vdc power supply input powers
all amplifiers and op amps within each driver circuit. It is also used to create a
regulated 5 volt source. This was done via a LM317T variable positive voltage
regulator. The 5 volts is used to power all the integrated circuits within each
channel.
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110
Antenna element #1
S D A l SCL1
17 Vdc
5 Vdc
Matching
Single antenna driver #1
Element #8
S D A l SCL 1
17 Vdc
5 Vdc
Matching
Single antenna driver #8
RF i/p
Element #9'
Way
SD A l
Splitter
SCL 1
17 Vdc
5 Vdc
Matching
Single antenna driver #9
Element #16
SDA 1 S C L 1
17 Vdc
5 Vdc
Matching
Single antenna driver #16
SDAO
Parallel
Port
Interface
Computer
SDA
SCLO
SCL
SDAl
SCL1
17 Vdc
>
---------------
Figure 6.1
}
}
------------------ ♦♦
Adjustable
regulator
(1.5 A)
Control for
channels 1 -
Control for
channels 9 - 1 6
17 Volts dc
(5.2 V)
Functional block diagram o f 4 x 4 phased array
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Ill
A physical limitation exists when more than eight channels are to be
operated simultaneously. This is due to chip address repetition of the input/output
expanders and the analog-to-digital converters. Each of these chips has 3 bits for
setting its chip address. This means a total o f 8 (23) addresses may be used before
they start repeating. For proper device operation, it is imperative that each of
these chips has a different address, so that they may be individually controlled or
accessed by the computer software. Otherwise, the device will malfunction.
It turned out that these chips also have fixed internal addresses. These
addresses are the same for a particular chip number. So, whenever they are being
accessed by software, the internal addresses and externally set 3-bit addresses are
combined to form the chip address. There are two types o f input-output expander
available from Phillips Semiconductor. They are the PCF7485T and PCF7485AT.
They are exactly the same except for their internal addresses. This means that they
could each have the same 3-bit address, but a different chip address. This solved
our problem with the i/o expanders. We simple used
8
of each chip giving us a
total o f 16 chips with different chip addresses.
Unfortunately, Phillips only has one type of analog-to-digital converter
(ADC) for I2C bus control, the PCF8591. This means that their chip addresses
will start repeating after the 8 th chip. Initially we devised a way o f getting around
this and were pretty convinced that it would work. So, we went ahead and laid out
our PCBs, etched our boards, soldered, and started testing. Then we realized that
our readings were not consistent and found out that the problem was caused from
inconsistencies in our “trick” connections.
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112
This is what we did. Each ADC has four analog inputs. We only needed
two for each channel, that is, one for the Vphs and the other for Vmag of the
phase gain comparator. We had no intention o f sharing one chip between two
channels because that would mean that the channels would be joined by two
tracks (or wire connector), creating a path for RF interference. This was to be
avoided. We just did not want to take that chance, not after our problems with the
earlier 3 x 4 design. So, we had one chip per channel, which only used two o f its
four analog inputs. We therefore alternated the inputs for every other channel
while setting the chips to the same bit address. For example, we used inputs AINO
and AIN1 for channel one, then inputs AIN2 and AIN3 for channel two while
setting both chips to the same address, 0 0 0 for each of the 3 bits. This means that
we had
8
pairs o f ADC for the 16 channels. The unused input pins of each ADC
chip were all connected to the chips’ 5-volt power supply voltage. The software
was then instructed to get the data at the relevant inputs for a particular channel.
In this way the inputs o f each pair of ADC would be able to change state without
causing confusion, since they are active low.
A problem, however, arose whenever the ADC reference voltage exceeded
that at the unused inputs. They should both be 5 volts, but this could not always
be guaranteed. This discrepancy led to inconsistency in the measurements. At this
point, the circuits were already soldered. Not much could have been done without
running wires all over the place, which was to be avoided at all cost.
Finally we gave up on trying to trick the circuit and installed a multiplexer
across the I2C data lines. It is I2C compatible and its function is to expand a single
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data line into two lines. Therefore it takes the SDA and SCL and creates SDA 0,
SCL 0, SDA 1 and SCL 1. SDA 0 and SCL 0 control channels 1 to 8 , which have
the first set o f ADC with addresses 0 - 8 , and SDA 1 and SCL 1 control channels
9 to 16, which have the second set of ADC with addresses 0 - 8 . The data lines
become active whenever a channel is being accessed. Only one channel may be
accessed at a time, so either line pair
0
or line pair
1
will be active, but never both
at the same time. This ensures that only one ADC address is seen at a time. Figure
6.1 shows the expansion of SDA and SCL by the multiplexer (MUX).
Ch5 -2
Ch9 - 4
C h l3 - 6
Ch6 - 2
ChlO - 4
C h l4 - 6
Ch3 -1
Ch7 - 3
C h ll - 5
C h l5 - 7
C h 4 -1
Ch8 - 3
C h l2 - 5
C h l6 - 7
C h i -0
SCLO
SDAO
SDA
M UX
SCL
SDAl
SCL1
Figure 6.2
Distribution of SDA and SCL I2C bus lines
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114
The actual wiring o f the multiplexer was not straightforward. Because the
device was already constructed, the simplest way was sought to connect the
multiplexer to the existing circuits. Figure 6.2 shows the actual layout of the
channels and the chosen connection of the multiplexer. SDA 0 and SCL 0 are
connected to odd-numbered channels (1, 3, 5 etc.), while SDAl and SCL 1 are
connected to even-numbered channels (2, 4,
6
, etc.). The channel number and
allocated ADC addresses are shown. The program has been instructed
accordingly. The power supplies were similarly routed.
6.2
RF DISTRIBUTION NETWORK
The design o f the 16-way splitter is similar to that for the 3 x 4 phased
array (section 3.2) where the H network was used. Figure 6.3 shows the PCB
RF Input
Figure 6.3
RF Distribution Network
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115
layout pattern (not drawn to scale). In this case however, the tracks were made 2.4
mm wide with 0.28 mm ground spacing, hence forming 50-ohm coplanar
transmission lines.
6.3
THE ANTENNA DESIGN
Patch antennas were used for our antenna elements. They were not
designed to any particular specifications, except to be able to be physically
mounted on the device. This was so because their coupling behavior is not yet
properly modeled (see Ref [7]), hence conditions for creating desirable input
impedances are not known as yet. In the meantime, the patches were center fed
and were tuned to be purely resistive. This, of course contradicts the conventional
Edge of
PCB
Patch
element # 1
Feed
point
- Patch
element #16
Patch
Element #4
Figure 6.4
Center fed patch antennas
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116
theory o f patch antennas, which outlined various off-center feed techniques for
proper impedance matching. This was already discussed in Chapter 2.
Sixteen square patches were made, each 48 mm on a side and spaced 5
mm apart. Figure 6.4 shows the layout. The patches were etched on one side of a
double-sided copper-clad board. All copper was removed from the spaces
between the patches. The other side of the PCB was grounded. The feed lines
were fed through the grounded side to the patches. A small section of the ground
plane under each patch element was etched away to admit the signal cables
feeding the patches.
6.3.1 Tuning the Patch Antennas
As previously explained, we are not yet able to design the patches with 50ohm input. Instead, we simply tuned them to be a resistive load to the driver
circuits at our operating frequency of 1 GHz. The patch antenna element
physically resembles a parallel plate capacitor. Its capacitance was calculated to
be 70 pF (for 0.048 x 0.048 m2 plate area with dielectric constant, sr = 4.5 at 1
GHz). In the actual circuit, these antennas are fed from the output amplifier
through a directional coupler. The directional coupler is inductive and when
placed in series with the patch, the total impedance is still inductive.
Tuning was done by simply placing a variable 5 - 20 pF capacitor in series
with the patch and the feed line, and adjusting the capacitor value until a pure
resistance value was seen on the Smith chart. This setup is shown in Figure 6.5.
The resistance value obtained was 20 ohms. All patch elements were individually
tuned.
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117
Patch element
Network
Analyzer
P o rt 1 (S „ )
100 pF
Directional
C oupler
(Inductive)
5-20 pF
Amplifier’s load (tuned to 20 ohms)
Figure 6.5
Setup for tuning patch element
The tuning capacitors were placed on the grounded-plane side of the
antenna PCB and were connected to the driver circuits by 50-ohm coaxial cables.
In this way, the antenna assembly is easily interchangeable. So, at some point in
the future when the patch antennas are designed with 50-ohm input, they may be
easily connected to the driver circuits.
6.4
BOARD DESIGNS AND DEVICE CONSTRUCTION
As previously mentioned, all PCBs were made using the Isopro layout tool
and Quick Circuit milling machine. All tracks and pads were manually laid out
using component dimensions that were either taken from their manufacturer’s
data sheets or were directly measured. In this section the layout o f all the boards
in the 4 x 4 phased array device is shown. All circuits were milled on 1/16th inch
thick, double sided copper clad boards. All coplanar 50-ohm RF tracks were
milled to be 2.4 mm wide with 0.28 mm (11 mils) milling bits. These values were
obtained applying the equations for CPW designs in Section 3.2.5.
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Non-RF
118
tracks were milled to any convenient width with either 0.38 mm (15 mils) or 0.78
mm (31 mils) bits. These bit sizes were chosen because they were the only ones
available at the time.
Figure
6 .6
shows the first of the four antenna driver circuit boards. Each
board contains four evenly spaced driver circuits, making a total of 16 drivers.
Their edges are milled so that they may be plugged into the 64-pin card edge
connectors located on both top and bottom distribution boards. The lines shown
Plug into
Edge connector
l/
To patch 1
RF in
Ref out
Probe in
Ref in
To patch 2
RF in
Ref in
To patch 3
RF in
Ref in
To patch 4
RF in
Ref in
Figure
6 .6
Layout o f antenna driver circuits, board 1 of 4
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119
are the actual milled out paths. All tracks and pads are contained within these
lines, while all other areas are grounded. The other side of the board is a solid
ground plane and is connected to the top ground plane by vias. Proper coplanar
design techniques were used. For simplicity, the components are not shown, but
their locations may be inferred from the locations of the pads. Only surface mount
components were used. Soldering these components required extreme skill and
patience. Some o f the ICs have only 0.3 mm spacing between their pins and great
care had to taken to avoid shorting the pins. All boards had to be thoroughly
cleaned and inspected after milling.
Channel 1 was modified to provide the RF reference signal and to measure
the probe’s feedback signal. Figure 6.7 shows this modification and may be
compared to Figure 5.11 in Chapter 5. The sampled RF output signal from the
directional coupler is amplified and distributed as the RF reference signal. At the
same time, the normal RF output of the channel is sent to patch element 1.
RF input
Variable
Phase shifter
2 x 0 °-1 8 0 °
5-bit digital
attenuator (30dB)
RF Amp
Directional
Coupler
to patch 1
Sampled
Rfo/p
Ref out
Op Amp
t (gam-3.7)
Amp
12-bit
serial
DAC
8 - bit
I/O expander
To Computer
Probe
R ef
SDA
Parallel
Port
Driver
8-bit
ADC
Phase/Magn
Comparator
SCL
Figure 6.7
Modifications to channel 1
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120
Pow er
su p p ly
----------- G = ^
inputs
&
Grounded
Pins
I2C bus
connector
(a)
Card edge
Connector
(b)
Figure 6 . 8 Input distribution board: (a) Bottom layer (when viewed through the
top layer); (b) Top layer.
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121
During device operation, channel 1 phase and magnitude settings are fixed
so that the reference signal remains at the same value at all times. All the other
channel values are set with respect to channel 1. In this way, any circuit changes
due to global occurrences should not affect the relative measurements.
Figure
6 .8 (a)
and
6 .8 (b)
show the bottom and top layers o f the input
distribution PCB. It has dimensions o f 21 cm by 21 cm. Some of the tracks have
been labeled. The input RF distribution network is readily visible and is placed on
the bottom layer. The top layer has eight card edge connectors soldered as shown.
All non-signal pins (without pads) o f these connectors are soldered to ground on
both top and bottom layers. This has a double purpose of connecting the top layer
ground plane to that o f the bottom layer, and providing mechanical sturdiness. At
all times, adequate grounding was placed around the RF connectors and tracks.
Figure 6.9(a) and 6.9(b) show the bottom and top layers of the top
distribution board. It has dimensions of 21 cm by 21 cm. The top layer supports
the RF output BNC connector from each channel to its respective patch element,
while the bottom layer supports the other 16 card edge connectors. Another RF
network is etched on the top layer to distribute the Ref signal. Once again, the
unused pins o f the card edge connectors are soldered to the top and bottom layer
ground planes, for the same reasons as before.
For the sake o f completeness, the layouts of the multiplexer and the
variable regulator boards are shown in Figure 6 .10.
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122
•
Probe input
BNC
: '«
------ 4
® :
•
-
•
•
•
a
®!
•
— a
®
Card edge
connector
:
Q :
6'
P i
P i
P i
O ;
'
i
®
■
•
•
Q
_<
;a
P i
®i
6'
•
i
•
4
•
®
■ «
•
•
*
•
$
:
a
:
S>:
• «
6:
o
O'
I <
•—
•®!
•
• :«
•
• ■a
P i
Pi
0
• -*
® :
• '■ «
• • '•
® :
• -•
• -«
®
• ••
o :
o '
o
BNC
mounts
.
(a)
BNC
mounts
Ref
distribution
network
(b)
Figure 6.9 Top distribution board: (a) Bottom layer (viewed from top); (b) Top
layer
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123
SDAO SCLO
S D A l SCL 1
SDA SCL
(a)
Figure 6.10
6.5
(b)
(a) Multiplexer board; (b) Variable regulator board
THE 4 X 4 PHASED ARRAY DRIVER
The final device was assembled and housed in a metal casing. The 16
driver circuits were shielded from each other by V2 inch vertical grounded planes,
and covered with copper foil. Figures 6.11(a) and 6.11(b) show the device without
and with casing. In Figure 6.11(a) board 1 cover is removed so that its internal
components are visible. The card edge connectors allow the device to be easily
assembled and disassembled. The probe connector is at the back of the device and
is not seen in these pictures.
The device was powered up and tested by the controller program. A brief
description o f the controller program is given in section 6.7 of this chapter. A
special RF probe was required to measure the actual signals at each antenna so
that a comparison could be made with the feedback values. There was no readily
available microwave probe, so we had to make one. We will now give a brief
description o f its design.
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124
(b)
Figure 6.11
connected
The 4 x 4 phased array: (a) Not encased; (b) Encased with antennas
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125
6.6
THE ANTENNA PROBE
A high input impedance probe was required to measure the magnitude and phase
o f the signal at each antenna in such a way that it does not change the loading of
the RF output circuits. The effect this has on the radiation pattern was ignored.
Such a probe was designed. Recall that the patch antennas are actually capacitors
with capacitance o f 70 pF, which has an extremely low reactance at 1 GHz, our
operating frequency. Our probe must therefore have an input circuit that provides
a relatively high reactance at 1 GHz. This was achieved with two series 0.5 pF
capacitor. The sketch o f Figure 6.12(a) illustrates this. An RF amplifier (Gal-33)
is connected on the other side of
Probe tip
o.5p
|| 0 .5P To RF amplifier
'!
kf
----- Patch element
1
*
ground plane yJ
RF Signal from driver
FR4 dielectric
^
(a)
Probe tip
Am p
RF out cable
■(b)
(c)
Figure 6.12 Antenna probe: (a) Illustration; (b) Actual probe; (c) Probe with RF
and DC line feeds
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126
the series capacitors and has an input impedance of 50 ohms. In this setup, most
of the current will flow into the patch element; thus our probe will have negligible
effect on the antenna circuit. Another way to look at this is that the parallel
combination o f 0.25 pF and 70 pF yields 70.25 pF. This change is negligible.
The signal at the input of the amplifier was measured to be 14 dB less than
that at the antenna, indicating the negligible loading effect o f the probe. The amp
was biased for a gain o f 17 dB, making the overall gain of the probe equal to 3 dB
(as was measured). The output signal may either be sent to the probe input of
channel l ’s phase gain comparator, or connected to a network analyzer for direct
measurement.
6.7
THE CONTROLLER PROGRAM
The system program is of two types: (1) a C-program that controls the full
operation o f the device and (2) a C compatible GTK+ windows program that
facilitates graphical inputs and outputs [6 6 ]. The full program, along with detailed
inserted comments, is given in Appendix A. GTK+ is a multi-platform toolkit for
creating graphical user interfaces. It is made up o f a complete set o f widgets. A
widget is an object used to hold data and present an interface to the user. It’s a
combination o f state and procedure. Each widget is a member of a class, which
holds the procedures and data structures common to all widgets o f that class. A
widget instance holds the procedures and data structures particular to that single
widget. Each widget class typically provides the general behavior associated with
a particular kind o f interaction with the user.
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127
Figure 6.13 is a flow chart illustrating the main events within the program.
The dotted boxes are added for clarity and are not program events. The flow chart
is actually a description of the “main()” function of the device program. After
starting the program within the Linux operating system, the hardware (digitally
controlled ICs) and calibration tables are first initialized. Initialization need only
be done once. The calibration table values are stored in a file called
‘calibration.dat’, and were obtained from previous device measurements. The
method o f doing this will be discussed in the next chapter.
After initialization, the GTK+ commands are called and an X-window is
created. Attenuation (horizontal) and phase (vertical) scales are added with cursor
position markers. The desired attenuation and phase values for channels 2 to 16
are selected by left clicking at any point within the window. The selected values
are marked by a rectangular dot within the window. A single dot will have an xvalue corresponding to its attenuation and a y-value corresponding to its phase.
An example o f this type o f window is given in Figure 6.14. The full window will
be shown in the next chapter.
A soon as an input value (magnitude and phase) is selected it is converted
to its corresponding digital values by comparing them with values from the
calibration tables and is used to activate the respective circuit components. The
magnitude and phase o f the sampled RF output are digitized and compared with
actual values in the calibration tables. These measurements are sent to the GTK+
window to be displayed alongside the already displaying desired values. In this
way, an immediate check of the accuracy o f the device may be obtained. Another
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128
START
Initialize
Hardware
Set
Channel 1
IS dB attn
0° phase
Initialize
Calibration
Tables
Set Phase of
other channels
Set Attn of other
Channels
Open Xwindow and set
horizontal
(magnitude)
and vertical
(phase) scales
Use the mouse
to select
desired
magnitude and
phase settings
Search Magnitude
calibration table for
control value
Search Phase
calibration table for
matching value
Send control value
to input/output
expander
Send value to
input/output
expander
Convert to analog
voltage by DAC
Set 5-bit attenuator
control
Set desired phase
Set desired
attenuation
RF Output
Directional
coupler
Sensed
Magn& Ph
Display
Values
Antenna
probe values
Convert
values
Convert
values
END
Figure 6.13
Flow chart of controller program
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129
Figure 6.14 An example of a GTK+ window with horizontal and vertical scales.
check is achieved when the values read by the antenna probe is displayed. This
value should match both the desired and feedback values. Therefore the window
will contain two different screen markers for each magnitude and phase pair. The
first one is the desired value that was initially entered, and the second is the
feedback (sampled).
6.7
CONCLUSIONS
The design and construction of a 4 x 4 phased array antenna device and a
microwave antenna probe have being presented. The operation of the controller
software has also been discussed.
The architecture used in this design was extremely successful. RF pickups
were negligible and the input and output impedances of the phase shifters and
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130
attenuators remained constant during phase and magnitude variations. Channel
shielding was very simple; each channel was enclosed by grounded partitions that
effectively prevent RF interferences. That is, each channel was effectively selfcontained and separated from each other.
An antenna probe was designed and constructed and is to be used for
verification o f signals at the antennas. It has high input impedance at the operating
frequency o f 1 GHz. This means that during measurements, the electrical
characteristics o f the antenna elements will not be significantly affected.
The testing and measurements for this device and its probe are discussed
in the next chapter.
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131
Chapter 7
Device Specifications, Calibration and Test
Measurements
7.1
DEVICE CHARACTERISTICS
The characteristics and limitations of the 4 x 4 phased array device are
determined from those o f the discrete components from which it is made. For
example, the absolute maximum power supply voltage for the device is equal to
that o f the component that has the lowest of the absolute maximum power supply
voltage values. Other values such as input dynamic range, operating frequency
range, etc., are determined in a similar manner. Table 7.1 shows the relevant
characteristics o f each component as stated by the manufacturers.
From Table 7.1 it is seen that the phase-gain comparator chip, AD8302,
has a maximum power supply voltage o f 5.5 volts, which is the smallest value in
the table. This means that the device “5 volt” power supply must not exceed 5.5
volts, otherwise the phase-gain comparator chip will be damaged. Actually, the “5
volt” power supply value was set to 5.2 volts and is generated from the 17 V line.
Recall that the 17 volts powers the RF amplifiers and op amps and is far below
their absolute maximum values. The 5.2 volts ensures that the reference voltage of
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132
Table 7.1 Discrete component characteristics at room temperature
Type
Device discrete
surface mount
components
(part number)
Operating
frequency
range
Phase shifter
(JSPHS-1000)
0.85 - 1
GHz
Max. input
RF Power (50
ohm system)
dBm
(mW)
DC Power
supply
(Volts)
Min
Max
20
(100)
0 -1 5 V for
phase control
0 .7 -3 .7
GHz
24
(251)
3-5
8
13
(20)
7
20
Directional coupler
(ADC-6-13)
DC-4
GHz
0 .2 -1 .3
GHz
27
(500)
-
Phase-gain comparator
(AD8302)
0.1 - 2 .7
GHz
10
(10)
2.7
5.5
Digital
Input/output expander
(PCF8574)
SCL clock
100 kHz
-
2.5
7
Digital
12-Bit DAC
(DAC7611)
Clock
20 MHz
-
4.75
6
Digital
8 -B it ADC
PCF8591
SCL clock
100 kHz
-
2.5
8
Parallel port driver
(74LS05)
Pulse rate
(ns)
DC - 0.030
-
5
7
Digital
Multiplexer
(PCA9540)
Clock freq.
0 -400 kHz
-
1.8
7
DC
Op amps:
(TL3472)
Bandwidth
DC—4 MHz
-
4
36
(LM324)
DC-1 MHz
-
3
32
RF
RF
5-Bit attenuator
(HMC273MS1OG)
RF
Rf Amplifier
(GAL-33)
RF
RF
Digital
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133
the ADC is always higher than its maximum analog input. This analog input, 0 5 volts, is the amplified output o f the phase-gain comparator (0 - 1.8 V).
Amplification was done using fixed-gain op amps. The gain o f the amplifier was
such that its maximum output voltage was 5.1 volts. Since this is higher than the
original reference voltage of 5 volts, errors were introduced in the analog to
digital conversion. That is, all outputs of 5 volts or greater would be given the
same digital value o f 255 (since it is an 8-bit ADC, the digital values ranges form
0 to 255). Raising the supply voltage to 5.2 volts effectively raised the reference
to 5.2 volts, thus fixing this problem. In this way, no additional wires or circuitry
was added to the device.
It can also be seen from the table that the operating frequency range o f the
device is determined by that o f the phase shifter, and ranges from 850 to 1000
MHz. All other RF components exceeded this range.
The digital devices are
operated far below their maximum clock speeds. However, their maximum speed
is limited to 100 KHz, the speed o f the I2C clock.
The maximum input RF power to the device is not easily determined from
Table 7.1. Although the phase-gain comparator has the minimum value o f 10
dBm, that does not mean that it will be the limiting value. There are other factors
that affect its value and they are discussed in the next section.
7.1.1 Determination of Input Signal Power
To prevent damage to the device, it is imperative to determine the
maximum allowable input signal power and power supply voltages. As explained
in the previous section, the power supply voltage was set to 17 volts dc for the
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134
amplifiers and 5.2 volts for all other components. However, determination o f the
maximum RF signal power is a little more involved.
A 1 GHz signal at -15 dBm was connected to the input o f the device. The
signal was traced and measured at each stage along the device circuitry. Figure
7.1 is a block diagram o f the RF path through Channel 1 of the device. The
absolute magnitudes at points A, B, C, D, E, F, G, H and I were measured and
recorded as shown. From these measurements, the gain of each block was
determined. In this setup the attenuator was set for minimum attenuation (control
= 31); therefore only its insertion loss would be recorded. All measurements were
taken with a network analyzer. The gain o f each stage as obtained from Figure 7.1
is shown in Table 7.2.
Phase
shifters
RF
I/P
Directional
Coupler
Attenuator
to ant.
RF Amp 1
16-way
RF
Splitter
(1 of 16 channels)
RF Am p 2
16-way
Splitter
for R ef
1 o f 16 Ref signal
(to phase-gain comparator)
A = -15 dBm
D = -40 dBm
G = -31 dBm
B = -31 dBm
E = -23 dBm
H = -14 dBm
C = -36 dBm
F = - 26 dBm
I = -30 dBm
Figure 7.1 RF path through the device.
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135
A m p lifie r
2 is used to compensate for the 16 dB loss in the reference
signal 16-way divider.
Table 7.2
RF gain for each stage
Components Stage
Gain
Input RF 16-way splitter (A to B)
-16 dB
0 - 360° phase shifter (B to C)
-5 dB
Attenuator insertion loss (C to D)
-4 dB
RF Amplifier 1 (D to E)
+ 17 dB
Directional coupler
(a) Direct feed through port (E to F)
(b) Coupled port (E to G)
(a) - 3 dB
(b) - 8 dB
RF Amplifier 2 (G to H)
+ 17 dB
Reference 16-way splitter (H to I)
-16 dB
As previously mentioned in Chapter 5, for proper operation of the phasegain comparator, the reference signal at I must be set to -30 dBm. As seen in
Figure 7.1, an input power o f -15 dBm will set the reference signal to -30 dBm
whenever the channel is set for zero attenuation. Since Channel 1 is used to
generate this reference signal, any change in its attenuation must be compensated
for by an opposite change in the input signal power so that -3 0 dBm is maintained
at I.
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136
From the above discussion, it can be seen that the minimum input power
for proper operation o f the device is -15 dBm, and the maximum would be +15
dBm, to compensate for the 30 dB attenuation in channel 1. From Figure 7.1, a
+15 dBm input would set point B to -1 dBm. Going back to Table 7.1, it can be
seen that all RF component maximum ratings are above -1 dBm, therefore, a +15
dBm input is safe.
It is always good to know the absolute maximum power input that a
device can withstand without damage. This value may be calculated by placing
the values in Table 7.1 into their respective points in Figure 7.1 and adding back
the circuit losses until to input power is calculated. Using this method, the phase
shifter was found to be the limiting component. By placing its value of +20 dBm
(from Table 7.1) at point B in Figure 7.1, the maximum possible input power was
calculated to be 36 dBm (20 dBm + 16 dB).
7.1.2 Total Power consumption
During operation, the device pulls 1.2 amperes o f current from a 17 volt
DC source. That is, it uses 20.4 Watts o f power. That’s approximately 1.3 Watts
per channel; however, most of this power is consumed within the RF amplifiers.
7.2
CALIBRATION
Once the above characteristics were verified, the device was calibrated.
Channels 2 to 16 were calibrated with respect to Channel 1. As mentioned before,
Channel 1 was set to a fixed attenuation control value of 15 and phase shift o f 0°.
A network analyzer was used to provide a 1 GHz, -5 dBm signal to the input of
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137
the device and to measure successively the outputs at each channel while their
magnitudes and phases were varied. A special calibration program, written in C
programming language, was used for magnitude and phase variation. The
calibrated values were recorded and stored in a file called “calibration.dat” which
may be accessed by the main controller program. The file consists o f 32
attenuation and 64 phase measurements for channels 2 to 16. Each set of
measurements has five columns; namely, digital control value, digital value of
magnitude feedback, digital value of phase feedback, measured magnitude value,
and measured phase value. As an example, the magnitude and phase calibration
values for Channels 6 are given in Tables 7.3(a) and 7.3(b).
The digital control value for magnitude measurement ranges from 0 to 31,
corresponding to the 5-bit control o f the digital attenuators. That for phase ranges
from 0 to 4095, corresponding to the 12-bit digital-to-analog controller for the
phase shifter. The feedback values for both magnitude and phase range from 0 to
255, corresponding to the 8-bit analog-to-digital converters. The measured values
were obtained from the network analyzer. The program was stepped through and
the measured values were recorded. Examples of these calibration values for
Channels 2 and 6 (randomly selected) are shown in Figure 7.2. These values were
measured with respect to Channel 1, which is set for zero phase change and an
attenuation control o f 15. With respect to the test setup (length of coaxial
connecting cables, etc.) the actual measured output of Channel 1 was -23 dB and
-37 0 for the magnitude and phase respectively. Therefore, for the -5 dBm input
signal power, the absolute output magnitude o f channel one was -28 dBm. The
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138
250
200-
9toS
T<JD
&
~Q
o>
U
_C
a.
.
o
<0
-Q
Ta>
J
a>
Ll_
100
50 -
1-------------- 1-------------- .--------- 0 -15
-10
-5
0
5
10
15
-1B0
20
•120
-60
0
60
120
160
Relative p h a se shift (degrees)
Relative m agnitude (dB)
(ii)
(i)
(a)
250
200
O
(0J
X
"<D
.SD
>
♦ ♦
^
8(0
150'
.c
Q.
O
xt(U
d<D
>
Li_
100 -
D
(0>
5
T3
...........................
50 -
---------------- ,--------------- ,-----------0 -15
-10
-5
0
5
10
15
20
•160
Relative magnitude (dB)
-120
-60
0
60
120
Relative phase shift (degrees)
(ii)
(i)
(b)
Figure 7.2 Plots o f magnitude and phase calibration values for Channels 2 and 6:
(a) Magnitude and phase plots for Channel 2 calibration values; (i) Magnitude
feedback versus relative output magnitude; (ii) Phase feedback versus relative
output phase; (b) Magnitude and phase plots for Channel 6 calibration values; (i)
Magnitude feedback versus relative output magnitude; (ii) Phase feedback versus
relative output phase
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139
outputs o f the other channels were calibrated with respect to these values under
the same test conditions. During the calibration o f any one channel, all other
channels, with the exception of Channel 1, were set to zero attenuation and zero
phase shift.
The controller program uses the “calibration.dat” file to set the relative
output phases and magnitudes o f each channel as specified by the desired input
values. It also uses the table to convert the feedback values from its digital form to
actual magnitude and phase values. In this way, the control values may be easily
varied until the desired feedback is obtained, indicating the magnitudes and
phases at the outputs. A detailed explanation of this is given in the next section.
7.3
SETTING THE OUTPUTS
The device was connected to a 17-volt power supply and the parallel port
of the computer containing the control program. A network analyzer was used to
supply a 1GHz input signal at -5 dBm, and to measure the magnitude and phase
at the output o f each channel. Table 7.3(a) and 7.3(b) show the actual calibration
values for Channel 6. The values for the other channels are similar. These tables
will be used in explaining how the actual outputs o f the device are obtained. Also,
to assist in this explanation, code fragments from relevant sections of the main
controller program (Appendix A) will be inserted. Particular attention was given
to the trend o f the values in the table (calibration values). This was very important
to the development o f the program.
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140
The control columns in the tables consist o f the actual values required by
the circuit components to effect the corresponding changes in magnitude and
phase. The attenuator can only have a maximum of 32 values (25) ranging from 0
to 31, corresponding to its 5-bit digital control. The phase control may be varied
Table 7.3
Magnitude and phase calibration values for channel 6
(a) Magnitude calibration values
Control
(0-31)
Magnitude
Feedback
(0 - 255)
Phase
Feedback
(0-255)
Measured
Magnitude
(dB)
Measured
Phase
(degrees)
0
2 1 2
1 7 6
- 3 5 . 7
- 2 . 0
1
2 0 7
1 8 6
- 3 4
- 8 . 0
2
2 0 3
1 9 1
- 3 4 . 1
- 1 4 . 0
3
1 9 9
1 9 8
- 3 3 . 1
- 1 7 . 0
4
1 9 2
2 0 2
- 3 1 . 8
- 2 2 . 0
5
1 8 8
2 0 4
- 3 0 . 7
- 2 5 . 0
6
1 8 4
2 0 6
- 2 9 . 8
- 2 7 .
7
1 8 0
2 0 9
- 2 8 . 8
- 3 0 . 0
8
1 7 4
2 1 1
- 2 7 . 4
- 3 2 . 0
9
1 7 0
2 0 9
- 2 6 . 4
- 3 3 . 0
1 0
1 6 6
2 0 7
- 2 5 . 4
- 3 5 . 0
1 1
1 6 1
2 1 2
- 2 4 . 3
- 3 5 . 0
1 2
1 5 6
2 1 2
- 2 3 . 0
- 3 7 . 0
1 3
1 5 2
2 1 2
- 2 2 . 1
- 3 7 . 0
1 4
1 4 9
2 1 5
- 2 1 . 1
- 3 9 . 0
1 5
1 4 5
2 1 2
- 2 0 . 1
- 4 1 . 0
1 6
1 3 6
2 2 4
- 1 8 . 1
- 4 6 . 0
1 7
1 3 3
2 2 4
- 1 7
- 4 7
1 8
1 2 9
2 2 7
- 1 6 . 2
- 4 7 . 0
. 9
. 2
0
. 0
1 9
1 2 5
2 2 6
- 1 5 . 3
- 4 7 . 0
2 0
1 2 1
2 2 2
- 1 4
. 1
- 4 7 . 0
2 1
1 1 7
2 2 2
- 1 3 . 2
- 4 7 . 0
2 2
1 1 3
2 2 0
- 1 2 . 2
- 4 7 . 0
2 3
1 1 0
2 2 2
- 1 1 . 3
- 4 8 . 0
2 4
1 0 5
2 1 6
- 1 0 . 3
- 4 5 . 0
2 5
1 0 2
2 1 6
- 9 . 3
- 4 4 . 0
2 6
9 8
2 1 4
- 8 . 5
- 4 5 . 0
2 7
9 5
2 1 6
- 7 . 5
- 4 5 . 0
2 8
9 0
2 1 2
- 6 . 4
- 4 3 . 0
2 9
8 7
2 1 1
- 5 . 5
- 4 3 . 0
3 0
8 3
2 1 0
- 4 . 6
- 4 3 . 0
3 1
7 9
2 0 9
- 3 . 7
- 4 3 . 0
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141
(b) Phase calibration values
Control
(0 - 4095)
0
64
128
192
256
320
384
448
512
576
640
704
768
832
896
960
1024
1088
1152
1216
1280
1344
1408
1472
1536
1600
1664
1728
1792
1856
1920
1984
2048
2112
2176
2240
2304
2368
2432
2496
2560
2624
2688
2752
2816
2880
2944
3008
3072
3136
3200
3264
3328
3392
3456
3520
3584
3840
3904
3968
4032
Magnitude
Feedback
(0 - 255)
212
211
212
211
212
212
211
212
211
208
208
208
208
207
207
207
207
207
206
207
207
207
207
206
206
204
203
202
202
199
200
201
202
203
204
205
206
207
209
209
211
211
212
213
214
215
215
215
216
216
216
217
219
217
219
219
220
219
220
220
220
Phase
Feedback
(0 - 255)
179
176
170
164
158
152
145
139
132
123
115
106
96
92
82
72
63
51
35
17
7
5
12
28
46
64
81
100
117
134
148
162
174
185
195
207
216
221
231
237
244
247
250
251
249
248
246
241
238
233
230
225
219
214
211
206
189
185
181
175
171
Measured
Magnitude
(dB)
-35.8
-35.8
-35.8
-35.8
-35.7
-35.8
-35 .7
-35.8
-35.6
-34.9
-34.9
-34.9
-34. 9
-34.9
-34.9
-34.9
-34.9
-34.9
-34.9
-34.6
-34.9
-34.9
-34.9
-34.7
-34.7
-34.2
-34.1
-34.1
-34.1
-33.1
-33.5
-33.5
-34.0
-34.1
-34.2
-34.4
-34.7
-34.9
-35.1
-35.1
-35.5
-35.5
-35.7
-35.9
-36.1
-36.2
-36.2
-36.2
-36.5
-36.5
-36.5
-36.7
-37.0
-36.7
-36.8
-36.7
-37.8
-36.8
-37.0
-37.0
-37.0
Measured
Phase
(degrees)
-5.0
-3.0
0.0
3.0
5.0
9.0
11.0
14 .0
19.0
22.0
26.0
29.0
33.0
37 .0
43.0
48.0
54.0
59.0
67.0
75.0
83.0
93.0
104.0
115.0
128.0
139.0
153.0
165. 0
177 .0
-170.0
-159.0
-148.0
-138.0
-128.0
-119.0
-112.0
-103.0
-97.0
-89.0
-83.0
-75.0
-71.0
-66.0
-61.0
-57 .0
-52.0
-47.0
-44.0
-40 .0
-35.0
-32.0
-29.0
-26.0
-23.0
-21.0
-18.0
-8.0
-6.0
-3.0
-1.0
1.0
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142
from 0 to 4095 and corresponds to the 12-bit DAC. It would be impractical to
vary the phase control in too small a step, so steps of 64 were used.
The input magnitude and phase values of the device are selected by
clicking at any random point within a pre-scaled input X-window. Each point
(little square block) simultaneously corresponds to a relative magnitude (xcoordinate value) and a phase (y-coordinate value). The program is adjusted so
that all input selections are relative to Channel 1 settings. Figure 7.3 shows an
example o f this input X-window when all input values were randomly selected.
Figure 7.3
An example of the input X-window.
The control o f the magnitudes and phases are done separately within the
program. This means that one of these values will be executed before the other.
The question is, which to do first? The answer to this was not very obvious at
first, but after doing some test runs and working out some bugs in the program, it
became apparent that the magnitude must be set before the phase. The reason is
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
143
right there in the calibration tables. Note that in the measured phase column of the
magnitude table in Table 7.3(a), there is a significant phase change associated
with magnitude changes. On the other hand, from observation of the phase table
in Table 7.3(b), it is seen that the magnitude in the measured magnitude column
changes very little over the full 360° phase change. Therefore, by first setting the
required output magnitude value, the phase offset (phase lag) introduced may be
compensated for when the program is setting the phase output value, without
causing any significant changes in initial magnitude value.
During program startup the calibration tables and the device hardware are
first initialized. Initialization is down only once, so its command is placed in the
main function o f the controller C program. The initialization of the calibration
tables assigned names to the relevant columns and consecutive numbers to the
rows. In this way any value may be read by its row and column location. The
most convenient way to do this is to make a “struct” (or structure) assignment.
The actual assignments is shown the following program code fragments:
P rogram fra g m en t 1:
struct CalibrationData
float setting;
int feedback;
int control;
{
/* real world measurement */
/* corresponding digital representation */
/* digital output to effect real world value */
In­
struct
{
struct CalibrationData m a g n i t u d e [32];
struct CalibrationData phase[64];
} calibration[16];
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144
Program fragment 1 shows the naming of the columns o f both tables as
setting, feedback, and control, as will be used by both the magnitude table,
containing 32 rows, and the phase table, containing 64 rows. The program is set to
accommodate a total o f 16 channel calibrations, although only 15 are used.
P rogram fragm en t 2:
for
(i = 1; i < 16; i++)
{
/* ... read magnitude calibration */
for
(j = 0; j < 32; j++)
fscanf(fp,
fscanf(fp,
fscanf(fp,
fscanf(fp,
fscanf(fp,
"Id",
"%d",
"%d",
"%f",
”%f",
{
& (calibration[i].magnitude[j].c o n trol));
& (calibration[i].magnitude[j].feedback) );
iitemp);
& (calibration[i].magnitude[j].setting) );
Sftemp);
}
/* ... read phase calibration */
for
(j = 0; j < 64;
fscanf(fp,
fscanf(fp,
fscanfffp,
fscanf(fp,
fscanf(fp,
j++)
”%d",
"Id",
"Id",
"If",
"If",
(
& (calibration[i].phase[j].con t r o l ));
Sitemp);
& (calibration[i].phase[j ].feedback));
sftemp);
& (calibration[i].phase[jJ.setting));
)
}
Code fragment 2 shows the assignment of the columns of each table. The
itemp and ftemp columns are not used. For the magnitude table, its control
column is assigned the name “control,” its magnitude feedback column is
assigned the name “feedback,” and its measured magnitude is assigned the name
“setting.” Similarly, for the phase table, its control column is assigned the name
“control,” its phase feedback column is assigned “feedback,” and its measured
phase column is assigned “setting.” In both tables their channel number is
represented by the value ‘i’ and the row number by the value ‘j ’.
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145
7.3.1 Setting the Output Magnitude
Once the desired magnitude is entered, the “setmagnitude” function starts
the process o f setting the output magnitude. The input is first converted to the
format o f the values in the calibration table. A search is made to find the closest
matching “setting” value. Once this is found, the corresponding control value is
read. This value is then used to set the required amount o f attenuation o f the
attenuator chip so that the desired output is obtained. Because of the discrete
nature o f the attenuators, sometimes the exact magnitude may not be obtainable.
In these cases the closest value is selected.
Once the output is set, a feedback value is generated from the phase gain
comparator. This value is matched in the feedback column o f the magnitude table
and its matched “setting” value is found. This setting value should correspond to
the desired input value and is an indication o f the accuracy o f the device.
For example, if the desired relative output magnitude for Channel 6 was
+9 dB relative to the reference (-23 dB), a search would be made for the value of
-23 + 9 = -14 dB in the calibration magnitude table for Channel 6. This table is
shown in Table 7.3(a). In is seen that the closest matching value is -14.1 dB. The
program would identify this value as “calibration[6].magnitude[20].setting. It will
then identify the matching control value as “calibration[6].magnitude[20].control”
to be equal to 20. The 5-bit binary value for 20 (binary 10100) would be sent to
the control pins o f the attenuator chip, where its attenuation value would be set so
that its output is 14.1 dB. Note that control value = 31 gives 0 dB attenuation,
while control value = 0, gives maximum attenuation. The corresponding
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146
magnitude feedback value is “calibration[6].magnitude[20].feedback” which
corresponds to the value 121 from the table.
Because o f the monotonic nature of the values in the feedback and setting
columns, manipulating the output magnitude was relatively simple. A visual
inspection o f Table 7.3(a) shows that the “feedback” (magnitude feedback)
steadily decreases from 212 to 79 while “setting” (measured magnitude) steadily
increases from -35.7 to -3.7 dB. The magnitude values are all relative to the input
-5 dBm level o f the network analyzer. This means that the absolute output
magnitude range is -40.7 to -8.7 dBm, if connecting cable losses in the test setup
are neglected.
7.3.2 Setting the Output Phase
A similar search is done in the phase table to match the desired output
value. The matching control value is used to set the output value of the 12-bit
ADC chip, which would produce a phase shift matching that in the table.
However, there is an inherent phase offset caused from setting the magnitude.
This offset is always a phase lag. This means that the phase at the output will not
correspond to the matching value in the phase table, but to a previous value, i.e. a
value that comes before it in the table. This is immediately seen in the value o f the
phase feedback. To get the correct output phase, the control value is gradually
incremented until the expected phase feedback value is found. Let us explain this
by an example.
Using Table 7.3(b), if an output phase of 128° is desired at Channel 6, the
program will search Channel 6 calibration table (i = 6) and will find a setting
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147
match o f 128° at “calibration[6].phase[20]. setting.” That is, 128° is found at the j
= 20 position in the calibration table for Channel 6. It will move across and find
the corresponding control value, “calibration[6].phase[20].control”, o f 1536. This
value is converted to a serial 12-bit binary value and sent to the ADC phase
controller chip (via the i/o expander), where the required phase shift is produced.
If all goes well, a phase feedback of 46, “calibration[6].phase[20],feedback”,
should be seen. But the attenuator for Channel 6 may not be set for maximum
attenuation and thus would caused an additional phase shift (phase lag). Other
circuit or environmental conditions may cause this effect as well.
Suppose the magnitude were set for 14.1 dB, as in the previous example,
so that a phase lag o f -2° - (-47°) = 45° is to be expected. This is obtained by
taking the difference o f the phase shift at control = 0 and that at control = 20 in
the magnitude table. Therefore, the output phase will be 128° - 45° = 83°. From
the phase table, 83° will produce a feedback of 7. Therefore, the program will see
a feedback value o f 7, and will immediately know that the desired output phase
has not been achieved. It will then start increasing the control value from 1536 in
predetermined increments, say 12, for example, until the feedback of 46 is
obtained. Extreme care must be taken at this point. Small enough increments must
be used to ensure that the actual value of 46 is obtained (and not passed over).
However, the smaller the increment, the longer the program takes to set the
output. On the other hand, if large increments are used and a range o f say 43 to 49
(i.e., 46 +/- 3) is set as the required value, the output phase may not be set to the
exact required value and deviations as much as 20° may be obtained. Thus,
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148
tradeoffs are required. The implementation o f this may be seen in the full program
in Appendix A.
Many other techniques of setting the output phase based on the feedback
value were tried, but they were not valid for all possible input selections. This is
because one actual feedback value corresponds to two different phase shifts. That
is, a phase shift from -180° to 0° to +180° corresponds to a feedback value o f 0 to
255 to 0. It is extremely difficult for the program to know which feedback value is
preferred in all possible cases.
One such technique that we tried was to assume that all phase offsets are
caused by the attenuators.
These offsets were obtained from the magnitude
calibration tables and added to the input phase before the output is set. The phase
feedback
column
of
the
“calibration[i].magnitude[j].offset”.
magnitude
The
table
phase
lag
was
was
labeled
represented
as
as
“calibration[i].magnitude[0].offset - calibration[i],magnitude!]].offset”, and was
added to the input phase value. So, in the previous example, instead o f searching
for 128°, we would search for 128° + 45° - 165°. The phase controller DAC will
then be set to a value o f 1728 (from Table 7.3(b)) and not 1536. However, there is
no sure way o f checking the phase feedback value for accuracy.
7.4
MEASUREMENTS AND RESULTS
7.4.1 Testing with 50-ohm terminators connected to the outputs
The device was once again connected to a 17-volt power supply and the
parallel port o f the computer containing the control program. The output of each
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149
channel was terminated with a 50-ohm load (not the antennas). A network
analyzer was used to supply a 1GHz input signal at -5 dBm, and to measure the
magnitude and phase at the output o f each channel. Channels 2 through 16 were
tested using the feedback tracking method discussed in the previous section. All
inputs were randomly entered. The output of each channel was individually
recorded and plotted against the input values. Figure 7.4(a) shows a plot of the
desired magnitude (or inputs) versus actual (or measured) output magnitudes, and
Figure 7.4(b) shows a plot of the desired phase (or inputs) versus actual (or
measured) output phases. All values shown are relative to the reference values of
Channel 1. The straight lines shown represent the ideal case, for which the inputs
are exactly equal to the outputs. The diamond-shaped points show the measured
output values corresponding to the input values marked by the smaller square
boxes. All input values he on the ideal line.
The phase test results for channels 3 to 16 were very similar to those of
Channel 2. The highest phase deviation measured during any o f the phase tests
was 12 degrees and occurred for Channel 7. O f all the output phase
measurements, 80 percent were within ± 5° of the desired phase values, and 15
percent were within ± 8°. The other 5 percent of measurements varied from ± 9°
to ± 12° o f the desired output values. A more rigorous controller program may be
used to reduce the large phase variations.
The magnitude test results for ah channels were similar to those o f Figure
7.4(a). The largest measured magnitude deviation from the desired value was 1.8
dB. However, most measurements were within ± 0.5 dB. Deviations in excess of
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'
w
_10
a
Input relative magnitude (dB)
-15 -
(a)
180
ideal
u>
120
a.
-180
-120
-60
60
-60
120
180
-
Input p h a se (degrees)
-120
-
-180
(b)
Figure 7.4
Test results for Channel 2 relative to the reference, for 50 Q loads
(a) Input magnitude versus its measured output (b) Input phase versus its
measured output.
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151
± 0.5 dB were mainly caused by the slight magnitude variation during phase
changes.
In the above phase and magnitude tests, while measuring a particular
output, all other outputs were connected to 50 Q terminators instead o f the patch
antennas. The main reason for doing this was to maintain constant output
impedance across all channels while measuring with the 50 Q port network
analyzer. The patch antennas have an input impedance o f 20 Q. Ideally, they
should be 50 Q, but such designs are not yet available.
However, the device may be tested with the antennas connected. The
actual signals at the antennas may be represented by the feedback measurements
and displayed in the same window with their input values. The accuracy of these
feedback values may be compared with that obtained from the phase and
magnitude feedback measurements in the above setup.
Once again, the results obtained for Channel 2 may be used to represent
the average trend in feedback measurements for all the channels. Figure 7.5 (a)
and 7.5 (b) are magnitude and phase plots of the feedback values versus the
measured outputs. In this case the straight line represents the ideal case, for which
the measured and feedback values are equal. The vertical distance between the
feedback and measured value indicates the amount of deviation. It can be seen
from Figure 7.5(a) that the feedback phase value is a very close representation of
the measured value. However, deviations in excess of 2 dB were obtained for the
feedback magnitude measurements.
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152
15
m
■o
10
cU)
(0
JoXL
<0
.Q
T0J)
<1)
-
5 -
-15
-10
-5
ideal
v
»
10
?
15
-5
Measured output magnitude (dB)
#*
-♦
-10
-15
(a)
180
ideal
d>
CD
T3
120
-
Q.
60 -
T>
-180
-120
120
-60
180
-60
Measured output phase (degrees)
-120
-
-180
(b)
Figure 7.5
Test results for Channel 2 relative to the reference, for actual loads
(a) feedback magnitude versus its measured output (b) Feedback phase versus its
measured output.
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153
7.4.2 Testing with the antennas connected to the outputs
All the antennas were connected to their respective outputs. Random
magnitude and phase values were entered and their corresponding feedback
values were displayed beside them. Figure 7.6 is a screen shot of the input and
outputs values displayed in the same X-window. The smaller squares are the
inputs. The horizontal axis is the relative magnitude in dB while the vertical axis
is the phase in degrees. The difference in the value of the feedback magnitude
versus its input value may be obtained by using the magnitude scale to
measure the horizontal separation between the block pairs. Similarly, the phase
difference may be obtained by using the phase scale (vertical) to measure the
vertical separation between the block pair. Each block pair is connected together
by a dotted line and represents the input and output values for the channel shown
in brackets.
From the figure, it is seen that very good phase matching was obtained for
all channels; however, over 2 dB magnitude deviations were obtained for
channels 12, 8, 7, and 16. The accuracy o f these feedback values depends on their
actual manipulation within the controller program. A measure of this accuracy
may be obtained by comparing these values with those obtained in Figure 7.5,
where the actual measured values were compared against the feedback, thus
indicating the accuracy o f the feedback. From this comparison it can be seen that
large magnitude deviations were to be expected.
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154
S i Dtvice:otit
(16)
(13)
( 10)
(14)
( 12)
(11)
Figure 7.6
Screen shot o f input and output phase and magnitude
measurements with all antennas connected. The dotted lines are drawn in to show
each input (small block) output pair for the corresponding channel number (in
parentheses).
We may thus conclude that the result shown in Figure 7.6 is a true
indication o f the relative output magnitudes and phases.
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155
7.5
MEASUREMENT WITH THE RF PROBE
The RF probe (see Chapter 6) was used to probe each antenna. Its output
was connected to the network analyzer so that any variation in phase and
magnitude may be observed. The magnitude and phase o f each channel were
varied while the surface o f the output antenna was probed.
All phase and magnitude variations were observed. However, the
magnitude varied over a 10 dB range instead of the 30 dB obtained when the
channel outputs were measured directly (without antennas). The reason for this
was previously outlined in Chapter 6. The output signal from each channel is
divided between the series capacitor (used for tuning) and the patch antenna.
At times, the measurements taken by the probe were erratic. This was
expected since the presence o f a moving grounded object so close to the antennas
causes variation in the antenna’s electrical properties. Because of this, no actual
probe measurements were recorded.
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156
Chapter 8
Compensating for Mutual Coupling
The final application of the 4 x 4 phased array driver described in the
previous chapters is to test a newly proposed approach that exploits mutual
coupling among patch antenna elements. The physical design of these antennas
will be such that mutual coupling between antenna elements is enhanced at the
frequency o f operation. However, this coupling will affect the magnitudes and
phases o f the signal in each patch antenna element. The desired relative
magnitude and phase values at the antenna elements are affected by the coupling
and need to be changed to maintain beam steering accuracy.
To deal with this effect, the controller program for the device was
designed to compensate for the coupling. Through a series o f iterations, the
desired output values may be set, measured, reset, and re-measured as many times
as necessary to maintain output accuracy.
In this chapter, a technique used to study mutual coupling effects between
neighboring patch antenna elements is outlined. The modifications to the
controller program that allow the device to compensate for these effects, and an
example o f its application to a 4 x 4 patch antenna array, are also discussed.
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157
8.1
COUPLING
BETWEEN
TWO
PATCH
ANTENNA
ELEMENTS
A single antenna element of the 4 x 4 patch antenna array was connected
to the output of channel 2 of the phased array driver device and its relative
magnitude and phase values were set to 19 dB and 0° respectively, while its
feedback magnitude and phase values were being monitored. These values are
relative to the reference signal in channel 1. A neighboring antenna element was
connected to the output of another channel and its magnitude and phase were
varied over 30 dB (in 5 dB steps) and 360° (in 45° steps), respectively, while
observing the magnitude and phase feedback o f the first antenna. All unused
channels were terminated in 50-ohm resistive loads to eliminate any interference.
Figure 8.1 shows magnitude versus phase plots of the signal measured at
channel-2 output. Figure 8.1(a) shows the deviation in magnitude and phase
values at the first antenna when the magnitude at the second antenna is varied
over 30 dB, while keeping its phase constant at 0°. Similarly Figures 8.1(b),
8.1(c), and 8.1(d) show deviations caused when the second antenna magnitude is
fixed at 19 dB and its phase is varied, magnitude is fixed at -12 dB and its phase
is varied, and its phase is fixed at 180° while its magnitude is varied, respectively.
Figures 8.1(a), 8.1(b), and 8.1(c) show significant deviation in both
magnitudes and phases. The maximum deviation in magnitudes occurred in
Figure 8.1(c). This was to be expected since the magnitude difference between the
two antennas was at a maximum (30 dB), thus promoting strong mutual coupling.
Figure 8.1(d) shows the least amount of deviation.
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158
1
♦
■o
CD
(0
c
5
>
Ta>
CD
+
0 .5
0 .5 -
-♦---- 9♦
c
D)
(0
2
o>
-0 .5
P h a se variation (d e g re e s)
-0 .5 ■
P h a se variation (degrees)
(a)
~o
CD
3
C
D>
(0
2
TJ
CD
0 .5 -
c
o
<D
(b)
0 .5 -
♦ ♦
-♦114-------# -
-5
T3
-0 .5 -
P h a se variation (d e g re e s)
(c)
- 0 .5 -
P hase variation (degrees)
(d)
Figure 8.1
Magnitude and phase deviations at the antenna connected to
channel 2 whenever the magnitude and phase of its adjacent antenna is varied in
steps o f 5 dB and 45 degrees, respectively: (a) Magnitude is varied over 30 dB
while phase remained fixed at 0°; (b) Magnitude is fixed at 18 dB while phase is
varied over 360°; (c) Magnitude is fixed at -10 dB while phase is varied; (d)
Magnitude is varied while phase is fixed at 180°.
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159
These measurements effectively demonstrate the effect each antenna has
on its neighbors and illustrates the need for a feedback control mechanism. The 4
x 4 phased array driver has been designed with such a feedback control
mechanism. By constantly measuring and readjusting the relative magnitude and
phase values at each antenna, the desired output values may be obtained.
8.2
COMPENSATING
FOR
MAGNITUDE
AND
PHASE
VARIATIONS
The controller program of the 4 x 4 phased array driver was modified to
compensate for any magnitude and phase variations at its outputs. It does this by a
series o f iterations within the main program. The desired values are first set for
each antenna element and the actual values at the antennas are measured by the
feedback mechanism. Because of mutual coupling and other effects, the feedback
measurements do not normally match those expected for the desired outputs.
Whenever this happens, the program adjusts the output magnitude and phase
control values until the desired feedback values are obtained. This process
continues until all outputs are set to their desired values. This process is shown in
the flow chart o f Figure 8.2. Since the feedback values are generated from an 8-bit
analog-to-digital controller, its actual value will range from 0 to 255, or 28 values.
The procedure for setting the magnitudes and phases are the same as those
described in Section 7.3 o f Chapter 7, where all outputs are set relative to the
reference value o f channel 1. The desired relative output magnitudes and phases
are obtained by matching their values to corresponding control values within the
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160
calibration tables. An example of the calibration table for channel 6 was given in
Table 7.3 o f the previous chapter.
Set desired
output
Measure
feedback
Measure
feedback
Feedback
equal
Desired
value?
No
Adjust output
control value
Yes
Desired
output is set
Figure 8.2
Flow chart of program algorithm for setting output values.
8.2.1 Compensating for Magnitude Variations
After the desired output magnitude is set, the program is instructed to read
the magnitude feedback value from the phase-gain comparator chip. This
feedback value is compared against the expected feedback from the calibration
table for that channel. The expected feedback value is the value that matches the
desired one within the calibration table. If the newly-read feedback value is
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161
different from the expected value, the program adjusts the magnitude control of
the 5-bit digital attenuator until a feedback match is achieved.
The very nature o f the operation o f the phase-gain comparator ensures the
accuracy o f this technique. As long as the feedback values are matched, the
relative magnitude o f the reference and o f the output signal being measured is the
same, irrespective o f their values. This is also true for the phase measurements.
That is, an equal feedback value means an equal relative value.
8.2.2 Compensating for Phase Variations
The technique described in Section 7.3.2 is used to initially set the desired
output phase. The program is instructed to continuously monitor the phase
feedback value o f the phase-gain comparator and to adjust the phase control
voltage o f the phase shifters until a matching feedback value is obtained. The
program senses the disparity in the phase feedback values and makes the
necessary adjustments. This is outlined in Section 7.3.2.
8.3
MEASUREMENTS AND RESULTS
All 16 antennas of the 4 x 4 patch antenna array were connected to the
outputs o f the phased array driver device and a random set of desired magnitudes
and phases were entered. The program was instructed to measure and reset the
output values three times. Table 8.1 shows the deviations measured while setting
the outputs. The operation of the program is such that channel 2 magnitude is first
set, followed by its phase. Then channel 3 magnitude and phase, and so on, until
channel 16 magnitude and phase are set. Once all outputs are set, their feedback
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162
Deviation measurements while setting the outputs
Table 8.1
Desired
outputs
Antenna
Measured
deviation as
each output is
set
Magn. Phase
(dB)
(deg)
Measured
deviation after
all outputs are
set
Magn. Phase
(dB)
(deg)
1st reset and
measured
deviation
2nd reset and
measured
deviation
Rel.
Magn
(dB)
Rel.
Phase
(deg)
2
10
100
-1
-11
-1
+10
0
-9
0
-2
3
-10
200
0
-14
-1
-5
-2
-8
0
-1
4
5
300
-2
-6
-4
-6
-2
+2
0
+1
5
-5
100 -4
-40
-4
-42
-1
-4
0
0
6
10
20
0
-55
0
-55
-1
-6
0
-2
7
-6
120
-4
+1
-4
+3
0
-4
0
-3
8
-5
200
0
-36
0
-33
0
-15
0
-4
9
10
0
-2
-33
-2
-36
0
-20
0
-1
10
10
50
-1
+6
-2
+12
-1
-5
0
-1
11
-7
220
-1
-34
-2
-24
-2
-5
-1
0
12
-2
300
-2
-13
-2
-16
-1
-6
-1
-2
13
1
330
-2
-77
-2
-80
-1
-10
0
14
-5
50
+1
-33
+1
-33
0
0
0
15
0
100
-2
-22
-2
-20
-1
-4
0
-3
16
8
200
-3
-48
-3
-48
-1
-2
0
-2
Magn.
(dB)
0
Phase
(deg)
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Magn.
(dB)
Phase
(deg)
-1
163
values are read and compared against the desired feedback within the calibration
table for each channel. The outputs are reset until feedback matching is achieved.
All measurements are relative to the reference signal o f channel 1 (-23 dBm, 0
degree).
All feedback values were converted to their respective magnitude (dB) and
phase (degree) values. It can be seen from the third column of Table 8.1 that up to
4 dB magnitude deviation (for antenna 7) and 77° phase deviation (for antenna
13) were obtained. There are two major reasons for such large deviations. (1) The
values within the calibration tables, which were obtained with a 50-ohm load
terminating each channel, are compared to values obtained with non-resistive,
non-50-ohm antennas connected at the outputs. (2) The effects of mutual
coupling.
After all outputs were set, another measurement of the feedback values
was taken and compared to the expected value from the calibration tables. The
deviations are shown in column 4 (measured deviations after all outputs are set).
Note that these values are different from those of column 3. This additional
deviation is caused by mutual coupling effects and is an actual demonstration of
such effects. Having detected these deviations, the program reset and re-measured
the outputs until feedback matching was obtained. It did this in two iterations and
the measured deviations are shown in columns 5 and 6, respectively. Notice that
the deviation is reduced in successive settings (that is, the process converges) and
in some cases no deviations were obtained. Such convergence is possible because
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164
the changes in mutual coupling effects get much smaller, sometimes negligible,
for each output reset. Therefore, no more than two iterations were needed.
More accurate setting of the outputs may be achieved by using smaller
increments when adjusting the magnitude and phase control values. However, the
smaller the steps, the longer the program takes to execute. Therefore, in some
applications accuracy versus time tradeoffs may be required.
8.4
CONCLUSION
The effects o f mutual coupling have been demonstrated by measuring the
magnitude and phase variations at one antenna, while its neighboring antenna’s
values were varied. As expected, maximum coupling effects occurred when the
magnitude difference was largest and the phase was varied. The effects o f phase
variation are dependent on the operating frequency o f the device and the
separation between antenna elements.
All 16 antennas were connected to the outputs of the phased array driver
and the desired output magnitude and phase values were entered. It was shown
that mutual coupling effects among the antenna elements caused significant
deviations in their magnitudes and phases values. By running two sets of
iterations, the controller program of the device reduced these deviations to
acceptable limits. It has been clearly shown that the device is capable of
compensating for any deviations of its output magnitude and phase settings. The
circuit achieves the specified magnitudes and phases at each antenna element
even in the presence o f significant mutual coupling.
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165
Chapter 9
Conclusions
The design, construction, and testing of a phased array device that is
capable o f driving an array of patch antennas has been presented. Each channel of
the device has a variable and controllable phase shift and magnitude of up to 360°
and 30 dB respectively. The device had been designed to satisfy the requirements
for testing o f a newly proposed concept of radiation from patch antenna arrays.
At first, a 3 x 4 (12 channels) phased array device utilizing transmission
line phase shifting techniques and operating at a frequency o f 1 GHz was
designed and tested. During testing, it was observed that although 360° of
controllable phase shift was obtained at each of its outputs, the magnitude
variation was quite erratic and at times uncontrollable. There were two primary
factors that contributed to this. First, there was a significantly large variation of
output impedance with phase for the transmission line phase shifters. The
dimensions chosen for the realization of these phase shifters were such that a
significant impedance variation occurred at their outputs whenever the phase was
varied through its full 360° range.
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166
The second factor that contributed to the erratic and uncontrollable
magnitude was the variation of the input and output impedance of the voltage
variable attenuator whenever its attenuation was varied. The fact that the phase
shifters feed directly into the attenuators further complicated the problem and
created large impedance mismatches. Because o f this erratic behavior, the device
did not meet our specifications. All efforts to stabilize this impedance variation
failed and we were forced to redesign the device.
Other factors that may have contributed to this problem are coupling
between adjacent circuits, cross talk and RF pickup in wire connectors for the
computer interface board to the antenna driver circuits, and the improper sampling
(for feedback) o f the output RF signals.
Another 1 GHz phased array device was designed with a more rigorous
adherence to RF and microwave circuit design principles. This new design
utilized variable phase-shifter and attenuator packages with fixed 50-ohm input
and output impedances, thus eliminating unwanted magnitude variations. Each
channel in the array has its own digital control circuits. This eliminated the need
for long interconnects between boards and allowed for proper ground shielding
between channels. Coplanar waveguides were used because they were more
suitable for the PCB machine milling process. Additionally, the output RF signal
was sampled with directional couplers. In this way, the electrical characteristics of
the output circuits were not noticeably disturbed by the sampling process.
The architecture of the new design is an extension o f that for a single
channel that was meticulously designed to avoid the previous problems of the 3x4
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167
array. Each functional block of this single channel was separately designed,
packaged in grounded casing, and thoroughly tested. The test results were
compared against those of the manufacturers to ensure proper operation of each
component. The first test circuit designed was that of the phase shifter, followed
by the 5-bit digital attenuator, phase-gain comparator and finally the directional
coupler. Operation o f the amplifier, the input/output expanders, and the analog-todigital converters were already verified from the design o f the 3x4 phased array.
Also, the focus was mainly on the phase shifter and attenuator, especially on their
input and output impedance variations. Satisfactory test results led to the design
and construction o f a single channel. This single channel was fully tested and
extremely satisfactory results were obtained. It was also use as the testing circuit
for the development o f the controller program. The single channel was properly
characterized and its architecture was applied to the development of a full 4 x 4
phased array.
In the new device, sixteen single channels were interconnected to drive a 4
x 4 patch antenna array. Each channel uses two series 0 ° to 180° voltage variable
phase shifters to provide a 0 0 to 360 0 phase shift and a 5-bit digital attenuator to
provide over 30 dB o f magnitude variation. Each output was sampled with a
directional coupler and its magnitude and phase were compared to those of a fixed
reference. The results were compared against the calibrated values and used to
test and control the accuracy o f the outputs. The setting of the output magnitude
and phase is computer controlled.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
168
The calibrated values were obtained from actual measurements done with
a network analyzer. The main program was modified to step incrementally
through the magnitude and phase variations while allowing the measured outputs
to be recorded. These values were entered into tables and saved within special
files for access by the main program. 32 magnitude values and 64 phase shift
values were recorded and stored for Channels 2 to 16.
During the design of the 4x4 array, special care was taken to ensure that
all digital ICs were properly addressed and only one may be accessed at a time by
the controller program. The PCB design of the channels was such that shielding
was very simple; each channel was enclosed by grounded partitions that
effectively prevented RF interferences. That is, each channel was effectively selfcontained and separated from each other.
A variety o f tests were carried out and very good results were obtained.
The device met all the required specifications. As an additional verification o f the
signals at the antennas, an RF probe for the antenna surfaces was designed. Its
measurements were displayed on a network analyzer, but erratic signals were
obtained.
The effects o f mutual coupling between two adjacent patch antenna
elements have been studied. Mutual coupling effects were demonstrated by
observing the signal in one antenna element while varying the magnitude and
phase o f its neighboring element. Significant variations in magnitude and phase
were measured at the observed element. It was also shown that maximum
coupling effects occurred when the relative magnitudes of the signal in both
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
169
antenna elements were at a maximum and the phase was varied. These effects
were manifested as variations in magnitude and phase values. Therefore, the
desired relative magnitude and phase values at antenna elements within an array
are affected by coupling.
Mutual coupling effects were also demonstrated in the setting of the
desired outputs at each antenna element within a 4 x 4 antenna array. The
controller program was redesigned to set, measure, reset, and re-measure the
output values until the desired settings were achieved. In this way, the deviations
in relative magnitudes and phases were reduced to acceptable limits. This
demonstrates that the device is capable of accurately setting the magnitudes and
phases o f the signal at its antenna elements even in the presence of mutual
coupling.
The 4 x 4 phased array driver may be operated over a frequency range of
0.85 to 1 GHz with a minimum and maximum input power of -15 dBm and +15
dBm, respectively. That is, it has an input dynamic range of 30 dBm. However, it
can withstand an absolute maximum input power o f 36 dBm. It requires an
operating DC voltage o f 17 volts and consumes 20.4 watts of power.
9.1
FUTURE WORK
The 4 x 4 patch antenna array used for testing this device was not designed
in accordance with the newly proposed concept o f radiation from patches. The
theoretical analyses and exact design procedures for such antennas are not yet
available. This work is being done elsewhere and as soon as it is completed, a 4 x
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
170
4 patch antenna array with 50 ohm input may be designed and used to test the
radiation pattern o f the 4 x 4 phased array driver presented in this thesis.
The ultimate application of this work will be in the design o f a Ka band
transceiver with an N x M integrated antenna array.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
171
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix A
The Controller Program
#include
#include
#include
#include
#include
#include
#include
tinclude
linclude
#include
<stdio.h>
<stdlib.h>
<gtk/gtk.h>
<sys/time.h>
<unistd.h>
< s y s / t y p e s .h>
<sys/stat.h>
<fcntl.h>
<errno.h>
<time.h>
# i n c l u d e < l i n u x / i 2 c .h>
#include <linux/i2c-dev.h>
ttdefine E V E N T _ M E T H O D (i , x)
#define XSIZE
#define YSIZE
GTK_WIDGET_GET_CLASS(i)->x
620
720
in t n o _ o f _ p r e s s e s = 0;
in t p h a s e _ c o n t r o l ;
/* B a c k i n g p i x m a p f or d r a w i n g a r e a
s t a t i c G d k P i x m a p * p i x m a p = N ULL;
*/
/* C r e a t e a n e w b a c k i n g p i x m a p of t h e a p p r o p r i a t e s i z e */
static gboolean con f i g u r e _ e v e n t ( GtkWidget
*widget
GdkEventConfigure *event
{
if
(pixmap)
g_object_unref
(pixmap);
pixmap = gdk_pixmap_new
(widget->window,
widget->allocation.width,
w i d g e t - > a l l o c a t i o n .he ig ht ,
- 1);
gdk_draw rectangle
(pixmap,
widget->style->white_gc,
TRUE,
0, 0,
widget->allocation.width,
widget->allocation.height);
r e t u r n TRUE;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
/* R e d r a w t he s c r e e n f r o m t he b a c k i n g p i x m a p
s t a t i c g b o o l e a n expose__event ( G t k W i d g e t
GdkEventExpose
*/
*widg et ,
*event )
{
gdk draw_drawable
(widget->window,
widget->style->fg_gc[GTK_WIDGET_STATE
( w i d g e t ) ],
pixmap,
e v e n t - > a r e a . x , e v e n t - > a r e a .y,
e v e n t - > a r e a .x, e v e n t - > a r e a .y,
e v e n t - > a r e a . w i d t h , e v e n t - > a r e a .h e i g h t );
return
FALSE;
}
/* D r a w a r e c t a n g l e o n t h e s c r e e n
static void d r a w _ b r u s h ( GtkWidget
gdouble
gdouble
*/
*widg et ,
x,
y)
{
GdkRectangle
update_rect;
update_rect.x = x - 5 ;
u p d a t e _ r e c t .y = y - 5 ;
u p d a t e _ r e c t . w i d t h = 6;
u p d a t e _ r e c t . h e i g h t = 6;
g d k _ d r a w _ r e c t a n g l e (pixmap,
widget->style->black_gc,
TRUE,
u p d a t e _ r e c t .x, u pd a t e _ _ r e c t .y,
u p d a t e _ r e c t .w id th , u p d a t e _ r e c t .h e i g h t )
gtk_widget_queue_draw_area (widget,
u p d a t e _ r e c t .x, u p d a t e _ r e c t .y,
u p d a t e _ r e c t .w i d t h , u p d a t e _ r e c t .h e i g h t )
/* D r a w n e w
r e c t a n g l e on t h e s c r e e n */
s t a t i c v o i d d r a w _ b r u s h _ f e e d b a c k ( G t k W i d g e t *widget,
gdouble
x,
gdouble
y)
{
GdkRectangle
update_rect;
u p d a t e _ r e c t .x = x - 3 ;
u p d a t e _ _ r e c t .y = y - 3 ;
u p d a t e _ r e c t . w i d t h = 4;
u p d a t e _ r e c t .h e i g h t = 4;
g d k _ d r a w _ r e c t a n g l e (pixmap,
widget->style->black_gc,
TRUE,
u p d a t e _ r e c t .x, u p d a t e _ r e c t .y,
u p d a t e _ r e c t .wi dt h, u p d a t e _ _ r e c t .h e i g h t )
g t k _ w i d g e t _ q u e u e _ d r a w _ a r e a (widget,
u p d a t e _ r e c t .x, u p d a t e _ r e c t .y,
u p d a t e _ r e c t . w i d t h , u p d a t e _ r e c t .h e i g h t )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
178
}
void quit
()
{
exit
(0) ;
}
/*************** *** *** *** *** *** *** *** *** *** ** *** *** *** *** *** *** */
/* P C F 8 5 7 4
/* P C F 8 5 9 1
/* P C A 9 5 4 0
- R e m o t e 8 - b i t I/ O e x p a n d e r f or l 2 C - b u s
- 8 - b i t A / D a n d D / A c o n v e r t e r */
- 2 - c h a n n e l I2C m u l t i p l e x e r */
*/
struct
{
i nt fd;
u n s i g n e d c h a r data;
} p c f 8 5 7 4 [8], p c f 8 5 7 4 a [8];
struct
{
int fd;
unsig n e d char control;
} p c f 8 5 9 1 [8];
struct
/* c o n t r o l b y t e
*/
{
i nt fd;
u n s i g n e d c h a r co n t r o l ;
} p e a 954 0;
struct
{
struct
{
i nt
c ha n n e l ;
} mux;
struct
{
i nt is__8574a;
i nt chip;
} ioe;
struct
{
i nt chip;
struct {
in t ch a n n e l ;
in t i n p u t _ v a l u e ;
in t t a r g e t _ d a t a ;
} ph as e, m a g n i t u d e ;
} adc;
} t r a n s m i t t e r [16]
=
{
{ 0 ,
0 } ,
t o ,
{ 0 ,
0 ,
0 } ,
{ 1 ,
0 ,
0 } }
{ { 0 } ,
{ 0 ,
4 } ,
{ 0 ,
{ 2 ,
o ,
0 } ,
{ 3 ,
0 ,
0 } }
{ { ! } ,
{ 0 ,
2 } ,
{ 4 ,
{ 0 ,
0 ,
0 } ,
{ 1 ,
0 ,
0 } }
{ { 0 } ,
{ 0 ,
6 } ,
{ 4 ,
{ 2 ,
0 ,
0 } ,
{ 3 ,
0 ,
0 } }
{ { 1 } ,
{ 0 ,
1 } ,
{ 2 ,
{ 0 ,
o ,
0 } ,
H
,
o ,
0 } }
{ { 0 } ,
{ 0 ,
5 } ,
{ 2 ,
{ 2 ,
0 ,
0 } ,
{ 3 ,
o ,
0 } }
H
U
,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
179
{{1},
{{0},
{0,
{0,
{{1},
{{0},
{1,
{1,
{1,
{1,
{1,
{1,
{1,
{1,
{{1},
1(0},
{{1},
{ { 0 },
{{1},
{{0},
3},
7),
0},
4},
2},
6},
1},
5},
3},
7},
{6,
{6,
{1,
{1,
(5,
{5,
{3,
{3,
{7,
{7,
{0,
(2,
{0,
{2,
{0,
{2,
{0 ,
{2,
{0 ,
(2,
0},
0},
0},
0},
0},
0},
0},
0},
0},
0},
o,
0,
0,
o,
0,
0,
0,
o,
0,
0,
{1,
{3,
{1,
{3,
{1,
{3,
{1,
{3,
{1,
{3,
0,
0,
0,
0,
0,
0,
0,
0,
0,
o,
0}}
0} }
0}}
0}}
0}}
0}}
0}}
0}}
0}}
0}}
};
i nt
i n i t i a l i z e _ h a r d w a r e ()
{
in t
i,
fd;
fo r (i = 0; i < 8; i++) {
if ( (fd = o p e n (" / d e v / i 2 c - 0 " , 0 _ R D W R ) ) = = -1) r e t u r n (-1);
if (ioctl(fd, I 2 C _ S L A V E , 0 x 2 0 | i) = = -1) r e t u r n (-1);
p c f 8 5 7 4 [i ]. f d
= fd;
p c f 8 5 7 4 [ i ] . d a t a = OxFF;
if
if
( (fd = o p e n (" / d e v / i 2 c - 0 " , 0 _ R D W R ) ) = = -1) r e t u r n (-1);
(ioctl(fd, I 2 C _ S L A V E , 0x38 | i) = = -1) r e t u r n ( - 1 ) ;
p c f 857 4 a [ i ] .fd
= fd;
p c f 8 5 7 4 a [ i ] . d a t a = OxFF;
if
if
( (fd = o p e n (" / d e v / i 2 c - 0 " , 0 _ R D W R ) ) = = -1) r e t u r n ( - l ) ;
(ioctl(fd, I 2 C _ S L A V E , 0x48 | i) = = -1) r e t u r n (-1);
pcf8591[i].fd
= fd;
p c f 8 5 9 1 [ i ] .c o n t r o l = 0x00;
}
if ( (fd = o p e n (" / d e v / i 2 c - 0 " , 0 _ R D W R ) ) = = - 1 )
return(
if (ioctl(fd, I 2 C _ S L A V E , 0x70) = = - 1 ) r e t u r n ( - 1 ) ;
pca9540.fd
= fd;
p c a 9 5 4 0 . c o n t r o l = 0x05;
if ( w r i t e ( p c a 9 5 4 0 .fd, & ( p c a 9 5 4 0 .c o n t r o l ), 1) != 1)
r e t u r n (-1);
r e t u r n (0);
}
/* s e l e c t c h a n n e l 0 or 1 of t he m u l t i p l e x e r
i nt s e l e c t m u l t i p l e x e r ( i n t c h a nn e l)
*/
{
in t
fd;
unsigned char control;
/* a r g u m e n t r a n g e
if ( ( c h a n n e l < 0)
c h e c k */
|| ( c ha nn el
> 1))
return(-l);
fd
= p c a 9 5 4 0 .fd;
c o n t r o l = p c a 9 5 4 0 .c on t r o l ;
/* if
((control
& 0x03)
== ch a n n e l )
r e t u r n (0);
*/
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
- 1 ) ;
180
/* w r i t e c o n t r o l b y t e */
c o n t r o l = ( c o nt ro l & OxFE)
if (write(fd, S co n t r o l , 1)
p c a 9 5 4 0 .c o n t r o l = co n t r o l ;
| c ha nn el ;
!= 1) r e t u r n (-1);
r e t u r n (0);
}
/* r e a d 8 - b i t d a t a f r o m t h e s p e c i f i e d c h a n n e l n u m b e r
a d c w i t h t h e g i v e n c h i p h a r d w a r e a d d r e s s (0-7) */
int r e a d _ a d c ( i n t chip, int c h an ne l)
(0-3)
of t h e
{
int fd;
u n s i g n e d char control;
u n s i g n e d c h a r data;
unsigned char buffer[2];
/* a r g u m e n t r a n g e
if ((chip
< 0)
if ( (c ha n n e l < 0)
fd
= pcf8
control = p c f 8
5 9 1
5 9 1
c h e c k */
|| (chip
|| ( c ha nn el
>7))
> 3))
r e t u r n (-1);
r e t u r n (-1);
[ c h i p ] .fd;
[ c h i p ] .c o n t r o l ;
/* w r i t e c o n t r o l b y t e */
c o n t r o l = (contr o l & OxFC) | c ha n n e l ;
if (write(fd, S co nt r o l , 1) != 1) r e t u r n (-1);
p c f 8 5 9 1 [ c h i p ] .c o n t r o l = c o n t r o l ;
/* r e a d d a t a */
if (read(fd, b u f f e r ,
d a t a = b u f f e r [1];
2)
!= 2)
r e t u r n (-1);
return(data);
}
/* w r i t e s p e c i f i e d v a l u e
of th e i oe w i t h t he g i v e n
i nt w r i t e _ i o e ( i n t
chip,
to t he s p e c i f i e d b i t n u m b e r
chip hardware address ( 0 - 7 )
* /
( 0 , 1 )
in t bit,
int value)
{
int fd;
u n s i g n e d c h a r data;
/* a r g u m e n t r a n g e c h e c k */
if
( (chip
< 0) || (chip
> 7)) re t u r n ( - l )
if
((bit
< 0) || (bit
> 7)) r e t u r n (-1)
if
( (value < 0) || (value
> 1)) r e t u r n (-1)
fd
= p c f 8 5 7 4 [ c h i p ] .fd;
data = pcf8574[chip].data;
if
(value)
data
else
data
|=
(1 «
&= ~(1
bit);
<< b i t ) ;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
( 0 - 7 )
/* w r i t e d a t a */
if (write(fd, Sdata, 1) != 1)
p c f 8 5 7 4 [ c h i p ] . d a t a = data;
r e t u r n (-1);
r e t u r n (0);
}
i nt w r i t e _ i o e _ a ( i n t
chip,
int bit,
int value)
{
in t fd;
u n s i g n e d c h a r data;
/* a r g u m e n t r a n g e c h e c k */
if
((chip
< 0) || (chip
> 7))
if
((bit
< 0) || (bit
> 7))
if
((v al ue < 0) || (value
> 1))
r e t u r n (-1)
return(-l)
re t u r n ( - l )
fd
= p c f 8 5 7 4 a [ c h i p ] .fd;
d a t a = p c f 8 5 7 4 a [ c h i p ] .data;
if
(value)
data
else
data
|=
(1 «
&= ~(1
b i t );
<< bit);
/* w r i t e d a t a */
i f (write(fd, &data, 1) != 1)
p c f 8 5 7 4 a [ c h i p ] . d a t a = data;
r e t u r n (-1);
r e t u r n (0);
}
#define
tdefine
fdefine
CLK
SDI
LD
6
7
5
int w r i t e _ d a c 7 6 1 1 ( i n t
chip,
int value)
{
in t
if
i;
( (v a l u e < 0)
||
(value > O x O F F F ) ) r e t u r n (-1);
/* i n t e r n a l s e r i a l r e g i s t e r */
f o r (i = 11; i > = 0; i — ) {
/* C L K l o w */
w r i t e _ i o e ( c h i p , CLK, 0);
/* S DI = D[i] */
w r i t e _ i o e (chip, SDI,
/* C L K h i g h
r e g i s t e r */
- clock Serial
write_ioe(chip,
CLK,
Data
(value >> i)
Input
& 0x0001)
into internal
serial
1);
}
/* L D l o w - m a k e
DAC regis t e r
transparent
*/
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
write__ioe (chip,
LD,
0);
/* L D h i g h */
write_ioe(chip,
LD,
1);
r e t u r n (0);
}
i nt w r i t e ^ a t t e n u a t o r (in t
chip,
int value)
{
int
if
f or
i;
(( va lu e < 0)
||
(value > O x O O l F ) ) r e t u r n (-] ) ;
(i = 0 ; i < 5 ; i++)
w r it e ioe(chip,
{
- i,
4
(value »
i)
& 0x 0 0 0 1 ) ;
r e t u r n (0);
i nt w r i t e _ d a c 7 6 1 1 _ a ( i n t
chip,
in t v alue)
{
in t
i;
if ((v al ue < 0) || (value > O x O F F F ) ) r e t u r n (-; ) ;
/* i n t e r n a l s e r i a l r e g i s t e r */
f or (i = 11; i > = 0 ; i — ) {
/* C L K l o w */
w r i t e _ i o e _ a ( c h i p , CLK, 0 ) ;
/* S D I = D[i] */
w r i t e _ i o e _ a (chip,
internal
serial
SDI,
(value >> i)
/* C L K h i g h - c l o c k S e r i a l
r e g i s t e r */
w r i t e _ i o e _ a ( c h i p , CLK, 1);
/* L D l o w - m a k e D A C r e g i s t e r
w r i t e _ i o e _ a ( c h i p , LD, 0 ) ;
/* L D h i g h */
write_ioe_a(chip,
LD,
Data
& 0 x0 0 0 1 ) ;
Input
transparent
into
*/
1);
r e t u r n (0);
}
i nt w r i t e _ a t t e n u a t o r _ a ( i n t
chip,
i nt value)
{
in t
if
fo r
i;
((v al ue <
(i =
0 )
||
(value > O x O O l F ) ) r et ur n) -: ) ;
0 ;
i < 5 ; i++) {
write ioe_a(chip,
4
- i,
(value >> i)
& 0x0001)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
183
r e t u r n (0);
}
int m a g n i t u d e ( i n t
a nt e n n a ,
int
input_value)
{
i nt
if
if
i;
( ( a n t e n n a < 1) II ( a nt en na > 16)) r e t u r n (-1);
{ ( i n p u t _ v a l u e < 0) || ( i n p u t _ v a l u e > O x O O l F ) )
r e t u r n (-
1);
i = a n t e n n a - 1;
select_multiplexer(transmitter[i].mux.channel);
if ( t r a n s m i t t e r [ i ] .i o e .is _8 5 7 4 a )
w r i t e _ a t t e n u a t o r _ a ( t r a n s m i t t e r [ i ] .i o e .chip,
input_value);
else
w r i t e _ a t t e n u a t o r ( t r a n s m i t t e r [ i ] .i o e .chip,
input_value);
r e t u r n ( r e a d _ a d c ( t r a n s m i t t e r (i ] . a d c .chip,
t r a n s m i t t e r [ i ] . a d c . m a g n i t u d e . c h a n n e l ) );
}
i nt p h a s e ( i n t
antenna,
i nt
input_value)
{
in t
if
if
1)
i;
( ( a n t e n n a < 1) || ( a nt en na > 16)) r e t u r n (-1);
( (input_value < 0 )
|| ( i n p u t _ v a l u e > O x O F F F ) ) r e t u r n (-
;
i = a n t e n n a - 1;
select__multiplexer(transmitter[i].mux.channel);
i f ( t r a n s m i t t e r [ i ] .i o e .is _8 5 7 4 a )
w r i t e _ d a c 7 6 1 1 _ a ( t r a n s m i t t e r [ i ] .i o e .chip,
input__value) ;
else
write dac7611(transmitter[i].ioe.chip,
input^value);
r e t u r n (r e a d _ a d c ( t r a n s m i t t e r [ i ] .a d c . c h i p ,
t r a n s m i t t e r [ i ] .a d c . p h a s e .c h a n n e l ) );
}
/- k - k -k * * * -k 'k 'k 'k -k -k - k - k 'k ie ic 'k - k 'k 'k i '-k 'k - k 'k 1 c -k - k - k - k 'k 'k -k -k -k - k - k 'k - k - k - k - k -k 'k i c i< * - k - k 'k * 'k -k - k - k - k 'k - k * * - k - k - k
■ k -k 'k -k 'k -k 'k - k 'k 'k 'k - k 'k - k - k 'k 'k - k -k -k 'k 'k - k - k 'k 'k -k if- k 'k 'k 'k 'k -k 'k 'k ^ 'k 'k - k - k ^ r - k 'k 'k -k - k - k 'k -k 'k -k 'k 'k - k 'k 'k - k 'k - k '^ 'k -k - k ^
struct CalibrationData {
float setting;
i nt f e e d b a c k ;
int control;
value
/* r e a l w o r l d m e a s u r e m e n t */
/* c o r r e s p o n d i n g d i g i t a l r e p r e s e n t a t i o n
/* d i g i t a l o u t p u t to e f f e c t r e a l w o r l d
*/
};
struct
{
s t r u c t C a l i b r a t i o n D a t a m a g n i t u d e [32];
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
*/
184
s t r u c t C a l i b r a t i o n D a t a p h a s e [32];
} c a l i b r a t i o n [16];
/* g e t
int
calibration data
fo r a n t e n n a s
2 through
16 */
i n i t i a l i z e _ c a l i b r a t i o n _ t a b l e s ()
{
F I L E *fp;
int i, j;
int i temp;
f l o a t ftemp;
/ * o p e n c a l i b r a t i o n d a t a f i l e */
if ( (fp = f o p e n C c a l i b r a t i o n . d a t " ,
r e t u r n (-1);
/*
for
fscanf(fp,
fscanf(fp,
fscanf(fp,
fscanf(fp,
fscanf(fp,
for a n t e n n a
(i =
"%d",
"%d",
"%d",
"%f",
"%f",
2 through
16...
"r") ) = = NULL)
*/
1; i < 16; i++) {
/* ... r e a d m a g n i t u d e c a l i b r a t i o n */
fo r (j = 0; j < 32; j++) {
& ( c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . c o n t r o l ) );
& ( c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . f e e d b a c k ) );
&itemp);
& ( c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ].s e t t i n g ) ) ;
& f t e m p );
}
/*
for
f s c a n f (fp,
f s c a n f ( fp,
fscanf(fp,
fscanf(fp,
f s c a n f (fp,
...
( j
read phase
0 ;
=
j
<
calibration
3 2 ;
j++)
*/
{
" % d " , & ( c a l i b r a t i o n [ i ] . p h a s e [j ] . c o n t r o l ));
"%d", &i t e m p ) ;
"%d", & (calibration[i].phase[ j ].feedback)) ;
i r g. ■£ »i
&ftemp);
o l
,
n o, x:ft
o r
r & ( c a l i b r a t i o n [ i ] . p h a s e [j ] . s e t t i n g ) ) ;
f
\
;
/*
close
calibration data
fi l e
*/
f c l o s e (f p ) ;
r e t u r n (0);
static
i nt
a n g l e b e t w e e n ( f l o a t pi,
f l o a t p2)
{
if (pi > p2) p 2 + = 360;
r e t u r n ( p 2 - pi);
in t
int
search_phase_table(int
*feedback)
an t e n n a ,
float
s e t ti ng ,
i nt
* co nt r o l ,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
185
{
in t
if
i,
j;
( ( a n t e n n a < 2)
i = antenna
for
(a n t e n n a
> 16))
return(-l);
- 1;
(j = 0;
if
||
j < 30;
j++)
{
(
a n g l e b e t w e e n ( c a l i b r a t i o n [ i ] .p h a s e [ j ] . s e t t i n g ,
s e tt in g)
<=
anglebetween(calibration[i].phasefj].setting,
c a l i b r a t i o n [ i ] . p h a s e [ j + l ] . s e t t i n g ) ) b re a k ;
}
* c o n t r o l = (int) (
a n g l e b e t w e e n ( c a l i b r a t i o n [ i ] . p h a s e [ j ] . s e tt in g,
(calibration[i].phase[j+l].control calibration[i].phase[j].control) /
anglebetween(calibration(i].phase[j].setting,
c a l i b r a t i o n [i] . p ha se [j +1 ] .setting) +
c a l i b r a t i o n [ i ] . p h a s e [ j ] . c o n t r o l t 0.5
s e t ti ng )
*
s et ti ng )
*
) ;
* f e e d b a c k = (int) (
a n g l e b e t w e e n ( c a l i b r a t i o n [ i ] . p h a s e [ j ] . s e tt in g,
(calibration[i].phase[j+l].feedback calibration[i].phase[j].feedback) /
anglebetween(calibration[i].phase[j].setting,
calibration[i].phase[j+l].setting) +
c a l i b r a t i o n [ i ] . p h a s e [ j ] .f e e d b a c k t 0.5
);
phase_control
= *control;
p r i n t f (" I n p u t P h a s e C o n t r o l
phase__control) ;
setting
(0 - 3968)
= %d\n",
r e t u r n (0);
}
i nt s e a r c h _ m a g n i t u d e _ _ t a b l e ( i n t
^ c o n t r o l , int * fe e d b a c k )
antenna,
f l o at
s e tt in g,
int
{
int
if
i, j;
( ( a n te nn a
i = antenna
for
< 2)
||
( a nt en na
> 16))
r e t u r n (-1);
- 1;
(j = 0; j < 30; j++) {
if ( c a l i b r a t i o n [ i ] . m a g n i t u d e [ j + 1 ] .s e t t i n g > s e t ti ng )
break;
}
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
186
* c o n t r o l = int) ( { s e t t i n g - c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . s e t ti ng )
* (c a l i b r a t i o n [i ] . m a g n i t u d e [j + 1 ] . c o n t r o l c a l i b r a t i o n [ i ] . m a g n i t u d e [j ] .control) /
(calibration[i].magnitude[j+1].setting c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] .setting) +
c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ]. c o n t r o l t 0.5
);
* f e e d b a c k = (int) ( ( s e t t i n g c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] .setting) *
(calibration[i].magnitude[j+1].feedback c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] .feedback) /
(calibration[i].magnitude[j+1].setting c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] .setting) +
c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . f e e d b a c k t 0.5
);
p r i n t f (" I n p u t M a g n i t u d e
Control
setting
(0 - 31)
= %d\n",
*control);
r e t u r n (0);
}
i nt
set_phase(int
antenna,
float
input_phase)
{
i nt c on t r o l , f e e d b a c k ;
in t beta;
if ( ( a n t e n n a < 2) || ( a n t e n n a > 16))
return(-l);
s ea rc h_ p h a s e _ _ t a b l e (antenna, i n p u t p h a s e ,
&feedback);
i f (con tro l < 0) c o n t r o l = 0;
if ( c ont ro l > OxOFFF) c o n t r o l = OxOFFF;
beta = phase(antenna,
sc on t r o l ,
control);
p r i n t f (" I n p u t p h a s e s e t t i n g = % f
= % d\ n \ n " , input__phase, be t a ) ;
d e g r e e s .... F e e d b a c k
Phase
return(beta);
}
int
set_magnitude(int
an t e n n a ,
float
i np u t _ m a g )
{
int co n t r o l ,
in t alpha;
if
feedback;
( ( a n t e n n a < 2)
||
( an t e n n a > 16))
return(-l);
se a r c h _ m a gnitude_table(antenna, input_mag,
Sfeedback);
if (cont ro l < 0) c o n t r o l = 0;
if ( c on tr ol > O xOOlF) c o n t r o l = O xOOlF;
alpha =magnitude(antenna,
&control,
control);
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
187
p r i n t f (" I n p u t m a g n i t u d e s e t t i n g = %f d B m . ... F e e d b a c k
magnitude
= %d \ n \ n " , i n p u t _ m a g , a l p h a ) ;
return(alpha);
}
/* C o n v e r t 8 - b i t d i g i t a l m a g n i t u d e
m e a s u r e d v a l u e s */
float
get_magnitude(int
a nt e n n a ,
feedback value
float
* s e t t in g,
to a c t u a l
in t
f ee db a c k )
{
int
if
i,
j;
( { a n t e n n a < 2)
||
i = antenna
-1;
for
j < 30;
(j = 0;
if
fe ed b a c k )
( a nt en na > 16))
j++)
return
(-1);
{
( c a l i b r a t i o n [ i ] . m a g n i t u d e [ j + 1 ] .f e e d b a c k <
br e a k ;
}
* s e t t i n g = (float) (
c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . f e e d b a c k - f ee db ac k)
(calibration[i].magnitude[j+1].setting c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] .setting) /
(calibration[i].magnitude[j] .feedback calibration[i].magnitude[j+1].feedback) +
c a l i b r a t i o n [ i ] . m a g n i t u d e [ j ] . s e t t i n g + 0.5
*
) ;
printf
("Magnitude
s e t t i n g = %f\n",
^setting);
r e t u r n (* s e t t i n g ) ;
}
/* M a k i n g
term positive
i nt m o d ( i n t
a,
*/
i nt b)
{
printf
if
("a = %d,
b
(a = b) {
if
(a > 240)
else
if
= %d\n",
return
(a < 20)
a,
b);
( (255-a)
return
* 2);
(2 * a);
}
else
if
(a < b)
return
(b - a ) ;
else
return(a
- b);
}
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
188
/* Convert 8-bit digital phase feedback value to actual measured
values */
float g e t _ p h a s e ( i n t
fe ed ba ck )
a nt e n n a ,
float
*setting,
i nt
*control,
int
{
i nt
if
i,
j;
( ( a n t e n n a < 2)
i = antenna
- 1;
for
j <
(j
=
0 ;
3 0 ;
||
(a n t e n n a > 16))
return
(-1);
j++)
{
{
&&
if ( ( c a l i b r a t i o n [ i ] . p h a s e [ j + 1 ] .c o n t r o l > p h a s e _ c o n t r o l )
( c a l i b r a t i o n [ i ] . p h a s e [ j + 1 ] .f e e d b a c k < = f e e d b a c k ) ) b r e a k ;
}
* s e t t i n g = (float) ( ( f e e d b a c k calibration[i].phase[j].feedback) *
anglebetween(calibration[i].phase[j].setting,
calibration[i].phase[j+1].setting) /
mod(calibration[i].phase[j].feedback,
calibration[i].phase[j+1].feedback) +
c a l i b r a t i o n [ i ] . p h a s e [j ] . s e t t i n g + 0 .5
);
{
if ( ( c a l i b r a t i o n [ i ] . p h a s e [ j + 1 ] .c o n t r o l > p h a s e _ c o n t r o l )
( c a l i b r a t i o n [ i ] . p h a s e [ j + 1 ] .f e e d b a c k > f e e d b a c k ) ) b r e a k ;
&&
}
* s e t t i n g = (float) ( ( c a l i b r a t i o n [ i ] . p h a s e [ j ] . f e e d b a c k f e e d b a c k ) * a n g l e b e t w e e n ( c a l i b r a t i o n [ i ] . p h a s e [ j ] . s et t i n g ,
calibration[i].phase[j+l].setting) /
mod(calibration[i].phase[j].feedback,
calibration[i].phase[j+1].feedback) +
c a l i b r a t i o n [ i ] . p h a s e [j ] . s e t t i n g + 0 . 5 ) ;
}
printf
("Phase s e t t i n g = %f d e g r e e s \ n " ,
*setting);
r e t u r n (* s e t t i n g ) ;
}
display__magnitude(int antenna,
float input_magnitude)
{
float
s et t i n g ;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
189
i nt f e e d b a c k _ m a g n i t u d e ;
float measured_magnitude;
if
( ( a n t e n n a < 2)
||
feedback_magnitude
input_magnitude);
(a n t e n n a
> 16))
return
(-1);
= set_magnitude(antenna,
measured_magnitude = get_magnitude(antenna,
feedback_magnitude);
p r i n t f (" O u t p u t M a g n i t u d e
measured_magnitude);
S se tt i n g ,
= %f d B m \ n \ n \ n " ,
r e t u r n ( (measured__magnitude + 40) *20);
}
display_phase(int
an t e n n a ,
float
input_phase)
{
f l o a t s et t i n g ;
in t f e e d b a c k j p h a s e ;
float measured_phase;
i nt c on t r o l ;
if
( ( a n t e n n a < 2)
feedbackphase
||
( a nt en na
> 16))
= set_phase(antenna,
measured_phase = get_phase(antenna,
feedback_phase);
if
return
input_phase);
Ssetting,
(measured__phase < 0) m e a s u r e d _ p h a s e
p r i n t f (" O u t p u t
P h a s e = %f d e g r e e s \ n " ,
return(measured_phase
*
(-1);
+=
& co nt r o l ,
360;
measured phase);
2);
}
/****************************■*■*************■*■*********************
****************************************************************/
static
gboolean b u t t on_press_event( GtkWidget
GdkEventButton
*wid ge t,
*event )
{
int c h a n n e l ;
int i ;
f l o a t i n p u t M a g n i t u d e [15];
f l o a t i n p u t P h a s e [15];
f l o a t d e s i r e d M a g n i t u d e [15] ;
f l o a t d e s i r e d P h a s e [15] ;
f l o a t a n g l e = 179.9;
float setting;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
190
i = no of_presses + 2;
draw_brush
if
(event->button ==
(widget,
320,
1 && p i x m a p
0);
!= N U L L
&& n o _ o f _ p r e s s e s
< 15
{
draw_brush
(widget,
event~>x,
event->y) ;
inputMagnitude[i] = ((event->x)/
inputPhase[i] = (event->y)/2;
2 0
- 1 6 ) ;
p r i n t f ( " \ n A n t e n n a #%d; R e l a t i v e M a g n i t u d e = %f dB;
Relative
P h a s e = %f d e g r e e s \ n " , i, i n p u t M a g n i t u d e [ i ] , i n p u t P h a s e [ i ] );
desiredMagnitude[i] = inputMagnitude[i]
desiredPhase[i] = inputPhase [ i ] ;
if
(desiredPhase[i]
> angle)
-
2 4 ;
desiredPhase[i]
p r i n t f ( " \ n I n p u t M a g n i t u d e = %f; I n p u t
d e s i r e d M a g n i t u d e [ i ] , d e s i r e d P h a s e [ i ] );
+=
- 3 6 0 ;
P h a s e = %f\n\ n" ,
d r a w _ _ b r u s h _ f e e d b a c k (widget, d i s p l a y j m a g n i t u d e ( i ,
d e s i r e d M a g n i t u d e [ i ] ), d i s p l a y _ p h a s e ( i , d e s i r e d P h a s e [ i ] ));
/*
fflush(stdout);
*/
++no_of_presses ;
return TRUE;
}
else
printf("All
16 c h a n n e l s
are
set.\n");
}
i nt m a i n ( int
char
argc,
*argv[]
)
{
GtkWidget
GtkWidget
GtkWidget
GtkWidget
GtkWidget
GtkWidget
in t i;
* wi nd ow ;
*drawing_area;
*table;
*hr ul e;
*vrule;
* bu tt on ;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
191
if
( i n i t i a l i z e _ h a r d w a r e () = = -1) {
p e r r o r (" R e a s o n fo r e rror:
r e t u r n (-1);
");
}
m a g n i t u d e (1,
p h a s e (1, 0);
if
15);
( i n i t i a l i z e _ c a l i b r a t i o n _ t a b l e s {) = = -1)
p e r r o r (" R e a s o n fo r e rr or : ");
r e t u r n (-1);
{
}
gtk_init
(&argc,
&argv);
window = gtk_window_new (GTK_WINDOW_TOPLEVEL);
g t k _ w i d g e t _ s e t _ n a m e (window, " Te st Inpu t" );
g__si gn al_ co nn ec t ( G _ O B J E C T (window), " d e s tr oy ",
G _ C A L L B A C K (quit), N U L L ) ;
/* C r e a t e
table
fo r p l a c i n g
ruler and drawing area
*/
t a b l e = g t k _ t a b l e _ n e w (3, 2, FALS E) ;
gtk c o n tainer_add (GTK_CONTAINER (window), t a b l e ) ;
d r a w i n g _ a r e a = g t k _ d r a w i n g _ a r e a _ n e w ();
gtk widget set_size_request (GTK_WIDGET
YSIZE7;
gtk_table_attach
(GTK^TABLE
0 ,
gtk_widget__set_events
/*
across
*
*
0 ,
0 ,
(table),
( d r a w i n g _ a r e a ) , XS IZ E,
drawing_area,
1,
2,
1,
2,
0 ) ;
(drawing__area, G D K _ P O I N T E R _ M O T I O N _ M A S K |
GDK_POINTER__MOTION_HINT_MASK);
T h e h o r i z o n t a l r u l e r g o e s o n top. A s t h e m o u s e m o v e s
th e
d r a w i n g area, a m o t i o n _ n o t i f y _ e v e n t is p a s s e d to t he
a p p r o p r i a t e e v e n t h a n d l e r f or t he ruler. */
h r u l e = g t k _ h r u l e r _ n e w ();
g t k _ r u l e r _ s e t j n e t r i c (GTK__RULER (hrule) , G T K _ P I X E L S ) ;
g t k _ r u l e r _ s e t _ r a n g e ( G T K _ R U L E R (hrule), - 1 6 ,
1 6 ,
0 ,
1 0
g signal_connect_swapped
" m o t i o n _ n o t i f y _ e v e n t ",
~~
m o t i o n n o t i f y ^ e v e n t )),
~~
gtk_table_attach
(G^OBJECT
(drawing_area),
GCALLBACK
G_OBJECT
) ;
(EVENT_METHOD
(hrule,
(hrule));
(GTK__TABLE (table) , hrule,
XS I ZE , XS IZ E, 0 , 0 ) ;
/* T h e v e r t i c a l r u l e r g o e s on t h e left. A s
across
* th e d r a w i n g area, a m o t i o n _ n o t i f y _ e v e n t
1 ,
2,
0 ,
1,
the m o u s e m o v e s
is p a s s e d t o the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
* appropriate
event handler
for t he
ruler.
*/
v r u l e = g t k _ v r u l e r _ n e w ();
g t k r u l e r _ s e t_ jn et ri c (GTK_RCJLER (vrule), G T K _ P I X E L S ) ;
g t k ~ r u l e r ~ s e t _ r a n g e ( G T K _ R U L E R (vrule), 0, 360, 0, 10);
g_signal_connect__swapped (G_0BJECT ( d r a w i n g _ a r e a ) ,
"motion_notify_event",
G _ C A L L B A C K (E V E N T _ M E T H O D (vrul
m o t ion_notify__e vent) ),
gtktableattach
/* S i g n a l s
u s e d to h a n d l e b a c k i n g p i x m a p
g_signal_connect
g_signal_connect
/* E v e n t
G _ O B J E C T ( v r u l e ) );
(G T K _ T A B L E (table), vrule, 0,
X SI ZE , XS IZ E, 0, 0);
signals
1,
1,
2,
*/
(G_0BJECT ( d r a w i n g _ a r e a ) , " e x p o s e _ e v e n t " ,
G _ C A L L B A C K ( e x p o s e _ e v e n t ), N U L L ) ;
(G_OBJECT ( d r a w i n g _ a r e a ) , " c o n f i g u r e e v e n t
G _ C A L L B A C K (c o n f i g u r e _ e v e n t ), N U L L ) ;
*/
g _ _ si gn al _c on ne ct ( G _ O B J E C T ( d r a w i n g _ a r e a ) ,
"button_press_event",
G C A L L B A C K ( b u t t o n _ p r e s s _ e v e n t ), N U L L ) ;
gtk widget_set_events
/*
(drawing_area, G D K _ E X P O S U R E _ M A S K
| GDK_LEAVE_NOTIFY_MASK
| GDK_BUTTON_PRESS_MASK
| GDK_POINTER_MOTION MASK
| GDK_POINTER_MOTION_HINT_MASK);
.. A n d a q u i t b u t t o n
button = gtk_button_new_with_label
g_signal_connect_swapped
("Quit");
( G _ O B J E C T (button), "c l i c k e d " ,
G_CALLBACK (gtk_widget_destroy),
G O B J E C T ( w i n d o w ) );
V
gt k_ wi dg e t _ _ s h o w
gtk_widget_show
gtk_widget_show
gtk_widget_show
gt k__widget_show
g t k m a i n ();
(drawing_area);
(table);
(vrule);
(hrule);
(window);
return 0;
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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