close

Вход

Забыли?

вход по аккаунту

?

High efficiency RF and microwave power amplifiers with non-constant envelope signals

код для вставкиСкачать
U n iv e r s it y
of
C a l if o r n ia
Los Angeles
H igh E fficiency R F and M icrow ave P ow er
A m p lifiers w ith N o n -c o n sta n t E n v elo p e S ign als
A dissertation submitted in partial satisfaction
of the requirements for the degree
Doctor of Philosophy in Electrical Engineering
by
J in -s e o n g J e o n g
2006
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
UMI Number: 3254771
INFORMATION TO USERS
The quality of this reproduction is dependent upon the quality of the copy
submitted. Broken or indistinct print, colored or poor quality illustrations and
photographs, print bleed-through, substandard margins, and improper
alignment can adversely affect reproduction.
In the unlikely event that the author did not send a complete manuscript
and there are missing pages, these will be noted. Also, if unauthorized
copyright material had to be removed, a note will indicate the deletion.
®
UMI
UMI Microform 3254771
Copyright 2007 by ProQuest Information and Learning Company.
All rights reserved. This microform edition is protected against
unauthorized copying under Title 17, United States Code.
ProQuest Information and Learning Company
300 North Zeeb Road
P.O. Box 1346
Ann Arbor, Ml 48106-1346
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
© Copyright by
Jin-seong Jeong
2006
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The dissertation of Jin-seong Jeong is approved.
ank M. Chang
Yang Yang
Tatsuo Itoh
Yuanxun E. Wang, Committee Chair
University of California, Los Angeles
2006
ii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
To m y parents,
M y sister and brother,
A nd m y lovely wife, Young. ..
iii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
T
able
C
of
o ntents
1 I n tr o d u c tio n .....................................................................................................
2
O verview o f R F and M icrowave Pow er A m plifiers and T ransm it­
ter A r c h ite c tu r e s ..................................................................................................
2.1
5
In tro d u c tio n ...............................................................................................
5
2.2 Performance Parameters of Power A m plifiers....................................
6
2.2.1
L in earity ..........................
6
2.2.2
E ffic ie n c y .....................................................................................
8
2.3 Power Amplifier C l a s s e s ........................................................................
10
2.3.1
Linear Power A m p lifie rs ...........................................................
11
2.3.2
Switching Mode Power A m plifiers..........................................
12
2.4 Power Amplifier Architectures for Non-constant Envelope Signals
3
1
15
2.4.1
Theoretical B ackgrounds...........................................................
15
2.4.2
Envelope Elimination and Restoration ( E E R ) ....................
18
2.4.3
Doherty A m plifier........................................................................
19
2.4.4
Chirix’s Outphasing
..................................................................
21
D u al-M od e Pow er A m p lif ie r s .................................................................
23
3.1
In tro d u c tio n ...............................................................................................
23
3.2 Principle of O p e ra tio n s...........................................................................
23
3.3 Previous W o r k s .........................................................................................
25
3.4 Dual Mode Divider and C om biner........................................................
27
iv
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.5
4
5
Future W o r k s ..........................................................................................
Efficient Im provem ent Techniques U sing A S M od u lation
...
32
4.1
In tro d u c tio n .............................................................................................
32
4.2
A S M o d u la tio n .......................................................................................
33
4.3
Switching Mode Power Amplifiers with A S M o d u la to r ...............
38
4.4
Switching Mode Power Amplifiers for Envelope Delta-sigma Mod­
ulation (E D S M )........................................................................................
40
4.4.1
Class D Power Amplifier with E D S M ....................................
40
4.4.2
Class ED Power Amplifier with E D S M .................................
48
Efficient M icrowave Pow er A m plifier w ith P u lsed Load M odula­
tion (PL M ) T e c h n iq u e s............................................................................
6
30
52
5.1
In tro d u ctio n .............................................................................................
52
5.2
Principle of O p era tio n s..........................................................................
56
5.3
Nonlinear Simulations
..........................................................................
66
5.4
Hybrid Implementations of PLM at 1.87 G H z ................................
67
5.5
MMIC Implementations of PLM at 17 GHz
...................................
70
Efficient Pow er C om biner D esign M eth od s............... .......................
75
6.1
In tro d u ctio n .............................................................................................
75
6.2
Tree Structure C o m b in in g ...................................................................
76
6.3
Area Efficient Power Combiner
.........................................................
79
6.4
34 GHz power amplifier with efficient com bining............................
80
v
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
7 C o n c lu s io n s .....................................................................................................
84
R e fe r e n c e s ..............................................................................................................
85
vi
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
L
is t
o f
F
ig u r e s
1.1
RF Module Trends (Courtesy of TI [4 ]).............................................
3
2.1
OFDM envelope waveform (802.11a)
.................................................
6
2 .2
Example ACPR specification (Courtesy of A g ile n t ) .......................
7
2.3
Typical efficiency curves of power am plifier.......................................
8
2.4
OFDM envelope PD Fs.............................................................................
9
2.5
General single-ended circuit configuration of RF P A s ...................
10
2.6 Ideal biasing curve of FETs
..................................................................
11
2.7 Class E Power Amplifier at 17 G H z .....................................................
14
2.8
Loadline analysis (a) class B loadline (b)
16
2.9
Efficiency enhancement methods (a) voltage modulation (b) load
modulation
6
dB b a c k -o ff................
..............................................................................................
17
2.10 Kahn T ra n sm itte r....................................................................................
18
2.11 Doherty A m plifier....................................................................................
20
2.12 Outphasing A m plifier..............................................................................
21
3.1
24
Power amplifier combining m ethod.................................
3.2 Drain efficiency curves for single and four amplifiers.........................
3.3
Dual-mode combiner under (a) high power mode (b)low power
m o d e ...........................................................................................................
3.4
3.5
24
26
Schem atic of D ual-m ode pow er am plifier w ith d u al m ode divider
and c o m b in e r ...........................................................................................
28
Photograph of fabricated dual-mode power am plifier......................
29
vii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.6
Measured gain and PAE of dual-mode power amplifier.....................
30
3.7
Tri-mode combining scheme....................................................................
31
4.1
First order A S modulator [51]................................................................
34
4.2
Noise spectrum after shaping [51]..........................................................
35
4.3
(a) 9 MHz sinusoid signal (b) Delta-Sigma modulation of sinusoid
36
4.4
The spectrum of the A E modultaed signal compared the original
9 MHz signal spectrum, (a) 16 OSR (b) 32 O S R .............................
37
4.5
Switching PA with AE m odulator.........................................................
38
4.6
Switching PA with envelope delta-sigma m odulator..........................
39
4.7
(a) Voltage mode class D power amplifier and (b) waveforms [6 ]. .
41
4.8
Simulation setup for VMCD with EDSM.............................................
42
4.9
Waveforms and spectrum for full swing sinusoid envelope..............
4.10 Waveforms and spectrum for
6
db back-off........................................
43
44
4.11 Drain efficiency, DC power RF power versus drain capacitance. ..
45
4.12 Drain efficiency, DC power and RF power versus on-resistance
..
46
4.13 Class D Power Amplifier for EDSM......................................................
47
4.14 Class ED transm itter architecture.........................................................
48
4.15 Class ED Power Amplifier for EDSM....................................................
49
4.16 RF output and DC Current waveforms................................................
50
4.17 O utput spectrum of class ED
51
5.1
..............................................................
Block diagram of the envelope delta-sigma modulation(EDSM)
system..........................................................................................................
viii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
54
5.2 Block diagram of a switched resonator consisting of a pulsed volt­
age source and a high-Q bandpass filter...............................................
57
5.3 Block diagram of the proposed PLM amplifier....................................
59
5.4 Equivalent circuit model of power combining in the PLM technique. 61
5.5 Normalized DC current, drain voltage and efficiency performance
of an ideal PLM amplifier........................................................................
64
5.6 Efficiency curve of the PLM amplifier versus the classical Doherty
Amplifier......................................................................................................
65
5.7 Simulated drain efficiency and power curves versus duty cycle. . .
67
5.8 Implementation of the PLM amplifier using GaAs FET s..................
68
5.9 Measured drain efficiency curves versus duty cycle.............................
68
5.10 Measured output power curve versus duty cycle.................................
69
5.11 O utput power, gain and drain efficiency curves versus input power
at 17 GHz....................................................................................................
71
5.12 17 GHz PLM power amplifier (a) 2 mm by 3 mm (b) 3 mm by 2 mm 72
5.13 Efficiency and output power curves for duty cycle with 200 MHz
envelope switching (a) efficiency (b) output p o w e r..........................
6.1 Tree structure with bus-bar
73
..................................................................
76
6.2 Tree structure with quaterwave transmission lin e ..............................
77
6.3 Equivalent circuit of the tree structure..................................................
78
6.4 Impedance Transformation.......................................................................
79
6.5 EM simulations for power divider and combiner.................................
81
Efficency, power, gain of 34 GHz power amplifier...............................
82
6 .6
ix
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6.7
Layout of
2
W 34 GHz power ampflier
x
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
L
is t
of
T
ables
1.1 Comparisons of 3G and WiMAX [3 ].....................................................
2 .1
Comparisons of recently reported class E power amplifiers
....
6.1 The performance of 34 GHz power amplifier........................................
xi
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2
13
82
A
ckn ow ledg m ents
It is a great honor for me to acknowledge many people who have supported my
journey toward Ph.D. degree. I must say th at I could not have finished my degree
program without their supports technically, financially, friendly, and lovely.
First and foremost, I would like to acknowledge my advisor, Professor Yuanxun
Ethan Wang. His technical intuitions always amazed me and his guidance was
always invaluable whenever my research had been on the downside. I feel both
honored and privileged to have been a part of his research group where I had
the opportunity to work with many talented people, including Sam Shinder, Itay
Kahaner, Kaihui Lin, Tzung-I Lee, Brian Liao, Lilia Liu, Jessie Xu, Crystal Jing,
Dr. Shinho Kim, and Dr. Wejun Yao.
A sincere appreciation is given to Professor Itoh and his group, including An­
thony Lai, Alexandre Dupuy, Brandon Choi, Dr. Sungjoon Lim and Dr. Younkyu
Chung. They were always supportive when I needed their equipment and techni­
cal discussions. I also thank all of the members of the Center for High Frequency
Electronics (CHFE), including Timothy Brockett, and Raj Sahae. I would es­
pecially like to thank Dr. Yi-Chi Shih from MMCOMM Inc. for his valuable
advice and helpful discussions on MMIC designs. My deep appreciation goes to
MMCOMM Inc. and the Air Force Research Laboratory for partially funding my
research.
I’m deeply grateful to all my friends in UCLA, including Dr. Kilchan Choi,
Jinyong Lee, Hyuckee Sung, Minjae Lee, Gyungsoo Byun, Yooncheol Kim, Dongho
Cha, Dr. Youngwoo Park, Dr. Jongsun Kim, and Dr. Sungsoo Kim. They all en­
riched my life inside and outside of UCLA.
xii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
My final gratitude goes to my family. I can not thank enough for the loving
supports from my wife. She was always with me whenever, wherever I needed
her. I also thank my sister and brother for their continuing supports. Especially,
I want to express my sincere gratitude to my parents, to whom this dissertation
is dedicated.
xiii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
V
it a
1974
Born, Seoul, Republic of Korea
1996
B.S. (Electrical Engineering)
Korea Advanced Institute of Science and Technology (KAIST)
Taejeon, Republic of Korea
1996 1999
Member of Technical Staff
Seodu Inchip Inc.
Seoul, Republic of Korea
2000
Member of Technical Staff
NOKIA Mobile Phones Inc.
Seoul, Republic of Korea
2000 2006
Graduate Research Assistant
University of California, Los Angeles (UCLA)
Los Angeles, California.
2002
M.S. (Electrical Engineering)
University of California, Los Angeles (UCLA)
Los Angeles, California.
2006
Intership
MMCOMM Inc.
Torrance, California.
2006
Ph.D. (Electrical Engineering)
University of California, Los Angeles (UCLA)
Los Angeles, California.
xiv
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
P
u b l ic a t io n s
J. Jeong, Y. E. Wang, ’’Pulsed load modulation (PLM) techniques for high ef­
ficiency non-constant-envelope amplification,” 2007 IEEE Power Amplifier Sym ­
posium, Long Beach, Jan. 2007.
J. Jeong, Y. E. Wang, ”A switching mode power amplifier for envelope-sigma
modulation (EDSM),” 2006 IEEE Topical Workshop on Power Amplifiers for
Wireless Communications, San Diego, Jan. 2006.
Y. Chung, J. Jeong, Y. E. Wang, and T. Itoh, ’’Power level-dependent dualoperating mode LDMOS power amplifier for CDMA wireless base-station appli­
cations,” IEE E Transaction on Microwave Theory and Techniques, vol. 53, pp.
739- 46, Feb. 2005.
J. Jeong, K. Kim, and K. Lee, ’’Temperature independent current supply with
automatic tuning” , The 2nd Korean Conference on Semiconductors, Taejeon,
Korea, Feb. 1995
xv
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A bstract
of the
D is s e r t a t io n
H igh E fficien cy R F and M icrow ave P ow er
A m p lifiers w ith N o n -c o n sta n t E n v elo p e S ign als
by
J in -se o n g J e o n g
Doctor of Philosophy in Electrical Engineering
University of California, Los Angeles, 2006
Professor Yuanxun E. Wang, Chair
In modern wireless communications, the modulation schemes require highly
linear power amplifiers since the high data rate is demanded while the band­
width is restricted. However, the conventional linear power amplifiers suffer from
the degradations of power efficiency because the highest efficiency can not be
maintained when the envelope varying signals are amplified. This dissertation
tackles those technological barriers through the several novel approaches from
architecture to circuit perspectives. First architectural approach, the dual-mode
power amplifier maintains the relatively high efficiency untii the output power is
backed-off by
6
dB. This approach saves DC power by reducing the size of power
amplifier when the output power is backed-off. The size of overall power amplifier
is controlled by turning on and off the small power amplifiers. The technical chal­
lenge is to implement a lossless divider and combiner network with the matched
impedances regardless of the number of active power amplifiers. A proposed
divider and combiner network meet this requirement. Secondly, a novel signal
processing techniques, envelope delta-sigma modulation, utilizing high efficiency
switching power amplifiers are presented. This approach provides a new paradigm
xvi
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
of linear amplification in digital fashion. Using class D amplifier, the feasibility
of this approach is evaluated. In addition to that, a novel power amplifier, class
ED is proposed for this advanced signal processing techniques. Thirdly, a new
concept of pulsed load modulation (PLM) is introduced. The proposed amplifier
maintains the maximum efficiency over a wide range of output power level. The
essential idea is to synthesize the load impedance for optimum efficiency using
switched resonator concepts. A high-Q, bandpass filter in conjunction with two
pulse-biased power amplifiers connected with a A/4 transmission line constitute
the switched resonator. Ideally, for a pair of identically sized and biased class B
amplifiers, the maximum efficiency of 78.5 % is maintained for up to
6
dB back­
off in the output power. The concept is validated by building power amplifiers
at 1.87 GHz with a pair of discrete FETs and at 17 GHz with 0.15 /rm GalnAs
pHEMT technology. The measured results demonstrate th at with the proposed
approach, significant efficiency improvement is obtained over conventional Class
B amplifiers. Lastly, a new power efficient combiner design method is presented
for millimeter wave power amplifiers. In conventional integrated power amplifiers,
most of estate are wasted in power combiner and divider layouts. By utilizing
these unoccupied areas as low loss capacitances, high efficiency power combin­
ing and compact power amplifier design are achieved. This concept is proved
by building 2 W , 44 % PAE, 34 GHz power amplifiers using 0.15 /rm pHEMT
technology.
xvii
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 1
In tro d u ctio n
According to the telecommunications industry association (TIA )’s 2006 an­
nual report [1 ], the revenue in the U.S. wireless market reached $174.7 billion
in 2005. Nearly two-thirds of the U.S. population has already subscribed to a
wireless service and
88
% of the population is expected to subscribe through year
2009. Although wireless voice service has been quite successful, the subscriber’s
desire for the broadband d ata access in mobile environments continues to grow
and it makes wireless services evolve to next generation wireless systems such as
3G, 4G and WiMAX systems. They enable subscribers to enjoy the same experi­
ences as they have at home or in the office with DSL, cable modem or local area
networks (LANs). In other words, broadband data, voice and video services will
be available anytime and anywhere at a reasonable cost.
Since the radio spectrum is already populated, these new technologies are
using highly linear modulation to efficiently utilize the limited bandwidth, i.e.
the envelopes of modulated RF signals are non-constant. Table 1.1 compares the
modulation schemes and the multiple access types of two mainstream 3GS1 and
mobile WiMAX wireless systmes. 3Gs use code division multiple access (CDMA)
for high capacity and mobile WiMAX adopts the orthogonal frequency division
multiple access (OFDMA) for the improved multi-path performance in non-lineof-sight environments [2]. All of them use highly linear modulation such as QAM
XCDMA2000 based and WCDMA based
1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 1.1: Comparisons of 3G and WiMAX [3]
A ttribute
lxEVDO Rev A
HSDPA/HSUPA
Mobile WiMAX
(HSPA)
Base Standard
CDM A2000/IS-95
WCDMA
IEEE 802.16e-2005
Duplex
FDD
FDD
TDD
Downlink MA
TDM
CDM-TDM
OFDMA
Uplink MA
CDMA
CDMA
OFDMA
Channel BW
1.25 MHz
5.0 MHz
5, 7, 8.75, 10 MHz
Modulation DL
Q P S K / 8 PSK /
QPSK/16QAM
QPSK/16QAM /
16QAM
64QAM
Modulation UL
B P S K /Q SK / 8 PSK
BPSK/QPSK
QPSK/16QAM
Coding
Turbo
CC, Turbo
CC, Turbo
and QPSK for high spectral efficiency. Apparently, these highly linear modu­
lations save a lot of bandwidth. However, they trade off with power efficiency.
Therefore, power efficient design of hardware, especially RF transceiver system
design becomes the critical design issues.
RF transceivers have been miniaturized on system on a chip (SoC) using lowcost and low-power integrated circuit (IC) technologies such as CMOS process.
Fig. 1.1 shows a today’s RF transceiver module. It consists of front end module
(FEM), transceiver IC and power amplifier module (PAM). Most of basedband
signal processor and RF receiver have been integrated on low-cost CMOS (IC)
while an attem pt to further shrink the size of module by stacking FEMs on the
transceiver ICs using bulk acoustic wave (BAW) devices has been reported. Al­
though CMOS power amplifier have been announced and have some potential to
integrate with transceiver, it has significant issues yet to be integrated with the
rest of the transceivers. Also, the power efficiency of CMOS power amplifier is
2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X
VCXO
Crystal
Front End
Module
Transceiver
PA Modulo
Figure 1.1: RF Module Trends (Courtesy of TI [4])
usually inferior to compound power amplifiers. So far, the compound processes
have been dominant in power amplifier business. Even with these decent pro­
cesses, power amplifier faces efficiency issues when it has to amplify the linear
modulated signals. To make it worse, most modern wireless standards require
power controls which results in high dynamic range of power amplifier. There­
fore, power amplifier remains as the most power-hungry component and the most
challenging design block of wireless systems. Efficient power amplifiers or trans­
mitting systems are inevitable for mobile cell phones assuming the battery tech­
nologies will not have a breakthrough in the near future. Also, inefficient power
amplifiers must be prohibited in high power amplifiers because the reliability is
the most im portant concern in base station applications.
The efficiency of power amplifier can be improved through either architec­
tural innovations and/or the advanced circuit design techniques. This disserta­
tion covers both perspectives in th at Chapter 3 through Chapter 5 covers ar­
chitectural techniques and Chapter
6
does the circuit techniques. Starting with
the overview of the conventional power amplifier topologies and architectures in
3
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 2, where the advantage and disadvantage of each classes and schemes are
discussed, Chapter 3 introduce the first architectural efficiency improvement tech­
nique based on dual-mode power combiner and splitter. Chapter 4 introduces a
novel signal processing techniques utilizing highly efficient switching mode power
amplifiers and Chapter 5 presents the pulsed load modulation (PLM) schemes
where the signal processing techniques in Chapter 4 are applied. Finally, a new
circuit design techniques for millimeter wave power amplifiers are introduced in
Chapter
6
and this dissertation concludes in Chapter 7.
4
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 2
O verview o f R F an d M icrow ave P ow er
A m p lifiers and T ran sm itter A rch itectu res
2.1
In tr o d u c tio n
The RF and microwave power amplifiers are used in various applications such
as wireless communications, broadcasting systems and radar systems. W hether
it is required to generate a few hundreds of watts in TV broadcasting applications
or a few milli-watts in wireless networks, the function of power amplifier can be
defined as converting DC power into RF power [5]. The performance of power
amplifier is mainly evaluated on how well this conversion is achieved, i.e. the
linearity and efficiency. Both parameters are equally im portant in modern power
amplifier design for any applications. However, achieving both simultaneously
has remained as the most challenging goal over the years. This chapter explains
the reasons why it is difficult to achieve both by introducing the operation prin­
ciple of conventional power amplification schemes. It begins with discussions
on how to assess the performance of power amplifiers, which can be done by
defining parameters such as adjacent channel power ratio (ACPR) and/or er­
ror vector magnitude (EVM) and drain efficiency and/or power added efficiency
(PAE). Then, the basic classes of power amplifiers including the linearity and
the efficiency of each class are discussed. Finally, the efficiency and linearity
5
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
improvement techniques for non-constant envelope signals are introduced and
investigated.
2.2
P er fo r m a n ce P a r a m e te r s o f P o w er A m p lifiers
2.2.1
L inearity
One of the critical factors in the design of power amplifier is the linearity.
The linear power amplifiers are not required for the constant envelope signals
such as FM, FSK and GMSK 1 because no amplitude modulations are necessary.
However, pulse shaped signals such as QPSK or QAM are popular due to the
demands for higher d ata rates and efficient utilization of spectrum. Such signals,
which are usually generated by I and Q sub-carrier modulation, contain both
amplitude and phase modulations, therefore, have non-constant envelope with a
peak-to-average ratio (PAR) of 3 to
6
dB. In addition to that, power control of
about 10 dB is required in 3G standards which makes overall PAR of 13 to 16 dB.
T sed in GSM systems
CD
■Q
D
"q .
E
<
Time
Figure 2.1: OFDM envelope waveform (802.11a)
6
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ftjvAAAAAAA/y|>/wV\AAA/yVM
15 kHz
1.98 MHz
Figure 2 .2 : Example ACPR specification (Courtesy of Agilent)
The multiple carrier systems such as cellular base station, mobile WiMAX, and
high definition television (HDTV) systems, also have peak-to-average ratio of
8
to 13 dB. The typical time domain waveforms of multiple carrier signals are
depicted in Fig. 2.1.
Linearity can be measured and characterized by several methods. Among
them, adjacent channel power ratio (ACPR) is typically used for pulse shaped
signals. The ACPR is defined by the ratio of the power in a specified band
outside the signal bandwidth to the rms power in the signal band [5]. Figure 2.2
shows the examples for ACPR measure. Another measure for linearity is error
vector magnitude (EVM). A signal transm itted by an ideal power amplifier would
have all constellation points precisely at the ideal locations. However, the actual
constellation points is deviated from the ideal location due to the nonlinearity in
7
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the power amplifiers. 2 The EVM measures the non-linearity of power amplifier
by calculating how far the actual constellation points are from the ideal locations.
2.2.2
Efficiency
The typical efficiency measures for power amplifier are the drain efficiency (77)
and the power-added efficiency (PAE), which are given by
P out
(2 . 1)
P dc
PAE
Pout Pin
PiD C
( 2 .2 )
In most of power amplifiers, these efficiencies have the maximum values when the
output is at the peak output power (PEP) and drops quickly as the output power
is backed-off as described in Fig. 2.3. In other words, the efficiencies are varying
2Deviation can be caused by other factors such as carrier leakage and phase noise.
Max.
Efficiency
PEP
>1
o
c
0)
o
►
Pout
Figure 2.3: Typical efficiency curves of power amplifier
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0.6
£
o
Q
0.4
0.5
0
1
Normalized Envelope
Figure 2.4: OFDM envelope PDFs.
depending on the amplitude of output RF signals. For constant envelopes signals
such as FM and GMSK, the amplitude stays at PE P such th at the efficiency does
not degrade. However, for non-constant envelope signals, the maximum efficiency
can not be maintained. In this case, the average efficiency is more useful and it
can be defined by
Va v g
out—AVG
=
(2.3)
Pdc- avg
As shown in Fig. 2.4, most of the time, the amplitude of RF signals stays at
much lower level than the PEP. This results in severe degradation in average
efficiency. Given the probability density function (PDF) of envelope and the
profile of the efficiency of a specific power amplifier, the average efficiency can
be easily calculated by integrating the product of PDF and the efficiency of
power amplifier at th at amplitude. For example, assuming Rayleigh-distributed
envelope for multi-carrier signal with a 10 dB peak-to-average ratio, the ideal
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
class A and B power amplifier have the average efficiency of merely 5 % and 28
%, respectively [5].
2 .3
P o w er A m p lifie r C la sse s
RF power amplifiers are classified as class A (or AB), B, C, D, E and F.
Among them, class A (or AB), B, and C are classified as linear amplifiers and
class D, E and F as switching mode power amplifiers.
Every class of power
amplifiers can be represented in single-ended form in Fig. 2.5 except switching
mode power amplifiers. The combination of biasing condition in Fig. 2.6 and
harmonic termination determines which class the power amplifier belongs to. The
details of each class are explained in the following sections. For fair comparison
between classes, the maximum drain current and voltages of FET are usually
Vdc
Q
Vbias
RL
Harmonic
Termination
Figure 2.5: General single-ended circuit configuration of RF PAs
10
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Saturation
Imax
Imax/2
Class A
Class B, F
— ►
VG
Pinch-off
Figure 2.6: Ideal biasing curve of FETs
normalized to 1 A and 1 V, respectively.
2.3.1
2.3.1.1
Linear Pow er A m plifiers
C lass A (or A B )
Class A and class AB are most popular linear amplifiers in commercial prod­
ucts due to their robustness and high linearity. In class A, the gate bias voltage
is selected such th at the quiescent current is the half of maximum drain current.
The transistor is always in active region. As the drain voltage as well as current
are sinusoid, class A power amplifier is inherently linear and no harmonic termi­
nation is necessary. DC power consumption is always constant so th at maximum
efficiency is 50 % at PEP. Although the efficiency is low, class A has highest gain
among all other classes. Because no harmonic is generated, class A can be used
at the maximum frequency (fx) of the transistor [5]. To improve the efficiency
11
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
of class A, the gate bias is slightly lowered in class AB. Since the non-linearity is
usually weak, no harmonic termination is required in class AB as well.
2.3.1.2
Class B
In class B, the bias voltage is selected such th at the quiescent current is zero.
Therefore the transistor is conducting half of RF cycles. Although class B is still
linear, the harmonic term ination is necessary. DC power consumption is less than
th at of class A by
7t / 2
so th at the maximum efficiency is
7t / 4
(78.5 %) at PEP.
Because the gain of class B is 6 dB lower than th at of class A, class B is usually
configured as push-pull to utilize both phases of input signals.
2.3.1.3
Class C
In class C, the gate is biased below pinch-off voltage so th at conduction period
is less than half of RF cycles. Class C is not linear any more. However, the
efficiency is increased because DC power consumption is further reduced. The
efficiency can be made arbitrarily high up to 100 % by reducing conduction
period, but output power is reduced to zero, accordingly.
Although class C
power amplifiers are rarely used in stand-alone forms, it is used in conjunction
with other classes. Such a scheme is Doherty amplifiers.
2.3.2
2.3.2.1
Sw itching M od e Pow er A m plifiers
Class D
In class D, two transistors are used as switches. Two switches are on and
off complementarily. Square waveform of drain voltage is filtered by series tuned
output filter. Ideally, the efficiency reaches 100 %. However, in high frequency
12
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
application, class D is rarely used because of on resistance of switch and switching
power loss by charging and discharging the drain capacitance [6]. Instead, class D
is popular in audio amplifier applications. In Chapter 4, the feasibility of class D
for RF applications will be discussed with the detailed analysis along with novel
signal processing techniques.
2.3.2.2
C lass E
Unlike class D and F, class E amplifier does not require rectangular waveform.
It utilizes a single ended transistor and a shunt capacitor to realize charge and
discharge of the current. Shunt capacitance includes both intrinsic output capac­
itance of the device and external capacitance. In class E, transistor is used as
on-to-off switch and it creates ideal none-overlapping voltage and current wave­
forms, which results in 100 % efficiency. Since there are no charging/discharging
losses, class E is a good candidate for high frequency applications. Tremendous
amount of researches are going on throughout the industry and academy [7]-[13].
Table 2.1 compares recently reported class E amplifier at various frequencies.
Fig. 2.7 is class E amplifier at 17 GHz with output power of about 30 dBm and
PAE of 45 % reported from UCLA.
Table 2.1: Comparisons of recently reported class E power amplifiers
Frequency
p
1 out
PAE
V
[GHz]
[dBm]
[%]
[%]
[12]
5-6
20.1
47.0
58.4
[13]
9-11
22.0
65
Fig. 2.7
17
30.0
45.0
Class E
Process
BiCMOS
InP DHBT
52.0
GalnAs pHEMT
13
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 2.7: Class E Power Amplifier at 17 GHz
2.3.2.3
Class F
Class F power amplifier is intrinsically a slightly overdriven Class B amplifier
with special harmonic terminations. The spectrum of a rectangular wave has
zeros at even order harmonics and peaks at odd order harmonics. The harmonic
termination should act as matched for the fundamental, open circuit for odd har­
monics, short circuit for even harmonics. The efficiency of an ideal power amplifier
increases from class B efficiency, 78.5 %, to 100 %, depending on the number of
harmonic terminations [14], The reported efficiency number is competitive with
class E given the same operation frequency and output power requirements.
14
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2 .4
P o w er A m p lifie r A r c h ite c tu r e s for N o n -c o n sta n t E n ­
v e lo p e S ig n a ls
2.4.1
T h eoretical Backgrounds
As discussed in Section 2.2.2, the efficiency of power amplifier drops when the
input driving power and/or output RF power are backed-off. Fig. 2.8 describes
the mechanism of efficiency drops by using the ideal loadline of class B. Other
switching classes may have different loadlines, but will show the same tendency
when the power is backed-off. Efficiency drop can be explained if we rewrite (2.1)
in terms of voltages and currents by
1 Vrf L
2 VDc I d c
P
Pdc
(2.4)
where VRF and I RF are the amplitudes of output voltage and current, Vdc is
drain supply voltage, IDc is average supply current. When back-off, VRF, IRF
and I d c are reduced accordingly, however, Vdc stays as depicted in Fig. 2.8(b).
For example, with 6 dB back-off, the efficiency becomes the half of maximum
efficiency since VRF, IRF and IDc are all halved except Vd c ■ Therefore, efficiency
is halved for every 6 dB power back-off such th at the efficiency curves have the
shapes depicted in Fig. 2.3.
Two methods can be applied to maintain the maximum efficiency while the
output power is backed-off. One is the voltage modulation and the other is load
modulation. In voltage modulation, Vd is modulated depending on input power
level such th a t (2.4) has a constant maximum value as depicted in Fig. 2.9(a).
Envelope Elimination and Restoration (EER)3 and adaptive biasing techniques
3also known as Kahn technique or polar modulation
15
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I dss
Fundamental
Loadline
Class B
Loadline
V dc
(a )
Id s s
6 dB Back-off
V dc
Vd
(b)
Figure 2.8: Loadline analysis (a) class B loadline (b) 6 dB back-off
belong to this voltage modulation.
In load modulation, the load impedance
changes according to power level such the power amplifier always operates in sat­
uration mode. In Fig. 2.9(b), the amplitude of output voltage does not change
which means th a t the load impedance changed and the efficiency in (2.4) is main­
tained. However, output power is backed-off by 3 dB in this case. There are many
16
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Id
I dss
Voltage
Modualtion
V dc
(a)
Id
Idss
Load Modualtion
V dc
Vd
(b)
Figure 2.9: Efficiency enhancement methods (a) voltage modulation (b) load
modulation
ways to achieve the load modulations depending on how to make load modula­
tion as well as how to bias the power amplifiers. Doherty amplifier and Chireix’s
outphasing belong to this category.
Recently, exhaustive researches have been performed to improve both the
17
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
linearity and efficiency of power amplifiers. Most of them are originated from
old techniques of vacuum tube era, which are K ahn’s EER techniques, Doherty
amplifier and Chireix’s outphasing. In next sections, these old techniques are
revisited and how they can be applied to the modern modulation schemes and
the advantage and disadvantages of each scheme are investigated.
2.4.2
E nvelope E lim in ation and R estoration (EER)
The K ahn’s envelope elimination and restoration (EER) transm itter consists
of a highly efficient switching mode power amplifier and a envelope amplifier [20].
A phase-modulated constant envelope signal is amplified by high efficiency switch­
ing power amplifier and voltage modulation is applied to the supply of output
power amplifier to restore the envelope information. Ideally, Kahn transm itter
generates an amplified replica of the input signal without loosing phase and en­
velope information. As shown in Fig. 2.10, both the amplitude and the phase
Lowpass
Filter
Envelope
Modulator
Amplitude
Baseband
Processer
Phase
Power
Amplifier
Figure 2.10: Kahn Transmitter
18
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
information are generated by a digital baseband processor. The amplitude is
usually modulated by delta-sigma modulator to maintain the high efficiency of
envelope amplifier and linear lowpass filter is placed to filter out the out-of-band
noise. It is reported th at the average efficiencies is three to five times higher than
those of linear amplifiers [21] [42],
Kahn transm itters suffer from two factors, the bandwidth and the mismatch
between the envelope path and the phase path. The envelope bandwidth must
be at least twice the RF bandwidth and the mismatch must not exceed on tenth
of the inverse of RF bandwidth [22]. The group delay of the lowpass filter makes
it difficult to satisfy these requirements. Therefore, this architecture is used only
in narrow band systems such as GSM /EDGE systems. In Chapter 4, envelope
delta-sigma modulation (EDSM) techniques are introduced to overcome this lim­
itations. Another drawbacks of Kahn techniques are AM-to-AM and AM-to-PM
distortions. Due to the power control requirements, predistortion techniques are
used for both the envelope and the phase [17]. In predistortion, any variations
caused by tem perature and supply fluctuation should be taken care of, which
necessitate exhaustive characterization and calibration. In [19], by using closedloop control of the transm itted phase as well as the amplitude modulation, the
limitations of the open-loop Kahn architecture are somewhat overcome. By tak­
ing the feedback signal from the output of the power amplifier, the AM-to-AM
and AM-to-PM distortions are corrected to a very high degree.
2.4.3
D o h erty A m plifier
The Doherty amplifier [25] consists of carrier and peaking amplifiers4 con­
nected with A/4 transmission line at the amplifier outputs as depicted in Fig. 2.11.
4also called as ‘main’ and ‘auxiliary’ amplifier
19
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
RF
Input
Main PA
o
"O
Aux PA
Figure 2.11: Doherty Amplifier
Another A/4 line is added at the input of peaking power amplifier to compensate
the 90° phase shift. Both amplifiers have the same maximum current and the
carrier amplifier is biased in class B while the peaking amplifier in class C. Class
C biasing point is determined such th at the peaking amplifier is only activated
when the output power is greater than 6 db back-off. When the peaking ampli­
fier is pinched-off, the output impedance of peaking amplifier is relatively high.
Therefore, the carrier amplifier sees the optimum load impedances and exhibits
the maximum efficiency at 6 dB back-off. When the peaking amplifier is acti­
vated, the efficiency of the peaking amplifier starts increasing while the carrier
amplifier remains at saturation mode exhibiting maximum efficiency due to load
modulation. As a result, Doherty amplifier has two peak efficiency points at PEP
and 6 dB backoff while the relatively high efficiency is maintained in between.
In Chapter 5, this efficiency dip is avoided using pulsed load modulation (PLM)
techniques. It is also reported th at the maximum efficiency range can be further
20
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
extended through either the multi-stage Doherty amplifier [39] [29] or using the
different size ratio between the carrier and peak amplifiers [49].
The Doherty amplifier faces several design issues when it’s implemented. The
first one is the design of peaking amplifier. It has to have the twice gain of
carrier amplifier while maintaining the same capacity. Also, it requires careful
pinch-off biasing which is always sensitive to tem perature variations. The output
impedance of the peaking amplifier when it’s pinch-off is another issue. Since it is
not a perfect open circuit, it degrades overall efficiency. This is the reason why the
reported efficiency curves never exhibit the distinctive two peak points. Above
addressed problems are completely overcome in PLM schemes in Chapter 5.
2.4.4
C h irix’s O utphasing
Also known as linear amplification using nonlinear components (LINC) [30],
the outphasing transm itter in Fig. 2.12 generates non-constant envelope signal
by combining two different phase-modulated signals with constance envelopes.
Si(t)
-------- ►
S_
Sin(t)
o
35
i n
q_
< 1
G(Si(t)+S2(t))
S2(t)
-------- ►
Figure 2.12: Outphasing Amplifier
21
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
An AM-to-PM modulator which consists of baseband signal processor and RF
synthesizer generates two constant envelope RF signals th at are efficiently am­
plified, combined and eventually generate non-constant RF signals. Ideally, two
constant envelope signals can be amplified with maximum efficiency using the
switching mode power amplifiers. However, the normal combing schemes lose the
power efficiency according to the output power levels since two signals are inher­
ently out-of-phase and therefore the load impedances are reactive. It is reported
this wasted out-of-phase power can be recycled [32], but it is not an ultimate
solution. The Chireix combining relaxes the efficiency degradation by tuning out
the reactive component at a specific out-of-phase level maximizing the efficiencies
around this optimum output power level. The average efficiency of non-constant
envelope signal is improved over the conventional linear amplifier. For example,
an average efficiency of 52.1 % can be achieved for an ideal class B amplifier with
10 dB Rayleigh envelope signals [40]. However, the Chireix combining is rarely
used in practical applications since it is hard to make perfect voltage sources
at RF and microwave frequency ranges and they cause distortions [34]. While
the outphasing exhibits a wide bandwidth, predistortion or feedback loop are
necessary since it has severe distortions.
22
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 3
D u a l-M o d e P ow er A m p lifiers
3.1
In tr o d u c tio n
As discussed in 2.4, the load modulation techniques are used in Doherty ampli­
fier and outphsing amplifier in the form of load pulling and the voltage modulation
techniques are used in Kahn techniques. Another way to enhance the efficiency
is to change the periphery size of the power amplifier depending on the power
levels [38]. The basic idea is to save DC power by reducing the size of power
amplifier for low power output. This approach also can be classified as the load
modulation technique since the load impedance should be changed according to
the size of power amplifier for optimum efficiency. This Chapter discusses newly
proposed dual-mode power amplifier based on this load modulations.
3.2
P r in c ip le o f O p e r a tio n s
In power amplifier designs, usually, multiple power amplifiers are combined to
generate high power regardless of hybrid or MMIC implementations as depicted
in Fig. 3.1. The power combining methods will be further discussed in Chapter 6.
Figure 3.2 shows the efficiency curves for single power amplifier alone and 4 power
amplifiers combined. Theoretically, the efficiency curve of combined amplifiers
moves rightward by 6 dB from single power amplifier case such th at PE P is
23
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PA
PA
PA
PA
Figure 3.1: Power amplifier combining method.
4 PAs
PA
o
c
<D
O
6dB
LLl
c
►
Q
► Pin
Figure 3.2: Drain efficiency curves for single and four amplifiers.
24
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6 dB higher than single power amplifier.
However, at the same input power
level, for example, at the PEP of single power amplifier, the efficiency of four
power amplifiers is much less than th at of single power amplifier. Reasonable
approaches would be utilizing the efficiency curves of both cases indicated as the
red line in Fig. 3.2. This can be achieved by controlling the number of effective
power amplifiers depending on the input power level. However, careful design of
combining network is necessary.
3 .3
P r e v io u s W ork s
Several promising approaches have been recently proposed in UCLA research
group.
Among them, the dual-mode combining scheme has proven to be an
effective approach in increasing power efficiency without compromising linearity
performance [35] [36]. The dual-mode combining is done by using an amplifier
combining scheme th at combine the output power from an array of amplifiers
while the number of amplifiers in use is selected according to the signal input
power level. The technical challenge for such a system is to realize a lossless
combiner network with impedance always matched at each different selection
state.
The objective to maintain the impedance match is to avoid the extra
distortion introduced by the gain and phase changes during the switching process.
The dual-mode topology is shown in Fig. 3.3. This power combining network
consists of a four-amplifier array and a 50 fl matched microstrip combiner. When
the signal level is low, the combiner is operated at its lower power mode. The
combining scheme for this mode of operation is shown in Fig. 3.3(b). In this
mode, only one amplifier is active, while all others are off. When an amplifier is
turned off, its output impedance is nearly infinite1. The dual-mode combiner is
1open-circuit
25
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X/ 4
X/ 4
ohms
X/4
X/4
X/4
Microstrip Combiner
(a)
X/ 4
S z„
P£>
' I Open
V2Z0
IJ
1--------I
Open
V2Z„
1 Open
Open
l«-l
V2Z.
i
X/ 4
s
-
! Open
I d _____
1
I
I
!
50
ohm
V2Z0
I
Off
(b)
Figure 3.3: Dual-mode combiner under (a) high power mode (b) low power mode
designed using this fact in such a way th at the active amplifier is able to deliver
power to the matched output load with minimum influence from the loading of
the other three amplifiers. This is done using a number of quarter-wavelength
transformers. For higher signal level, the combiner can be switched to its higher
power mode of power combining operation. This state is described in Fig. 3.3(a).
26
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In this case, four parallel amplifiers are evenly delivering the maximum power to
the 50 O load. Notice th at 50 f I quarter-wavelength transformer must be added
at the input of the 3rd and 4th amplifiers so th at the power can be added in
phase at the output.
3 .4
D u a l M o d e D iv id e r an d C o m b in er
Dual mode combiner utilizes a fact th at the output impedance is almost re­
active when the FETs are in the deep pinch-off region [37]. Fortunately, the
same assumption can be applied to the input impedance. To verify this, 4 test­
ing power amplifiers are fabricated using Fujitsu FLL351 GaAs devices at the
target frequency of 2.2 GHz. About 1.1 dB of return loss is measured for output
impedance and about 1.2 dB is measured for input impedance when the gated
is biased at -5 V and the drain voltage is at 10 V. Using this fact, dual mode
divider can be constructed in the similar way as dual mode output combiner us­
ing quarter wave transmission lines. The overall architecture of dual mode power
amplifiers with dual mode divider and combiner is depicted in Fig. 3.4.
At lower power mode, the bottom three power amplifiers are turned off. To
take advantage of reactive input impedance of power amplifiers when power am­
plifiers are deeply pinched-off, the input impedance should be made to be short
circuit other than open circuit in case of output impedance. This can be ma­
nipulated by adding 50 Q transmission lines at the input and output of power
amplifiers. By doing this, at lower power mode, point A, B, C and D in Fig. 3.4,
all achieve the open circuit. As a result, input power is amplified only by the
upper amplifier minimizing the losses at the other branches. The insertion loss
of input divider at lower power mode is measured to estimate the improvement
over switching divider. The insertion loss of 0.82 dB for input divider and 0.78
27
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(q >
,N
u .
c
,N
gC
c<U
N
0
^r
N
0
M
0
o
N
u .
c
O
-AA/V-----
a
O
Ln
Figure 3.4: Schematic of Dual-mode power amplifier with dual mode divider and
combiner
28
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.5: Photograph of fabricated dual-mode power amplifier
dB for output combiner was measured. Both of them are just half of the in­
sertion loss of switching divider. At higher power mode, other than switching
divider, four branches are all conducting without any conducting loss. In other
words, higher power mode is the exactly same as conventional power combining
scheme as described in Fig. 3.4. In this case, the gain and efficiency curves are 6
dB shifted version of those of single amplifier. Any improvement in lower power
mode results in overall efficiency improvement.
Fig. 3.6 shows the measured gain and PAE for lower power mode and higher
power mode. The gain and PAE of single amplifier are also measured for com­
parison purpose. As expected, the gain and the efficiency of higher power mode
are not dropping much from single power amplifier. However, the gain of lower
power mode drops by more than 3 dB although the insertion losses of input di­
vider and output combiner were improved. The reasons for this degradation on
both gain and efficiency were investigated through ADS simulations. The main
reason is the leakage power from output to input when the FETs are turned off.
29
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Gain - Single PA
35
Gain - lower power mode
Gain - higher power mode
PAE - Single PA
PAE - lower power mode
PAE - higher power mode
m
OE
<£ 25
Q.
I 20
ST
pc - 15
m
0
0
5
10
15
20
25
30
35
Pin [dBm]
Figure 3.6: Measured gain and PAE of dual-mode power amplifier.
Imperfection of open circuit in output combiner draws some amount of output
power and it is returned to input divider and it is negatively combined with input
power so th at the gain is reduced. It could be manipulated by adjusting length
of transmission lines of divider and combiner, but it is not preferred because of
stability problems. Only way to resolve this problem is to reduce the size of
capacitance between gate and drain of FETS.
3.5
F u tu re W orks
The concepts described in 3.4 can be explored in the opposite direction. Given
the specified output power, single power amplifier can be divided by 4 power am-
30
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PA
V2Z,
V2Z,
PA
PA
V2Z,
Nd = 2N s + 1
V2Z,
V2Z.
Tri-m ode Combiner
Figure 3.7: Tri-mode combining scheme.
plifiers, which have 6 dB lower PEP. These power amplifiers can be further divided
by 16 power amplifiers, which have 16 dB lower PEP. In this case, tri-mode can
be used and the efficiency at the lower power level could be further improved
over dual mode case. However, the current dividing and combining scheme has
limitation because the number of power amplifiers is exponentially increasing as
the mode is added. The new combining scheme described in Fig. 3.7 is more
promising in terms of the number of power amplifier devices. In this scheme, the
number of devices is linearly increasing. It reduces not only the number of devices
but also the number of quarter wave transmission lines. However, the capacity
of power amplifier should be doubly increased which make it almost impossible
to implement using discrete devices. Integrated circuit implementation is more
preferred in this scheme.
31
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 4
E fficient Im p ro v em en t T echniques U sin g AE
M o d u la tio n
4.1
In tr o d u c tio n
Other than linear power amplifier, the switching mode power amplifiers such
as Class D, E and F are high efficiency power amplifiers by nature. Ideally, the
efficiencies of those amplifiers are reaching 100 %. However, the envelope varying
signal cannot be amplified without distortions in such high efficiency amplifiers.
Therefore, the switching mode power amplifiers are not appropriate for the high
capacity modulation schemes such as PSK and QAM. To utilize this high ef­
ficiency power amplifiers for linear amplification, the techniques such as Kahn
techniques and outphasing were developed. However, as discussed in Chapter 2,
there are pros and cons for these conventional efficiency enhancement techniques.
Recently, a new linearization technique using the sophisticating signal process­
ing has been proposed for high efficiency switching mode power amplifiers. The
essential idea is to use digital pulse modulations such as AE modulations in the
amplification process. The Bandpass A E Modulation (BDSM) was utilized to
linearize high efficiency switching amplifiers such as Class S and Class D [45] [50].
In [43] [44], Envelope A E Modulation (EDSM) was proposed to overcome the
drawbacks of BDSM in a similar form of Kahn techniques. EDSM is practi-
32
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
cally more promising because the AE modulator modulates the envelope of RF
input instead of modulating RF input itself as in BDSM. It relaxes the speed
requirements of AE modulators and also reduces the switching rate to below RF
carrier frequency. In this chapter, the performance and feasibility of EDSM is
theoretically studied and the issues associated with EDSM are discussed in terms
of implementations. In addition, a new circuit topology is proposed for EDSM
schemes.
4.2
A E M o d u la tio n
The quantization errors, also called as quantization noises, always exist when
a continuous signal is sampled. Statistically, these errors have no correlation
between samples if the step size of quantization is smaller than the variation
of continuous signal. Therefore, it is usually modeled as white Gaussian noise.
However this quantization noise can be reduced if the signal is sampled fast
enough beyond Nyquist-rate because the spectrum of quantization noise is widely
spread in the sampling frequency band. The reduction of in-band quantization
noise level is estimated by an oversampling ratio (OSR), which is defined as a
ration between the sampling rate and the Nyquist-rate. The AE modulator is
basically oversampling modulator with noise shaping features. Using the low pass
filter in the negative feedback, most of the quantization noise power is pushed to
higher frequencies so th at in-band quantization noise is further reduced. Fig. 4.1
illustrates first-order noise shaping in A E modulator. The input x to the circuit
feeds to the quantizer via a low pass filter, or an integrator, and the quantized
output y feeds back to subtract from the input signal. This feedback forces the
average value of the quantized signal to track the average input signal. Any
persistent difference between them accumulates in the integrator and eventually
33
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
q
A/D
A/D
♦
q
A/D
i/(z-i) h CD
A/D
q
A/D
A/D
Figure 4.1: First order AE modulator [51].
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Shaped
Quantization
Noise
In-band signal
I - — — — —
i
//
i /
— — — — — — —
Raw Quantization
Noise
Frequency
Figure 4.2: Noise spectrum after shaping [51].
corrects itself. Fig. 4.2 shows the noise spectrum after noise shaping where inband noise is suppressed and most of noise power is pushed to high frequency.
To demonstrate the noise shaping feature of delta-sigma modulator, 1 bit
delta-sigma modulator is implemented in ADS. The original signal and the mod­
ulated signal is compared in Fig. 4.3. A sinusoid signal with 9 MHz frequency in
Fig. 4.3(a) is discretized by delta-sigma modulator to become a burst of pulses
as shown in Fig. 4.3(b). The spectrums of such pulses are plotted in Fig. 4.4.
Fig. 4.4(a) demonstrates the spectrum of the delta-sigma modulated signal with
a 16 oversampling ratio and it is compared against the spectrum of original 9
sinusoid signal. If we consider the frequency band up to 10 MHz is what we are
interested as in-band signal. The in-band quantization noise for oversampling
ratio of 16 is about 35 dBc from the signal level. When the oversampling ratio is
increased from 16 to 32 as in Fig. 4.4(b), the in-band noise level drops to almost
50 dBc, which can satisfy the need of most communication systems. Another
way to obtain better quantization noise shaping is to use higher order low pass
35
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1.0
"O
9-
0.6
0.4
i
100
Time (ns)
i
i
r
300
(a)
I
100
Time (ns)
3oo
(b)
Figure 4.3: (a) 9 MHz sinusoid signal (b) Delta-Sigma modulation of sinusoid
filters in the feedback loop of delta-sigma modulators which will result in higher
order delta-sigma modulators.
36
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-100-
I
0
I
I
I
I
10
I
I
I
I
i
20
I
I
I
I
I
30
I
I
I
I
I
40
I
I
I
Freq. (MHz)
I
50
(a)
I
o
CL
-
40-
-
60-
-
80-
Freq. (MHz)
-100
0
10
20
30
40
50
(b)
Figure 4.4: The spectrum of the A E modultaed signal compared the original 9
MHz signal spectrum, (a) 16 OSR (b) 32 OSR
37
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
RF Input— ►
RF Output
►
Switching
PA
Output
Filter
Figure 4.5: Switching PA with AE modulator.
4 .3
S w itc h in g M o d e P o w er A m p lifiers w ith A S M o d u la ­
to r
Thanks to the noise shaping property of delta-sigma modulator, high efficiency
amplification is possible for non-constant envelope signals without scarifying the
linearity. As illustrated in Fig. 4.3, a non-constant envelope signal can be con­
verted to a binary bit stream which preserves in-band signal information and can
be efficiently amplified with switching amplifiers. Finally, the original signal is
recovered by filtering the out-of-band quantization noise at the output. How­
ever, implementing this delta-sigma modulator is almost impractical because,
for RF input of few Giga Hertz, extremely high sampling is required to shape
the noise and the switching PA has to operate at that oversampling frequency.
Moreover, the input impedance of the power amplifier has to be matched over
the broad bandwidth of the input signal, from DC to many times of the carrier
frequency[43]. In [45], bandpass delta-sigma modulation (BDSM) is used to re­
duce the sampling rate. In a BDSM, a lower sampling rate can be used as long as
it is much greater than the bandwidth of interest presented in the input signal.
38
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
DC Supply
Output Filter
RF Input
RF Output
Limiter
Switching PA
Figure 4.6: Switching PA with envelope delta-sigma modulator.
Starting from a suitable lowpass delta-sigma modulator, a lowpass to bandpass
frequency transformation is performed to place the center of noise transfer func­
tion at the carrier frequency. In BDSM, the oversampling should be at least 4
times of carrier frequency to achieve reasonable distortion levels. For example,
a
1
GHz RF input needs 4 GHz delta-sigma modulator, which is still a burden
in current solid state technology. The efficiency of Class D power amplifier with
BDSM was investigated in [50]. Theoretically, the drain efficiency of switching
amplifiers are reaching
100
% for constant envelope signals so th at the overall
efficiency of BDSM should be the same as constant envelope cases if it is driven
by delta-sigma modulated bit-stream. However, it cannot be achieved in practice
for several reasons. Among them, the most serious one is the switching power
loss. As the frequency goes higher, the switching power loss is becoming the
principle source of efficiency degradation in BDSM.
In [43] [44], the envelope delta-sigma modulation (EDSM) was proposed to
overcome the drawbacks of BDSM in a similar form of Kahn Techniques. In
EDSM as shown in Fig. 4.6, the envelope of RF input is detected and feeds to
lowpass delta-sigma modulator instead of RF input itself feeding to bandpass
delta-sigma modulator.
It relaxes the speed requirements and complexity of
39
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
delta-sigma modulators. In [50], it is shown that the average switching rate is
more im portant than the sampling rate of delta-sigma modulator in term of the
efficiency degradation due to switching power losses in class D power amplifier.
In EDSM, the number of transition, which means the average switching rate, is
further reduced because when the output of the delta-sigma modulator is low,
the carrier transition is disabled for certain periods, which makes the average
switching rate lower than carrier frequency.
4 .4
S w itc h in g M o d e P o w er A m p lifie rs for E n v e lo p e D e lta sig m a M o d u la tio n (E D S M )
4.4.1
Class D Pow er A m plifier w ith E D SM
The improvements and the limitations of the envelope delta-sigma modulation
scheme (EDSM) on current driven power amplifiers were addressed in previous
sections. The EDSM is more suitable for switching mode power amplifiers such
as Class D and Class E because the transistors are operating at cut-off and
saturation region while most PA is operating in active region. However, as the
frequency of operation goes higher, switching power amplifiers suffers from power
losses due to the on-resistance of transistor and the drain capacitance. In this
section, the performance improvement and the limitations of the EDSM on the
switching power amplifiers, specifically voltage mode class D, are investigated.
Fig. 4.7 shows the schematic of voltage mode class D (VMCD), usually referred
to as class D, power amplifier and the drain voltage and current waveforms. Two
transistors are on and off alternatively such th at the voltage waveform is the
square wave.
The series resonator with the resonant frequency equal to RF
frequency makes output current wave form to be a sinusoid signal. Therefore,
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VDD
H4,
M2
RL
(a)
M1
<
x
M2
x
M1
M2
><------ ►
► t
13
o
c
2
t
Q
(b)
Figure 4.7: (a) Voltage mode class D power amplifier and (b) waveforms [6 ].
the drain current of each transistor becomes a half-wave rectified sinusoid as
shown in Fig. 4.7(b). Ideally, no overlapping of the current and voltage at the
41
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VDD
M1
180
AS
M2
RL
Figure 4.8: Simulation setup for VMCD with EDSM.
drain makes the efficiency to be 100 %. However, the drain capacitance need to
be charged and discharged every transition and it causes the current spikes and
the switching power loss given by
Ploss — ^
d s Vd d
/ rf
(4-1)
This switching loss is independent of on-resistance of transistor and becomes the
dominant efficiency degradation factor at high frequencies.
The block diagram of the simulation setup for voltage mode class D power
amplifier with EDSM is depicted in Fig. 4.8. For fair comparison with BDSM
in [50], an Excelics EPA240B heterojunction FET is used for the class D power
amplifier simulation model. The 9 MHz sinusoid envelope of RF input is fed to
lst-order, 64-oversampling rate (OSR) delta-sigma modulator.
Fig. 4.9 and Fig. 4.10 show the output waveforms and RF spectrums when the
envelope is a 9 MHz sinusoid and the sampling rate of delta-sigma m odulator is
42
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0 ,8
0 .9
Time [us]
p
0 .7
.
„
,
. 1. . . . { ! . . . . . j j . . . . J I , .. .. , i M l . , , , ,
1
. 1
.
..................... ........
0 .8
| .....
i j m m i .. . . . . .. . . . .. .. . . .
0 .9
Time [us]
E130
“
20
ti-30
1.0
Frequency [GHz]
Figure 4.9: Waveforms and spectrum for full swing sinusoid envelope.
43
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0 .7
0 .8
0 .9
1 .0
Time [us]
0 .8
0 .9
Time [us]
1.0
Frequency [GHz]
Figure 4.10: Waveforms and spectrum for
6
db back-off.
44
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
100
im
90
600
80
E
70
I
60
o
SO
|
•
s
30
500
400
n
O'
300
Drain Effflecieney
200
-+—DC Power
Consumptl
-•—OutputI ..
20
10
100
0
0
0.5
1
Drain Capacitance
1.5
[pFJ
Figure 4.11: Drain efficiency, DC power RF power versus drain capacitance.
640 MHz at the carrier frequency of 1 GHz. Fig. 4.9 is when the envelope signal
has full swing range and Fig. 4.10 is when it is backed-off by
6
dB. For both cases,
intermodulations are lower than -40 dBc and the drain efficiencies are (a) 80.51
% (b) 66.27 % respectively. The drain efficiency of 80.51 % is about 10 % higher
than BDSM in [8 ]. This improvement comes from the reduced switching rate, i.e.
OSR, because the switching loss is proportional to the number of transitions in
the switching FETs [8 ] and it is given by
P loss = -jpDsVr>DfAVG
where
f avg
(4.2)
is the average number of transitions. In addition to OSR reduction,
the number of transition is further reduced because, when the input is low, the
45
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
450
90
■*—Drain Effieciency
DC Pov/er
Consumption
100
10 :— ■- Output Rowe r
50
I
0
0
2
!___ I
4
1- - - 1- - - I--- I
6
I -t
i
0
10
On-Res (stance [Ohm]
Figure 4.12: Drain efficiency, DC power and RF power versus on-resistance
carrier transition is disabled for certain periods which makes the average switching
rate lower than carrier frequency. For the
6
dB backed-off case, the switching loss
is also reduced compared to the full swing case which maintains the decent power
efficiency performance. As mentioned before, class D power amplifier suffers from
the power losses due to the drain capacitance and on-resistance of the transistors.
Fig. 4.11 shows the efficiency dependency on the size of drain capacitance.
As expected, DC power consumption increases as the drain capacitance increases
because more switching power, given in (4.2) is drawn from power supply and
entirely dissipated when it is discharged. However, the output power is constantly
maintained. The efficiency dependency on on-resistance is also estimated in Fig.
4.12. As the on-resistance increase, the drain efficiency decreases. In this case,
46
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.13: Class D Power Amplifier for EDSM.
the output power also decreases and this turns out to be more serious problem
in EDSM scheme. The switching power loss due to the drain capacitance can
be compromised in current mode class D (CMCD) and class E power amplifier.
Further studies such as the effcet of phase mismatch between RF and envelope
signals should be performed.
The prototype of class D power amplifier has been designed using 0.15 fi m
GalnAs pHEM PT process as shown in Fig. 4.13. It consists of one 8 -finger 150 /jm
width microstrip type device and two 4-finger 150 /j,m width coplanar waveguide
47
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
DC Supply
AE
RF Output
►
RF Input
Class E PA
Figure 4.14: Class ED transm itter architecture.
(CPW) type device. This prototype is designed symmetrically using two devices
for M l in Fig. 4.7(a) on the purpose of controlling the amount of currents from
the supply. In other words, it could be used in the study of multi-level delta-sigma
modulation schemes.
4.4.2
Class ED Pow er A m plifier w ith E D SM
A new switching mode power amplifier scheme, class ED is proposed for EDSM
in this section. In this scheme, the charging/discharging problem of class D type
of amplifier discussed in section 4.4.1 is completely removed and the fidelity of
output signal is preserved. The block diagram of class ED transm itter architec­
ture is depicted in Fig. 4.14. It is based on class E amplifier with switching supply.
The DC supply current is controlled by the output of the envelope delta-sigma
modulator.
Fig. 4.15 shows the circuit diagram. The output of delta-sigma modulator
goes to S 2 input and the carrier multiplied by delta-sigma modulator output
goes to Si input. There are two states depending on the output of delta-sigma
48
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VDD
C2
S2
BPF
RF
Short
C1
RL
Figure 4.15: Class ED Power Amplifier for EDSM.
modulator. At H igh state, S2 is on and whole amplifier acts as normal class E
power amplifier. C\ and L are given by the optimal class E equations proposed
by [1 0 ], which is given by
Ci = 0.685
1
(4.3)
U JoRl
L = 0.732—
UJn
(4.4)
At Low state, both Si and S 2 are off. At this state, node A should be driven
by short circuit to properly operate the band pass filter at the output. However,
node A doesn’t need to be DC short. Instead, RF short path is provided by L
49
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
AmpHtonfe mf O u tp u t cm tm t
21 .4
21.6
21.8
22.4
T im e (u s)
Figure 4.16: RF output and DC Current waveforms.
and C 2 by having C 2 such th at
C2 =
2
• Ci
LC? — —
U)r\
(4.5)
(4.6)
Ideally, C 2 is two times larger than C\ according to class E equations in [10] and
could be S 2 transistor parasitic capacitor. Because there is no DC short path
from node A and B , the number of charges at these nodes are preserved and no
discharging occurs during the transitions and at Low state.
A simulations are performed based on this scheme using 5 GHz 802.11a trans­
mit signal. Ideal band pass filter with 20 MHz bandwidth is used for filtering
out the out-of-band noise of delta sigma modulations and ideal switch model is
used for Si and S 2 switches. Class E power amplifier is designed to achieve high
drain efficiency of 98 % with 30 dBm maximum output power. The envelope of
802.11a signal is modulated by delta-sigma modulator with 32 OSR. As seen in
Fig. 4.16, the current from supply follows the magnitude of load current. More-
50
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o_ -80
4-*
O -1 0 0
20
40
-40
30
-20
-10
0
10
20
30
40
Frequency (MHz)
Figure 4.17: O utput spectrum of class ED
over, there are no currents at low states. These two factors make it possible to
m aintain the maximum efficiency of class E PA even when the output power is
backed-off. Fig. 4.17 shows the output power spectrum. 87.7 % of drain efficiency
is achieved at 21 dBm output power level. Around 10 % of efficiency drop still
comes from switching actions of delta-sigma modulations, but not from charging
and discharging.
51
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 5
E fficient M icrow ave P ow er A m p lifier w ith
P u lse d Load M o d u la tio n (P L M ) T echn iq u es
5.1
In tr o d u c tio n
In wireless transm itters, a variety of waveforms over multiple frequency chan­
nels are often needed such as continuous wave, frequency hopping, 16QAM or
CDMA etc. The availability of output power, the linearity and bandwidth of the
power amplifier and the power efficiency of the transm itter under those various
modulation formats are all desired. One well known problem on maintaining
high transm itter efficiency with linear power amplifiers is the efficiency of con­
ventional microwave power amplifiers is discounted when the output power is
backed off because of amplitude fluctuations caused by non-constant envelope
modulations. During the past, a number of transm itter efficiency enhancement
techniques have been proposed to alleviate this problem [5] [38]. Among those
techniques, the most promising one is so-called load modulation techniques. It is
based on the simple fact th at the power efficiency can be restored when the load
impedance is adversely changed according to output power fluctuation. This is
to keep the power amplifier devices always operate in close to saturation mode.
However, to dynamically adjust the load impedance in RF power amplifiers is not
an easy task given the high power conditions and the low loss requirements at the
52
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
amplifier output. The load modulation itself, if not well controlled, can introduce
extra distortions th at affect the linearity. Typical examples of load modulation
techniques include the Doherty amplifier [39] and Chireix’s outphasing ampli­
fier [40] [41]. Both of them use the load pulling phenomenon th at happens when
two transistor outputs are combined to realize load modulations. The controls of
load modulations are through different gate biases on the two transistors in the
Doherty amplifier and through phase modulations in Chireix’s outphasing am­
plifier. However, the potential efficiency improvement due to load modulations
in either configuration is not optimal when the output power fluctuates over a
wide range. In addition, as the controls of the load modulations are enforced
by the transistor characteristics in an analogue fashion, it may create significant
amount of nonlinear distortions in the amplification process. Pre-distortion tech­
niques are usually required in order to maintain the linearity, which increases
the complexity and limits the bandwidth performance of the system. Alternative
approaches to load modulation techniques for efficiency enhancement are drain
modulation techniques such as Kahn techniques or Envelope Elimination and
Restoration (EER) techniques [42] which relies on the drain voltage modulation
to generate non-constant envelopes at the output and to save the DC power con­
sumption. Though it promises optimal efficiency over any power levels for ideal
devices, it requires a linear switching power supply with good efficiency and large
output current. Such switching power regulators are usually with low switching
rates and not available for broad band modulations.
To achieve both optimal load modulation over a broad range of power level
and broadband RF signal amplifications at the same time, a novel pulsed load
modulation (PLM) technique is proposed. The essence is to control the load
modulation characteristics precisely in a digital pulsed fashion. In order not to
compromise the linearity, the original analog signal to be amplified has to be first
53
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Baseband
Processer
Am plitude
Envelope
Modulator
Phase
Power
A m plifier
High Q
Filter
Figure 5.1: Block diagram of the envelope delta-sigma modulation(EDSM) sys­
tem.
discretized into burst of RF pulses using the Envelope Delta-Sigma Modulation
technique (EDSM) [43] [44]. The block diagram of EDSM is shown in Fig. 5.1.
Like in the EER technique or other polar amplifier schemes, the signal is separated
into a RF carrier path and an envelope path. The envelope is discretized into
rectangular pulses by a low pass Delta-Sigma modulator. The envelope pulses
are modulated back to the carrier signal at the amplifier. This forms bursts of
RF voltage pulses at the power amplifier output that are filtered by a low loss
bandpass filter to become a continuous output current. The original RF signal
with the analog envelope is thus restored. Comparing to other pulsed amplifier
schemes like Class K amplifiers with bandpass Delta-Sigma modulations [45], it
reduces the required bandwidth of the power amplifier and relaxes the switching
rate requirement of the Delta-Sigma modulator to below the RF carrier frequency.
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The pulsed envelope signal can be modulated back to the carrier either through
the gate control or switching of the drain supply. The latter approach suffers
the same bandwidth problem of EER techniques as it requires a high speed large
current switching power supply.
It is much easier if the pulse modulation is
realized by simply switching on and off the gate control of the transistors so th at
no power handling capability of the circuitry is compromised. However, the load
matching between the PA under switching and the bandpass filter needs special
consideration and design.
It is previously mentioned that the optimal efficiency performance can be
achieved when the load impedance is inversely proportional to the square root of
the output power. Such load characteristics can be achieved when the amplifier
and the bandpass filter forms so-called switched resonator terminations [46] [47].
This is just like any pulsed RF voltage source connected to a current limiting
bandpass filter. It provides not only the filtered signal at the output but also
the desired load modulation characteristics at the input when the pulse is on.
As a single power transistor does not behave like a voltage source due to its
high output impedance when it is turned off through the gate, a combination
of two transistor devices with a quarter-wave delay line is used to emulate the
output of a voltage source. One is to provide a constant RF voltage output when
the pulse is on and the other is to provide low output impedance like th at in a
voltage source through impedance transform when the pulse is off. This is to
absorb the current flowing out from the filter. It will be shown later th at the
potential efficiency performance with two identical transistors is optimal for up
to
6 dB
back off from the peak output power. The range of optimal efficiency
can be further extended if an asymmetrical combination of two transistors is
used. The linearity performance of the proposed PLM technique is insensitive
to the device non-linearity since the amplification is in pulsed modes and both
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
transistors operates in the voltage saturation most of the time. The pulse rate
needed is usually just a few times higher than the amplified signal bandwidth
and it can be much smaller than the RF carrier frequency. Thus the technique is
feasible for broadband microwave and millimeter wave applications. On the other
hand, a high-Q low-loss microwave filter like a cavity filter has to be used at the
output in order to avoid power loss. Another challenge of the PLM technique is
the drain-gate breakdown voltage requirement of the transistors is higher than
th at in ordinary amplifiers because of the rise of the voltages in transient states
caused by the switching. This challenge may be addressed by the utilization of
wide band gap devices like GaN transistors.
This paper is organized as follows. The operating principle of the PLM tech­
nique is first introduced and the theoretical performance of the power efficiency is
derived. Simulation results with ideal non-linear transistor models are then used
to confirm the theory. Lastly, a PLM amplifier with two discrete GaAs FET
devices and a cavity filter is developed and an efficiency experiment is carried
out to demonstrate the feasibility of the proposed approach.
5.2
P r in c ip le o f O p er a tio n s
The essential concept of the PLM technique is based on the characteristics of
the switched resonator term ination shown in Fig. 5.2. A high-Q bandpass filter in
conjunction with a pulsed voltage source forms a switched resonator [46] [47]. The
voltage source outputs a constant voltage Vmax when the pulse is on. It forces
zero output by short-circuiting to the ground when the pulse is off. The filter
is designed in a way so th at the input impedance emulates th at of a series LC
resonator. This implies an open-circuit like out-of-band reflection at the input
port of the bandpass filter. The other end of the filter is connected to a constant
56
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
High Q
Filter
1
<—
Vmax
-----Vout
lout
-----
Ropt/2
Reff
Figure 5.2: Block diagram of a switched resonator consisting of a pulsed voltage
source and a high-Q bandpass filter.
load resistance given by R opt/2.
R opt is the optimum matching impedance of
the transistor amplifier th at will be discussed later. The bandpass filter should
prevent any sudden change of the RF current flowing through it.
Besides converting a pulsed signal to the original analogue signal through
filtering, the resonator also exhibits different equivalent impedance values during
the energy charging and discharging process before it reaches to the steady state.
For example, a barely charged series L C resonator behaves like open circuit to
the RF signal at its resonant frequency. But it changes to short circuit when
the resonator is almost fully charged. By keeping a certain percentage of energy
charged in the resonator through the alternations of charge and discharge process,
one can realize any particular equivalence resistance value. During the turning
on period, the effective load impedance observed from the input of the filter R ef j
can be related to the duty cycle of the pulses D. Assuming the switching speed
of envelope modulator is much greater than the bandwidth of high Q bandpass
filter, the output current of PA is then approximately proportional to duty cycle
of envelope modulator D and stays constant during the full cycle. As the input
current of a L C filter equals to its output current, the relationship in (5.1) should
57
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The effective load impedance at the ”on” state is thus yielded as
max _ 1 n /o
D
_ Vmax
ef f — T
~ T^-^opt/2
J-out
U
(5 .2 )
The load impedance increases from Ropt/2 to infinity when the duty cycle drops
from 100 % to 0. The output power is given by,
lout^out
2VmaxD / R opt
(5.3)
Comparing 5.2 and 5.3, it is obvious th at the optimal load modulation condition
required by a power amplifier can be obtained as long as the above assumptions
are satisfied.
To take advantage of the switched resonator concept, the RF voltage source
can be formed by either combinations of a RF amplifier and a switch [48] or
two RF amplifiers as presented here. The second configuration provides better
utilization of the device power and is thus considered more practical. It consists
of a pair of FET devices which are connected through quarter-wave impedance
transformers. As shown in Fig.3, This is similar to how a Doherty amplifier is con­
nected. The switched envelope pulses are generated by the envelope modulator.
It controls the gates of both devices by turning them on and off simultaneously.
A high-Q current filter is placed at the output to prevent sharp change of the
current and to restore the original analog envelope. Combining two amplifiers is
58
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
RF
Carrier
High Q
Filter
Main PA
Envelope
Modulator
T3
CO
o
Ropt/2
Aux PA
lout
Figure 5.3: Block diagram of the proposed PLM amplifier.
to form a voltage source at the input of the filter for both linearity and efficiency
purposes. It requires the PA to provide a low voltage level with the maximum
current absorption, e.g., RF short at the input of the filter when the envelope
modulator output is ”0” and a stable RF voltage with the maximum current
output capability when the output is ” 1” . This is to preserve the linearity of
the filtering process required by the assumption of Delta-Sigma modulations. As
the output current is simply a filtered version of the pulsed voltage input, it is
not subjected to the impact of impedance variations due to switching. Another
attribute necessitates the pulsed voltage source equivalence is th at the optimal
load modulation characteristics can be maintained for different power levels from
the previous switched resonator analysis.
The operating principle of the PLM technique using two identical transistors
is explained in details as follows: assuming both devices work in Class B and the
maximum drain voltages and current are Vmax and
For Class B, Vmax = 2Vrjc
where V*. is the drain supply voltage. Imax is chosen to be slightly under the
59
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
maximum current rating of the device. The optimum impedance R ^ is defined
by Vmax/ I max. The definition of the main PA and the auxiliary PA is shown in
Fig.5.3. To form a ’’pulse off’ state, both devices are turned off and both PAs are
open circuit looking from the load. However, at the combiner output, the high
output impedance of the main PA is transformed to a short circuit. Thus the
amplifier pair forces zero voltage at the combiner output by absorbing the current
from the filter into this short-circuit. At the ’’pulse on” state, both devices are
turned on and driven into voltage saturation. The maximum output current is
2Imax because the load impedance is set to Ropt/2. When the transistors are
switched off and on, the filter limits the output current to a value between zero
and
2 / max,
the effective load impedance looking into the filter is higher than
Ropt/2. As the auxiliary PA sees an effective load impedance value higher than
Ropt, it is driven into deeper voltage saturation which forces the voltage at the
combiner output V2 to be Vmax. Therefore, at the combiner output the PA works
like a RF voltage source with pulsed amplitudes between Vmax and 0. In the
’’pulse on” state, the maximum output voltage at the combiner in turn forces the
current output of the main PA to reach to the maximum because of the current
and voltage transfer relations of the quarter wave impedance transformer given
in (5.4).
Vi = jRopJrn-: V2 = j Ropt 11
(5-4)
The auxiliary PA can be thus modeled as a voltage source (Vmax) and from (5.4)
the main PA can be modeled as a current source ( j l max) and they are given by
V2 = Vmax
= jlmax
60
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(b-5)
11
Ropt
Main
►
lout
►
A ux
Vmax V ^ y
Figure 5.4: Equivalent circuit model of power combining in the PLM technique.
Thus the connection of two transistors with a quarter-wave transformer behaves
like a combination of a current source and a voltage source in equal phase and
equal potential depicted in Fig.4. Strictly speaking, the current dividing ratio
between the two branches of equal potential can be arbitrary. However, one can
always drive the main PA slightly harder so th at the main branch has slightly
higher potential at the combiner output, thus the main branch should provide
a portion of the total output current to the maximum degree possible.
The
auxiliary PA should then provide the rest of the current. It is clear th at the
auxiliary PA always operates in voltage saturation mode and exhibits the highest
possible power efficiency. However, the overall power efficiency includes the main
PA has to be discussed separately in two situations at different levels of power
back off. When the power back off level is less than
6
dB, this corresponds to
a duty cycle of 0.5 < D < 1. As I out is greater than Imax, the main PA branch
should provide the maximum possible current of I max and the auxiliary PA should
61
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
provides the remaining current as follows.
I/ti
I-max
h = lout - I m = /max(2D - 1)
(5.6)
The main PA output voltage should also reach to the maximum because of the
impedance transformer,
Pf
j Ropt
Im
jVmax
(5-7)
The output current is given by I\ = j l max according to (5.5). Therefore, the
main PA operates under the optimum match condition with the best efficiency
regardless of power back off. The DC power consumption can be calculated using
7
th at is the ratio between the DC current and the RF current (
7
= ir/2 for
Class B).
Pdc = {Idci + I d c 2 )Vdc = { iD Ii +
7
D I2)VDc
= 27 ImaxVmaxD2
(5.8)
In conjunction with (5.3), the drain efficiency is calculated to be optimal through­
out this range,
,’ = f e = ^ = i = 78Ji*
When the power back off level is more than
6
( 6 ' 9 )
dB, e.g. 0 i D j 0.5, the total
current I out is less than Imax- Thus all the current is provided by the main PA,
62
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
as
max
(5.10)
I2 —0
The output voltage of the main PA is thus given by,
^1
j Ropt Im
j^^maxD
(5,11)
The output current still satisfies A = j l max• The effective load impedance of
the main PA becomes 2D R opt which is smaller than the optimum impedance.
Efficiency drop is thus expected. The DC power consumption is given by
P d c — ( I d c i + I d c 2 ) V d c = {1 D I 1
+ 7 D / 2)Vdc
(5.12)
Since Pout is proportional to D 2, the drain efficiency in this range of duty cycles
is twice th at of the Class B amplifier efficiency with the same amount of power
back-off, as indicated in (5.12).
(5.13)
Fig. 5 summarizes the above equations with the plots of main PA output
voltage, DC currents for both transistors and the efficiency curve versus different
duty cycles of pulses. The maximum drain efficiency is maintained for up to 6 dB
back-off from the peak output power. It is also clearly seen th at the efficiency
enhancement is resulted from the faster DC current drop rate in the auxiliary PA
versus the decrease of the output power level. In fact, the DC current behavior
63
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
cas
>
Idcl
0
20
40
SO
100
Duty Cycle (%}
Figure 5.5: Normalized DC current, drain voltage and efficiency performance of
an ideal PLM amplifier.
can be very helpful in identifying whether the pulsed load modulation technique
operates properly in tests and measurements.
Despite the similarity in the way the transistors are combined, the operating
principle of the PLM amplifier is fundamentally different from th at of traditional
Doherty amplifiers in the following two aspects. First, in Doherty amplifiers, the
main amplifier remains at saturation at a certain range of output power, but the
auxiliary amplifier operates at saturation only for two discrete levels of output
power, which results in efficiency drop in the middle range. In the proposed PLM
scheme, this problem no longer exists as both amplifiers work in saturation mode
64
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1
0.8
’T O G
s*
c
1 OA
iii
0.2
0
-IE
-10
-5
0
Output Back off (dBJ
Figure 5.6: Efficiency curve of the PLM amplifier versus the classical Doherty
Amplifier.
for up to 6 dB output back-off level in the case where identical amplifier devices
are used. In Fig.5.6, the theoretical efficiency performance of the PLM technique
is compared with th at of the classical Doherty amplifier. A flat efficiency curve
until 6 dB back-off should be maintained for the PLM amplifier while the Doherty
amplifier has an efficiency dip to about 90 % of the optimal value.Though the
efficiency difference seems to be minor between these two techniques, the PLM
technique allows for further extension of the optimal efficiency range if asymmet­
rical pairs of devices are used, without incurring a deeper efficiency drop like in
the extended Doherty amplifier [49]. In terms of the linearity, Doherty amplifiers
65
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
intrinsically work in a linear mode which requires more accurate control of the
bias conditions, the gain characteristics and even the peripheral sizes of the de­
vices in order to achieve linear amplification. These requirements are no longer
necessary in the proposed PLM scheme as both transistors are overdriven to the
saturation mode and the linearity is controlled by the duty cycle of the pulse
modulations.
5.3
N o n lin e a r S im u la tio n s
To validate the PLM theory, simulations are performed using equation based
nonlinear transistor model. The equation is given by
I d s = - - S + ^ V<3— ■g m
• tanh
(1 0
• VDS)
(5-14)
Where I^s is the drain-source current, Vgs is the gate-source voltage, Vd8 is drainsource voltage and gm is the transconductance of the transistor.
Hyperbolic
tangent function approximates the knee effect of transistor and no breakdown
effect was assumed. The drain capacitance is assumed to be 10 pF and it is tuned
out with a biasing inductor at the fundamental frequency. For both amplifiers,
the drain bias,
is set to 5 V and Imax is 1 A.
Therefore, the optimum
load is 10 0 and the maximum power is 1.25 W for each amplifier. The RF
frequency is 1.87 G H z and the gate switching rate is 25 M H z. The output filter
is high-Q series LC resonator and its bandwidth is chosen to be 5 M H z. After
performing harmonic balance simulations, Fig.5.7 shows the drain efficiency as
well as the output power versus different duty cycles. Dash lines represent ideal
characteristics of the PLM technique from the theory. The maximum efficiency
simulated is about 74 %. The simulation results agree with the theory very well
66
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
80
2,5
£
:>»
o
c
«3
Ec
CL
2
Q 20
0.5
0
20
40
60
80
100
Duly Cycle [%]
Figure 5.7: Simulated drain efficiency and power curves versus duty cycle.
in general, except a small drop of 3 % or 4 % in efficiency while the amplifier
starts to operate in the pulsed mode. This may be due to the power loss in the
transient switching process.
5 .4
H y b rid Im p le m e n ta tio n s o f P L M a t 1 .8 7 G H z
To further validate the theory and examine the feasibility, an amplifier is built
with a pair of FLL351 GaAs FETs from Fujitsu. The amplifier operates at 1.87
GHz and it is biased in Class B. As shown in Fig. 5.8, RT/duroid is used for
s u b stra te an d th e am plifiers, m icro strip sp litte r/c o m b in e r an d th e cavity filter
are connected with SMA connectors with the insertion loss calibrated. A base
station duplexer for PCS band is used as the output filter and it has about a
67
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 5.8: Implementation of the PLM amplifier using GaAs FETs.
SO
50
i
40
s
M
o
E
LU
JE
m
Q
Class B
20
10
0
0
20
40
m
80
100
Putf Cycle f%|
Figure 5.9: Measured drain efficiency curves versus duty cycle.
68
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
15
0
20
40
oO
100
Duty C y c le (1)
Figure 5.10: Measured output power curve versus duty cycle.
30 MHz bandwidth at the center frequency of 1.87 GHz. The average passband
insertion loss is 0.7 dB. As aforementioned, the stopband performance of the
filter is also im portant beside the passband insertion loss. The stopband return
should be almost completely reflective with relatively flat phase response over a
certain bandwidth depending on the switching frequency. A 25 O T-line is added
in front of filter to calibrate the phase of An and to make it close to zero degree
th a t emulates an open circuit reflection. The amplifier operates under a 5V drain
supply voltage and it outputs a maximum output power of
2
W att. A duty cycle
test is performed to validate the efficiency performance at different power back-off
level. The switching speed is 25 MHz with a duty cycle from 10 % to 100 % and
the rising and falling time is
1
ns.
69
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Measurement results in Fig. 5.9 show similar efficiency behavior as predicted.
The drain efficiency is about 50 % at the full power and 38 % at
6
including the cavity filter insertion loss. This is compared to 25 % at
dB back-off
6
dB back­
off for the Class B case. Measured output power versus duty cycle is depicted
in Fig. 5.10. O utput power should be proportional to the square of the duty
cycle to assure linearity. Deviation in the linearity curve is believed to be mainly
related to ’’soft breakdown” phenomenon of the FET device, as similar behavior
has been observed in simulations with non-linear transistor models including the
breakdown effect. This nessitates a high break down design in the power amplifier.
5.5
M M IC Im p le m e n ta tio n s o f P L M at 17 G H z
The bulky quaterwave transmission lines in PLM scheme prevents monolithic
implementations at low frequency applications. Also, to achieve the high linear­
ity and the low loss, the requirements for output bandpass filter are stringent.
As seen in previous section, the sizes of output filters such as cavity filters and
combline filters are not acceptable for mobile applications. Therefore, at low
frequency applications, PLM architecture is suitable for high performance basestation applications, where the size is not a concern. However, at high frequency,
every feature size shrinks according to the wavelengthes including the length of
quaterwave transmission lines and the size of filters. Another benefit of using high
frequency is the possibility of transm itting and receiving high rate data because
the wide bandwidth can be utilized in high frequencies. In this section, microwave
monolithic integrated circuit (MMIC) is built for PLM scheme at 17 GHz.
0.15 /im GalnAs pHEMT technology from Winsemiconductor is used for
MMIC implementations. Fig. 5.11 shows drain efficiency, output power and gain
70
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
30
70
60
50
-10
O
0
0
5
10
Pin [dBm]
15
20
Figure 5.11: O utput power, gain and drain efficiency curves versus input power
at 17 GHz.
versus input power for 8 -finger, 100 n m pHEMT device1 at 17 GHz. The gate
bias is at device pinch-off voltage, -1.5 V and the supply voltage is 4 V. The
parasitic capacitance at drain is tuned out with the short stub which is also used
for drain biasing. This individual power amplifier is design to be matched to 25
Q such th at the main and aux amplifier together see 50 O load. At the operating
input power level, 17 dBm input, it generates 23.8 dBm output power and the
drain efficiency is 56.7 %. Since the gain at 17 GHz is relatively low, the pream­
plifier is designed with 4-finger, 100 fim device. The overall layout of PLM at
17 GHz is depicted in Fig. 5.12. The size of chips are
6
mm2.
Equivalently, 0.8 mm of gate width
71
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Igim&m
;*§fj
"Wm
Figure 5.12: 17 GHz PLM power amplifier (a) 2 mm by 3 mm (b) 3 mm by 2 mm
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
70
60
RLM
50
40
Ideal
30
20
10
0
20
0
40
60
80
100
Duty Cycle [%]
(a)
0.45
0.4
0.35
0.3
§*
PLM
0.25
3
O
Q.
0.2
0.15
Tdeaf
0.1
0.05
0
20
40
60
80
100
D uty C ycle [%]
(b)
Figure 5.13: Efficiency and output power curves for duty cycle with 200 MHz
envelope switching (a) efficiency (b) output power
73
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Simulations show th a t envelope switching rate of 200 MHz is feasible and the
efficiency and the output power versus duty cycle is shown in Fig. 5.13.
74
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 6
E fficient P ow er C om b in er D esig n M e th o d s
6.1
In tr o d u c tio n
In high efficiency power amplifier design, the power combiner is extremely
im portant because it is the last stage of power amplifier and it could corrupt the
overall power efficiency. There are a number of techniques in power combining
suitable for either hybrid or MMIC implementations, which include Wilkinson
combiners, bus-bar combiners, Lange couplers, traveling wave combiners and
Dolph-Chebychev tapered line combiners [52]. Power combiner can be evaluated
through such parameters as the size, loss, frequency bandwidth, stability and bias
compatibility [52], Sometimes, the size of combiner is too big to be implemented
in MMIC at low frequency if the transmission lines proportional to wavelength
have to be used. Also, the big size causes the significant signal loss and reduces
the bandwidth of signal since the signal has to travel a longer distance. If the
signal loss is not well taken care of, overall efficiency of power amplifier suffers
significantly. Therefore, main concern for power combiner design are minimizing
the size as well as the loss. Another concern is the biasing. Again, a big biasing
circuitry will cause the loss, thus directly affects the efficiency. In addition to
that, the biasing scheme can disturb the main combining circuitry such th at the
significant loss can happen due to mismatches. Therefore, the combining scheme
with inherent basing capability would be desirable. In other words, a compact
75
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Bais Feed
PA
PA
PA
PA
Bais Feed
Figure 6.1: Tree structure with bus-bar
power combiner scheme with easy biasing circuitry would be the best choice for
efficient power amplifier designs.
6.2
T ree S tr u c tu r e C o m b in in g
Most of today’s MMIC power amplifier design take tree structure combing and
the biasing is implemented using either bus-bar or quaterwave transmission line as
depicted in Fig. 6.1 and Fig. 6.2. Bus-bar in Fig. 6.1 provides the easy high current
biasing to all the devices and results in the compact design. However, it requires
2D or 3D EM simulations and the shunt inductance matching is needed on the
ends of the bus-bar, which could be lossy [53]. Although biasing using quaterwave
76
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Bais Feed
PA
PA
PA
PA
Bais Feed
Figure 6.2: Tree structure with quaterwave transmission line
transmission line in Fig. 6.2 requires more space than bus-bar biasing, the stability
is usually better due to the odd-mode cancelation at the resisters between power
amplifier outputs. Considering the length of the quaterwave transmission line
and the size of tree structure, the disadvantage due to the size is minimal.
The tree structure has to achieves both power combining and impedance trans­
formation since power amplifier output impedance is quite lower than the load
impedance, 50 Q. Fig. 6.3 shows the equivalent circuits of tree structure. It con­
sists of series inductors and shunt capacitors. Series inductors are implemented by
the transmission lines and shunt capacitors are implemented by lumped capacitors
in MMIC design. The circuit parameters such as L and C can be optimized as fol­
lows. Since each power amplifier always wants to see optimum load impedance,
77
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
R*opt
-
tv y - w
L
I
_rY"YW
L
R*opt
I
YYYYV
L
I
50 n
R*.opt
-rY Y W .
L
I
R*,opt
r m
I
\
L
I
Figure 6.3: Equivalent circuit of the tree structure.
Ropt, the conjugate of R opt, R lpt should be transformed to 50 Q as shown in
Fig. 6.3. The conjugate of the optimum power amplifier load impedance, R*pt
is usually capacitive and low impedance, since the parasitic drain capacitance of
power amplifier is tuned out with inductive loads. In the designing of tree struc­
ture, staring from R*opt, first, the impedance is transformed to A, B in Fig. 6.4
using inductors or transmission lines and capacitors. If it reaches the real axis
of Smith chart, combining two branch results in half the real impedance. This
process continues until the final impedance becomes 50 il. This Smith chart ap­
proach really helps in designing compact combiner which will be discussed in the
78
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 6.4: Impedance Transformation.
next sections.
6.3
A r e a E fficien t P o w er C o m b in er
As seen in the previous section, the tree structure requires shunt capacitances
for impedance transformation. In MMIC design, usually, metal-insulator-metal
(MIM) capacitors are used for this purpose. However, MIM capacitors are lossy
and process variant such th at MIM capacitors are not suitable for the tuning at
RF frequencies. Some foundry provides the well controlled shunt capacitors by
m o u n tin g M IM cap acito rs on th e back via. However, th is ap p ro ach is process
specific and is not widely used.
On the other hand, as seen in Fig. 6.1 and
Fig. 6.2, a lot of estate is not used for any reason in the tree structure. There
79
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
are big gaps between the branches of tree structures depending on the length of
the power devices. Therefore, it would be reasonable approach to utilize these
unoccupied estate somehow as capacitors. The essential idea is to replace the
MIM capacitors as metal-substrate-ground (MSG) capacitances by filling out the
unoccupied area as metals. The loss will be minimized since the GaAs substrate
is a much better dielectric than the nitride used in MIM capacitor in terms of
the loss. Even though dielectric constant is smaller than nitride, because the
amount of unoccupied area is huge, the reasonable size can be achieved. The
coupling between the MSG capacitors and the transmission lines would cause the
design issues. However, ever increasing computing power and the advance EM
simulators such as IE3D makes this approach feasible for efficient and compact
power combiner designs. W ith aid of EM simulator and Smith chart approach
discussed in the previous sections, power divider and combiner is designed and
simulated at 34 GHz as depicted in Fig. 6.5. The length of combiner is 0.3 mm
by 1.4 mm which is very compact comparing to conventional schemes.
6.4
3 4 G H z p o w er a m p lifier w ith efficien t c o m b in in g
The prototype for 34 GHz power amplifier using the combining design scheme
discussed in the previous section has been designed and in fabrication. 0.15 n m
GalnAs pHEM PT technology is used and 2 mil substrate is used for MSG capac­
itors. Fig.
6 .6
shows efficiency and power and gain of design power amplifier. It
has about 36 dBm peak power and 46.259 % of drain efficiency. The performance
of 34 GHz power amplifier is summarized in Table 6.1 and the layout is depicted
in Fig. 6.7. The size is 2 mm by 2 mm. To the author’s knowledge, this power
amplifier has the smallest size and highest efficiency at this frequency and this
power level.
80
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 6.5: EM simulations for power divider and combiner.
81
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Drain Effciencv T%1 and PAE
- 30
Pout
-
20
20
-
Drain Eff
Gain
- 10
0
Pin [dBm]
Figure 6 .6 : Efficency, power, gain of 34 GHz power amplifier.
Table 6.1: The performance of 34 GHz power amplifier.
Frequency
Pout - 1dB
PAE
[GHz]
[dBm]
34
36.11
Gain
Max S\i
[%]
V
[%]
[dB]
[dB]
44.00
46.26
13.95
-12.61
82
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Pout [dBm] and Gain [dB]
40 -
Figure 6.7: Layout of 2 W 34 GHz power ampflier.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 7
C o n clu sio n s
Among the wireless transceiver design components, the transm itter, especially
the power amplifier, has been drawing tremendous attentions from either academy
or industry since it is one of the most power exhaustive block and it has to be
improved to realize true ubiquitous environments. Many techniques have been
proposed at different design levels. However, there has been no winning scheme.
Starting with investigating the conventional power amplification techniques, this
dissertation has proposed several schemes for high efficient high linear power
amplification of non-constant envelope signals from architecture levels to circuit
levels. The main paradigm of this thesis is the linear analog amplification in
digital fashion. These concepts are yet to be widely accepted from either academy
or industry. However, it is believed th at they have huge potential therefore more
works should be followed. It could not be better if the contents of this dissertation
could contribute to the tiny portion of technological advances in this directions.
84
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
R
eferences
[1 ] ”2006 Telecommunications Market Review and Forecast” , TIA
[2] ’’Mobile WiMAX - P art I: A Technical Overview and Performance Evalua­
tion”, W iM A X Forum, August, 2006
[3] ’’Mobile WiMAX - P art II: A Comparative Analysis” , W iM A X Forum, May,
2006
[4] B. Krenik, ’’Making Wireless” , IM S workshop presentation, 2004
[5] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N. Pothecary, J. F. Sevic and N. O. Sokal, ’’Power amplifiers and transm itters for RF
and microwave,” IEE E Transactions on Microwave and Techniques, vol. 50,
no. 3, pp. 814-26, March 2002.
[6 ] H. Kobayashi, J. M. Hinrichs, and P. Asbeck, ’’Current mode class-D power
ampfliers for high efficiency RF applications,” IEEE Transactions on M i­
crowave and Techniques, vol. 49, pp. 2480-2485, Dec. 2001.
[7] A. Grebennikov, ” Switched-mode tuned high-efficiency power amplifiers: his­
torical aspect and future prospect”, IEE E Raio Frequency Integrated Circuits
Symposium”, 2002.
[8 ] T. Sowlati, C. Andre, T. Salama, J. Sitch, G. Rabjohn, D. Smith, ’’Low
voltage, high efficiency GaAs class E power amplifiers for wilress transm itters” ,
IEEE Journal of Solid-State Circuits, Vol. 30, No. 10, pp. 1074-1080, Oct. 1995.
[9] H. Jager, A. Grebennikov, E. Heaney, and R. Weigel, ’’Broadband highefficiency monolothic InG aP/G aA s HBT power amplifiers for 3G handset ap­
plications” , IEEE M T T -S Digest, pp. 1035-1038, 2002.
[10] A. Grebennikov, and H. Jager, ’’Class E with parallel circuit - a new challenge
for high-efficiency RF and microwave power amplifiers”, IEE E M T T -S Digest,
pp. 1627-1630, 2002.
[11] T. B. Mader, Z. B. Popovic, ’’The transmission-line high-efficiency classE amplifier,” IEEE Microwave and Guided Wave Letters, vol. 5, no. 9, pp.
290-292, Sep. 1995.
[12] R. Negra, W. Bachtold, ” Lumped-element load-network design for class-E
power amplifiers,” IEEE Transaction on Microwave and Techniques, vol. 54,
No. 6 , pp. 2684-2690, June 2006.
85
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[13] T. Quach, et. al, ” Ultrahigh-efficiency power amplifier for space radar appli­
cations,” IEEE Journal of Solid-State Circuits, vol. 37, no. 9, pp. 1126-1134,
Sep. 2 0 0 2 .
[14] F. H. Raab, ” Class F power amplifiers with maximally flat waveforms,” IEEE
Transactions on Microwave and Techniques, vol. 45, pp. 2007-2012, Nov. 1997.
[15] E. McCune and W. Sander, ’’EDGE Transmitter Alternative using Non­
linear polar modulation,” in Proc. Int. Symp. Circuits Systm.es., vol. Ill, pp.
594-597, May 2003.
[16] D. Sue and W. McFarland, ”An IC for Linearizing RF Power Amplifiers
Using Envelope Elimination and Restoration,” IEEE J. Solid-State Circuits,
vol. 33, pp. 2252-2258, Dec. 1998.
[17] W. Sander, S. Schell and B. Sander,” Polar Modulator for Multi-mode Cell
Phones.” Proc. C1CC, pp. 439-445, Sept. 2003.
[18] T. Sowlati, Y. Greshishchev and C. A. T. Salama, ’’Phase Correcting Feed­
back System for Class E Power Amplifier,” IEE E J. Solid-State Circuits, vol.
31, pp. 544-550, Apr. 1997.
[19] T. Sowlati, D. Rozenblit, R. Pullela, M. Damgaard, E. McCarthy, D. Koh, D.
Ripley and F. Balteanu, ”Quad-Band G SM /G PRS/ED G E Polar Loop Trans­
m itter,” IEEE J. Solid-State Circuits, vol. 39, pp. 2179-2189, Dec. 2004.
[20] L. R. Kahn, ’’Single sideband transmission by envelope elimination and
restoration,” Proc. IRE, vol. 40, no. 7, pp. 803-806, July 1952.
[21] F. H. Raab and D. J. Rupp, ’’High-efficiency single-sideband H F/V H F trans­
m itter based upon envelope elimination and restoration,” Pro. Sixth Int. Conf.
HF Radio Systems and Techniquies (HF ’94) (IEE CP 392), York, UK, pp.
21-25, July 4-7, 1994.
[22] F. H. Raab, ” Intermodulation distortion in Kahn-technique transm itters,”
IEEE Trans. Microwave Theory and Techniquies, vol. 44, no. 12, part 1, pp.
2273-2278, Dec. 1996.
[23] F. H. Raab, ’’Drive modulation in Kahn-technique transm itters,” Int. M i­
crowave Symp. Digest, vol. 2 , pp.811-814, Anaheim, CA, June 1999.
[24] M. D. Weiss, F. H. Raab, and Z. B. Popovic, ’’Linearity characteristics of Xband power amplifiers in high-efficiency transm itters,” IEEE Trans. Microwave
Theory and Tech., vol. 47, no. 6 , pp. 1174-1179, June 2001.
86
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[25] W. H. Doherty, ” A new high efficiency power amplifier for modulated waves,”
Pro. IRE, vol. 24, no. 9, pp. 1163-1182, Sept. 1936.
[26] D. M. Upton and P. R. Maloney, ”A new circuit topology to realize high
efficiency, high linearity, and high pwer microwave amplifiers,” Proc. Radio
and Wireless Conf. (RAWCON), Colorado Springs, pp. 317-320, Aug. 9-12,
1998.
[27] J. Schuss et al, ’’Linear amplifier for high efficiency multi-carrier perfor­
mance,” U.S. Patent 5,568,086, Oct. 1996.
[281 J. Long, ’’Apparatus and method for amplifying a signal,” U.S. Patent
5,886,575, March 1999.
[29] B. E. Sigmon, ’’Multistage high efficiency amplifier,” U.S. Patent 5,786,938,
July 28, 1998.
[30] H. Chireix, ’’High power outphasing modulation,” Proc. IRE, vol. 23, no.
11, pp. 1370-1392, Nov. 1935.
[31] D. C. Cox and R. P. Leek, ”A VHF implementation of a LINC amplifier,”
IEEE Trans. Commun., vol. COM-24, no. 9, pp. 1018-1022, Sept. 1976.
[32] R. Langridge, T. Thornton, P. M. Asbeck, and L. E. Larson, ” A power re-use
technique for improving efficiency of outphasing microwave power amplifiers,”
IEEE Trans. Microwave Theory Tech., vol. 47, no. 8 , pp. 1467-1470, Aug. 1999.
[33] B. Stengel and W. R. Eisenstat, ”LINC power amplifier combiner efficiency
optimazation,” IEEE Trans. Veh. Technol., vol. 49, no. 1, pp. 229-234, Jan.
2000 .
[34] C. P. Conradi, R. H. Johnston, and J. G. McRory, ’’Evaluation of a lossless
combiner in a LINC transm itter,” Proc. 1999 IEEE Canadian Conf. Elec. and
Comp. Engr., Edmonton, Alberta, Cananda, pp. 105-109, May 1999.
[35] C. Y. Hang, Y. E. Wang, and T. Itoh, ”A new amplifier power combin­
ing scheme with optimum efficiency under variable outputs,” IEE E M T T -S
International Microwave Symposium, 2002.
[36] Y. Chung, J. Jeong, Y. E. Wang and T. Itoh, ’’Power Level-Dependent DualOperating Mode LDMOS Power Amplifier for CDMA Wireless Base-Station
Applications,” IEEE Transaction on Microwave Theory and Techniques, vol.
53, pp. 739- 46, Feb. 2005.
87
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[37] S. Yanagawa, H. Ishihara, and M. Ohtomo, ” Analytical method for deter­
mining equivalent circuit parameters of GaAs F E T ’s,” IEEE Transactions on
Microwave and Techniques, vol. 44, no. 10, pp. 1637-1641, 1996.
[38] S. C. Cripps, RF Power Amplifiers for Wireless Communications. Norwood,
MA: Artech House, 1999.
[39] F. H. Raab, ’’Efficiency of Doherty RF power-amplifier systems,” IEEE
Trans. Broadcasting, vol. BC-33, no. 3, pp. 77-83, Sep. 1987.
[40] F. H. Raab, ” Efficiency of outphasing RF power amplifier systems,” IEEE
Transactions on Communications, Vol. COM-33, No. 10, Oct. 1985.
[41] A. Birafane and A. B. Kouki, ”On the linearity and efficiency of outphasing
microwave amplifiers” , IEEE Transactions on Microwave Theory and Tech­
niques, Vol.52, No. 7, July 2004.
[42] F. H. Raab, B. E. Sigmon and R. G. Myers, ”L-Band transm itter using Kahn
EER technique,” IIE EE Transactions on Microwave Theory and Techniques,
Vol.46, No. 12, Dec. 1998.
[43] Y. Wang, ” A Class-S RF Amplifier Architecture with Envelope Delta-Sigma
Modulation,” IEEE RAW C O N Digest, 2002.
[44] Y. Wang, ”An Improved Kahn Transmitter Architecture Based on DeltaSigma Modulation,” 2003 IEE E M T T -S Int. Microwave Symp. Dig., pp. 13271330, June 2003.
[45] A. Jayaraman, P. F. Chen, G. Hanington, L. Larson, and P. Asbeck, ’’Lin­
ear High-efficiency Microwave Power Amplifiers Using Bandpass Delta-sigma
Modulators,” IEEE Microwave Guided Wave Letter., vol. 8 , no. 3, pp. 121-123,
March 1998.
[46] S. Kim, X. Xu, and Y. E. Wang, ’’Power Efficient RF Pulse Compression
through Switched Resonators,” 2005 IEEE International Microwave Sympo­
sium Digest, Session WEPG-7, June, 2005.
[47] S. Kim and Y. E. Wang, ’’Theory of Switched RF Resonators,” IEE E Trans­
actions on Circuits and Systems I, accepted.
[48] J. Jeong and Y. E. Wang, ” A Switching Mode Power Amplifier for Envelope
Delta-Sigma Modulation (EDSM),” 2006 IEEE Topical Workshop on Power
Amplifiers fo r Wireless Communications, San Diego, Jan. 16, 2006.
88
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[49] M. Iwamoto, A. Williams, P. Chen, A. Metzger, C. Wang, L. E. Larson and
P. M. Asbeck, ”An Extended Doherty Amplifier with High Efficiency over a
Wide Power Range,” 2001 IEEE M T T -S Int. Microwave Symp. Dig., vol 2,
pp. 931-934, May 2004.
[50] T. Johnson, S. Stapleton, ’’Available Load Power in a RF Class D Amplifier
with a Sigma-Delta Modulator Driver,” IEEE RA W CO N Digest, 2004.
[51] U. Beis ”An introduction to delta sigma convertes,” tutorial on the web.
[52] S. P. Marsh,” MMIC power splitting and combining techniques,” IE E Tuto­
rial Colloquium on Design of R F IC ’s and M M IC ’s, pp. 6/1-6/7, Nov. 1997.
[53] S. P. Marsh, D. K. Y. Lau, R. Sloan, and L. E. Davis, ’’Design and analysis
of an X-band MMIC ’Bus-Bar’ power combiner” , Symp. on High Performance
Electron Devices fo r Microwave and Optoelectronic Applications, pp. 164-169,
Nov. 1999.
89
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Документ
Категория
Без категории
Просмотров
0
Размер файла
2 685 Кб
Теги
sdewsdweddes
1/--страниц
Пожаловаться на содержимое документа