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Fully integrated silicon germanium microwave phased-array receivers for satellite communications

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FULLY INTEGRATED SIGE MICROWAVE PHASED-ARRAY RECEIVERS
FOR SATELLITE COMMUNICATIONS
By
YU YOU
A dissertation submitted in partial fulfillment of
the requirements for the degree of
Doctor of Philosophy
WASHINGTON STATE UNIVERSITY
School of Electrical Engineering and Computer Science
DECEMBER 2013
UMI Number: 3611320
All rights reserved
INFORMATION TO ALL USERS
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a note will indicate the deletion.
UMI 3611320
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To the Faculty of Washington State University:
The members of the Committee appointed to examine the dissertation of Yu You
find it satisfactory and recommend that it be accepted.
___________________________________
Deukhyoun Heo, Ph.D., Chair
___________________________________
Partha Pratim Pande, Ph.D.
___________________________________
Benjamin Belzer, Ph.D.
ii
ACKNOWLEDGMENT
This dissertation would not be possible without the help from many people. First and
foremost, I would like to thank my advisor Professor Deukhyoun Heo for his guidance and
constant support during my doctoral studies at Washington State University. I also would like to
thank all the ARMAG (Advanced RF and Mixed-Signal Application Group) colleagues, Peng
Liu, Jaeyoung Jung, Siqi Zhu, Huan Peng, Xinmin Yu, Suman Sah, Nghia Tang, Pawan Agarwal
and etc. for their support and collaborations.
I am also grateful to my committee members, Professor Partha Pratim Pande and Professor
Benjamin Belzer, for their time and interest, and valuable comments.
The research work presented in this dissertation is sponsored by Linear Signal, LLC. Their
support for my works is greatly appreciated.
Finally, I would like to thank my wife, Linna Luo, my parents, and parents-in-law, for all
their love and support.
iii
FULLY INTEGRATED SIGE MICROWAVE PHASED-ARRAY RECEIVERS
FOR SATELLITE COMMUNICATIONS
ABSTRACT
by Yu You, Ph.D.
Washington State University
December 2013
Chair: Deukhyoun Heo
This dissertation is dedicated to presenting various designs and analysis for RF phase shifting
architectures to implement microwave phased-arrays receivers in commercial SiGe process.
Three design examples in X-band, L/S/C/X band, and K-band, are demonstrated.
An X-band 8-channel SiGe PIN diode phased-array receiver for 9.5-11.5 GHz applications
has been proposed and fabricated in a commercial 0.18-µm SiGe BiCMOS process. The receiver
consists of low noise amplifiers (LNA), 3-bit variable gain amplifiers (VGA), 3-bit passive phase
shifters and 4:1 active combiners. High performance PIN diode switches used in phase shifters
ensure low phase error. The bridged-T type phase shifter with center-tap inductor is analyzed
using an equivalent-circuit model to obtain analytical form of component values. The receiver
achieves over 10 dB measured average gain, less than 5 dB NF (@max. gain and ref. phase state)
per channel. The RMS gain error is less than 0.67 dB and the RMS phase error is less than 5°
with VGA control at 9.5-11.5 GHz for all phase states.
For the second implementation, an ultra-wide band 8-channel L/S/C/X band phased-array
receiver is presented, which includes LNAs, 4-bit VGA, and 4-bit active phase shifters. Shunt
feedback LNAs are adopted in order to achieve wideband amplification. Differential structures
are used for VGAs and phase shifters to reduce ground parasitics. In order to achieve wide band
iv
operation, vector modulator is adopted for the phase shifter compared with passive one. The
receiver achieves 10.2 GHz 3 dB bandwidth, which is from 1.1 GHz to 11.3 GHz, one decade
frequency bandwidth.
The final implementation is a 4-channel K-band phased-array receiver using deep silicon via
(DSV) technology to reduce ground parasitic. A new phase shifter structure by using floating
body technique to reduce insertion loss, and using parasitic resonant frequency elimination
technique to increase bandwidth is proposed. Simulated results show less than 4.1° RMS phase
error and less than 1.3 dB RMS gain error is achieved over 30% fractional bandwidth. The one
channel can achieve 18.2 dB gain, 2.82 dB NF, and -8.5 dBm output P1dB at 20 GHz with 45
mW power consumption.
v
TABLE OF CONTENTS
ACKNOWLEDGMENT.......................................................................................................... iii
ABSTRACT ............................................................................................................................. iv
LIST OF TABLES ................................................................................................................... ix
LIST OF FIGURES .................................................................................................................. x
PUBLICATIONS ................................................................................................................... xiv
1
INTRODUCTION............................................................................................................ 1
1.1 Phased-Array System ................................................................................................... 1
1.2 Phased-array Architecture ............................................................................................ 3
1.3 Thesis Objective ........................................................................................................... 5
1.4 Thesis Organization ...................................................................................................... 6
2
X-BAND PHASED-ARRAY RECEIVER ...................................................................... 8
2.1 System Architecture ..................................................................................................... 9
2.2 Building Block Design ............................................................................................... 10
2.2.1
X-band LNA ........................................................................................................ 10
2.2.2
X-band VGA ....................................................................................................... 12
2.2.3
X-band Pin-diode Based Phase Shifter ............................................................... 14
2.2.4
X-band Active Combiner .................................................................................... 18
2.3 Measurement .............................................................................................................. 19
2.3.1
On-wafer Measurement ....................................................................................... 19
vi
2.3.2
Packaged Chip Board Measurement ................................................................... 27
2.4 Summary..................................................................................................................... 31
3
L/S/C/X BAND PHASED-ARRAY RECEIVER ......................................................... 32
3.1 System Architecture ................................................................................................... 32
3.2 Building Block Design ............................................................................................... 33
3.2.1
Wideband LNA Design ....................................................................................... 33
3.2.2
Wideband Differential VGA ............................................................................... 36
3.2.3
Wideband Active Phase Shifter........................................................................... 40
3.3 Simulation Results ...................................................................................................... 43
3.3.1
Simulation Results of Building Blocks ............................................................... 44
3.3.2
Simulation Results of System ............................................................................. 47
3.4 Summary..................................................................................................................... 50
4
K-BAND PHASED-ARRAY RECEIVER .................................................................... 51
4.1 System Architecture ................................................................................................... 51
4.2 Building Block Design ............................................................................................... 52
4.2.1
K-band LNA ........................................................................................................ 52
4.2.2
K-band VGA ....................................................................................................... 53
4.2.3
K-band Low Insertion Loss and wideband Phase Shifter ................................... 54
4.3 Simulation Results ...................................................................................................... 59
4.3.1
Simulation Results of Building Blocks ............................................................... 59
vii
4.3.2
Simulation Results of System ............................................................................. 63
4.4 Summary..................................................................................................................... 66
5
CONCLUSION .............................................................................................................. 67
6
BIBLIOGRAPHY .......................................................................................................... 69
viii
LIST OF TABLES
Table 2-1 Inductance and capacitance values for 45° and 90° in X-band phase shifter ............. 18
Table 2-2 Performance Comparison of X-band multi-channel phased-array receivers.............. 26
Table 3-1 Width Ratio of Cascode Stage in wideband VGA ..................................................... 38
Table 3-2 L/S/C/X band phase shifter control table ................................................................... 43
ix
LIST OF FIGURES
Figure 1-1 Phase Array antenna systems: (a) An SPS-48E radar antenna (the large square panel)
[4], mechanically steered, and (b) Alaska District’s 90-foot diameter phased-array radar for
missile warning and space surveillance [5], electrically steered. ............................................ 1
Figure 1-2
n-channel phased-array receiver .............................................................................. 2
Figure 1-3 Phased-array application in civilian sector [6] [7] ........................................................ 3
Figure 1-4
Phased-array receiver architectures: (a) RF phase shifting, (b) IF phase shifting, (c)
LO phase shifting..................................................................................................................... 4
Figure 2-1
Block diagram of the eight-channel X-band phased-array receiver ....................... 10
Figure 2-2
Circuit diagram of X-band LNA ............................................................................. 12
Figure 2-3
Circuit diagram of X-band VGA ............................................................................ 13
Figure 2-4
(a) Octagonal PIN diode layout, (b) equivalent of center-tap inductor, (c) circuit
diagrams of X-band phase shifter, and (d) equivalent circuit for 45° and 90° bit ................. 16
Figure 2-5
Circuit diagram of X-band combiner ...................................................................... 18
Figure 2-6
Chip microphotograph of the 8-channel phased-array receiver (2.4 × 4.8 mm2)... 19
Figure 2-7
Measured input, output return loss and reverse insolation for 8 phase states ......... 20
Figure 2-8
Measured VGA gain control and phase response at 10.5 GHz............................... 20
Figure 2-9
Measured single channel (channel 1) characteristics for all 3-bit phase states
(@max VGA gain): (a) gain and RMS gain error; (b) 3-bit insertion phase response and
RMS phase error. ................................................................................................................... 22
Figure 2-10 Measured NF for channel 1 (@max VGA gain and ref. phase state) ..................... 22
Figure 2-11
Measured input P1dB (@max and min VGA gain) ............................................... 23
x
Figure 2-12 (a) phase states of four channels (@max VGA gain); (b) Measured RMS phase
mismatches compared with channel-1 for all phase states .................................................... 24
Figure 2-13 Measured RMS gain mismatches of four channels................................................. 25
Figure 2-14 Measured RMS gain and phase errors of channel-1 due to coupling when changing
gain or phase states of channel-2 ........................................................................................... 25
Figure 2-15 Board measurement set up for X-band phased-array receiver ................................ 28
Figure 2-16 Board measured channel 1 performance with 8 gain states .................................... 28
Figure 2-17 Board measured channel 1 performance with 8 phase states .................................. 29
Figure 2-18 Ground parasitics for flip chip package .................................................................. 30
Figure 2-19 Simulated gain (dotted red line) including ground parasitics of flip chip package
compared with measured results (solid line, S51-channel 1, S54-channel 4) ....................... 30
Figure 3-1 L/S/C/X band phased-array receiver ......................................................................... 32
Figure 3-2 Gain and power distribution for L/S/C/X receiver ..................................................... 33
Figure 3-3 Schematic of LNA in L/S/C/X band phased-array receiver ...................................... 35
Figure 3-4 Schematic of wideband VGA in L/S/C/X band phased-array receiver ...................... 37
Figure 3-5 Half of inter-stage circuit in wideband differential VGA........................................... 38
Figure 3-6 Equivalent inter-stage circuit of wideband VGA ....................................................... 39
Figure 3-7 Schematic of wideband QAF ...................................................................................... 41
Figure 3-8 Schematic of wideband differential adder .................................................................. 41
Figure 3-9 Push-pull differential-to-single-ended converter in active phase shifter .................... 42
Figure 3-10 Wideband LNA simulation results: gain, return loss and NF ................................. 44
Figure 3-11 Wideband LNA simulation results: input P1dB ..................................................... 45
Figure 3-12 Wideband differential VGA simulation results: gain ............................................. 45
xi
Figure 3-13 Wideband differential VGA simulation results: gain range and phase variation over
gain states .............................................................................................................................. 46
Figure 3-14 Wideband VGA simulation results: linearity.......................................................... 46
Figure 3-15 Layout of L/S/C/X phased-array receiver ............................................................... 47
Figure 3-16 Simulated four channels’ gain ................................................................................ 48
Figure 3-17 Simulated four channels’ phase response ............................................................... 48
Figure 3-18 Simulated gain control range and phase variation over gain states ........................ 49
Figure 3-19 Simulated gain variation over phase stages and all 16 phase states ....................... 49
Figure 4-1 DSV in SBC18 H3D process [37] .............................................................................. 51
Figure 4-2 Schematic of K-band LNA ......................................................................................... 52
Figure 4-3 Schematic of K-band VGA......................................................................................... 54
Figure 4-4 Schematic of NMOS switch ....................................................................................... 55
Figure 4-5 Conventional switched LC phase shifter and its simplified small-signal circuit model
of ON and OFF states ............................................................................................................ 56
Figure 4-6 Proposed switched LC phase shifter and its simplified small-signal circuit model of
ON and OFF states ................................................................................................................ 58
Figure 4-7 Schematic of K-band 4-bit phase shifter .................................................................... 58
Figure 4-8 K-band LNA simulation results: gain, return loss and NF ......................................... 59
Figure 4-9 K-band LNA simulation results: stability for corner and temperature ....................... 60
Figure 4-10 K-band VGA simulation results: gain range and phase variation over gain states . 60
Figure 4-11 K-band VGA simulation results: input and output return loss ............................... 61
Figure 4-12 K-band VGA simulation results: Input P1dB ......................................................... 61
xii
Figure 4-13 K-band phase shifter simulation results: Input, output return loss, phase response and
gain ........................................................................................................................................ 62
Figure 4-14 Simulated RMS gain and phase error of K-band phase shifter ............................... 63
Figure 4-15 Layout of K-band phased-array receiver ................................................................ 64
Figure 4-16 Simulated one channel gain states and phase variation .......................................... 64
Figure 4-17 Simulated phase states and gain variation .............................................................. 65
Figure 4-18 Simulated gain and phase imbalance ...................................................................... 65
Figure 4-19 Monte Carlo simulation results (1000 sample) for one channel ............................. 66
xiii
PUBLICATIONS
1. Y. You, S, Zhu, K. F. Warnick and D. Heo, “An X-band Eight-Channel Phased Array
Receiver With Low Phase Error SiGe PIN Diode Phase Shifter” will submit to TCAS I in
October, 2013.
2. Y. You, S, Zhu, K. F. Warnick and D. Heo, “A Low Phase Error X-band Eight-Channel
SiGe PIN Diode Phased Array Receiver,” The European Microwave Integrated Circuits
Conference (EuMIC), 2013, pp. 268-271. Oct 2013
3. S. Zhu, Y. You, K. F. Warnick, S. P. Sah and D. Heo, "An 8-channel Ku Band
Transmitter Beamformer with Low Gain/Phase Imbalance between Channels", European
Microwave Conference (EuMW), 2013, pp. 947-950. Oct 2013.
4. S. Zhu; A. O. Mikul, P. Sun; Y. You; Kim, J.-H. B.-S. D. Heo,, "Inductor-less SiGe pin
diode attenuator with low phase variations," Electronics Letters, vol.48, no.20,
pp.1287,1289, September 27 2012
5. O. Mikul, S. Zhu, P. Sun, Y. You, S. P. Sah, D. Heo, "Low Phase Imbalance Broadband
Attenuator based on SiGe PIN Diode", IMS 2012, Montreal, June 2012.
6. Siqi Zhu, Yu You, Deuk Heo, et al., “Current-reuse and Gate-modulation Techniques for
Sub-1mW QVCO”, Electronics Letters, Vol. 47, No. 9, pp. 530-531, Apr. 2011
7. L. Wang, P. Sun, Y. You, A. Mikul, R. Bonebright, G. A. Kromholtz, and D. Heo,
“Highly Linear Ku-band SiGe PIN Diode Phase Shifter in Standard SiGe BiCMOS
Process”, IEEE MWCL, Vol. 20, NO. 1, Jan 2010
xiv
1
1.1
INTRODUCTION
Phased-Array System
Over the last decade, phased-array systems proposed in 1950s [1], have been receiving
considerable attention by the military and industry in communication and radar systems
applications (Figure 1-1). Compared with mechanical scanning methods, shown in Figure 1-1 (a),
which is inherently slow, requiring large amounts of power to respond rapidly and to handle high
speed moving targets, phased-array systems that use electrical scanning (Figure 1-1 (b)) provide
significant advantages. Phased-array systems can achieve electronic beam forming and fast beam
scanning by controlling the phase of EM wave transmitted or received by each element relative
to the phases of other elements in the array [2]. Another fundamental merit of phased-array
systems is better signal-to-noise ratio (SNR) because signals from antenna arrays add coherently
while noise from each receiver chain adds incoherently, hence increasing the channel capacity
[3].
(a)
(b)
Figure 1-1 Phase Array antenna systems: (a) An SPS-48E radar antenna (the large square panel)
[4], mechanically steered, and (b) Alaska District’s 90-foot diameter phased-array radar for
missile warning and space surveillance [5], electrically steered.
1
Figure 1-2 illustrates the basic operating principle of phased-array receiver. Traditionally, a
phased-array consists of a group of antennas that provide beamforming and beam steering
capabilities. For the receiver side, the radiated signal reaches each antenna element of the array
at different times depending on the angle of incidence and the distance between the antennas.
The phased-array system compensates for the phase and amplitude difference before combining
these radiated signals. At the same time, strong interference from different directions can be put
in the null of a radiation pattern so that their influence on the desired signal can be decreased.
Therefore, the effective radiation pattern for the phased-array is reinforced in a desired direction
and suppressed in undesired directions. A similar explanation applies to the transmitter side with
spatial power combining method.
V1
Phase shifter
Φ
LNA
V2
IF
Σ
Vn
LO
Φ
LNA
Combiner
Figure 1-2
n-channel phased-array receiver
Initially phased-arrays have been used extensively in military application, such as
surveillance, target detection systems and missile defense. Recently, its application has been
extended to civilian sectors [6] [7]. Figure 1-3 shows some typical examples, such as rapid
hazardous weather detection, surveillance for air traffic control, air quality control and etc.
2
Moreover, consumer oriented communications use phased-array, such as WiMax wireless
networking and automotive radar.
Figure 1-3 Phased-array application in civilian sector [6] [7]
1.2
Phased-array Architecture
Basically, there are two types of architecture of phased-arrays. One is RF phase shifting
architecture, while the other is mixer-based architecture, with either LO or IF phase shifting.
Figure 1-4 shows the different phased-array architectures.
In terms of the architecture of phased-array, phase shifting in the RF domain for each array
has been dominant since they were first developed [9]. Also, phased-arrays based on LO phase
shifting and IF shifting have been widely investigated. Phased-arrays based on RF phase shifting
[8]-[13], IF phase shifting [14], and local oscillator (LO) phase shifting [15]-[17] have been
implemented in standard CMOS and SiGe technologies.
RF phase shifting architecture is prevalent because it has been developed due to several
advantages over its alternatives. First, the output RF signal after the combiner has high pattern
directivity, and can suppress the interference signal before the mixer. This acts like a spatial filter,
which receives the RF signal from a specific direction. On the other hand, all directions of
3
interfering signals of systems adopting LO and IF phase shifting methods do not filter out before
the mixer, which will generate lots of spurs and inter-modulation decreasing system S/N.
Another advantage of RF phase shifting architecture is that it does not require a distribution LO
network. This leads to simple system architecture and layout, especially for large phased-array
with 64-100 elements. Also, in satellite or defense-based applications, the required LO phase
noise is extremely low, which can be achieved by using an external oscillator.
Figure 1-4
Phased-array receiver architectures: (a) RF phase shifting, (b) IF phase shifting,
(c) LO phase shifting
4
Therefore, based on the above information, RF phase shifting architecture was chosen for our
research. However, RF phase shifting architecture has some disadvantages. Phase shifting in the
RF domain is always difficult and cumbersome. In this dissertation, an X-band 8 elements
phased-array receiver, an L/S/C/X ultra-wideband phased-array receiver, and a K-band 4-channel
phased-array receiver are developed in a SiGe BiCMOS process using RF phase-shifting
architecture.
1.3
Thesis Objective
The advances in CMOS and SiGe HBT processes have allowed high-performance ICs to be
implemented at microwave and even millimeter-wave frequencies. We aim to develop low cost
phased-array receivers, especially at L/S/C/X/Ku/K-bands, while still maintaining all the
functionality (NF, power, bandwidth, etc.) compared with its GaAs counterpart. GaAs cannot
compete with CMOS and SiGe HBT process in terms of yield, functionality and integration
density on a single chip. CMOS or SiGe HBT process can easily integrate multiple channels with
all the digital control functions on a single silicon chip with excellent yield and uniformity.
The primary objective of this thesis is to develop multi-channel phased-array receivers at
L/S/C/X/Ku/K-bands using commercial SiGe process, and to investigate technical difficulties of
integrating phased-array receiver in a single silicon chip as well as the package issues. Phase
shifter is essential and the most challenging element in phased-array system as to compensate for
the time delay between antenna elements. The passive phase shifting approach along with active
method are both studied aiming at low insertion loss, wideband, low RMS gain, and low phase
error. Amplitude control is also desirable in modifying the array factor to minimize sidelobes and
place nulls on interferer positions. VGAs are explored to provide low phase variation over gain
5
control states, which is important to maintain similar phase response while minimizing the
amplitude variation in the phase shifter. LNAs and combiners are also investigated to provide
competitive performance for the system.
The main contributions of the research works are summarize as follows: high performance
PIN diode switches are designed to ensure low phase error in X-band phase shifters; the bridgedT type phase shifter with center-tap inductor is first analyzed using an equivalent-circuit model
to obtain analytical form of component values; an ultra-wideband phased-array receiver from Lto X-band demonstrating more than one decade 3dB bandwidth is designed; and a new phase
shifter structure by using floating body technique to reduce insertion loss, and using parasitic
resonant frequency elimination technique to increase bandwidth is proposed in K-band.
1.4
Thesis Organization
The thesis is organized into 5 chapters. A brief overview of the phased-array system
operating principles, advantages of phased-arrays and architecture are provided in Chapter 1.
Chapter 2 will discuss the design of X-band 8-channel phased-array receiver based on PIN diode
passive phase shifting approach. The bridged-T type phase shifter with center-tap inductor is
analyzed using an ideal equivalent-circuit model to obtain analytical form of component values.
Chapter 3 presents an L/S/C/X 8-channel phased-array receiver in which active phase shifting
approach is adopted as passive one cannot achieve ultra-wideband performance. Ultra wideband
LNA and differential ultra-wideband approximate dB-linear gain control VGA are also discussed.
In chapter 4, a low insertion loss, wide band phase shifter in K band is proposed. The phase
shifter uses floating body and parasitic resonant frequency elimination technique. This K-band
phased-array receiver is implemented in commercial 0.13µm SiGe process with deep silicon via
6
(DSV) technology to decrease parasitic ground inductance. The dissertation is concluded in
chapter 5.
7
2
X-BAND PHASED-ARRAY RECEIVER
Phased-arrays implemented using SiGe and CMOS technologies have been widely
demonstrated from microwave to millimeter-wave frequencies [18]-[21], [9] for a variety of
applications, such as wireless communications, radar and high-speed short-range wireless
personal area networks. Due to its advantages, phase shifting in the RF domain for each array
element is chosen for the proposed receiver design. Appropriate phase delay as well as variable
gain weighting for signals at each input is desirable for phased-array systems. The gain
weighting controls the sidelobe performance of the beams, whereas proper phase shifting
improves signal reception from a desired direction and rejects emissions from other directions,
increasing SNR at the receiver output [22]. To achieve high directionality, accurate phase for
each signal path is required. Decreasing phase errors results in improved performance of array
pattern through enhanced directivity and reduced beam pointing angle error. Gain weighting in
each channel equalizes the amplitude in phase shifter and tapers amplitude across array to
decrease side-lobes [2].
The proposed X-band 8-channel SiGe PIN diode phased-array receiver [23] [24] incorporates
a VGA and passive phase shifter for amplitude and phase control in each channel. Low insertion
loss and high isolation PIN diode switches [25] used in phase shifters ensure low phase error [26].
A current steering VGA [27] provides low phase variation over gain control states, which
maintains similar phase response while equalizing the amplitude in phase shifter. The design is
optimized to minimize VGA phase error at high gain states. A LNA precedes the VGA in each
channel, which enhances noise figure performance to ease off-chip LNA requirements. RF
signals for four channels are combined after the phase shifters using an active approach.
8
This chapter is organized as follows: Section 2.1 presents the details of proposed X-band
phased-array system, and more specific building block design, and implementation details are
provided in section 2.2. The measurement results of the phased-array system are presented in
section 2.3.
2.1
System Architecture
Figure 2-1 presents the system architecture of the X-band 8-channel phased-array receiver.
Channel 5-8 is a replica of channel 1-4. Each array channel is composed of a LNA, a 3-bit VGA
and a 3-bit passive phase shifter. The 3-bit VGA adopts current steering structure to control the
gain of each channel, allowing high directional pattern and pattern side-lobe reduction. The 3-bit
phase shifter based on low loss PIN diode is realized with switched low-pass structure for 45°
and 90°, and switched low-pass/high-pass structure for 180°. Because of loss in phase shifter, it
is better to allow VGA preceding phase shifter to decrease system noise figure. Each VGA and
phase shifter can be controlled independently using digital inputs from an array decoder which is
composed of a 3-to-8 address decoder. A 3-bit digital data sequence, which sets the phase to each
phase shifter or gain to each VGA, is loaded to the phase shifter or VGA by an enabling clock
signal and an address decoder output corresponding to the address of each channel. Through
amplitude and phase control in each channel, the RF signals have approximately equal phase and
amplitude before the combiner. An active binary fashion combiner is realized to combine 4
channels RF signals into one output.
9
Figure 2-1
2.2
Block diagram of the eight-channel X-band phased-array receiver
Building Block Design
2.2.1
X-band LNA
The schematic of LNA, shown in Figure 2-2, consists of two-stage common emitter
amplifiers with emitter degeneration in the first stage. According to [28], an optimum collector
current density (Jc) at minimum NFmin is determined for Q1. Then the emitter length of Q1 is
scaled for the optimum noise resistance (Ropt) to be 50 Ω while maintaining the same Jc. Thus,
10
the resistive part of noise impedance is matched with source impedance. The emitter
degeneration inductor (LE) matches the real part of input impedance, as well as improves
linearity by adding a negative feedback, at cost of reducing gain and slight increasing NF. At this
frequency range, LE has negligible influence on Ropt as collector-base feedback capacitance’s
influence is small at this frequency range (Cµ =43 fF). Simulation shows the Ropt only increases
less than 2 Ω. The series inductor LB serves to resonate with the input capacitance, Cπ, at the
center of operating frequency, as well as to transform the optimum noise reactance to the center
of Smith chart. The input impedance can be expressed as
Zin ≈ s( LB + LE ) +
g L
1
+ m E
sCπ
Cπ
(2-1)
where gm is the transconductance of Q1. The equivalent capacitance for the ESD diodes and pad
is around 38 fF, which does not disturb the input impedance matching as it can be included into
LB matching design. The size and bias point of second stage transistor Q2 is optimized for gain.
The inter-stage matching (LC, C2) is critical to obtain good forward gain (S21), as well as desired
linearity, which is optimized to achieve the best conjugate matching between optimum source
impedance and optimum load impedance, while at same time obtaining moderate linearity. The
output matching network is an L-network, which consists of a shunt inductor (L1) and a series
capacitor (C3). De-Q resistor, R1, provides better bandwidth performance, as well as improves
stability.
The simulated gain, NF and output P1dB at 10.5 GHz are 18 dB, 3.8 dB and 0.6 dBm,
respectively. The simulated input and output return loss are all below -10 dB.
11
Figure 2-2
2.2.2
Circuit diagram of X-band LNA
X-band VGA
Amplitude control as well as phase control is desirable in modifying the array factor to
minimize sidelobes and place nulls on interferer positions. The VGA adopts a current steering
structure, which has a constant bias current for the input stage, providing lower phase changes
over the VGA gain states, thus leading to a lower phase imbalance compared with varying transconductance or feedback approaches.
The schematic of the proposed VGA is shown in Figure 2-3. C1, C2 and C3 are DC blocking
capacitors. L2 and L3 are loads of the first and second stage amplifiers, respectively. R1, R2, R3
and R4 are emitter degeneration resistors to improve linearity. L1 is the input impedance
matching inductor. Transistor Q5 is always activated by the digital control signal D_on,
providing the minimum gain of VGA. Q2, Q3 and Q4 have binary scale sizes for current
weighting. The gain variation is implemented by steering the bias current of the input transistors
(Q2, Q3 and Q4) to two cascode stage transistors (Q6 and Q61, Q7 and Q71, Q8 and Q81).
When the control voltage (D1, D2 and D3) is high, current is steered to RF path and signal is
12
amplified, which sets the highest gain. When control voltage (D1, D2 and D3) is low, current is
steered to AC ground without amplification, and this is minimum gain setting. The input stage
current (ISS) keeps constant regardless of gain states, leading to constant input impedances. The
output impedance is also constant for different gain states by virtue of isolation of second stage.
According to [27], the input transistors Q2, Q3 and Q4 are binary scaled for 3-bit operation,
and therefore the trans-conductance is scaled as well in the same way. Thus the VGA voltage
gain can be expressed as
Av = − sg m 0 L 2 (1 + α ⋅ d 1 + 2α ⋅ d 2 + 4α ⋅ d 3 )
(2-2)
where gm0 is the trans-conductance of Q1, and {d1 d2 d3} is the binary word for the digital control
തതത, D2 and തD2
തതത, D3 and തD3
തതത}, which is the least significant bit (LSB), the
voltage for {D1 and തD1
second least significant bit and the most significant bit (MSB), respectively. ߙ is the current ratio
of Q4 to Q1.
Figure 2-3
Circuit diagram of X-band VGA
13
The VGA is designed to achieve 12 dB gain control range, leading to ߙ=0.43. The size of Q1
is chosen to have a small size. Then the size of Q2, Q3 and Q4 are scaled. Degeneration resistors
(R1, R2, R3 and R4) are also scaled in the same way to improve the accuracy of bias current as
well as to increase linearity of first stage. The output capacitance (Cµ +Cπ) for cascode stage
slightly change depending on the gain states. Since the transistor size of Q3 and Q4 is smaller
than Q2, the phase variation is small for LSB and the second least significant bit. However, it
gets worse when switching to MSB. The VGA in phased-array receiver is used to equalize the
amplitude in phase shifter, thus the phase imbalance is more important for LSB and the second
least significant bit as they provide small gain steps for equalization.
The simulated gain range is 12 dB (-2~10 dB). The input and output return loss are all below
-10 dB at 9.5~11.5 GHz.
2.2.3
X-band Pin-diode Based Phase Shifter
A PIN diode is implemented by highly doped P+ (anode) and N+ junction (cathode) with
lightly doped intrinsic (I) region. In a standard SiGe 0.18-µm BiCMOS process, the PIN diode is
realized with HBT material layer [25]: the P+ base layer, the N-epi collector layer and the buried
n+ subcollector layer. According to [25], the insertion loss can be improved by reducing forward
bias resistance through minimizing the anode’s periphery-to-area (P/A) ratio. The relationship
between current dependent resistance RI and P/A can be represented by (2-3):
li 2
1
P
RI ≈
+ v perim ( ))
(
2 µ I dc τ int erface
A
(2-3)
where, li is the thickness of intrinsic region, µ is the average electron and hole mobility, Idc is
the forward bias current, τinterface is the P+/I interface minority carrier lifetime, vperim is the
effective hole surface recombination velocity. For 50 µm2 anode size, changing from rectangular
14
and square shape to octagonal shape will result in 52.9% and 9.28% P/A improvement,
respectively. Figure 2-4 (a) shows the octagonal PIN diode with 50 µm2 anode size.
The passive X-band phase shifters, shown in Figure 2-4(c), are switched LC networks using
different L and C to implement different phase delay. The 180° bit uses high-pass/low-pass filter,
and the 90° and 45° bit use bridged-T low pass filter. In 90° and 45° bit, two different switches
are adopted. SiGe PIN diodes are chosen on RF signal path for high linearity, low insertion loss,
and low phase error. The 50 µm2 PIN diode provides around 0.8 dB insertion loss, over 15 dB
isolation at 10.5 GHz, which ensures good return loss and isolation, thus, better phase error [26].
Low parasitic and high resonant frequency inductors based on EM simulation help to decrease
phase error [26]. MOSFET switches are used for parallel resonance to reduce power
consumption. The resistors Rb set PIN diode current to 1 mA, which provides the highest
linearity [29]. Center-tap inductors, L1 and L2, are used instead of two single-ended inductors to
save chip areas and reduce the loss associated with the inductors.
Figure 2-4(b) shows the equivalent circuits of symmetric center-tap inductor with a magnetic
coupling coefficient k between two inductors, which generate a mutual inductance of M. The two
coupled inductors have almost same inductance value L. And the coupling factor k, selfinductance L, and mutual inductance M are related by
M ≈ k LL = kL .
(2-4)
The equivalent circuit of 45° and 90° bits are depicted in Figure 2-4(d). The center-tap
inductor with mutual coupling (M) leads to greater inductance in series (L+M), and larger
parallel capacitance compensating the mutual inductor compared with using single-ended
inductors.
15
The ABCD-matrix of an ideal lossless transmission line with Z0 characteristic impedance and
θ electrical length is given by
 cosθ
A
B

 
 C D  =  j 1 sin θ


 Z0
jZ0 sin θ 
.
cosθ 

(2-5)
Figure 2-4
(a) Octagonal PIN diode layout, (b) equivalent of center-tap inductor, (c)
circuit diagrams of X-band phase shifter, and (d) equivalent circuit for 45° and 90° bit
Also, the ABCD-matrix of T-type low pass filter using center-tap inductor, the phase delay path
for 45° and 90° shown in Figure 2-4(d), is given by
 A B  1
 C D  = 0

 
1


jω ( L + M ) 
1
j

1
  ωM + 1

ωC
16
0
 1
1 
 0

jω( L + M )
.
1

(2-6)
If the bypass path is ideal, meaning 0° phase delay, a desired phase delay θ can be achieved
by equating the two ABCD-matrixes in equation (2-5) and (2-6). Thus, the inductors and
capacitors in 45° and 90° bits can be represented by
k cot 2 θ + cot 2 θ + 2
Z0 (
− cot θ )
k
+
1
L=
,
2ω
C=
(2-7)
2L(k + 1)
.
Z02
(2-8)
According to (2-7) and (2-8), the inductance and capacitance values for 45° and 90° are
calculated, as shown in Table 2-1, if k is assumed to be 0.9, which is a good estimation for
center-tap inductor at this range of inductance. However, the reference path provides about 5°
phase delay in simulation, rather than an ideal 0° phase delay. A small increment of phase shift
in the delay path can compensate for the reference path.
The 180° bit is implemented using a high-pass/low-pass topology. For the low-pass and highpass Π network, the input and output ports must be matched while having desired phase shift at
the center frequency. The inductance and capacitance can be calculated for a desired phase delay
as [30]
L3' =
L3 =
Z0
ω0 tan θ / 2
C3' =
Z 0 sin θ
C3 =
ω0
17
1
,
ω0 Z 0 sin θ
tan θ / 2
ω0 Z 0
.
(2-9a)
(2-9 b)
The simulated insertion loss is 10±1.5 dB. The return losses are all below -10 dB at 9.5-11.5
GHz.
Table 2-1
2.2.4
Inductance and capacitance values for 45° and 90° in X-band phase shifter
45°
90°
L
164 pH
389 pH
C
249 fF
591 fF
K
0.9
0.9
X-band Active Combiner
The beam combiner is realized with active adder amplifiers for wideband signal combining,
and the combining of the four channels is done in binary fashion. The receiver consists of two
4:1 combiners. Figure 2-5 depicts the schematic of the combiner. The signals are then combined
through the cascode transistors. Resistors, Re, served as degeneration to improve linearity, and
inductor L1, along with resistor R1 are used as the load to provide better broadband performance.
Figure 2-5
Circuit diagram of X-band combiner
18
All I/O pads including RF pads are protected by using dual-diode ESD cells. Minimum size
of ESD diodes are used at the input of LNA. Standard transistor cells and models are used, and
microstrip lines are used throughout the chip for interconnection. Passives including inductors,
capacitors and interconnects are simulated in ADS Momentum.
2.3
Measurement
2.3.1
On-wafer Measurement
The phased-array receiver is implemented in a 0.18-µm SiGe BiCMOS process with ft of 150
GHz, which occupies 2.4 × 4.8 mm2 including all pads, as shown in Figure 2-6
Address
Vdd
CH1
LNA
VGA
Phase Shifter
CH2
CH3
CH4
Figure 2-6
Chip microphotograph of the 8-channel phased-array receiver (2.4 × 4.8 mm2)
The single-channel and four-channel phased-array chips are measured on-chip after a
standard probe-tip short-open-load-thru (SOLT) calibration. The only control inputs applied to
the chip are supply voltages (analog and digital), address bits (3 bits), data bits (3 bits) and clock
signals. A single channel consumes a total current of 30 mA with 1.8 V supply voltage for LNA,
19
3.3 V for VGA, phase shifter and digital control circuit. The combiner consumes 16 mA with 3.3
V supply voltage.
0
-30
Output
-4
-40
-6
Input
-8
-10
-50
Isolation
-12
Isolation (dB)
Input & output return loss (dB)
-2
-14
-60
-16
-18
-20
9.5
10.0
10.5
-70
11.5
11.0
Frequency (GHz)
Figure 2-7
Measured input, output return loss and reverse insolation for 8 phase states
-238
16
14
-240
10
-244
8
Gain (dB)
Phase (degree)
12
-242
-246
6
-248
4
Phase
Gain
-250
2
0
2
4
6
Digital State
Figure 2-8
Measured VGA gain control and phase response at 10.5 GHz
20
Figure 2-7, Figure 2-8, Figure 2-9, Figure 2-10 and Figure 2-11 depict the single channel
(Channel-1) measured results. The input return loss is < -7.4 dB from 9.5 to 11.5 GHz, and
output return loss is < -2.3 dB at 9.5-11.5 GHz, shown in Figure 2-7. The input and output
matching networks are designed to incorporate parasitics from flip-chip package, which consists
of around 0.2 nH series inductance and 34 fF parallel capacitance. This will result in some
degradation of return loss. Another reason for bad output matching is that one inductor at output
is not properly EM simulated. The isolation between input and output is better than -50 dB.
The measured VGA exhibits 12 dB gain control range over 3-bit control states at 10.5 GHz.
(see Figure 2-8). The phase response varies 8.7° over all the gain states, and furthermore, it only
changes less than 1.5° from 100 state to 111 state, where gain varies 2 dB, which can be used to
adjust RMS gain error in phase shifter with slight degradation of RMS phase error.
20
2.0
Average
W/O VGA control
W VGA control
1.8
Gain (dB)
1.4
1.2
10
1.0
0.8
5
0.6
0.4
0
9.5
10.0
10.5
Frequency (GHz)
(a)
21
11.0
0.2
11.5
RMS Gain Error (dB)
1.6
15
400
10
W/O VGA control
W VGA control
8
0
-200
6
-400
4
RMS Phase Error (degree)
Insertion Phase (degree)
200
-600
-800
9.5
10.0
10.5
2
11.5
11.0
Frequency (GHz)
(b)
Figure 2-9 Measured single channel (channel 1) characteristics for all 3-bit phase states (@max
VGA gain): (a) gain and RMS gain error; (b) 3-bit insertion phase response and RMS phase error.
5.8
5.6
Noise Figure (dB)
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
9.0
9.5
10.0
10.5
11.0
11.5
12.0
Frequency (GHz)
Figure 2-10
Measured NF for channel 1 (@max VGA gain and ref. phase state)
22
0
VGA Min Gain
VGA Max Gain
Output Power (dBm)
-10
-20
-30
-40
-50
-32.5dBm
-60
-60
-50
-40
-30
-14dBm
-20
-10
Input Power (dBm)
Figure 2-11
Measured input P1dB (@max and min VGA gain)
The measured average gain, shown in Figure 2-9(a), is 11.1-16.4 dB at 9.5-11.5 GHz, and is
14.2 dB at 10.5 GHz. The measured RMS gain error is less than 1 dB without VGA control and
less than 0.67 dB with VGA control for all 3-bit phase state at 9.5-11.5 GHz. The measured
insertion phase responses show very linear phases at 9.5-11.5 GHz [Figure 2-9(b)]. It can be seen
that RMS phase error is less than 4.8° at 9.5-11.5 GHz, achieving 6-bit accuracy. Some phase
error is introduced by VGA when it is used to equalizing the amplitude imbalance between
different phase states. However, the phase error introduced by VGA is very small due to low
insertion phase variation over gain states, especially at high gain states. Still, the RMS phase
error remains less than 5° at 9.5-11.5 GHz, slightly worse than without VGA control. At 9.5-11
GHz, the RMS phase error is actually better than without VGA control.
The NF of 1st channel is less than 5 dB from 9.5 GHz to 11.5 GHz, shown in Figure 2-10.
The other three channels (Ch2-ch4) exhibit similar NF performance. The measured input P1dB is
23
-32.5 dBm at maximum VGA gain, and -14 dBm at minimum VGA gain (see Figure 2-11). The
linearity is limited by VGA, and not by the phase shifter and combiner.
300
Phase state (111) for ch1~ch4
Insertion Phase (degree)
200
100
0
-100
-200
Ref. phase (000) for ch1~ch4
-300
-400
9.5
10.0
10.5
11.0
11.5
Frequency (GHz)
(a)
Phase 000
Phase 001
Phase 010
Phase 011
Phase 100
Phase 101
Phase 110
Phase 111
Phase Mismatch (degree)
5
4
3
2
1
0
9.5
10.0
10.5
11.0
11.5
Frequency (GHz)
(b)
Figure 2-12
(a) phase states of four channels (@max VGA gain); (b) Measured RMS phase
mismatches compared with channel-1 for all phase states
24
2.0
Phase 000
Phase 001
Phase 010
Phase 011
Phase 100
Phase 101
Phase 110
Phase 111
1.8
Gain Mismatch (dB)
1.6
1.4
1.2
1.0
0.8
0.6
9.5
10.0
10.5
11.0
11.5
Frequency (GHz)
1.0
8
RMS gain error over VGA gain states
RMS gain error over phase shifter states
RMS phase error over VGA gain states
RMS phase error over phase shifter states
0.8
RMS Gain Error (dB)
Measured RMS gain mismatches of four channels
6
4
2
0.6
0
0.4
-2
-4
0.2
-6
0.0
RMS Phase Error (degree)
Figure 2-13
-8
9.0
9.5
10.0
10.5
11.0
11.5
-10
12.0
Frequency (GHz)
Figure 2-14
Measured RMS gain and phase errors of channel-1 due to coupling when
changing gain or phase states of channel-2
Channels 2, 3 and 4 were also measured to characterize the mismatches between channels,
which were determined by comparing the S-parameters at maximum gain and 0°-bit (reference
25
bit) with channel-1 of all the phase states. Figure 2-12(a) shows the phase states of four channels
at maximum VGA gain setting. The RMS phase mismatches, shown in Figure 2-12(b), are less
than 3.5° at 9.5-11.5 GHz, much smaller than 45° of the 3-bit phase quantization level. The RMS
gain mismatches are below 1.56 dB for four channels for all 3-bit phase states (Figure 2-13),
which is slightly large due to the imbalance of gain between channels. Channel-4 has better
ground parasitics than other channels, which provides higher gain compared with other channels.
This chip is designed for flip-chip package with 220 um pad pitch, which is conservative
regarding yield issue. If a smaller pad pitch, such as 150um, is used, more ground pads can
decrease the imbalance of ground parasitics and reduce RMS gain mismatch.
Table 2-2
Ref.
Performance Comparison of X-band multi-channel phased-array receivers
RMS
RMS
Freq.
Phase
No. of
Gain
Gain
Phase
(GHz)
bits
Channels
(dB)
Error
Error
(dB)
(deg)
Technology
0.13um
8.5-
BiCMOS
10.5
0.13um
8.5-
CMOS
10.5
[18]
[19]
Noise
Pdiss (mW)
Figure
Tot. / per
(dB)
channel
3
2
8.5-11.5
0.15-0.3
—
4.5-5.5
8/4
4
4
7.5-12.5
0.3-1.3
2-17
3-5
76/19
4
8
8-20.5
0.5-0.9
2.5-5.7
4-12
561/70
4-5
4
6-10.1
0.2-0.8
4.5-13
3.75-5
144/36
0.47-1
3.5-4.8
3
8
11.1-16.4
0.4-0.67 *
2.8-5 *
4.2-5
813/88.5
0.18um
[9]
6-18
BiCMOS
0.13um
8.5-
CMOS
10.5
0.18um
9.5-
[20]
This
Work
*
BiCMOS
11.5
With VGA control
26
Coupling between channels plays an important role in phased-array chips, as described in [9]
and [31]. To investigate the coupling between channels, channel 1 is measured under maximum
gain and reference bit condition when varying the gain and phase states of channel 2 for all 3 bits.
Note that the input impedance at channel 1 is set to an open circuit, which leads to maximum
voltage coupling, thus, a worst case condition for coupling [31]. As shown in Figure 2-14, the
measure RMS gain error is less than 0.35 dB, and RMS phase error is less than 3.5°, which are
negligible. From this graph, it is evident varying phase shifter’s states of channel 2 produces
more phase and gain errors than changing VGA’s gain states. This is because the leakage from
phase shifter of channel 2 will undergo a shorter path to combiner than from VGA [9].
Table 2-2 presents a comparison of this work with other X-band multi-channel phased-array
receivers. The design in [9] is based on an active vector modulator method showing very
wideband performance. It is evident that this design achieves the lowest RMS phase error
compared with chips in [18], [19] and [20] with equal bandwidths which adopt a passive phase
shifting approach.
2.3.2
Packaged Chip Board Measurement
The chip was designed for flip chip BGA package. Figure 2-15 shows the evaluation board
measurement test setup with flip-chip packaged chip soldered on board.
Figure 2-16 show the evaluation board measurement results of channel 1 with reference
phase state which means all the PIN diodes are turned on. The input return loss is less than -3 dB.
Phase variation of gain setting is less than 30°. The gain is between 2.4 dB and 12 dB at 10GHz,
and -11 dB and 2.5 dB at 13 GHz. Figure 2-17 shows the measured return losses, gain and phase
state with maximum gain setting of channel 1. The input return loss is less than -4 dB. Gain
variation over all 8 phase states is than ±3.3 dB.
27
Figure 2-15
Figure 2-16
Board measurement set up for X-band phased-array receiver
Board measured channel 1 performance with 8 gain states
The gain roll off is large, about 15 dB from 10 GHz to 13 GHz. Phase variation over gain
control states is around 20°~39°, which is big when used to compensate for the gain imbalance
28
between different channels. Moreover, the return losses are not good enough. The reason is that
package ground parasitics are not considered during the design stage. Only 8 RF inputs’ and 2
RF outputs’ parasitics are included in the post layout simulation. The package ground parasitics
are not small enough to be neglect, which is shown in Figure 2-18. Label ground1 shows ground
parasitics for LNAs which is so large (about 0.3 nH) to substantially degrade the LNA
performance. Ground2 is the parasitics for VGA and phase shifter.
Figure 2-17
Board measured channel 1 performance with 8 phase states
29
Figure 2-18
Ground parasitics for flip chip package
Figure 2-19 Simulated gain (dotted red line) including ground parasitics of flip chip package
compared with measured results (solid line, S51-channel 1, S54-channel 4)
Figure 2-19 depicts the simulation results of gain including ground parasitics of flip chip
package compared with measured results. It can be seen the simulation results match with
measured results when ground parasitcs of package are considered.
30
2.4
Summary
A low phase error X-band eight-channel phased-array receiver in a 0.18-µm SiGe BiCMOS
technology has been demonstrated at 9.5-11.5 GHz. The receiver is based on RF phase shifting
architecture with LNAs, 3-bit variable gain amplifiers, 3-bit passive phase shifters and 4:1 active
combiners. Board measurements show some problems due to lack of including ground parasitics
of package. On wafer measurement results show less than 0.7 dB RMS gain error, and less than 5°
RMS phase error with VGA control by using high performance PIN diode in phase shifter. On
wafer measurements on all four channels show low RMS gain and phase errors due to coupling
between the four different channels. To the authors’ knowledge, the receiver has the best RMS
phase error performance in recently published work on multi-channel X-band phased-array
receivers using passive phase shifters.
31
3
3.1
L/S/C/X BAND PHASED-ARRAY RECEIVER
System Architecture
Frequency bands from L to X band have been used extensively for wireless communication
and satellite communication. An 8 element phased-array receiver covering the frequency band
was developed to reduce total die area and production costs in multiband receiver
implementations. However, the design of wide band receiver is very challenging in term of wide
band low noise input stage design, wide band gain control design and wide band phase control
design. Figure 3-1 shows the system architecture, which include LNAs, 4-bit VGAs, and 4-bit
active phase shifters. However, it does not include combiner for simplification.
Figure 3-1
L/S/C/X band phased-array receiver
32
Shunt feedback LNAs are adopted in first stage for each channel in order to achieve
wideband amplification. Wideband single-ended to differential converter in the second stage
provides differential conversion and common-mode rejection. To minimize ground parasitics,
differential structure is used for VGA and phase shifter. The final stage after phase shifter is a
push-pull amplifier providing differential-to-single-ended conversion. In order to achieve wide
band operation, vector modulation is adopted for the phase shifter compared with passive one.
-26 dBm
-8 dBm
0 dBm
-5 dBm
LNA
VGA
PS
18 dB
-13~8 dB
-5 dB
Figure 3-2
Gain and power distribution for L/S/C/X receiver
The gain and power distribution for L/S/C/X receiver is depicted in Figure 3-2. The output
power of LNA is -5 dBm, and the gain range for VGA is from -13 dB to 8 dB.
3.2
Building Block Design
3.2.1
Wideband LNA Design
We aim to design a ultra-wideband low noise amplifier within the entire frequency range of
0.8 GHz to 12 GHz (L/S/C/X band) meeting the requirement of high gain (>15 dB) with low
noise figure while at same time achieving the lowest DC power consumption possible. Instead of
integrating several LNAs in a multi-standard receiver for different frequency bands, this
wideband LNA significantly reduces the complexity of the receiver architecture, and because of
33
its broadband characteristic, this LNA is also capable of being used in very high speed
communication systems.
As for noise figure, it is particularly challenging to achieve the noise figure specification in
that the device optimum input impedance, Fopt, for minimum noise figure is frequency dependent;
therefore, it is impossible to achieve Fmin over the entire frequency band. Moreover, the
bandwidth is very wide. Choosing bias point at minimum noise figure current density for bipolar
can improve NF performance, but decrease gain at same time. According to the Friis equation, it
is better to get larger gain at the first stage to suppress noise at subsequent stages. These two
conflicting requirements result in the need for a first stage with better gain and acceptable noise
figure. In this project, the bias current density at center frequency for the first stage is slightly
higher than current density of minimum noise figure to trade off noise figure and gain.
Some amplifier topologies are taken into consideration including a distributed amplifier and a
lumped element feedback amplifier. The distributed amplifier has higher DC power consumption
because it requires more transistors than other topologies, although it has the widest bandwidth.
The distributed amplifier also suffers from lower efficiency and higher noise. In order to achieve
the aggressive target of this project, especially bandwidth from 0.8 GHz to 12 GHz, a two stage
wideband LNA is proposed, which consists of common-emitter stage using resistive shunt-shunt
feedback in the first stage and a conventional emitter-couple stage with other input AC grounded
in the second stage to provide single-end-to-differential conversion.
Figure 3-3 shows a simplified schematic of the proposed LNA based on resistive feedback. A
shunt feedback resistor Rf is exploited to extend the bandwidth. A source-degeneration inductor
Le, which is implemented as a microstrip line, is also introduced at the input bipolar transistor to
ensure good input matching and stability over the entire bandwidth. Since the inductor Lb is
34
inside the feedback loop, it is smaller than a conventional shunt peaking inductor [32].
According to [32], fast current variation is delayed by inductors, which results in more current
being available to charge the parasitic capacitor associated with each node. For this reason, faster
variation is realized, leading to a wider bandwidth [33]. Lb1 works as a series peeking inductor
to boost high frequency gain. The feedback loop must be optimized to avoid introducing
additional excessive noise. With this optimized feedback, the desired bandwidth, good input
return loss and acceptable noise figure can be achieved simultaneously. A smaller feedback
resistor Rf compared with 1k of conventional design is used to decrease the quality factor of the
input series resonance circuit. However, the feedback resistor Rf degrades the noise figure of
LNA by approximately 0.5dB at center frequency.
Figure 3-3
Schematic of LNA in L/S/C/X band phased-array receiver
Moreover, we can lower the quality factor of the input matching network, which consists of
inductor Lb and Le, and base-emitter capacitance, Cbe, of Q1 if the effect of the resistive
feedback (Rf) is negligible. The Qin is set to be less than 1 in this design. As a result, the low
Qin renders the design a favorable wideband characteristic and better robustness to process
35
variation. Resistors Rc1 and Rc2 degrade the quality factor of load inductor Lc1 and Lc2, thus
further increasing the bandwidth.
3.2.2
Wideband Differential VGA
Basically, there are three VGA topologies based on a variable attenuation, feedback control
and current switching. The current switching structure is also chosen for L/S/CX receiver in that
it can maintain almost constant input impedance when gains change. However, compared with
VGA in X-band receiver design, differential structure is adopted to reduce ground parasitics at
cost of little bit more chip area.
Figure 3-4 depicts the schematic of differential VGA which contains two stages with
different gain steps. A common collector buffer is followed by the second VGA stage to
accommodate the low input impedance of phase shifter. The first and second stages have same
topologies but different sizes of bipolar transistors according to different gain steps. For the first
stage, an n-to-2n decoder takes a 2 bit inputs and produces 4 outputs (B0, B1, B2 and B3) which
control cascode stage differential pairs. Decoder makes only one cascode stage activate, the other
cascode stages deactivate. Then the sizes of bipolar transistors in cascode stage can be designed
accordingly to bypass more current, thus decrease more gain. Namely, the larger the current
diverted to the voltage supply (Vdd), the more attenuated the VGA gain. The total current of I1,
as shown in Figure 3-4, is split to the two paths according to the size ratio of bipolar transistors
as [34]
I bypass = I1 × α
where α = W1/W2, and W1 and W2 are the width of bypass path and signal path.
36
(3-1)
Bit B0 is the default state paralleled with the default signal path to increase turned-on
transistor size. When bit B0 is off, other bits (B1, B2 and B3), are turned-on whose sizes are
small or similar compared with the size of Bit B0, thus led to small phase variations. According
to the gain step in cascode stage (1.3dB/step in the 1st stage and 5.2 dB/step in the second stage),
the width ratio can be calculated through the following equation (3-2) for each bit which is listed
in Table 3-1
G = 20log(
Gain step
[0,1.3,2.6,3.9]
Wref − Wbypass
Wref
)
(3-2)
Gain step
[0,5.2,10.4,15.6]
Vdd
Vdd
Rl
outp
outn
I bypass
B3
Q9
B1
B2
Q10
Q7
Q8
Q5
Q6
B0
Q4 B0
Q3
I1
inp
Q1
Q2
inn
Re
GND
Figure 3-4
Schematic of wideband VGA in L/S/C/X band phased-array receiver
37
Table 3-1
Width Ratio of Cascode Stage in wideband VGA
α of first stage
α of second stage
Bit 1
0.14
0.45
Bit 2
0.26
0.7
Bit 3
0.36
0.83
However, the gm of cascode transistors does not exactly scale with transistor width. The
values in Table 3-1 are initial values, which need to be modified during the schematic simulation.
In order to achieve wide band performance, the inter-stage equivalent circuits are analyzed to
get insight how to broaden bandwidth performance. Figure 3-5 depicts half of the inter-stage
circuit of wideband VGA. The circuits in dashed line boxes are cascode stages for the first and
second stage. Q1 are input transistor, and Q2 are input transistor of second stage. R1 is the load
resistor, Re1 and Re2 are degeneration resistors, and C1 is DC block capacitor.
Figure 3-5
Half of inter-stage circuit in wideband differential VGA
38
Figure 3-6 depicts the equivalent inter-stage circuits of wideband VGA where Ccs (collector
to substrate capacitance) is so small to neglect its feedback effect. Series capacitors C1 and Cbe
can be represented by a capacitor Cs (equation 3-3). Then the series RC network, Cs and Re2 is
equivalent to the parallel RC network using the equation (3-4, 3-5).
Cs =
C1Cbe
C1 + Cbe
(3-3)
Q2
Ceq = Cs
1 + Q2
(3-4)
Req = Re 2 (1 + Q 2 )
(3-5)
where Q is represented by equation (3-6)
Q=
Figure 3-6
1
ωCs Re 2
Equivalent inter-stage circuit of wideband VGA
39
(3-6)
From Figure 3-6 (c), the input impedance can be calculated which is shown in equation
(3-7). Thus, the transimpedance gain Zx and the pole P1 can be expressed as follow:
Zx =
P1 =
Since Q is greater than 1 and 1
P1 can be simplified to 1
Rl C s
1
1
s (Ccs + Ceq ) + (
)
Rl + Req
1
R
ω 2Cs Re 2 (1 + e 2 (1 + Q 2 ))
Rl
ω Re 2 Rl Cs
(3-7)
(3-8)
>>1 in the frequency range, the expression of
. In order to increase the bandwidth of VGA, Rl and Cs needs
to be decreased. Usually, a large value is chosen for DC blocking capacitor which will
lower the pole frequency. Thus, the value of C1 is chosen to be equal the capacitance of Cbe
since we cannot decrease capacitance of C1 without limit as it will increase loss of RF signal
path. Secondly, R1 is optimized to offer better trade-off between gain and bandwidth.
3.2.3
Wideband Active Phase Shifter
An active phase shifter based on vector modulation was designed due to ultra-wideband
operation. Quadrature signal generation is essential for active phase shifter in a phased-array.
They are extensively used to generate basis quadrature vectors, which are then combined in an
active or passive method to create required phase delays. A quadrature all-pass filter (QAF) [35]
with high quadrature accuracy and low insertion loss over a wide bandwidth is used in L/S/C/X
phased-array receiver.
40
As shown in Figure 3-7, the quadrature phase generation is based on orthogonal phase
splitting between I path and Q path. According to [35], from input IN_p to output OI_p, it
exhibits high-pass characteristic, while from input IN_n to output OI_p, low-pass characteristic
are observed. Therefore, the linear combination of these characteristic leads to the all-pass
operation.
Figure 3-7
Schematic of wideband QAF
Vdd
Rl
Rl
outp
Iin+
SI
Q3 Q4
Q1 Q2
Iin+
Iin-
M1
M2
outn
SIB
Qin-
SQ
M3
I Ibias
I_DAC
M4
Iqbias
Q_DAC
MI
Figure 3-8
Q7 Q8
Q5 Q6
Qin+
MQ
Schematic of wideband differential adder
41
Qin+
SQB
Figure 3-8 shows the analog differential signed-adder [35], which combines the V-I
converted I- and Q-input from a QAF in current domain at the output node, synthesizing the
desired phase shifts. The polarity of I/Q input can be switched by changing the tail current from
one path to the other path with switches SI/SIB and SQ/SQB. Resistor load, Rl, is adopted instead
of inductor to save chip area as small form factor is also a consideration. The gain control of Iand Q-path of the adder for 4-bit phase resolution can be implemented by varying the bias
current ratio between two paths which requires DAC to calibrate. However, the complicate DAC
design is skipped in this phased-array receiver to get better chance of one-time success.
Therefore, manual control of DC current and control sign are adopted, and the control table is
listed in Table 3-2.
Figure 3-9
Push-pull differential-to-single-ended converter in active phase shifter
The differential-to-single-ended converter’s inputs inp and inn, shown in Figure 3-9, connect
to the differential output in differential adder. R1 is placed at the emitter of Q1 in order to
42
improve the output return loss at the cost of gain. R2 is used to balance gain between commonemitter and common-collector path. DC voltage Vb1 sets the current of converter.
Table 3-2 L/S/C/X band phase shifter control table
ABCD
3.3
SI
SIB
SQ
SQB
I_DAC
Q_DAC
(V)
(V)
0000
0°
1
0
1
0
0.55
2
0001
22.5°
1
0
1
0
0.95
0.95
0010
45°
1
0
1
0
0.95
0.55
0011
67.5°
1
0
1
0
1.5
0
0100
90°
1
0
0
1
2
0.51
0101
112.5°
1
0
0
1
0.95
0.6
0110
135°
1
0
0
1
0.75
0.95
0111
157.5°
1
0
0
1
0.5
2
1000
180°
0
1
0
1
0.55
2
1001
202.5°
0
1
0
1
1
1.5
1010
225°
0
1
0
1
2
0.63
1011
247.5°
0
1
0
1
2
0.48
1100
270°
0
1
1
0
2
0.44
1101
292.5°
0
1
1
0
2
0.6
1110
315°
0
1
1
0
0.7
2
1111
337.5°
0
1
1
0
0.44
2
Simulation Results
43
3.3.1
Simulation Results of Building Blocks
Figure 3-10 shows gain, return loss and noise figure simulation results of LNA with different
temperature (-40°~85°). The gain is greater than 15 dB at 0.8~12 GHz. The input return loss is
less than -9 dB from 0.8 GHz to 12 GHz. The noise figure under room temperature is less than
4.6 dB. Figure 3-11 depicts the input P1dB simulation result which is -4.6 dBm.
Figure 3-10
Wideband LNA simulation results: gain, return loss and NF
VGA simulation results are shown in Figure 3-12, Figure 3-13, and Figure 3-14. The gain of
VGA is better than 3.5 dB over 0.8~12GHz, and gain variation over temperature is small, 2.2 dB
maximum at 0.8 GHz. Gain control range is over 20 dB for whole frequency band, shown in
Figure 3-13. Phase variation over all 16 gain control states is less than 3.6°. It can be seen from
Figure 3-14, gain starts to saturate at vin=85 mV (peak value).
44
Figure 3-11
Figure 3-12
Wideband LNA simulation results: input P1dB
Wideband differential VGA simulation results: gain
45
Figure 3-13
Wideband differential VGA simulation results: gain range and phase variation
over gain states
Figure 3-14
Wideband VGA simulation results: linearity
46
3.3.2
Simulation Results of System
The layout of 8 channel L/S/C/X band phased-array receiver is shown in Figure 3-15. The
size of layout is 2.4 mm X 4.8 mm. The power consumption is 1000 mW.
Figure 3-15
Layout of L/S/C/X phased-array receiver
Figure 3-16 shows all 4 channels’ simulated gain. The gain is greater than 21.8 dB from 0.8
GHz to 12 GHz. Its 3 dB bandwidth is 10.2 GHz, from 1.1 GHz to 11.3 GHz, achieving over 164%
bandwidth. Also, the gain imbalance is very small, less than .18 dB between channels. Figure
3-17 shows the phase imbalance between channels. It is less than 1.3° over whole frequency
band.
47
Figure 3-16
Figure 3-17
Simulated four channels’ gain
Simulated four channels’ phase response
Figure 3-18 and Figure 3-19 show the gain control and phase control capabilities. In Figure
3-18, the receiver can achieve over 20 dB gain control while still maintain similar phase response.
48
The phase variation is less than 3.5°. The phase error is less than ±5°, and gain variation over
phase states is less than ±2.9 dB, shown in Figure 3-19.
Figure 3-18
Simulated gain control range and phase variation over gain states
Figure 3-19
Simulated gain variation over phase stages and all 16 phase states
49
3.4
Summary
An ultra-wideband eight-channel phased-array receiver in a 0.18-µm SiGe BiCMOS
technology has been demonstrated in simulation at 0.8 GHz to 12 GHz. Simulated results show
one decade frequency bandwidth is achieved, from 1.1 GHz to 11.3 GHz. Also the receiver
shows excellent channel imbalance in terms of gain and phase due to differential structure.
50
4
4.1
K-BAND PHASED-ARRAY RECEIVER
System Architecture
A K-band phased-array receiver is also developed for satellite communication. The system
structure is same with L/S/C/X band phased-array receiver, shown in Figure 3-1. In X-band
phased-array design, asymmetry of ground connection between channels cause amplitude and
phase imbalance due to asymmetry ground pads location although ground parasictics to each
separate channel are tuned to get minimum value. In L/S/C/X band receiver, differential
structures are adopted to minimize ground parasitics effect at the cost of chip area and power
consumption. While in K-band design, the ground parasitics, which is simulate in X-band design,
will kill the gain of amplifier as frequency is two times higher. Differential structures will lead to
more power consumption and occupy more chip area. Therefore, a new technology reducing
ground parasitics significantly will be used in this K-band phased-array design.
The Jazz SBC18 H3D process provides a low parasitic inductance ground by using deep
silicon via (DSV) [36] [37]. The inductance of the DSV is approximate 5pH providing a ground
path in amplifier with literally no parasitic inductance [37]. The DSV is a tungsten filled plug
connecting the lowest metal layer to a highly doped P++ silicon substrate.
Figure 4-1
DSV in SBC18 H3D process [37]
51
4.2
Building Block Design
4.2.1
K-band LNA
In [28], the author developed a general LNA design procedure for simultaneous noise and
power matching. In this design methodology, the transistor size is chosen for optimum current
density to get minimum noise figure, then is scaled to make input optimum input noise resistance
to be 50 Ω. The degeneration inductor is used to increase input resistance to 50 Ω, and a base
inductor resonates the input reactance. However, as frequency goes higher, the base-collector
capacitance, Cµ , will introduce some deviation to the assumptions that guarantee above design
methodology. For example, the minimum noise figure is a function of transistor’s size (emitter
length) at optimal current density. When scaling the transistor to get 50 Ω, its optimum noise
figure current density will also change. Also the degeneration inductor changes the optimal noise
resistance (Ropt).
Figure 4-2
Schematic of K-band LNA
52
A new design procedure for simultaneous noise and input power matching is developed
considering base-collector capacitance (Cµ) in [38]. The Cµ effect can expressed with a shunt
capacitance (CM) at the base node using Miller-effect, which can incorporated in input matching
design. Figure 4-2 shows the schematic of K-band LNA which consists of two stages. Cascode
stage is used in the first stage in order to improve isolation. Common emitter are optimize for the
gain in the second stage. The DSVs providing excellent ground connection (5 pH) are used in the
first and second emitter nodes. Degeneration inductor LE1 is 100 pH, which is realized by
meander line to save chip area and improve quality factor. The input transistor Q1 is 20 µm, at
collector current 4.2 mA, leading to 49 fF base-collector capacitance. According the CM equation
in [38], shown in (4-1), the Cµ can be expressed as a shunt resistor of 40 Ω and a shunt
capacitance of 59.3 fF, which are significant that cannot be neglect.
ω 2 g m LE Cµ
2 + (ω g m LE ) 2
jωCM =
+ jωCµ
1 + (ω g m LE ) 2
1 + (ω g m LE ) 2
(4-1)
This shunt RC needs to be incorporated into input matching network to get better input return
loss. LE2 is used to improve output linearity to get larger than 0 dBm output power. Resistor RC2
is used to improve output match and stability.
4.2.2
K-band VGA
K-band VGA, shown in Figure 4-3, has same structure with the one in X-band design. It has
4 bit gain control instead of 3 bit. The sizes of transistors Q1, Q2, Q3 and Q4 are binary scaled,
which are 1.5 µm, 3 µm, 6 µm, and 12 µm. The degeneration resistors, R1, R2, R3 and R4, are
500 Ω, 250 Ω, 125 Ω, and 62.5 Ω. The size ratio between Q1 and Q0 determines the gain range.
However, the final ratio needs to be tuned to get enough gain control range. The size of Q0 is
1.65 µm. The collector current of Q1 is biased at low gain region, 200 µA, to save power as well
53
as improve linearity. Thus, the second stage is biased at large current, 8.5 mA, to boost up gain
in VGA. LE2 helps to improve linearity, and inter-stage matching, LC1 and C2, are tuned to
compromise gain and linearity. LI is the input matching component, and RI is Q degeneration
resistor to increase bandwidth of input matching. Inductor LC2 along with resistor RC2 serve as
output matching components.
In [39], the author proposed a method to reduce phase variation by terminating the base of
cascode-stage with a shunt capacitor of an optimum value. An optimum capacitor of 1.1 pF is
added to the each base of cascode-stage to reduce phase variation over gain control.
Vdd
CD2
RB
LC1
LC2
D4
D3
D2
D4
D3
D2
D1
Q4A
Q2A
Q3B
Q3A
Q4B
Q2B
D1
Q1B
Q1A
Q00
RC2
C2
C3
C1
Q5
Q4
Q3
Q2
Q1
Q0
CD1
LI
RI
R4
R3
DSV
R1
DSV
Figure 4-3
4.2.3
R2
R0
LE2
DSV
Schematic of K-band VGA
K-band Low Insertion Loss and wideband Phase Shifter
In X-band receiver design, high performance PIN diodes [25] are used as switches in phase
shifter. But their performance gets poor as frequency goes higher. The insertion loss is around 2
dB, and isolation is 10 dB at 20 GHz. CMOS switch design above 20 GHz is challenging due to
54
its high insertion loss and low isolation. The main limitation of CMOS switches is the junction
diodes associated with source/drain nodes to substrate (Figure 4-4), which allow more signal
leakage from signal path to the substrate especially when operating frequency is high, such as in
K-band.
Figure 4-4
Schematic of NMOS switch
Figure 4-5 shows the conventional switched LC phase shifter. A Π-type low pass filter is
chosen in the phase shifter. CP is equivalent tuned-off capacitance of transistor M2. LP is used to
resonate with CP at operating frequency to isolate the signal path from ground. Figure 4-5 (b) and
Figure 4-5 (C) show the equivalent circuit when control voltage VC is high and low assuming
NMOS switched are ideal. However, on-state channel resistance of non-ideal NMOS switches
will increase insertion loss, and capacitance between source and drain due to Cgs and Cgd will
degrade the isolation. In order to decrease insertion loss as well as improve power handling
capability of CMOS switches, the resistance between source/drain nodes to substrate is often
increase. In [40], the authors bias the body with a large resistor. However, at frequency higher
than 20 GHz, this will lead to a poor isolation between source and drain due to coupling through
junction diodes.
55
Figure 4-5
Conventional switched LC phase shifter and its simplified small-signal circuit
model of ON and OFF states
Since the reverse isolation of NMOS switches gets worse as frequency goes high and
transistor size gets large, the equivalent turned-off capacitance can be utilized in low pass filter
for the off state. Figure 4-6 shows the proposed switched LC phase shifter which uses switches
turned-off capacitance as shunt capacitor in low pass filter. Thus, the transistor size can be
increased to get desire capacitance in low pass filter, while at same time, the insertion loss is
improved.
There is another benefit of the proposed switched low pass filter. The input impedance of
Figure 4-5 (b) can be calculated as follow:
s 2 LP (CP + 2C1 ) + 1
Z in =
2 sC1 ( s 2 LP CP + 1)
56
(4-2)
where s = jω .
From above equation, the series resonate point can be determined as follow:
1
ωsrsn =
LP (CP + 2C1 )
(4-3)
In conventional switched LC phase shifter, LP needs to resonate with CP at the operating
frequency to isolate signal path from ground. Therefore,
1
LP CP
ωo =
(4-4)
Also in order to get wide flat phase delay response, CP has the following relationship
with C1, [41]
CP = 2C1
(4-5)
By using equation (4-3) and (4-5), we can obtain the following equation,
ωsrsn =
ωo
2
(4-6)
Therefore, the parasitic series resonate point in conventional structure is close to the
operating frequency which will degrade the performance greatly. It produces a trough in
insertion loss response. While in proposed structure, the equivalent circuit when switch is on,
shown in Figure 4-6 (b), does not have this series resonate point, thus lead to broad-band
characteristic.
Figure 4-7 shows the complete 4-bit phase shifter. The 22.5°, 45°, and 90° use the proposed
switched LC phase shifter, and the 180° used high-pass/low-pass structure. As it can be seen, all
the ground is connected to the backside metal of chip through DSV.
57
Figure 4-6 Proposed switched LC phase shifter and its simplified small-signal circuit model
of ON and OFF states
Figure 4-7
Schematic of K-band 4-bit phase shifter
58
4.3
Simulation Results
4.3.1
Simulation Results of Building Blocks
Figure 4-8 shows gain, return loss and noise figure simulation results of K-band LNA. The
gain is greater than 16.5 dB at 17~23 GHz. The gain is peaked at low frequency band to
compensate high frequency band gain peak of VGA. The input and output return loss is less than
-10 dB from 17 GHz to 23 GHz. The noise figure under room temperature is less than 2.84 dB.
Figure 4-9 depicts stability factor of K-band LNA with corner and temperature variation. The
simulated output P1dB is 4.6 dBm.
Figure 4-8
K-band LNA simulation results: gain, return loss and NF
The simulated VGA exhibits 21.8 dB gain control range over 4-bit control states at 20 GHz.
(see Figure 4-10). The phase response varies 16° over all the gain states, and however, it only
changes less than 3.4° from 0010 state to 1111 state, where its gain varies 14 dB, which can be
used to adjust RMS gain error in phase shifter with slight degradation of RMS phase error.
Figure 4-11 shows input and output return loss over 16 gain state. They are all below -10 dB.
59
Figure 4-12 shows the input P1dB simulation results for different gain state. It is -3.5 dBm at
highest gain setting, and 1 dBm at lowest gain setting.
Figure 4-9
Figure 4-10
K-band LNA simulation results: stability for corner and temperature
K-band VGA simulation results: gain range and phase variation over gain
states
60
Figure 4-11
K-band VGA simulation results: input and output return loss
2
Input P1dB (dBm)
1
0
-1
-2
-3
-4
0
2
4
6
8
10
12
14
Digital State
Figure 4-12
K-band VGA simulation results: Input P1dB
61
The simulated input and output return loss of K-band phase shifter are all below -10 dB from
17 GHz to 23 GHz, shown in Figure 4-13. The simulated insertion loss is better than 11.2 dB at
17-23 GHz. The maximum gain variation is 5.47 dB at 17 GHz. The simulated insertion phase
responses show very linear characteristic at 17-23 GHz. The simulated RMS gain error is less
than 1.3 dB for all 4-bit phase state at 17-23 GHz. [Figure 4-14]. It can be seen that RMS phase
error is less than 4.1° at 17-23 GHz, achieving 6-bit accuracy. Simulated results show the phase
shifter achieving 30% fractional bandwidth.
Figure 4-13 K-band phase shifter simulation results: Input, output return loss, phase response
and gain
62
1.4
RMS gain error
RMS phase error
4
1.2
3
1.0
2
0.8
RMS Gain Error (dB)
RMS Phase Error (degree)
5
1
0.6
0
17
18
19
20
21
22
23
Frequency (GHz)
Figure 4-14
4.3.2
Simulated RMS gain and phase error of K-band phase shifter
Simulation Results of System
The layout of 4 channel K-band phased-array receiver is shown in Figure 3-15. The size of
layout is 2.03 mm X 2.45 mm. The power consumption is 180 mW for 4 channels. Figure 4-16
shows one channel simulated gain and phase variation over gain states. The gain range is greater
than 20 dB at 17-23 GHz. The maximum gain is 18.2 dB at 20 GHz. Phase variations over gain
states is less than 4° at 20 GHz over 14 dB gain control range providing relative constant phase
response while minimizing amplitude variation. Figure 4-17 depicts the phase response and gain
variation over phase states for one channel. It can be seen gain variation is less than 3.6 dB over
all 16 phase states. The RMS gain and phase error are similar to the results in Figure 4-14.
63
Figure 4-15
Figure 4-16
Layout of K-band phased-array receiver
Simulated one channel gain states and phase variation
64
Figure 4-17
Figure 4-18
Simulated phase states and gain variation
Simulated gain and phase imbalance
The simulated NF is 2.82 dB at 20 GHz, and less than 3.5 dB from 17 GHz to 23 GHz. The
simulate output P1dB is -8.5 dBm and output IP3 is -2.2 dBm. Figure 4-18 shows the simulated
amplitude and phase imbalance between channels. It is very small due to symmetry layouts and
DSV providing very small inductance in ground connection. Figure 4-19 shows the Monte Carlo
65
simulation results of one channel gain. The mean value of gain is 18.3 dB at 20 GHz, and
standard deviation is 1.37 dB.
Figure 4-19
4.4
Monte Carlo simulation results (1000 sample) for one channel
Summary
A low phase error, wideband K-band four-channel phased-array receiver in a 0.18-µm SiGe
BiCMOS technology has been simulated at 17-23 GHz. The receiver consists of LNAs, 4-bit
VGA, and 4-bit passive phase shifters. A new phase shifter structure is proposed to increase
bandwidth and low down insertion loss. Simulated results show less than 4.1° RMS phase error
and less than 1.3 dB RMS gain error over 30% fractional bandwidth by using the proposed
floating bulk new phase shifter structure. The one channel can achieve 18.2 dB gain, 2.82 dB NF,
and -8.5 dBm output P1dB at 20 GHz with 45 mW power consumption.
66
5
CONCLUSION
Phased-array systems have been used since the 1950’s to achieve fast beam scanning and
electronic beam control. In this dissertation, the RF phases shifting architecture for phased-array
receiver is exploited in L/S/C/X/Ku/K band. Phase shifter is essential and the most challenging
element in phased-array system as used to compensate for the time delay between antenna
elements. The passive phases shifting approach along with active method are both studies aiming
at low insertion loss, wideband, low RMS gain, and low RMS phase error according to system
specifications.
In X-band phased-array receiver, high performance PIN diode switches used in phase shifters
ensure low phase error for all 3-bit phase states. The bridged-T type phase shifter with center-tap
inductor is analyzed using an equivalent-circuit model to obtain analytical form of component
values. The 9.5-11.5 GHz receiver achieves the following on-wafer measurement results: over 10
dB measured average gain, less than 5 dB NF (@max. gain and ref. phase state) per channel. The
RMS gain error is less than 0.67 dB and the RMS phase error is less than 5° with VGA control at
9.5-11.5 GHz for all phase states. A gain control of 12 dB is also achieved with a phase variation
of 8.2°. The RMS phase mismatch and RMS gain mismatch among the four channels are less
than 3.5° and 1.5 dB, respectively, for all 8 phase states, over 9.5-11.5 GHz. The packaged chip
suffers gain loss and rapid gain rolloff due to package ground parasitics. After including package
ground parasitics, the simulation results match with board measured results.
In L/S/C/X band phased-array receiver, vector modulator is adopted for the phase shifter in
order to achieve wide band operation. Differential structures are used through receiver chain
except that the input and output are single-ended 50 Ω for testing purpose. Therefore, the
67
cumbersome ground parasitic problems are mitigated thanks to the symmetry layouts. The
receiver achieves 10.2 GHz 3 dB bandwidth, which is from 1.1 GHz to 11.3 GHz, one decade
frequency bandwidth.
A new phase shifter using floating body and parasitic resonance eliminating techniques is
proposed in order to lower insertion loss and increase bandwidth. The simulated RMS gain error
is less than 1.3 dB, and RMS phase error is less than 4.1° for all 4-bit at 17-23 GHz, achieving 6bit accuracy. Simulated results show the phase shifter achieving 30% fractional bandwidth. The
simulated one channel can achieve 18.2 dB gain, 2.82 dB NF, and -8.5 dBm output P1dB at 20
GHz with 45 mW power consumption.
68
6
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