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Embedded substrate noise measurement formixed-signal/radio frequency/microwave integrated circuits

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EMBEDDED SUBSTRATE NOISE MEASUREMENT FOR MIXED-SIGNAL/RADIO
FREQUENCY/MICROWAVE INTEGRATED CIRCUITS
By
MING HE
A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL
OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT
OF THE REQUIREMENTS FOR THE DEGREE OF
DOCTOR OF PHILOSOPHY
UNIVERSITY OF FLORIDA
2006
1
3347133
2009
3347133
Copyright 2006
by
Ming He
2
ACKNOWLEDGMENTS
I would like to begin by thanking my advisors, Professors William R. Eisenstadt and
Robert M. Fox, for their guidance and support throughout the course of this work. Without their
support and guidance, my exploration in this research could not succeed. I also would like to
thank the members of my supervisory committee --Professors John G. Harris and Oscar D.
Crisalle -- for their guidance and interest in this work. I also thank Marcy Lee for her countless
help on ordering equipment.
Much appreciation goes to the Semiconductor Research Corporation (SRC) and National
Science Foundation (NSF) for funding this work, as well as IBM and Mosis for providing test
chips. I would also like to thank fellow students Tao Zhang, Xueqing Wang, Du Chen, Xuelin
Wu, Xiaoqing Zhou, Qizhang Yin, Yu Su, Changhua Cao, Yanping Ding, Chikuang Yu, Haifeng
Xu, Dongming Xu, Xiuge Yang, Xuege Wang, Sanghoon Choi, Inchang Seo, Jangsup Yoon,
Okjune Jeon, Kooho Jung, Jongshick Ahn and Sudeep Puligundla for their helpful discussions,
advice and friendship.
Finally, I am grateful to my wife, Xiaoxiang Gong. Her love and dedication have been
essential to the fulfillment of this work. Also, I would like to thank my parents and my
grandmother for their love and encouragement throughout the years.
3
TABLE OF CONTENTS
page
ACKNOWLEDGMENTS ...............................................................................................................3
LIST OF TABLES...........................................................................................................................7
LIST OF FIGURES .........................................................................................................................8
ABSTRACT...................................................................................................................................13
CHAPTER
1
INTRODUCTION ..................................................................................................................15
1.1 Background of Radio Frequency/Microwave Test...........................................................15
1.2 Future of Testing: Embedded Test ...................................................................................18
1.3 Challenges and Approaches in Embedded RF/Microwave Test ......................................20
1.3.1 Direct Measurement of Specifications ...................................................................21
1.3.2 Alternate Testing Methods .....................................................................................22
1.3.3 Summary.................................................................................................................24
1.4 Organization of the Dissertation.......................................................................................25
2
EMBEDDED SUBSTRATE NOISE MEASUREMENT ......................................................27
2.1 Introduction.......................................................................................................................27
2.2 Substrate Noise Coupling Mechanism..............................................................................28
2.3 Substrate Noise Reduction Techniques ............................................................................32
2.3.1 Substrate Engineering.............................................................................................33
2.3.2 Device Isolation Methods.......................................................................................33
2.3.3 Grounding Effects ..................................................................................................37
2.3.4 Noise-Reduction-Oriented Circuit Design Techniques..........................................38
2.4 Substrate Noise Coupling Modeling and Extraction Strategies .......................................39
2.5 Substrate Noise Measurement ..........................................................................................42
2.5.1 DC Measurements ..................................................................................................42
2.5.2 Direct Probing Measurement..................................................................................42
2.5.3 Embedded measurement techniques.......................................................................43
2.6 Proposed Embedded Substrate Noise Measurement ........................................................45
2.6.1 Potential Benefits....................................................................................................46
2.6.2 Design Issues ..........................................................................................................46
2.7 Research Goals .................................................................................................................47
3
AUTOMATIC GAIN CONTROL BASED MEASUREMENT SYSTEM ...........................49
3.1 Introduction.......................................................................................................................49
3.2 Theory of AGC .................................................................................................................49
3.3 Circuit Design...................................................................................................................53
4
3.3.1 Variable Gain Amplifier.........................................................................................54
3.3.2 Peak Detector..........................................................................................................57
3.3.3 Loop Filter and Gm-1 Block ..................................................................................59
3.3.4 On-chip Bias and Voltage Reference Circuits........................................................60
3.3.5 T-switch..................................................................................................................60
3.3.6 Overall System with Embedded Test Points ..........................................................61
3.4 Simulation of AGC Design...............................................................................................62
3.5 Measurement Results........................................................................................................65
3.6 Conclusions.......................................................................................................................67
4
LOGARITHMIC AMPLIFIER DETECTOR ........................................................................68
4.1 Introduction.......................................................................................................................68
4.2 Review of Various Logarithmic Amplifier Techniques ...................................................68
4.3 Logarithmic Amplifier Circuit Design .............................................................................71
4.3.1 Limiter Design.................................................................................................74
4.3.2 Rectifier Design...............................................................................................76
4.3.3 DC Offset Cancellation ...................................................................................80
4.4 Simulation Results and Analysis ......................................................................................81
4.5 Conclusions.......................................................................................................................89
5
DOWN-CONVERSION BASED MEASUREMENT SYSTEM ..........................................90
5.1 Introduction.......................................................................................................................90
5.2 Down-Conversion Mixer ..................................................................................................91
5.2.1 Introduction ............................................................................................................92
5.2.2 Circuit Design.........................................................................................................96
5.3 Verification of Mixer Design............................................................................................96
5.3.1 Test Setup and Calibration ..............................................................................97
5.3.2 Measurement Results ......................................................................................99
5.4 Summary and Conclusions .............................................................................................101
6
MODELING AND VERIFICATION METHODOLOGY FOR SUBSTRATE
COUPLING EFFECTS ........................................................................................................102
6.1 Test Structures for Substrate Coupling Investigation.....................................................102
6.2 Substrate Model Extraction ............................................................................................105
6.3 Measurement Results......................................................................................................109
6.4 Discussions .....................................................................................................................111
6.4.1 Effect of Measurement Errors on Model Extraction ............................................111
6.4.2 Multiple-contact Coupling Problem .....................................................................112
6.5 Conclusions.....................................................................................................................114
7
SUMMARY AND FUTURE WORK ..................................................................................115
7.1 Summary.........................................................................................................................115
7.2 Future Work....................................................................................................................117
5
APPENDIX
A
ERROR ANALYSIS FOR PSEUDO-LOGARITHMIC AMPLIFICATION .....................121
B
CALIBRATION FOR ONE-PORT MEASUREMENT SYSTEM .....................................125
C
EMBEDDED SUBSTRATE COUPLING MEASUREMENT AND SEMI-PHYSICAL
MACROMODEL EXTRACTION.......................................................................................129
C.1 Embedded Substrate Coupling Measurement ................................................................129
C.2 Semi-physical Macromodel ...........................................................................................132
LIST OF REFERENCES.............................................................................................................139
BIOGRAPHICAL SKETCH .......................................................................................................146
6
LIST OF TABLES
Table
page
1-1
Typical RF and IF measurements made on a RF device ...................................................17
4-1
Logarithmic amplifier output variations under different conditions (10mV 100MHz
sinusoid input)....................................................................................................................88
4-2
Logarithmic amplifier output variations under different conditions (100mV 100MHz
sinusoid input)....................................................................................................................88
C-1
Typical values of R12 as a function of separation distance ..............................................135
C-2
Typical values of C12 as a function of separation distance ..............................................135
C-3
|G12| variations under different frequencies (separation distance = 220μm) ...................138
C-4
|G12| variations under different frequencies (separation distance = 1200μm) .................138
7
LIST OF FIGURES
Figure
page
1-1
System integration of core semiconductor technologies ...................................................15
1-2
The evolution from (a) conventional test with high-cost ATE to (b) embedded test
with low-cost ATE.............................................................................................................19
1-3
Variation in process or circuit parameter and its effect on circuit specification and
test ......................................................................................................................................23
2-1
Overview of the substrate noise coupling problem............................................................27
2-2
Body effect represented by a dependent current source ....................................................30
2-3
Commercial substrate doping profiles: (a) high-resistivity substrate, (b) lowresistivity substrate.............................................................................................................32
2-4
The effect of guard rings with different substrate doping profiles ....................................34
2-5
Guard ring isolation versus frequency as a function of width ...........................................35
2-6
Guard ring isolation versus frequency as a function of package inductance.....................35
2-7
Triple-well isolation strategy .............................................................................................36
2-8
Deep trench isolation .........................................................................................................37
2-9
Separating the LNA and mixer grounds increased isolation .............................................37
2-10
Floor planning for substrate coupling reduction................................................................38
2-11
Typical verification flow for substrate noise analysis .......................................................39
2-12
Two-port setup for high-frequency substrate coupling measurement ...............................43
2-13
Measurement setup of substrate noise coupling ................................................................44
2-14
Embedded substrate noise measurement ...........................................................................45
3-1
AGC circuit block diagram and linearized loop model .....................................................50
3-2
Constant settling time AGC with arbitrary VGA gain and Gm control characteristic. ......52
3-3
VGA cell schematic ...........................................................................................................54
3-4
DC offset cancellation for VGA causing multiple feedback loops....................................56
8
3-5
Start-up circuit solves the multiple operating point problem in VGA...............................57
3-6
Half-wave peak detector and full-wave peak detector.......................................................58
3-7
Loop filter ..........................................................................................................................59
3-8
Differential difference amplifier (DDA) (CMFB circuit not shown) ................................59
3-9
Wide-swing constant-gm bias circuit..................................................................................60
3-10
Transmission gate and T-switch ........................................................................................61
3-11
Overall AGC system with embedded test points and embedded test point
implementation ..................................................................................................................62
3-12
Gain tuning curve of VGA blocks .....................................................................................63
3-13
Frequency response of two-stage VGA .............................................................................63
3-14
Linearity of two-stage VGA in THD (%) versus input signal strength .............................64
3-15
Input versus output characteristic of peak detector............................................................64
3-16
Transient response of AGC to a 10MHz sinusoidal input with varying amplitude...........65
3-17
Microphotograph of the AGC system................................................................................66
3-18
Bias circuit with external resistor connection....................................................................67
4-1
Transconductance feedback logarithmic amplifiers with (a) diode or (b) transistor .........68
4-2
Simplified block diagram of successive-detection logarithmic amplifier .........................70
4-3
Signal flow in a successive-detection logarithmic amplifier .............................................70
4-4
Normalized gain, bandwidth and gain-bandwidth product for a single stage versus
the number of stages for overall gain of 80dB...................................................................73
4-5
Maximum input error versus the number of stages for overall gain of 80dB....................74
4-6
Limiting amplifiers ............................................................................................................75
4-7
Limiting amplifier using triple-well NMOS loads.............................................................76
4-8
Gilbert cell based rectifier..................................................................................................77
4-9
Full-wave rectifier with unbalanced source-coupled pairs ................................................77
9
4-10
Signal flow in a successive-detection logarithmic amplifier with pseudo-logarithmic
rectifiers .............................................................................................................................79
4-11
Simulated DC transfer curve for full-wave pseudo-logarithmic rectifier and ideal
VLOG curve versus input voltage ........................................................................................79
4-12
DC offset cancellation techniques .....................................................................................80
4-13
Simulated AC response of (a) single-stage and (b) 9-stage limiting amplifier..................81
4-14
Simulated RSSI output and input error versus input voltage.............................................82
4-15
Output error versus input voltage ......................................................................................83
4-16
Output error versus temperature ........................................................................................83
4-17
Logarithmic amplifier output distributions with mismatch, process variation and
mismatch plus process variation (10mV 100MHz sinusoid input)....................................86
4-18
Logarithmic amplifier output distributions with mismatch, process variation and
mismatch plus process variation (100mV 100MHz sinusoid input)..................................87
4-19
Logarithmic amplifier output voltages from Cadence simulation versus theoretical
values .................................................................................................................................89
5-1
Down-conversion based substrate noise measurement......................................................90
5-2
Multiplication based mixer and its signals spectrum.........................................................92
5-3
Simplified mixer ................................................................................................................92
5-4
Single-balanced and double-balanced mixers....................................................................93
5-5
Down-conversion mixer schematic....................................................................................96
5-6
Microphotograph of the down-conversion mixer ..............................................................97
5-7
Mixer measurement setup ..................................................................................................97
5-8
External buffer ...................................................................................................................98
5-9
Mixer Reflection Coefficient (S11) at RF Port................................................................100
5-10
Mixer output linearity versus input signal level ..............................................................101
6-1
Test structures for embedded substrate noise measurement ............................................103
6-2
Microphotograph of the test chip containing the substrate noise test structure...............104
10
6-3
Measurement setup for substrate coupling investigation.................................................104
6-4
HFSS model of test structure ...........................................................................................106
6-5
Equivalent circuit of the test structure .............................................................................107
6-6
Semi-physical equivalent circuit for G12..........................................................................108
6-7
Comparison of measurement and simulation results of isolation for different
separation distances between two substrate contacts.......................................................110
6-8
A two-dimension view of isolation versus separation distances and frequencies ...........110
6-9
Comparison of measurement and simulation results of |G12| for different separation
distances between two substrate contacts ........................................................................111
6-10
Errors in|G12| because of random errors in measurement ...............................................112
6-11
Substrate noise coupling between multiple contacts .......................................................113
6-12
Substrate impedance network between multiple contacts ...............................................113
7-1
Improved down-conversion based substrate noise measurement scheme .......................117
7-2
Logarithmic amplifier output versus input voltage..........................................................118
7-3
Output error versus input voltage ....................................................................................118
7-4
Example of down-conversion based embedded substrate noise measurement................119
A-1
Piecewise linear approximation to a logarithmic curve...................................................121
A-2
Signal flow of a successive-detection logarithmic amplifier...........................................122
A-3
Characteristics of an N-stage pseudo-logarithmic amplifier ...........................................123
A-4
Maximum input error as a function of single stage gain .................................................124
B-1
S-parameter measurement with calibration setting the reference plane ..........................125
B-2
Flow graph of the hypothetical error adapter...................................................................126
C-1
Measurement setup for embedded substrate coupling detection .....................................129
C-2
Equivalent circuit of the test structure .............................................................................130
C-3
De-embedding bondpad and interconnection ..................................................................131
C-4
Semi-physical equivalent circuit for G12..........................................................................133
11
C-5
R12 versus different separation distances between two substrate contacts ......................134
C-6
C12 versus different separation distances between two substrate contacts ......................134
C-7
|G12| distributions at different frequencies (separation distance = 220μm) .....................136
C-8
|G12| distributions at different frequencies (separation distance = 1200μm) ...................137
12
Abstract of Dissertation Presented to the Graduate School
of the University of Florida in Partial Fulfillment of the
Requirements for the Degree of Doctor of Philosophy
EMBEDDED SUBSTRATE NOISE MEASUREMENT FOR MIXED-SIGNAL/RADIO
FREQUENCY/MICROWAVE INTEGRATED CIRCUITS
By
Ming He
December 2006
Chair: William R. Eisenstadt
Cochair: Robert M. Fox
Major Department: Electrical and Computer Engineering
Due to the ever-growing demand for IC production cost reduction, there are more and
more system-on-chip (SoC) designs that require the integration of analog/radio frequency
(RF)/microwave and digital circuits on the same die arise and which pose challenges to
RF/microwave testing.
Traditional RF/microwave testing that relies on expensive automated test equipment
(ATE) systems cannot keep up with the pace of the growing complexity of the testing process
without increasing test cost and is becoming one of the major obstacles for overall IC production
cost reduction. Embedded testing is a potential solution to answer those challenges. The basic
idea of embedded testing is to move high-speed and high-bandwidth portions of expensive ATE
system onto the IC device-under-test (DUT) by additional design-for-test (DFT) circuitry, thus
reducing the requirements and eventually the cost of external ATE system.
SoC designs suffer from substrate noise coupling due to the finite isolation provided by the
semiconductor substrate. The study of substrate coupling effects is especially challenging in
terms of circuit design and modeling.
13
The proposed embedded substrate noise measurement system consists of an off-chip
broadband signal source and example test circuits integrated with the DUT. The signal source
acts as a noise generator and injects well-controlled signals into the substrate, and then the
embedded test circuit will extract useful information from the response of the detector and report
the data as baseband signals; the baseband signals are delivered off-chip to an external tester.
First, a low-frequency, on-chip substrate noise measurement test vehicle is designed and
used to demonstrate the embedded system feasibility. Next, a system capable of measuring
substrate noise coupling over a very wide frequency span up to the millimeter wave range is
demonstrated. Finally, an application of the embedded measurement system is presented and a
semi-physical macromodel is extracted based on experimental data.
14
CHAPTER 1
INTRODUCTION
The growth of the personal communication market in recent years has led to a
relentless push for IC cost reduction, which has quickly driven cost-sensitive radio
frequency integrated circuit (RFIC) integration levels from single-function parts in 1995
to full front ends and simple handset functions on a chip today. In the future, the demand
for more system functionality (Figure1-1) on a single die (system-on-chip, SoC) or in a
single package (system-in-package, SiP) will increasingly blur the lines between
traditional digital, analog, RF/microwave and mixed-signal devices. This trend will drive
test equipment toward a highly configurable, single platform solution that can test any
application.
Figure1-1. System integration of core semiconductor technologies
1.1 Background of Radio Frequency/Microwave Test
Traditionally, RF design and silicon manufacturing have contributed the highest
overall IC cost component, thus the test cost received little attention. Improvements in
manufacturing technology, and relaxed performance requirements of some application
15
domains, lead to high-yield low-area design processes, and the cost of manufacturing RF
dies has reduced appreciably. However, the test cost has not reduced at the same rate, and
indeed has been an increasing percentage of the overall IC cost.
The first high-volume microwave chip tests were relatively simple, including the
tests of switches, amplifiers, mixers, LNA/mixer combinations, etc., and they were
typically performed after ICs were packaged in cheap small outline integrated circuit
(SOIC) packages since package scrap costs were very low. Wafer-level tests were used to
prune away catastrophically defective dies before packaging and the RF path was
completely by-passed in wafer-level test. As the IC complexities have increased, the
yields are lower, the package costs become an appreciable component of the overall cost,
and the need for wafer-level RF path test before packaging has arisen. Since 1999, there
has been a steady increase in the number of high-volume RFICs that are tested on-wafer
instead of, or in addition to, being tested at package level. In addition, an increasing
number of bare dies are being used in bump-bonded circuitry.
In the past 30 years, wafer probing above a GHz has progressed from impossible,
to a useful R&D tool, to a necessary production tool, and to a mainstream very largescale integration (VLSI) topic. With the development of high-performance and highfrequency on-wafer probes and probe stations, wafer-level test and characterization can
be performed before the ICs were diced and packaged. Current RFIC testing
methodologies require performance-based measurements (i.e., using external outside-thechip instruments), and the complexity of applications increases the number of instruments
in a given test system (Table 1-1) [1].
16
Table 1-1. Typical RF and IF measurements made on a RF device
AM-PM conversion (static)
Nth order intermodulation
x Two-tone IP3, IP5
Adjacent channel power
Complex demodulation
Phase noise/jitter (CW)
Digital input-threshold voltage
x Modulated
Digital output levels
Power (dBm)
x Output power
Efficiency (RF out/DC in)
x vs. bias voltage
Frequency
x CW
x vs. time (tune drift)
Gain or loss
Pulsed RF measurement
x vs. control voltage or digital state
x Frequency
x Power
Gain compression
x S-parameter
x Pout @ N dB, saturation
Harmonic distortion
x dBc
x SOI, TOI
Pulsed RF profile signal overshoot &
ringing
RF rise time (10% to 90%)
I/Q modulator imbalance (static)
x Amplitude & phase error
S-parameter
x Gain/loss isolation, match, VSWR,
gamma
I/Q modulator suppression
Spurious signals
@ known frequency, search
x Carrier & unwanted sideband
Isolation
Supply currents
x Enabled, sleep mode
Minimum detectable signal
Switching speed
x D digital input to D gain or D
Mixer conversion gain or loss
frequency
Mixer leakages
VCO frequency
x LOÆRF, LOÆIF, carrier feed
x vs. voltage
through
x Tune linearity
Noise Figure
x Tune range
x Tune sensitivity (dc-freq)
x vs. digital state
VSWR
Voltages
Notes: amplitude modulation (AM), phase modulation (PM), carrier wave (CW), decibel
(dB), in dB with respect to carrier (dBc), second order intercept (SOI), third order
intercept (TOI), in-phase/quadrature-phase (I/Q), local oscillator (LO), voltage standing
wave ratio (VSWR), 3rd intermodulation product (IP3), 5th intermodulation product
(IP5), dB below one milliwatt (dBm), voltage controlled oscillator (VCO).
Extremely complex, million-dollar automated test equipment (ATE) systems have
now become readily available from a variety of vendors that integrate all of these
17
functions and provide a much higher throughput capability than typical rack-and-stack
equipment. The number of RF ports varies from two, for a minimal system for power
amplifiers, to 20 or more for complex RFICs. All ATE systems provide DC power
supplies for powering and controlling the device-under-test (DUT) and measuring various
voltages and currents. As RF front-end chips start to integrate intermediate frequency (IF)
functions, mixed-signal subsystems are being added to ATE systems, which typically
provide analog signal stimuli, such as arbitrary waveform generators (AWGs). This trend
of increasing instrument numbers, complexity and performance is expected to continue.
Conventional analog/RF/microwave IC tests use ATE systems. However, the cost
associated with ATE systems has significant impact on total manufacturing test cost.
First, the complexity of the test systems needs to be matched to the complexity of the ICs
to be tested and generally the cost of the ATE system is proportional to the complexity of
the devices it can test. The increasing integration density of ICs nowadays will drive up
the cost of ATE systems and eventually the overall test cost. Also, the ATE system is
costly to operate and has a complicated test procedure development, which will make the
situation even worse. Alternative solutions must be found to reduce test cost.
1.2 Future of Testing: Embedded Test
There are three approaches in terms of test cost reduction: test less, test earlier or
test faster [2]. “Test less” reduces unnecessary or duplicated test steps in different test
phases (i.e., wafer test vs. package test). Wafer-level testing is a perfect example for “test
earlier”. Package scrap is saved by performing screening and RF path test before
packaging. The “test faster” strategy involves the use of test parallelism and/or highthroughput testers. For some product groups (e.g., memory), current wafer probe
technologies can handle parallel testing of 32 to 256 and more devices.
18
Embedded test is a potential and advanced solution that addresses the above listed
needs and an efficient way to reduce ATE capital expenditures.
(a) Conventional Test
(b) Embedded Test
Figure 1-2. The evolution from (a) conventional test with high-cost ATE to (b) embedded
test with low-cost ATE
Conventional test methods use external testers to generate test stimulus and the
DUT response is directly measured from the stimulus. High-bandwidth data transfer is
done at the operation speed of the DUT. The measurement results include the
transmission properties of the interconnection, such as wires, connectors, probe cards,
etc., and require interconnect uniformity (matched impedance throughout the signal
19
path). Extra effort and cost to decouple the response of the interconnection from the
actual response of the DUT are needed to ensure accurate measurement results.
The integration of embedded test circuitry into the DUTs results in a new on-chip
and off-chip distribution of test resources compared to the conventional test resource
partitioning, as shown in Figure 1-2. Embedded test integrates the capability of highspeed and high-bandwidth portions of the external ATE circuits directly into the DUTs.
With these embedded circuits (i.e., multiplexer/demultiplexer, signal generators,
samplers, converters, response compressors, etc.), high-speed test stimulus and response
signature generation functions can be customized per test application type, and on-chip
test data compression reduces ATE data logging requirements.
1.3 Challenges and Approaches in Embedded RF/Microwave Test
However, embedded test has to face the following major challenges before
becoming successful:
x
On-chip generation of high-quality and high-speed test signals using low-cost
hardware;
x
High-speed on-chip response acquisition followed by analysis or response
compaction.
The IEEE 1149.1 (JTAG) boundary scan standard [3] provides an effective means
for test access to internal modules of the DUT for testing static faults in digital ICs [4]. Its
JTAG counter part in mixed-signal testing, the IEEE 1149.4 standard [5], is seen in
various publications [6-7]. Although some improvements [8] have been shown to
overcome the low-bandwidth limit of boundary-scan test on RF pins, more research in
this area is needed.
Digital built-in-self-test (BIST) circuits usually return a simple pass/fail bit or a
multi-bit “signature” that allows the ATE testers to evaluate the quality of the device [9].
20
Since the DUT tests itself using BIST, a much less expensive ATE tester can be used.
Unfortunately, analog BIST technology has always lagged behind digital BIST because
of the required high accuracy of signals generated and measured on-chip.
Design-for-test (DFT) techniques have been introduced and are becoming an
industry-wide practice. DFT strategies generally fall into two categories: some methods
follow the tradition production test procedure and measure the specifications of the DUT
directly using dedicated circuits; while some other approaches evaluate DUT
performance indirectly.
1.3.1 Direct Measurement of Specifications
Traditional production test examines the functional specifications of analog/mixedsignal circuits by using the appropriate tester resources and using the same kind of test
stimuli and configuration with respect to which the specifications are defined [10] (i.e.,
gain for codec, multi-tone signal generator for distortion measurement, etc.). The
measurement procedures are consistent with the intuitive meaning of the module
behaviors, and it is easy to interpret the measurement results.
Various implementations of on-chip signal generators for testing analog/RF circuits
are reported in the literature [11-15]. Note that the on-chip microwave signal source in
[15] can generate pure sinewave and multi-tone signals above the GHz range, which
enables on-chip microwave test [16]. An on-chip spectrum analyzer using a direct
conversion technique with 8-bit resolution is reported in [17]. An on-chip
sampler/oscilloscope based on sub-sampling of periodic signals was proposed by P.
Larsson [18], and some of its applications can be found in [19-20]. These works show the
feasibility of using embedded test circuits for high-frequency and high-performance
21
analog/RF blocks measurement, even though the chip area overhead brought by the
additional circuitry might be a potential obstacle.
However, a direct measurement method might not be suitable for multiplespecification measurements. First, multiple specification measurements require different
kinds of resources, which will make the chip area overhead problem more severe. Also, if
the measurement of multiple specifications cannot be performed at the same time, overall
test time will be longer and overall manufacturing cost will go up.
1.3.2 Alternate Testing Methods
The concept of alternate test was proposed in [21-23] by A. Chatterjee. The basic
idea of alternate test is to relate DUT performance to process variations, and to perform
less costly additional tests instead of explicit measurements to evaluate DUT
performance. Similar to the direct measurement method, alternate test also applies a test
stimulus and measures DUT response. But the test stimuli have to be optimized so that
DUT specifications can be predicted accurately from alternate response.
As shown in Figure 1-3(a), after the measurement, feature extraction and mapping
have to be done to obtain corresponding DUT specifications. Figure 1-3(b) illustrates the
effect of variation of process parameters on the specification and the corresponding
measurement data. The variation in parameter space P (i.e., gate oxide thickness,
threshold voltage, temperature, etc.) affects the specification space S by a corresponding
sensitivity factor. Similarly, the variation in P also influences the measurement space M.
Given the parameter space P, any point in P can be mapped onto the specification space S
by fps and onto the measurement space M by fpm.
22
(a)
Process Parameter Space (P)
Measurement Space (M)
Distribution of a
measurement data
corresponding to
parameter perturbation
Distribution of a parameter
corresponding to the
process/netlist
f pm
f ps
f ms
Region of operation
of a “good” system
Distribution of a
specification due to
non-zero tolerance in
parameter value
Specification Space (S)
Nominal or design
value
(b)
Figure 1-3. Variation in process or circuit parameter and its effect on circuit specification
and test
Therefore the region of acceptance in specification space S has a corresponding
accepted region in process parameter space P, which in turn defines the accepted region
23
in M. Nonlinear statistical multivariate regression can be used to construct a mapping
function between M and S: fms. By mapping measurement data to specification through
fms and comparing with various specification thresholds, we can predict whether the DUT
is faulty or not.
The key issues of alternate test are to find a suitable transient test stimulus and to
predict circuit specifications accurately from alternate test responses. Several papers in
the literature reported applications of alternate test to op-amps, low-frequency filter
circuits [24], and even high-frequency RF modules [25].
But current methods require a large number of samples to validate an alternate test,
and more efficient statistical or analytical methods to verify fault coverage have to be
developed for proliferation of alternate tests. Also, built-in response acquisition in
alternate testing of RF circuits is difficult to complete and still in the development stage
[26].
1.3.3 Summary
Even though the above approaches (i.e., boundary scan, BIST, DFT) do not give
complete answers for the challenges of embedded test, it is still of interest to develop
embedded RF/microwave test circuits taking account the tradeoffs among the ATE tester
cost, product testability and chip area. Integration of a wider array of digital CMOS
circuits, mixed-signal and even optical/mechanical silicon together in future products will
continue to make embedded test attractive rather than to increase the platform complexity
of ATEs towards a “do all” platform, as many more critical RF/microwave nodes will be
unobservable and/or uncontrollable by today’s test techniques.
24
1.4 Organization of the Dissertation
This Ph.D. dissertation consists of seven chapters. An overview of the research is
given in this current chapter (Chapter 1), including the background of RF/microwave test,
motivation for embedded RFIC test, challenges and existing techniques for embedded
test.
Chapter 2 reviews some background knowledge on substrate noise coupling
analysis. Basic concepts of substrate noise coupling mechanism and reduction techniques
are described, and some features and trends of current substrate noise measurement are
presented. An embedded substrate noise measurement test scheme is then proposed.
Research goals and the scope of this work will be discussed.
Chapter 3 describes an AGC based low-frequency substrate noise measurement test
vehicle. A design based on analysis of conventional AGC loops is then presented.
Fundamentals of AGC operation are also reviewed in that chapter.
Chapter 4 presents the design and simulation of pseudo-logarithmic amplifier based
on successive-detection architecture. This amplifier can be used as a signal detector and
the limitations of it will be discussed.
A down-conversion mixer based high-frequency substrate noise measurement
system with very wide frequency bandwidth and dynamic range is presented in Chapter
5. The test setup and measurement results on a prototype chip demonstrate the
practicality of the circuit for on-chip embedded substrate noise test.
Chapter 6 shows the embedded substrate coupling measurement results and a semiphysical macromodel based on experimental data. Error analysis and application of this
model to multiple-contact coupling problem are also discussed.
25
A summary of research work discussed in this dissertation and suggestions for the
future work are presented in Chapter 7.
26
CHAPTER 2
EMBEDDED SUBSTRATE NOISE MEASUREMENT
2.1 Introduction
Driven by cost-constrained applications such as telecommunications, computing
and consumer/multimedia and facilitated by continuing miniaturization in the CMOS
VLSI technology, designers are given the opportunity to integrate multiple system
components (i.e., analog, digital, RF sections) onto a few chips or even on one single
multi-million transistor chip – a so-called System-on-chip (SoC). This pays dividends in
enhanced performance, as well as dramatically-reduced area, power, and most
importantly, the overall system cost. However, the integration of both analog/RF and
digital circuits on the same die also opens the door to a host of challenging noise coupling
effects which create mixed-signal signal integrity problems.
Vdd
+
-
Package
Digital FET
p+
n+
Analog FET
n+
n+
n+
p+
P Substrate
Figure 2-1. Overview of the substrate noise coupling problem
As shown in Figure 2-1, the switching activity of digital circuits injects spurious
signals into the substrate, and the fluctuations couple through metal lines and through the
27
substrate to the sensitive analog parts of the chip. Substrate noise can cause performance
degradation, or complete functional failures in the worst case.
2.2 Substrate Noise Coupling Mechanism
All the currents that are injected into the substrate will cause fluctuations of the
substrate voltage, and these fluctuations are called substrate noise. Substrate noise
currents in CMOS circuits are produced by several mechanisms, of which the dominant
are impact ionization currents, source/drain capacitive currents and supply coupling
currents.
Impact ionization occurs in a saturated MOSFET channel when the electrical field
strength is high enough to cause hot electrons. These electrons can release excess energy
by colliding with nearby lattice sites and create additional electron-hole pairs [27]. For
the NMOS device, additional electrons are swept into the drain, and the holes are injected
into the substrate creating a positive substrate current. This substrate current for NMOS
devices can be estimated [27-28] by the following semi-analytical expression (Equation
2-1):
I sub
§ C t1/ 3 x1/ 2
C1 (Vds Vdsat ) I d exp ¨ 2 ox j
¨ V V
© ds dsat
·
¸¸
¹
(2-1)
where Id is the drain current, Vds is the drain-to-source voltage, Vdsat is the drain-to source
voltage at saturation, tox is the gate oxide thickness and xj is the source/drain junction
depth. C1 and C2 are semi-empirical constants. Note that the substrate current is directly
proportional to the drain current Id, which means wider MOS devices operating as digital
switches will generate more substrate current since they conduct more current. A wider
device also indicates larger pinch-off region, giving rise to a larger number of hot
carriers. Another trend worthy of mention is that device scaling is likely to worsen this
28
problem due to shorter channel length, increased channel fields, smaller gate oxide
thickness tox and decreased junction depth xj.
Due to the junction capacitances between the source/drain of the transistors and the
bulk/well, voltage fluctuations on the source or drain can couple to the bulk/well. The
resulting substrate voltage shows the same characteristic as the switching node voltage.
In digital circuits, the supply current causes large ohmic IR voltage drops while
the fast current transients of the switching gates cause large inductive L di
dt
voltage
drops ( 'I noise) in the supply network. This supply noise couples capacitively into the
substrate from VDD via the n-well junction capacitance, and resistively from VSS via the
substrate contacts.
Voltage fluctuations across the passive components can also affect substrate
potential. Passive components in typical semiconductor processes include resistors,
capacitors, inductors and local diffusions. On-chip resistors are either poly-type or
diffused. Both resistor types can inject noise into substrate through parasitic capacitance.
On-chip capacitors can be poly-to-poly, metal-to-metal or poly-to-substrate types. All of
these can be significant substrate noise injectors. On-chip inductors and interconnects
inject noise into the substrate through the parasitic oxide capacitance to the substrate.
Local diffusions in the substrate can be p-type or n-type. N-type diffusions can inject
noise into the substrate through a reverse bias capacitance. P-type diffusions are often
used as substrate contacts or guard rings. The grounding for guard rings should be
properly done; otherwise they can be very effective path for substrate noise injection.
Similar to substrate noise injection, the reception of substrate noise by the MOS
devices can take place through the source/drain depletion junction. MOS devices also
29
exhibit a more severe form of substrate interaction due to the body effect. The substrate
potential dependence of the threshold voltage can be shown by Equation 2-2:
Vth
Vt 0 J ( 2IF VSB 2IF )
(2-2)
where VSB is the source to bulk potential, Vt0 is the threshold voltage for VSB equal to
zero, 2IF is the surface inversion potential and J
2qH si N sub
denotes the body effect
Cox
coefficient.
The bulk potential influences the threshold voltage and directly affects the
saturation current of the MOS transistor, which is given by Equation 2-3 (ignoring
channel-length modulation effect):
ID
1
W
PnCox (VGS Vth ) 2
L
2
(2-3)
Figure 2-2. Body effect represented by a dependent current source
In some sense [30-31], the bulk acts as a second gate and can be modeled by a
current source connected between drain and source (Figure 2-2). g mb can be expressed as
(Equation 2-4):
g mb
wI D
wVBS
PnCox
wV
W
(VGS Vth )( th )
L
wVBS
(2-4)
And gmb can be related with gm, the small-signal transconductance of the MOS
device by Equation 2-5:
30
g mb
gm
J
2 2IF VSB
K gm
(2-5)
and the factor K is typically in the range of 0.1 to 0.3, which means the body-to-drain
gain is only 10-14 dB lower than the gate-to-drain gain. At low to medium frequencies,
this will make MOSFET devices very vulnerable to substrate noise.
Substrate coupling can have different effects in different types of substrates. There
are two commonly used substrate profiles in commercial foundries, as shown in Figure 23. The first substrate consists of a thin surface buried-p region of 1-2Pm thickness and a
highly resistive bulk region of resistivity in the range of 10-30:-cm. This substrate is
used in certain BiCMOS processes. The low-resistivity surface layer serves as a channelstop layer for MOSFETs, reduces CMOS latch-up and raises the surface inversion
potential under the field oxide. The second substrate is used in most CMOS processes.
Some processes have a thin channel-stop implant at the surface, approximately 0.5-1Pm
thick, with a resistivity in the range of 0.5-1:-cm. The epitaxial layer thickness is about
10um with resistivity of 10-15:-cm. The bulk region is heavily doped, with a low
resistivity of about 10-100m:-cm, and thickness in the range of 100-400Pm. At low and
medium frequency, all substrates typically show a resistive behavior. This assumption is
accurate to a cut-off frequency, fc, which is defined by Equation 2-6 [32].
fc
1
1
2S RsubCsub
2SU subH Si
(2-6)
where Rsub and Csub are the resistance and capacitance of the substrate, and U sub and H Si
are the resistivity of the substrate and the permittivity of the silicon, respectively.
31
1 m
Channel-stop region
P-type 1 -cm
10 m
Lightly Doped Epi Layer
p-type ~10-15 -cm
~300 m
Heavily Doped p-Substrate
~10-100m -cm
(a)
(b)
Figure 2-3. Commercial substrate doping profiles: (a) high-resistivity substrate, (b) lowresistivity substrate.
Equation 2-6 provides a good reference for designers looking to use a proper
substrate model. As an example, for silicon substrate resistivity of 100:-cm, cut-off
frequency is in the range of 1.5 GHz. It is important to understand these limitations so
that they can serve as guidelines in the choice of the substrate resistivity to be used for a
given technology. Different techniques used for the modeling of substrate noise coupling
will be discussed in Section 2.4.2.
2.3 Substrate Noise Reduction Techniques
The principal strategies to limit or reduce substrate noise coupling can be grouped
into the following four categories:
x
Techniques reducing the noise generation from the noise source/generator (eg.
Switching digital circuits),
x
Techniques attenuate substrate noise from the noise generator to its bulk node,
x
Techniques changing the propagation of the noise to the sensitive circuits through
the substrate (not so effective in low-resistivity substrate),
x
Techniques that make the analog circuit insensitive to the substrate noise coupling
to its bulk node.
32
The techniques in first category are beyond the scope of our discussion here, and
this dissertation will only concentrate on the techniques in the last three categories.
2.3.1 Substrate Engineering
High-resistivity substrates have been proposed as a solution for suppressing
substrate noise and for increasing the quality factor (Q) of the passives [33] [34].
Improvement of Isolation (S21) about 10-20 dB for high resistivity substrate (Rsub >
1000:-cm) has been reported. Some other approaches followed similar idea by locally
increasing substrate resistance by a very large factor, such as the “high energy proton
bombardment” method [35]. But substrate resistivity cannot be raised without limits, and
other problems such as latch-up effects will arise and have to be solved.
SOI is often considered as a solution for substrate noise coupling [36], but the
buried oxide layer will lose its advantage at high frequency and becomes transparent to
substrate noise.
2.3.2 Device Isolation Methods
Guard ring structures around a noise source provide a low impedance path for AC
grounding and minimize the amount of noise injected into the substrate. Sensitive circuits
can use guard rings to decouple noise from the substrate.
Figure 2-4 shows the effectiveness of using N-well guard rings compared to P+
guard rings in low-resistivity (“heavily doped”) and high-resistivity (“lightly doped”)
substrates [37]. P+ guard rings are more effective than the N-well guard rings, because
they are resistively linked to the p-type substrate.
33
Figure 2-4. The effect of guard rings with different substrate doping profiles
Guard rings typically provide more effective isolation in a high-resistivity
substrate, and their efficiency also depends on their width, the noise frequency and the
package inductance [38].
Figure 2-5 and Figure 2-6 show how guard ring efficiency is affected by different
factors. The appropriate use of guard rings will be determined by the frequency of noise
to be suppressed, the available space, and the required attenuation.
Lower package inductance is very effective at reducing substrate coupling but
sometimes is an expensive approach because of the extra package costs.
34
Figure 2-5. Guard ring isolation versus frequency as a function of width
Figure 2-6. Guard ring isolation versus frequency as a function of package inductance
Triple-well (“deep N-well”) is now a common option in most CMOS processes.
Figure 2-7 shows the cross section of a triple well transistor with measured isolation
results as presented in [39]. The triple-well example showed in [39] exhibits an additional
~20dB isolation at low frequency compared to conventional P+ guard ring scheme. But
35
there is no publication yet showing how well this technique can be extended into the mmwave regime.
Figure 2-7. Triple-well isolation strategy
Deep trench isolation (Figure 2-8) is available in bipolar/BiCMOS processes,
which use high-resistivity substrates. The deep trench forces substrate current down into
the high-resistivity region of the substrate and attenuates the substrate noise coupled into
the sensitive circuits on the same substrate.
36
Figure 2-8. Deep trench isolation
2.3.3 Grounding Effects
It has been common practice to have separated supplies and grounds for analog and
digital sections on the same chip, for the isolation of switching noise generated by digital
parts from the sensitive analog circuitry. In [40], it showed (Figure 2-9) an example based
on this concept: substrate noise coupling between different sections on the same substrate
can be attenuated by providing them with different substrate grounds.
Figure 2-9. Separating the LNA and mixer grounds increased isolation
37
2.3.4 Noise-Reduction-Oriented Circuit Design Techniques
Other than process- and layout-based methods discussed above, noise-aware circuit
design techniques are also employed to reduce the substrate coupling effect.
Careful floor planning is playing an important role in RF/mixed-signal designs.
Increasing the distance between noisy and sensitive circuit blocks is a natural thought for
substrate noise isolation. For a low-resistivity substrate, substrate resistance between two
surface contacts is a function of distance, and it can help to reduce the substrate coupling.
However in high-resistivity substrates, most of the substrate current will propagate
vertically in the epitaxial layer and the bulk is considered as a single electrical node [37].
In this case, distance cannot be used to isolate sensitive and perturbing cells. Figure 2-10
shows a typical floor plan for mixed-signal design [41]. Proper substrate modeling and
good understanding of noise distribution among individual blocks are of great importance
for the designers to decide whether substrate coupling has been reduced sufficiently and
create the optimum floor plan.
Figure 2-10. Floor planning for substrate coupling reduction
38
Other substrate noise reduction techniques, such as using “active guard band filter”
[42] [43] and guard ring diode [44], have also been reported.
2.4 Substrate Noise Coupling Modeling and Extraction Strategies
As discussed in the previous section, the various techniques used to mitigate
substrate noise are heavily employed by SoC designers, guided by rules of thumb,
intuition, or past experience. However, without the ability to analyze and manage the true
effects of substrate noise, many of these techniques are often over deployed (i.e., overspacing of digital and analog blocks, excessive guard rings, high-cost low-parasitic
packages, etc), resulting longer design cycles and increased manufacturing costs.
Complete
Physical Design
Extract
Substrate Network
Compute
Substrate Noise
Simulation including
Noise-sensitive Devices
Modify Design Using
Provided Information
Figure 2-11. Typical verification flow for substrate noise analysis
39
To understand and model the effects of substrate noise coupling in SoC designs,
substrate parasitics should be combined with the circuits for simulation. However,
simulating an entire SoC design that includes all substrate parasitics is beyond the scope
of traditional circuit simulators. A complete analysis of substrate noise coupling effects
requires both substrate noise modeling as well as circuit simulation. A typical flow for
substrate noise analysis is shown in Figure 2-11.
Given the model as discussed in Section 2.2, there exist several techniques to
analyze and compute the substrate network in integrated circuits, each with a different
trade-off between accuracy, flexibility and computation speed.
Some techniques [37] [45] based on finite-element method (FEM) were published
for detailed numerical analysis in a few standard situations. They use a full numerical
analysis of all potentials and currents in the substrate, either by simulation of a 3D
resistance mesh of the complete substrate or by device simulation. However, these
approaches are not efficient enough for implementation in a standard CAD system.
Furthermore, they do not provide a circuit model for the designer as a direct feedback
between the circuit design, the layout design and the substrate coupling problems.
An alternative approach is based on a numerical [46] [47] or semi-analytical [48]
[49] solution of the differential equations that describe substrate transport. By using a
boundary-element method (BEM), with a suitable choice of the Green’s function, it is
possible to derive circuit models for the parasitic substrate cross-talk directly from the
layout. This avoids a full discretization of the complete substrate and allows a straight
forward computation of a fully specified equivalent electrical network.
40
The differences in discretization methodology give rise to differences in
computation speed. The 3D discretization of the FEM results in a dramatically large
system of equations to be solved compared to the 2D discretization of the BEM.
However, the FEM system is sparse, while the BEM system is full. For each method,
highly optimized specific solution methods are typically used. For the FEM, popular
solution methods include GMRES-like methods [45] and for the BEM, they include the
so-called fast multipole method [50] and the Schur method [51]. Alternatively, hybrid
FEM/BEM methods could combine the advantages of both methods [52].
Numerical analysis and computation of the substrate model is usually performed
after layout extraction and does not provide a priori insight to the circuit designers. Due
to the ever growing density and complexity of the integrated system, recursive iteration
between the transistor-level circuit simulation and the post-layout verification could be
very time-consuming. It is desirable to obtain a compact representation of the interactions
of circuit elements that couple through the substrate. A popular approach consists of
creating equivalent circuits or simple analytical models (macromodels), whose
parameters are selected to fit either measured or simulated substrate conduction behaviors
[53] [54].
Macromodels will help the designer in the early stage of the design and they can be
used to guide the placement of various components before the final layout is done.
However, this method brings new challenges to the circuit designers, including how to
distinguish critical noise sources and sensitive nodes in the circuits, and how to identify
the possible noise coupling paths in order to generate a correct substrate network.
41
2.5 Substrate Noise Measurement
Substrate noise measurement is an intuitive way to verify the results of substrate
modeling or to study time-domain or frequency-domain effects of substrate noise.
Various schemes have been reported in published papers and they address the problem of
substrate noise estimation from different perspectives.
2.5.1 DC Measurements
Substrate coupling can be treated as a two-port problem, with one port acting as a
noise injector and the other as a noise sensor. The simplest way to do so is to directly
measure the resistance network between one port and another port in the real substrate
[49]. A voltage source can be attached to the injection node and by measuring the current
flowing out of the sensor, the DC resistance between these two substrate contacts can be
obtained. The same procedure can be repeated for each pair of ports until the whole
resistive matrix is completed. However, this method is only valid at DC and low
frequency. As discussed in Section 2.2.1, [32] points out that a frequency limit exists for
the substrate resistive behavior assumption.
2.5.2 Direct Probing Measurement
As discussed earlier, substrate coupling is a two-port problem, and it is possible to
make such a measurement up to very high frequencies, using high frequency scattering
parameter measurement techniques.
In [55] [56] the authors have used a two-port test structure, as shown in Figure 212, to verify the validity of the simulator and the equivalent circuit of the substrate.
42
G1
G2
S1
S2
Noise
Injector
Noise
Sensor
G1
G2
Figure 2-12. Two-port setup for high-frequency substrate coupling measurement
Since all the measurements in [32] [55] are made on wafer, it is very difficult to
study coupling effects that occur only through the substrate in the presence of package
parasitics. Direct coupling between the probes used for the measurement also sets the
noise floor of measurements.
In [56], an advanced de-embedding method has been introduced to eliminate the
crosstalk between the RF probes and improve measurement accuracy. However, this
method requires RF probes spacing to remain constant throughout the measurement
sequence, and an ultrasonic cutter has to be used in order to change the connection for
calibration.
2.5.3 Embedded measurement techniques
A scheme is presented in [37] [57] to use the threshold voltage modulation of a
single MOSFET to sense the transient substrate noise. The outputs of the MOS devices
are measured as the RMS noise voltage induced on an external node, as shown in Figure
2-13.
43
Figure 2-13. Measurement setup of substrate noise coupling
Another scheme using a statistical approach is presented in [58] [59]. High-gain
voltage comparators are used as noise sensors, information describing substrate noise
generated by an on-chip inverters bank is extracted using statistical analysis techniques.
However, this technique neglects the spectral domain information of the injected noise,
which might be crucial in certain applications.
Both measurement techniques discussed above cannot measure the substrate noise
directly but through the influence of substrate voltage on the MOSFET current or
comparator state.
A real-time direct measurement technique is proposed in [59] [60] by using an
analog amplifier. A differential amplifier is used as substrate noise sensor, with one input
connected to the substrate and the other to a “quite” reference, to directly measure the
substrate voltage. But this technique has a limited bandwidth only up to 1GHz, mostly
determined by the bandwidth of the amplifier.
In [61], a scheme to measure narrow-band noise injected by an on-chip VCO is
presented. The basic idea is to implement an on-chip heterodyne down-converter, which
will translate detected signals to a different frequency and bring them off-chip. This make
44
it possible to avoid the contamination of the substrate coupled signals caused by direct
coupling through the package or through the board. Measurement results for narrow band
signal in GHz range are also reported.
2.6 Proposed Embedded Substrate Noise Measurement
In any measurement scheme discussed before, the paths taken by the coupled noise
are difficult to distinguish from each other. For example, package-induced and substratecoupled signals are especially difficult to discriminate if their coupling strengths are
similar. Detection of the coupling signal paths and strengths at different operating
frequencies is also important, since signal coupling mechanisms typically will vary with
frequency.
Attempting to answer these challenges, our proposed work integrates the substrate
noise measurement as an embedded system that can detect broadband signals and deliver
low-frequency analog test outputs through IC pads to a simple external test setup.
On-/Off-Chip
Signal source
DUT
Substrate
Contact
Low Frequency
Analog Output
(To Tester)
LowFrequency
External
Tester
Wafer
DUT
Embedded
Test circuits
Figure 2-14. Embedded substrate noise measurement
45
As shown in Figure 2-14, the basis of embedded substrate noise measurement is an
on-/off-chip broadband signal source plus some test circuitry integrated with the DUT.
The signal source acts as a noise generator and injects well-known signals into the
substrate, and then the embedded test circuit will extracts useful information from the
response of the detector into baseband signals, which are deliver off-chip to external
tester.
2.6.1 Potential Benefits
Compared to other existing substrate noise measurement methods, the potential
benefits offered by the proposed embedded test methods are listed as follows:
x
The broadband signal detection enables the investigation of substrate signal
propagation mechanism at different operation frequencies and the study of substrate
parasitic influence on advanced high-speed/RF circuits.
x
Low-frequency output provides excellent isolation between input and output signal
ports, and greatly improves the accuracy of the measurements. Crosstalk problem
between RF probes is no longer a serious issue, and calibration procedure with
rigid probe location control as mention in [46] can be avoided. Also low-frequency
output will alleviate the requirements for an external tester and help to cut down the
test cost, as discussed in Chapter 1.
x
On-chip test circuits will detect desired signals and extract useful information
before the signals are routed off-chip, thereby allowing the study on the effects of
signal coupling through substrate and/or other paths separately (i.e. package
parasitics induced substrate noise). Also, on-chip test circuits can be used for
measurement in any type of semiconductor substrate and simplify the measurement
setups.
2.6.2 Design Issues
Although our proposed work has all the advantages described above, several design
issues have to be solved before the implementation of such a system to be practically
useful.
46
First, the chip area overhead brought by the additional test circuitry must be
minimized due to economic considerations. It is not easy to shrink the system design
without degrading the performance of on-chip test circuits.
Secondly, calibration of on-chip test circuits is a substantial effort in order to
guarantee and further extend the measurement accuracy. Precise, yet easier calibration
techniques are desired to simplify the calibration procedure and cut down the test cost.
The third issue is the introduction of additional on-chip test circuitry should have
few effects on other circuits on the same chip without degrading their original
performance significantly.
Finally, the on-chip test circuits should be done with minimal power consumption.
If an on-chip signal source is employed, the power of the generated test stimulus should
be kept low without compromising the signal quality.
All the design issues listed here will be further discussed in the next few chapters
when the designs of components in the proposed work are presented.
2.7 Research Goals
A set of preliminary specifications for the embedded substrate noise measurement
system was developed through interactions with TI:
x
x
x
Small detector size
Sensitivity: 10’s of mV (for large ICs )/a few μV (for small ICs )
Bandwidth: 10 - 30 MHz
Based on the specs above, our first goal of this work is to develop a low-frequency
(10MHz) on-chip substrate noise measurement test vehicle to demonstrate the embedded
system feasibility.
47
The second goal is to develop a system capable of measuring substrate noise
coupling over a very wide frequency span up to millimeter wave range.
48
CHAPTER 3
AUTOMATIC GAIN CONTROL BASED MEASUREMENT SYSTEM
3.1 Introduction
Automatic gain control (AGC), is one of the most useful circuits in modern
communications receivers, and it is employed in systems where the input signal level varies over
a wide dynamic range. AGC will detect the amplitude of the received signal and automatically
adjust the gain in order to maintain a constant output signal level. Since the output signal level is
always fixed, one can predict the input signal level if the gain information is known. This makes
it possible to use an AGC as a signal strength meter for embedded substrate noise measurement.
In this chapter, an AGC based embedded substrate noise measurement test vehicle is
presented as follows: first, the principle of AGC operation is discussed; next, detailed circuit
designs are described; finally, simulation results and measurement results are shown to verify the
design.
3.2 Theory of AGC
An AGC system is an intuitively nonlinear system, and there seldom are general largesignal solutions to the nonlinear equations that describe the system dynamics. However, for most
systems, an approximate solution can be derived in terms of a small-signal model.
A method is proposed in [62] to obtain constant AGC loop settling time independent of the
received signals. Two assumptions are made for the discussion: first, It is assumed that the AGC
loop only responds to the signal amplitudes and all the signals are represented in terms of their
amplitudes; second, the peak detector is assumed to extract the peak amplitude linearly and
instantly (it operates much faster than the basic operation of the loop).
49
¦
(a)
¦
¦
(b)
Figure 3-1. AGC circuit block diagram and linearized loop model
The basic elements of an AGC system is shown in Figure 3-1(a). The input signal is
amplified by a variable gain amplifier (VGA) whose gain depends on a control signal Vc. The
peak detector measures the peak amplitude, Aout, of the amplified signal Vout and is compared
with a DC reference signal Vref. The difference between these two signals (error signal) is then
filtered and used to control the gain of the VGA, until the measured peak amplitude, VP, is made
equal to Vref. Figure 3-1(b) illustrates a linearized AGC system that can be solved analytically.
The transfer function of the VGA can be written as
AOUT
ª
A º
KV 1 exp « ln[G (VC )] ln( I N ) »
KV 1 ¼
¬
(3-1),
where AOUT and AIN are the amplitudes of the input and output signals, respectively.
50
The output y in Figure 3-1(b) is given by y
and the gain control voltage is expressed as VC
³
t
0
x ln G (VC ) (3-2),
Gm
VREF KV 2 y dW
C
(3-3).
Taking the derivative of Equation 3-2 with respect to time and we can get
dy
dt
1 dG (VC )
dx
dt G (VC ) dt
(3-4).
Equation 3-3 can be rewritten with Equation 3-4 substituted in to yield
dy
dt
where K
G
G
dx
dy
K m VREF KV 2 y Æ
( KV 2 K m ) y
dt
C
dt
C
G
dx
K m VREF
dt
C
(3-5),
1 dG (VC )
.
G (VC ) dVC
Equation 3-5 describes a first-order linear high-pass system and its time constant is given
1
by W
Gm º
ª
K
K
.
V
2
«
C »¼
¬
Achieving a constant settling time will allow the AGC loop bandwidth to be maximized
for fast signal acquisition while maintaining stability over all operating conditions. In classical
designs, Gm and C are held constant, and criterion for constant AGC settling time comes to
K
1 dG (VC )
=constant, which leads to the well-know exponential VGA gain
G (VC ) dVC
characteristic requirement: G (VC )
K 2 e KVC [63]. However, in CMOS technology, achieving an
exponential relationship is not as obvious as in bipolar technology.
An additional degree of freedom can be obtained if the loop filter (Gm/C) is made
nonlinear. As shown in Figure 3-2, a constant settling time AGC system can be realized with a
Gm-1 block to generate the inverse function of the VGA. Assume the capacitance C is fixed and
all the transconductances in the AGC loop are functions of VCP:
51
Gm1i (VCP )
K1i Gm (VCP ) , for i=1, … , N
Gmj (VCP )
K j Gm (VCP ) , for j=2, 3
then the criterion for constant W becomes
(3-6),
Gm 2 (VCP ) dG (VCP )
=constant.
G (VCP ) dVCP
¦
Figure 3-2. Constant settling time AGC with arbitrary VGA gain and Gm control characteristic.
It can be shown that AGC constant settling time can be satisfied for any monotonic
nonlinear VGA gain versus control signal (VCP) relationship if the Gm has the same nonlinear
function within a constant proportionality.
Inside the Gm-1 block, Gm3(VCP) replicates the nonlinearity of VGA and integrator
transconductances and is used to generate the inverse transconductance function. The negative
feedback loop with the OPAMP will force VC
Gm 3 (VCP ) RL 2VDC ; hence, the inverse function is
generated as:
VCP
§
·
VC
Gm1 ¨
¸
© K 3 RL 2VDC ¹
(3-7).
52
Note that function Gm( ) must be monotonic for Gm-1( ) to be valid.
The VGA gain is the product of the gains of N stages and is
N
–G
G (VCP )
m1i
(VCP ) RL1i
(3-8).
i 1
Using Equation 3-8, the VGA gain and loop filter’s transconductance can be written as a
function of VC:
G (VC )
ª VC
º
«
»
¬ K 3 RL 2VDC ¼
Gm 2 (VC )
N
N
–K
1i
RL1i
(3-9),
i 1
K 2VC
K 3 RL 2VDC
(3-10).
Similarly, the overall time constant of the AGC in Figure 3-2 can be derived and is
W
CRL 2 K 3 VDC
N K 2 VREF
(3-11).
Note that zero gain state for loop filter transconductance must be prevented; otherwise, the
feedback loop will become broken indefinitely. A practical circuit implementation to eliminate
zero gain state will be discussed later.
3.3 Circuit Design
Our test vehicle will be designed based on the constant settling AGC structure in Figure 32. The Gm-1 block not only generates the inverse transconductance function that is important in
the derivation, but also it provides valuable information of VGA stage gain. When the loop is
stable, one can write VC ' VDC Gm 3 (VCP ) RL 2 ; hence, the transconductance is
Gm3 (VCP )
VC '
VDC RL 2
(3-12).
Using Equation 3-8, the VGA gain can be expressed as
53
G (VCP )
ª VC ' º
«
»
¬ K 3 RL 2VDC ¼
N
N
–K
1i
RL1i
(3-13).
i 1
By measuring VC’ and setting the reference voltage Vref, the input signal amplitude can
simply be calculated by Vref/G(VCP). Note both voltages are DC signals, which require very
simple external measurement setup.
3.3.1 Variable Gain Amplifier
As shown in Figure 3-3, the proposed VGA consists of a linear transconductance cell,
Gilbert cell-type differential pairs and load resistors. The fixed input transconductor is a
differential pair linearized through resistor degeneration. The differential pairs of Gilbert cell are
used to tune the output currents of the transconductor and steer the corresponding portion to the
load resistors, which makes the VGA gain adjustable. The additional transistors, M21 and M22,
are used to keep the VGA gain greater than zero.
Vdd
Vdd
Vdd
Vdd
Vp2
Vp1
M15
Vdd
2I0
M3
I0
M5
2I0-I3
Vin+
Vc-
M11
M12
Vdd
M4
I0
M1
2I0
M6
M2
Vp1
2I0-I4
Vin-
IS
Vc+
M16
Vc+
M13
M14
Vc-
Rs
I5
I6
I3
M9
M17
I1
I2
M10
M18
M7
M21
I8
Vn1
Vc+
Vc+
I6a
M22
Vout-
I7a
RL
I9
I7
M8
Vn1
Vout+
I4
IL
RL
M19
M20
Figure 3-3. VGA cell schematic
54
I10
VGS,M1 and VGS,M2, are maintained constant due to the feedback provided by M5 and M6,
which forces a constant current through the input transistors, M1 and M2. As a result, the
differential input voltage appears across the input resistor Rs, providing a constant
transconductance Gm
I1
1/ Rs . By observing the input currents, we then have
I 0 I S and I 2
I0 I S
(3-14).
The output currents, I1 and I2, of the input transconductor are 1:1 mirrored to the gain
tuning differential pair: I1
I 3 and I 2
I4 .
The control voltages, Vc+ and Vc-, are applied to the differential pairs, M11-M12 and M13M14, to adjust the currents to the load resistor:
I5
ª¬1 f VC º¼ 2 I 0 I 3 and I 6
f VC 2 I 0 I 3 (3-15),
I8
ª¬1 f VC º¼ 2 I 0 I 4 and I 7
f VC 2 I 0 I 4 (3-16),
I6a
I7a
I6 I7
2
(3-17),
where 1 ! f VC ! 0 .
The output stage consists of load resistors with common-mode feedback and current
sources (M19 and M20). Since I 9
the output load current is I L
I 5 I 6a I L and I10
I10 , I 9
I 5 I 6 a I 7 a I8 2
I 7 a I8 I L ,
(3-18).
Using Equation 3-14, 3-15, 3-16 and 3-17, Equation 3-18 can be rewritten as
IL
ª¬1 f VC º¼ I S
(3-19).
The voltage gain of the VGA is then
55
AV
where I S
Vout
Vin
2 ª¬1 f VC º¼ I S RL
Vin
2 I L RL
Vin
2
RL
ª1 f VC º¼
RS ¬
(3-20)
Vin
. For 1 ! f VC ! 0 , VGA zero gain state can be prevented.
RS
(a)
Vdd
Vdd
Vdd
Vdd
Vp2
Vp1
Vdd
M15
M3
Vdd
M4
M5
M11
M12
Vp1
M6
Vin+
Vc-
M16
M1
M2
Vin-
Vc+
Vc+
M13
Vc+
M22
M14
Vc-
Rs
M9
M17
M10
M18
M7
M8
Vn1
M21
Vout+
Vn1
Vc+
RL
Vout-
RL
M19
M20
(b)
Figure 3-4. DC offset cancellation for VGA causing multiple feedback loops
Figure 3-4(a) shows the DC offset cancellation scheme used for the VGA stages. Multiple
feedback loops are formed inside the VGA cell with DC feedback path applied. There are two
negative feedback loops (Vin+-M1-RS-M2-M6-M18-M14 and Vin+-M1-M5-M17-M12-M21-RL-M20)
and one positive feedback loop (Vin+-M1-M5-M17-M12-M21-RL-M22). Due to the presence of
positive feedback loops (Figure 3-4(b)), there can be multiple operating points [64]. By doing
DC sweep simulation on input bias voltage Vin and Vout, it shows (Figure 3-5(b)) three possible
56
operating points for the VGA circuit when the DC offset cancellation structure is applied.
Undesired operating points have to be removed to guarantee the stability of the VGA circuit.
(a)
Desired
operating
point
(b)
Figure 3-5. Start-up circuit solves the multiple operating point problem in VGA
In order to eliminate the undesired operating points, a start-up circuit is designed and
added to the VGA cells, as shown in Figure 3-5(a). The simulation result in Figure 3-5(b) shows
that the two extra operating points are avoided and the start-up circuit is transparent to the
normal operation of the VGA.
3.3.2 Peak Detector
The analog peak detector is a key piece in our AGC system. It detects the peaks of VGA
output signals and holds the value to compare with the reference value (the desired value for
57
VGA output), feeding the comparison results (errors) to the loop filter and Gm-1 stages to create
a proper gain control signal [65].
(a)
(b)
Figure 3-6. Half-wave peak detector and full-wave peak detector
The simplified schematic of a classical half-wave peak detector is shown in Figure 3-6(a).
When a input signal Vin(t) arrives and is higher than the hold voltage Vout, the OTA will generate
a sharp negative transition that switches M1 on. The current mirror M1-M2 will charge the hold
capacitor C until Vout equals Vin.
A simplified schematic of the proposed full-wave peak detector is shown in Figure 3-6(b).
The tracking behavior of the peak detector can be varied by tuning the transconductance of the
unidirectional current mirror and the loading capacitor C.
58
3.3.3 Loop Filter and Gm-1 Block
Figure 3-7. Loop filter
As discussed in Section 3.2, the transconductance of the loop filter has to have the same
gain versus control signal relationship with a constant of proportionality as a VGA cell does. The
loop filter consists of a “scaled” version of the VGA cell and an integration capacitor at the
output node (see Figure 3-7). The transfer function of the loop filter can be expressed as
VC
Vin
Gm RL
.
1 sCRL
Figure 3-8. Differential difference amplifier (DDA) (CMFB circuit not shown)
A differential difference amplifier (DDA) is used as the OPAMP in the Gm-1 block because
the loop operates in differential mode. As shown in Figure 3-8, the proposed DDA has two
differential input pairs and a differential output pair. When used in negative feedback with very
large loop gain, the DDA forces the two differential inputs ( Vc Vc and V 'c V 'c ) to be
59
identical and generates the corresponding control voltage for the VGA stages. To ensure a wide
output control voltage range, the DDA is implemented as a folded cascade structure. A CMFB
circuit is used to set common mode voltages of the two output nodes.
3.3.4 On-chip Bias and Voltage Reference Circuits
As shown in Figure 3-9, a wide-swing constant-gm bias circuit is applied to provide onchip bias reference. A start-up circuit is included to prevent zero current state for all the
transistors. This bias circuit is consists of four different feedback loops. The addition of the
resistor RS kills the positive feedback loop gain, which makes the loop stable (the loop gain is
less than one). However, if RS decreases, the positive feedback loop gain will increase and the
system could become unstable. This effect will be discussed later in more detail.
Vdd
Vdd
M7
M8
Vdd
M11
Vbiasp
Vdd
Vcascp
M6
M10
M9
Vdd
M14
M18
M15
M16
M4
M5
M1
M13
M17
IREF
M12
M3
M2
Vbiasn
Vcascn
RS
Bias Loop
Cascode Bias
Start-up Circuit
Figure 3-9. Wide-swing constant-gm bias circuit
3.3.5 T-switch
To increase testability of the whole system, some of the internal nodes need to be tested.
One of the common ways to provide access to internal analog signals is through analog test
60
buses. The external tester can gain access to internal nodes by opening and closing the
appropriate transmission gates or other switching structures.
Vin
Vcontrol
M0
Vout
(a)
(b)
Figure 3-10. Transmission gate and T-switch
The most common CMOS structure for implementing an analog transmission gate is a
back-to-back PMOS and NMOS transistor pair [9]. As shown in Figure 3-10(a), complementary
control signals are applied to the two transistor so that they are both on and off at the same time.
However, a capacitive coupling path (drain-to-source capacitance) exists even when the
transmission gate is turned off. This circuit will suffer from crosstalk problem between input and
output nodes. To avoid this problem, a T-switch is used in our design (Figure 3-10(b)). The
ground transistor M0 is closed whenever the switches are opened, thereby shunting any crosstalk
signals to ground.
3.3.6 Overall System with Embedded Test Points
The proposed overall system, including two VGA’s, peak detector, loop filter and Gm-1
block, is shown in Figure 3-11(a). Two embedded test points, SW1 and SW2, are inserted into
the design for more testability. Each test point consists of six T-switches (all the signal paths are
differential), as shown in Figure 3-11(b). Additional control signals are provided to control the
signal paths of the embedded test points in different test modes. For example, if SW1 is turned
61
on, then the VGA output nodes are disconnected from the internal signal path to the peak
detector and connected to the buffer so that they can be externally accessed.
¦
(a)
(b)
Figure 3-11. Overall AGC system with embedded test points and embedded test point
implementation
3.4 Simulation of AGC Design
The proposed AGC circuits were simulated using Cadence Spectre with IBM7wl BiCMOS
0.18um models.
Figure 3-12 shows gain tuning curve of the VGA in the inverse gain control loop (DC
gain) and a VGA in the signal amplification path. Gain information of signal amplification
(VGA) stage can be predicted by obtaining the gain control characteristic of VGA in Gm-1 block.
Constant offset between two gain tuning curves can be calibrated easily. The average gain tuning
sensitivity is around 25dB/V.
62
Figure 3-12. Gain tuning curve of VGA blocks
Frequency responses of the two-stage VGA in different gain modes are shown in Figure 313. The upper -3dB corner frequency is 20MHz.
Figure 3-13. Frequency response of two-stage VGA
The linearity of the two-stage VGA is specified by single-tone total harmonic distortion
(THD) in maximum output swing mode (400mVpk) in Figure 3-14. It shows around 1% THD
for input signal range from 40mV to 200mV.
63
Figure 3-14. Linearity of two-stage VGA in THD (%) versus input signal strength
Figure 3-15 shows the input versus output characteristic of the peak detector for DC input
and 10MHz sine wave input. The transfer function is reasonably linear when input is in the range
of 5mV to 400mV.
Figure 3-15. Input versus output characteristic of peak detector
64
The proposed AGC system in Figure 3-11 is simulated using the transient response for a
10MHz sine wave whose initial input amplitude is 10mVpk, but every 4μs the input signal
strength is increased to 20mVpk, 50mVpk. The response of VGA output is shown in Figure 316. The difference of settling time is due to the different initial startup transient when the input
signal strength is changed.
Figure 3-16. Transient response of AGC to a 10MHz sinusoidal input with varying amplitude
3.5 Measurement Results
The proposed AGC system in Figure 3-11 was laid out using IBM7wl 0.18μm process
with 7 metal layers. Figure 3-17 shows the die photo for the fabricated AGC chip. The total chip
area including bond pads is 2000 x 2000μm, whereas the actual AGC circuit area is 1500 x
1300μm. The 10pF loading capacitor for peak detector is integrated on chip, while two 100pF
capacitors for loop filter are provided externally.
With all prepared measurement setups, an unexpected problem were found during basic
DC measurement. The bias circuit, shown in Figure 3-18, consists of current mirrors providing
gate voltages to cascade structures of PMOS and NMOS transistors. An external resistor is
connected to allow the bias current to be adjusted for process variations. It is designed to provide
65
50μA current with an external resistor of 2.2KŸ. A grounded variable resistor RS is connected
through DC probe to the chip. However, at certain frequency, the positive feedback loop
oscillates because the parasitic capacitor CP (provided by bond pad, DC probe decoupling
capacitor, connection wire, etc.) reduces the impedance at the source of M2.
A solution for the stability problem is to keep the loop gain of positive feedback smaller
than one all the time. Instead of using external resistor, a fixed value on-chip resistor can be
applied to insure the stability of bias circuit (by minimizing the parasitic capacitance Cp at the
drain of M2).
BUF
SW1
Peak
Detector
-1
SW2
Figure 3-17. Microphotograph of the AGC system
Due to the on-chip bias circuit oscillation, the evaluation of overall system performance is
impossible at this time. Additional chip fabrication is needed in the future.
66
Figure 3-18. Bias circuit with external resistor connection
3.6 Conclusions
For low-power application, the linear amplification (AGC) has a limited useful
instantaneous input dynamic range before saturation occurs. Also, the frequency response of the
peak detector sets the limit for AGC on high-frequency signal processing. Finally, the large chip
area overhead of the embedded AGC circuits prevents the practical application of this technique.
67
CHAPTER 4
LOGARITHMIC AMPLIFIER DETECTOR
As discussed in Chapter 3, in order to develop a compact embedded system capable
of measuring substrate noise coupling over a very wide frequency span, alternative
methods must be found.
4.1 Introduction
A logarithmic amplifier can be employed as an embedded signal strength indicator
for substrate coupling measurements. Compared to a linear AGC-based measurement
method, the advantage of this technique is that it can detect broadband signals and
compress a much wider input dynamic range into a small range at the output.
This chapter is organized as follows. First, existing logarithmic amplifier
techniques are discussed. Next, the circuit design of a logarithmic amplifier is described,
followed by simulation results. Finally, limitations of this method for embedded substrate
noise measurement will be discussed.
4.2 Review of Various Logarithmic Amplifier Techniques
Logarithmic amplifiers can be found in many applications in the fields of
communication and of measurement systems [66]. A logarithmic amplifier can be
realized with an inverting operational amplifier circuit with nonlinear feedback (Figure 41), which obtains excellent logarithmic response from the PN junction I-V characteristic.
Rin
Vin
+
VLOG
(a)
(b)
Figure 4-1. Transconductance feedback logarithmic amplifiers with (a) diode or (b)
transistor
68
Assume the forward conducted diode obeys the following constitutive law
I diode
Ise
VLOG
VT
(4-1),
where VT=kT/q, k is Boltzman constant, T is absolute temperature, q is the charge of an
electron, and Is is the scale current proportional to the area of diode junction.
By writing current node equation at the negative input of the op-amp in Figure 4-1,
I diode
I in
Vin
Rin
(4-2),
and combine with Equation 4-1, the log output of the transconductance feedback
logarithmic amplifier can be obtained as:
VLOG
VT log(
Vin
)
I S Rin
(4-3).
However, elaborate compensation techniques (i.e., temperature compensation) are
required to make the transconductance feedback logarithmic amplifiers meet the demands
of most applications. Dynamic range and response time also limit their application.
A more powerful logarithmic technique is the use of successive-detection
architecture, wherein the summation along a cascade of identical limiting amplifiers
approximates the logarithmic function as a piecewise-linear function. This method
depends on the circuit architecture to produce a (pseudo-)logarithmic transfer function
without relying on a physical device’s nonlinearity.
A simplified block diagram of a commonly used pseudo-logarithmic amplifier is
shown in Figure 4-2. Several identical limiting amplifiers are cascaded to obtain limiter
outputs and each limiter output is fed into rectifier. The output currents of the rectifiers
are summed with a low pass filter (LPF), which is used to determine the received signal
level.
69
Figure 4-2. Simplified block diagram of successive-detection logarithmic amplifier
Consider a logarithmic amplifier with N cascaded stages, each having a smallsignal voltage gain of AV, with a limiting voltage VL. As shown in Figure 4-3, assume the
mth stage is driven to voltage-limited output, AV mVin
VL , where Vin is the amplitude of
the sinusoidal input signal. As the signal progresses down the gain chain to the
subsequent stages, it will begin to clip. And the output of the summer will be written as:
Vin AV Vin AV 2Vin AV 3Vin ... AV m 1Vin ( N m 1)VL
VLOG
(4-4).
AV m 1
Vin ( N m 1)VL
AV 1
Vin
AV2Vin
AVVin
1st
2nd
AVmVin=VL
mth
VL
VL
VL
(N-1)th
(m+1)th
Nth
Vin
Lim Out
Vin
AVVin
AV2Vin
AVmVin=VL
VL
VL
VL
Low
Pass
Filter
Log Out
VLOG
Figure 4-3. Signal flow in a successive-detection logarithmic amplifier
70
If AV 1 , then Equation 4-4 can be simply written as:
AV m 1Vin ( N m 1)VL
§V ·
log ¨ in ¸
§
1 ·
© VL ¹ V
¨ N 1
¸ VL L
log AV
AV ¹
©
§
1 log VL
VL
log Vin ¨ N 1 log AV
AV log AV
©
·
¸ VL
¹
(4-5).
Equation 4-5 shows a linear relationship between the output of the detector and
log(Vin ) . The slope of the transfer function is given by
VL
, and VL and AV will be
log AV
obtained from calibration of the circuit. Then the nominal output voltage of the
logarithmic amplifier for any input level within the linear range of the device can be
predicted by using Equation 4-5.
4.3 Logarithmic Amplifier Circuit Design
Considering the multistage limiting amplifier structure shown in Figure 4-2, input
signal dynamic range and frequency determine total gain Atot and overall 3-dB
bandwidth Ztot . In order to achieve desired accuracy and minimize power consumption,
the following questions need to be answered. What is the optimum number of stages
which will require the least gain-bandwidth product per stage? What is the output log
conformance (error) within the input signal range?
To simplify the problem, assume that each stage is represented by an ideal voltage
amplifier A0, an output resistance Rout, and a load capacitance CL [67]. The overall
transfer function is then given by:
71
§
¨ A
0
H (s) ¨
¨ 1 s
¨ Z
0
©
where Z0
·
¸
¸
¸
¸
¹
n
(4-6)
( Rout CL ) 1 is the 3-dB bandwidth of each stage.
To determine the optimum number of stages, we employ the 3-dB bandwidth Ztot of
the overall system as a measure of its speed. Assume s Ztot and calculate the value of
Z0 such that
ª
º
«
»
«
»
A0
«
»
2
«
§ Ztot · »
« 1 ¨
¸ »
«¬
© Z0 ¹ »¼
n
A0 n
2
(4-7)
Thus, one obtains Ztot
Z0
n
2 1
(4-8).
For n t 2 , (4-5) can be approximated as: Ztot
Z0
0.9
n
(4-9).
Let B denote the gain-bandwidth product of a single stage and assume B to be
constant for a given power dissipation in a given technology, then
B
Ztot
Atot A0Z0
1
n
Ztot n
0.9
(4-10)
0.9 B
Atot 1
n
n
To minimize the denominator, D
(4-11).
Atot differentiate with respect to n:
72
1
n
n , take its natural logarithmic and
1 wD
D wn
1
1
2 ln Atot 2n n
(4-12).
The optimal number of stages can be calculated as nopt
(4-13).
2 ln( Atot )
Figure 4-4 shows single stage gain A0, bandwidth Ȧ0, gain-bandwidth product B
and as a function of the number of stages with overall 3-dB bandwidth ( Ztot ) of 100MHz
and overall cascaded gain (Atot) of 80dB.
1
10
0.5
5
0.1
0.05
0.01
1
55
10
15
20
25
29
1
Figure 4-4. Normalized gain, bandwidth and gain-bandwidth product for a single stage
versus the number of stages for overall gain of 80dB
As derived in Appendix A, the accuracy of logarithmic amplifier (defined as input
error) is closely related to single stage gain A0, which is determined by Atot and the
number of stages. As shown in Figure 4-5, input error decreases for smaller value of
single stage gain A0.
73
Maximum Error (dB)
10
10
10
10
1
0
-1
-2
0
5
10
15
20
25
30
35
40
Stage number
Figure 4-5. Maximum input error versus the number of stages for overall gain of 80dB
From the discussion above, the optimal number of stages is determined by both
bandwidth and accuracy. Depending on the system specifications, tradeoffs must be made
to satisfy the bandwidth and accuracy requirements.
The initial specifications for the proposed logarithmic amplifier detector are to
operate at 100MHz with ±1dB accuracy and with sensitivity within μV range. Hence the
3-dB bandwidth and overall gain are chosen to be 100MHz and 80dB. From Figure 4-5,
the optimum stage number for ±1dB error is 9. Using Eqn. (4-9), the -3dB frequency
corner for a single amplifier stage is about 333MHz.
4.3.1 Limiter Design
An NMOS differential pair with NMOS load is often used for limiting amplifier
stages (Figure 4-6 (a)). The advantage of this configuration is that the gain depends on
the ratio of input transistor size and load transistor size. Using the square law equation
74
(ignoring body effect) of NMOS transistors, the voltage gain of this circuit can be shown
as:
A
gm1
gm3
(W / L)1
(W / L)3
(4-14)
(a)
(b)
Figure 4-6. Limiting amplifiers
But in a n-well CMOS process, the NMOS loads suffer body effect and therefore
the gain also depends on gmb of the loads. The body effect can be eliminated using current
mirrors (Figure 4-6 (b)). But then the gain of such a circuit depends on the accuracy of
the current mirrors.
Other drawbacks of the second configuration include extra power consumption and
degraded frequency response. The triple-well transistor provided by IBM SiGe process
enables one to get rid of body effect on the load transistor with the penalty of slightly
increased chip area.
Figure 4-7 shows a discrete triple-well NMOS transistor and the limiting amplifier
using triple-well NMOS loads. Deep nwell shields the bulk of the transistor from
substrate and the source can be tied to the bulk.
75
(a) Cross-section view of a triple-well NMOS transistor
Vdd
D
G
M3
P-Sub
Vin+
S
M1
M4
M2
Vin-
Nwell
Contact
(b) Limiting amplifier
Figure 4-7. Limiting amplifier using triple-well NMOS loads
4.3.2 Rectifier Design
In an architecture of piecewise linear approximation (Figure 4-2), each piece of
linear session is obtained by rectifying each gain cell output of the limiting amplifier. All
the rectified waveforms are then summed and filtered to yield a DC-like indicating
voltage.
Multipliers based on Gilbert cells (Figure 4-8) can be used as full-wave rectifiers.
Transistor M1-M4 act as switches and M5-M6 act as a differential pair. Rectification is
achieved by turning on M1-M4-M5 and M2-M3-M6 alternatively during positive and
negative cycle of Vin. But they are not appropriate for low voltage operation because they
use four stacked transistors.
76
Vdd
M7
M8
M9
Iout
M1
M2
M3
M4
Vin+
Vin+
Vin-
Vin+
M5
M6
Vin-
Figure 4-8. Gilbert cell based rectifier
Kimura proposed a technique for CMOS pseudo-logarithmic rectifiers operable on
low supply voltages [68] [69].
ID2+ID3
ID1+ID4
M1
M2
M3
Vin
xN
M4
x1
xN
I0
x1
I0
(a)
(b)
Figure 4-9. Full-wave rectifier with unbalanced source-coupled pairs
Figure 4-9(a) shows two identical unbalanced source-coupled pairs with one pair
size N times as large as the other. The circuit schematic of complete full-wave rectifier
with unbalanced source-coupled pairs is shown in Figure 4-9(b). Assume all transistors
are operating in the saturation region, the differential output current, Iout , is calculated in
Equation 4-15.
77
I out
( I D1 I D 4 ) ( I D 2 I D 3 )
­
I0
,
° when Vin d
E
N
°
° N 1
N ( N 1) E 2
I0 4
Vin
°2
N 1
° N 1
°
°
° when I 0 d V d I 0 ,
in
°
E
NE
°
®
° 2( N 1) N E V 2 4 N E V ( N 1) I 0 NV 2
in
in
in
°
E
2 NI 0
,
°
2
(
N
1)
N
1
°
°
°
°
I0
,
° when Vin t
E
°
°̄0
where E
(4-15),
1
W
Pn Cox ( ) , μn is the effective surface mobility, COX is the gate capacitance
L
2
per unit area, W is the gate width and L is the gate length for an NMOS transistor.
When input voltage is small ( Vin d
I0
), most of the current will flow through
NE
the larger size transistors (M1 and M4), and Iout is a parabolic function of input voltage.
As input voltage increases (
I0
d Vin d
NE
I0
E
), smaller size transistors (M2 and M3)
start to contribute current on the left, and Iout can be approximated as a logarithmic
function. When input voltage Vin t
I0
E
, the output current is zero.
As shown in Figure 4-10, assume the mth stage is driven to voltage-limited output,
AV mVin
VL and the rectifier output can be approximated as Vout
Equation (4-15), the output of the summer will be written as:
78
K log(Vin ) . Using
VLOG
K log(Vin ) K log( AV Vin ) K log( AV 2Vin ) ... K log( AV m 1Vin )
(4-16),
1
mK [ (m 1) log( AV ) log(Vin )]
2
which will exhibit a negative slope in output transfer curve, as shown in Figure 4-11 and
4-14.
Figure 4-10. Signal flow in a successive-detection logarithmic amplifier with pseudologarithmic rectifiers
VLOG
2I0
16X
8X
6X
VLOG
V
in
I
0
E
Figure 4-11. Simulated DC transfer curve for full-wave pseudo-logarithmic rectifier and
ideal VLOG curve versus input voltage
Figure 4-11 shows DC transfer curve for different values of N. If the ratio of
unbalanced source-coupled pair (N) increases, the pseudo-logarithmic function input
79
range are widened. However, larger N means more input parasitic capacitance for the
input transistors, which will degrade the frequency response of the rectifier. N=6 is
chosen for the proposed rectifier design.
4.3.3 DC Offset Cancellation
DC offset cancellation is a very important issue in the limiter design since the
mismatch of the devices could cause significant offset and smear the small input signals.
C
C
R
R
C
C
R
R
Bias
(a)
(b)
Figure 4-12. DC offset cancellation techniques
Two different approaches are considered for DC offset cancellation. The first
method (Figure 4-12(a)) is to use coupling capacitors between each stage of the limiting
amplifiers. The coupling capacitors eliminate DC offsets and the resistors provide input
DC bias voltage for the next stage. The values of C and R determined the high pass
corner. The major drawback of this method is that passive components occupy large chip
area. The other method (Figure 4-12(b)) is to use DC feedback circuit, which requires an
external capacitor C2. The second method was chosen because it leads to less chip area
overhead.
80
4.4 Simulation Results and Analysis
The useful dynamic range of a successive-detection logarithmic amplifier is limited
on the lower end when all stages are in the linear region or input noise floor causes the
last stage to its limiting voltage. And the upper limit is reached when the input causes the
first stage in the cascade structure to clip.
The proposed logarithmic amplifier is design and simulated with IBM7wl BiCMOS
0.18um models. For the simulation, the power supply is 1.8V and the DC bias current is
7.85mA.
(a)
(b)
Figure 4-13. Simulated AC response of (a) single-stage and (b) 9-stage limiting amplifier
81
AC response of single-stage and 9-stage limiting amplifier are shown in Figure 413, which ensures the proper operation of logarithmic amplifier at the desired frequency
(100MHz). The -3dB frequency of entire amplifier chain is 316 MHz, which also can be
estimated using Equation 4-9.
Figure 4-14 shows the logarithmic amplifier RSSI output (logarithmic output) and
the input signal dynamic range at 100MHz. At 25 qC , the log conformance is to within
±1dB for an input in the range of -80 to 0 dBV (100μV to 1V), which satisfies the system
accuracy requirement.
Figure 4-14. Simulated RSSI output and input error versus input voltage
The performance of the logarithmic amplifier at different temperatures is also
examined. From Figure 4-15, it is found that the input error (as defined in Appendix A) is
around ±1dB for temperature variation from -40 to 100 qC when input signal level is in
the range of -80 to 0 dBV, which is acceptable for measurement system specifications.
As shown in Figure 4-16, for 100MHz sinusoid input with 10mV amplitude, the
output voltage variation is around ±0.06dB for temperature varying from -40 to 100 qC .
By examining the relation between the input voltage and output voltage in Equation (4-
82
14) and (4-15), it can be shown this variation mainly results from the “proportional-tothe-absolute-temperature” (PTAT) bias tail current I0. If the bias circuit is improved to be
temperature independent, it is expected that the output variation will be further reduced.
Figure 4-15. Output error versus input voltage
Figure 4-16. Output error versus temperature
The fabrication procedure of CMOS integrated circuits is highly complex
nowadays. Most submicron MOS technology use more than 10 masks for over 100 steps
of chemical processes to deposit oxide layers and photoresist materials, to transfer mask
patterns to wafers with optical lithography, followed by chemical etchings. Even with
computer-controlled high-precision fabrication steps, some errors, for example, in mask
83
alignment, doping or implantation of targeted amounts of impurities, chemical etching of
polysilicon gate lengths of MOS transistors, and thickness control of the thin-gate oxide
layer are inevitable.
The performance of logarithmic amplifier circuit critically depends on the geometry
characteristic of MOS transistors, which can vary due to process variations and
mismatches between devices. To account for the process and mismatch variations, which
have a more vital impact on production yields as processes continue to be scaled down to
smaller geometries, Monte Carlo analysis or corner analysis can be employed to the
proposed logarithmic amplifier.
Monte Carlo analysis allows the study of how the manufacturing variations affect
the production yield of the design. Typically statistically varying parameter values are
included in device models and the shape of each statistical distribution represents the
manufacturing tolerances on devices. Monte Carlo analysis performs multiple
simulations, with each simulation using different parameter values for the devices based
on the assigned statistical distributions. The distribution of performances will provide
designer useful information to examine how manufacturing tolerances affect the overall
production yield of the design and change the design to improve the yield. However,
Monte Carlo simulations are computationally extremely expensive, especially for large
circuits.
One method of reducing the computational requirements of Monte Carlo
simulations is to perform design verification at a set of corners, which are expected to
represent the conditions that result in worst-case performances. Corner analysis looks at
the performance outcomes generated from the most extreme variations expected in the
84
process, supply voltage, and temperature values (“the corners”). With this information, it
can be determined whether the circuit performance specifications will be met, even with
the combination of random process variations in their most unfavorable patterns.
Compared to Monte Carlo analysis, the advantage of corner analysis is its relative
simplicity. However, the biggest issue with corner analysis is if the corners are not
provided, then the designer may not know what the corners actually are, which will
frequently lead to wastes of design time, or even a design impossible to realize. Since no
worst case corners are available in IBM7wl and the technology provides statistical
models, Monte Carlo analysis is preferred here for design verification.
In the first Monte Carlo analysis, the size of sample is 200 and 100MHz sinusoid
input is assumed with 10mV amplitude. Within three standard deviations (į) of the mean
(μ), simulation with mismatch only (Figure 4-17(a)) shows 1.99% variation of output
voltage. Figure 4-17(b) shows 9.97% variation of the output voltage caused by process
variation. Mismatch plus process variation led to 9.17% variation of output voltage, as
shown in Figure 4-17(c).
Figure 4-18(a), 4-18(b) and 4-18(c) shows the simulated logarithmic amplifier
output distributions with mismatch, process variation and mismatch plus process
variation from the second Monte Carlo analysis. The input signal amplitude is changed to
100mV while with same frequency 100MHz as the first analysis. Within three standard
deviations (į) of the mean (μ), simulation results show 2.35% output voltage variation by
mismatch, 11.29% output voltage variation by process variation, and 10.51% output
voltage variation by mismatch plus process variation.
85
50
45
P = 0.5280V
V= 0.0035V
Number of samples
40
35
30
25
20
15
10
5
0
0.515
0.52
0.525
0.53
0.535
0.54
0.545
Vlog (V)
(a)
60
P = 0.5267V
V= 0.0175V
Number of samples
50
40
30
20
10
0
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Vlog (V)
(b)
45
40
P = 0.5266V
V= 0.0161V
Number of samples
35
30
25
20
15
10
5
0
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0.56
Vlog (V)
0.57
(c)
Figure 4-17. Logarithmic amplifier output distributions with mismatch, process variation
and mismatch plus process variation (10mV 100MHz sinusoid input).
86
50
45
P = 0.4204V
V = 0.0033V
Number of samples
40
35
30
25
20
15
10
5
0
0.41
0.415
0.42
0.425
0.43
0.435
Vlog (V)
(a)
45
40
P = 0.4198V
V = 0.0158V
Number of samples
35
30
25
20
15
10
5
0
0.37
0.38
0.39
0.4
0.41
0.42
0.43
0.44
0.45
0.46
0.47
Vlog (V)
(b)
45
40
P = 0.4196V
V= 0.0147V
Number of samples
35
30
25
20
15
10
5
0
0.38
0.39
0.4
0.41
0.42
0.43
0.44
0.45
0.46
Vlog (V)
0.47
(c)
Figure 4-18. Logarithmic amplifier output distributions with mismatch, process variation
and mismatch plus process variation (100mV 100MHz sinusoid input).
87
Table 4-1. Logarithmic amplifier output variations under different conditions (10mV
100MHz sinusoid input)
Condition
Mean output
Output voltage
Output voltage
VLOG (V)
standard deviation (V)
variation (%)
Mismatch
0.5280
0.0035
1.99
Process Variation
0.5267
0.0175
9.97
Mismatch plus process
0.5266
0.0161
9.17
variation
Table 4-2. Logarithmic amplifier output variations under different conditions (100mV
100MHz sinusoid input)
Condition
Mean output
Output voltage standard
Output voltage
VLOG (V)
deviation (V)
variation (%)
Mismatch
0.4204
0.0033
2.35
Process Variation
0.4198
0.0158
11.29
Mismatch plus process
0.4196
0.0147
10.51
variation
The performance of the logarithmic amplifier under different conditions is
summarized in Table 4-1 and 4-2. For the Monte Carlo simulations discussed here, it is
assumed ideal external resistor and capacitor are used at the output (LPF). The results all
show very small variation of VLOG (įmax=0.0175V), demonstrating the processindependent merit of the successive detection architecture for small signal (10mV) and
large signal (100mV) measurement.
As shown in Figure 4-19, a good agreement of logarithmic amplifier output voltage
between Cadence simulation (assuming perfect matching, with nominal power supply
88
1.8V at 25 qC ) results and theory values calculated from Equation (4-16) was found and
it shows ±0.4dB output error for over 80dB input signal range (-90 to 0 dBV).
Figure 4-19. Logarithmic amplifier output voltages from Cadence simulation versus
theoretical values
4.5 Conclusions
Comparing to linear AGC-based detector, the proposed logarithmic amplifier
detector has a much wider input signal dynamic range, occupies smaller chip area (904 x
476μm including bond pads, active circuit area 500 x 185 μm). Circuit simulations were
performed under different temperature, mismatch and process variation conditions. Small
variations of the output voltage show the robustness of the logarithmic amplifier.
Temperature compensation and careful layout techniques will further improve the circuit
performance.
However, for a given accuracy requirement, frequency response of the rectifiers
and the multi-stage amplifier structure set the fundamental limit for signal detection
frequency (hundreds of MHz).
89
CHAPTER 5
DOWN-CONVERSION BASED MEASUREMENT SYSTEM
In order to develop a compact embedded system capable of measuring substrate
noise coupling over a very wide frequency span, a new technique based on frequency
translation is proposed.
5.1 Introduction
As shown in Figure 5-1, a new broadband embedded measurement technique is
proposed to measure and characterize substrate noise in RF/microwave ICs. Substrate
noise is introduced by injecting a well-defined signal from an external signal source into
the substrate. An external LO signal is supplied to the on-chip mixer at a frequency
slightly offset from the injected signal frequency. The detected signal is down-converted
to baseband and fed to low frequency external test equipment. By varying input signal
frequency and LO signal frequency correspondingly, substrate noise coupling over a very
wide frequency range can be investigated. Comparing to linear AGC-based and
logarithmic amplifier based measurement methods, the advantage of such technique is
that it can detect broadband signals.
Figure 5-1. Down-conversion based substrate noise measurement
90
This chapter is organized as follows. First, the down-conversion based
measurement technique is presented. Next, a down-conversion mixer circuit design is
described. This is followed by the test setup and measurement results that verify the
circuit performance. In addition, Appendix B introduces the fundamentals of calibration
for RF measurement, which is helpful for the understanding of the substrate coupling
measurement setup and data extraction.
5.2 Down-Conversion Mixer
The key piece of the system is the down-conversion mixer, which will translate an
incoming RF signal (from the substrate) to a lower frequency, so that an external tester
could perform signal strength detection at IF or low frequencies. Down-conversion
mixers based on signal multiplication are usually preferred because ideally they generate
only the desired intermodulation product. Also, good isolation between all three signals
(RF, LO and IF) can be achieved because of the separate ports for the different signal
sources [70].
Most down-conversion mixers are three-port devices, as shown in Figure 5-2(a).
They take two input signals: the RF signal, Asin(ȦRFt) and the LO (local oscillator)
signal, Bsin(ȦLOt). The output is a mixing product of these two inputs and is an
intermediate frequency (IF) signal:
A sin ZRF t B sin ZLOt AB
>cos(ZRF ZLO )t cos(ZRF ZLO )t @
2
(5-1).
The output contains the sum (“up-conversion”) and difference (“down-conversion”)
of the two input frequencies. For down-conversion mixers, the lower frequency (“IF”)
component is the desired one and can be obtained by low-pass filtering the mixer output
signal, as shown in Figure 5-2(b).
91
Down Conversion
Mixer
RF
IF
A sin ZRF t
B sin ZLO t
LO
ZRF ZLO
(a)
ZLO
ZRF
ZRF ZLO
Z
(b)
Figure 5-2. Multiplication based mixer and its signals spectrum
5.2.1 Introduction
Active mixers can provide large voltage gain by proper choice of device size and
bias current. By virtue of their gain, active mixers reduce the noise contributed by
subsequent stages.
Figure 5-3. Simplified mixer
The simplified version of perhaps the most popular multiplier is shown in Figure 53. RF voltage signals are first converted into current IRF and then the multiplication is
92
done in the current domain. Two possible topologies of implementing CMOS active
mixers are shown in Figure 5-4.
Vdd
VIF
M3
M6
M4
M5
M1
M2
VLO
VRF
(a)
(b)
Figure 5-4. Single-balanced and double-balanced mixers
The advantage of single-balanced mixer is its simplicity. But the major problem of
such a configuration is the LO-IF feed-through. Usually VLO is chosen large enough so
that the transistors M2 and M3 switch alternatively all of the tail current from one side to
the other at the LO frequency. Now consider a more realistic case when M2 and M3 are
both on for certain part of the period. During this time, M2 and M3 operate as a
differential pair, thus amplifying the LO signal. The large LO content at the output might
desensitize the succeeding stages. In the case of double-balanced mixer of Figure 5-4(b),
two differential pairs are connected in anti- parallel in terms of LO, providing a firstorder cancellation. Therefore, the LO terms sum to zero at the output, providing a high
degree of LO-IF isolation.
Conversion gain of a mixer is defined as the ratio of desired IF output to the value
of the RF input. For the multiplier described in Figure 5-2, ignoring the “up-conversion”
93
component in Equation (5-1), the conversion gain can be calculated as the IF output
amplitude,
is AV
AB
divided by amplitude of RF input, A. Hence the conversion gain
2
B
, which is half of the LO amplitude.
2
In practice, the LO provides a periodic switching input rather than a sinusoidal
waveform. For a square waveform with period
ZLO
, it can be expressed as:
2S
ª sin(nS )
º
cos(nZLO t ) »
«
S n 1,3,5... ¬ n
¼
4
4
4
cos(ZLO t ) cos(3ZLO t ) cos(5ZLO t ) ...
3S
5S
S
4
VLO (t )
f
¦
(5-2).
For the mixer shown in Figure 5-4(a), RF input is converted into current through
M1, thus
I RF (t )
g m1VRF cos(ZRF t )
(5-3).
Combine Equation (5-2) and (5-3), the output can be obtained as:
Vout (t )
g m1 RL
4
1
1
[cos(ZLO t ) cos(3ZLO t ) cos(5ZLO t ) ...]VRF cos(ZRF t ) (5-4).
S
3
5
Ignoring the high order harmonics of the LO signal and the up conversion term, the
output and the conversion gain of a down-conversion mixer can be shown as:
Vout (t )
AV
2
S
Vout
VRF
g m1 RLVRF cos > (ZRF ZLO )t @
2
S
(5-5)
(5-6).
g m1 RL
94
By increasing bias current or W
L
of M1, we can increase gm1 and therefore the
conversion gain of the mixer. This result also can be applied to double-balanced downconversion mixers (Figure 5-4(b)).
Noise analysis in mixers is different from traditional white noise analysis for linear
and time invariant systems. It can be shown that thermal noise in an RF input transistor is
totally transferred to output, as in a single-stage amplifier [73].
For a single-balanced mixer shown in Figure 5-4(a), during the time interval when
LO voltage is less than Vds,sat of the switching transistors M2 and M3, both transistors are
turned on and contribute to the output noise, behaving like a differential pair. The noise
from switching pairs can be solved using a stochastic differential equation [71] [72].
Simple and fast estimation techniques for mixer noise analysis are presented in [73] [74].
It is shown in [73] that the corresponding output noise PSD is:
in2
§ g ˜g ·
16kT J ¨ m 2 m3 ¸ 8kT J G (t )
© g m 2 g m3 ¹
where G (t )
2
(5-7).
g m 2 ˜ g m3
, gm is the gate transconductance, k is Boltzmann’s constant, T
g m 2 g m3
is the absolute temperature, and Ȗ is 2/3 for long-channel transistors but can be higher for
short-channel devices.
Increasing the channel length of switching transistors is desirable because this
decreases gm2 and gm3, reducing the output noise contribution. However, larger transistors
size will introduce more parasitic capacitance, which can degrade the mixer performance
at high frequencies and can represent a larger load for the circuit driving the mixer. Large
LO amplitude increases the conversion gain and also reduces the noise contribution of
switching pair.
95
5.2.2 Circuit Design
Schematic of the double-balance down-conversion mixer used in this design is
shown in Figure 5-5. This mixer is employed as down-conversion sensor, with one input
terminal capacitively coupled to the substrate contact (“detection node”) through a MOS
cap and the other tied to a “quiet” reference.
Figure 5-5. Down-conversion mixer schematic
5.3 Verification of Mixer Design
The down-conversion mixer shown in Figure 5-5 was fabricated in the IBM7wl
BiCMOS 0.18μm process. The microphotograph of mixer test structure is shown in
Figure 4-14. The whole chip area is 1016 x 576 μm, which is mostly limited by bond
pads. The core active area is only 232 x 296 μm and takes around 12% of the entire chip
area. The input coupling and bypass capacitors are 9.2pF each. The poly resistors Rb1 and
96
Rb2 are 100Kȍ and isolate the RF input bias from RF signal source. The 50ȍ resistor Rrf
is also integrated on-chip for broadband input matching.
GND
LO+
LO-
GND
GND
RF
GND
IF
Out+
Active Area
232×296 μm2
IF
Out-
GND
Ref
GND
Ibias
VRF
GND
VDD
GND
Figure 5-6. Microphotograph of the down-conversion mixer
5.3.1 Test Setup and Calibration
The DC measurement is quite easy to set up. By applying correct DC biases to the
corresponding pads through DC probe, one can observe the total bias current and output
bias voltage. The bias current is tuned by adjusting a potentiometer connected to Ibias pad.
A star grounding scheme is used to avoid ground loop problem.
BALUN
Bias T
RF
Figure 5-7. Mixer measurement setup
97
The characterization of a mixer is complicated procedure and the basic
measurement setup is shown in Figure 5-7. Unlike DC measurement, RF measurement
does not give instant, accurate results. All the elements on the signal propagation path
will bring signal loss and reflection; hence the actual input signal power into the DUT
will not be equal to the one coming out of the signal generator. Calibration has to be
employed in order to obtain actual incident power and accurate experiment data. The oneport SOL calibration scheme is discussed in Appendix B.
Since the mixer output impedance and spectrum analyzer input impedance is not
matched, an off-chip OPAMP based external buffer is used to provide isolation between
mixer output and spectrum analyzer.
(a)
(b)
Figure 5-8. External buffer
98
The configuration of an OP-AMP based buffer is shown in Figure 5-8(a), low
distortion differential driver (AD8138 from Analog Devices) and differential driver
evaluation board are used in actual buffer design (Figure 5-8(b)). This driver has low
output harmonic distortion of -85dBc at 20MHz offset, low input voltage noise of 5nV/¥Hz, and 3-dB bandwidth of 320MHz. For single-ended input signal, the buffer
input impedance and the voltage gain can be calculated as follows:
Rin
AV
RG
RF
1
2( RG RF )
Vout
Vin
(5-8)
RF
4 RG
(5-9).
A high impedance probe can also be used as output buffer and it provides zeroing
control for more accurate measurement result. In our measurement, a GGB picoprobe
(Model 34A) is employed as the external buffer. The input impedance is approximately
10Mȍ shunted by 0.1pF with a probe rise-time of around 120ps. It attenuates the output
signal by a factor of 20:1 and its output was designed to plug into a 50ȍ input impedance
instrument. The 3-dB bandwidth of this high impedance probe is 3GHz.
5.3.2 Measurement Results
For the test chip measurement, the power supply is 2.5V and the DC bias current is
1mA. The external LO power applied to one LO port is about 2dBm, equivalent to a
peak-to-peak voltage swing of 0.8V.
At the RF port of the down-conversion mixer, the measured reflection coefficient
(S11) is below -10dB from 5GHz to 20GHz, as shown in Figure 5-9. It shows good input
99
impedance matching over wide frequency span, which is achieved by the use of on-chip
50ȍ resistor.
Figure 5-9. Mixer Reflection Coefficient (S11) at RF Port
The second measurement is to determine the linearity of the mixer. It is very
important because the mixer is the first block of the system and it determines sensitivity
of the overall system. By obtaining the output versus input characteristic of the mixer, RF
input signal level can be predicted from the measured IF output.
Measurement results for input signals at different frequencies (5GHz to 20GHz) are
shown in Figure 5-10. Note that the sensitivity (from less than -60 dBm to greater than
2dBm) of the mixer is more than adequate to meet the initial system specification
mentioned in Chapter 2. The voltage conversion gain of the mixer is around 10dB and the
measured LO-RF isolation is below -37dB up to 20GHz.
100
Figure 5-10. Mixer output linearity versus input signal level
5.4 Summary and Conclusions
The successful development of down-conversion mixer as substrate noise detector
has shed light on the future of RF embedded substrate noise coupling measurements. This
technique can be applied to substrate parasitics extraction for RF/microwave integrated
circuits. The applications of this embedded measurement system will be discussed in the
next chapter.
101
CHAPTER 6
MODELING AND VERIFICATION METHODOLOGY FOR SUBSTRATE
COUPLING EFFECTS
The successful development of a down-conversion mixer as substrate noise
detector has been demonstrated in previous chapter.
In this chapter, a down-conversion based embedded substrate noise measurement
system and its application are presented as follows: first, the test structures designed and
fabricated for the investigation of substrate coupling under different coupling conditions
(e.g., coupling with different separation distances at different frequencies) is described,
followed by the on-wafer measurement results of the test structures up to 20GHz. Next,
the extraction of the substrate macromodel and the determination of its element values
are discussed in detail. The results obtained from extracted model will be verified through
comparison to experimental results and error analysis results will be shown. Finally,
application of this extracted model on handling multiple-contact coupling problem will
be discussed.
6.1 Test Structures for Substrate Coupling Investigation
Special test structures were designed and fabricated in IBM7wl 0.18μm
technology, to investigate substrate coupling under different conditions by on-wafer
measurement. As shown in Figure 6-1, the test structures include substrate noise injection
(“aggressor”) points on the left and one substrate contact on the right as detection node
(“victim”) connected to the mixer (“embedded measurement”) on the same chip. By
changing test signal injection location (S1-S10), substrate coupling distance between the
injection point and detection node will be changed. Also, by changing test signal
frequency, the effect of operation frequency on substrate coupling can be investigated.
102
S6
Chip edges
S5
“Aggressors”
S7
S4
S8
S3
“Victim”
S9
S2
D
S10
S1
Figure 6-1. Test structures for embedded substrate noise measurement
Figure 6-2 shows the microphotograph of fabricated test chip with test structures
and embedded mixer detector. The test chip measured 2000 x 2000 μm. All the substrate
contacts used in the test structures are of the same size 20 x 20 μm, and the separation
distance between these substrate contacts is from 220μm to 1200μm. The resistivity of
the lightly-doped P- substrate is 11-16ȍ-cm. The thickness of the chip is 250μm with
non-conductive epoxy on its backside. A sheet of glass with sufficient thickness (1000
μm) is place between the chip and the chuck of the probe station to avoid any additional
interaction. Thus the backside of the chip can be treated as well insulated.
103
Figure 6-2. Microphotograph of the test chip containing the substrate noise test structure
Figure 6-3. Measurement setup for substrate coupling investigation
Figure 6-3 shows the simplified measurement setup for test-structure/embedded
mixer detector including the probe pads. One port of the test structure is driven by the RF
signal (V1) from an external signal generator (HP ESG series signal generator E8257B,
104
250kHz-40GHz) through bond pad S1, and the other port (V2) is connected to the input of
the mixer. The output of the mixer VO will be measured on a spectrum analyzer (HP8563E spectrum analyzer, 30Hz-26.5GHz) with the high-impedance probe (GGB
picoprobe Model 34A, DC-3GHz) described in previous chapter.
6.2 Substrate Model Extraction
Before constructing an equivalent circuit model, substrate coupling test structures
are simulated using the electromagnetic tool HFSS (High Frequency Structure Simulator
by Ansoft).
The whole 3-D simulation model is shown in Figure 6-4. The radiation boundary
(air) is defined to allowed waves to radiate infinitely into far space. Inside the air box is
the test chip model, which consists of (from top to bottom): silicon-dioxide (passivation
on top of the chip), silicon (the wafer die under test, including substrate contacts, p-well
and p-substrate), glass. The thickness of each level is given as physical dimensions which
are obtained from MOSIS [75]. Beneath the glass is a perfect conductor plane,
representing the metal chuck of the probe station.
From the top and cross section views of the simulated structure, it can be observed
that most of the radiation patterns of the coupling signal die out within the test structure
model and only a negligible fraction reaches deep into the substrate, which means the
back plane connection condition has little effect on the simulation results. The HFSS
simulation result confirms that the glass at the bottom isolate the back plane of the test
chip from the metal chuck of the probe station in the embedded measurement. Thus in the
following analysis, a floating back plane for the test chip is assumed. The equivalent
circuit model based on this assumption will be discussed next.
105
Figure 6-4. HFSS model of test structure
The substrate test structure discussed here can be described by a two-port
equivalent circuit of Figure 6-5, where G12=G21 is assumed because of reciprocity and
YMX is the input admittance of the embedded mixer detector. From the equivalent circuit,
G12, the transadmittance between two substrate contacts, which represents the substrate
coupling, can be calculated as,
G12
V2
˜ G12 G22 YMX V1
(6-1).
Y-parameters of the test structure are calculated from a measured set of Sparameters, which also yields the output admittance G22 of the test structure. The
substrate contacts in all test structures are of the same size and shape, so G11=G22. Then
the two-port Y-parameters for the equivalent circuit are given by:
106
Y
§ y11
¨
© y21
y12 · § G11 G12
¸ ¨
y22 ¹ © G12
G12
·
¸
G22 G12 ¹
(6-2).
Figure 6-5. Equivalent circuit of the test structure
From Equation (6-2), G12 and G22 can be calculated from Y-parameters as:
G12
y12 , G22
y22 y12
(6-3).
Combining Equation (6-1) and (6-3), Equation (6-1) can be rewritten as:
G12
V2
˜ y22 YMX V1
(6-4).
For the measurement described below, in the first step, the S-parameter
measurement is performed, which yields the output admittance y22 of the test structure.
An additional deembedding step is used to remove the influence of the pad capacitances
and interconnection inductances. In the third step, the amplitudes of input signal V1 and
mixer output signal VO are measured.
V2
V
can be calculated from 2
V1
V1
§ V2
¨
© VO
· § VO ·
¸ ˜ ¨ ¸ and
¹ © V1 ¹
VO
is the voltage conversion gain of embedded mixer detector, which is already obtained
V2
107
from the measurements discussed in the previous chapter. Isolation between two substrate
contact, I, is defined here as
I
20 ˜ log
V2
V1
(6-5).
As discussed in detail in [32], a semi-physical equivalent circuit (shown in Figure
6-6) is used to model G12 in the test structure. A capacitor C12, which represents the
dielectric behavior of the bulk substrate and depends on the substrate permittivity H si , is
shunted to the substrate resistance R12. Note that C12 and R12 are related by
C12
H si U sub / R12
(6-6),
where H si and U sub are the permittivity and resistivity of the bulk substrate, respectively.
JG
This can be derived from Maxwell’s equations considering the electrical field E
JG
determines both the curry density J
JG
E / U (corresponding to 1/R) and the displacement
JG
JG
current density D H E (corresponding to C).
G 12
1
jZ C 12
R12
Figure 6-6. Semi-physical equivalent circuit for G12
For given substrate contact size, G11 and G22 have constant values and G12 is a
function of the separation distance (d) between the two contacts and the frequency of
injected signal (f). Since R12 increases as the distance d is increased, the variation of R12
with d can be characterized efficiently as a polynomial in d, i.e.,
R12
k0 k1d k2 d 2 ... km d m
(6-7),
108
Where ki and the polynomial order, m can be determined by first pre-computing the
actual parameters and then using a suitable curve fitting technique. The curve fitting is
required only once for a given process. The resulting polynomials can then be stored in a
library and used for the extraction of other different structures in the same technology.
6.3 Measurement Results
In this section, the results obtained with the embedded measurement technique are
presented and compared to the simulation results based on the semi-physical model
discussed in Section 6.2.
Figure 6-7 shows the measured and simulated isolation for the test structures in
Figure 6-1. Due to space limitations, only some of the measurement results are shown
here. A very good agreement is observed for different separation distances with
frequency up to 20GHz. It is clear from the figure that the isolation is about 5dB lower
when frequency increases from 5GHz to 20GHz. The isolation is weakly dependent on
the separation distance, improving about 5dB when the distance increases from 220um to
1200um. This is so because the value of R12 is comparable to the reactance of C12 in this
frequency range and C12 starts to play a role for substrate coupling. The simulation result
of isolation based on macromodel is shown again in Figure 6-8.
As shown in Figure 6-9, the good agreement of |G12|, the magnitude of G12,
between measurement and simulation results demonstrates the suitability of embedded
substrate coupling measurement and the accuracy of extracted macromodel.
The macromodel proposed in the previous sections has been validated through
measurement of the test chip described above up to 20GHz. From simulation results
based on extracted macromodel, the effects of separation distance (d) and operation
frequency (f) on substrate coupling are clearly shown (Figure 6-8).
109
-35
Meas:220um
Sim: 220um
Meas:1200um
Sim: 1200um
Isolation (dB)
-40
-45
-50 9
10
10
10
10
11
Frequency (Hz)
Figure 6-7. Comparison of measurement and simulation results of isolation for different
separation distances between two substrate contacts
Figure 6-8. A two-dimension view of isolation versus separation distances and
frequencies
110
4
x 10
-4
Meas:220um
Sim: 220um
Meas:1200um
Sim: 1200um
3.5
G12(mag) (: -1 )
3
2.5
2
1.5
1
0.5 9
10
10
10
10
11
Frequency (Hz)
Figure 6-9. Comparison of measurement and simulation results of |G12| for different
separation distances between two substrate contacts
6.4 Discussions
6.4.1 Effect of Measurement Errors on Model Extraction
All measurement systems, including vector network analyzer (VNA) employed in
our measurement, can be plagued by three types of measurement errors: systematic
errors, drift errors and random errors. Systematic errors are caused by imperfections of
the test equipment and test setup. Drift errors occurs when a test system’s performance
changes after a calibration has been performed. Random errors vary randomly as a
function of time and they are not predictable.
Systematic errors can be characterized through calibration (i.e., SOL calibration)
and mathematically removed after the actual measurement. Drift errors are primarily
caused by temperature variation and assumed to be already minimized by periodic
recalibration. The main contributors to random errors are instrument noise (i.e., sampler
111
noise, IF noise floor) and connection repeatability. Therefore they cannot be removed by
calibration, and the effect of random errors on model extraction must be evaluated.
It is not uncommon to see 2% factory uncertainty [80] on measurement equipment
after calibration process. From Equation (6-1), assuming 2% variations on
V2
, y22 and
V1
YMX, the errors of G12 are shown in Figure 6-10. Within five standard deviations of the
mean, magnitude error of |G12| is less than ±0.35dB, which compares reasonably to the
random errors.
Worst case error
0.5
0.4
0.3
' |G12| (dB)
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
ǻ mag.
-0.5
10
9
10
10
Frequency (Hz)
Figure 6-10. Errors in|G12| because of random errors in measurement
6.4.2 Multiple-contact Coupling Problem
The substrate noise coupling model described in previous sections is originally
developed for two contacts. Impedance values are extracted for a pi-network that includes
a cross coupling impedance between the two contacts (“ports”). However, substrate noise
coupling involves multiple contacts (“ports”), which are illustrated in Figure 6-11, i.e.,
112
the effect of D3 must be taken into account when considering the substrate coupling
between D1 and D2.
Figure 6-11. Substrate noise coupling between multiple contacts
By using two-port Z parameters extracted from each contact pairs, a lumped
impedance network [76] can be used to model coupling between multiple contacts, as
shown in Figure 6-12. For example, the process for an N contact problem consists of the
following steps. First, two-port Z parameters are extracted by considering one contactpair at a time. An N x N Z-matrix is then constructed, whose entries corresponding to the
two contacts (i.e., i and k) are given in Equation (6-8). Finally, the impedance values will
be calculated from the overall Z-matrix.
Figure 6-12. Substrate impedance network between multiple contacts
113
Z
§ .. ..
¨
¨ .. zii
¨ .. ..
¨
¨ .. zik
¨ .. ..
©
.. ..
.. zik
.. ..
.. zkk
.. ..
..
..
..
..
..
.. ·
¸
.. ¸
.. ¸
¸
.. ¸
.. ¸¹
(6-8).
A problem with this impedance determination method from Z-matrix is that beyond
a certain size, the matrix becomes too large to solve. For a practical SoC IC, the
computation time required will be prohibitively long to attempt a full scale circuit
simulation. Partitioning the full matrix into smaller sections can help to make quick
approximations [77]. By ignoring the impact of distant contacts, coarse-fine
approximation techniques [49] can be employed to improve simulation efficiency. Other
acceleration techniques such as multi-pole method [78], FFT method [79] are also
reported.
6.5 Conclusions
The goal of embedded substrate test is to generate a macro model out of finite
simple test structures, aiming at results of general validity. This model can be used as a
guideline for SoC designers at the early stage of system integration, providing a more
intuitive view of substrate noise coupling. A simple and accurate macromodel based on
curve fitting has been described and it agrees quite well with the embedded measurement
results, up to 20GHz. This model is scalable with separation distance and coupling signal
frequency. Techniques of adapting extracted two-port macromodel to solve multi-port
problem are also discussed.
114
CHAPTER 7
SUMMARY AND FUTURE WORK
7.1 Summary
This research work focused on embedded substrate noise coupling measurement
circuits for RF/microwave integrated circuits, as one of the alternative solutions for IC
testing cost reduction. First, fundamental background knowledge describing substrate
noise coupling was introduced. Second, several existing embedded measurement and
substrate modeling methods were investigated and a new embedded test concept for
RF/Microwave circuits was proposed. The designs, simulation and measurement results
of the necessary components for the proposed embedded substrate measurement were
discussed. These included an AGC based detector, logarithmic amplifier based detector
and down-conversion mixer based detector. Finally, an application of this embedded
measurement system was described, and a semi-physical macromodel based on
experiment data was presented.
The major contributions of this dissertation work are summarized as follows. Based
on the fundamentals of substrate noise measurement and existing embedded test methods,
the conception of embedded noise measurement for high-frequency circuits was
proposed, which was mainly composed of an off-chip signal generator plus test circuitry
(detector) integrated with the test structures for substrate parameter extraction. After an
external signal source launched a test signal onto the wafer, the on-chip signal detector
received the signal from the output of test structure, and then extracted the useful
information into baseband signals, which were finally transmitted back to the external
low-frequency tester. Some of the potential advantages included: broad-band and widedynamic range signal detection, excellent input/output port isolation, versatile
115
applications for different technologies, easy measurement setup and hence test cost
reduction.
A low-frequency on-chip substrate noise measurement test vehicle based on
constant-settling time AGC system was designed. A 10MHz linear (THD ~1%) variable
gain amplifier with 40dB gain tuning range was designed and simulated. Op-amp based
peak detector, loop filter and voltage reference circuit were designed and simulated. Due
to unexpected oscillation problem with on-chip bias circuit, the evaluation of the overall
system was impossible. On the other hand, the complexity and large chip area overhead
(1500 x 1300μm) of the system prevented the application of this measurement scheme.
A 100MHz CMOS pseudo-logarithmic amplifier detector based on successivedetection architecture was designed and simulated. Although a wide-dynamic range (-80
to 0dBV), good detection accuracy (log conformance within r 1dB), and a much smaller
overhead (500 x 185μm) were achieved, the frequency response of amplifier and rectifier
sets the upper limit for the frequency range of signal detection.
In order to satisfy the requirement of a high dynamic range and broad band signal
detection, a down-conversion based detection scheme was proposed. A CMOS downconversion mixer detector was designed, and the measurement results showed it could
work with signal up to 20GHz and had a dynamic range over 70dB, with very compact
size (232 x 296μm).
Based on the success of the development of down-conversion detection circuit, a
practical application for embedded substrate noise measurement was demonstrated. First,
isolation measurements on test structures were performed. A semi-physical macromodel
was then extracted from the experimental data and it was scalable with separation
116
distance and coupling signal frequency. The application of this macromodel to multiplecontact coupling problem was also discussed.
7.2 Future Work
The ultimate goal of our research was to realize a substrate noise coupling
measurement system on-chip. The successful development of down-conversion mixer as
substrate noise detector has demonstrated the feasibility of the embedded system for
substrate noise measurement. However, the detected signal amplitude measurement is
performed by external tester (spectrum analyzer) and external buffer (high-impedance
probe) has to be used for impedance matching purpose.
One possible improvement of the proposed embedded substrate noise measurement
scheme is to add on-chip signal amplitude extractor (logarithmic amplifier) as shown in
Figure 7-1. In this way, measurement setups for substrate coupling will be greatly
simplified – only DC measurement will be required at the output. The robustness of
logarithmic amplifier as a signal amplitude extractor versus temperature and process
variations is discussed in detail in Chapter 4.
Figure 7-1. Improved down-conversion based substrate noise measurement scheme
The improved embedded substrate coupling measurement system is simulated with
IBM7wl BiCMOS 0.18um models. The simulated logarithmic amplifier outputs for
sinusoid input signals at different frequencies (10GHz to 20GHz) are shown in Figure 7-
117
2. The frequency offset between the injected signals and LO is 100MHz, so the frequency
of input signals to the logarithmic amplifier is 100MHz. An over 80dB (-90 to -10dBV)
input signal dynamic range is achieved and the output of logarithmic amplifier is very
consistent (dB) under different frequencies of input signal (Figure 7-3).
Figure 7-2. Logarithmic amplifier output versus input voltage
Figure 7-3. Output error versus input voltage
118
The down-conversion mixer detectors can be inserted on virtually any nodes of
interest in the SoC with good isolation to the circuits under investigation. One possible
application of embedded detectors (mixers) plus an on-chip signal amplitude extractor
(logarithmic amplifier) is shown in Figure 7-4. Each mixer “MX” output is connected
through a switch “SW” with control logic that effectively isolates the mixer output from
the logarithmic amplifier input (i.e., T-switch discussed in Chapter 3), if the mixer is to
be de-activated.
Figure 7-4. Example of down-conversion based embedded substrate noise measurement
Within the conception of the proposed embedded substrate noise measurement, a
few possible future tasks are suggested as follows.
The proposed embedded test scheme is only applied to unshielded substrate
coupling (direct coupling between two substrate contacts without any isolation structures)
measurement in a high-resistivity substrate. And the coupling behaviors in different
119
substrates (i.e., low-resistivity substrate, SOI substrate) under different shielding
conditions (i.e., p+/n+ guardrings, deep trench) are worth further investigation.
Macromodel extraction based on experimental data can be extended to predict the
coupling for different CMOS processes and to evaluate the effects of different substrate
noise isolation structures. This model also needs to be validated in larger circuit
examples.
Another possible application for this embedded test scheme is package/board
characterization. By performing two separate embedded measurements, the effects of
package/board induced signal coupling can be characterized properly.
120
APPENDIX A
ERROR ANALYSIS FOR PSEUDO-LOGARITHMIC AMPLIFICATION
A pseudo-logarithmic transfer curve is defined to be an approximation to an ideal
logarithmic curve. A simple example of approximation to a logarithmic curve is shown in
Figure A-1. The logarithmic curve is approximated by a series of line segments of
varying length and slope. For a fixed range of the original curve, more line segments
Vout (V)
improve the approximation.
Vin (V)
Figure A-1. Piecewise linear approximation to a logarithmic curve
Shown in Figure A-2 is the successive-detection architecture which is studied and
discussed in this section. The figure is repeated (Chapter 4, Figure 4-3) here for
convenience. Figure A-3 [66] shows the composite output response of a pseudologarithmic amplifier comparing with a true logarithmic response. We can also take it as
a semi-logarithmic version of Figure A-1 (with logarithmic response at the breakpoints).
121
The logarithmic curve becomes linear and the straight-line segments appear curvy on
such a scale. The true logarithmic curve can be shown as
Vout
K1 log( K 2Vin )
where K1
VL
, K2
log( AV )
Vin
(A-1)
AV n 1
.
VL
AV2Vin
AVVin
1st
2nd
AVmVin=VL
mth
VL
VL
VL
(N-1)th
(m+1)th
Nth
Vin
Lim Out
Vin
AV2Vin
AVVin
AVmVin=VL
VL
VL
VL
Low
Pass
Filter
Log Out
VLOG
Figure A-2. Signal flow of a successive-detection logarithmic amplifier
When
VL
AV
N m 1
d Vin d
VL
or mVL d Vout d (m 1)VL , the equation describing any
AV N m
arbitrary straight-line segment of the composite logarithmic response is
Vout
AV n m 1
Vin
1
(m )VL
AV 1
AV 1
(A-2)
where n is the total number of line segments (limiting amplifier stages), and m is an index
of the line segment (limiting amplifier stage) being discussed.
Select any output voltage Vout and we can solve Equation (A-1) and (A-2) for ideal
logarithmic input voltage, Vin ,log and the actual input voltage of pseudo-logarithmic
amplifier, Vin ,actual . Input error (in dB) is defined by:
122
§V
20 log ¨ in , actual
¨ Vin ,log
©
Error
·
¸¸
¹
(A-3)
Vout
nVL
(m 1)VL
mVL
2VL
VL
VL
AV N
VL
AV N 1
...
VL
AV
Nm1
VL
AV N m
...
VL
AV
Vin
Figure A-3. Characteristics of an N-stage pseudo-logarithmic amplifier
VL
When
Vin
'
Vout '
AV
N m 1
d Vin d
VL
or mVL d Vout d (m 1)VL , define
AV N m
AV N m 1
Vin
VL
(A-4)
Vout
m
VL
(A-5)
Rewriting Equation (A-1) and (A-2), we can get
Vin,log '
Vin , actual '
AV Vout
'
(A-6)
( AV 1)Vout ' 1
(A-7)
123
Now the input error can be express as
Error
'
§V
·
20 log ¨ in , actual' ¸
¨ Vin ,log ¸
©
¹
ª ( AV 1)Vout ' 1 º
20 log «
»
'
AV Vout
¬«
¼»
(A-8)
From inspection of Figure A-2, we can see that maximum input errors occur where
the slopes of the two curves are equal. As shown in Figure A-3, the input error decreases
for smaller values of single stage gain AV.
Maximum Error (dB)
10
10
10
10
1
0
-1
-2
0
5
10
15
20
25
Single stage gain (dB)
Figure A-4. Maximum input error as a function of single stage gain
124
30
APPENDIX B
CALIBRATION FOR ONE-PORT MEASUREMENT SYSTEM
Unlike digital multimeter, a microwave s-parameter measurement system (i.e., a network
analyzer) does not give accurate data instantaneously. Calibration must be performed in order to
guarantee the accuracy and repeatability of measurements. Calibration procedure will also create
a well defined reference plane at the interface of the measurement system and the DUT (Figure
B-1).
Reference Plane
Figure B-1. S-parameter measurement with calibration setting the reference plane
For on-wafer measurement we will define the reference plane between the microwave
probe tips and the landing bond pads which connect to the DUT. The other parts in the
measurement system including cables and test fixtures can be calibrated using standards that are
traceable to the National Bureau of Standards (NBS).
The calibration of the connection path as a whole can be done with one-port (Short-OpenLoad, SOL) calibration method introduced by Wijnen [81]. Figure B-2 shows a flow graph of a
hypothetical error adapter, representing the error model for one-port measurement system. The
signal flow is visualized by the arrows: a0 and b0 are the incident and reflected waves detected
125
by the test set (i.e., at the output of coaxial cable); a1 and b1 are the waves associated with the
DUT (i.e., at microwave probe tips). Four error terms are used to define the system errors:
Directivity error, e00: represents all the signals that are reflected before they could reach
the reference plane of microwave probe tips.
Frequency response errors, e10 and e01: represent the errors caused by a non-ideal signal
path from test set to the probe tips (i.e., cable loss).
Port match error, e11: represents the reflected signal as a result of non-ideal effective
source impedance when looking back into the reference plan of probe tips.
*L
Figure B-2. Flow graph of the hypothetical error adapter
The error terms can be obtained by the calibration with open, short and load standards. In
practice, e10 and e01 cannot be distinguished from each other and will be used together as a
product. The measured data at the output of the cable are:
* m _ open
e00 e01e10
1 e11
(B-1)
* m _ short
e00 e01e10
1 e11
(B-2)
* m _ load
e00
(B-3)
The error terms can now be calculated using Equation (B-1), (B-2) and (B-3):
126
* m _ load
e00
e11 1 2
e01e10
2
(B-4)
* m _ load * m _ short
* m _ open * m _ short
(B-5)
(* m _ open * m _ load )(* m _ load * m _ short )
* m _ open * m _ short
(B-6)
Applying simple flow graph rules to Figure B-2, the measured reflection coefficient * m is
equal to:
*m b0
a0
e00 e01e10
* actual
1 e11* actual
(B-7)
Solving for * actual , (B-7) can be rewritten as:
* actual
* m e00
e11 (* m e00 ) e01e10
(B-8)
Substitution of Equation (B-4), (B-5) and (B-6) into (B-8) leads to the following equation:
* actual
* m * m _ load
* m * m _ load 2(* m * m _ open )
* m _ load * m _ short
(B-9)
* m _ open * m _ short
The power delivered to the DUT can be derived from the error model as follows. We know
the signals b0 and b1 in Figure B-2 are
b1
a0 e10 a1e11
Æ
b1
a0 e10
1 * actual e11
The available power from the source is Pavailable
(B-10)
2
a0 , and the power delivered to the DUT
is
PDUT
2
b1 a1
2
2
§
a1 ·
b1 ¨1 2 ¸
¨
b1 ¸¹
©
2
b1
2
1 *
127
2
actual
(B-11)
From Equation (B-10), we can get
PDUT
b1
2
1 *
2
actual
Pavailable
e10
1 * actual e11
128
2
1 *
2
actual
(B-12)
APPENDIX C
EMBEDDED SUBSTRATE COUPLING MEASUREMENT AND SEMI-PHYSICAL
MACROMODEL EXTRACTION
C.1 Embedded Substrate Coupling Measurement
The simplified measurement setup for test-structures plus an embedded mixer detector is
shown in Figure C-1. The figure is repeated (Chapter 6, Figure 6-3) here for convenience. One
port of the test structure is driven by the RF signal (V1) from an external signal generator (HP
ESG series signal generator E8257B 250kHz-40GHz) through bond pad S1, and the other port
(V2) is connected to the input of the mixer. The output of the mixer VO will be measured on a
spectrum analyzer (HP-8563E 30Hz-26.5GHz spectrum analyzer) with the high-impedance
probe (GGB picoprobe Model 34A) described in previous chapters.
External
LO
Chip Edge
Test
Structure
S1
External
Signal
Source
V1
Mixer
V2
To
Vo high-imp. probe &
spectrum analyzer
50Ÿ
G
Figure C-1. Measurement setup for embedded substrate coupling detection
The first measurement is to characterize the S-parameters of test structures. The test
structures were measured using two ground-signal-ground (GSG) microwave probes (Cascade
Microtech Microprobe ACP40, DC-40GHz), contacting at port1 (V1) and port2 (V2) as
indicated in Figure C-1. A symmetrical layout was chosen so that a good contact of the probes
can be ensured by comparing the reflection at both ports. The mandatory connections of the
ground pads are realized in the top metal levels with thick oxide layer (typical oxide thickness is
129
4 μm for metal6 and metal7), so that the interaction with the substrate is minimized. The Sparameters are measured from 1GHz to 20GHz with a HP-8510C vector network analyzer
(30Hz-26.5GHz). Accurate calibration was ensured by Short-Open-Load (SOL) method
discussed in Appendix B. The power of test signal delivered to the test structure can be
calculated using Equation (B-12).
Figure C-2. Equivalent circuit of the test structure
Figure C-2 shows the equivalent circuit of the test structure in the measurement described
above. The two-port Y-parameters (between V1 and V2) for the equivalent circuit are given by:
Y
§ y11
¨
© y21
y12 · § G11 G12
¸ ¨
y22 ¹ © G12
G12
·
¸
G22 G12 ¹
(C-1).
Y-parameters of the test structure are calculated from the measured S-parameters, which
are given by:
y11
(1 S11 )(1 S22 ) S12 S 21
'
(C-2)
y12
2S12
'
(C-3)
y21
2S21
'
(C-4)
130
y11
(1 S11 )(1 S22 ) S12 S 21
'
where '
(1 S11 )(1 S22 ) S12 S 21 .
(C-5)
The substrate contacts in our test structure are of the same size and shape and assume
symmetrical layout, so G11=G22. Then from Equation (C-1), G12 and G22 can be calculated from
Y-parameters as:
G12
y12 , G22
y22 y12
(C-6).
DUT
Pad
Pad
Ytot
Yopen
Ypad+ YInt
YDUT
Gnd
Ypad+ YInt
Gnd (b)
(a)
Figure C-3. De-embedding bondpad and interconnection
An additional measurement step is performed to remove the influence of the bondpad
capacitances and interconnection inductances. Figure C-3(a) shows a simplified diagram of onwafer input admittance measurement of a DUT. The DUT is connected to external equipment
through interconnection and a bondpad. The measured admittance (Ytot) is the total admittance of
bondpad (Ypad), interconnection (Yint) and the DUT (YDUT). In order to characterize the true
131
admittance of a DUT, a “dummy” open-structure (Figure C-3(b)) with just the bondpad and the
interconnection, is carefully designed and measured. By measuring the admittance of this openstructure (Yopen), the admittance of bondpad and interconnection is de-embedded, hence the
actual admittance of the DUT can be easily calculated as:
YDUT
Ytot (Ypad Yint ) Ytot Yopen
(C-7).
The third measurement is to characterize the down-conversion mixer. By measuring the Sparameters and performing the de-embedding measurement step described above, input
admittance of the mixer (YMX) can be accurately obtained. Mixer linearity (conversion gain)
measurement is also performed, as discussed in Chapter 5.
From Figure C-2,
V2
V
can now be calculated from 2
V1
V1
§ V2
¨
© VO
· § VO ·
VO
is the voltage
¸ ˜ ¨ ¸ and
V
V
2
¹ © 1¹
conversion gain of embedded mixer detector. The transadmittance between two substrate
contacts, G12, which represents the substrate coupling, can be calculated as,
G12
V2
˜ G12 G22 YMX V1
(C-8).
Combining Equation (C-6) and (C-8), Equation (C-8) can be rewritten as:
G12
V2
˜ y22 YMX V1
(C-9).
C.2 Semi-physical Macromodel
As discussed in detail in Chapter 6, a semi-physical equivalent circuit (shown in Figure C4) is used to model G12 in the test structure. A capacitor C12, which represents the dielectric
behavior of the bulk substrate and depends on the substrate permittivity H si , is shunted to the
substrate resistance R12. Note that C12 and R12 are related by
C12
H si U sub / R12
(C-10),
132
where H si and U sub are the permittivity and resistivity of the bulk substrate, respectively.
G 12
1
jZ C 12
R12
Figure C-4. Semi-physical equivalent circuit for G12
For given substrate contact size, G11 and G22 have constant values and G12 is a function of
the separation distance (d) between the two contacts and the frequency of injected signal (f).
Since R12 increases as the distance d is increased, the variation of R12 with d can be characterized
efficiently as a polynomial in d, i.e.,
R12
k0 k1d k2 d 2 ... km d m
(C-11),
where ki and the polynomial order, m can be determined by first pre-computing the actual
parameters and then using a suitable curve fitting technique.
The substrate resistances (R12) obtained from macromodel simulation and embedded
measurements are plotted in Figure C-5 as a function of the separation distance between two
substrate contacts in the test structure. The values of parasitic capacitances (C12) associated with
substrate resistance (R12) are shown in Figure C-6, also as a function of the separation distance.
The macromodel proposed Chapter 6 has been validated through measurement of the test
chip described above up to 20GHz. Typical values of R12 and C12 as a function of separation
distance are summarized in Table C-1 and C-2. The good agreement of R12 and C12, between
embedded measurement and macromodel simulation results demonstrates the suitability of
embedded substrate coupling measurement and the accuracy of extracted macromodel.
133
15
14
13
12
R12 (k: )
11
10
9
8
7
6
5
0
200
400
600
800
1000
1200
Separation Distance (P m)
Figure C-5. R12 versus different separation distances between two substrate contacts
4
3.5
C12 (fF)
3
2.5
2
1.5
0
200
400
600
800
1000
1200
Separation Distance (P m)
Figure C-6. C12 versus different separation distances between two substrate contacts
134
Table C-1. Typical values of R12 as a function of separation distance
Separation (μm)
Measurement (kŸ)
Macromodel (kŸ)
Error (dB)
220
8.36
8.20
-0.168
484
11.15
11.17
0.016
656
12.22
12.17
-0.036
890
13.29
13.25
-0.026
1156
14.20
14.18
-0.012
Table C-2. Typical values of C12 as a function of separation distance
Separation (μm)
Measurement (fF)
Macromodel (fF)
Error (dB)
220
2.72
2.83
0.344
484
2.04
2.01
-0.129
656
1.87
1.89
0.092
890
1.71
1.73
0.101
1156
1.60
1.61
0.054
As discussed in Chapter 6, random errors in measurement cannot be removed by
calibration, and it is not uncommon to see 2% factory uncertainty [80] on measurement
equipment after calibration process. Assuming all measurements (calibration and verification)
are made with 1000 averages, Figure C-7 shows the distributions of magnitude of G12 at 5GHz
(a), 10GHz (b) and 20GHz(c) for separation distance of 220μm. Within three standard deviations
(į) of the mean (μ), it shows 2.79%, 2.81% and 2.75% variations at 5GHz, 10GHz and 20GHz,
respectively.
135
250
-4
P = 1.468x10
-6
V= 1.364x10
Number of samples
200
150
100
50
0
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.5
1.51
G12(mag) (: -1)
1.52
x 10
-4
(a)
300
-4
P = 2.08x10
250
Number of samples
V= 1.945x10
-6
200
150
100
50
0
2.02
2.04
2.06
2.08
2.1
2.12
2.14
G12(mag) (: -1)
2.16
x 10
-4
(b)
300
-4
P = 3.627x10
250
Number of samples
V= 3.322x10
-6
200
150
100
50
0
3.5
3.55
3.6
3.65
G12(mag) (: -1)
3.7
3.75
3.8
x 10
-4
(c)
Figure C-7. |G12| distributions at different frequencies (separation distance = 220μm)
136
250
-5
P = 8.647x10
-7
V= 7.858x10
Number of samples
200
150
100
50
0
8.4
8.5
8.6
8.7
8.8
8.9
9
G12(mag) (: -1)
x 10
-5
(a)
250
-4
P = 1.229x10
-6
V= 1.086x10
Number of samples
200
150
100
50
0
1.19
1.2
1.21
1.22
1.23
1.24
1.25
1.26
1.27
G12(mag) (: -1)
1.28
x 10
-4
(b)
300
-5
P = 2.136x10
250
-6
Number of samples
V= 1.997x10
200
150
100
50
0
2.06
2.08
2.1
2.12
2.14
2.16
G12(mag) (: -1)
2.18
2.2
2.22
2.24
x 10
-4
(c)
Figure C-8. |G12| distributions at different frequencies (separation distance = 1200μm)
137
Table C-3. |G12| variations under different frequencies (separation distance = 220μm)
Frequency (GHz)
Mean (ȍ--1)
Standard deviation (ȍ--1)
Variation (%)
5
1.47 x10-4
1.36 x10-6
2.79
10
2.08 x10-4
1.95 x10-6
2.81
20
3.63 x10-4
3.32 x10-6
2.75
Table C-4. |G12| variations under different frequencies (separation distance = 1200μm)
Frequency (GHz)
Mean (ȍ--1)
Standard deviation (ȍ--1)
Variation (%)
5
8.65 x10-5
7.86 x10-7
2.73
10
1.23 x10-4
1.15 x10-6
2.80
20
2.14 x10-4
2.00 x10-6
2.81
The distributions of magnitude of G12 at 5GHz (a), 10GHz (b) and 20GHz(c) for separation
distance of 1200μm are shown Figure C-8. The variations are 2.73% at 5GHz, 2.80% at 10GHz
and 2.81% at 20GHz. The variations of |G12| under different frequencies for different separation
distances are summarized in Table C-3 and C-4.
138
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145
BIOGRAPHICAL SKETCH
Ming He was born in Guangzhou, China in 1977. He received his B.S. degree in Electrical
Engineering from South China University of Technology, Guangzhou, China in 2000 and his
M.S. degree in electrical engineering from the University of Florida, Gainesville, in 2002. In the
fall of 2002, he worked as an intern in the National Semiconductor, in Santa Clara, CA. He is
currently working toward the Ph.D. degree in electrical engineering.
His research interests are in the areas of analog/mixed-signal/RF IC design and embedded
IC design-for-test.
146
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