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Microwave characterization and design of aluminum gallium arsenide/gallium arsenide heterojunction bipolar transistors

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M icrow ave characterization and design o f A lG a A s/G a A s
heterojunction bipolar transistors
Wu, Der-Woei, Ph.D.
The Pennsylvania State University, 1993
UMI
300 N. Zeeb Rd.
Ann Arbor, MI 48106
The Pennsylvania State University
The Graduate School
MICROWAVE CHARACTERIZATION AND DESIGN OF AlGaAs/GaAs
HETEROJUNCTION BIPOLAR TRANSISTORS
A Thesis in
Electrical Engineering
by
Der-Woei Wu
Copyright 1993 Der-Woei Wu
Submitted in Partial Fulfillment
of the Requirements
for the Degree of
Doctor of Philosophy
December 1993
We approve the thesis of Der-Woei Wu
,
O'
Date of Signature
David L. Miller
Professor of Electrical Engineering
Thesis Advisor
Co-Chair of Committee
Lynn A. Carpenter
Associate Professor of Electrical Engineering
Co-Chair of Committee
Mukunda B. Das
Professor of Electrical Engineering
Thomas N. Jackson
Professor of Electrical and Computer Engineering
Joseph P. Dougherty
Senior Research Associate and
Associate Professor of Materials
r l i l i s
Larry C. Burton'
Professor of Electrical and Computer Engineering
Head of the Department of Electrical Engineering
Ab st r a c t
In recent years, heterojunction bipolar transistors (HBTs) have gained wide
acceptance for their excellent capabilities in high-speed digital IC and analog
microwave and millimeter-wave applications. Further improvement in highfrequency performance will require great attention in the optimization of the
epitaxial structure, fabrication process and device physical layout. In this thesis, a
new method of small-signal modeling and microwave characterization for
AlGaAs/GaAs HBTs is presented. The implication of the model parameters on
device design is discussed, and the modeling procedure is tested on the fabricated
devices.
The effects of device structure and layout parameters on the high-frequency
performance of HBTs have been analyzed. Several critical parameters were
formulated to maximize two figures of merit characterizing transistor highfrequency response, namely, the cutoff frequency, / p and the maximum oscillation
frequency,/^.
To examine the microwave performance of AlGaAs/GaAs HBTs, a self­
aligned HBT process was designed and realized. Without using sophisticated
fabrication techniques and novel structures, this device has demonstrated
performance suitable for microwave and millimeter wave applications.
A new parameter extraction technique for HBTs is proposed and
demonstrated in this work. This technique, directly determining the small-signal
model parameters, advances current equivalent circuit modeling capability of HBTs
by minimizing the interactive computer optimization/simulation process and
removing the need of special test structures. The accurate and reliable
determination of the model parameters will provide essential information on device
design, structure optimization and process monitor.
T a b le o f C ontents
L ist of Figures........................
viii
L ist of T ables ............................................................................................................xii
Acknowledgements................................................................................................xiii
1
Introduction .........................................................................................................1
1.1
Overview........................................................................................... 1
1.2
Research Objectives and Summary of Results.................................. 3
1.3
Thesis Outline................................................................................... 5
2
P rinciples of O peration .................................................................................... 7
2.1
Transistor Gain Mechanism.............................................................. 7
2.2
Base Current Components...............................................................12
2.2.1 Recombination in Space-Charge Region (SCR)............... 12
2.2.2 Surface Recombination Current in the Exposed
Extrinsic Base Region.........................................................14
2.2.3 Base Contact Recombination Current...............................16
2.2.4 Bulk Recombination in the Base Region...........................17
2.2.5 Hole Back-Injection Current............................................. 21
2.3
Small-Signal Analysis......................................................................21
2.3.1 Small-Signal Parameters Based on the Charge-Control
Model................................................................................. 23
2.3.2 High-Frequency Common-Emitter Forward Transfer
Admittance Representation................................................28
2.3.3 Parasitic Resistances and Capacitances............................ 29
2.3.4 Minority-Carrier Diffusion Coefficient and Electron
Saturation Velocity............................................................ 32
vi
3 D evice D esign Consideration ......................................................................... 34
3.1
High-Frequency Performance Figures of M erit............................... 34
3.1.1 Derivation o f /r..................................................................... 34
3.1.2 Derivation o f / ^ .................................................................. 37
3.2
Layout Design..................................................................................... 42
3.2.1 Emitter Width SE.................................................................. 42
3.2.2 Emitter Length LE.................................................................46
3.2.3 Base Contact Width SB........................................................ 48
3.3
Epitaxial Structure Design................................................................. 49
3.3.1 Abrupt versus Graded Emitter-Base Junction.................... 49
3.3.2 Base Design..........................................................................53
3.3.3 Collector Design................................................................... 57
3.4
Material Aspect................................................................................... 60
4 D evice Fabrication and E xperimental Results ........................................ 63
4.1
Device Fabrication..............................................................................63
4.1.1 Epitaxial Structure................................................................ 63
4.1.2 Self-Alignment Technique...................................................65
4.1.3 Processing Steps................................................................... 67
4.2
Experimental Results.......................................................................... 75
4.2.1 Network Representation with S-parameters...................... 75
4.2.2 DC Characteristics................................................................ 78
4.2.3 Microwave Results............................................................... 86
5 Unique D etermination of HBT s Equivalent Circuit Parameters ....... 92
5.1
Overview............................................................................................. 92
5.2
Technical Approach........................................................................... 94
5.2.1 Model Determination............................................................94
5.2.2 Extraction Algorithm............................................................95
5.2.2.1 Extraction of the Resistive Parasitic
Components..........................................................101
5.2.2.2 Extraction of the Intrinsic Elements................... 107
5.2.2.3 Determination of the Overall Equivalent
Circuit Parameters................................................109
5.3
Measurement and Results.................................................................113
5.4
Verification of the Extracted Parameters........................................117
5.4.1 Calculated Small-Signal Parameters................................ 117
5.4.2 Scaling of the Model Parameters....................................... 124
5.4.2.1 Scaling of the Parasitic Resistances................... 124
vii
5.5
6
5.4.2.2 Scaling of the Parasitic Capacitances................. 126
5.4.2.3 Scaling of the Intrinsic Elements....................... 132
Summary........................................................................................137
Conclusions ...................................................................................................... 139
6.1
Research Summary.........................................................................139
6.2
Future W ork.................................................................................. 141
References ...............................................................................................................144
L is t o f F ig u r e s
Figure 2.1.1
(a) Schematic diagram of a HBT illustrating various current
components, (b) The band diagram for a HBT with a graded
emitter-base junction operated in the active mode. (Adapted
from reference [2-3])........................................................................ 8
Figure 2.2.1
Identification of various base current components......................... 13
Figure 2.2.2
The conduction band edge at and near the surface of an HBT
with a graded heterojunction under forward bias. (After
reference [2-10]).............................................................................15
Figure 2.2.3
Recombination processes: (a) radiative recombination, (b)
Auger recombination, (c) single-level SRH recombination.............18
Figure 2.2.4
The DC current gain versus the base width at different doping
concentration, assuming unity emitter injection efficiency............. 22
Figure 2.3.1
High-frequency common-emitter hybrid-rc equivalent circuit
model.............................................................................................. 24
Figure 2.3.2
Correspondence of equivalent circuit elements and device
physical structure............................................................................ 25
Figure 3.2.1
The device structure used in the discussion................................... 43
Figure 3.2.2
Experimental data of
as a function of emitter stripe width
with Le ~ 10 |xm and Jc ~ 1.5X104 A/cm2....................................... 44
Figure 3.2.3 Calculated emitter utilization factor as a function of the emitter
stripe width with/T= 40 GHz, Poff = 70 and base sheet
resistance of 400 QJsq.................................................................... 47
Figure 3.3.1 Comparison of energy band diagrams of abrupt and graded
hetero-junctions.............................................................................. 51
Figure 3.4.1 Band lineups between AljGa7As/GaAs and GaJyIn49P/GaAs
material systems.............................................................................. 61
Figure 4.1.1 Schematic diagram for the self-aligned technique........................... 66
Figure 4.1.2 SEM photography of the self-aligned structure with a 0.25-pm
spacing between emitter mesa wall and base metal........................ 68
Figure 4.1.3 (a), (b) Schematic representation of the HBT fabrication
process used in this work................................................................70
Figure 4.1.3 (c), (d) Schematic representation of the HBT fabrication
process used in this work................................................................71
Figure 4.1.4 SEM photograph of a fabricated HBT. This device has one
emitter stripe and two base stripes with AE= 8 pmxl 3 pm........... 74
Figure 4.2.1 Schematic of a two-port network showing the definition of the
S-parameters................................................................................... 77
Figure 4.2.2 Common-emitter output characteristics of an HBT with AE= 18
x33 pm2. The base current starts at 100 pA with 100 pA steps.... 79
Figure 4.2.3 The Gummel plot of an HBT with AE = 18x33 pm2 at VCE= 3
V..................................................................................................... 80
Figure 4.2.4 DC current gain (3vs Ic of an HBT with AE = 18x33 pm2 at VCE
= 3 V............................................................................................... 81
Figure 4.2.5 The determination of (a) collector-base junction breakdown
voltage, BVcbo, and (b) collector-emitter junction breakdown
voltage, BVceo................................................................................. 83
X
Figure 4.2.6
Maximum available gain/maximum stable gain {MAG/MSG) and
current gain (H2I) for the HBT with AE = 8x13 |xm2 at VCE= 3
V and Ic = 20 mA........................................................................... 87
Figure 4.2.7
The collector current dependence off Ta n d f o r the HBT
with A e = 8 |xmxl3 |xm at VCE= 3 V.............................................. 88
Figure 4.2.8
The collector-emitter voltage dependence off Tand
for the
HBT with Ae = 8 |xmxl3 |xm at Ic = 3 mA.....................................89
Figure 4.2.9
MAG/MSG as a function of frequency for two different size
devices.............................................................................................91
Figure 5.2.1
Overall lumped-element small-signal equivalent circuit model......96
Figure 5.2.2
Low-frequency hybrid-7t equivalent circuit model for HBTs........ 97
Figure 5.2.3
The extraction procedure for obtaining the intrinsic Yparameters of the low-frequency hybrid-7t equivalent circuit
model...............................................................................................99
Figure 5.2.4
The corresponding admittance blocks of the intrinsic hybrid-7t
equivalent circuit model................................................................ 100
Figure 5.2.5
Modified low-frequency equivalent circuit model by absorbing
the effect of Ree..............................................................................103
Figure 5.2.6
The extraction of the emitter series resistance, Ree...................... 105
Figure 5.2.7
The extraction of the base series resistance,
Figure 5.2.8
The extraction of the collector series resistance, Ree................... 108
Figure 5.2.9
The extraction of rKas a function of frequency........................... 110
Figure 5.2.10 The extraction of CKand
.......................... 106
as a function of frequency.............. I l l
Figure 5.2.11 The extraction of g ^ as a function of frequency......................... 112
Figure 5.2.12 The flow diagram of the algorithm used to determine the
equivalent circuit parameters for HBTs........................................ 114
Figure 5.3.1
Extraction of CKand as a function of frequency up to 10
GHz...............................................................................................115
Figure 5.3.2
Comparison between the measured and model-generated Sparameters..................................................................................... 118
Figure 5.3.3
Comparison between the measured and modeled (a) current
gain \H21) and (b) maximum stable/maximum available gains
(MSG/MAG)..................................................................................119
Figure 5.4.1
The device layout used in the model parameter calculation.........121
Figure 5.4.2
Comparison of the measured, calculated and modeled maximum
stable/maximum available gains (MSG/MAG)...............................125
Figure 5.4.3
The fit of the extracted emitter series resistance to emitter
length Le........................................................................................ 127
Figure 5.4.4
The fit of the extracted base series resistance to emitter length
Le...................................................................................................128
Figure 5.4.5
The fit of the extracted collector series resistance to emitter
length Le........................................................................................ 129
Figure 5.4.6
The fit of the intrinsic base-collector capacitance to base length
Lb...................................................................................................130
Figure 5.4.7
The fit of the extrinsic base-collector capacitance to base length
Lb...................................................................................................131
Figure 5.4.8
The fitting of the intrinsic transconductance g ^ .......................... 133
Figure 5.4.9
The fitting of the small-signal input resistance
.........................134
Figure 5.4.10 The fitting of the small-signal input capacitance CK.....................136
L is t o f T a b l e s
Table 4.1.1
MBE Wafer Epitaxial Structure.......................................................64
Table 5.3.1
Equivalent Circuit Parameters, Quad-8 x 13 |im2-emitter HBT
at VCE= 3V.................................................................................... 116
Table 5.4.1
MBE Wafer Epitaxial Structure Used in Model Calculation.........120
Table 5.4.2
The Corresponding Layout Dimensions Used in Model
Calculation.................................................................................... 121
Table 5.4.3
The Extracted and Calculated Small-Signal Parameters
122
Acknow ledgem ents
This dissertation would not have been possible without the assistance of a
large number of people. I would like to thank my co-advisors, Drs. David L. Miller
and Lynn A. Carpenter, for giving me the wonderful opportunity to work on this
topic and providing me a great learning experience. I would also like to thank Dr.
Mukunda B. Das for many inspiring discussions and comments on the equivalent
circuit modeling. Special thanks are due to Dr. Thomas N. Jackson for stimulating
discussions on various aspects of the thesis. Thanks are also due to Dr. Joseph P.
Dougherty for gladly accepting to serve on my committee and representing the
faculty for related areas.
Additionally, I would like to express my appreciation and gratitude to all the
personnel of the processing and testing in Lowell Semiconductor Operation, M/ACOM, Inc., MA, for the HBT process development and device characterization
work. I am especially grateful to Mike Fukuda and Chris Mclean of Corporate
R&D, M/A-COM, Inc., for the device development and fabrication. I am also
extremely grateful and indebted to Dr. Yong-Hoon Yun of M/A-COM under
whose leadership and guidance the device fabrication and modeling work were
carried out. The encouragement and support provided by Gerry DiPiazza and Dr.
Peter Staecker (both of M/A-COM) is gratefully acknowledged.
Finally, I thank my parents for their indispensable love and support, which
have been a large part of my education, and my wife, Yun-yun, who has shown me
tremendous indulgence and support in numerous ways over the years.
Support during the course of this work was partially funded by U. S. Army
Research Office. The device development and characterization portions of this
work were sponsored by Corporate R&D, M/A-COM, Inc., MA.
Chapter 1
I n t r o d u c t io n
1.1
O v e r v ie w
The quest for faster, more densely packed, and lower power-consumption
devices has long been the impetus for growth in the electronics industry. With the
maturity of the epitaxial growth technologies, such as molecular beam epitaxy
(MBE) [1-1] and metal-organic chemical vapor deposition (MOCVD) [1-2], device
designers now have greater freedom to select the material systems with superior
carrier transport properties and to tailor the device structures for optimum
performance. Accordingly, semiconductor devices with unprecedented high-speed
performance have been demonstrated in recent years.
Among these devices, the heterojunction bipolar transistor (HBT), the
subject of this thesis, is emerging as a very promising high-speed device for a wide
variety of applications [1-3, 1-4]. The HBT, originally proposed by Shockley in
1948 [1-5], and later analyzed by Kroemer in 1957 [1-6], is a bipolar transistor in
which one or both junctions are formed between dissimilar semiconductor
materials. By using a wide-bandgap emitter material (or narrow-bandgap base) to
Chapter 1 Introduction
2
provide nearly unity carrier injection efficiency, the base can be doped much more
heavily than the emitter, allowing low emitter-base capacitance and greatly reduced
base series resistance. In addition, electron transport in compound semiconductors
is also very rapid compared to that in silicon. Together with the availability of semiinsulating substrates, III-V HBTs have offered high-speed operation advantages
over Si bipolar transistors.
In comparison with GaAs MESFETs (metal-semiconductor field effect
transistors), the superior properties of HBTs include high current handling
capability because the entire emitter area conducts current,
and high
transconductance due to the exponential dependence of the output current on the
input voltage [1-7]. HBTs have also demonstrated greater speeds with relaxed
lithographic dimensions. The high current driving capability and easily tailored
breakdown voltage via epitaxial layer design have led to higher power handling
capability per effective transistor area [1-8]. This makes HBTs more suitable for
high power generation at microwave/millimeter-wave frequencies than both Si
bipolar transistors and GaAs MESFETs. In addition to high power density, HBTs
also feature low phase noise, due to reduced trapping effects, and high linearity,
due to high base doping, which are critical advantages for designing oscillators and
linear amplifiers, respectively [1-9]. Kim et al. [1-10] have reviewed GaAs HBT
device and IC technology in detail. Asbeck et al. [1-11] have also provided
information about the applications and issues pertaining to the future development
of HBTs.
Chapter 1 Introduction
1.2
R e s e a r c h O b je c t iv e s
3
and
Sum m ary
of
R e su l t s
From the device design viewpoint, a simple three-step iterative approach,
namely, design, fabrication and characterization, is often used to improve the device
performance. It is the goal of this work to provide an efficient and reliable approach
to ameliorate this costly and time-consuming design-to-fabrication process. This is
achieved by introducing a novel parameter extraction technique to improve current
HBT equivalent circuit modeling capability and by investigating the important
issues related to the design and fabrication of HBTs. In the course of this study, a
complete HBT design-to-fabrication process is developed with emphasis on
equivalent circuit modeling of the device.
As the heterojunction bipolar transistor technology matures, accurate and
efficient device modeling becomes increasingly important in determining the factors
that limit the device performance. The conventional approach to HBT equivalent
circuit modeling has involved numerically fitting a relatively large number of
equivalent circuit parameters to match measured data, despite the uncertainty and
non-uniqueness in determining the element values. Many laboratories have
proposed parameter extraction techniques for HBTs. However, even the best of
those approaches requires some separate measurement of test structures to
characterize parasitics.
One of the most significant results obtained in this thesis is the development
of a new parameter extraction technique for HBTs. Utilizing a low frequency
extraction algorithm, the intrinsic elements and the resistive parasitics are obtained.
The overall small-signal equivalent circuit of HBTs is then determined based on
Chapter 1 Introduction
4
those extracted element values. The advantage of using this low frequency
algorithm to extract intrinsic parameters is two-fold. Firstly, it effectively removes
the effects of the pad and interconnect parasitics. Special test structures to deembed the parasitics are therefore unnecessary. Secondly, it greatly simplifies the
analysis of the equivalent circuit. That is, with the simplified equivalent circuit, each
element can be analytically represented. The successful development of the
technique has important contributions to the science of HBT devices. Not only does
it reduce the time required to model the device behavior over the frequency of
interest due to the minimized computer optimization process, but, most
importantly, it also provides a unique and reliable approach to the determination of
each element value, which can be related to the physical structures and operations
of the device. Therefore, it offers essential information on device design, structure
optimization and circuit design.
The role of epitaxial layer design and device layout design on the highfrequency performance of HBTs is also examined in this thesis. For example, the
influence of the emitter width, emitter length, base contact width and the doping
and thickness of the base and collector epitaxial layers on device performance are
presented. The first-order design criteria for several critical parameters are
analyzed. In addition to high-frequency parameters, the physical mechanisms
affecting the DC performance of HBTs are also discussed.
A self-aligned AlGaAs/GaAs HBT fabrication process was developed in this
work. With emitter area of 8x13 pm2, base doping of 2x1 O'9 cm J and base
thickness of 1500 A, the device has demonstrated DC current gain of 50, f T and
of 30 and 25 GHz, respectively. These are excellent results considering that a
Chapter 1 Introduction
5
relaxed geometry and simple fabrication process was employed. Using the
equivalent circuit modeling technique developed in this work, it is predicted that
greatly improved high-frequency response is realizable.
1.3
T h e s is O u tl in e
This dissertation is divided into six chapters. Chapter 2 discusses the basic
operating mechanisms of HBTs and differentiates those from homojunction bipolar
transistors. Various base current components, which limit the DC performance of
the transistors, are identified and their physical origins are described. Small-signal
analysis of the HBTs is provided in this chapter, by which the equivalent circuit
model used in this thesis work is constructed. This chapter also lays the foundation
for interpreting the measured DC and high-frequency results obtained in chapter 4
and is used to validate the extracted small-signal parameters in chapter 5.
Chapter 3 explains the critical parameters of the device design. Two widely
used high-frequency figures of merit are derived as a starting point. The design
criteria, trade-offs and limitations of important design variables are presented.
Combined with the technique developed in chapter 5, optimum design for a given
electronic function can be achieved. This chapter ends with a discussion of
GalnP/GaAs HBTs, which is intended to provide the insight to different material
aspects and their influence on the device performance.
Chapter 4 delineates the self-alignment process and the fabrication
procedures for the AlGaAs/GaAs HBTs. Utilizing a simple fabrication process,
devices suitable for microwave/millimeter wave applications are obtained. In
Chapter 1 Introduction
6
addition, this chapter introduces the 5-parameters, which are important quantities
for characterizing the microwave performance. This chapter ends by demonstrating
the DC and high-frequency characteristics of the fabricated devices.
Chapter 5 presents the technique developed for determining the small-signal
equivalent circuit parameters of HBTs. It begins with the model determination, then
describes the technical approach used. The detailed procedures which lead to the
simplification and determination of the overall high frequency equivalent circuit
model are given. This algorithm is verified, first, by comparing the modeled and
measured frequency response and 5-parameters. To further ensure the validity of
this method, the extracted parameters are very carefully compared with the
calculated small-signal model parameters using the analysis outlined in chapter 2.
The extracted parasitics and intrinsic parameters are also scaled versus device
geometrical parameters to serve as the third check of the algorithm. The scalability
of this model also demonstrates the most important application of this technique,
that is, it eliminates the need for a cumbersome and limited standard device library.
Chapter 6 summarizes the contributions of this thesis work and proposes
suggestions for future work on HBTs.
Chapter 2
P r in c ip l e s o f O p e r a t io n
2.1
T ransistor G ain M echanism
The three terminals of the HBTs, and their simplified physical layout, are
illustrated in figure 2.1.1 (a), for an N-p-n transistor (where N denotes widebandgap material or AlGaAs in this case). Figure 2.1.1 (b) shows the energy band
diagram of an HBT with a linearly graded heterojunction (the design aspect of
heterojunction grading is discussed in section 3.3.1) and biased into the active
mode, i.e., forward-biased emitter-base and reverse-biased base-collector junctions.
In this diagram, the currents created by electron-hole pair generation in the
collector depletion layer or the collector body have been neglected.
The basic transistor action can be explained as follows. The application of
forward bias reduces the conduction-band potential barrier for electron flow from
emitter to base. Most of the electrons that surmount this barrier diffuse or drift (if
there is a quasi-electric-field present) across the base without recombining with
holes, since the base is made narrow as compared to the electron diffusion length.
Upon reaching the reverse-biased base-collector junction,
electrons
are
Chapter 2 Principles of Operation
8
p - CaAa
/irv /to fC o n
rn
,
*
.
I
i
I '
* l
...................... 1 ...
I
m/furUm
|
| C o B o t Mo a
Ft
ii
rST!
i
.....
V
(a)
Emittor
T
Emffler current l| - In ♦ I
Collector current lc - In • l|
(b)
Figure 2.1.1 (a) Schematic diagram of a HBT illustrating various current
components, (b) The band diagram for a HBT with a graded emitter-base junction
operated in the active mode. (Adapted from reference [2-3])
9
Chapter 2 Principles of Operation
swept into the collector by the large electric field within the junction. Since most of
the injected electrons can reach the collector without recombining with holes in the
base region, the collector current will be very close to the emitter electron current.
Therefore, carriers injected from a nearby emitter junction can result in a large
current flow in a reverse-biased collector junction.
Now, if the transistor is biased into the active mode and the base-collector
reverse saturation leakage current is neglected, various current components across
the base-emitter junction can be simplified to the following equations (VBE> 3kT/q)
P (^ > •
C2.1.1)
,
(2. 1.2)
p ( |^ f - ) ,
(2.1.3)
and
where /„ is the electron current injected from the emitter into the base, Ip is the hole
currentinjected fromthe base intothe emitter; Is is therecombination
within theemitter-base spacecharge
currents Ino, Ipo, and Iso are given by
current
region (SCR) [2-1]. The reversesaturation
Chapter 2 Principles of Operation
10
where AE is the emitter area, q is the electron charge, DnB and DpE are the diffusion
constants for the base and emitter regions, respectively; WB is the base width, LpE is
the hole diffusion length in the emitter; NAB and NDE are the doping concentrations
in base and emitter regions, respectively; xo is the excess carrier lifetime in the
depletion region, and W'g is the distance within the depletion region where
appreciable recombination takes place [2-2]. niB and niE are the intrinsic carrier
concentrations in base and emitter regions, respectively, and are expressed as
niE=(NCENVE)*Gxp(-E gE/2kT ) ,
(2.1.7)
% =(W ct Wra)* e x p (-£ „ /2 « -) ,
(2.1.8)
and
where Nc and Nv are the effective density of states in the conduction and valence
bands; Eg is the bandgap and the subscripts E and B represent the corresponding
emitter and base regions.
Following Kroemer's analysis [2-3], we have
p = ^ - = In ~ Ir < — = Pnux ,
I B I p + Ir + Is I p
(2.1.9)
where p is the DC current gain and is the most important figure of merit
characterizing the DC performance of the transistor; Ir is the bulk recombination
current. P ^ is the maximum value given by the ratio of the injected electron and
hole currents and is achievable when the recombination currents are negligible
compared to the injection currents. Substituting for /„ and Ip in (2.1.9) from (2.1.1),
(2.1.2), (2.1.4), (2.1.5), (2.1.7), and (2.1.8), one obtains
Chapter 2 Principles of Operation
11
P - = ^ f ! ! P£(T rST ^ ) exP(AEg/ ^ )
“
D fiW 'N v 'N a 'N y '
.
(2.1. 10)
where A Eg= EgE - EgB is the difference between the energy bandgap of the emitter
and base materials.
For a homojunction bipolar transistor, equation (2.1.10) simplifies to
p
DjM
e
DpBWsN „
,
(2.1.11)
because the emitter and base regions are composed of the same energy bandgap
material. From equation (2.1.11), it is clearly seen that in order to have appreciable
current gain, the emitter must be more heavily doped than the base in a
homojunction bipolar transistor. Unfortunately, decreasing NAB results in an
increase in the base series resistance and increasing NDE results in an increase in the
emitter-base junction capacitance. Both of these effects severely limit the high
frequency performance of the transistor.
This dilemma is overcome in the HBT by the use of a wider bandgap
material for the emitter than for the base. Re-examining equation (2.1.10), for
AljGa7As/GaAs HBTs, AEg~ 14.5kT and exp(A£s/ k T ) = 2• 106. The difference
in bandgap between the emitter and base creates an additional barrier to unwanted
hole injection from base to emitter and provides a factor of over 10* improvement
in
over the homojunction case. This high P ^ frees the device designer from
the constraint of doping the emitter more heavily than the base. Therefore, base
resistance can be lowered by doping the base very heavily (1019 - 1020 cm3). This
allows a very thin base, on the order of 1000 A or less, to achieve a low base transit
time without increasing the base layer sheet resistance. The emitter doping
Chapter 2 Principles of Operation
12
concentration can be much lower than that of the base, resulting in a much lower
junction capacitance due to depletion region extending into the lightly doped
emitter body. The decrease in base resistance, transit time and junction capacitance
result in a device with exceptional performance. To date, N-p-n microwave
transistors with maximum oscillation frequency,
up to 350 GHz [2-4] and
cutoff frequency, f T, exceeding 100 GHz [2-5] have been reported.
2.2
BASE CURRENT COMPONENTS
To better understand the DC behavior of HBTs, various base current
components which dictate the current gain of the device will be discussed in this
section. As schematically shown in figure 2.2.1, there are six base current
components for an emitter-up HBT under normal operating conditions. These are:
(1) recombination at the surface of the emitter-base space-charge region (SCR), (2)
recombination in the bulk of the emitter-base SCR, (3) surface recombination
current in the exposed base region, (4) interface recombination at the base contact,
(5) bulk recombination in the base, and (6) hole back-injection current. Again, the
base-collector reverse bias current due to diffusion and generation is neglected.
2.2.1
Recombination in Space-Charge Region (SCR)
Recombination in the SCR, which occurs both at the surface (1) and in the
bulk (2), contributes a 2kT dependence of the base current on the emitter-base
voltage (i.e., IB varying as exp(qVBE/2kT)). This has been found to be very
important in HBTs due to high recombination in these regions [2-6 ~ 2-8], In the
Chapter 2 Principles of Operation
13
forward biased emitter-base junction, high concentration of electrons and holes
diffuse from the neutral emitter and base regions into the space-charge region due
to the lowered electrostatic potential barrier. The electron and hole concentration
can become nearly equal only in the emitter-base SCR. This equality maximizes
Shockley-Read-Hall (SRH) recombination so that substantial recombination can
occur in this region.
Electron Flow
Hole Flow
Emitter (N)
(6) (5)
Emitter-Base
SCR
{hk-
(2) ( 1)
i-U -
Exposed Base Region
^ 1
(3)
_____________
(4)
Base (p+)
Collector (n)
Figure 2.2.1 Identification of various base current components.
To illustrate the significance of this effect to the current gain of HBTs, a
simple analysis is performed below, where the base current is assumed to be
dominated by the recombinations in the SCR. Under this assumption, the base
cunrent is given by
14
Chapter 2 Principles of Operation
/fl =
6XP(^ ^ ) + ^
( f °L*)n,fl CXp(^
' ) ’
(2,2,1)
where PE, 5,,, and L, are the emitter periphery, surface recombination velocity, and
surface diffusion length, respectively. The first term in equation (2.2.1) represents
the bulk SCR recombination (see equation (2.1.3)) and the second term describes
the surface recombination current [2-9]. Based on equation (2.1.9) and (2.2.1), we
now have
(fi;fl Q^be)
2 kT
(2 .2 .2)
Equation (2.2.2) suggests that when recombination in the SCR dominates the base
current, the advantage of using the heterojunction to enhance P through the
exponential factor of Eg in equation (2.1.10) is lost. Under this condition, current
gain is enhanced through the qVBE term in equation (2.2.2), which predicts a highly
non-linear device with the highest gain obtained when driven hard. It is clear that
the full value of the HBT is clearly only obtained when the SCR recombination
current is minimized.
2.2.2 Surface Recombination Current in the Exposed Extrinsic Base Region
A free GaAs surface is characterized by a high surface recombination
velocity because of Fermi-level pinning in connection with a high surface-state
density. Figure 2.2.2 illustrates the conduction band edge at and near the surface of
an HBT with a graded heterojunction under forward bias [2-10], The band-bending
occurs at the surface due to the Fermi-level pinning. As a result, the electrons
injected from the emitter into the base diffuse laterally and experience an electric
field created by the band-bending, which accelerates these electrons toward the
Chapter 2 Principles of Operation
15
Potential energy
(eV)
Base
Emitter
-Extrinsfe
base \
Figure 2.2.2 The conduction band edge at and near the surface of an HBT with a
graded heterojunction under forward bias. (After reference [2-10])
Chapter 2 Principles of Operation
16
surface, where they recombine with the majority carrier holes. This extrinsic base
surface recombination current can be a major component to the overall base
current, especially for small-geometry devices where the device area-to-perimeter
ratio is small [2-11]. Since reducing the device dimensions is crucial to minimize the
parasitic effects and allow higher frequency operation, this current gain degradation
associated with the increased contribution of surface recombination current, which
is also known as the emitter-size effect [2-12], greatly limits the device scale
reduction required for high-speed applications.
Thin layers of depleted AlGaAs, fabricated by etching the extrinsic AlGaAs
emitter layer down to 50 ~ 100
A,
have been successfully used to suppress the
electron concentration at the surface of the extrinsic base. This leads to a lower
surface recombination current and maintains the current gain such that it is virtually
independent of the area-to-perimeter ratio [2-13 ~ 2-15]. In addition, the use of a
graded-base structure to introduce a vertical quasi-electric field in the base, thus
preventing injected electrons from reaching the surface region, has been proposed
to suppress this surface recombination effects [2-16, 2-17]. Surface chemical
treatment to saturate the dangling bonds on the GaAs surface, thereby reducing the
surface-state concentration, is also utilized to reduce surface recombination [2-18].
2.2.3 Base Contact Recombination Current
To reduce the extrinsic base resistance and base-collector capacitance for
better high-frequency performance, it is essential to utilize a self-aligned emitter
technique to reduce the distance between the emitter mesa and the base contact
metal [2-19]. Since the ohmic contact is also characterized with a high
Chapter 2 Principles of Operation
17
recombination velocity, an effect similar to extrinsic base surface recombination can
occur. This effect has been demonstrated experimentally by Lee et al. [2-20]. For
the device with spacing between the emitter mesa and the base contact metal much
larger than the lateral diffusion length of electrons, most of the electrons injected
into the base will not reach the base contact, but they will either diffuse across the
base to the collector, recombine in the bulk of the base layer or recombine at the
extrinsic base surface, as we have previously described. However, if the emitter
mesa to the base contact separation is comparable to the lateral diffusion length of
electrons, then recombination at the base contact can be large.
2.2.4 Bulk Recombination in the Base Region
Recombination of electrons in the p* bulk base region is governed by three
basic mechanisms, namely, radiative, Auger and Shockley-Read-Hall (SRH) [2-1]
recombinations. Figure 2.2.3 shows these three processes. The radiative
recombination is a direct band-to-band transition which involves the annihilation of
a conduction band electron and a valence band hole, as pictured in figure 2.2.3 (a).
This process, which is important for most III-V compounds with direct energy
gaps, is typically radiative, with the excess energy released by emission of a photon
(light). A second very important effect which occurs at high doping level is due to
non-radiative Auger recombination. This is due to the direct band-to-band
recombination between an electron and a hole across the bandgap, accompanied by
the transfer of energy to another free electron or hole, as shown in figure 2.2.3 (b).
The final process to be considered (see figure 2.2.3 (c)) is the Shockley-Read-Hall
recombination, sometimes referred to as the R-G (recombination-generation) center
Chapter 2 Principles of Operation
18
Electron
------------------
Ec
Emission of Photon
- 6 ---------------------
Ev
(Radiative)
Hole
(a)
Electron
Ec
Energy Transferred to Free Electron or Hole
(Auger)
“ D—
Ev
Hole
(b)
Electron
Ec
Capture
Emission
I
or
Emissic
„
- X - X ---------- X - X ----------- Ej
Heat or Phonons Produced
(single-level SRH)
O---------------- o -
Ev
Hole
(c)
Figure 2.2.3 Recombination processes: (a) radiative recombination, (b) Auger
recombination, (c) single-level SRH recombination.
19
Chapter 2 Principles of Operation
recombination. This type of recombination generally occurs via deep levels located
close to the center of the bandgap. These deep levels or recombination centers arise
from crystal defects, and impurities, and have the effect of disrupting the perfect
periodicity of the semiconductor lattice. They thereby give rise to discrete energy
levels in the bandgap in a similar way to donor and acceptor levels. This type of
recombination is very efficient, because the deep levels act as 'stepping stones',
aiding the transition of electrons and holes between the conduction and valence
bands. Thermal energy (heat) is released during the process, or equivalently, lattice
vibrations (phonons) are produced.
For radiative recombination, the lifetime is inversely proportional to the
doping concentration, i.e.,
—
R Nv a b
£y
,
(2.2.3)
where Bp is the radiative constant, and NAB is the base doping concentration. The
experimental data for Bp is available in reference [2-21]. For Auger recombination,
the minority-carrier lifetimes in low-level injection are given by
x-
p
AB
•
( 2 -2 -4 )
where Cp is the Auger recombination coefficient In p +-GaAs the value of xAug can
be less than nanoseconds for base doping greater than lxlO19 cm3. The effective
value of xSRH in GaAs depends on material growth techniques, although it varies
little with doping density for doping densities greater than 1014cm 3.
The effective bulk recombination time, x^, can be expressed as
Chapter 2 Principles of Operation
20
—
^no
.
^SR H
^A ug
(2.2.5)
^ra d
Tiwari et al. have determined the effective bulk minority-carrier lifetime from
measurements on HBTs and published results [2-22]. The inferred electron lifetime
in p-GaAs as a function of net acceptor concentration is given by
J
! _ +J
V
. .
lxlO 10 1.6x10®
(2.2.6)
The above empirical expression is obtained for net acceptor concentration from 1017
cm*3 to 2X1020 cm-3. The unit of lifetimes in the above expression is seconds and the
unit of acceptor doping is cm3. %SR(ifad is the lifetime dominated by SRH
recombination and radiative recombination, and xA is the lifetime that is dominated
by Auger recombination. The importance of the bulk base recombination can be
demonstrated by examining the DC current gain, which is expressed as
R= — = -r— = Y 'aT .
I B / „ + / , + /, l-y < X r
(2.2.7)
The emitter injection efficiency, y, and the base transport factor, otp are defined as
y = 1m2. =
L
h
I P+ / „ + ' ,
and
/
1 —1
w
a r = — = —— L = sech(— ) ,
r /*
K
W
(2.2.8)
(2.2.9)
where WB is the quasi-neutral base width and Ln is the electron diffusion length.
Since Ln = ^ D n •
, where Dn will be discussed in section 2.3.4, the bulk base
region recombination affects the DC current gain by entering into the expression for
base transport factor (equation (2.2.9)) through the electron diffusion length, L„.
Chapter 2 Principles of Operation
21
This can be appreciated by plotting the DC current gain versus the base width at
different base doping, assuming unity emitter injection efficiency. Figure 2.2.4
illustrates such base transport factor limited DC current gain. It should be noted
that the rapid decrease of the current gain at high doping is mainly due to the Auger
recombination.
2.2.5
Hole Back-Injection Current
The hole back-injection current from the base into the emitter is
proportional to the injected hole concentration at the emitter edge of the emitterbase junction (junction law). In equation (2.1.9), P reaches the maximum value
when the base current consists solely of back-injected holes. In fact, for a typical
HBT, this hole injection current is virtually eliminated due to the band offset in the
hetero-interface. As a result, in most cases, Ip becomes a negligible part of the base
current as compared to the other recombination currents.
2.3
S m a l l -S ig n a l A n a l y s is
To date, many researchers have contributed to HBT small-signal modeling
[2-23 ~ 2-26]. A device-physics-based small-signal equivalent circuit model [2-23]
will be used as the basis for our analysis and model construction in chapter 5. This
device model is obtained by solving the current continuity equation to determine the
time- and position-dependent minority carrier electron concentration in the base
region of the transistor. Once the base region electron concentration is known, the
detailed two-port admittance parameters (T-parameters) of the intrinsic HBT can be
Chapter 2 Principles of Operation
22
10
DC Current Gain
N. 0 = 4 x 1 0 ^ cm
N*g=2x10'® cm
N*g=1x10 cm
103
,2
10 '
,1
10
,0
10'
0
500
1000
1500
2000
Base Thickness WQ(A)
Figure 2.2.4 The DC current gain versus the base width at different doping
concentration, assuming unity emitter injection efficiency.
Chapter 2 Principles of Operation
23
obtained. From a knowledge of the carrier distribution, the key small-signal
parameters (the transconductance, the base input capacitance, and the related
transit time constants) can be determined using the charge-control concept, which
will be examined in detail later. The parasitic elements, especially the distributed
characteristics of the base resistance and the collector-base capacitance, are then
included to develop the high frequency equivalent network model, as shown in
figure 2.3.1. The significance of this device model is its ability to provide a direct
relationship between the physical structures, the mechanisms responsible for the
device operation and the electrical parameters. The correspondence between the
physical structure and the model elements is illustrated in figure 2.3.2. The elements
in this equivalent circuit are analyzed as follows.
2.3.1
Small-Signal Parameters Based on the Charge-Control Model
The charge-control concept, introduced by Johnson and Rose in 1959 [2-
27] and used by Sparkes et al. in the analysis of bipolar transistors [2-28], is a
rather simple concept that relates the active region stored charge to the terminal
currents and voltages. The same concept is also applicable to the small-signal
analysis of field-effect transistors [2-29,2-30].
By solving the current continuity equation for minority carrier electrons in
the base region under steady state condition and applying appropriate boundary
conditions, the carrier distribution can be expressed in the following simple manner,
provided that the electron lifetime x„ is sufficiently large [2-31]:
24
Chapter 2 Principles of Operation
Cbe
B
ee
E
Figure 2.3.1 High-frequency common-emitter hybrid-rc equivalent circuit model.
Chapter 2 Principles of Operation
25
ee
be T
cc
Semi-insulating GaAs Substrate
Figure 2.3.2 Correspondence of equivalent circuit elements and device physical
structure.
26
Chapter 2 Principles of Operation
where WB is the quasi-neutral base width; /i(0) is the minority-carrier density at the
emitter-base depletion layer edge, and n(WB) is that at the base-collector depletion
layer edge, and
n(0) = ^ - e K p l,q V l,E/ a ' ) ,
Pi 0)
(2.3.2)
n(WB) = nc = - ^ ~ ,
<jvsal
(2.3.3)
and
where nie is the intrinsic carrier concentration in the heavily doped p* base and p(0)
is the base region hole concentration near the emitter-base depletion layer edge and
^BE is the base-emitter applied bias. The above equations are derived under the
assumptions that VBE » kTlq and VCB is large so that n(WB) becomes the saturated
velocity carrier concentration, nc. The stored minority-carrier base charge, QB, can
be obtained simply by integrating the excess electron density distribution across the
base-width, i.e.,
2» = AEq [ ‘ n(x)dx= Acq 4 ® s . + ncWD] .
(2.3.4)
From the distribution n(x), we can calculate the collector current as follows:
Ic = AEqD — i = AEqD
.
c
EH " d r U
EH n wB
(2.3.5)
Since QB is proportional to / c, by differentiating Ic with respect to Kbe» the
effective base charging capacitance, Cbt, can be expressed as
i-'be =
Sm o
t tc *
where gmo is the intrinsic transconductance [2-32]; and
(2.3.6)
27
Chapter 2 Principles of Operation
The parameter n is the ideality factor for collector current, and is generally very
close to unity due to diffusion-driven injection of electrons into the base [2-8]. The
intrinsic emitter-to-collector transit time is v ec = x \ + xc.
The neutral baseregion carrier transittime, x'b, isobtained bycalculating
the stored minority carrier base charge andthecollectorcurrent.For the
uniform-
base transistors,
d IC
2D n
ifll
•
( 2 -3 -8 )
where Dn is the electron diffusion constant in the base and via, is the electron
saturation velocity. These two parameters, Dn and vja), will be discussed later. In
equation (2.3.8),
is due to the carrier velocity saturation in the collector space-
charge region. With nc appearing as a background constant carrier concentration
everywhere in the neutral base, (ncWB) contributes to the stored base charge which
leads to x [2-23].
The collector-base depletion layer transit time, xcscl, is calculated from the
total induced charge in the collector body, Qc and collector current, i.e.
t CSCI,=
where
—if = —
,
dlc 2vja<
(2.3.9)'
is the base-collector depletion layer width. The factor of two arises
because only half of the charge needed to neutralize the moving charge in the
current stream is associated with hole charge in the base (the other half is
neutralized by extra ionized donors in the collector).
The small-signal input resistance for the base-emitter junction, rK, can be
found as
Chapter 2 Principles of Operation
28
31/
3/
31/
ft
rK=
(2.3.10)
where $ac (or denoted as h/e) is the ac (incremental) common-emitter current gain.
The collector output resistance, r0, can be expressed as
(2.3.11)
where NDC is the doping concentration in collector; NAB is the doping concentration
in the base. Usually r0 is very large, i.e., there is a large Early voltage or negligible
base width modulation, due to heavily doped base and lightly doped collector. The
last term in (2.3.11) is obtained, assuming that NAB » NDC and the collector and
base layers are uniformly doped.
2.3.2
High-Frequency Common-Emitter Forward Transfer Admittance
Representation
To account for the high-frequency behavior of the device, the current
continuity equation has to be solved for the time- and position-dependent minority
carrier concentration in the base region. The overall common-emitter forward
transfer admittance, Y 2I, of the intrinsic device at high frequency is represented by
(2.3.12)
where to is the angular frequency of operation [2-23]. For uniform-base transistor,
%0 = Wy(7i:2Dn) = Tj/4.93 is the 3dB cutoff frequency of Y‘21\ and x,,, = k0x0 + xcscl +
where k0 = 0.61 is a phase delay constant to approximate the exact hyperbolic
cosecant function of the complex forward transfer admittance.
Chapter 2 Principles of Operation
29
2.3.3 Parasitic Resistances and Capacitances
The emitter series resistance Ree is the sum of the emitter contact resistance
Rec and the emitter bulk resistance Reb, namely,
(2.3.13)
where Reb = WE/(qNDBp nESELE)>with WE being the quasi-neutral emitter width; NDE
the doping concentration in the emitter; and
the electron mobility in the emitter;
and SE, Le are the emitter contact width and length, respectively. The emitter
contact resistance can be calculated by Rec = pfC/ ( S ^ ) , with pfCbeing the specific
contact resistance of the emitter contact, which is readily obtained from TLM
(transmission line model) measurements in process control monitors.
The emitter-base junction capacitance, Cje, for a heavily doped base, using
the depletion approximation, is given by
AIGaAs°Et-'E
(2.3.14)
where eAIGaAs is the permitivity of emitter material or AlGaAs in this case; and xde is
the emitter-base depletion region width, with
„2
_ ^ A IAGlGaaA
A ss i ^ B E
^BE )
X de ~ ---------- 7r----------Q^de
(2.3.15)
where (pBE is the built-in potential of the base-emitter junction. The calculation of
the heterojunction diode built-in voltage has been analyzed by Chand et al. [2-34].
From the band diagram, cpflBcan be shown as
<Pbe = (EgB-<Pn-<PP+&Ec ) /q ,
(2.3.16)
where EgB is the bandgap of the GaAs base; (p„ = Ec - EF in the neutral N-AlGaAs;
and (pp is the energy measured from the Fermi level in the base to the valence band
Chapter 2 Principles of Operation
30
edge; and AEc is the conduction band discontinuity. It is noted that in the
calculation of %E the carrier degeneracy condition in the base and the smaller
electron density than doping concentration due to large donor activation energy in
the AlGaAs emitter [2-35] can all be taken into account.
The separation of base series resistance and the base-collector capacitance
into intrinsic andextrinsic parts in the equivalent circuit isa first-order attempt to
represent the distributednature of the base resistance and the collectorcapacitance.
This separation can also be used to identify the contributions from each geometrical
element to overall performance. The base resistance and collector capacitance
models have been proposed by Das [2-33] and S. Ho et al. [2-26]. The overall base
series resistance can be written as:
R* = ^bi
Rb* "h Rbc *
(2.3.17)
where Rb} is the intrinsic base resistance (spreading resistance), and
fl
6'
-P
12WbLe
A
(2. 3. 18)
Rbx is the extrinsic base resistance between base metal stripe and the emitter mesa
sidewall, and
Rbx= - ^ j f s- .
(2.3.19)
E
R be^ is the transfer resistance under the base contact, and
R =
or—
2Lb
/
CQth[ S
' c o t h
l*6L
V P<* ,
(2.3.20)
where pb = \/(qNABiip) is the intrinsic base resistivity. }ip is the hole mobility in the
base. Rfr is the sheet resistance of the extrinsic base between the emitter and base
Chapter 2 Principles of Operation
31
contact, Rbs, is the sheet resistance under the base contact; and pc6 is the specific
contact resistance of the base contact; and SB, L0 are the base contact width and
length, respectively; and $EB is the spacing between the base metal and the emitter
mesa.
The base-collector junction capacitances can also be treated in a similar
manner:
Cci is the capacitance under the emitter stripe, and
C
( 2 . 3 . 21 )
*GaA,SEL B.
Ccx is the capacitance under the base-emitter gap, and
C
( 2 .3 .2 2 )
t
* dc
Ccc is the capacitance between the base contact and the collector
Ccc = 2ecatoSBLB, ^
Xdc
(2.3.23)
where eGaAs is the permitivity of GaAs.
To represent the effective intrinsic collector capacitance, Cc, an effective
base-collector RC time constant can be defined as follows:
RbbC c
= C c i ( \ R b i + R-bx ^ R b c )
+C „(i/?6c)
^cx ^ l^ b x
+ ^bc )
n
~
The extrinsic collector capacitance, Chc, follows from
Cte = (C d + Ctt + C J - C e .
(2.3.25)
Note thatin equation (2.3.24), the total base-collectorcapacitance is
multipliedby the
contact resistance Rbc. Thus, it is necessary to minimize the
32
Chapter 2 Principles of Operation
contact resistance associated with the metal-semiconductor interface in order to
reduce the RbbCc time constant, which is the dominant parasitic that determines the
maximum oscillation frequency,/^, of the device. This will be analyzed in the next
chapter.
Finally, the collector series resistance, Rcc, can be obtained in a similar
fashion as the base series resistance and the bulk emitter resistance. For a heavily
doped sub-collector region, and relatively large area, however, the collector series
resistance is usually quite small.
2.3.4 Minority-Carrier Diffusion Coefficient and Electron Saturation Velocity
In order to calculate the base and collector transit time, it is necessary to
know the minority carrier diffusion coefficient, Dn, and the electron saturation
velocity, vM(. The minority electron drift mobility, f i f , can be empirically expressed
[2-22] as
P
8300
(2.3.26)
The minority carrier diffusion coefficient can thus be obtained through the
Einstein relationship, i.e., Dn = n/kT lq.
As the electrons in GaAs are transported through the high electric field
region in the reverse-biased collector depletion layer, they gain enough energy from
the field and transfer energy to the lattice by the generation of high energy optical
phonons. Since this process is an efficient energy loss mechanism for the electrons,
the drift velocity of the distribution reaches a limiting value where it no longer
Chapter 2 Principles of Operation
33
increases with the electric field. This value is referred to as the saturation velocity,
vsal. It has been pointed out, however, that velocity overshoot, resulting from the
nonstationary transport, in III-V compound semiconductors can be significantly
higher than their steady-state values [2-36]. Based on theoretical calculations, the
average carrier saturation velocity can be sufficiently enhanced in the
submicrometer and the ultrasubmicrometer structures [2-37] and in the properly
designed reduced field profile [2-38]. Rockett [2-39] and Katoh et al. [2-40]
studied the electron velocity overshoot by the Monte Carlo method concluding that
electron velocities greater than the steady-state values are possible in the collector
region of N-p-n AlGaAs/GaAs HBTs, but only for small values of reverse or
forward bias of the base-collector junction. Moreover, electron velocities of 7-9x
107 cm/s are only possible over about 300-500
A, just inside the collector and
at
300 K or below. In this work, the collector space-charge region is around 0.5
micron thick. Hence, we expect the velocity overshoot phenomena to be
insignificant and the saturation velocity to be given by the empirical relation [2-41]
vM = (1.28 - 0.0015 x T) x 107cm/s .
(2.3.27)
It should be noted that all of the elements in the equivalent circuit discussed
so far have been defined with the geometry or structure parameters. This is very
important in the model determination because it provides a direct link between the
design parameters and the device equivalent circuit elements such that the device
behavior over a specified frequency range can be predicted from a given device
geometry and layer structure
C h a p ter 3
D e v ic e D e s ig n C o n s id e r a t io n
3.1
H ig h -F r e q u e n c y P e r f o r m a n c e F ig u r e s
of
M e r it
The two most commonly quoted figures of merit for high-frequency
performance of microwave transistors are the unity current gain frequency or the
so-called current gain cutoff frequency, f T, and the unity power gain frequency also
known as maximum frequency of oscillation,
The former is defined as the
frequency at which the common emitter short-circuit incremental current gain Poc
(hfe) is unity; w h i l e i s defined as the frequency at which the unilateral power
gain becomes unity.
3.1.1
Derivation o ffT
As discussed in section 2.3, charge-control modeling relates the overall time
delay in terms of the controlling charge and the controlled output current. Using
Gummel's definition [3-1], f Tis given by
Chapter 3 Device Design Consideration
35
where xec is the total emitter-to-collector transit time, made up of delay components
corresponding to different regions of the device. This transit time can be expressed
as
^ = ^ + < + ' t rac/ + x, .
(3.1.2)
where x’b and xcsct have been discussed in section 2.3; and xe, xc will be discussed in
the following paragraphs.
The emitter delay xt consists of two components. One component of xe is
the emitter-base depletion layer capacitance charging time through the emitter
diffusion resistance. It corresponds to the time required to charge the base-emitter
junction capacitance, CJt. The emitter delay xe can be expressed as
x‘ =^dlc- = c ^ dlc =—
gma =JT
qlc c i- '
(3-'-3)
where dQm is the differential charge stored at the emitter-base depletion region
edges. An additional part of xe is associated with holes that are stored in the quasi­
neutral emitter. This delay component, however, was shown to be negligible in the
graded HBTs [3-2] due to the nearly unity emitter injection efficiency provided by
the band offset at the hetero-interface.
The fourth delay xc is the RC time constant for charging the effective input
capacitance arising due to the presence of the base-collector capacitance in
response to an incremental input voltage with the output terminals short-circuited
Chapter 3 Device Design Consideration
36
where CJc = Ccc + Cci + Ccx is the total base-collector junction capacitance. Equation
(3.1.4) shows the importance of minimizing the series collector and emitter
resistances in order to reduce the time constant associated with charging the basecollector junction capacitance.
The overall transit time can now be expressed as
kT
QJC
x
7 Tn+ V
„M, + ^2 vm + c * (* " + r » ) •
W 2n
W
In the above discussion, f T is derived from the charge-control model. Since f T is
defined as the frequency at which the incremental common-emitter current gain
becomes unity with output of the transistor shorted, f T can also be calculated from
the small-signal equivalent circuit outlined in section 2.3. Examination of the
incremental distribution and flow of carriers in the neutral regions of the device
leads to relationships between the junction voltages and currents. The linearized
relationships between the incremental voltages and currents are then represented by
the hybrid-rc equivalent circuit
Several comments are in order regarding the device design using equation
(3.1.5). First, for a given device geometry, the transistor must be operated at high
collector current levels in order to minimize the first term in equation (3.1.5). For
digital circuits, in which power dissipation is of prime concern, the base-emitter and
base-collector junction areas must be reduced as much as possible in order to allow
high-speed operation at lower collector currents. Tailoring of the electric field
profiles in the base and collector regions can be used to reduce the base transit time
and collector depletion layer transit time [3-3 - 3-5]. The last term in equation
(3.1.5) emphasizes the need for an advanced fabrication technology. A low-
Chapter 3 Device Design Consideration
37
resistance ohmic contact technology and process steps to minimize the extrinsic
base-collector junction capacitance, such as ion bombardment [3-6] and self­
alignment of the base and collector contacts [3-7, 3-8] are critical for realizing
ultrafast HBTs.
3.1.2 Derivation o f f ^
The second widely used figure of merit,
is associated with the power
gain of the device. As shown in the previous section, the cutoff frequency, f T, does
not depend strongly on the parasitic base resistance. This can be easily understood
because the current which must charge the capacitances does not come from the
base, but is injected through the emitter. The most important parasitic resistance
affecting the cutoff frequency is thus the emitter contact resistance. However, for
the maximum oscillation frequency, which is a measure of power gain, it will be
demonstrated that base series resistance is often the dominating factor.
Unlike the current gain, the power gain of the transistor is quite sensitive to
the source and load terminations. In order to deliver the maximum power from the
source to the load, the input and output of the transistor must be conjugately
matched to the source and load impedances, respectively. However, since the input
and output impedances of the transistor are complex at high frequencies, the
simultaneous conjugate-match condition at both ports may cause the device to
become unstable. Based on the stability of the device, two power gains are defined
as follows: the maximum stable gain (MSG) and the maximum available gain
(MAG) are the maximum power gains when the input and output are
simultaneously conjugate-matched, with MSG being defined when the device is
Chapter 3 Device Design Consideration
38
conditionally stable and MAG being defined when the device is unconditionally
stable.
These power gains are most readily calculated from two-port parameters by
straightforward analysis. Since the various two-port parameter sets can all be
expressed in terms of each other, the power gains can be measured or computed
from the most convenient parameter set. For a device having arbitrary source and
load impedances, the power gain can be expressed as [3-9]
4l//2,12Re(Z9) •Re(Kf )
G = . tr
"
,, „ ,2 >
!(//„ +Z s)-(//22 +YL) - H l2-H2i\2
(3.1.6)
where Zs is the source impedance, YL is the load admittance and H's are the twoport hybrid parameters. A detailed discussion of these parameters will be performed
section 4.2.1. Maximum available gain can be determined by varying the source and
load admittances until a maximum of equation (3.1.6) is achieved. Unfortunately,
because all the parameters in equation (3.1.6) are complex at high frequencies,
there is a frequency range in which the real part of the input impedance looking into
the base is negative. Consequently, the maximum available power gain from
equation (3.1.6) is infinite, and the transistor oscillates. In real applications, the
most useful power gain expression is that of the maximum available power gain
when the stability factor K > 2, which, in terms of T-parameters, can be expressed
as [3-10],
MAG =
.|}V Yl2! r ----------------- ^
K + j K 2- l
---------------- ,
4Re(yM)Re(K,2)-2 R e (y i2y21)
(3.1.7)
where
^
2Re(yn )Re(r22)-R e(y;2K!I)
F71--------,Z2l/l2l
'
(
}
39
Chapter 3 Device Design Consideration
The expression that determines the margin of stability is the maximum stable power
gain, which, when K = 1, is given by
MSG = j ^ | .
12
(3.1.9)
One additional power gain is the unilateral power gain, U [3-11]. This is the
maximum available power gain when the two-port network inputs and outputs have
been simultaneously matched and the feedback parameter has been neutralized to
zero. This neutralization or unilateralization is accomplished by adding a network
such that a part of the output signal is fed back to the input circuit in order to
balance out a portion of the feedback inherent in the transistor. This gain is the
highest possible power gain that an active two-port network can ever attain.
In terms of T-parameters, the unilateral power gain is given by [3-12],
iy _ y i2
t / = --------- - 2I— -------------- .
4[Re(yj, -yj2)Re(T22 -^ 12 )]
(3.1.10)
The frequency where the unilateral power gain drops to unity defines the boundary
between an active and a passive network. Theoretically, this frequency, referred to
a s /»«ix>
^ e maximum frequency of oscillation, can be shown to be the same as the
frequency at which the maximum available gain becomes unity. Experimentally, U
or MAG is calculated from the measured 5-parameters (5-parameters are converted
to y-parameters and equation (3.1.10) or (3.1.7) is used), and
is defined as the
frequency at which both U and MAG are equal to 0 dB. It is observed, however,
that the value obtained by extrapolating observed U at -6dB/octave is large than
that inferred from the measured values of MAG at the same extrapolation rule [313]. This is presumably due to the fact that the measurement frequency range of 1-
Chapter 3 Device Design Consideration
40
26 GHz potentially falls into the unstable region, which complicates the task of
extrapolation.
While MAG, MSG, and U are easily determined from two-port parameters,
equations (3.1.7) and (3.1.10) provide limited insight into the physical parameters,
such as resistances and capacitances, which influence the power gain of the device.
A first order analysis to determine the physical parameters that limit the power gain
can be done by using equation (3.1.10) in conjunction with the equivalent circuit in
figure 2.3.1. Neglecting the effects of emitter series resistance Ree and collector
series resistance Rcc on power gain, and assuming the reverse transfer admittance
Yn is zero (unilateral case), it can be shown by circuit analysis that the magnitude of
the forward transfer admittance, \Y2I\ , at high frequencies is given by
IK. I s — & — = & .—
,
21 c o - C ^
//?*,’
(3.1.11)
where f T = gJ(2itfCJ is used. Similarly, we can obtain
R e lY J s -—- ,
(3.1.12)
R e l^ ] = gm•%- = 2rfTCc .
CK
(3.1.13)
and
Thus,
IY j
_ 1
U
4Re|Yu ]Re|Y22] / 2 8jc-**C c
The maximum frequency of oscillation can be approximated from the frequency at
which U becomes unity. It is therefore given by the classical expression,
Chapter 3 Device Design Consideration
41
( 3 - u
5
)
Note that in addition to the assumptions listed above in deriving equation
(3.1.15), we have also lumped the intrinsic and extrinsic base resistances into Rbb
and Cp i.e., Rb + Rbcm = R^. The accuracy of using equation (3.1.15) to estimate
has been examined by Laser et al. [3-14]. Calculating the exact K-parameters in
equation (3.1.10) from more sophisticated equivalent circuit, like the one in figure
2.3.1 with no approximation, they concluded that the use of equation (3.1.15) to
predict / M, is useful and valid for the frequencies over which the device is
dominated by parasitic resistances and capacitances. However, equation (3.1.15)
underestimates
because of an incipient resonance due to the phase-delay
induced by the transit-time effects. The latter conclusion is also in agreement with
the findings of other researchers [3-15 ~ 3-17]. It should be pointed out that this
resonance effect is only observable at the frequencies above which transit-time
effects are dominant. For the case that the resistive and capacitive parasitics of the
device are of sufficient magnitude to obscure the effect of finite transit times, the
single RC time constant representation which gives 6dB/octave roll-off
characteristics is still adequate.
Despite its limitations, equation(3.1.15) illustrates a few general points
about the power performance of bipolar transistors at high frequencies. In order to
achieve the highest
both the base resistance and the base-collector junction
capacitance must be minimized. Equation (3.1.15) demonstrates the advantage of
HBTs over homojunction bipolar transistors as a consequence of a higher allowable
base doping (and thus lower base resistance). While the intrinsic base-collector
Chapter 3 Device Design Consideration
42
junction capacitance can not really be modified by the fabrication process (i.e., only
can be changed by different geometries and epitaxial structures), the extrinsic basecollector junction capacitance can be reduced by suitable device fabrication
techniques, such as emitter-base self-alignment and extrinsic collector layer ion
bombardment. A combination of these techniques has allowed the realization of
AlGaAs/GaAs HBTs w ith /^ = 218 GHz [3-18].
3.2
L ayout D esign
Based on the figures of merit discussed in the previous section, some impor­
tant aspects and approaches used to design the devices for microwave/millimeterwave applications are presented. The device structure used in this discussion is
illustrated in figure 3.2.1.
3.2.1
Emitter Width SE
The emitter stripe width, SE, is one of the most critical geometrical
parameters in the design of microwave transistors. The selection of SE has
implications on the emitter and base resistance, the emitter and collector
capacitances, and therefore the operating frequency as well as the power gain.
Theoretically,/^ is inversely proportional to the emitter stripe width, because the
RhbCjc time constant is, to the first order, proportional to (SE)2. This relationship has
also been demonstrated experimentally. Figure 3.2.2 shows f max as a function of
emitter stripe width from published results.
Chapter 3 Device Design Consideration
u c r — - - + £•
N • AlGaAs EmJitter
p f - GaAs B ate
n* • GaAs Collector
n* • GaAs Sub-collector
Semi-Insulating GaAs Substrate
Figure 3.2.1 The device structure used in the discussion.
44
Chapter 3 Device Design Consideration
(GHz)
100
Ref[1 -10]
M
I
Ref(1-10]
max
0
120.9(GHz)/S
1
2
3
4
Emitter Width S £ ((im)
Figure 3.2.2 Experimental data of/ „ , as a function of emitter stripe width with LE ~
10 jam and Jc ~ 1.5xl04 A/cm2.
Chapter 3 Device Design Consideration
45
For devices designed for high frequency application, one must also consider
the current crowding effect because the high-frequency component of the emitter
current is concentrated at the emitter edge [3-19]. It should be noted that the
current crowding effect exists even for the DC operation. However, as analyzed by
Liu [3-20], the high-frequency current crowding effect was found to impose more
stringent design consideration on the emitter width than the DC case. Consequently,
only high-frequency effect is discussed here. This effect is characterized by the
emitter utilization factor (SEeJ3/SE), which is defined as the magnitude of the
microwave component of emitter current normalized to that at the emitter edge [321], i.e.,
Emitter UtilizationFactor=
(3.2.1)
where j e(x) is the small signal current density distribution under the emitter at the
frequency/, and
where A is a constant, and the complex wave propagation constant, y, can be
expressed a s ,
where pSB is the intrinsic base sheet resistance, gz is the small-signal input resis­
tance, CKis small-signal input capacitance, gmo is the intrinsic transconductance, Pae
is the incremental current gain and f T is the intrinsic cutoff frequency ( =1/2tcx',c). In
Chapter 3 Device Design Consideration
46
deriving (3.2.3), the emitter-base junction capacitance Cje has been neglected as
compared to emitter base charging capacitance Cbe (see section 2.3) which is
justifiable in HBTs for normal operating conditions. Figure 3.2.3 shows the
calculated emitter utilization factors as a function of the emitter width under
different frequencies. To choose an emitter width with near unity emitter utilization
factor for the frequency of interest can ensure the current carrying capability for
HBTs to be dependent on the emitter area rather than the emitter periphery.
Equations (3.2.1) ~ (3.2.3) thus provide a good guideline for designing the
optimum emitter width.
3.2.2
Emitter Length LE
The emitter finger length LE is primarily determined by the emitter
metallization resistance [3-22] and, in the case of power device design, junction
temperature distribution along the emitter length [3-23]. The limit on the emitter
stripe length arises due to the finite thickness (typically 2.5 pm, in this work) of the
emitter metallization. In order to maintain the uniform vertical flow of the emitter
current, the maximum emitter stripe length LE(mttX) can be defined such that the
emitter contact resistance Rec is at least an order of magnitude larger than the
emitter metallization resistance, i.e.,
Am
x S£
£
1
0
,
S£
where p„ is the specific contact resistance of the emitter contact and
(3.2.4)
is the
emitter metallization sheet resistance. For the case of the device used in this work,
pec = 5x1 O'7 Q-cm2, and pM= 0.01 QJsq, LE(max) = 22 pm.
Chapter 3 Device Design Consideration
47
1.0
Emitter Utilization Factor
0.8
0.6
0.4
-------------f=30 GHz and
-------------M O GHz and
7 -------- 7 f=30 GHz and
• -------- • M 0 GHz and
0.2
0
1
J c=5x10 A/cm‘
.£=5x104 A/cm]
J =1x10 A/cm"
£ = 1 x 1 04 A/crW
2
3
4
Emitter Width S£ (urn)
Figure 3.2.3 Calculated emitter utilization factor as a function of the emitter stripe
width with/r = 40 GHz, Pac = 70 and base sheet resistance of 400 QJsq.
Chapter 3 Device Design Consideration
48
Additionally, one needs to consider the phase matching condition. At
microwave frequencies, the wavelength of the signal being amplified can be
comparable to the dimensions of the active device in use. This is especially true for
device fabricated on semiconductors of relatively high dielectric constant, such as
GaAs (er = 12.9). Unless wave propagation is an intrinsic part of device operation,
the longest dimension of the device should kept smaller than approximately A/8
(where X is the wavelength in the semiconductor, which is 835 |im at 100 GHz). In
this way, in-phase operation of the device for good efficiency can be ensured. This
is especially important in the design of power devices.
3.2.3 Base Contact Width SB
The design of the base contact width SB is crucial in maximizing f max. Larger
SB can reduce the base contact resistance and thus the base series resistance.
However, smaller SB is desired to minimize the base-collector capacitance. As
pointed out in section 3 .1 ,/ ^ depends strongly on the R^C^ product. Therefore,
the RbhCjc fu116 constant has to be minimized for optimum f max. One approach has
been to design the base contact width such that SB = (LT)B, where (LT)B is the
transfer length of the base contacts and is given by [3-24]
(3.2.5)
where
is the specific contact resistance of the base contact and Rbs. is the sheet
resistance under the base contact. The base contact resistance, Rbc, which has been
discussed in section 2.3, can be re-written as
Chapter 3 Device Design Consideration
49
R = M l k coth
6c
2-L b
(3.2.6)
From equation (3.2.6), it is clear that the dependence of the base contact resistance
on SB comes solely from the hyperbolic cotangent term. On the other hand, the
extrinsic base-collector capacitance Cjc depends linearly on SB. With SB = (Lr)fl,
hyperbolic cotangent term in (3.2.6) increases to 1.3 of its minimum value, (i.e.,
cothOc)!^.,; = 1), and increases to 1.2 of the minimum value if SD= 2(Lr)fl is used.
However, the device with SB = (LT)B can reduce the value of Cjc by 40% as
compared to the device with SB = 2(LT)B, assuming SB = SE. Therefore, it can be
shown that using SB= (LT)Bwill result in a higher f max than using SB > 2(Lr)B. In fact,
using a simple simulation, it is found that optimum
can be obtained when SB is
designed to be slightly less than (LT)B [3-7]. For a sheet resistance of 400 QJsq
(e.g., GaAs base doping of 2xl019cm 3, and thickness of 1500 A), and pc6 of 5x10-®
fi-cm2, SB = 1 pm should be used, unless other means of reducing extrinsic basecollector capacitance are employed.
3.3
E p it a x ia l S t r u c t u r e D e s ig n
The epitaxial layer structure, i.e., the vertical dimensions and the impurity
profiles, plays a key role in designing HBTs. In this section, we focus on the design
criteria for enhancing the high-frequency performance of the device.
3.3.1
Abrupt versus Graded Emitter-Base Junction
One of the most important features of molecular beam epitaxy (MBE) is the
ability to grow structures with abrupt transitions between materials with different
Chapter 3 Device Design Consideration
50
energy bandgaps. The energy band diagram of such abrupt junctions reveals
discontinuities in the conduction and valence bands at the hetero-interface. An
alternative approach is to gradually vary the composition between the two different
materials in order to smooth out these band discontinuities and thus form a graded
junction. Figure 3.3.1 compares the energy band diagrams of abrupt and graded
emitter-base junctions of AlGaAs/GaAs HBTs. Examination of figure 3.3.1 brings
out the respective advantages of each type of junction. Compared to a
homojunction (shown as dashed lines in figure 3.3.1) the difference between the
energy barriers for holes and electrons (qAVp - qAVn) is AEg for a graded junction
and AEv for an abrupt junction. It should be pointed out that this difference occurs
because the energy barrier for electrons of an abrupt junction is much larger than
that of a graded junction (qkVnAbmp, = AEc + qAVnCradtd), although the energy
barriers for holes are apparently equal, i.e., qAVpAbrupl = qAVpGraied. Since for
AlGaAs/GaAs heterojunctions AEv ~ 0.35A£S, the injection factor (equation
(2.1.10)) for an abrupt Al0JGa07As/GaAs HBT is IJIp <*= txp(AEy/kT) ~ 160 (as
opposed to 2xl06 for a graded junction). Therefore, despite the fact that the backinjected diffusion hole current in the emitter of an abrupt junction is comparable to
that of a graded junction, the injection ratio is decreased for an abrupt junction
device. However, as described in section 2.2, the base current of a HBT consists of
several components, including the emitter space-charge recombination current
which is directly proportional to the intrinsic carrier concentration («,.). Because the
heterojunction suppresses the back injection of holes, most of the recombination
inside the emitter-base space-charge region occurs near the hetero-interface. As can
be seen from figure 3.3.1, the energy bandgap near the hetero-interface is
Chapter 3 Device Design Consideration
A brupt Junction
51
Graded Junction
Figure 3.3.1 Comparison of energy band diagrams of abrupt and graded hetero­
junctions.
Chapter 3 Device Design Consideration
52
significantly larger (/t; is smaller) for the abrupt junction, hence the emitter-base
space-charge current both in the bulk and the surface will be smaller for an abrupt
junction device relative to a graded junction device. In practice for an abrupt
AlGaAs/GaAs HBT, the decrease in injection ratio is compensated by the decrease
in recombination at the surface and in the bulk of the emitter-base space charge
region [3-25].
Another consequence of the larger energy barrier for electron flow in the
case of the abrupt junction is that the built-in voltage and therefore the turn-on
voltage of abrupt heterojunctions is larger than that of a graded junction. While an
increase in the turn-on voltage is usually not important in microwave applications,
especially in power applications where the devices operate at high collector-emitter
voltages, although it may reduce the efficiency slightly, it leads to larger power
dissipation in digital circuits, especially in high speed-logic circuits, where the
devices operate over small voltage swings.
An additional property of abrupt junctions is that the conduction band spike
may act as a "ramp" to launch hot electrons into the base. Since these energetic
electrons possess a higher velocity then thermalized electrons as they traverse the
base region, both the neutral base recombination and the base transit time are
possibly reduced. The actual resulting benefit depends on how much excess energy
these launched electrons receive from the electric field inside the junction. If the
electric field at the interface is too high, some fraction of these electrons will scatter
into the lower mobility (and therefore lower velocity) satellite conduction-band
valleys (L and X valleys), resulting in an insignificant overall enhancement in
transport through the base. In addition, if the base is sufficiently thin, some of these
Chapter 3 Device Design Consideration
53
hot electrons will enter the collector high field region and readily acquire sufficient
energy from the collector field to create avalanche multiplication [3-26], reducing
the breakdown voltage. Therefore, the benefit of launching hot electrons is difficult
to quantify.
In spite of these issues of ballistic transport, recombination, etc.; in practice,
the most important issue of abrupt versus graded junctions is that a compositionally
graded junction can better tolerate the base dopant (Be) diffusion from the base
into the emitter provided that the p-dopant is still confined in the emitter-base
graded region [3-27,3-28]. Since the base doping is typically 10 to 100 times larger
than the emitter doping in a high-frequency HBT, even a slight penetration of Be
into the AlGaAs easily counterdopes the metallurgical N-type region, forming an
AlGaAs PN homojunction. Thus, all the advantages associated with the
heterojunction are lost. On the other hand, a similar amount of Be movement into a
graded junction HBT has a smaller effect (the turn-on voltage is increased slightly).
Not only is the growth of heavily doped HBTs with abrupt junctions more difficult,
abrupt HBTs may be also be more susceptible to reliability problems caused by the
Be movement during operation [3-29]. For this reason, the HBTs used in this study
are graded junctions.
3.3.2 Base Design
The design variables for the base layer are the thickness, doping, and profile
(composition or doping grading). An essential component of the base design calls
for reducing the base resistance and the base transit-time simultaneously. Roulston
et al. have shown that, as a first-order analysis, if all vertical delays, except the base
Chapter 3 Device Design Consideration
54
delay, are held c o n stan t,/^ is maximized when the base transit time equals half of
the total transit time [3-30]. The optimization is obtained by differentiating/^ with
respect to
and setting the derivative to zero. This maximum is the result of a
trade-off between the base resistance and the base transit-time. When the collector
is fully depleted under operating voltage and at high current , the optimized base
width ( W b) opt *s given by
where T| is the field factor; rj = 2 for the uniform base and T| > 2 for the graded base
transistors. For a uniformly doped base with NAB ~ 2xl019 cm3 and Wc = 5000
(Wb)0pt is approximately 1250
A,
A. With (3.3.1), the optimized maximum oscillation
frequency ( / ^ o / r can be expressed as
(3.3.2)
j
where F is the ratio of collector to emitter junction area, typically on the order of 24. It should be pointed out that / Ml is shown to be inversely proportional to SE
again, as discussed in section 3.2.1. The maximization in equation (3.3.2) is a direct
result of a trade-off between base resistance and the base transit-time.
While the optimum base width has been derived in equation (3.3.1), the
base doping, NABshould be kept as heavy as possible in order to m aximize/^, thus
pushing for higher operating frequency. GaAs can be doped with either Be or C at
concentration up to ~ 1020 cm 3 as reported in the literature [3-31, 3-32]. Because
of the concentration-dependent Be diffusion coefficient, the increase of the Be
Chapter 3 Device Design Consideration
55
doping level above 5xl018 cm3 has been found to cause surface segregation [3-33]
and diffusion
[3-34]
during growth and subsequent device processing.
Consequently, degradation of current gain via increased hole injection will occur.
Growth techniques, such as high group V overpressure during growth [3-35, 3-36],
low substrate temperature [3-36, 3-37] and the addition of a small amount of In to
the Be-doped layers [3-38], have met with some success. The use of other dopant
species, such as C [3-39], or the use of different substrate orientations [3-40] are
also being investigated.
Since carbon does not exhibit the enhanced diffusion in GaAs shown by Be
at high concentrations, using C as an alternate acceptor dopant in AlGaAs/GaAs
HBTs has recently attracted a great deal of attention. HBTs with epitaxial carbondoped base layers have already been realized by various growth systems [3-41 ~ 344]. The minority electron transport properties in p+-GaAs doped with Be and C
have been compared using the zero-field time-of-flight (ZFTOF) technique [3-45].
This work concluded that D ^, Ln (electron diffusion length) and the majority hole
mobility are comparable for p *-GaAs doped to ~ 1019 cm 3 with both Be and C
dopants. High performance carbon-doped HBTs with base doping of 1020 cnv3 [332] also suggested that similar minority electron properties can be obtained for
doping > 1019cnv3.
As for the reliability issue of the C-doped materials, using nuclear reaction
analysis and Ruthford backscattering (RBS), Hofler and Hsieh found that at least
25% of carbon was interstitial in 5xl019cnv3 MOCVD and MOMBE wafers [3-46].
This result implies that C redistribution similar to Be may occur under bias stress
for devices prepared with heavy C doping, assuming C and Be redistribution occurs
Chapter 3 Device Design Consideration
56
through similar interstitial mechanisms. Recently, Yamada et al. reported the
reliability characteristics of AlGaAs/GaAs HBTs with Be and C doped (lxlO19 cm*
3) layers [3-47], Using 10% degradation in P as the failure mechanism, both devices
have shown acceptable performance with median-time-to-failure (MTTF) rate of
1.8xl08 hours and 4.2x10s hours for Be and C, respectively, at 125°C junction
temperature. The Be-doped HBTs used in this study were grown under reduced
substrate temperature and high arsenic-gallium flux ratio conditions [3-36]. Indeed,
utilizing very low substrate temperature (300°C), well controlled arsenic-gallium
flux ratio, and migration enhanced epitaxy (MEE) technique, Zhang et al. have
recently demonstrated well defined and stable Be profiles for p = lxlO19 ~ lxlO20
cm*3 [3-48]. Further comprehensive reliability evaluation on Be- and C-doped
materials for doping in the range of lxlO19 ~ lxlO20 cm*3 will be very important to
devices for microwave/millimeter-wave applications.
Modification of the basic uniform base profile to a graded-base profile has
also shown improved device performance. As is well known, the graded base and
the resultant built-in electric field can aid the transport of minority electrons across
the base region and significantly shorten the base transit time, resulting in higher
cutoff frequency, f T . For AlGaAs/GaAs HBTs, both composition grading [3-49]
and doping grading [3-50] have been demonstrated with improved performance.
Since the electrons in the base are accelerated and gain kinetic energy from the
field, if this energy is larger than 0.31 eV (energy difference between L and T
valley), some electrons can transfer to the lower mobility satellite valleys.
Therefore, grading of the base must be done carefully. Normally, the aluminum
composition in the base varies from 10-15% (near the emitter-base junction) to 0%
Chapter 3 Device Design Consideration
57
(near the base-collector junction). It is worthwhile to note that when doping
gradients are employed in the base, the base bandgap shrinkage has to be taken into
account. The effective electric field in the quasi-neutral base is thus composed of an
electric field due to the doping gradient and a quasi-electric field due to the
position-dependent band structure. The former effect is the impurity drift field and
tends to accelerate electrons across the base. The latter field, which is caused by the
bandgap shrinkage effect, however, is a retarding field. As a result, the doping
grading effect on th e /r may not be sizable. Another advantage for compositional
graded base, which has been discussed in section 2.2, is the capability of preventing
injected electrons from reaching the exposed extrinsic base surface, and thus
eliminating the emitter-size effect [3-51].
3.3.3
Collector Design
The collector structure has an enormous influence on
f T, breakdown
voltage, and current-handling capability, through the space-charge limited current
effect, also known as the Kirk effect [3-52]. In the case of power applications, it
also affects the power output, power gain, and the efficiency. The design variables
for the collector layer are typically the doping and epitaxial collector thickness.
Selection of doping and thickness generally requires compromising between
breakdown voltage, current-handling capability and frequency performance, and
thus varies with specific applications.
An important limit on collector current density for bipolar transistors is the
base pushout or Kirk effect. When the electron density injected into the basecollector depletion region becomes comparable to the background donor density,
Chapter 3 Device Design Consideration
58
the fields in the base-collector depletion region become distorted. The critical
current density which marks the onset of this phenomenon is expressed as
J Sc i = Q V saln c = q v ll
jy
00
| ^ Eoe r(^Cfl * 9 0 0 )
qW 2c
(3.3.3)
where nc is the critical electron density at the onset of space-charge limitation in the
depletion region, (pCfl is the base-collector built-in potential and VCB is the basecollector applied bias. Above this current density, holes penetrate into the collector
leading to increased base transit time, reduced current gain and the falloff of f T. As
can be seen from (3.3.3), the maximum collector current is limited by the electron
saturation velocity, vtal, collector doping NDCand collector thickness Wc . Attaining
electron velocity overshoot, via the special profile design [3-4, 3-5, 3-53], and the
use of a collector material with a high steady-state velocity at high electrical field
[3-54], and a thin highly doped collector are all beneficial to the operating current
For power HBTs, however, thicker and lightly doped collector layers are
usually desired to sustain a large breakdown voltage at the base-collector junction.
The breakdown voltage is typically that of the reverse-biased base-collector p-n
junction if the device is operated in common-base mode. Therefore, the breakdown
voltage is given by
BVcm = ECWC - Wlc SqNc
p?- ,
2e„e, ’
(3.3.4)
where Ec is the critical breakdown field. Equation (3.3.4) shows that thicker
collector layers with low doping concentrations are needed to maximize breakdown
voltage. However, the base-collector depletion layer transit time, xcscl, which is
59
Chapter 3 Device Design Consideration
usually a substantial fraction of the overall transit time, also increases with the
collector layer thickness because of the following relationship:
W
t = ^ >
(3-3.5)
^sat
where Wc has been used for
, indicating a fully depleted collector layer.
Counteracting this, thick collectors result in lower base-collector capacitance C^,
which reduces the collector charging time constant, thus higher
and f T can be
obtained.
McGregor et al. recently proposed a procedure to attain the collector
doping for maximum / ‘max and predict the power gain at peak f T (the current gain
cutoff frequency corresponding to the onset of Kirk effect) [3-55]. Differentiating
fmax
respect to NDCand setting the derivative to zero, the NDCfor which f max is a
maximum can be shown as
fcT_
N oc= —
q
C*_
„ : "
.
2qAEvsalXb
(3.3.6)
Even with several severe assumptions made in their analysis to facilitate a simple
analytic expression, the simple relationship developed can provide a good starting
point for the collector doping design. For emitter doping of 5x1 O'7 cm 5, base
doping of 2xl0/9 cm 5 and base thickness of 1000 A, NDC~ 10/5 env5 is obtained. In
most cases, however, the collector doping of around 10/6 cm 5 is chosen to achieve
a higher current density operation.
Chapter 3 Device Design Consideration
3 .4
60
M a t e r ia l A s p e c t
The AlGaAs/GaAs HBT is up to now the most widely used HBT due to the
excellent lattice match and large bandgap difference between AlAs and GaAs. High
electron mobility and substantial velocity overshoot as well as high quality semiinsulating substrates (compared to Si and InP) for GaAs has made this material
system highly suitable for microwave integrated circuit applications. So far, the
state of the art performances have been mostly obtained with AlGaAs/GaAs HBTs.
There are, however, several disadvantages in using this material system. First of all,
relatively high (~ 60% of bandgap difference) potential barrier appearing in
conduction band edge between AlGaAs and GaAs. As a result, one has to employ
compositional grading on this heterojunction to make smooth transition for
maximum electron injection efficiency, as we have discussed in section 3.3.1.
Secondly, A l^ G a^ s is quite reactive to oxygen and is plagued by the donorrelated deep traps, known as DX centers, if the A1 composition x is greater than
about 22%. Consequently, very high purity A1 (6N~7N) has to be used to reduce
the space-charge recombination current in the emitter-base junction region in order
to obtain high DC current gain. Also, the A1 composition used in the emitter layer is
usually kept below 30% to minimize the concentration of DX centers. While high
DX concentration may not have detrimental effects on switching characteristics of
AlGaAs/GaAs HBTs [3-56], it was found that the nature of capture and emission of
electrons by DX centers in the AlGaAs near the surface of the emitter-base junction
is responsible for the origin of the anomalous noise "bump" observed at
intermediate frequencies [3-57].
Chapter 3 Device Design Consideration
61
Ga^In^P/GaAs HBTs lattice-matched to GaAs have been proposed by
Kroemer [3-58] to improve the carrier injection into the base because of the higher
bandgap of the Gaj ; In49P (1.88eV) and the favorable band lineup at the
heterojunction. Figure 3.4.1 demonstrates the comparison of the band lineups
between AlJ0G a70As/GaAs and Gaj ; In49P/GaAs [3-59]. One can readily observe
the superior features, for HBT applications, of the Gajyln^P/GaAs heterojunction.
The smaller conduction band discontinuity (AEc £ 120 meV) eliminates the need
for the heterojunction grading required for AlGaAs/GaAs system. The larger
valence band discontinuity provides a much higher potential barrier to effectively
block the hole injection, i.e., the
ratio can be further improved almost
regardless of the base doping. Other attractive features are small offset voltage (40
meV) achievable [3-60] and lower reactivity with oxygen of GalnP with respect to
AlGaAs and the etching selectivity between GalnP and GaAs.
0.12 eV
0.22 eV
1
^
AlGaAs
Eg
=
1.79 eV
i—
GaAs
GalnP
GaAs
Eg
Eg = 1.42eV
J__
A l = 30%
“
—
=
_L _
T ' ~
0.15 eV
E g =^1.42 eV
1.88 eV
0.34 eV
.
Ga = 51%
Figure 3.4.1 Band lineups between AljGa7As/GaAs and GaJ;In49P/GaAs material
systems.
Chapter 3 Device Design Consideration
62
To date, Ga^In^P/GaAs HBTs have already demonstrated excellent DC
performance [3-60, 3-61] and comparable RF [3-62, 3-63] performance to
AlGaAs/GaAs HBTs. The actual experimental work on this material system is not
performed in this thesis. All the design criteria and modeling technique developed in
this work, however, are applicable to the Ga^In^P/GaAs HBTs. In view of the
highly desirable and promising features of Ga^In^P/GaAs HBTs, future research
and development on this material system needs to be emphasized.
C h ap ter 4
D e v i c e F a b r ic a t io n
4.1
D e v ic e F a b r ic a t io n
4.1.1
Epitaxial Structure
and
E x p e r im e n t a l R e s u l t s
Table 4.1.1 shows the epitaxial structure for the HBTs used in this work.
The structures were grown by MBE on (100) oriented semi-insulating (S.I.) GaAs
substrate. Some of the wafers were grown at Penn State, while most were
purchased elsewhere. Dopants for the n-type and p-type layers were Si and Be,
respectively. In this section, the purpose of each layer is highlighted.
The emitter layer consists of an "emitter-cap" or "emitter-contact" layer and
a wide band-gap layer. The cap layer is used to make low-resistivity ohmic contacts
to the emitter, thereby reducing the emitter contact resistance. This layer consists of
high conductivity GaAs with a thin layer of AljGa7As, the composition of which is
gradually changed to match that of the cap and wide band-gap emitter layers. The
same structure also exists between the wide-gap emitter and the GaAs base layer.
The smooth transition in the conduction band can maximize electron injection
efficiency. The aluminum composition in the emitter is chosen so that the bandgap
Chapter 4 Device Fabrication and Experimental Results
64
difference between the emitter and the base is AEg »
kT. Traditionally, an
aluminum composition of 30% is used to avoid a high concentration of deep level
traps, and is adopted in this work. It should be noted that, theoretically, an A1
composition of 20% is still sufficient to yield AEg »
kT\ and this reduction of
aluminum mole fraction may eliminate anomalous low-ffequency noise [4-1]. The
selection of a graded heterojunction over an abrupt heterojunction has been
discussed in section 3.3.1.
T a b l e 4.1.1
MBE W a fe r E p it a x ia l S t r u c t u r e
Layer
«+-GaAs cap
Graded AlGaAs emitter
A/-AlGaAs emitter
Graded AlGaAs emitter
A1 composition
Doping (cm-3)
Thickness (A)
0
5 x l 0 18
75 0
0-0.3
5 x l 0 17
300
0.3
5 x l 0 17
1200
0 .3 -0
5 x l 0 17
300
p+-GaAs base
0
2 x l 0 19
1500
/i-GaAs collector
n+-GaAs sub-collector
0
3 x l 0 16
5000
0
5 x l 0 18
6000
S.I. GaAs substrate
0
-
-
The design consideration for the base and collector layers is presented in
section 3.3. To reduce the base series resistance, the base layer is very heavily
doped. The thickness is a compromise between base resistance, transit time, and
transport factor, which, in turn, affects the DC current gain. The collector is
Chapter 4 Device Fabrication and Experimental Results
65
relatively thick and lightly doped to reduce the collector capacitance and increase
the breakdown voltage. The sub-collector is heavily doped to lower the collector
contact resistance.
4.1.2 Self-Alignment Technique
As explained earlier, it is desirable to place the emitter active area and base
contacts as close to each other as possible to reduce base series resistance and
improve device high-frequency performance. The technique which achieves this
purpose is commonly called self-aligned (SA) processing. Dumke et al. proposed
the first self-aligned approach for AlGaAs/GaAs HBTs [4-2]. Since then, many
other techniques have been reported [4-3 ~ 4-9]. In this section, a simple triple­
level photoresist liftoff technique to accomplish this process is described. The
schematic diagram for this SA process is illustrated in figure 4.1.1.
After emitter mesa etch, the photoresist was kept intact on the wafer
surface and served as a protective film for the emitter ohmic metal. Two layers of
photoresist, consisting of a bottom layer of polymethylmethacrylate (PMMA) and a
top layer of regular photoresist, were spun sequentially on the wafers. The top
photoresist was delineated by regular UV exposure and photoresist development
In order to form a overhang profile facilitating the later liftoff process, the bottom
PMMA was undercut with deep UV flood exposure, followed by chlorobenzene
development. The wafer was then subject to base ohmic metal evaporation. Finally,
the triple-level photoresists and the unwanted base metals were lifted off
simultaneously. The resultant structure has base metal self-aligned to emitter active
area with the separation controlled by the degree of the undercut during the etch
Chapter 4 Device Fabrication and Experimental Results
Collimating Base Ohmic Metal Evaporation
3rd Level PR
1st PR
2nd Level PR
(PUMA)
Sub-Collector
Seml-Insulatiug GaAs Substrate
Figure 4.1.1 Schematic diagram for the self-aligned technique.
Chapter 4 Device Fabrication and Experimental Results
67
down to the base layer. This spacing is typically 0.25 |im in our devices. Figure
4.1.2 shows the SEM photography of the self-aligned structure with a 0.25-|xm
spacing between emitter mesa wall and base metal.
Another widely used self-aligned technique is to treat the emitter metal as an
etch mask. The undercut under the emitter metal serves to control the separation
between the emitter sidewall to the base ohmic metal. This approach, however,
leads to anomalous etching characteristics. Since the emitter ohmic metal is
protected by the photoresist in our approach, common failure mode of the emitter
metal shorted to the base metal can be effectively eliminated. In comparison to
other complicated self-aligned technique, such as Si02 sidewall deposition followed
by RIE etching-back process [4-8] and multiple ion-implantation process [4-7], this
technique is much simpler and provides higher yield.
4.1.3
Processing Steps
The fabrication process described here was adopted from M/A-COM's
existing GaAs MESFET process technology. A self-aligned emitter mesa to base
metal technique was developed specifically for HBT fabrication. Additionally, the
entire process was completed by M/A-COM's device development group at M/ACOM's MMIC facility. The device was fabricated with a triple mesa structure. All
the mesas in the HBT structure were constructed using wet chemical etching
(WCE). No ion-implantation steps were used either for isolation or reduction of
extrinsic collector capacitance. This process has been successfully demonstrated on,
first, 8-pm and later 3-(im emitter-width HBTs.
Chapter 4 Device Fabrication and Experimental Results
2 0 K V U D : 1 2 MM
68
S = OG0 O0 P =0 0 0 0 0
Figure 4.1.2 SEM photography of the self-aligned structure with a 0.25-pm spacing
between emitter mesa wall and base metal.
Chapter 4 Device Fabrication and Experimental Results
69
The epitaxial layer structure for the MBE wafers has been given in table
4.1.1. A schematic representation of the process sequence up to active device
formation is shown in figure 4.1.3; and descriptions of each processing step are
explained below.
(1). Emitter ohmic contact:
The first process step is the formation of the emitter contact layer by the
liftoff technique. Pre-clean treatment is used to remove the native oxide on the
GaAs surface. Ohmic contacts consist of 3300-A-thick AuGe/Ni/Au layers
sequentially thermally evaporated and then lifted off.
(2). Emitter mesa etch to base layer:
Emitter mesa etch is the key step in the success of the entire process. A
suphuric acid based wet etching solution is used to achieve a preferred (slight
crystallographic anisotropy) etching profile for the subsequent self-aligned process.
In addition to controlling the etch depth by a careful prior-to-etch calibration, there
are two other methods used to monitor the exposure of the p+-GaAs base layer.
One method is to measure the breakdown voltage between two tungsten needles
probing the surface [4-10]. The surface breakdown voltage generally depends on
the doping concentration, and the surface conditions of the material. For the heavily
doped p +-GaAs ip ~ 2 xl019 cm"3), the breakdown voltage value is usually less than
3.5 V, and for N-AlGaAs (n ~ 5 x l0 17 cm*3), the value is approximately 6-10 V. It
is noted that during the AlGaAs layer breakdown measurement, the current passing
through the two probes has to be limited to a very small value to prevent the
current from tunneling through the remaining AlGaAs layer, which would result in
an irreversible, destructive breakdown [4-11]. The second method is to measure the
Chapter 4 Device Fabrication and Experimental Results
70
Emitter Ohmic Veial Eroporallon and liftoff
M
X
Emitter Mesa Definition
Vet Etching to Base Layer
Sub-Collector
Semi-Insulating C&Ai Substrate
M
iZZZL
Base Ohmic Metal Evaporation
Triple-Lerel Photoresist liftoff
Sub-Collector
Base Ifesa Definition
Semi-Insulating CaAs Substrate
Vet Etching to Sub-Collector layer
Figure 4.1.3 (a), (b) Schematic representation of the HBT fabrication process used
in this work.
Chapter 4 Device Fabrication and Experimental Results
71
Collecter Ohmic C otU d lieUI EnponlioD end liftoff
CoDtcUr M en DefimUoo
Tet Rchb( to Seml-IimUUsf SnM nte
iDojini it 370 Cfor 60 mc
Setni-IsnUUsi Ceil Silotnte
W
FKVD Nitride DepodUoo
O n H ij Metil b ip o n tio o u d LUloB
Ktride
Seml-hxulitinj Ceil Subetnte
W
Figure 4.1.3 (c), (d) Schematic representation of the HBT fabrication process used
in this work.
Chapter 4 Device Fabrication and Experimental Results
72
diode I-V characteristics between the exposed area and the emitter contact pads. A
rectifying I-V characteristics can be observed once the base layer is revealed.
(3). Base ohmic contact:
Contacts are made to the base layer by the triple-level photoresist liftoff
technique outlined in the previous section. E-beam evaporated 3000-A-thick
Au/Zn/Au is used for p-ohmic metals.
(4). Base mesa etch:
The mesa is etched down to the /i+-GaAs sub-collector layer for collector
contacts. A phosphoric acid based wet etching solution is used. This isotropic
etchant with an etching rate of 50-60 A/sec provides the sloping sidewalls preferred
for metal step coverage.
(5). Collector ohmic contact:
Contacts are made to the sub-collector layer by using a liftoff technique and
metallization scheme similar to that employed for the emitter contact. Alloying for
all three contacts was carried out simultaneously at 370°C for 60 seconds. At this
point, the processing of individual devices is completed.
(6). Collector mesa etch:
Devices are isolated from one another at this stage by removing the sub­
collector layer between them. Again, the phosphoric acid based etchant is used to
accomplish the device isolation. Ion-implantation damage can also be used to
preserve the device planarization. To simplify the process, however, this approach
was not used.
(7). Silicon nitride deposition and top via etch:
Chapter 4 Device Fabrication and Experimental Results
73
A 5000-A-thick silicon nitride passivation layer is deposited over the entire
wafer surface using plasma enhanced chemical vapor deposition (PECVD).
Photoresist patterns are defined for the top via hole areas, and silicon nitride is
etched from these areas using SF6 plasma.
(8). Overlay metals:
In order to interconnect the emitter, base and collector contacts of the
device to the probe pads through the top via holes, a 2.5-|am-thick metal Ti/Pt/Au
e-beam evaporated metal is formed again by the liftoff technique.
(9). Airbridge formation and street etch:
Depending on the layout, the use of the airbridge can reduce the parasitic
capacitances. In the case of multiple-fingered and multi-celled structures, the
airbridge connections are necessary to prevent shorting of the device. Instead of
conventional electroplating, the liftoff technique is used for airbridge fabrication
due to more reliable, reproducible, better quality metal produced. It is also a
simpler process. The process is very similar to that of base ohmic metal formation.
Three layers of photoresist are used with the bottom resist defined by the airpost
mask and the top resist defined by the airspan mask. The top and bottom
photoresists are separated by a thick PMMA layer. The PMMA was flood-exposed
to create the undercut profile to facilitate the liftoff of the Ti/Pt/Au e-beam
evaporated metals.
The final step in the processing is etching of 20-pm-deep trenches in the
streets between chips to eliminate chipping and cracks during the chip separation
process. The fabricated HBT is shown in figure 4.1.4.
Chapter 4 Device Fabrication and Experimental Results
74
Figure 4.1.4 SEM photograph of a fabricated HBT. This device has one emitter
stripe and two base stripes with AE = 8 |im x 13 |Xm.
Chapter 4 Device Fabrication and Experimental Results
4 .2
E x p e r im e n t a l R e su l t s
4.2.1
Network Representation with S-parameters
75
A two-port network, such as a transistor, can be characterized by a number
of parameter sets, such as hybrid (or H-) parameters, impedance (or Z-) parameters
and admittance(or Y-) parameters which relate theinput terminal voltage
(V,) and
current (/,) tothe output terminal voltage (K2) and current (/2) [4-12].Depending
on the choice of independent and dependent variables, different parameters can be
defined. These parameters are determined from measurements at the terminals of
the two-port network, in such a way as to eliminate one of the independent
voltages or currents. These parameters are defined as follows:
//-parameters:
Vx= H uIx+H nV2 ,
(4.2.1)
/ 2= / / 21/, + / / 22K2 .
(4.2.2)
VJSSZ11/ I +Z12/ 2 ,
(4.2.3)
V2= Z 2,/ 1+ Z 22/ 2 .
(4.2.4)
Z-parameters:
K-parameters:
,
(4.2.5)
/ 2= r 2,v;+y22K2 .
(4.2.6)
Theoretically, any of these parameter sets can be used at any frequency;
however, at high frequencies, total voltage and current at the ports of the network
can not be easily measured, broadband short and open circuits are difficult to
achieve, and active devices (such as transistors) may not be stable when open or
short circuit terminated. To characterize the microwave performance, scattering
Chapter 4 Device Fabrication and Experimental Results
76
parameters (5-parameters), which relate the incident to the reflected (or scattered)
wave, are extensively used because they are easier to measure at high frequencies
than other kinds of parameters. A brief review of 5-parameter terms and definitions
is presented in this section.
A two-port network is shown in figure 4.2.1 with incident (a,, a2) and
reflected (bn b2) waves used in 5-parameter definitions. The a's and b's are related
to the normalized incident and reflected voltages by the following relations:
V +(x)
.
(4-2.7)
.
(4.2.8)
and
Here, F+(x) and V (x)representthe incident and reflectedvoltages atposition x
along thetransmission
line, and
Z0 is thecharacteristic impedance
of the
transmission line. The linear equations describing the two-port network are:
a j
\S U 5,2 A '
u . 522 _
i---toa
1__
N -
(4.2.9)
Physically, Iat\2 is the incident power on the input port, and \b,\2 is the reflected
power on the input port. The parameters Su , S12, S2J, S22, are called the 5parameters of the two-port network. The 5-parameters are seen to represent
reflection or transmission coefficients at the respective ports.
The advantage of using 5-parameters is clear from their definitions. They
are measured using a matched termination (i.e., making at = 0 or a2 = 0). For
example, to measure Su , the ratio b ja , is measured at the input port with the
Chapter 4 Device Fabrication and Experimental Results
77
output port properly terminated, that is, with a2 = 0. Terminating the output port
with an impedance equal to the characteristic impedance of the transmission line
produces a2 = 0, because a traveling wave incident on the load will be totally
absorbed and no energy will be returned to the output port.
Incident
Transmitted
a.
Two-Port Network
Reflected
S 22
Reflected
bi
Transmitted
Input Port
Incident
Output Port
Figure 4.2.1 Schematic of a two-port network showing the definition of the
5-parameters.
Although S-parameters are the parameters of choice at high frequencies
because of their ease of measurement, equivalent-circuit modeling is more difficult
with 5-parameters because 5-parameters can not immediately be interpreted as
circuit element values. Since the total voltages and currents are related to the
incident and reflected voltage waves, the other parameter sets can be derived from
Chapter 4 Device Fabrication and Experimental Results
78
the 5-parameters [4-12]. More intuitive device modeling and de-embedding
techniques are accomplished by converting the measured 5-parameters to Zparameters or K-parameters. The equivalent circuit modeling of AlGaAs/GaAs
HBTs is described in Chapter 5.
4.2.2 DC Characteristics
Typical DC electrical characteristics are as follows.
(1). Output characteristics Ic vs VCE: see figure 4.2.2.
The collector-emitter offset voltage VCE(offut) = 0.17 V results from a
combination of the different turn-on voltages for b-e and b-c junctions, different
junction areas, excess recombination currents in the collector space-charge region
(SCR), and resistive voltage drops between the external base contact and intrinsic
device [4-13]. The negative differential resistance observed at high collector current
and collector voltage is due to device heating [4-14]. The Early voltage obtainable
from this device is £ 800 V, resulting from high base doping.
(2). Gummel plot and DC current gain P vs Ic : see figure 4.2.3 and 4.2.4.
The collector and base current density Jc and JB versus emitter-base voltage
VBE on semi-log scale, which is known as Gummel plots, is shown in figure 4.2.3.
Due to strong and dominant recombination in the emitter-base space-charge region
(SCR) as described in section 2.2, the base current ideality factor is ranging from
1.4 to 2 for low current. The ideality factor in the Jc versus Kbe curve is almost
unity for low and high current densities, except at very high currents due to series
resistance.
The DC current gain p versus Ic characteristic is shown in figure 4.2.4. The
Chapter 4 Device Fabrication and Experimental Results
****** GRAPHICS PLOT ******
IC—VCE CHARACTERISTICS
40.00
4.000
/div
.OOOOL-i
.0000
VCE
5000/div
5.000
Figure 4.2.2 Common-emitter output characteristics of an HBT with AE =
pm2. The base current starts at 100 pA with 100 pA steps.
Chapter 4 Device Fabrication and Experimental Results
80
XXXXXX GRAPHICS PLOT XXXXXX
GUMMEL PLOT
JB
(
<JC
)
(
)
J 1E+04
1E+04
n = 1.01
decade
/div
decade
/div
n = 129
IE—04.
.8000
VE
.0700/div
f V)
IE—04
1.500
Figure 4.2.3 The Gummel plot of an HBT with AE = 18x33 |im-\
81
Chapter 4 Device Fabrication and Experimental Results
GRAPHICS PLOT ******
BETA VS JC
decade
/div
Slope = 0.16
Slope = 0.31
lE+OOl_
IE—01
JC
decade/dlv
1E+05
Figure 4.2.4 DC current gain P vs Ic of an HBT with AE = 18x33 jim2 at VCE= 3 V.
82
Chapter 4 Device Fabrication and Experimental Results
DC current gain P defined by IJ IB is ~ 50 at Jc = 10J A/cm2. It was found to
increase approximately as Jc016-031 in the useful Jc range of 10-10* A/cm2, as
illustrated in figure 4.2.3. The slope in P vs lc characteristics can be found to relate
to the ideality factor of the base-emitter heterojunction. For convenience, equation
(2.1.9) is again written as
p = -^ = —
.
/*
+ + /.
(4.2.10)
In equation (4.2.10), Ic is mainly composed of diffusion-driven injection of
electrons into the base region. For VBE> 3kT/q,
/c « e x p (£ jk ) .
(4.2.11)
The sum of Ip>Ir and It, i.e., / B, which is a " defect current" can be expressed as
/ Bo c e x p ( ^ - ) ,
D
v mkT
(4.2.12)
where m is the ideality factor of the base-emitter heterojunction, which has included
all the effects discussed in section 2.2. Substituting equations (4.2.11) and (4.2.12)
into (4.2.10), one can show
P = ^ - e x p [ ( l - - ) 2 M ~ ( / c ),'= .
1b
L
m kT ]
(4.2.13)
1 - — = 0.16-0.31 .
m
(4.2.14)
Hence,
The quantity obtained in this manner corresponds to ideality factor m = 1.19 ~
1.45, which is a value commonly reported due to significant SCR recombination.
(3). Breakdown characteristics : see figure 4.2.5.
Chapter 4 Device Fabrication and Experimental Results
83
(b)
Figure 4.2.5 The determination of (a) collector-base junction breakdown voltage,
BVcbo, a°d (b) collector-emitter junction breakdown voltage, BVCE0.
Chapter 4 Device Fabrication and Experimental Results
84
The most important breakdown voltage characteristics for HBTs depend on
the collector-base junction structure, which can be easily tailored to meet specific
applications via epitaxial design, i.e., collector doping and thickness. For this
particular epitaxial and layout design, the breakdown voltages are as follows.
• Collector-base junction breakdown voltage (with emitter open), BV cbo :
As in figure 4.2.5 (a) , BVcbo, governed by the collector doping and
thickness, is 19 V. Since the collector doping concentration is sufficiently low, the
junction breakdown is believed to result from the avalanche process. The hard
breakdown characteristic, seen in figure 4.2.5, is one indication of a good material
quality and fabrication process. Throughout the entire 3" wafer, no microplasma
breakdown was observed [4-15]. High BV cbo is desired for high device linearity and
high-power application. Thicker and lower doped collectors increase the
breakdown voltage at the cost of increased effective transit time and reduced
current density operation.
Under breakdown conditions, the collector thickness is fully punched
through. That is, the depletion layer reaches the n-n* interface (collectorsubcollector interface) prior to breakdown. For a one-sided abrupt junction (p+-n
base-collector junction), the punchthrough breakdown voltage is given by [4-16]
BVcbo_ W c ( 2
(4.2.16)
where
(4.2.17)
(4.2.18)
85
Chapter 4 Device Fabrication and Experimental Results
The parameters required for calculating the breakdown voltage are critical
breakdown field, Ec, collector doping, N ^ , collector thickness, Wc and basecollector built-in potential, q>cfl. For GaAs doped to 3xl016 cm*3, Ec is 5x10s V/cm
[4-17]. With Wc = 0.5 |xm and NAB =2xl019 cm*3, BV cbo is calculated to be 18.8 V,
which agrees very well with the experimental results.
• Collector-emitter junction breakdown voltage (with base open),5Vc£0 :
This voltage, BVCE0 = 12 V (figure 4.2.5 (b)), is governed by the collectorbase breakdown coupled with a feedback multiplication factor of the current gain
when measured as the base is driven by a current source. The measurement of
BVceo is performed as follows [4-18]. In common-base characteristics,
Ic = ^e '& o’ M „ + 1coo »
(4.2.15)
where a 0 is the common-base current gain, Mn is the collector multiplication factor
for electrons and l CB0 is open-emitter saturation current. The avalanche process
occurs when a 0Mn = 1. Since Ic » ICB0 , BVCEOis determined by
V CB
at I c = IE.
To quantitatively examine the uniformity of the collector-emitter breakdown
characteristics, one can define 8 as the ratio of area over which multiplication
occurs to the total junction area [4-19]. The collector-emitter breakdown voltage,
BVceo, is expressed as
BV
D \/
BV
ceo —
= _________________
„ ,
(l + |3-8)^
(4.2.19)
where n = 3.5 for GaAs [4-20]. Since DC current gain (3 = 12 at Ic = 50 (J.A, and
BV ceo = 12 V, BV cbo = 19 V, one obtains 8 = 33%, exhibiting that a fairly uniform
avalanche multiplication occurs in the collector junction area.
Chapter 4 Device Fabrication and Experimental Results
4.2.3
86
Microwave Results
All microwave characterizations in this work were performed using M/A-
COM's test facilities. Small-signal S-parameters were measured with a Cascade
Probe station and an HP 85IOC network analyzer between 1 to 26 GHz. A Cascade
MicroTech probe with a ground-signal-ground (coplanar waveguide configuration)
was used. To reduce the discontinuity between the device and the probes, the
device contact pads were designed as coplanar transmission lines. All devices were
measured in common-emitter (CE) configuration. The substrate was lapped to 10
mils with no via grounding. On-wafer probing was used with measurements
calibrated to the device probe pads by the SOLT (short-open-load-thru) technique
on an impedance standard substrate (ISS).
Figure 4.2.6 illustrates the measured data for an HBT with 8 jim-wide
emitter finger. Values for the maximum available gain/maximum stable gain
MAG/MSG and the current gain H2I are plotted as a function of frequency. The
maximum oscillation frequency,
is about 25 GHz. The current gain cutoff
frequency,/p measured under the same condition was estimated by extrapolation to
be 30 GHz, assuming a 6 dB/octave roll-off. The collector current dependence off T
and
at VCE = 3 V is plotted in figure 4.2.7. The effect of high Jc operation in
reducing the emitter-base junction charging time can be readily observed. The
variation of f T and
as a function of collector to emitter bias ^CE is seen in figure
4.2.8. The value o f/T rises at first due to the base-collector junction being biased
gradually out of the saturation region, and then falls as the collector transit time
Chapter 4 Device Fabrication and Experimental Results
87
30
20
Gain
(dB)
MAG
H21
-6dB/Oct
10
0
1
10
100
Frequency (GHz)
Figure 4.2.6 Maximum available gain/maximum stable gain (MAGIMSG) and
current gain (H21) for the HBT with AE = 8x13 fim2 at VCE= 3 V and Ic = 20 mA.
Chapter 4 Device Fabrication and Experimental Results
88
J c (A /cm 2)
101
102
103
104
105
80
60
—x— fmax
40
Frequency (GHz)
H20
10',-4
10*1
I C (A)
Figure 4.2.7 The collector current dependence of f T and
8x13 lam2 at VCE= 3 V.
for the HBT with AE =
Chapter 4 Device Fabrication and Experimental Results
x — fmax
Frequency (GHz)
30
—K
20
10
0
2
4
VCE W
Figure 4.2.8 The collector-emitter voltage dependence of f T and f max for the
with A e = 8x13 (im2 at Ic = 3 mA.
Chapter 4 Device Fabrication and Experimental Results
90
increases with the increasing base-collector depletion width. The maximum
oscillation frequency
on the other hand, which depends primarily on the device
lateral dimensions, is relatively invariant with Kce for V „ ^ 1 .2 V .
The scale-up capability of the device for power applications can be best
described by the following example. Figure 4.2.9 shows the MAG/MSG as a
function of frequency for two different size devices. The unit cell consists of two
one-emitter devices in parallel. When two devices were operated at the same
conditions (VCE and 7C), similar frequency response was obtained, suggesting
minimum parasitic elements were present. This is because as the device size is
increased, all resistive element values are reduced in proportion to the number of
unit cells, whereas all the capacitive element values increase by the same factor. The
RC charging time therefore remains constant, if the processing and the geometry of
scale-up devices introduces on new parasitics.
Chapter 4 Device Fabrication and Experimental Results
Gmax (dB)
20
91
—* — 2 unit cells with Vce=3V and Ic=5mA.
—x — 4 unit cells with Vce=3V and Ic=10mA.
15
10
5
20
40
60 80
Frequency (GHz)
Figure 4.2.9 MAG/MSG as a function of frequency for two different size devices.
Chapter 5
U n iq u e D e t e r m in a t io n
5.1
of
HBT's E q u iv a l e n t C i r c u i t P a r a m e t e r s
OVERVIEW
To further improve and optimize HBT device performance, it is important
to develop an accurate equivalent circuit model and parameter extraction scheme
based on experimental results and physical insight The conventional approach to
HBT equivalent circuit characterization is to vary the values of a relatively large
number of components to numerically optimize the fit of model-generated Sparameters to measured data. It has been found that such an approach can lead to
non-unique and/or non-physical solutions for component values, because of the
large number of parameters and the lack of constraints on their values. The final
result usually depends on the initial parameter values, the range of data used for
simulation, and the allowed range of parameter values during the optimization [51].
To overcome difficulties in determining unique solutions for the equivalent
circuit model parameters, many improved optimization algorithms have been
proposed [5-2 ~ 5-8], Using the simulated annealing (SA) algorithm, which is a
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
93
near global optimization method, Vai et al. have effectively avoided the local
minima entrapment problem of the optimization process [5-2]. This algorithm was
successfully applied to the optimization of an eight-element MODFET equivalent
circuit with satisfactory results. Bilbro et al. have also developed a tree annealing
(TA) algorithm, which is a tree-based search procedure, to improve the efficiency
of the SA algorithm as the number of unknowns increases [5-3]. Trew et al.
described a parameter extraction technique for HBTs that makes use of the emitterto-collector time delay to constrain the element values used in optimization [5-9].
Nonetheless, the optimization-based parameter extraction techniques are mostly
interactive, and generally require "expert guidance" in selecting the bounds on
parameter values [5-10, 5-11]. The process can be very time-consuming and
computationally intensive.
Costa et al. recently proposed a very elegant direct extraction method to
determine the HBT model parameters [5-12]. A similar approach has been
previously applied to advanced silicon bipolar junction transistors (BJTs) [5-13, 514]. In this technique, most of the parasitics are obtained from measurements of
test structures, and the intrinsic parameters are then de-embedded from the shells of
parasitics. This effectively eliminates any simulation/optimization process.
Unfortunately, a difficulty of this technique is that several test structures must be
fabricated on the same wafer as the device. Therefore, spatial variations stemming
from the material growth and fabrication process can easily invalidate the
underlying assumption that the test structures and actual devices are essentially
identical. Additionally, in this approach, all the parasitic elements have been
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
94
assumed to be bias-independent, which may not be valid for certain bias conditions
[5-15, 5-16].
In this section, a new parameter extraction technique, which was initiated by
M/A-COM's device development group, for HBTs is proposed. In this technique,
the determination of the equivalent circuit parameters is based on a novel low
frequency algorithm, where no special test structures are used. The measurements
used to obtain the equivalent circuit element values are the same as those for
characterizing device f T or
through a single 5-parameter sweep measurement
Using this approach, for the first time, all parasitic resistances and all intrinsic
parameters can be directly extracted from the measured 5-parameters without the
need of special test structures. Computer optimization is minimized and is mainly
used to properly distribute the intrinsic and extrinsic base resistances and collector
capacitances to account for the high-frequency characteristics. In addition, when
incoiparated into an automated RF test routine, this technique can be applied to all
devices on the same wafer, so process variations can be properly monitored in a
real-time fashion.
5.2
T echnical Approach
5.2.1
Model Determination
The intrinsic high-frequency equivalent network model has been discussed
in section 2.3. Additional circuit elements are appropriately added to account for
the distributed capacitances and inductances of the bonding pads and interconnects.
This completes our overall lumped-element small-signal equivalent circuit
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
95
representation of the HBT, which is shown in figure 5.2.1. This model consists of
an extrinsic part containing twelve parasitic elements, and the intrinsic device,
containing five elements characterized by six parameters (gm = gmo‘e~jm). The
parasitics associated with the probe pads and the device interconnect metals are
represented by shunt capacitances (Cbcp, Cbep, and Ccep) and series inductances ( Lb,
Le, Lc). The base-contact impedance is modeled by a parallel RC network (Rbcon and
C ..J [5-12]. The base contact resistance, Rbcon, and the combined intrinsic and
extrinsic base resistance, Rb, give the total base series resistance, Ra. The
distributed base-collector capacitance model has been described in section 2.3.3,
where Cc is the effective intrinsic capacitance and
is the effective extrinsic
capacitance. Rtt and Rcc are the emitter series resistance and the collector series
resistance, respectively. The intrinsic hybrid-7U network consists the small-signal
input resistance, rK, the collector output resistance, r0, the complex intrinsic
transconductance, gm, and the sum of the base-emitter depletion capacitance and the
base charging capacitance, CK.
5.2.2
Extraction Algorithm
The approach used in this work is, first, to reduce the aforementioned
overall high frequency model to a low frequency equivalent circuit, as shown in
figure 5.2.2, where R ^ and Rb,
and Cc have been lumped together to give R ^
and C„,
respectively. This simplification can effectively remove the effects of the
r
pad and interconnect parasitics. It also greatly simplifies the analysis of the
equivalent circuit. This step is achieved by taking sufficient low-frequency
measurement data and analyzing low-frequency data only. Secondly, by examining
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
- m
-
Smoe x p ( .jm )
E
Figure 5.2.1 Overall lumped-element small-signal equivalent circuit model.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
Intrinsic
r
Rbb
b
|
-----------VM — r
c.
E
Figure 5.2.2 Low-frequency hybrid-7t equivalent circuit model for HBTs.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
98
the low frequency network parameters, the parasitic resistances and the intrinsic
elements can be accurately extracted. The detailed methods used to extract the
resistances and intrinsic elements will be explained in section 5.2.3 and 5.2.4. The
procedure for this extraction is illustrated in figure 5.2.3. If the parasitic resistances,
Ree, R^, Rcc, can be determined accurately, the intrinsic y-parameters of the lowfrequency hybrid-7t equivalent circuit model can be found by the following simple
matrix manipulations:
(1). Convert the measured 5-parameters to Z-parameters.
(2). Subtract the parasitic resistances, Ree, /?M, Rcc.
(3). Convert the resultant Z-parameters to the intrinsic y-parameters.
By evaluating the admittance blocks, as shown in figure 5.2.4, each intrinsic
element in the hybrid-7t equivalent circuit model can be calculated. Finally, the
extracted parameters are then fixed and brought back to the overall equivalent
circuit model and the remaining parameters are carefully optimized to account for
the high frequency characteristics.
Low-frequency simplification of the equivalent circuit is the crucial concept
used in this technique. This concept has been reported previously to simplify the
intrinsic element representations of the equivalent circuit for GaAs MESFETs [517] and to extract the base and emitter resistances of the HBTs [5-18], However,
to the best of my knowledge, this is the first time that the low-frequency approach
leads to the extraction of the intrinsic elements and also the determination of the
entire equivalent circuit model parameters for the AlGaAs/GaAs HBTs.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
R bb
r
B -----
“i
Intrinsic
Elements
Bee
“WA/
99
c
(1) Convert [5] to [Z].
(2)
^12
\Z]de^fnbed
(3) Convert
^22 ~ K c ~ R c c .
to [Y] intrinsic
Figure 5.2.3 The extraction procedure for obtaining the intrinsic y-parameters of
the low-frequency hybrid-7C equivalent circuit model.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
-Y,12
100
Intrinsic
B
_ J
E
Figure 5.2.4 The corresponding admittance blocks of the intrinsic hybrid-jc
equivalent circuit model.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
101
5.2.2.1 Extraction o f the Resistive Parasitic Components
As described in the above section, the extraction of the parasitic resistances
is one of the key steps in this algorithm. These resistances were mostly obtained in
Si bipolar junction transistors (BJTs) by DC methods. A popular method, known as
the open-collector method, to determine emitter series resistance Rtt was proposed
by Giacoletto [5-19]. This method is based on measuring collector-emitter
saturation voltage for different base current when the collector is open-circuited..
Similarly, measurement of floating emitter-collector saturation voltages as a
function of forward-biased base current would provide evaluation of collector
series resistance Rcc. However, this method was found to be inaccurate due to the
current-dependency of the common-base reverse current gain [5-20]. A simple
method to determine the base series resistance was outined by Logan [5-21], in
which the base-emitter voltage was measured as a function of collector current. The
deviation from an exponential transfer function is attributed to an (JgR^) voltage
drop , where IB is the base current and R ^ the base series resistance. Similarly, this
method suffers lack of accuracy, especially, for HBTs, typical I-V curves are very
nonideal due to strong surface recombination effect (see section 2.2).
In this section, a simple ac method is described to extract these parasitic
resistances. The delightful properties of AlGaAs/GaAs HBTs such as very large
output resistance and small base-collector capacitance have made the analysis of the
equivalent circuit much simpler than Si BJTs. It should be pointed out that a similar
approach of extracting the emitter series resistance was proposed by Das [5-22].
Assessment of the accuracy and the validity of the extracted paramters is given in
section 5.4.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
102
(i) Extraction o f the Emitter Series Resistance, Ree
The low frequency equivalent circuit in figure 5.2.2 can be further simplified
to the circuit as shown in figure 5.2.5 by absorbing the effect of Ree [5-23]. This
modified equivalent circuit is obtained under the assumption that Ree and Rcc are
small resistances compared to r0, which is easily justified for HBTs due to the large
Early voltage, resulting from the heavy base doping. The corresponding intrinsic
parameters are related to the original elements by the following expressions [5-24]:
•
and
(5-2'»
C '=% ,
A
(5.2.2)
< = rn-A .
(5-2.3)
K = r0-& ,
(5.2.4)
where A = 1+ g„Jiet. By analyzing the modified low frequency equivalent circuit,
one obtains
IK 1= ------------------------------------------------In calculating equation (5.2.5), it was assumed that C'Kis much greater than
(5 2 5)
and
the Early voltage is so large that the effect of r’0 can be neglected. These conditions
are also justified in our devices. For r' » (Rbb +/?„), and at low frequency, where
CO« [C'n(Rbb+ Ree)]~l, equation (5.2.5) can be further reduced to
ly« L » ° a . = A
, . &mo
f “ . **ee
o •
<5-2-6>
Equation (5.2.6) describes the relationship between the emitter series resistance,
R„, and the extrinsic transconductance, g'^. It means that the intrinsic
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
Rbb
qi
103
Ra
B
■ee
E
Figure 5.2.5 Modified low-frequency equivalent circuit model by absorbing the
effect of R„.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
transconductance, g ^ , is reduced by a factor of
104
due to the presence of
the emitter series resistance and this reduced transconductance, i.e., extrinsic
transconductance, can be directly measured by obtaining (IK2/I) at low frequencies.
Since
= Ic/(nVT), where n is the ideality factor, and VT is the thermal voltage,
kT/q, equation (5.2.6) can now be expressed as
j j y ------- 7 ^ + * , . \ Hitowfreq.
Hence, by plotting
QY21\lmv freq) ' 1
(5.2.7)
lC
versus l//c, one can determine the emitter series
resistance as the intercept point to zero l//c, and (nVT) as the slope of the plot.
Figure 5.2.6 shows such a plot.
(ii) Extraction o f the Base Series Resistance,
Again, by analyzing the modified equivalent circuit model, one can obtain
the following expression
Y2, =
r— ,
21 z ; + R bb+R„
(5.2.8)
and
-f - = Z'r +Rbb+R „,
Yn
(5.2.9)
where
Z ' = - — . ” , ■.
' 1+ yco r'CfK
(5.2.10)
Solving Ry, from the above equations, we have
i
Re \hi
.V
Im ^ ] .
(5.2.11)
■
R** = Re[ i ] - R~ - Im
The base series resistance, /?M, can be calculated from equation (5.2.11) once Ree is
known. The extraction of R ^ is given in figure 5.2.7.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
105
10
8
■
Least S quare Fitting
M easured Data
(suiqo)
6
l‘ZAl/t
4
2
Intercept = R
0
0
= 0.96 ohm s
0.1
0.2
(Collector Current lc)’1 (mA)’1
Figure 5.2.6 The extraction of the emitter series resistance, Ret.
0.3
Resistance (Ohms)
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
106
30
e— 9
0.1
0.2
0.3
0.4
Frequency (GHz)
Figure 5.2.7 The extraction of the base series resistance, R^.
0.5
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
107
(iii) Extraction o f the Collector Series Resistance, Rcc
The collector series resistance, Rcc, is extracted with large current forced
into both the base and the collector of the HBTs. Under heavy forward bias
condition, Rcc can be determined as
Rcc —RejZ^
ZI2] .
(5.2.12)
The result of this extraction is shown in figure 5.2.8.
5.2.2.2 Extraction o f the Intrinsic Elements
As mentioned earlier, once the resistive parasitic element values are
calculated, the intrinsic parameters can be obtained by de-embedding those parasitic
resistances. Since the y-parameters of the intrinsic 7t-network (see figure 5.2.4) can
be expressed as
y„=-+yci)(c,+cM
),
(5.2.13)
^21 = 8m~
(5.2.14)
^IT
K
and
»
Yi2 = ~jtaC^ ,
(5.2.15)
Y22 — h ycoq,,
r0
(5.2.16)
The intrinsic element values can now be computed as
r"
1
Re[Ku + K12] ’
(5.2.17)
lm[r„+r„]
*“
.
>“
’
- M y .,]
^
(5.2.18)
(5.2.19)
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
108
10
Resistance (Ohms)
8
6
4
2
010.1
0.2
0.3
0.4
Frequency (GHz)
Figure 5.2.8 The extraction of the collector series resistance, Rcc.
0.5
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
109
(5.2.20)
x
and
-A n d Y 2l- Y n ]
CO
Re[r22+yl;] ’
(5.2.21)
(5.2.22)
The results of the extraction of rK, both CK and C^, and gmo as a function of
frequency are given in figure 5.2.9, 5.2.10, and 5.2.11 respectively. The element
values independent of the frequency indicate the validity of the model and the
extraction algorithm.
5.2.2.3 Determination o f the Overall Equivalent Circuit Parameters
So far, the intrinsic element values and the resistive parasitic parameters
have been determined without any computer optimization. The remaining elements,
the parasitic capacitances and inductances, can be found very reliably from
conventional S-parameter fitting using commercial computer-aided microwave
simulation and optimization program, such as EEsof Touchstone. To accurately
model the high frequency response, however, the intrinsic and extrinsic base
resistances and collector capacitances have to be distributed properly since they
were lumped together for the low frequency analysis. This is achieved by applying
the optimization process using the additional two restrictions, namely,
Rbb — R b
and
The values of
^beon
»
Cjj —Cc + Ci
and
(5.2.23)
(5.2.24)
have been previously determined by the low-frequency
extraction algorithm. Additionally, the expected value of Cc and
can be
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
110
300
Resistance (Ohms)
250
200
150
0.2
0.3
0.4
Frequency (GHz)
Figure 5.2.9 The extraction of rKas a function of frequency.
0.5
Chapter 5 Unique Determination of HBT's Equivalent Circuit Parameters
111
5x1O'13
5>X1U
B -— OC
Q
©(f
Capacitance (F)
4x10
12
3x10"
4x10‘’3
| - - O - - B ' ' S ' " O' ~ 0 - - B - - G - £ I - - B - - Q - G - - B - - B - - G - B - - B - - G - a - - B - H
3x1 O’13
D—Q—
I— 0 -
2x10"
2x1 O’13
1x10"
IxlO ''3
0
0.1
0.2
0.3
0.4
0.5
Frequency (GHz)
Figure 5.2.10 The extraction of C„ and
as a function of frequency.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
112
Transconductance (S)
0.3
0.2
0.1
0.1
0.2
0.3
0.4
Frequency (GHz)
Figure 5.2.11 The extraction of g ^ as a function of frequency.
0.5
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
113
estimated from the geometric dimensions as outlined in section 2.3.3. Together
with the facts that Rb has strong effect on Sn and Cc has dominant effect on SI2 and
S22, fast and unique determination of the overall equivalent circuit for HBTs can be
easily achieved. Finally, the algorithm used to determine the equivalent circuit
parameters for HBTs is summarized in figure 5.2.12.
5.3
M easurement and Results
The 5-parameters of the HBTs were measured on-wafer with a Cascade
probe station and an HP 85 IOC automatic network analyzer between 45 MHz and
26 GHz. The device is fed by coplanar transmission line and in common-emitter
(CE) configuration. With SOLT (short-open-load-thru) calibration standards
provided by Cascade Microtech on an impedance standard substrate (ISS), the
reference plane was calibrated up to the probe tips. Since this technique requires
sufficient low frequency data, as discussed in the previous section, the 'Frequency
Segment' feature of the HP 85 IOC was used so that the data used for extraction of
the parameters and for device performance evaluation could be acquired in the
same pass. Consequently, this saves considerable time.
To demonstrate the importance of using the low-frequency approach, figure
5.3.1 illustrates
and CKas a function of frequency up to 10 GHz. Clearly, for
frequencies higher than 0.6 GHz, both parameters start to show strong frequency
dependence. This technique has been applied to devices with different geometries
(emitter width of 8- and 3-pm) and bias conditions (up to Jc ~ 2xl04 A/cm2). Table
5.3.1 shows results for one device biased at two collector currents. This device has
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
S-parameter Measurements
See section 4.2.1 and 4.2.3
Low-Frequency
Extraction
114
* On-wafer probing from
45MHz-26GHz.
Extraction of the
Parasitic Resistances
See section 5.2.2.1
* Convert measured S-paramcters
to Y- and Z- parameters.
* Obtain Rec, Rbb and Rcc by
analyzing low-frequency
equivalent circuit.
Extraction of the
Intrinsic Elements
See section 5.2.2.2
* Convert measured S-paramelers
to Z- parameters.
* De-cmbed Rce, Rbb and Rcc.
* Convert de-embcdcd Z-parameters
to Y-parametcrs.
* Extract r^ ,
.x
and r0 by analyzing the intrinsic
pi-network.
"typically
Performed at
0.1-0.5 GHz
* Fix the parameters obtained in
low-frequency extraction.
High-Frequency
S-parameters
Fitting
Performed at
0.1-26 GHz
Determination of the
Overall Model Parameters
See section 5.2.2.3
* Apply the constraints:
Rbb = Rb + Rbcon
= Cc + Cbc
* Use optimization routine to fit
the measured data.
* Determine the remaining parameters:
Le, Lb, Lc, Ccep, Cbcp, Cbep and Cbcon.
Figure 5.2.12 The flow diagram of the algorithm used to determine the equivalent
circuit parameters for HBTs.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
□ LK
*
115
Cu
5. Ob-12
‘Ob-13
— E
1 . 0.57 GHz
f
a5)
2. 5e-12
/
—^
A
i
« =
0 . 000
——.
3 ^
.
-5b-13
— i
.0 .
000
Figure 5.3.1 Extraction of CMand CKas a function of frequency up to 10 GHz.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
116
T able 5.3.1
E q u iv a le n t C irc u it P a ra m e te rs , Quad-8x13 |xm2-emitter HBT at VCE= 3V.
Element
8mo (S)
Q (p F )
C«)
cem
cbc(fF)
Rb(Sl)
r.(Q)
x (psec)
(^ )
(PF)
* cc (Q)
(Q)
Che (fF)
C * (fF)
(fF)
Lb (pH)
Le (pH)
4 (pH)
7r = 4mA
0.146
2.4
183.3
132
178
10.45
100K
4.4
5.17
5.65
2.22
0.96
12
80
28
40
4
28
Ir = 8 mA
0.297
3.46
107.75
133
178
9.16
100K
3.73
5.17
5.65
2.22
0.96
12
80
28
40
4
28
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
117
four emitter fingers each with an emitter area of 8 x 13 pm2. Figure 5.3.2 compares
the measured 5-parameters with the model-generated 5-parameters of this device.
Throughout the entire 0.045-26 GHz frequency range, the modeled 5-parameters
agree very well with experimental data. The measured and modeled current gain
(H21) and maximum stable/maximum available gains (MSGIMAG) are shown in
figure 5.3.3. To quantify this modeling, the normalized error is computed by
_
1 " 5 ijmeatured ~ S y mod Wed
- ^ 1 I—
f i m - 1—
\l0s ^
ijmeasured
’
(53-1)
where n is the total number of the frequencies used in the calculation. For 27
discrete frequencies from 0.045 to 26 GHz, the errors are 3%, 2.2%, 7% and 6.5%
for 5,,, S2l, 5;2 and S22, respectively. Note that only the capacitive and inductive
parasitic parameters and the distribution of R ^ and
have been determined by
fitting data at high frequencies, while all other parameters were obtained from low
frequency extraction. The excellent fit to the measured data again validates the
proposed equivalent circuit model and the extraction algorithm.
5.4
V erification of the E xtracted Parameters
5.4. 1 Calculated Small-Signal Parameters
Using the analysis given in section 2.3, all small-signal parameters in the
lumped-element equivalent circuit model can be calculated based on the physical
structures of the devices. In this section, the calculated small-signal parameters will
be compared with the extracted parameters attained from the algorithm described in
previous section.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
118
+ M easured S l l
a M easured 522
lodel.
[45.0 KHz
16.0 GHz
+ M easured 512
a M easured 521
521 /
lodel
Figure 5.3.2 Comparison between the measured and model-generated Sparameters.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
„
mi
MODELED
119
mi
MEASURED
(dB)
10.00
-
10.00
0.010
1.000
FREQ-GHZ
100.0
(a)
MSGIMAG
MODELED
M SG/M AG
MEASURED
35.00
(dB)
10.00
-
10.00
10.010
1.000
100.0
(b)
Figure 5.3.3 Comparison between the measured and modeled (a) current gain (H2l)
and (b) maximum stable/maximum available gains (MSGIMAG).
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
120
The epitaxial structure parameters used in this model calculation are shown
in table 5.4.1. The device layout is shown in figure 5.4.1. The corresponding
dimensions are given in table 5.4.2.
The detailed descriptions of each layer have been provided in section 4.1.1.
The only difference in this epitaxial profile is that the base doping is increased to 3x
1079 cm7 and
1000 A
base thickness is reduced to
for better high-frequency
response. Table 5.4.3 shows the extracted and calculated small-signal parameters.
T a b l e 5.4.1
M B E W a f e r E p it a x ia l S t r u c t u r e U s e d
Layer
/i+-GaAs cap
Graded AlGaAs emitter
N-AlGaAs emitter
Graded AlGaAs emitter
A1 composition
in
M o d e l C a l c u l a t io n
Doping (cm 3)
Thickness (A)
0
5 x l 0 18
750
0 .3 -0
5 x l 0 17
300
0.3
5 x l 0 17
1200
0 -0 .3
5 x l 0 17
300
p +-GaAs base
0
3 x l 0 19
1000
/i-GaAs collector
/i+-GaAs sub-collector
0
3 x l 0 16
5000
0
5 x l 0 18
6000
S.I. GaAs substrate
0
-
-
Chapter 5 Unique Determination of HBT's Equivalent Circuit Parameters
Lm
Ohmic Contact Metal
Lb
l»
Mesa Area
Figure 5.4.1 The device layout used in the model parameter
calculation.
T a b l e 5.4.2
T h e C o r r e s p o n d in g L a y o u t D im e n s io n s U s e d
Descriptions
Emitter Mesa Width SE
Emitter Metal Length LME
Emitter Mesa Length LE
Base Contact Width SB
Base Mesa Length LB
Emitter-Base Spacing SEB
Base-Collector Spacing SBC
Collector Contact Width Sc
Collector Contact Length Lr
in
M o d e l C a l c u l a t io n
Dimensions (pm)
3
10
12
4
16
0.25
2
6
16
121
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
122
T a b l e 5.4.3
T h e E x tr a c te d a n d C a lc u la te d S m a ll-S ig n a l P a r a m e te r s
VCE= 3 V, VBE= 1.46 V, Ic = 3.6 mA (Jc = 2xl0< A/cm2)
Model Parameters
R « (O )
Extracted
6.58
Kc
R-eb
Calculated
5.64
5
0.64
Equations Used
(2.3.13)
90
92.33
12.98
11.35
68
(2.3.17)
5.92
7.8
1.4
5.1
1.3
Similar to
(2.3.17)
8 m o ( S)
0.136
0.139
(2.3.7)
cn(pF)
0.85
0.79
(2.3.6) and (2.3.14)
223.21
221.62
(2.3.10)
r.(Q)
280K
220K
(2.3.11)
Ce (fP)
21
18.4
11
0.92
20.2
(2.3.24)
Cfc(fF)
11
13.7
(2.3.25)
x (psec)
2.8
3.1
(2.3.12)
R bbW
R bi
R bx
R bc
R cc
(O)
R ci
R cx
D
^ccon
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
123
A few comments about table 5.4.3 should be made. First of all, The
parasitic resistances and capacitances analyzed in section 2.3.3 assume a oneemitter, two-base and two-collector device geometry. However, the geometry of
the device used in the calculation is one-emitter, one-base and one-collector.
Therefore, the equations used to calculate these parameters have to be modified
slightly. For example, the base series resistance is doubled because there is only one
base contact in this device. Similarly, Cex and Ccc would be one-half of the values
using equations (2.3.22) and (2.3.23), respectively. Secondly, in the calculation of
intrinsic transconductance gmo, an ideality factor n of unity was used due to
diffusion-driven injection of electrons into the base. Thirdly, the values of sheet
resistance and specific contact resistivity for emitter, base and collector contacts
and series resistance calculations were determined from the measurements on
process control monitoring (PCM) structures such as cross bridge and TLM (see
section 2.3.3) patterns. Fourthly, the calculations of parasitic resistances and
capacitances have been broken down into the individual components corresponding
to the physical origins of the parasitics. This exercise is of great importance as it
provides a direct link between the physical structures of the device and the device
equivalent circuit elements. The dominant parasitics of each element from the
device layout can thus be identified. For instance, the emitter and base series
resistances are mainly determined by the contact resistances in this device. A lower
resistivity ohmic contact for base and emitter can therefore further reduce these two
parasitic resistances.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
124
Figure 5.4.2 compares the measured, calculated and modeled maximum
stable/maximum available gains (MSG/MAG). The excellent agreement between
these data again provides a strong support of the validity of the proposed
equivalent circuit model and the extraction algorithm.
5.4.2 Scaling o f the Model Parameters
To demonstrate the usefulness of this parameter extraction technique, the
scaling of the extracted equivalent circuit parameters is performed in this section.
The scaling of the model parameters is a rather important practice because it avoids
the need of building a cumbersome library of devices with different sizes and,
furthermore, it validates the accuracy of the proposed equivalent circuit model and
the extracted model parameters. The scaling analysis employed in this section has
assumed that the emitter width SE (SE = 3 |xm) of all devices is constant. Devices
used in this section have two-emitter, three-base and two-collector contacts with
varying emitter length LE of 10, 15 and 20 |i.m. Additionally, all devices are
operated at Jc = 1x10* A/cm2and VCE= 3 V.
5.4.2.1 Scaling o f the Parasitic Resistances
To perform the scaling of the emitter series resistance, one can re-write
equation (2.3.13)
R ee= R ' c + R 'b
(5.4.1)
_SE
qNDE^nE^E .
where WE is the quasi-neutral emitter width; NDE is the doping concentration in the
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
125
40
Calculated Using the Analysis Presented In Section 2.3
M easured
Modeled Using the Proposed Param eter Extraction Technique
MSG/MAG (dB)
30
0.1
10
1
100
Frequency (GHz)
Figure 5.4.2 Comparison of the measured, calculated and modeled maximum
stable/maximum available gains (MSGIMAG).
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
126
emitter; pi^ is the electron mobility in the emitter; and pec is the specific contact
resistance of the emitter contact. From equation (5.4.1), it can be easily seen that
the emitter series resistance Ree is inversely proportional to LE. Figure 5.4.3
illustrates the fit of the extracted emitter series resistance to LE. The error bars
indicates the variations of the extracted
C€
over a 3" wafer. Excellent fit of the
emitter series resistance to LE‘ proves that R„ is correctly described in the
equivalent circuit. Similar results were obtained for R ^ and Rcc. That is, given the
same emitter width, Rbb and Rcc vary inversely with the emitter length. Figure 5.4.4
and 5.4.5 represent the fits for R and Rcc, respectively.
5.4.2.2 Scaling o f the Parasitic Capacitances
The scaling of the intrinsic and extrinsic base-collector capacitances can be
analyzed in a similar manner. For a simple parallel plate model of the junction
capacitance, the base-collector capacitance is given by
c = Sl A c. oc l
,
( 5.4 .2)
**
where xdc is the base-collector depletion layer width, Ac is the base-collector
junction area and Lg is the base mesa length. Therefore, for a given base and emitter
width, the intrinsic and extrinsic base-collector capacitances are expected to scale
linearly with the base length LB. The fit of the intrinsic base-collector capacitance is
shown in figure 5.4.6. Similar result can be obtained for the extrinsic base-collector
capacitance, which is plotted in figure 5.4.7. It should be pointed out that the
extrapolation of LB - 0 corresponding to a non-zero capacitance for both
and Cc
is presumably due to the fringing capacitance and the parasitics which do not scale
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
127
5
Fitting
Extracted Emitter R esistance
Resistance (Ohms)
4
3
2
1
0
0
0.05
0.10
0.15
0.20
(Emitter Length LE)'1 (urn)'1
Figure 5.4.3 The fit of the extracted emitter series resistance to emitter length LE.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
128
40
Fitting
B ase S eries R esistance
Resistance (Ohms)
30
20
Rul=274.3/L,
10
0
0
0.05
0.10
0.15
(Emitter Length LE)'1 (urn)'1
Figure 5.4.4 The fit of the extracted base series resistance to emitter length LE.
0.20
Chapter 5 Unique Determination of HBT's Equivalent Circuit Parameters
129
5
Fitting
Collector S eries R esistance
Resistance (Ohms)
4
3
2
R C O =42.96/LI
1
0
0
0.05
0.10
0.15
(Emitter Length L£)'1 (jim)’1
Figure 5.4.5 The fit of the extracted collector series resistance to emitter length LE.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
130
100
Intrinsic Base-Collector Capacitance
Fitting
Capacitance (fF)
80
C = 1.91 x(Lb)+10.0
60
10
15
20
25
Base Length (pm)
Figure 5.4.6 The fit of the intrinsic base-collector capacitance to base length LB.
30
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
131
Fitting
Extrinsic Base-Collector C apacitance
Capacitance (fF)
50
10
15
20
25
B ase Length (pm)
Figure 5.4.7 The fit of the extrinsic base-collector capacitance to base length LB.
30
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
132
with the base length.
5.4.2.3 Scaling o f the Intrinsic Elements
(i). Intrinsic Transconductance
The scaling of g ^ can be demonstrated by re-examining equation (2.3.7)
_
_
d lc
_
Q fc
_
t
rc
a
'i s
(5 A 3 )
For given collector current density Jc and emitter width SE, g ^ should vary linearly
with the emitter length LE. The fitting of g ^ is given in figure 5.4.8.
(ii). Input Resistance rK
Employing the charge control concept, the small-signal input resistance for
the base-emitter junction rn can be represented by
.. _ dVflE _ Pa
(5.4.4)
'W
8>nmo
Since the incremental common-emitter current gain
-1
P = ^- =
Pac a/B dlc
Ir
the input resistance rKtakes the following form:
r ,° 'A ( I c )‘ = A (Jc -SE-Ll:)B ,
(5.4.6)
where A = m(nkT)/q and B = -m 1. Equation (5.4.6) demonstrates the scaling rule
for the input resistance rK. Given that the collector current density Jc and emitter
width SE are kept constant, rKshould vary with the emitter length LE to the power
of (-m 0 as long as T doesn't change. The fitting of rKis performed in figure 5.4.9.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
0.75
Fitting
Transconductance
Transconductance (S)
0.60
0.45
0.30
0.15
20
10
Emitter Length LE (|im)
Figure 5.4.8 The fitting of the intrinsic transconductance g ^ .
133
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
120
Fitting
Input R esistance
Resistance (Ohms)
100
80
60
r=1101.5*(LE)-1
10
20
Emitter Length LE (pm)
Figure 5.4.9 The fitting of the small-signal input resistance rK.
134
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
135
A tJ c = lxlO4 A/cm2, the DC current gain is essentially independent of the collector
current as shown in figure 4.2.3. Therefore, m is approaching unity as depicted in
figure 5.4.9.
(iii). Input Capacitance CK
In the active forward mode operation of an HBT, the small-signal input
capacitance CKcan be expressed as
CK= Cjt +Cbe ,
(5.4.7)
where Cje is the emitter-base junction capacitance and Cbt is the effective base
charging capacitance (refer to equation (2.3.6)). Equation (5.4.7) can be modified
to derive the scaling factor, i.e.,
^
£ *Ap
ic “
—
^ S mo
i
T
tc —L e
I J C ’
-------------- 1---------™
Xde
nkT
TI
^
'C
(5.4.8)
where AE is the emitter-base junction area, xde is the emitter-base depletion region
width and v„ is the intrinsic emitter-to-collector transit time. It is clearly seen in
equation (5.4.8) that the small-signal input capacitance CK scales linearly with the
emitter length LE when Jc and SE are kept constant. The fitting of CK is plotted in
figure 5.4.10. Similarly, the small capacitance as emitter length approaches zero is
presumably due to the fringing capacitance and the parasitics which do not scale
with the emitter length.
Chapter 5 Unique Determination of HBTs Equivalent Circuit Parameters
3.5
Fitting
Input C apacitance
Capacitance (pF)
3.0
2.5
2.0
20
10
Emitter Length LE (pm)
Figure 5.4.10 The fitting of the small-signal input capacitance Cr
136
Chapter 5 Unique Determination of HBT's Equivalent Circuit Parameters
5 .5
137
SUMMARY
In summary, a new parameter extraction technique for HBTs has been
developed. Utilizing a novel low frequency extraction algorithm to extract the
intrinsic elements and the resistive parasitic components, this technique is much
more reliable and efficient than the conventional approach. This extraction
technique has been applied and verified to give an excellent fit to the measured
data. The extracted parameters have also been carefully shown to be consistent
with calculations based on the physical structure of the device. To exploit the
usefulness of the proposed technique, the scaling of the model parameters is
performed. The successful demonstration of the scalability of the element values
further validates the accuracy of the model.
The novel features of this technique are summarized below.
(i).
No special test structures or measurements are required. The
measurements used to obtain the equivalent circuit element values are
the same as those for characterizing device f T or f max. This technique,
however, does require the acquisition of sufficient low-frequency data,
which can be easily achieved using the 'Frequency Segment' feature of
the HP 8 5 IOC automatic network analyzer.
(ii). The low-frequency extraction part of this technique can be readily
programmed for incorporation into an automated RF test routine. The
extraction of the intrinsic elements and resistive components is
consistent and repeatable and thus can be used in the statistical process
Chapter 5 Unique Determination of HBT's Equivalent Circuit Parameters
138
control. This parameter extraction technique is therefore a very
powerful tool for monitoring the fabrication process.
(iii). Excellent agreement of the measured and extracted parameters using the
device-physics-based equivalent circuit provides great confidence for
circuit designers when extrapolating to higher frequencies.
(iv). Computer optimization is minimized and is mainly used to properly
distribute the intrinsic and extrinsic base resistances and collector
capacitances. As a result, unique and fast determination of the
equivalent circuit parameters can be ensured as compared to
conventional approaches.
C h a p ter 6
C o n c l u s io n s
6.1
R esea rch S u m m a r y
The rapid advancement of heterojunction bipolar transistor (HBT)
technology in recent years has made accurate and reliable device modeling
indispensable. However, the approach to HBT equivalent circuit characterization is
still based on the simulation and optimization loop, despite the uncertainty and non­
uniqueness in determining the model parameters. To unambiguously determine the
large number of elements of HBT equivalent circuit, one should directly obtain as
many of the element values as possible before resorting to the computer simulation
and optimization process.
In this thesis work, a new parameter extraction technique for HBTs is
presented. Employing a novel low frequency extraction algorithm, fast and unique
determination of the equivalent circuit parameters is realized. The contributions of
this work to the science of HBT devices can be summarized as follows. First, it will
provide essential information on device design and structure optimization. Second,
the quantitatively accurate equivalent circuit, representing the device behavior over
Chapter 6 Conclusions
140
a specified frequency range, will be reliable and readily available for circuit design.
Third, it will serve as a guideline to improve the device fabrication processes by
indicating the factors that limit the device performance and speed potential. It will
also provide an effective method for monitoring the fabrication process.
The validity of this technique has been carefully confirmed by many
methods. In the course of this exercise, several important applications of this
technique were revealed. It was found that the equivalent circuit modeling can be
used as a very efficient diagnostic tool for improving device design. Furthermore,
certain model elements were shown to exhibit stronger correlation than others with
device high-frequency performance. Consequently, real-time monitoring of these
parameters can establish invaluable information for statistical process control. The
demonstration of the scalability of this model is extremely important. It extends the
practical application of this modeling technique. New devices can be designed
based on incremental changes in the dimensions of the unit cell, which will
effectively eliminate the need for the cumbersome and limited standard library
structures.
Various critical design variables have been identified and their influence on
device performance was discussed. The design considerations for the epitaxial layer
structure and the device layout were presented.
A self-aligned AlGaAs/GaAs HBT fabrication process was developed in this
work. With emitter area of 8x13 pm2, base doping of 2xl0/9 cm J and base
thickness of 1500 A, the device has demonstrated DC current gain of 50, f T and f max
of 30 and 25 GHz, respectively. These are impressive results considering that a
relaxed geometry was used, no sophisticated processing schemes were included and
Chapter 6 Conclusions
141
a conventional and simplified device structure was employed. Using the equivalent
circuit modeling technique described in this work, it is believed that greatly
improved high-frequency response is realizable.
6.2
Future W ork
Based on the results of this work, several areas of improvement are worth
further investigation.
(i) Equivalent Circuit Modeling
A. Analyze the Bias Dependence of the Element Values
For nonlinear device modeling, the voltage and/or current dependence of
the model parameters is required. The dynamic variation of the element values has
usually been assumed to be the same as the static (or bias) variation. This quasi­
static assumption has been proven to work quite well for many design applications
[6-1]. Therefore, as a first step for the nonlinear modeling, the bias dependence of
the model parameters extracted using the technique developed in this work will be
investigated. Subsequently, the influence of the device intrinsic parameters on
circuit operation will be evaluated to better understand the nonlinear characteristics
of HBTs under various bias operations.
B. Demonstrate Improved Device Performance and Design
By analyzing the extracted model parameters and the physical structures of
the device, it is expected that improved device design can be realized. For example,
the base contact resistance is identified to be the dominant component of the total
base series resistance and is an important parasitic limiting the microwave
Chapter 6 Conclusions
142
performance of our devices. A higher base doping and/or lower contact resistivity
metallization scheme or an improved p-type contact fabrication procedure should
be used to achieve higher frequency response. Additionally, the impact of using the
extrinsic collector proton (or oxygen) implantation to reduce the extrinsic basecollector junction capacitance [6-2, 6-3] can be investigated using the techniques
developed in this thesis work.
(ii) Device Fabrication
A. p-Type Ohmic Contact
Fabrication of the p-type ohmic contact to the base layer has been one of
the most important process steps in HBT fabrication. As device dimensions are
reduced, low-resistance ohmic contacts are required to achieve low base series
resistance so that the high-frequency performance of the device can be
proportionately improved. At the same time, due to high current density operation
associated with the device scaling, a thermodynamically stable and uniform contact
is needed to ensure reliable device operation. A high eutectic melting point
metallization system, such as Ti/Pt/Au, can be used to improve the contact
planarity, the thermal stability and the current flow uniformity [6-4]. Unfortunately,
at lower base doping (5x1 O'8 ~ lx l0 /9 cm5), the specific contact resistivity for this
system is not suitable (pf = 2.3x10 s Q-cm2) for devices with small dimensions. A
careful electrical and reliability study of this metallization system for higher base
doping (lxlOi9 ~ 6 xl0'9 cm 5) should be performed.
Chapter 6 Conclusions
143
B. HBTs Using Other Materials
As discussed in section 3.4, HBTs based on the Gaj ; In49P/GaAs system
should be explored. The degree of improvement over AlGaAs/GaAs should be
investigated for a wide range of applications, such as VCOs and power amplifiers
and high-speed digital IC's. Al48InJ2As/In^Ga47As and InP/InJJGa47As HBTs
lattice-matched to semi-insulating InP substrates show great promise as highfrequency devices and can be integrated with optical devices for use in longer
wavelength optical communication system. The strained Si/SiGe HBT with its
potential compatibility with the vastly more mature Si bipolar transistor technology
is also an excellent candidate for high-frequency operation.
R eferen ces
[1-1]
A. Y. Cho and J. R. Arthur, "Molecular beam epitaxy," Prog. Solid-State
Chem., vol. 10, Pt. 3, pp. 157-191,1975.
[1-2]
R. D. Dupuis, L. A. Moudy, and P. D. Dapkus, "Preparation and properties
of Gay.j/djAs-GaAs heterojunction grown by metal-organic chemical vapor
deposition," Gallium-Arsenide and Related Compounds, 1st. Phys. Conf.
Ser., vol. 45, pp. 1-9, 1979.
[1-3]
M. Hirayama, K. Honjo, M. Obara, and N. Yokoyama, "HBT IC
technologies and applications in Japan," IEEE GaAs IC Symp. Dig., pp. 36, 1991.
[1-4] P. M. Asbeck, M. F. Chang, J. J. Corcoran, J. F. Jensen, R. N. Nottenburg,
A. Oki, and H. T. Yuan, "HBT application prospects in the US: where and
when?," IEEE GaAs IC Symp. Dig., pp. 7-10,1991.
[ 1-5] W. Shockley, US Patent 2 569 347, filed 26 June 1948.
[1-6] H. Kroemer, "Theory of a wide-gap emitter for transistor," Proc. IRE, vol.
45, pp. 1535-1537,1957.
References
[1-7]
145
P. M. Asbeck, M. F. Chang, K. C. Wang, D. L. Miller, G. J. Sullivan, N. H.
Sheng, E. Sovero, and J. A. Higgins, "Heterojunction bipolar transistors for
microwave and millimeter-wave integrated circuits," IEEE Tram. Electron
Devices, vol. ED-34, pp. 2571-2579, 1987.
[1-8]
J. A. Higgins, "Heterojunction bipolar transistors for high efficiency power
amplifiers," IEEE GaAs IC Symp. Dig., pp. 33-36,1988.
[1-9]
M. E. Kim et al., "12-40 GHz low harmonic distortion and phase noise
performance of GaAs heterojunction bipolar transistors," IEEE GaAs IC
Symp. Dig., pp. 117-120,1988.
[1-10] M. E. Kim, A. K. Oki, G. M. Gorman, D. K. Umemoto, and J. B. Camou,
"GaAs heterojunction bipolar transistor device and IC technology for highperformance analog and microwave applications," IEEE Trans. Microwave
Theory Tech., vol. MTT-27,pp. 1286-1303, 1989.
[1-11] P. M. Asbeck, M. F. Chang, J. A. Higgins, N. H. Sheng, G. J. Sullivan, K.
C. Wang, "GaAlAs/GaAs heterojunction bipolar transistors: issues and
prospects for application," IEEE Trans. Electron Devices, vol. ED-36, no.
10, pp. 2032-2042, 1989.
References
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[2-1]
C. T. Sah, R. N. Noyce, and W. Shochley, "Carrier generation and
recombination in p/i-junctions, and p/i-junction characteristics," Proc. IRE,
vol. 45, pp. 1228-1243,1957.
[2-2]
C. H. Henry, R. A. Logan, and F. R. Merritt, "The effect of suface
recombination on current in Ga^^Al^s heterojunctions," J. Appl. Phys.,
vol. 49, pp. 3530-3542, 1978.
[2-3]
H. Kroemer, "Heterojunction bipolar transistors and integrated circuits,"
Proc. o f IEEE, vol. 70, no. 1, pp. 13-25, 1982.
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V it a
1963 — Born, Tainan, R.O.C.
1985 — B .S., Tamkang University, Taiwan, R.O.C.
Employment Record
M/A-COM, Inc, MA., Senior Engineer, May 1992.
The Pennsylvania State University, PA, Research Assistant, 1989 to 1992.
Microelectronics Technology Inc., Taiwan, Engineer, 1987 to 1988.
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