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CMOS -based monolithic MEMS technology and its applications in microwave systems

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Mehmet Ozgur
B. S. June 1994, Bilkent University, Ankara, Turkey
M. S. September 1996, Bilkent University, Ankara, Turkey
A Dissertation submitted to
The Faculty of
The School of Engineering and Applied Science
of the George Washington University in partial satisfaction
of the requirement for the degree of Doctor of Science
May 21, 2000
Dissertation directed by
Mona Elwakkad Zaghloui
Professor of Engineering and Applied Science
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Silicon technologies such as CMOS and BiCMOS have been traditionally thought of as
analog and digital electronic processing mediums. However, this has started changing recently
by application of new fabrication techniques borrowed from MicroElectroMechanicalSystems
(MEMS). The new methods have revitalized the field and have created enormous new
opportunities for these technologies. Integrated systems such as micromachined accelerometers,
deformable mirrors, and more recently all-optical routers demonstrate the capabilities of new
systems with the additional functions of sensing and actuation integrated with computational
capability. These new technologies offer lower-cost, smaller size and higher reliability.
In this work, a new micromachining technology, which is termed CMOS-based
Monolithic MEMS Technology (CM-MEMS) is developed. In this technology, the standard
CMOS process procedure is followed by a four-mask low-temperature post-processing. The
post-process consists of ten steps that include thin and thick-film processing, electroplating, bulk
and surface micromachining, and wet and dry etching. Three dimensional, high-aspect-ratio
mechanical structures can be fabricated on top of the CMOS chips, without altering the electrical
properties of the electronic circuits.
The CM-MEMS technology is capable of meeting the requirements of various
applications. The low-frequency applications of this technology include the microfluidic
systems, sensor and actuator applications. The most important advantage of CM-MEMS at lowfrequency application is that it allows the integration of sensing and actuation functions with the
CMOS electronics. Particularly, in this work, the high-frequency applications of the developed
technology are investigated. Several crucial components necessary for a microwave
communication system are demonstrated including Iow-loss coplanar transmission lines, filters,
power couplers and dividers, antennas, thermopile power sensors. One of the most important
aspects of this fabrication approach is that a new class of microwave systems can be developed
that utilize mechanical structures to reconfigure electrical properties of the circuit. Analytical and
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numerical characterization of the developed micromachined components and the verification of
the models via measurements are described.
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I would like to thank my advisors Prof. Mona Zaghloul, and Michael Gaitan for their
guidance, and invaluable encouragement throughout this work
I would like to thank to my family for their understanding, patience and support.
This work is dedicated to people who strive for new ideas and do everything to conquer
their dreams.
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ABSTRACT_____________________________________________________________________ II
T h e S e c o n d S il ic o n R e v o l u t io n
T h e N e e d f o r In t e g r a t io n
l . 1.2
F r o n t ie r s in M ic r o s y s t e m F a b r ic a t io n
S ta te m e n t o f t h e P ro b le m
C o n t r i b u t i o n s o f t h e t h e s is
In t r o d u c t io n
2 .2
M O SFET T echnology
T h e B a s ic F a b r ic a t io n P r o c e s s
F uture o f th e
CMOS T e c h n o l o g y
C M O S M ic ro m a c h in in g a n d C la s s if ic a tio n o f N o v e l A p p lic a tio n s
2 .4
L i m i t a t i o n s o f t h e C M O S M ic r o m a c h i n i n g
E l e c t r o m a g n e t ic L o s s e s
2 .4 .2
M e c h a n ic a l St r e s s
P o l y s il ic o n
In t r o d u c t io n
O v e rv ie w o f
CM-MEMS P r o c e s s
F lo w
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St e p
1: CMOS F a b r ic a t io n
3.2 .2
S t e p 2: D e p o s it io n o f t h ic k f il m p h o t o r e s is t (T F P R -l)
S t e p 3: D e p o s it io n o f S e e d L a y e r
St e p
S t e p 5: E l e c t r o p l a t in g
3.2 .6
S t e p 6: S t r ip p in g t h e S e e d L a y e r
3 .2 .7
S t e p 7: S t r e s s -c o m p e n s a t io n
S t e p 8: B a c k s id e P a t t e r n in g
S t e p 9: B u l k M ic r o m a c h in in g
3 .2 .1 0
S t e p 10: S u r f a c e M ic r o m a c h in in g
D e p o s it io n o f TFPR-2
I n te g r a tio n a n d P a c k a g in g
F a b r i c a t i o n E x a m p le : T u n a b le C a p a c i t o r
C o n c lu s io n
CHAPTER 4____________________________________________________________________ 83
In tro d u c tio n
H ig h P e r f o r m a n c e L u m p ed C o m p o n e n ts
In d u c t o r
RF F il t e r s
Du plex ers
D i s t r i b u t e d D e v ic e s
C o p l a n a r T r a n s m is s io n L in e s (C T L s)
C o u p l e r s a n d D iv id e r s
CHAPTER 5___________________________________________________________________ 193
In tro d u c tio n
T u n a b le C a p a c ito r
5 .2 . l
T r a d it io n a l M e t h o d s
M e c h a n ic a l T u n a b l e C a p a c it o r s
M e c h a n ic a l S w itc h
FET S w it c h e s
PIN S w it c h e s
M e c h a n ic a l S w it c h e s
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5.3 .4
P r o p o s e d S w it c h Im p l e m e n t a t io n s
5.3 .5
D is c u s s io n s
M e c h a n ic a l F il t e r s
S u r f a c e -A c o u s t ic -W a v e (S A W ) F il t e r s
5.4 .2
M e c h a n ic a l F il t e r s
H ig h -T e m p e r a t u r e -S u p e r c o n d u c t o r (H TS) F il t e r s
5 .4 .4
D is c u s s io n s
CHAPTER 6___________________________________________________________________IM
REFERENCES_________________________________________________________________ 188
v ii
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F i g u r e 2 . 1: C r o s s - s e c t i o n a l v ie w s o f
F i g u r e 2.2: V a r i o u s
NMOS f a b r i c a t i o n
seq u en ce.
a rc h ite c tu re s .
F i g u r e 2.3: T h i n f i l m s in a s t a n d a r d 2 M e t a l / 2 P o l y a n a l o g
F i g u r e 2.4: B y m i c r o m a c h i n i n g
CMOS, t h r e e
p ro c e ss.
c l a s s o f d e v ic e s c a n b e f a b r i c a t e d .
CMOS s i l i c o n
F i g u r e 2.5: C o p l a n a r t r a n s m i s s i o n l i n e s f a b r i c a t e d o n
s u b s tra te .
F ig u r e 2.6: T h e r m a l a n d in t r in s ic s t r e s s e s c o n t r ib u t e t o t h e m e c h a n ic a l d e f o r m a t io n s
a f te r th e re le a s e o f th e
F ig u r e 2.7: L a r g e s c a l e m e c h a n ic a l f a il u r e s a r e f a ir l y c o m m o n if l a r g e RF d e v ic e s a r e
F ig u r e 2.8: T h in - g l a s s m e m b r a n e is s o b r it t l e t h a t it c r a c k s d u r in g t h e dry e t c h c y c l e
F ig u r e
3.1: C r o s s - s e c t io n a l
v ie w o f a c h ip f a b r ic a t e d b y t h e
C M O S - b a s e d M o n o l it h ic
F ig u r e
3.2: CMOS f a b r ic a t e d
c h ip o r w a f e r w it h a n o p e n a r e a f o r s il ic o n m ic r o m a c h in in g . 26
F ig u r e
F ig u r e
S p in c u r v e f o r
F ig u r e
3.5: A t y p ic a l TFPR-I
F ig u r e
3.6: C r - A u
F ig u r e
F ig u r e
3.8: S e c o n d
F ig u r e
3.9: G o l d
F ig u r e
3.10: E l e c t r o p l a t in g
F ig u r e
3.11: N o n c o n t a c t o p t ic a l
Ist l a y e r
p r o f il e o f t u n a b l e c a p a c it o r
e v a p o r a t io n
I n - s it u c l e a n in g a n d se e d l a y e r d e p o s it io n s e t u p .
la y er o f
u s e d a s a m o l d fo r e l e c t r o p l a t in g .
e l e c t r o p l a t in g
setu p
in t e r f e r o m e t e r p r o f il e c h a r a c t e r iz a t io n s e t u p
(W y k o
plu s)
F ig u r e
3.12: P r o f il e s
F ig u r e
3.13: C o n c e n t r a t io n
F ig u r e
3.14: P l a t in g
F ig u r e
3.15: CMOS
o f t h e g o ld plated a r e a s .
d if f e r e n c e s a r e e v id e n t in s m a l l a r e a s .
d e p e n d s o n t h e c o n c e n t r a t io n o f r e a c t io n s p e c ie s
d ie t o b e p l a t e d is p l a c e d o n t h e c o p p e r h o l d e r a n d c o r n e r s o f t h e c h ip
w ir e b o n d e d t o t h e b l o c k
F ig u r e
3.16: a f t e r
F ig u r e
3.17: L o w - k p o l y im id e
t h e s e e d l a y e r is r e m o v e d
f o r s t r e s s -c o m p e n s a t io n
v iii
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F ig u re
F ig u re
3.19: T e c h n i q u e s
F ig u re
3.20: C o m p e n s a t i o n
w ith g la s s s u p e r s t r a t e b o n d e d o n t h e a r e a t o be s u sp e n d e d .
F ig u re
3.21: C o m p e n s a t i o n
w ith
F ig u re
F ig u re
3.23: B l o c k
F ig u re
3.24: X e n o n - d i f l u o r i d e
F ig u re
3.25: S a c r i f i c i a l
F ig u re
3.26: L a y o u t o f t h e
F ig u re
3.27: TFPR-l
F ig u re
3.28: A
F ig u re
3.29:3D s u r f a c e
I n te r f e r o m e tr ic m e a su re m e n t of a d is trib u te d f i l t e r
e m p lo y e d f o r s t r e s s c o m p e n s a tio n .
l a y e r d e p o s itio n
B e f o r e ( a ), a n d a f t e r ( b ), b u l k m i c r o m a c h i n i n g o f t h e s i l i c o n .
d ia g r a m o f t h e e tc h in g s y s te m
p h o to re s is t
is r e m o v e d t o r e l e a s e s m a l l m e m b r a n e s
t u n a b l e c a p a c i t o r ( a ) a n d f a b r i c a t e d d e v i c e ( b ).
3 (B).
p a t t e r n i n g in s t e p
f te r s te p
(X e F :) e t c h i n g s t a t i o n s
2 (a) a n d
s te p
p r o f i l e a f t e r s te p s te p 3 o b ta in e d by n o n - c o n t a c t o p t i c a l
in t e r f e r o m e t e r .
F ig u r e 3.3 0 : P a t t e r n e d s e c o n d T F P R , w h ic h is u s e d a s a m o l d d u r in g in 5™ s t e p , is s h o w n
F ig u r e 3 .3 1: If e l e c t r o p l a t in g is l o n g e r t h a n 3 0 m in a n d t h e s o l u t io n t e m p e r a t u r e g e t s
F ig u r e
3.32: T h e p l a t e d
g o l d is c h a r a c t e r iz e d w it h o p t ic a l p r o f il e r p r io r t o
A u /C r s t r ip p in g
F ig u r e
p r o c e s s a l l o w s l o w - l o s s , h ig h p e r f o r m a n c e o p e r a t io n o f
F i g u r e 3.3 4 :
id e a l
f o r l o w - f r e q u e n c y e l e c t r o n i c , MICROFLUIDIC,
F i g u r e 4 . 1: T r a d i t i o n a l s u p e r h e t e r o d y n e - t r a n s c e i v e r a r c h i t e c t u r e r e q u i r e s s e v e r a l h ig h
F ig u r e 4.2: P h a s e L o c k L o o p f r e q u e n c y s y n t h e s iz e r
F ig u r e 4 .3 : A L C - t u n e d o s c il l a t o r a s a f e e d b a c k c ir c u it
F ig u r e 4 .4 : P l a n a r in d u c t o r s a r e m o d e l e d w it h v a r io u s p a r a s it ic s
F ig u r e 4.5: A t l o w f r e q u e n c ie s , m ic r o m a c h in e d in d u c t o r s a r e l im it e d b y t h e c o n d u c t o r
F i g u r e 4 .6 : F o u r t y p e s o f i n d u c t o r f a b r i c a t i o n is i n v e s t i g a t e d
F ig u r e 4.7 : S u s p e n d e d e l e c t r o p l a t e d -c o p p e r in d u c t o r s h a v e v e r y l o w p a r a s it ic s
F ig u r e 4.8 : P o l y im id e s u p p o r t e d C M O S in d u c t o r
F ig u r e 4.9 : P e a k q u a l it y f a c t o r s o f in d u c t o r s a r e c o m p a r e d f o r s e v e r a l d if f e r e n t
t e c h n o l o g ie s .
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F ig u r e 4 .1 0 : L a y o u t p a r a m e t e r s u s e d in t h e s c a l a b l e m o d e l o f t h e in d u c t o r
F ig u r e 4 . 1 1: F r e q u e n c y d e p e n d e n c y o f t h e s e r ie s r e s is t a n c e d e p e n d s o n t h e g e o m e t r ic a l
F i g u r e 4 .1 2 : O b s e r v e d d e p e n d e n c y o f (a , f3) o n g e o m e t r i c a l f a c t o r s .
F ig u r e 4 .1 3 : In d u c t a n c e p e r u n it a r e a in c r e a s e s w it h n u m b e r o f t u r n s u s e d in t h e in d u c t o r .
F ig u r e 4 .1 4 : C a l c u l a t e d p e a k q u a l it y f a c t o r s f o r t h e s a m e s e t o f 10 n H in d u c t o r s s h o w n in
F ig . 4 .1 1.
F ig u r e 4 .1 5 :
QMAXd e p e n d s
stro n g ly o n
F ig u r e 4 .1 6 A r e l a t iv e l y w e a k r e l a t io n b e t w e e n Q.w« a n d
Cs is o b s e r v e d
for a
10 n H
F ig u r e
4.17: RF f il t e r s a n d
d u p l e x e r s a r e n e c e s s a r y t o is o l a t e t h e d e s ir e d f r e q u e n c y
F i g u r e 4 .1 8 : M e a s u r e m e n t a n d s i m u l a t i o n r e s u l t s o f a s e r i e s LC r e s o n a t o r w i t h f l= 3.22
F i g u r e 4 .1 9 : 3.7
GHz t h i r d
o r d e r B u t t e r w o r t h b a n d p a s s f i l t e r is f a b r i c a t e d w i t h o n - c h ip
F ig u r e
4.20: 3.7 GHz f il t e r
is s im u l a t e d w it h t h e e x t r a c t e d c ir c u it m o d e l s o f in d u c t o r s
F ig u r e 4 .2 1 : R e s is t a n c e s o n t h e s e r ie s - o r s h u n t -c o n n e c t e d r e s o n a t o r s h a v e d if f e r e n t
F i g u r e 4 .2 2 : I f i n d u c t o r s w i t h r e s i s t a n c e - t o - i n d u c t a n c e r a t i o s l e s s t h a n e q u a l t o 0.33 Q /n H
F ig u r e 4 .2 3 : F r e q u e n c y a n d im p e d a n c e n o r m a l iz e d b a n d p a s s p r o t o t y p e
F ig u r e 4 .2 4 :
Two c o n f ig u r a t io n s
o f c o u p l e d - l in e s e c t io n s t h a t a r e u s e d f o r b a n d p a s s
a p p l ic a t io n s .
F ig u re
4.25: O p tim iz e d
s in g le s e c tio n r e s o n a t o r s h a v e
0.8 dB l o s s
40 GHz a n d 22 d B
F ig u r e 4 .2 6 : In t e r - s e c t io n d is c o n t in u it y is m in im iz e d w it h t h e m a t r ix c o n n e c t io n o f o p e n o p e n AND SHORT-OPEN SECTION
F ig u r e
4.27: CM-MEMS t e c h n o l o g y
F ig u r e
a l l o w s t h e f a b r ic a t io n o f l o w - l o s s a ir - b r id g e s .
S c h e m a t ic c r o s s - s e c t io n a l v ie w o f a c o p l a n a r w a v e g u id e f a b r ic a t e d o n a
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F ig u r e 4 .2 9 : a ) T h e l in e s h o w n b y w it h d a s h - d a s h in R Q - p l a n e is m a p p e d o n t o r e a l a x is in Z Q
F ig u r e 4.3 0 : W ith p a r t ia l -c a p a c it a n c e a p p r o a c h d e v e l o p e d b y V e y r e s a n d H a n n a
F ig u r e 4 .3 1: T he c a l c u l a t e d c a p a c it a n c e s w it h a n a l y t ic a l f o r m u l a t io n d e v e l o p e d in t h is
F ig u r e 4 .3 2 : C o p l a n a r t r a n s m is s io n l in e s a r e a n a l y z e d w it h s e v e r a l a p p r o x im a t io n s
F ig u r e 4 .3 3 : C o n d u c t o r l o s s is c a l c u l a t e d in t e r m s o f t h e c u r r e n t d is t r ib u t io n in t h e
sy s te m
F ig u re
4.34: Loss
F ig u re
4.35: C o n d u c t o r
i n t e g r a l is t a k e n b e t w e e n p o i n t s
l and 8
l o s s f a c t o r o f m ic r o m a c h in e d
CMOS c o p l a n a r CPW a s
a fu n c tio n
OF Zo FOR fl=68 fJAt
F ig u re
4.36: C r o s s - s e c t i o n a l
F ig u re
F ig u re
4.38: C r o s s - s e c t i o n a l
v ie w o f t h e c o u p l e d c o p l a n a r s e c t i o n a l o n g x - a x is
M i c r o g r a p h o f t h e W ilk in s o n d i v i d e r b e f o r e p o s t - p r o c e s s i n g
v ie w o f t h e p o s t - p r o c e s s e d
CMOS c h ip
w ith e n c lo s e d b o n d
F i g u r e 4 .3 9 : M e a s u r e d a n d s im u l a t e d r e s p o n s e s o f t h e W il k in s o n d iv id e r
F i g u r e 4.4 0 : F r e q u e n c y d e p e n d e n c ie s o f t h r e e p o l y s i l i c o n t e s t r e s i s t o r s
m e a s u re d up t o
1 16
R,, R:, a n d R, a r e
50 GHz
F ig u re
4.41: M i c r o p h o t o g r a p h
F ig u re
4.42: SEM p i c t u r e
o f t h e m ic r o m a c h in e d K a - b a n d b r a n c h l i n e c o u p l e r
o f t h e c o m p e n s a t e d m e m b r a n e . F ilm t h i c k n e s s e s a r e r e a d f r o m t h i s
F ig u r e 4 .4 3 : Il l u s t r a t io n o f a c o m p e n s a t e d g r o u n d e q u a l iz a t io n s e c t io n u se d in B L C
F ig u r e 4 .4 4 : O n e o f t h e T - ju n c t io n s s h o w in g c o m p e n s a t e d 2 nd l e v e l m e t a l l iz a t io n a n d
F ig u re
4.45: G r o u n d
F ig u re
4.46: C a p a c i t a n c e
e q u a l i z e r s a r e m o d e le d w i t h a s h u n t lu m p e d c a p a c i t a n c e
c o n t r i b u t i o n s f r o m s o u r c e s i d e n t i f i e d in F ig .
4.45 a s
a fu n c tio n o f
F ig u r e 4 .4 7 : C a p a c it a n c e c o n t r ib u t io n s fr o m s o u r c e s id e n t if ie d in F ig . 4.45 as a f u n c t io n o f
F i g u r e 4.4 8 : E q u i v a l e n t c i r c u i t o f t h e T - j u n c t i o n s w i t h i n t e r n a l g r o u n d - e q u a l i z e r s .
F i g u r e 4 .4 9 : T h e T - j u n c t i o n s w i t h (z.,d)=(35, 10) f o r 5 0 Q a n d (35,20) f o r 35 £2 a r e s i m u l a t e d b y
u s in g t h e c a p a c i t a n c e s f r o m a 3D q u a s i - s t a t i c f i e l d s o l v e r .
F ig u r e 4 .5 0 : E a c h s u b s e c t io n is s im u l a t e d s e p a r a t e l y a n d t h e n s u b s e c t io n s a r e s im u l a t e d
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F i g u r e 4 .5 1: M e a s u r e d a n d s i m u l a t e d r e s p o n s e o f a n o n - c h ip 5 0 Q. t e r m i n a t i o n
F i g u r e 4.5 2 : M e a s u r e d a n d s i m u l a t e d r e s p o n s e o f t h e
BLC w h e n
3 rd p o r t is t e r m i n a t e d .
F i g u r e 4 .5 3 : T w o - p o r t m e a s u r e d a n d s i m u l a t e d r e s p o n s e o f t h e m i c r o m a c h i n e d
BLCw h e n
3 rd
F ig u r e 4.5 4 : S im u l a t e d m a g n it u d e a n d p h a s e d if f e r e n c e b e t w e e n 2 nd a n d 3 rd p o r t s .
F ig u r e 5.1: E l e c t r o s t a t ic a c t u a t io n is b a s e d o n c a p a c it iv e f o r c e s b e t w e e n t h e p l a t e s
F ig u r e 5.2: T h e r m a l e x p a n s io n d if f e r e n c e s b e t w e e n t w o a r m s c a u s e t h e t ip o f t h e b e a m t o
F ig u r e 5.3: A n o v e l t u n a b l e c a p a c it o r w it h in t e g r a t e d t h e r m a l a c t u a t o r is d e v e l o p e d
F ig u r e 5 .4: S u r f a c e p r o f il e o f a n a c t u a t e d b o t t o m p l a t e
F ig u r e 5.5: A c t u a t e d p l a t e o f t h e m e c h a n ic a l c a p a c it o r is m o d e l e d a s a f ix e d - f ix e d - b e a m
F ig u re
5.6: C r o s s - s e c t i o n a l
F ig u re
5.7: E q u i v a l e n t c i r c u i t o f
F ig u re
5.8: C a p a c i t a n c e
v ie w o f t h e
FFB h a s
a n o n -u n ifo rm p r o f ile
m e c h a n ic a l t u n a b l e c a p a c ito r
p e r u n i t l e n g t h o n x - a x i s is c a l c u l a t e d b y u s i n g p a r a l l e l - p l a t e
F ig u r e 5.9: T h e n o n - l in e a r p r o f il e o f t h e b o t t o m p l a t e is c r it ic a l in t h e c a p a c it o r d e s ig n .
F i g u r e 5.10: ( d -Vumx) is t h e m in im um d i s t a n c e b e t w e e n t w o p l a t e s
F ig u r e 5 . 11: T u n a b l e c a p a c it o r p r io r t o p o s t - p r o c e s s in g f a b r ic a t io n
F ig u r e 5.1 2 : ( a ) P a r a s it ic e l e m e n t s d u e t h e p a d a n d t h e t r a n s m is s io n l in e s e c t io n t h a t a r e
F ig u re
5.13: M e a s u r e m e n t
F ig u re
5.14: M e a s u r e d
a n d c u rv e -fit r e s u l t f o r a tu n a b le c a p a c ito r
c a p a c ita n c e c h a n g e o b ta in e d fro m th e r m a lly a c tu a te d tu n a b le
F i g u r e 5 .1 5 :
FET s w i t c h e s
o p e r a te by c o n tr o llin g th e c h a n n e l re s is ta n c e
F i g u r e 5.1 6 : S m a l l s i g n a l e q u i v a l e n t m o d e l s f o r
PIN d io d e s
F i g u r e 5.17: S h u n t - t y p e , e l e c t r o s t a t i c a l l y a c t u a t e d
fa b ric a te d
SPST s w i t c h
o p e r a t e s w ith v e r y h ig h
c a p a c ita n c e r a t i o s b e tw e e n tw o s t a t e s
F ig u r e 5 . 18: T o p s id e v ie w a n d c r o s s - s e c t io n a l v ie w a l o n g x - a x is f o r a t h e r m a l l y a c t u a t e d
F ig u r e 5 .1 9 : C r o s s - s e c t io n v ie w o f t h e f a b r ic a t e d c a n t il e v e r s a l o n g y- a x is .
F ig u r e 5 .2 0 : P r o p o s e d l a y o u t o f T y p e -I a s w it c h . T h e c o n t a c t p a d o n FFB s h o r t s t w o s ig n a l
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F ig u r e
5.21: T y p e -I b
F ig u r e
5.22: M ic r o g r a p h o f T y p e -H a
F ig u r e
5.23: M ic r o g r a p h
o f s h u n t -T y p e -II a s w it c h p r io r t o p o s t - p r o c e s s in g
F ig u r e
5.24: M ic r o g r a p h
F ig u r e
5.25: S e r ie s
F ig u r e
F ig u r e
5.27: P r o f il e o f t h e
F ig u r e
5.28: V e r t ic a l PIN d io d e s
s e r ie s s w it c h p r io r t o p o s t - p r o c e s s in g
s w it c h p r io r t o p o s t - p r o c e s s in g
T y p e -II b s w it c h p r io r t o p o s t - p r o c e s s in g
( a ), a n d s h u n t ( b ), T y p e -II- a s w it c h e s
In t e r f e r o m e t r ic m e a s u r e m e n t s o f t h e s h u n t T y p e -II- a s w it c h f a b r ic a t e d
r e l e a s e d c a n t il e v e r s h o w n in
F ig . 5 .2 5 b
w it h a ir - b r id g e c o n n e c t io n r e q u ir e v e r y s o p h is t ic a t e d
F ig u r e 5.2 9 : In t e r m e d ia t e f r e q u e n c y (IF) f il t e r s a r e n e c e s s a r y t o f il t e r c l o s e l y s p a c e d
F ig u r e
5.30: T y p ic a l l y ,
m e c h a n ic a l f il t e r s e m p l o y a m e c h a n ic a l r e s o n a t o r t o a c h ie v e h ig h
F ig u r e
5.31: T o p s id e v ie w
F ig u r e
5.32: SEM o f a s p r in g - c o u p l e d
o f a f u l l y in t e g r a t e d m ic r o m e c h a n ic a l r e s o n a t o r o s c il l a t o r
b a n d p a s s m ic r o m e c h a n ic a l f il t e r u s in g
5.33: SEM o f
F ig u r e
a f r e e - f r e e - b e a m m ic r o m e c h a n ic a l r e s o n a t o r
x iii
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T a b l e 3.1: C o m p a r is o n b e t w e e n p o l y im id e a n d B C B d ie l e c t r ic f il m s
T a b l e 4 . 1: P h y s ic a l c o n s t a n t s a n d p a r a m e t e r s u s e d in t h e m o d e l
T a b l e 4 .2 : E x p e r im e n t a l v e r if ic a t io n o f t h e s c a l a b l e m o d e l f o r m ic r o m a c h in e d in d u c t o r s
T a b l e 4 .3 : E x p e r im e n t a l v e r if ic a t io n o f t h e s c a l a b l e m o d e l f o r m ic r o m a c h in e d
T a b l e 4 .4 : N u m e r ic a l v e r if ic a t io n o f t h e d e v e l o p e d a n a l y t ic a l f o r m u l a t io n fo r c o u p l e d
T a b l e 4 .5 : C P W d im e n s io n s o f e x p e r im e n t a l d a t a s e t s a n d c o m p a r is o n o f c o m p u t e d a n d
T a b l e 4 .6 :3 D e m s im u l a t io n s s h o w t h a t T - j u n c t io n is f a ir l y in s e n s it iv e t o t h e in d ic a t e d
(D, L).
T a b l e 5 .1 : C o m p a r is o n o f s t a t e -o f -t h e a r t t u n a b l e c a p a c it o r s
T a b l e 5.2: M e c h a n i c a l p r o p e r t i e s o f t h i n - f i l m s . M e a s u r e d v a l u e d o f r e s i d u a l s t r e s s ,
Y o u n g 's m o d u l u s ,
E, a n d
P o is s o n 's r a t io a r e m e a s u r e d g iv e n in
T able
5.3: Two c a p a c it o r s
T able
5.4: St a t e -o f - t h e - a r t FET s w it c h e s
T able
5.5: S t a t e -o f -t h e - a r t P IN
T able
5.6: C o m p a r is o n
T able
T a ble
5.8: C o m p a r is o n
T a ble
w it h id e n t ic a l c a p a c it a n c e r a t io s a n d m a x im u m c a p a c it a n c e s
s w it c h e s
o f s t a t e - o f - t h e a r t m e c h a n ic a l s w it c h e s
F o u r s w it c h c o n f ig u r a t io n s a r e in v e s t ig a t e d
o f s w it c h t e c h n o l o g ie s in t e r m s o f t h e c u t - o f f f r e q u e n c ie s
P r o p e r t ie s o f c o m m o n a c o u s t ic m a t e r ia l s
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17 1
The Second Silicon Revolution
“A second silicon revolution is under way in the electronics world. Its hallmark is the
integration of mechanical structures and multifunctional materials alongside microcircuits on one
and the same chip. Actuators, passive tunable microwave devices, optical devices, micropumps,
valves, and various chemical and physical sensors are being monolithically integrated with
transistors to generate new generations of integrated microsystems that perform superbly and
cost less.” [1]
“Until now, the microelectronics industry has measured its progress by the number and
smallness of the transistors that can be packed on a single piece of silicon. In the future, this
metric will be supplanted by others that measure how capable a chip is: how well it can
understand and influence its environment, and how it can assist or enlighten its user.”
Several precursors of the new microsystems are already familiar. One is the thermal ink­
jet printer module, a self-contained print head that packages silicon MOS control circuitry and
resistance heaters with micromachined orifices through which ink droplets are ejected. It
achieves degrees of resolution and speed impossible with traditional technology.
Another example is the airbag-release module for automobiles. The crash-detection
device combines silicon micromachined accelerometers with electronics for triggering airbag
inflation. The modules are produced in large quantities, and at least one version monolithically
integrates electronic and mechanical functions on a single chip. The airbag sensors also "wake
up" and do a self-check when the automobile ignition key is turned—the kind of self-awareness
anticipated for the microsystems of tomorrow.
Yet another device is the digital micromirror display, developed by Texas Instruments
Inc., Dallas. Now being marketed for projection displays, the device consists o f an array
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containing millions of electrostatically controlled tiltable mirrors, plus circuitry, fabricated on a
single silicon chip.
The Need for Integration
Semiconductor manufacturing techniques used in the batch fabrication of microsensor
systems could give them integrated circuit (IC)-like performance and cost-effectiveness. Other
advantages also accrue, including smaller size, lower weight, higher performance, and greater
reliability, as well as the possibility of new capabilities.
The most compelling motivator for such system-on-a-chip development, particularly for
high-volume applications, is cost. Integrated microsystems promise to be by far the least costly
because the expense of packaging the microsystem and assembling it into a macrosystem will be
drastically reduced. Much of the labor involved for those tasks would simply disappear.
An added benefit of systems on a chip is their smaller volume and lighter weight. In
many applications, such as satellites, size and weight can be key contributors to cost.
In other applications, the factor of importance is performance. For example, the output
signal from a sensor is often a change in capacitance. For some accelerometers and gyros, small
changes in a femtofarad capacitance must be monitored. For such a device, sensitivity and
performance can be seriously degraded by the parasitic capacitance of bond pads on the chip as
well as that of the interconnect wiring between the sensor chip and the control electronics.
Putting everything on the same piece of silicon means the control electronics can be fabricated
next to the sensors, all but eliminating the interconnect capacitance, and greatly improving the
ultimate sensitivity and performance.
System reliability improves because a prime failure mechanism in traditional ICs-the
failure of the bond wires used to electrically connect the circuit to the package—is eliminated.
Performance and reliability advantages are multiplied as higher degrees of integration occur,
reducing not only bond pads and bond wires, but also the number of board and system
The issue of monolithic integration versus assembly of microsystems from discrete
components remains controversial because high-volume applications will be needed to make the
monolithic approach economical. We believe however, that the enormous capability of these
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monolithically integrated microsystems, along with their low cost and high reliability, will fuel
the development of powerful applications that will generate a phenomenal demand.
Frontiers in Microsystem Fabrication
A MicroElectroMechanicalSystem (MEMS) is a miniature device or an array of devices
combining electrical and mechanical components and fabricated with Integrated Circuit (IC)
batch-processing technique. Critical to this definition is that MEMS has both device and
fabrication aspects. There are several MEMS fabrication techniques currently in widespread use,
including bulk and surface micromachining, thick-film processing, molding, electroforming. The
fabrication of a monolithic MEMS device with integrated mechanical and electrical systems
requires a mass-fabrication process, which combines several of these MEMS fabrication
techniques with standard thin-film process modules.
The thin-film process modules are well-developed technologies such as CMOS,
BiCMOS, bipolar fabrication technologies. Although these modules are fairly sophisticated with
as much as 200 process steps, essentially, they consist of several photolithographic steps after
initial ion implantation and oxidation. Controlled deposition of a thin-film and its patterning
assures the fabrication of thin-films at precise locations with desired electrical properties.
Despite the considerable number of steps, the semiconductor industry equipped with the
electronic design automation (EDA) tools, is very successful in obtaining consistent fabrication
results. Semiconductor revenues accounting these processes are estimated to be more than $150
billion for 1999.
On the other hand, there are few established monolithic MEMS process modules
available. Moreover, only two of them are capable of monolithic integration of electronics and
mechanical systems. These two technologies are iMEMS by Analog Devices and Digital
Micromirror Device (DMD) Technology by Texas Instruments. Both of these technologies use
CMOS (or BiCMOS) technology as a base process module, and add a single film of surface
micromachined layer. Unfortunately, these process have been developed for a specific
applications, therefore their capabilities are limited.
The first generation commercial MEMS processes utilize surface micromachining, which
is fabrication of micromechanical structures from deposited thin films. Originally employed for
integrated circuits, films composed of materials such as low-pressure chemical-vapor-deposition
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polycrystalline silicon, silicon nitrite, and silicon dioxides can be sequentially deposited and
selectively removed to build or "machine" three dimensional structures whose functionality
typically requires that they be freed from the planar substrate [2].
Sandia National Labs’ SUMMIT and Integrated MEMS, and University of California at
Berkeley (UCB)’s Modular Monolithic MEMS Technologies are more advanced surface
micromachining technologies, but none of them are available commercially as of January 2000.
These technologies employ thick structural-polysilicon films to realize the mechanical systems.
The integration of low-stress polysilicon films is a significant challenge, since the process needs
annealing temperatures in excess of 800 °C. In EMEMS process, this problem is solved by
fabricating the mechanical structures before the electronic circuits. On the other hand, UCB
changed the metallization in the electronics part of the system with tungsten, which can
withstand the elevated annealing temperatures.
Despite the improvements in surface micromachining techniques, such MEMS process
modules have limited applications. Although several revolutionary devices have been fabricated
by surface micromachining, all of these devices need mechanical freedom for their functionality.
Therefore, the processes, in which these devices are fabricated, can be classified as lowfrequency MEMS processes. On the contrary, radio-frequency (RE) applications such as mobile
communications have different requirements. The quality requirements of the high frequency
components can only be met by using additional MEMS techniques.
The quality of passive RF devices is improved by decreasing the dielectric and conductor
losses. The dielectric losses can be minimized either by increasing the distance between the
device and substrate or by removing the substrate altogether. Generally, the latter of these
options is preferred. The etching step, in which this is achieved, is called bulk micromachining.
The available etching methods fall into three categories in terms of the state of the etchant: wet,
dry, and plasma [2]. In addition, the conductor losses are minimized by depositing thick metals.
The integration of active and passive RF circuits is far more difficult than the similar
challenge encountered in low-frequency MEMS processes. The main problem is that the
traditional silicon-based IC processes are limited by the low electron mobility in the silicon. The
lack of speed in silicon has led to development of alternative thin-film processes based on exotic
materials such as GaAs, SiGe, and InAs etc. However, these new technologies are considerably
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more expensive than silicon based technologies (except SiGe technology), therefore the designs
realized in them have never reached the same level of integration. Additionally, passive
microwave systems have to be designed with distributed elements, which are generally very
large. Consequently, the fabrication of integrated systems is very expensive at high frequencies.
In practice, only very important passive components are integrated with the active devices.
Others are manufactured on low-cost microwave substrates. Currently, the cost-optimized
solution is based on chip level integration on the microwave substrates.
The high frequency MEMS processes under development follow the same trend [3].
Perhaps, the biggest improvement brought by the use of MEMS processes at frequencies above
1 GHz is that the microwave substrate is replaced by bulk-micromachined silicon substrates.
This approach offers lower dielectric loss, lower conductor loss, lower dispersion, and better
dimensional control. This extends the frequency of operation to higher frequencies. One of the
novel devices that has very promising future is the mechanical switch. Even the first generation
of these switches performed better than their optimized active counterparts that have been used
heavily in communication applications. Availability of such low-cost high-performance
mechanical switches will revolutionize the field, because there is a whole new class of devices
that can be realized by using these switches for reconfiguration purposes. Microwave systems
employing such components will perform significantly better than those without them.
Statement of the Problem
The combination of the new and old fabrication techniques has proved to be very
promising for the electronics industry. However, this industry that used to handle several
specialized processes with difficulty, now faces a far more difficult challenge: the development
of a highly functional processes that can manufacture products with variety of functions. These
processes must produce not only traditional VLSI circuits and memories but also many sensors,
actuators, microfluidic, optical and reconfigurable RF components.
None of the commercial processes and processes under development is capable of
integrating this wide variety of processes in a single process. On the other hand, since such a
process will have very wide range of applications, the products that are fabricated through such a
process will have several advantages compared to those manufactured through a specialized
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process, not only because additional functions can be added to increase their functionality, but
also because of their lower cost, higher reliability and smaller size.
While the density of the VLSI circuit is still increasing, it is predicted that the
fundamental limits will be reached in a decade. Increasing cost of research and fabrication as the
feature size goes below the wavelength of the optical lithographic sources, additional means of
increasing the value of the product will become important. Therefore, it is believed that the
semiconductor industry will need highly-functional fabrication processes.
Among the fastest growing markets in the last decade, the communication market is
particularly important. Mobile, optical and satellite communication are expected to grow,
because the demand for the broadband communication is far from being satisfied. Consequently,
the next generation technologies have to take into account the requirements of the
communication market.
In addition, this new technology must be flexible enough to be used in the new fields
such as the microfluidic systems. Finally, even the most sophisticated solution to this problem
must have well-defined chip-level or wafer-level integration schemes. New technologies include
more and more of packaging and integration processes into chip-level processes to lower the cost
of the fabrication.
Contributions of the thesis
In this thesis a new micromachining process termed as CMOS-based Monolithic MEMS
(CM-MEMS) is described. This highly functional process can be used for all the applications
described below:
1. CMOS analog and digital circuits.
2. Sensors based on piezoresistive, thermal, or mechanical effects.
3. Actuators based on electrostatic and thermal effects.
4. Mechanical systems.
5. Integrated passive and active MicroFluidic components.
6. Passive RF components operating frequencies up to 60 GHz.
7. Reconfigurable microwave systems.
In addition, no extra process is necessary for the integration of active microwave circuits. They
can be readily integrated with this process.
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It is believed that CM-MEMS is the first MEMS technology to offer this level of
functionality. To demonstrate the full potential of the developed process is beyond the scope of
this thesis. Instead, the capabilities of this technology are demonstrated for RF and microwave
applications. The contributions in this area are summarized as follows:
A. Improvements in fixed-response passive RF devices.
B. Reconfigurable passive RF devices.
The fixed-response RF devices are the types of devices that have fixed mechanical geometry and
cannot be reconfigured by using actuators. The improvements in their performance are due to the
micromachining that minimizes the losses and dispersion. Six fixed-response passive RF devices
are described. These devices are
A l. High quality micromachined inductors.
A2. Micromachined lumped filters and duplexers.
A3. Micromachined coplanar transmission lines.
A4. Coupled coplanar transmission lines.
A5. Wilkinson power divider.
A6. Internally ground-equalized branch line coupler.
All of the devices are described with developed analytical and numerical models, their
performance is verified with measurements. Beside the demonstration of these components in
this new technology, serious consideration has been given for their theoretical understanding.
The theoretical contributions for the devices listed above are summarized below:
A scalable, physical-model for micromachined inductors is developed that accounts
for the parasitics in a fabricated device. It is experimentally shown that it predicts the
inductor performance accurately.
A layout optimization procedure for inductors is developed based on the physical
Feasibility of the lumped filters is shown for the third generation mobile
communication systems.
A new semi-analytical quasi-TEM formulation for micromachined transmission lines
is developed. For the first time, a formulation that can be incorporated in a CAD
environment includes the effects of finite thickness of dielectric layers and finite
thickness of metal strips.
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A surface impedance formulation based on quasi-static approximation is developed
for the conductor losses for micromachined coplanar lines.
Quasi-static thickness corrections to the coupled-coplanar transmission line
formulation are introduced.
Novel filter architectures based on coupled-coplanar transmission lines have been
Self-annealing for polysilicon resistors used in RF systems is introduced.
A new type of ground-equalization method is introduced: Internal groundequalization!
Three types of ground equalization techniques are investigated: wirebonding, air­
bridge, internal.
The second of class of devices is referred as the reconfigurable passive RF devices. The
response of these devices can be altered by mechanical reconfiguration. In this thesis, five novel
devices are discussed that take full advantage of the new MEMS process. These are:
B 1. Thermally actuated tunable capacitor.
B2. Two configurations of electrostatically-actuated mechanical switch.
B3. Two configurations of thermally-actuated mechanical switch.
Mechanical tunable capacitors and switches have enormous
communication applications. Perhaps one of the most important applications is the next
systems employ
superheterodyne architectures with at least two intermediate frequency stages. Currently, the
stringent requirements can only be satisfied by using components from various technologies,
such as surface-acoustic-wave (SAW), low-temperature-cofired-ceramic (LTCC), and highquality discrete inductors and variable capacitors (varactor). The quality of the devices that are
fabricated with the CM-CMOS technology is comparable or better than the solutions given by
these alternative technologies.
Reconfigurable passive microwave devices can also be used in distributed systems.
Particularly, tunable capacitors can be used in tunable filters and tunable matching networks.
Currently, there is no known method to achieve integrated tunable filters at RF frequencies.
Tunable filters based on Texas Instruments DMD technology has already been demonstrated, but
they use high quality switches to control a capacitor bank to obtain the desired performance [3],
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Filters based on tunable capacitors are more compact, and consume less power compared to the
ones based on the capacitor-banks. However, the use of mechanical switches in the tunable filter
is quite significant, because it is one of the first examples of the reconfigurable RF systems. The
mechanical switches can also be used up to frequencies 60 GHz to reconfigure the distributed
networks, such as antennas, couplers, and distributed filters.
The contributions in this part of the thesis are summarized as follows:
A novel thermal capacitor architecture is demonstrated based on the actuation of
fixed-fixed beams.
A scalable electrical equivalent model based on the physical parameters of the
capacitor is developed. The potential of the proposed design is demonstrated based on
this model.
Cantilever-based thermal actuation is proposed for mechanical switch applications.
Four different categories of switches are investigated. Novel implementations for
each category are proposed.
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CMOS technology has been the driving force for the semiconductor industry since early
1970s. The number of transistors per system and performance have been increasing steadily
since CMOS fabrication was invented. Fabrication breakthroughs such as deep-UV lithographic
systems, copper interconnect, low-k interlayer dielectrics and system level innovations such as
superscalar CISC-based CPU systems, neural networks, novel digital signal processing (DSP)
architectures (such as very long instruction word -VLIW- architectures) have contributed to this
incredible pace of growth. Nonetheless, everything has been achieved without changing the basic
outline of a CMOS process.
More recently, several micromachining techniques have created big repercussions
throughout the semiconductor industry. Among these techniques are surface and bulk
micromachining of silicon, chemical-mechanical polishing (CMP) and advanced electroplating
techniques have shown numerous novel devices that finally have made their ways to the market.
None of the previous efforts has concentrated on CMOS technology with an aim of
creating a high performance microwave technology by modifying the CMOS process. In this
work, a combination of new technologies is presented to achieve passive microwave systems
integrated with CMOS circuits. Since CM-MEMS is based on the CMOS fabrication, in this
chapter underlying CMOS process flow and its limitations are discussed.
MOSFET Technology
At present, the MOSFET is the dominant device used in VLSI circuits, because it can be
scaled to smaller dimensions than can other types of devices. MOSFET technology can be
subdivided into NMOS (n-channel MOSFET) technology and CMOS (complementary
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MOSFET) technology, which provides n-channel and p-channel MOSFETs on the same chip.
Both technologies are attractive because the NMOS circuit has fewer processing steps than does
the bipolar transistor, while CMOS circuit has substantially lower power consumption compared
to both bipolar and NMOS circuits.
The Basic Fabrication Process
For NMOS processing, the starting material is a p-type lightly doped (~1015 cm'3),
<100>-oriented, polished silicon wafer. The <100>-orientation is preferred over <111> because
it has an interface trap density which is about one tenth of <11 i>. The first step is to form the
oxide isolation. A thin oxide pad (-500 °A) is thermally grown, followed by a silicon nitride
(-1000 °A) deposition (Fig. 2.1a). The active device area is defined by a photoresist mask, and a
boron chanstop (channel-stop) layer is then implanted through the composite nitride-oxide layer
(Fig. 2.1b). The nitride layer not covered by the photoresist mask is subsequently removed by
etching. After the stripping the photoresist, the wafer is placed in an oxidation furnace to grow
the field oxide where the nitride layer is removed, and to drive the boron implant. The thickness
is field oxide is typically 0.5 to 1 pm.
The second step is to grow the gate oxide and to adjust the threshold voltage. The
composite nitride-oxide layer over the active area is removed, a thin gate oxide layer is grown.
For an enhancement-mode n-channel device, boron ions are implanted in the channel region as
shown in Fig. 2.1c to increase the threshold voltage to a predetermined value. For a depletion­
mode n-channel device, arsenic ions are implanted in the channel region to decrease the
threshold voltage to a negative value.
The third step is to form the gate. A polysilicon layer is deposited and is heavily doped by
diffusion or implantation of phosphorus to a typical sheet resistance of 20 to 30 Q/sq. This
resistance is adequate for MOSFETs with gate lengths larger than 3 pm. For smaller devices,
refractory metals or polycides (i.e. a composite layer of metal silicide and polysilicon) are used
as the gate materials, to reduce the sheet resistance to about I Q/sq.
The fourth step is to form the source and drain. After the gate is patterned (Fig. 2. Id), it
serves as a mask for the arsenic implantation to form the source and drain, which are self-aligned
with respect to the gate. At this stage, the only overlapping of the gate is due to lateral straggling
of the implanted ions. If low-temperature processes are used for the subsequent steps to
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Patterned polysilicon gate
S i3N4
SiO ,
Boron Field Implant
Arsenic Implant
Boron Channel Implant
Field Oxide
Flowed p-glass
Figure 2.1: Cross-sectional views of NMOS fabrication sequence, (a)
Formation of SiC>2 , Si3 N4 and photoresist layer, (b) Boron field implant, (c)
Growth of field oxide, (d) Formation of polysilicon gate, (e) Formation of source
and drain ohmic contacts, (f) P-glass deposition.
minimize lateral diffusion, the parasitic gate-drain and gate-source coupling capacitances can be
much smaller than the gate-channel capacitance.
The fifth step is metallization. A phosphorus-doped (p-glass) is deposited over the entire
wafer and it is flowed by heating the wafer to give a smooth surface topology (Fig. 2.If). The
contact windows are defined and etched in p-glass. A metal layer, usually aluminum, is then
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Contact Metallization
Figure 2.1: (g) Completed single poly/single metal NMOS transistor.
deposited and patterned. The cross-sectional view of the completed single poly/single metal
MOSFET is shown in Fig. 2.1g.
If necessary more layers of metallization can be added on top to increase the connectivity
of the process. A CMOS process is very similar to the fabrication of NMOS process, except for
the p-channel MOSFET B+ and BFi ions are implanted into the n-well to form the source and
drain regions. A channel implant of arsenic ions may be used to adjust the threshold voltage.
Because of the additional steps needed to make the p-channel MOSFET, the number of steps to
make a CMOS circuit is essentially double that to make an NMOS circuit as shown in Fig. 2.2a.
There are alternative approaches to realize CMOS circuits. Instead of using n-well in ptype substrate, it is possible to use p-well in n-type substrate. In this case p-type compensation
must be high enough to overcompensate for the background doping of the n-substrate. In both
the p-well and the n-well approach, the channel mobility is degraded, because mobility is
determined by the total dopant concentration. Therefore, a third approach uses two separate wells
implanted into a lightly doped substrate as shown in Fig. 2.2b. This is called the twin well
approach. Because no overcompensation is needed in either of the twin wells, higher mobilities
can be obtained.
As the density of the transistors increases the necessary number of interconnection layers
must be increased to fully utilize the potential. As you go higher up in the interconnect layers, it
becomes important not to change the properties of the previous layer. The most important
limitation that will be considered here is the thermal budget of the structure. In most of the cases,
the melting point of aluminum determines the maximum temperature allowed for the next
processing step. Although general outline of the process is known, the details of a specific
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Oxide Spacer
Gate Oxide
Oxide Spacer
Gate Oxide
Figure 2.2: Various CMOS architectures, (a) Trench-isolation n-well CMOS technology,
(b) Twin-well CMOS technology.
process are not disclosed by the foundries. The thin films of a typical CMOS process are shown
in Fig. 2.3, where unknown thicknesses are indicated.
Future of the CMOS Technology
For transistors built between the years 2003 and 2006 in the 100-130 nm lithography
generation, minimum channel length will be 50 nm yielding a current gain frequency well
beyond 100 GHz and an unloaded digital circuit delay of about 10 ps.
Scaling principles dictate that as the channel length scales down, power supply voltage
must be reduced as well. Active power, which is proportional to the square of supply voltage,
and electric field will otherwise exceed reasonable limits. A high electric field can lead to a
number of deleterious effects that could impact chip reliability. Examples are hot-carrier
injection to gate oxide and electromigration due to the increased current density. Threshold
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S i,N ,n
< 0 .0 pm t?)
MX) pm plasma oxufc tf-4 4 )0 “ C >2h
pm tfsubstnuc temp
and 34) mm bake
I--------------------------------------------------------------------------------- 1 MI-M2 mule
L ..,
■ -i — -. i
1 0.h5 pm plasma oxide <4- 44)0 “ C
Ml Aluminum
(^substrate temp 2X1 “ C 4 mm
and 30 nun hake
| M y -Ml oxide
0.S5 pm low temp. CVD oxuic <rf-#iX) “ C
P ulyl
0 40 pm 4?)
M y l-M y 2
0.075 pm ( ’>
^ ^ m i i H i i MyI
04 0 pm i?)
I Field Oxide
0 /x )p m thermally jpuwn <#-H X I)a C
Figure 2.3: Thin films in a standard 2 Metal/ 2 Poly analog CMOS process.
voltage, on the other hand, can not be scaled in proportion to the power supply voltage. Some of
the thermally distributed electrons at the transistor source have energy enough to overcome the
potential barrier controlled by the gate voltage and so to flow to the drain. For a chip with an
integration level of
million transistors, the average leakage current of turned-off devices
should not exceed a few tens of nanoampers. This constraint restricts the threshold voltage to a
minimum of 0.2 V at the operating temperature, which can be 100 °C in the worst case.
CMOS power and performance are largely governed by the choices of power supply and
threshold voltages. CMOS performance is a sensitive function of the ratio of the threshold
voltage to power supply voltage.
The essential features of CMOS devices in the 100-130 nm generation are shallow trench
.5-2.0 nm gate oxide, an n+ and p+ doped polysilicon gate for the n-channel
MOSFET and p-channel MOSFET respectively, a source-drain extension 30-50 nm deep, and
self-aligned contact for contact.
To keep the short-channel effect (the decrease of MOSFET threshold voltage as the
distance between the FET’s source and drain becomes shorter) under control, the gate oxide
thickness is reduced nearly in proportion to channel length. A simple rule is that gate-oxide
needs to be about 1/50 to 1/25 of the channel length. For CMOS channel length of 50 nm (for
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100 nm-drawn) an oxide thickness of 1-2 nm is needed. This corresponds to only a few layers of
atoms. Therefore, the extrinsic factors such as defect density, surface roughness, or large-scale
thickness and uniformity control become very important. In addition, the gate oxide this thin is
vulnerable to quantum-mechanical tunneling, which give rise to a gate leakage current. It seems
that the scaling of the gate dielectric can be continued below 1.5 nm only if the gate-dielectric is
replaced with high-k (dielectric constant) materials, such as strontium titanate.
Of the other technological challenges beyond 100 nm feature size is the lithography. In
recent years, excimer lasers have replaced mercury lamps as lithography light sources. These
lasers are able to operate at 193 nm, as well as 248 nm wavelengths. The newest production
worthy 193 nm lithographic systems are based on light from an argon-fluoride excimer laser.
The next and perhaps the last production-worthy optical lithographic source will be fluorine
lasers. It seems that along with sub-wavelength resolution enhancement techniques, such as
optical proximity correction (OPC), phase-shift masks, and off-axis illumination, these source
can be used to pattern features down to 90 nm. Below 90 nm, the only all-optical lithography
option is extreme-ultraviolet systems, which use laser-produced plasma to obtain 13.4 nm light.
Beside the difficulty in finding a reliable illumination source, the construction of optical
system is a major problem. Because not only coatings on the optical elements, but optical
elements themselves are unique to wavelength. This adds enormous development cost for
successive lithographic systems. Below 70 nm technology node, only reflective systems can be
used since no transmissive optical materials known below 157 nm. Photoresist development for
these feature sizes is another major challenge. Studies are presently under way on applying the
thin-layer imaging to the chemically amplified resists. In short, production-worthy lithography
systems, capable of meeting the industry’s demand down to 30 nm resolution can be realized by
following an all-optical technology, however, many of the critical issues still remain to be
CMOS Micromachining and Classification of Novel Applications
CMOS technology is mainly optimized for digital circuit operation. However, it will be
shown that by simple post-processing, variety of novel devices can be fabricated by using the
same technology. Here, a basic classification of the devices is described. According to their
electromechanical requirements, the devices can be divided into five groups:
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Type I: This category includes devices that require silicon to be present for their operations. It
includes diodes and transistors, and hence all the analog and digital CMOS circuitry. The
active areas of these devices must be unaffected by post-processing.
Type II: This category includes devices that require thermal and mechanical isolation such as
thermocouples, thermopiles, sensors that rely on mechanical or thermal effects (acceleration,
pressure, flow, and orientation), cantilevers, and suspended-beam structures. The substrate
should be removed in certain portions of these devices by post-processing preferably without
additional masking. Additionally, optical devices, such as mirrors and actuators can be
classified mainly under this group.
• Type III: This category includes devices that require good electromagnetic (EM) isolation
from the lossy materials. In order to decrease wave propagation losses due to lossy
dielectrics, type m devices should be post-processed such that no lossy medium is present
closer than a certain critical distance to the EM propagation paths. Furthermore, type III class
devices should be planar. Two sub-classes can be identified as:
• Type Ul-a: These consist of passive microwave devices with fixed response that make the
most of the devices described in literature. All the Si underneath these devices should be
• Type IH-b: These consist of variable response devices whose response can be modified
through a control mechanism. Tunable filters, adaptive microwave circuits, tunable capacitor,
switch etc. belong to this type. Post-processing of these devices require fabrication of good
EM isolation from Si substrate. Additionally, part of device should be mechanically isolated
from all its surroundings to achieve variable response.
• Type IV: This class includes devices used in microfluidic applications, e.g. Microchannels,
micropumps, etc. Usually these devices are fabricated by using a sacrificial layer to form the
desired topologies. Most of the components necessary for a Bio-MEMS system can be
fabricated on CMOS.
Type V: Active microwave circuits, the solid-state laser circuits and acoustic components
need special substrates for operation. The most cost-effective way of integration of such
devices is to use flip-chip technology.
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No etching,
full silicon substrate
,SmaU microwave
(< 0.5mmx0.5mm)
Wet/Dry etch
Partial removal
of silicon substrate
‘Passive Microwave
(20 GHz-60 GHz)
Wet/Dry etch.
full silicon substrate
Wet/Dry etch,
Sacrificial layer + partial
silicon substrate removal
Figure 2.4: By micromachining CMOS, three class of devices can be
fabricated. Type I: Traditional use of CMOS technology. Type II: Sensor and
actuator that can be achieved by simple bulk micromachining. Type III: Passive
microwave devices. Type IV: Micro fluidic devices.
The simplest CMOS micromachining consists only partial removal of the silicon
substrate by wet or dry etching. Maskless post-processing of CMOS has been developed by
Baltes et al. in [4] and later improved by Tea et al. [5] can be used only to fabricate Type-0 class
of devices. The fabrication of type in and type IV devices requires additional processing,
therefore more complicated. These processes have beeen very important to understand the
limitations of the CMOS process and to develop solutions to improve the capabilities of CMOS.
The limitations of the CMOS micromachining are discussed next.
Limitations of the CMOS Micromachining
Even the fabrication of Type 0 devices turns out to be a challenge in many cases, because
CMOS is not developed such non-standard uses. Therefore, most of the thin-films have sub­
optimum performances for sensor and actuator applications. Beside the electrical properties of
these layers, their thermal, mechanical, and optical properties have become important.
Particularly, the high frequency applications need low-loss medium for operation. Two main
problems encountered in CMOS micromachining for RF applications are electromagnetic losses
and stress in CMOS membranes.
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Data Set 1
Data Set 2
Data Set 3
Data Set 4
Data Set 5
CO 30
Frequency [GHz]
Figure 2.5: Coplanar transmission lines fabricated on CMOS silicon substrate. The
data is taken from various CMOS processes available through MOSIS.
Electromagnetic Losses
From RF performance point of view, the quality of the devices fabricated in any substrate
is limited with two types of losses. These are dielectric losses and conductor losses. CMOS
substrate resistivity can be less than 10 and the typical sheet resistances are 0.07 to 0.02
Q/sq. Compared to semi-insulating GaAs substrate, which has the resistivity in excess of
105, the CMOS silicon substrate contributes excessive losses at frequencies above 1 GHz.
Therefore, the partial removal of the substrate underneath the RF devices is essential. Small RF
devices can be fabricated just by front-side etching, (type-II devices). These losses are shown for
coplanar transmission lines fabricated on CMOS substrates in Fig. 2.5.
Secondly, RF devices that are isolated from the lossy CMOS substrate, will be conductorloss limited. Given that aluminum is the dominant metallization until recently, it is a fundamental
limitation for the quality o f the RF devices.
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Differential th<
stress in met;
Intrinsic stress in Oxide
Etched Area
CMOS fabricated die
CM OS fabricated die
Figure 2.6: Thermal and intrinsic stresses contribute to the mechanical
deformations after the release of the CMOS membranes.
Mechanical Stress
One of the unforeseen problems with the CMOS micromachining is that the released
membranes have residual stress that causes buckling and significant failures in the devices.
CMOS thin film materials exhibit residual mechanical stress strongly dependent on the process
sequence and deposition technique used. Mechanical failures, such as cracks, void formation and
hillocks, are detrimental for any applications, but RF devices that are classified in Type III are
especially vulnerable because of their large size. Buckling of the membranes is not desired
either, even if the resulted mechanical profile can be determined beforehand, it is very difficult to
design microwave devices on such surfaces with predicted performance.
The mechanical stress in the layers is first caused by the different thermal expansion
coefficients of the silicon substrate and the deposited layer. This first contribution is usually
called thermal stress. The second stress contribution builds during the deposition, therefore it
strongly depends on the deposition technique. Some of the origins of this stress are volume
changes, phase transformations, recrystallization process, incorporation of atoms, or chemical
reactions. This type of stress is termed intrinsic stress. The determination of thermal and intrinsic
stresses of each layer is difficult and important for stress-compensation discussed in Chapter 3.
In figure 2.6 cross-sectional view of a cantilever after the release is shown. Unless there
is a stress compensation layer, all of the CMOS processes results this kind of stress-induced
buckling. In figure 2.7, a hybrid-processed coplanar flare antenna is shown. Because of the
excessive mechanical failures, the described fabrication is not usable for large microwave
structures [5].
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Figure 2.7: Large scale mechanical failures are fairly common if large RF
devices are fabricated even with silicon supports. Dark areas show the
considerable buckling of the metal films. The composite glass film between the
metal strips is broken in many places.
- Open
Mel a I
Mel a
Figure 2.8: Thin-glass membrane is so brittle that it cracks during the dry
etch cycle under its own stress, if it is not compensated.
The thin-glass films are closely monitored during the fabrication to determine the
initiation of the cracks. Figure 2.8 shows these cracks in the glass-membrane during the dry
etching cycle.
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Patterned polysilicon features are used for sensing, actuating or electrical resistor
purposes. Arguably, it is one of the most functional layers available in CMOS technology. Its use
in MEMS technology is important because of its piezoresistive properties. Many applications
that depend on the polysilicon performance for their functionality suffer inconsistencies due to
process variations and non-linearities. The process-dependent variations makes polysilicon is one
of the most difficult films to characterize.
In RF and microwave applications, the primary function of the polysilicon is to provide
the desired electrical resistance. A good 50 Q termination should have less than 1% inaccuracy.
It is very difficult to obtain such accuracy level if a typical CMOS process has ±10% deviation
from the mean value of the sheet resistance at DC.
The change of the sheet resistance as a function of temperature, mechanical stress and
power is also very serious problem. Change as high as 100% from the initial resistance value has
been observed in the experiments when more than 0.5 W of power is applied to micromachined
polysilicon resistors. Furthermore, depending on the temperature distribution and the maximum
temperature, the applied signal may cause localized annealing, which changes the sheet
resistance permanently. The annealing continues if high power levels are applied.
Polysilicon is very useful film, but it must be characterized for each application and the
process variations and nonlinearities must be compensated.
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A novel MEMS fabrication technology, which is termed as CMOS-based Monolithic
MEMS technology, is developed. The inherent limitations of the CMOS process are significantly
improved in order to be able to integrate sensing, actuating, computing, and communicating
functions in monolithic environment. Figure 3.1 illustrates cross-sectional view a completed
CM-MEMS chip. In this chapter, each of the steps is discussed in detail to fabricate such a
structure. In many steps, the preferred approach of fabrication is characterized and compared
with alternative techniques.
The MEMS fabrication methods used in this process are as follows:
. Thick film processing: In traditional semiconductor processing the thicknesses of the films
deposited and patterned is rarely thicker than 3 pm. However, in MEMS structures with
thicknesses 5 |im to 50 fim are regularly used. Patterning high-aspect ratio structures is
achieved by using special type of photoresists. These photoresists are used to pattern features
as thick as
mm with aspect ratios up to
1 0
:1 .
2. Surface Micromachining: The most common technique to fabricate suspended beams is to
use a sacrificial layer, on which the beams that will be suspended are patterned. The
sacrificial layer is later selectively removed by a dry or wet etching to release the beams.
Sacrificial layers are deposited by various thin film or thick film deposition techniques [6 ]
and it can be almost anything available in the semiconductor fabrication from photoresist to
metallizations and dielectric layers used between the metallizations.
3. Bulk Micromachining: This term is used when the substrate, on which several thin and thick
films are deposited, is selectively removed by dry or wet etching methods. The etching
systems vary with the substrate. Bulk micromachining systems available for silicon can be
classified in two groups: isotropic and anisotropic systems. Isotropic processes progress with
equal rate in all directions, but in practice etch rates are not always entirely omnidirectional.
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Isotropic processes tend to produce structures with rounded features. The most common
isotropic etchant used in the industry is xenon difluoride (XeF:). On the other hand,
anisotropic process tend to progress in a preferred direction and produce features sharply
defined features in the vertical direction. Three popular systems for wet anisotropic systems
are tetramethyl ammonium hydroxide (TMAH), potassium hydroxide (KOH), and ethylene
diamine pyrochatechol (EDP). There are two very popular dry anisotropic etchant systems
are SF6 plasma and deep-reactive ion etching (DRIE).
4. Electrodeposition (electroplating): An inexpensive way of depositing thick metal structures
with low-residual stress on a specified surface. For gold structures, electroplating is the only
way to deposit thick (>3 (im) layer at specified locations.
5. Stress-compensation: This is not generally thought as a MEMS fabrication method, but the
use of CMOS necessitates the use of a stress compensation for proper fabrication of large
suspended membranes. Stress compensation can be obtained by using three different
techniques: substrate bonding, low-temperature silicon nitride deposition and
temperature curable thick film deposition.
Overview of CM-MEMS Process Flow
CMOS-based monolithic MEMS technology consists of 4 mask processing after the
completion of standard CMOS process. It includes 10 processing steps. The enabling processing
micromachining and bulk micromachining. The processing steps are summarized as follows:
1. 2 Metal/ 2 Poly CMOS layouts and complementary 4 masks are designed.
1.1. CMOS part is fabricated through MOSIS in a standard CMOS foundry.
1.2. The complementary masks are fabricated through an independent mask maker.
2. Cavity definition
2.1. Use complementary mask #1 to pattern thick-film photoresist (TFPR).
3. Seed layer formation
3.1. In-situ cleaning aluminum oxide (AI2 O3 ) by using focused argon ion beams to get high
quality electrical contacts.
3.2. Chromium (Cr) is evaporated.
3.3. Gold (Au) is evaporated.
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Pom m ide
Air Givttv
Figure 3.1: Cross-sectional view of a chip fabricated by the CMOS-based
Monolithic MEMS technology.
4. Electroplating masking
4.1. Define the regions for electroplating by using complementary mask #2.
5. Electroplating
. Strip off the second thick film photoresist and etch exposed seed layer.
7. Screen-print thick, low-k polyimide EPOTEK 600. If necessary glass mount the chip with
additional steps. Patterning is performed with Mask #3.
. Prepare for bulk micromachining.
8.1. Backside alignment.
8.2. Thin film patterning of the backside by using complementary mask #4
9. Etch the exposed silicon by using XeFi and finish with anisotropic etchant.
10. Remove the sacrificial thick film photoresist deposited in the 1st step from the backside
(surface micromachining).
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Figure 3.2: CMOS fabricated chip or wafer with an open area for silicon micromachining.
Step 1: CMOS Fabrication
The first step is the fabrication of electronic circuits and passive networks, which later
will be released by surface or bulk micromachining. For consistent performance, it is necessary
to have a fabrication process that yields have less process variations not only in terms electrical
properties but mechanical and thermal properties of the thin films. Since the goal is to use the
same layers for new purposes, many properties of these films that have not been considered
before must be known beside their geometrical dimensions. For a microsystem that employs
thermal, mechanical effects as well as some fundamental material properties such as
piezoresistivity, characterization of related properties is essential. The CMOS foundries provide
only a small set of electrical properties of films. Therefore, the designer must first determine the
necessary properties of the composite films, before starting the design of the microsystem. For
microwave designs, the electromagnetic properties of the films such as resistivity, dielectric
constant as well the geometrical dimensions are important. The high frequency characteristics of
polysilicon-resistors, as well as their thermal and mechanical properties are important for
microwave designs. There are some devices, such as thermal actuators described in Chapter 5,
that require thermal, mechanical, material and electrical properties of the all layers used in the
Two different analog CMOS fabrication processes are utilized in this work. The initial
designs are fabricated in 2.0 pm double poly/double metal technology. When this process is
phased out, 1.2 pm double poly/double metal analog CMOS technology is used. In Fig. 3.2, a
cross-sectional view of a CMOS die is illustrated. In this figure, the area referred as open is
fabricated by several vias stacked in interlayer dielectric layers to form an access hole to silicon.
This is essential to remove the silicon substrate from the frontside of the chip. Therefore, they are
particularly useful for maskless processing described in [5].
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Figure 3.3: Patterned 1st layer of TFPR.
rpm (thousands)
Figure 3.4: Spin curve for AZ-P4620.
Step 2: Deposition of thick film photoresist (TFPR-1)
Thick film processing is necessary in fabrication of type n, Hl-b, and type IV devices on
CMOS. The first layer of thick film photoresist (TFPR) is used to define cavities required the
operation of these devices. In many cases, the first TFPR is used as a sacrificial layer, therefore,
it is placed on top of open areas as shown in Fig. 3.3
Two different TFPRs are investigated in this work. First, AZ-4562 TFPR (by AZ
Electronics, Inc.), which is obtained from Germany is characterized on 4 inch wafers. This
special TFPR gives extremely smooth surfaces compared to the other commercial TFPRs
because of a special solvent. On the other hand, AZ-P4620 (by AZ Electronics, Inc.) includes a
safer solvent, and more readily available. Mainly because of safety concerns, in spite of inferior
resolution and roughness, AZ-P4620 is chosen as the primary TFPR in this process.
The spin curve for AZ-P4620 is given in Fig. 3.4. These thicknesses are measured by
using Wyko RST-Plus (Veeco Inc) non-contact profiler after a thin layer of gold is evaporated on
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top. It is observed that the thicknesses are hard to repeat at low rpm levels (<1500 rpm). Even for
wafer processing, spin rates higher than 2500 rpm are favored. Thicker coatings up to 50 pm can
be achieved simply repeating the single-coat procedure.
In general, photolithographic processing of a single die is significantly more difficult and
less repeatable compared to wafer level processing. The problems stem from the fact that the dies
should be handled manually during every step, whereas the wafers usually handled with special
equipment. Additionally, the uniformity of the photoresist film is degraded due to edge effect.
Minimization of edge beads can only be accomplished by increasing the spin speed, hence
decreasing the film thickness.
Several thicknesses are investigated for the first TFPR film between 5 (im and 15 Jim.
Films thicker than 7 pm are spun in two steps. Each coat is prebaked at 100 C for 200 sec. The
films are exposed with an UV source and developed with AZ-K400 developer. For maximum
resolution, edge beads are exposed separately. The exposure time increases with thickness. As a
rule of thump, for 10 pm thick films require 400 mJ/cm 2 exposure, whereas edge beads usually
require more than one order of magnitude more exposure.
Figure 3.5 shows the profile of the TFPR-1 for one of the novel devices that are
fabricated with this procedure. It shows that the thickness varies ±1 pm in 150 pm extent. One of
the reasons why the roughness is this large, is the roughness of the starting surface. The finished
CMOS surface can have steps as high as 5 pm, if none of the planarization techniques, such as
chemical-mechanical-polishing (CMP), is used.
Figure 3.5: A typical TFPR-1 profile of tunable capacitor (#7).
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Figure 3.6: Cr-Au evaporation
Gauge' r®°n Monitor
Ion Gun
Turbo Pump
Position and
Angle Control
Gold Chromium
Figure 3.7: In-situ cleaning and seed layer deposition setup.
Step 3: Deposition of Seed Layer
It is known that direct deposition of gold (Au) over aluminum (Al) metallization does not
work for several reasons. The adhesion between the two metals is very poor because of the
indigenous aluminum oxide. The same oxide would increase the contact resistance between the
two metals. Secondly, direct contact between gold and aluminum results in the formation of
brittle alloy, AT-Au. The formation of this compound is known in the semiconductor industry as
the "purple plague" which is said to reduce the yield of the devices in some cases. For this
reason, commercial integrated circuits with aluminum metallization are rarely wirebonded with
gold bonding wire.
Formation of the gold/aluminum alloy can be prevented by sandwiching a barrier metal
layer such as chromium between metals. Therefore, the deposition of seed layer, as illustrated in
Fig. 3.6, consists of three steps: cleaning of aluminum pads, deposition of chromium as barrier,
and deposition of gold. The goal is lower the contact resistance to less than 0.1 Q for a 40 x
40 pm area.
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Because the test chips were in storage more than
months, the surface of the bonding
pads was contaminated with unspecified organic material and the aluminum oxide was
approximately 200 A thick [7]. First, the organic impurities were removed in an UV-ozone
cleaning system for 30 min.
The removal of the aluminum oxide can be accomplished chemically or mechanically.
Usually, the oxide etch solution is buffered oxide etch (BOE) which is made from 13 parts of
NH4 F (40%) and 2 parts of HF (49%) by volume and mixed with glacial acetic acid in the
volume ratio of 3:1. This wet etch solution is not very selective to aluminum, so caution is
required, general practice is to clean of I min [7].
Selectivity of the etchant is especially important for contact pads in CMOS. In the trials
by using diluted BOE, most of the pads were severely damaged. Since the aluminum films are
very thin (most cases less than 1.1 pm), a better control is required during oxide removal. This is
one of the main reasons why mechanical etching is used in this work. The second important
reason for this choice is the re-oxidation of aluminum pads, after the cleaning. This can be
prevented in mechanical etching by integrating evaporation into the same setup. Therefore, an
experimental in-situ cleaning and evaporation setup has been constructed. This setup, shown in
Fig. 3.7, is crucial to get good electrical contacts, however, there is a concern that even lowenergy ions might damage sensitive channels of CMOS transistors. Extra precaution is taken
over the active circuit areas by a thick TFPR-1 film. By using this procedure, very high quality
contacts are obtained between the aluminum contact pads and gold layer.
Barrier metal
Several metals can be used as a barrier metallization between aluminum and gold. Nickel
(Ni), titanium (Ti) and chromium (Cr) are preferred for their specific properties. Nickel is usually
favored for electroless deposition techniques. Several commercially available plating solutions
usually require strict control of pH and temperature of the solution. Trials with electroless plating
solutions show inconsistent results on MOSIS fabricated chips. In most of the cases, the plating
solution attacked severely to aluminum pads.
A better deposition technique is the evaporation of desired metals. This gives uniform
coating, better thickness control and more repeatability. Furthermore, evaporation is compatible
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Figure 3.8: Second layer of TFPR is used as a mold for electroplating.
with dry cleaning. Thus, it is possible to clean the surfaces and evaporate the barrier layer
without breaking the vacuum. In this work, chromium (Cr) is used as a barrier metal between Al
and Au. 75 to 250 A thick Cr is evaporated after surface cleaning. In thick-film processing, the
steps that should be covered with such thin films can be more than 25 |im high, it is vital to have
good coverage even in extreme cases.
Approximately 800-3000 A thick gold is evaporated by using the setup shown in Fig. 3.7.
Again, the step coverage is very important for the electroplating step. Therefore, thicker values
should be preferred.
Step 4: Deposition of TFPR-2
The seed layer is used to electroplate much thicker gold strips on the chip. Unlike
conventional photolithographic techniques, the electroplating procedure requires a mold to
define the patterns. The mold restricts the chemical reaction to specified areas, where the seed
layer is in contact with reactants. For molding purposes, TFPRs are commonly used. To achieve
successful deposition of thick films, the photoresist and seed layer must be inert to the plating
solution. Currently, only cyanide and sulfite-based, gold-plating solutions are available
commercially. However, research for new gold electroplating systems is still an exciting field
and new systems with superior plating properties are underdevelopment [8 ].
This step, illustrated in Fig. 3.8, usually requires thicker photoresist layer then the first
one (TFPR-1) irrespective to the electroplating constraints. Therefore, multiple-coats of AZP4620 are used for this purpose. The thicker the mold, the lower the resolution, because of the
limited aspect ratio that can be obtained with AZ-P4620.
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Electroplated Gotd
Figure 3.9: Gold electroplating
Cathode: Copper base
Anode: Platinum
Plating solution
Hot plate/stirrer
Figure 3.10: Electroplating setup.
Step 5: Electroplating
Electroplating is necessary to deposit thick films of gold on CMOS chips. The electroless
deposition and evaporation of gold are limited to thicknesses less than 1 pm. Although using
sputtering it is possible to deposit thicker films, in many cases, it is not practical because of cost
and contamination problems. On the other hand, as illustrated in Fig. 3.9, gold films as thick as
25 pm can be deposited fairly easily by electroplating. Additionally, it is known that
electroplated noble metal films have lower stresses than sputtered films, due to larger grain sizes
[9], [10].
Cyanide based plating solutions, such as Transene SG-1 (by Transene, Inc.), require
special handling. The substance inhibits cellular respiration and may cause blood, central
nervous system, and thyroid changes. Furthermore, it has been reported that gold cyanide
solutions may penetrate the photoresist and, as a result, cracking or dissolution of photoresist
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may occur. In comparison, gold-sulflte plating solutions are not sensitive to the photoresist,
however this bath gradually degrades during electrolysis.
UltraClad 710, by Ethone-Omi Inc., a sulfite based high-purity gold plating solution is
used in this work. The setup is shown in Fig. 3.10. The current density 40-50 (iA/mm2 at 55-60 C
with 400-500 rpm rigorous agitation the plating rate has been observed as 0.2 pm/min for 50 x
50 pm 2 area, which is almost 15 pm below the surface level. The experiments showed that the
deposition is limited by the diffusion in such small and concealed areas. The cathode is made up
from a platinum plate with an area of 2 x 5.3 mm2.
There are several parameters of the electroplating setup that need to be optimized for a
specific application. One of the difficulties is that the plating uniformity depends on several
factors. Several experiments are performed to determine the optimum plating conditions to
achieve uniform plating. Non-contact interferometric profiler shown in Fig. 3.11 is used
extensively to characterize the experiment results. To demonstrate the severity of the plating
non-uniformity, the surface profile of one of the earliest samples is shown in Fig. 3.12. This
sample is fabricated by evaporating chromium and gold directly on a new silicon wafer.
Patterned 10 (im thick TFPR has 100 x 100 (im open areas spaced by 50 (im. The profiles before
and after the seed layer is stripped are shown for the same sample. These profiles show
significant non-uniformity due to one-dimensional agitation. Similar tests with smaller features
show more uniform profiles, however, the plating at the midpoints strongly depend on the
minimum feature size in the direction of flow. As shown in Fig. 3.13, the plating thicknesses
decrease as feature size gets smaller.
In order to get uniform plating, plating areas exposed to the plating solution must have
equal current density and see equal concentration of reaction species. This condition is rather
difficult to satisfy. Temperature, current density, and agitation controls are equally important.
To minimize temperature changes, the plating solution is placed in a larger water tank
and all of them placed on a hot plate/stirrer. The temperature of the water is read via a
thermocouple and fed to the hot plate. The thermal capacity of the system is too large to be
handled effectively by the hot-plate, therefore in spite of the feedback, manual control is
necessary to keep the temperature of the plating solution in 58±3 °C range.
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Figure 3.11: Noncontact optical interferometer profile characterization setup (Wyko RST plus).
Figure 3.12: Profiles of the gold plated areas.
Minimum dimension (/a n )
Figure 3.13: Concentration differences are evident in small areas.
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There is an additional dimension to non-uniform plating problems related to type of
electrical excitation. Several studies discuss the merits of pulsed and DC type electrical
excitations [11]-[13], However, since the techniques and solutions vary widely the results are
inconsistent. But it appears that the papers favoring the pulsed plating outnumber the papers
favoring DC plating technique. It is feasible to think that the pulsed plating has better masstransfer properties. Pulsed plating trials with the current setup have failed. Additional study is
necessary to find the operating conditions for pulsed plating.
Agitation is vital for uniform electroplating. The simplest of available techniques is to use
a magnetic stirrer to agitate the plating solution. However, this technique is very limited since
creates virtually one-dimensional flow on the surface of the chip. This is illustrated in Fig. 3.14.
Then, the size of the plated area and its placement with respect to the flow becomes important.
The length of the plating pit along the flow, the depth of the pit, the speed of the flow at the top
surface, the angular deviation between the planes of the cathode and anode plates and even other
pits and their sizes relative to the considered pit become important in the final result. The effects
of these parameters were observed experimentally.
Perhaps, the most effective of solution to minimize the non-uniform plating due to nonuniform current distribution is to add a strip of metal around the device to be plated to minimize
the edge effects. A similar technique is adopted in this case, as shown in Fig. 3.15. A copper
plate 8.5 mm x 8.5 mm is machined to hold the experimental chip, which has the dimensions of
5 mm x 5 mm. Chips are wirebonded to the center of this area, therefore giving 1.75 mm-wide
metal strip around the die area for nonlinear current distribution. A similar strip exists on the
chip surface as well.
j Electroplated Gold
Figure 3.14: Plating depends on the concentration of reaction species.
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Figure 3.15: CMOS die to be plated is placed on the copper holder and
corners of the chip wirebonded to the block (a). At the other end the copper plate
is soldered to a special resin-coated wire for electrical connection (b).
Three different techniques were investigated to alleviate the problem. First, slower speeds
of agitation are considered. The speed of the agitation for the setup in Fig. 3.10 is measured in
terms of number of rotations per minute. The slope of plated areas shown in Fig. 3.13 goes down
from 1.5 (im / 100 |im for 500 rpm to 0.5 pm /100 pm for 200 rpm. If speeds lower than 100
rpm, the surface roughness becomes a major problem and the plating rate goes down. Since
increased plating time causes cracks in the TFPR-2 film, it is desired to keep to time less than 20
Secondly, ultrasonic agitation was investigated as a possible agitation technique. For this
purpose, the plating solution is placed inside ultrasonic cleaner, FS140, from Fisher Scientific
Inc. The experiments were unsuccessful because the cleaner does not allow controlling the power
level of the ultrasonic agitation. And the available level of the power was so high that in less than
5 minutes the TFPR-2 films are locally (at cavitation points) removed. This is still a feasible
technique at low power levels with a proper ultrasonic source or sources.
It is possible to achieve uniform plating profiles by using magnetic stirrer by controlling
the speed o f the rotations and the angle between planes of the electrodes. While the speed is
varied between 200-500 rpm, the angle is changed between -45° and 45° for every two minutes.
This technique gives less than 0.2 pm / 100 pm slope, smooth surfaces and less than 20 minutes
plating times for 7 pm thick gold.
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Figure 3.16: After the seed layer is removed.
Fundamental assumption in the characterization process outlined above is that the plating
surface planar and similar structures placed relatively far away. However, often enough the real
plating environment do not meet these criteria. The type of plating that usually encountered in
real applications is illustrated in Fig. 9, which requires coating of the vertical walls.
Step 6: Stripping the Seed Layer
Seed layer must be stripped after plating for electrical functionality. This is accomplished
by using wet etching of TFPR-2, gold and chromium. High selectivity of the etchants is desired.
Even if such etchants are available, several factors may cause unwanted damage to other
structures. The stripping completes the fabrication of low-Ioss, high quality metallization that is
much superior to anything available in CMOS. Such low-loss layers are very important for
passive RF devices necessary for mobile applications. The desired levels of sheet resistance is
less than 0 . 0 1 fi/sq.
TFPR-2 is stripped with acetone. If the thickness of the seed layer is less than 1000 A or
its coverage is not good enough, acetone might dissolve TFPR-1 films. Evaporated gold is
stripped by potassium iodide (KI). It has different etching rates for electroplated and evaporated
gold. Because of the non-planarity of the surface longer than normal etching cycles are required
to remove the seed gold film. Finally, chromium is removed with CR-7 mask etchant. During
this step, a severe attack of CR-7 to plated gold and exposed aluminum pads is observed. The
quality of the final geometry is limited because of the selectivity of the wet etchants used during
the stripping process. After chromium etch, plated gold becomes noticeably softer. Probing of
such areas is extremely difficult, and electrical contacts are not reliable and reproducible. Figure
3.16 illustrates the cross-sectional view of the post-processed chip after step 6 .
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Low-k Stress
Electroplated Gold.
Figure 3.17: Low-k polyimide for stress-compensation.
Engelmann et al. has reported similar difficulties by using TiW barrier layer with gold
[14]. They solved these problems by using dry etching. Gold layer can be stripped by RF sputter
etching in an Ar+-plasma. At a power density of about I W/cm2, an etching rate of 30 nm/min is
reported in [14]. Chromium can be etched in reactive ion etching chamber with a proper
chemistry. Dry etching techniques will certainly improve the quality of the final geometry, but
the non-planarity of the surface should be taken into account, since these techniques are
generally anisotropic.
Hirano et al. describes an ion-milling technique to pattern the electroplated gold lines.
The disadvantage of their process is that an additional mask is required [15].
Step 7: Stress-compensation
Fabrication of planar and mechanically robust membranes is very important for
microwave applications. Internal stresses of the CMOS films that comprise the suspended
membrane is large enough to cause mechanical problems, especially in large (>
2 0 0
2 0 0
membranes having only SiOi layers. Even in successfully suspended structures, the membranes
buckle, which complicates the design of high-frequency devices such as coupled lines with very
small spacing. Furthermore, the internal stress in the individual standard CMOS layers has been
a reliability issue for a long time [16]-[21]. Many measures have been taken to minimize this
stress to improve the reliability in recent CMOS processes. Despite these efforts, the internal
stresses in these layers remain considerably larger than what is required for robust planar
suspended membranes with large areas. These problems are solved by depositing a stress-
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20 pm
-10 pm
20 (xm
0 (im
Figure 3.18: Interferometric measurement of a distributed filter.Without
stress compensation, fragile parts of the CMOS membrane mechanically fail
during fabrication.
compensation layer on top, prior to the release of the beam by bulk-micromachining. Fig. 3.17
shows one type of compensation used in fabrication.
Figure 3.18 shows the failure mechanism in uncompensated suspended membranes
fabricated by the procedure described in [5]. After anisotropic etch step virtually all large
microwave components become un-operational. Fig. 3.18 shows fairly typical fabrication results
of this procedure. Internal stresses are still important for small structures such as thermopiles.
Yield rate of polysilicon thermopiles is practically zero, without using any stress-compensation.
Three different methods have been investigated for stress-compensation of the suspended
membranes. They are illustrated in Fig. 3.19. In the first one, a superstate is bonded adhesively
over the area that will be suspended [19]. The superstate is can be any low-loss microwave
material. In our trials, different types of glasses are used as a superstate. The first samples of
integrated multi-purpose power sensors are fabricated by using this procedure. As can be seen
Fig. 3.20, 150 p.m thick glass substate is placed on microwave components (antenna, matching
network, filter and termination), minimizing the unsupported suspended area required for power
converter. Several of these fabrications were carried out and packaged in DIP packages as shown
in Fig. 3.20.
CMOS Membrane
Figure 3.19: Techniques employed for ste ss compensation.
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Figure 3.20: Compensation with glass superstate bonded on the area to be suspended.
The compensation by bonding a superstate is not attractive since it does not lend itself
for mass-fabrication. In many cases, special adhesives should be used for bonding since their
microwave properties are important. This leads to investigation of the other two stresscompensation techniques. The second technique shown in Fig. 3.19, first described by Jaeggi et
al. [20]. They have done detailed study of stess compensation by using carefully deposited
silicon nitride (SiN) to put the suspended membrane under tensile stress. A similar study has bee
pursued in this work, as well. Fig. 3.21 shows the fabrication of the same system compensated by
a 3.0 (im thick PECDV deposited SiN film. The deposition rate at temperature 350 °C is
97°A/min. The deposition is performed in a gold-contaminated furnace at the Stanford
University Nanofabrication Facility through MEMS Exchange service. Detailed examination of
the Fig. 3.21 reveals that even large membranes can be fabricated without any mechanical
failures, however, even the maximum allowed thickness is not enough to compensate the internal
stress present in the CMOS membrane. Multiple coatings are necessary for the 1.2 pm CMOS
Figure 3.21: Compensation with PECVD SiN layer deposition.
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Another way to obtain mechanically robust membranes is to use single layer thick
coatings that can be screen-printed on the membrane area. This is advantageous because
compensation with thin SiN films require one high-resolution mask to obtain electrical contacts.
However, if the compensation is performed by screen-printing than film can be deposited on the
membrane area only, eliminating the need for additional high-resolution mask. The size of
membranes needed for microwave purposes is usually large ( >1 mm x 1 mm) and resolution of
screen-printing (10 pm feature size and 20 pm placement accuracy) is adequate. Therefore,
stress-compensation by screen-printing is more cost-effective compared to thin-film techniques.
In this post-processing procedure, the use of thick film stress-compensation is
advantageous. Particularly, it is necessary to have large cavities for the operation of the some of
the devices, such as tunable capacitors, switches and microfluidic components. A thick layer can
perform various functions besides stress-compensating the large CMOS membranes for
microwave operation. It might be used to fabricate reconfigurable microwave components by
supporting an additional layer of metallization. It is possible to have high quality gold plated
microfluidic structures supported by this layer to fabricate microfluidic devices or sensors.
Epo-tek 600 (by Epoxy Technology, Inc) is preferred as a compensation material because
of its excellent electrical and mechanical properties. Several thicknesses of polyimide (Epo-tek
600 is a polyimide based film) are experimented varying from 20 fim to 1 mm. As expected,
increasing the film thickness causes curing problems. If the recommended curing cycle ( I hour
prebake at 150 °C followed by 30 minutes final cure at 275 °C) is used for the film thicknesses
above 300 pm, the stress-generated cracks are observed. The optimum thickness of the
polyimide film varies with the application, nonetheless, for most of the microwave circuits that
does not contain any microfluidic components, the optimum thickness is found to be 200 pm.
Without any change in the curing procedure, we are able to obtain smooth, uniform, pin-hole and
crack free polyimide films on CMOS chips by multiple coatings. Each coating is cured with the
same procedure described above. Electrical properties of the polyimide changes with processing,
therefore curing procedure should be followed closely to obtain the same properties. A good
fabrication should yield films with dielectric constants as low as 2.4. Low dielectric constant
films are desirable for low-dispersion microwave propagation.
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Dielectric Constants
Loss Tangent (@ 1 MHz)
Curing Temperature (°C)
Breakdown Voltage (V/cm)
CTE (ppm/°C)
Thermal Conductivity (W/m °K)
Residual Stress (MPa)
Tensile Strength (MPa)
< 30
Film Thickness (jxm)
Table 3.1: Comparison between polyimide and BCB dielectric films.
Polyimides are high temperature engineering polymers originally developed by the
DuPont Company. When compared to most other organic or polymeric materials, polyimides
exhibit an exceptional combination of thermal stability (>500 °C), mechanical toughness and
chemical resistance. Because of their high degree of ductility and inherently low CTE,
polyimides can be readily implemented into a variety of microelectronic applications. DuPont
Pyralin series and Epo-Tek 600 are popular in stress-buffer coating of silicon wafers.
There is another class of polymers derived for low-k microelectronics applications. The
Cyclotene series by Dow Chemical Company are derived from B-staged bisbenzocyclobutene
(BCB) chemistry. They are particularly good for thin film applications such as interlayer
insulators. Both of these materials are investigated because of their low dielectric constants,
which is desired for microwave applications. A brief comparison is included in Table 2.1.
Step 8: Backside Patterning
The backside of the silicon is patterned by using standard photolithographic techniques.
Shipley 1813 positive photoresist is used in the backside patterning and in the frontside
protection during etching. Spinning speeds higher than 5000 rpm are used during the preparation
of the samples. The polyimide film should be protected by using multilayer coating. A simple
photolithographic preparation described here and illustrated in Fig. 3.22a is good enough for
bulk micromachining with xenon-difluoride (XeFi). If wet type of bulk micromachining is
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L o w -k Stress
C om pensation
L o w -k S tress
C om p en sation
Electroplated Gold
B ackside
O pen
1 S ilico n
C ontact Pad
M ask
Figure 3.22: Before (a), and after (b), bulk micromachining of the silicon.
needed than appropriate protection should be provided for the necessary parts of the die. For
example, silicon etching with tetramethylammonium hydroxide (TMAH) cannot be performed
with a photoresist masking. Low temperature oxide should be used as a mask in TMAH. It is
also known that polyimide film reacts with TMAH solution, therefore, those regions with
polyimide films should be well protected. XeFi pulse etching [19] is very simple and highly
selective for silicon. The only downside of this method is that it is isotropic and therefore it is
harder to control the etching profile with the increased surface roughness during long etch
cycles. Surface roughness during 400 |im substrate etch limits the resolution to 20 pm feature
size. Deep RIE systems with SF6 chemistry is a better approach if high accuracy and resolution is
Step 9: Bulk Micromachining
The chip is placed in one of the XeFi-etching stations shown in Fig. 3. 23 upside down to
etch the exposed silicon. Depending on the area and the volume of the exposed Si and the pulse
parameters, backside etching might take from 30 minutes to a few hours of etching (see [19] for
pulse-etching with XeF2 ). This step of the process is illustrated in Fig. 3.22b. During backside
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Figure 3.23: Block diagram of the etching system.
Figure 3.24: Xenon-difluoride (XeFi) etching stations.
etching, all of the silicon underneath the compensated area is removed. This exposes the
sacrificial photoresist and electrical contact pads accessible from the backside.
At room temperature, XeFi has a sublimation pressure of about 4 Torr. The gas will form
HF in the presence of water vapor, therefore proper ventilation is necessary. The reaction
between silicon and XeFi is given below
2 XeF2 + S i - * 2 X e + 5/F4
The etch appears to have very high selectivity to common thin films including silicon
dioxide, silicon nitride, photoresist and aluminum. The basic block diagram of the etching
system is shown in Fig. 3.23. It consists of a two stage mechanical roughing pump, stainless steel
or aluminum etching chamber, a capacitive pressure gauge, pneumatic valves a needle valve. All
the pneumatic valves are controlled with a computer. The XeFi is metered by using a pressure to
the etching chamber. Typical XeFj fill-in duration is less than 10 sec, but it depends on the
etching chamber. Two custom built systems used for silicon etching are shown in Fig. 3.24. One
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L o w -k S tress
C o m p en sa tio n
Electroplated Gold
p acj R elea sed
■ S ilic o n
Figure 3.25: Sacrificial photoresist TFPR-1 is removed to release small membranes.
of these systems has a 4 inch wafer processing capability, thus a large etching chamber. The fillin time for this chamber is more than 45 sec. It is desirable to have an etching chamber
comparable to sample size to predict the efficiency of the system accurately.
Both of the systems shown in Fig. 3.24 are optimized for CMOS die processing. It takes
approximately 130 of 2 Torr-pulses of XeFi to etch 4.7 mm x 4.7 mm CMOS chip completely.
Each pulse is 200 sec long including the fill in time.
Step 10: Surface Micromachining
Fig. 3.25 illustrates the last step of the process. In this step, the sacrificial photoresist
deposited in the 2nd step (TFPR-l) is removed through open holes in the CMOS membrane. One
of the unique features o f this process is that it allows the fabrication of various types of sensors
and actuators. This step assures the integration of these low-frequency components. Arguably,
this step might be the most important innovation brought to the fabrication process. The crosssectional view of the CM-MEMS chip is illustrated in Fig. 3.25.
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Integration and Packaging
Integration of chips at the system level and their packaging can no longer be considered
independent from the low level fabrication outlined above. Therefore, during the development of
the CM-MEMS technology, especially the integration issues are taken into account.
The CM-MEMS technology allows the integration of all the first four types of devices on
a single CMOS die. However, low electron mobility in silicon prevents the high frequency
operation of active devices in this medium even the state of the art photolithographic technology
is used. On the other hand, by using silicon-germanium heterojunction bipolar transistor
technology (SiGe-HBT) transistors with 90 GHz transit frequency (J'r) and maximum oscillation
frequency (ftmLr) have been demonstrated [22]. This level of performance has been achieved by
using standard CMOS processing tools integrated with CMOS devices. Although post­
processing of these dies are also possible with proper choice of etchant systems, we believe that
because of the cost considerations integration of such specialized chips with CM-MEMS
fabricated chips more cost-effective.
Flip-chip integration of active microwave components have been studied as one of the
most processing integration methods at high frequencies [23]-[25]. Based on these studied
several systems have already been announced. Presented technique is can easily altered to
incorporate flip-chip integration of active devices. Most of the techniques use electroplated gold
bumps to bond two substrates together. And usually electroplating requires additional
processing, therefore increase the cost of the fabrication, however, proposed process already has
electroplating step (#5). This eliminates additional cost for integration. Although it is not shown
in this work, the flip-chip integration of SiGe or GaAs based circuits can be done after step 6 and
before step 7. Necessary underfill must be carried out multiple times to fill the large air gap
because of existing TFPR-1 areas underneath the integrated chip. Similarly, other special chips
can be integrated with the micromachined CMOS chip in similar manner.
Fabrication Example: Tunable Capacitor
Detailed fabrication of a novel thermally actuated tunable capacitor is described. High
quality tunable capacitors are especially important for voltage controlled oscillators as described
in Chapter 5.
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Figure 3.26: Layout of the tunable capacitor (a) and fabricated device (b).
Figure 3.27: TFPR-1 patterning in step 2 (a), TFPR-2 patterning in step 4
(b), mask for screen printing of polyimide in step 7 (c), and mask used in backside
patterning step 9 (d).
E vap o rated
Figure 3.28: After step 2 (a) and step 3 (b).
The capacitor is designed by using 1.2 |im 2poIy/2metal CMOS technology. Final layout
of the device is shown in Fig. 3.26a. The fabricated devices include open holes necessary to
remove sacrificial TFPR-l layer. All the contact pads shown in Fig. 3.26b are two sided, that is
accessible from both sided of the CMOS membrane after silicon etch. Four low-resolution masks
used for post-processing are shown in Fig. 3.27. For this device, screen-printing mask is not
used, therefore the 3>rd mask does not have any features.
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Figure 3.29: 3D surface profile after step step3 obtained by non-contact
optical interferometer. Fig. 3.5 shows the 2D profile of this device, the average
thickness of the TFPR-l with is 11.1 Jim.
In step 2, two coats of AZ-P4620 are patterned by using the mask in Fig. 3.27 and
developed in 2:1 diluted AZ-400K for 45 sec. The thickness of this layer defines the spacing
between the parallel plates.
In situ cleaning is performed with IkV argon ions for 15 min. Since the beam diameter is
smaller than the total chip area, beam chip should be scanned. Then, 120 °A barrier material,
chromium, is evaporated. Fig. 3.28b shows the device after 3000 °A gold evaporated as a seed
layer for electroplating. Since whole top surface of the chip is covered with gold, accurate
interferometric reading of the 3D profile can be obtained. 3D model of the surface of the device
after 3rd step is included in Fig. 3.29. This shows very good TFPR-1 profile with average
thickness of 11.1 fim.
In the next step, the second layer of TFPR is spun and patterned by using the mask in Fig.
3.27b. In this step, it is important to have features on the vertical walls of the TFPR-1 be defined
clearly. This is extremely difficult to detect by using optical means because of a limited depth of
field in optical microscopy. Therefore, longer than normal exposure times should be used to
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P h o to r e s is t
M o ld s ..
Figure 3.30: Patterned second TFPR, which is used as a mold during in 5Ih
step, is shown. Microwave and dc-bias contact pads are also exposed.
Ev a p o t a t e d
Figure 3.31: If electroplating is longer than 30 min and the solution
temperature gets hotter than 65 °C, cracks in the TFPR-2 are observed (a). In 6th
step, TFPR is stripped with acetone (b), Au and Cr are etched by using KI and Cr7, respectively (c).
Electroplated system after 5th step is shown in Fig. 3.31a. As indicated earlier, high
temperature and long plating cause cracks in the thick photoresist. Plating in these cracks have
been observed in some cases. After TFPR-2 is stripped with acetone, the plating is characterized
with Wyko Optical Profiler system. Fig. 3.32a shows the measured surface profile of the device
after plating. An acceptable level of uniformity is obtained on the plated surface, with average
thickness 5 pm. On the other hand, the Metal2 contact area has average of 2 pm thick gold
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plating. Then, gold and chromium are stripped to isolated the devices electrically. At the end of
step 6th, the device is shown in Fig. 3.31c.
In the step 7, first the 100 pm thick Epo-tek 600 film is screen-printed by using the mask
in Fig. 3.27c. After it is cured, another coat of film is deposited, but this time is cured with a
glass superstrate attached. Bonding to an additional superstrate is usually preferred in lab
environment because it simplifies handling and eliminates difficulties encountered during
The backside of the chip is patterned by using Shipley 1813 spun at 5000 rpm and the
final mask in Fig. 3.27. Then, the exposed silicon is etched from the backside by using a XeFietching station.
Fig. 3.32b shows the released thermal actuated fixed-fixed beam after 10th step. The
detailed description of this device is described in chapter 5.
448 3 «|
2500 j
3000 J
2500 |
.'000 J
‘500 J
’000 j
-10 00
500 J
00 J
200 0
200 0
400 0
500 0
250 0
283 1
Figure 3.32: The plated gold ischaracterized with optical profiler prior to
Au/Cr stripping (a). If the reflection values from evaporated and plated gold
surfaces are assumed the same, the top
plate is 5 (imthick where as the contact at
the signal line is plated 2 |im thick. Profile of the released beam after final step
(b). This reading is taken from the backside of the tunable capacitor.
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Reconfiaurable Antennas
• Multi-frequency
• Phased-array
H ia h -0 Micromachined
• Inductors
• Transmission Lines
• Couplers, Dividers
N ew Components
• Switches
• Tunable Capacitors
• M echanical Filters
SPD T Switch
! Switches
Mech. '
Reconfiaurable Passive Networks
• Filters (Lumped, Distributed)
• Reconfigurable M Ns
• Phase Shifting Networks
A ctive M IC’s
(GaAs. SiG e. SiC...)
• LN A , Pow er Amps
• Mixers
• VCOs
Active CMOS
A D C /D A C
performance operation of RF and microwave applications.
' P hysical ( pow er, orientation, acceleration,
P olyim ide
• Protection
pressure, temperature, etc)
1C hem ical (g a s, hum idity, etc)
• M icroFluidic
system s
Convective ] Gas Sensors
Accelerometer 1 - IR Pixel
- Tilt sensor
MicroFIuidtc Systems
t;----£— j
’ Reservoir jI
- Microreactor
B io-M E M S
• B iosen sors
• B iotelem etry
S ilico n
• T herm al path
• A ctiv e d ev ices
• D rug delivery
and d iscovery
Figure 3.34: RF-CMOS-MEM process is ideal for low-frequency
electronic, microfluidic, sensor and actuator applications.
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Generally, functionality and complexity of MEMS processes are strongly related. The
development of highly functional processes is a non-trivial task. In many cases, a well-developed
process is considered as a module and it is combined with similar process modules to obtain a
more complicated process. This can be done either by interleaving the individual process steps
from several process-modules or by sequentially performing the process for each process
independently. The most successful example of sequential combination of process modules is the
Sandia National Lab’s Modular Monolithic MEMS process (MJS) [1]. However, MJS is
inherently for low-frequency applications, since it does not have any low-loss microwave
propagation medium.
The CM-MEMS is the first process that combines the high frequency and low-frequency
applications in one process. Figure 3.33 summarizes the high-frequency applications. Two main
applications are "wireless communications" at 0.8-3.0 GHz frequency range and "microwave and
millimeter-wave communication applications", such as satellite, local multipoint distribution
system (LMDS), phased-array communication systems. The advantages of this approach over
M3S are listed as follows:
1. Low-loss propagation at very high frequencies.
2. Cheaper compared to MMIC-base approaches.
3. No additional integration cost.
4. High quality novel passive devices, such as tunable capacitors, switches, tunable
filters, mechanical filter etc.
The advantages are especially significant for mobile communications. This process solves all the
major hurdles encountered in the superheterodyne transceiver system. It has become possible to
develop the first single-chip transceiver with the CM-MEMS technology, which can drastically
lower the cost of cellular system. Part of this success is attributed to the ability of having lowfrequency circuits inherently integrated with other components. The low-frequency components
are analog and digital CMOS electronic circuits that operate at the baseband.
The second major advantage of this process is the integration of sensors asshown in
Fig. 3.34 . This is a very active field of research and
has a very high potential
Particularly, if sensors in biological systems are considered, the area is very new. There are
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several very important applications, such as bio-telemetry, drug delivery and discovery. The
integration of powerful electronics with such bio-MEMS systems is crucial.
In order to show the capabilities of the CM-MEMS technology, several components are
discussed in Chapter 4 and Chapter 5. From fabrication point of view, the presented fabrication
procedure can be further improved to improve the minimum feature size and the aspect ratio in
CMOS layers, and in additional gold layer. As it has been pointed out several times, wet etching
steps are not selective enough for the devices with features smaller than 2 jim. Thus, these steps
should be replaced by dry etching procedures. This work should be considered as a proof-ofconcept. The developed fabrication can be tuned for the specific requirements of the application.
For example, the depth of the air-cavity defined by the thickness of the TFPR-1 should be
available to the designer as one of the design parameters. From this point of view, the CMMEMS is a significant deviation from the standard practice adopted by the CMOS fabrication
industry, in which the designer has no control in cross-sectional dimensions of the thin-films.
However, it is obvious that these new applications require these changes. In addition, the ability
of defining several different thicknesses of the TFPR-1 in the same wafer, which is not possible
currently, should be considered for the next generation. Several possible solutions to achieve this
have been already demonstrated in the literature.
Finally, perhaps one of the major disadvantages of this technology is the lack of electrothermo-mechanical characterization methods in the current generation of CMOS technologies.
This becomes particularly important when the sensors and actuators are designed out of CMOS
films. Since each CMOS process employs a propriety fabrication procedure, the properties of
thin films vary significantly. An easy and reliable characterization procedure has to be
developed. Without such a characterization, it is nearly impossible to transfer one design
between two different CMOS technologies. Therefore, although the presented ideas are
applicable to every CMOS and BiCMOS technology, the designs can not be used as they are.
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Advantages of the CMOS-based Monolithic CMOS (CM-MEMS) described in Chapter 3
can be grouped under two main categories:
1. Improvement in traditional passive devices.
2. Integration of novel devices.
There has been enormous interest to extend the capabilities of CMOS medium for
wireless communication applications. Increasing lithographic resolution has been the main
source of improvement in the performance of transistors. Not until recently, the optimization of
transistors was the only criterion in process changes. In many cases, quality of passive
components, that is resistors, capacitors, inductors, and interconnects, has been ignored. As a
result, some of the decisions, for example increasing the conductivity of substrate, were made to
scale the CMOS transistors, which in turn worsened performance of passive components
considerably. Especially, the analog front-end of the communication circuits suffers because of
the low-quality passive components. Among these, high quality inductors are particularly
important for several applications such as low phase noise oscillators, frequency synthesizers,
radio-frequency (RF) filters. In this chapter, micromachined inductors with peak quality factors
more than 400% higher than the traditional CMOS inductors are described.
The CM-MEMS technology allows monolithic fabrication of distributed passive
components in CMOS medium. Among these components are coplanar transmission lines,
couplers, power dividers which will be described.
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Filter (SAW)
0.6-3.1 MHz
1-3 GHz
(ceramic. SAW)
T JilJ
PLL buseil synih.
QPSK demodulator
TDM demultiplexer
Viterbi decoder
Reed-Solomon dec.
MPEG decoder
Figure 4.1: Traditional superheterodyne-transceiver architecture requires
several high quality components that usually achieved by technologies
incompatible with standard CMOS process.
The most striking benefit of this process is the addition of a whole new class of devices
that take advantage of electrically controllable high-quality mechanical structures. The
functionality of current CMOS fabrication technology can be improved dramatically. This new
class of devices will be discussed in Chapter 5.
High Performance Lumped Components
Silicon micromachining has changed the landscape of many areas. Successful
implementations such as accelerometers in the automotive industry and movable mirror displays
in the electronics industry have paved the road for novel ideas and applications in other areas as
well [2]. Particularly, the prospect of wide ranging applications of silicon micromachining in the
microwave frequencies has caused a dramatic increase in activity in this area [3], [26]. Specially,
the work in the microwave communications field has started with the realization of large
suspended inductors on CMOS chips [27].
Quality requirements for several components, used in the traditional superheterodyne
transceiver architecture, have been the main problem in the development of single-chip
transceiver systems. Tight design requirements can only be met if these high-quality external
components are used. These components are identified in Fig. 4.1
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Loop Filter
Figure 4.2: Phase Lock Loop frequency synthesizer.
Figure 4.3: A LC-tuned oscillator as a feedback circuit.
Inductors are necessary not only for RF filter design but also for several other systems in
a mobile communication front-end. In order to describe the importance of integrated high-quality
inductors, the frequency synthesis is summarized first.
Motivation: Frequency Synthesis
One of the major challenges in the design of a transceiver system is the frequency
synthesis of the local oscillator (LO) signal [28], [29]. The frequency synthesis is usually done
using a phase-locked loop (PLL) as illustrated in Fig. 4.2. The feedback in the loop forces the
output frequency to be Af times the reference signal. The reference signal is generated by a very
stable, low-frequency crystal oscillator. The spectral purity of such an approach depends on the
quality of voltage-controlled oscillator (VCO) employed. Due to very narrow channel spacings
used in cellular telecommunication networks, extremely low phase noise levels are required. At
10 kHz from the carrier, a single sided spectral noise density of -100 dBc/Hz is specified [28].
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©<=--------------7 W M H ----------°©
-L r
Figure 4.4: Planar inductors are modeled with various parasitics. In this, generally
accepted physical model, Rs and Ru,b are loss terms due to conductor and substrate,
respectively. Cox is the oxide parasitic capacitance and CSUb is the capacitance due to substrate.
Cf is the parasitic feedback capacitance.
This level of phase noise spectrum can only be achieved by using LC-tuned oscillators [29]. The
main specifications of a VCO are:
1. Oscillation frequency,/0
2. Available signal power to mixer, Ptlvs
3. Phase noise at a frequency offset of A/from the carrier, N(AJ)
4. Minimum frequency tunability
( f im x - f m i n ) K f m a . x + f m i n )
to compensate process variations.
A LC-tuned oscillator is a feedback network as shown in Fig. 4.3. The oscillator phase
noise for this topology, using a linear approximation, is given by [30]
where F is the noise figure of the active circuit with the positive feedback removed, k is the
Boltzman constant, T is the temperature and QL is the loaded quality factor of the resonator.
Quality factor of the resonator is given by QinJ/Qcup, where Qind and Qcap are quality factors of
inductor and capacitor, respectively. Thus, the quality factor of the LC resonator is limited with
the lowest quality factor in the system, usually, the inductor is the limiting component [28].
Recently, a lot of effort has been spent for realizing high quality on-chip inductors. However, it
is difficult to obtain quality factors more than 10 even for small values. Therefore, external
inductors with Qind>40 are preferred in many applications.
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Frequency (GHz)
Figure 4.5: At low frequencies, micromachined inductors are limited by
the conductor losses, whereas, at high frequencies, the self-resonance dominates
the quality factor. The calculation is based on the equivalent model show in the
In this work, it is shown that substantial improvement can be achieved by the
micromachined inductors and mechanically tunable capacitors. The achieved quality factors are
more than 10 times what can be obtained on CMOS substrate and close to values of the external
Current State-of-the-Art
Quality factor of an inductor is defined as
2 = 2*__________| s w
Entrgj __________
(4 2)
Energy losses are due to finite conductivity in the substrate and conductor. These losses and
parasitic capacitances are modeled with the equivalent circuit given in Fig. 4.4.
Most sub-micron CMOS processes use epi-wafers to eliminate the effects of hot-electron
induced substrate currents and to minimize crosstalk between analog sub-circuits. However, this
is detrimental for the high-frequency passive circuits, such as inductors and transmission lines.
For inductors, the losses due to substrate become dominant for frequencies above 1 GHz.
Therefore, even using thick and low-loss conductors will not improve the RF performance of
inductors, if the inductor-to-substrate distance is less than 10 (im. With the traditional fabrication
techniques (see Fig. 4.6a), quality factors are limited to 5 for a 10 nH inductor [31].
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Figure 4.6: Four types of inductor fabrication is investigated. Traditionally
planar inductors are fabricated with an aluminum film as far as possible from
substrate (a). With bulk micromachining substrate-losses can be eliminated (b).
Thick-electroplated gold inductors elevated more than 10 pm from the substrate
minimize the conductor losses and the fabrication cost (c). The highest quality
inductors are obtained with thick gold inductors and bulk micromachining, (d).
Various fabrication techniques are investigated to improve the quality factor of inductors
High-Quality Inductors in CM-MEMS Technology
Micromachined inductors are modeled with three parasitics Rx, Cv and C; as illustrated in
Fig. 4.5. Based on this model, the quality factor of an inductor by using energy loss definition is
given by
R;{cs+c f )
, ,
U.-a>-Ls{cs +Cf )
In this equation, the first term accounts for magnetic energy stored and ohmic loss,
whereas the second term includes the self-resonance effects due to parasitic capacitances. The
quality factor is inherently frequency dependent. Futhermore, the parasitic components have
additional frequency variations. For example, the series resistance changes with frequency as a
result of skin-effect, and eddy currents. A typical quality factor curve that includes such variation
is given in Fig. 4.5.
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Comparison of inductors based on such curves is difficult and cumbersome. Instead, two
critical points on this curve, namely the peak quality factor and the self-resonance point, may be
used for comparison purposes. These points capture essential nature of the curve, therefore, they
are chosen to compare the quality of inductors.
Based on the model shown in Fig. 4.5, the quality factor of an micromachined inductor
with inductance L, can be improved in two ways:
1. Increasing the self-resonance frequency.
2. Decreasing the ohmic losses.
Increasing the self-resonant frequency can improve the quality factor of an inductor at
high frequencies, but the low-frequency behavior will not be affected, unless the changes end up
changing the series resistances. The parasitic capacitances, (C5+C/), are contributed from various
sources. Underpass, inter-winding, discontinuity and ground capacitances are usually minimized
by layout optimization. Process changes, such as the use low-k materials, are utilized, as well.
Recently, Yoon et al. demonstrated planar inductors that are fully suspended in the air (the ideal
case) as shown in Fig. 4.7 [39]. Such un-supported micromachined inductors are extremely
fragile and mechanically weak, therefore should be handled very carefully. Mechanical
robustness is one of the desired characteristics of the inductors that must be considered in the
optimization. Therefore, in this work, the inductors are supported with a polyimide film with
dielectric constant as low as 2.5.
Wireless applications, below the operation frequency of 5 GHz, are mainly conductorloss limited. Therefore, ohmic losses should be decreased. Again, there are fabrication oriented
and layout oriented optimizations to lower the losses. The fabrication methods include the use of
better and thicker conductors [33], [35], [37], [39]. It has been also showed that the use of nonuniform strip widths significandy improves the performance of eddy-current-limited inductors
The developed processing technique allows the fabrication of three types of high quality
inductors, integrated with CMOS. These inductors are illustrated in Fig. 4.6.
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O verh an g air-gap |
Figure 4.7: Suspended electroplated-copper inductors have very low
parasitics, but they are very fragile, as well [39].
Figure 4.8: Polyimide supported CMOS inductor. This inductor has
inductance of 8.9 nH, the peak quality factor of 10.5 an d /re.vof 8.2 GHz.
1. CMOS interconnect layers (Metal 1 and Metal2) are used to realize inductors. Later, these
inductors are isolated from lossy silicon substrate by backside micromachining [41], [40].
This eliminates the parasitics due to substrate, as a result, an increase of 300% in the peak
quality factor has been achieved [40]. 8.9 nH inductor with 0 pt.u*=lO.5 and / r„=8.2 GHz
is demonstrated. Later, these results improved further by layout optimization [41]. This
approach gives 10 nH inductors with quality factors more than 16 and self-resonant
frequencies more than 12 GHz. Fig. 4.8 shows one of the backside micromachined
Several published peak quality factors are compared in Fig. 4.9. The removal of
substrate improves Qpeak for a 10 nH inductor from 3 to 9.6. Additionally, by layout and
process optimization, quality factor of inductors in CMOS is increased by a factor of two.
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The point "L" seems to be the upper limit that can be obtained by using thin-aluminum
2. Another class of high quality inductors is proposed but not demonstrated that overcomes
the aluminum limitations by using low-loss electroplated gold metallization elevated
above the substrate without any backside micromachining (as seen in Fig. 4.6c) [42]. The
resulting inductors have very high quality and will look like elevated inductor, shown in
Fig. 4.7, except supported by a low-loss polyimide layer. The preliminary calculations
indicate that for a 10 nH inductor, quality factors higher than 30 is possible with this
3. Highest quality can be obtained by further removing the substrate as illustrated in Fig.
4.6d. The use of thick gold lines decreases the series resistance more than three times, but
no inductors fabricated as such is demonstrated yet. There is an important difference
between inductors realized with gold and those with aluminum. Electroplating has an
inherent limitation due its low-resolution, therefore inductors with gold metallization
occupy larger area. Qpeuk values as high as 40 are predicted with this technique. This is
marked with "M" in Fig. 4.9. The details of the process are discussed in [42].
High quality RF filters that described in the section 4.2.2 need inductors with Rs/Ls < 0.33
Q/nH at 2.4 GHz. Such a 10 nH inductor will have a quality factor of 45 at 2.4 GHz (!) assuming
/ r„ > l0 GHz. This is more than 10 times of what has been possible on CMOS-quaiiiy silicon
substrate! And this is possible integrated with CMOS electronics.
The drastic improvement is possible because of the process and the scalable physical model
that accounts the parasitics accurately. Therefore, the developed physical model is described in
detail in the next section.
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50 -
p e a k
40 -
30 -
Inductance ( nH)
Figure 4.9: Peak quality factors of inductors are compared for several
different technologies. The red line shows the approximate boundary for inductors
fabricated on low-resistivity silicon substrates, e.g. CMOS process. In order to go
beyond this limit, many micromachining techniques are used. The points K and L
show the inductors reported in this work. The point M is the predicted
performance of the inductor fabricated with thick gold metallization.
1.7 pm thick S i0 2
Nguyen et al
9 pm thick polyim ide
Kim et al.
Multi-level interconnect
Burghartz et al
25 pm thick Ox. Porous Si.
Nam et al.
On glass. 3D. electroplating
Yoon et al.
Wire bonding
Lee at al.
Thick copper. 3D . electrop.
Young et al
30 pm polyimide on alumina
Kim et al.
Copper electroplating
Yoon et al.
1.2 pm CMOS
Ozgur et al.
Optimized 1.2 pm CM OS
Ozgur et al.
Gold-electroplau'ng on CMOS
Ozgur et al.
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Metal I
Figure 4.10: Layout parameters used in the scalable model of the inductor.
Scalable Physical Model
All four components that are shown in the equivalent model in Fig. 4.5, are expressed in
terms of the physical parameters of the system. The layout parameters are shown in Fig. 4.10.
Other physical parameters used during calculations are given in Table 4.1.
In this work only square spiral inductors are used. The inductance calculation is based on
the expanded Grover formula given in [44]
Ls =L + M+ -M _ = f(w,s,t,l,Z),
where L is the self-inductance, M+ and M_ are positive and negative mutual inductances,
respectively. The inductance calculation includes five variables: vv, is the width of the strips, s,
the strip spacing, I is the outer dimension of the inductor, t, is the thickness of the strips, and, Z,
is the number of segments in the inductor.
The Greenhouse’s method states that the overall inductance of a spiral can be computed
by summing the self-inductance of each wire segment and the positive and negative mutual
inductance between all possible wire segment pairs. The mutual inductance betweentwo wires
depends on their angle of intersection, length, and separation. Two wires orthogonal to each
other have no mutual coupling since their magnetic flux are not linked together. The current flow
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Q .cm
< 10
3x1 O’6
3x1 O'6
> 50
> 10
Table 4.1: Physical constants and parameters used in the model.
directions in the wires determine the sign of coupling. The coupling is positive if the currents in
the two wires are in the same direction and negative for opposite currents. To evaluate the
overall inductance of a V-tum square spiral, it involves 4N self-inductance terms, and 2N(N-l)
positive mutual-inductance terms and IN 2 negative mutual-inductance terms.
There is a slight difference between the calculated and measured inductance values. This
difference is attributed to the inductance due to extra connections that are not considered in the
calculations. There are other empirical formulas that give better approximations, however,
extensive characterization is necessary to develop such formulations [45].
Accurate calculation of Rs is very important for the loss estimation. Various effects must
be considered for accurate results. Due to complexity, analytical expressions are derived only
with several approximations. The zeroth order approximations assume that the resistance does
not change with frequency and equals to the simple DC resistance given by
Ruc= ~
where ltotai is the total length of the inductor, and /?*/,«,« is the sheet resistance of the metallization.
The subscript u refers to the underpass metallization used to connect the output port to the
center-tap. Usually the inductor is designed with the metal layer that has the lowest resistance.
For example in the 2poly/2metal CMOS process, the spiral would be designed with MetaI2 and
the underpass connection would be realized with Metal 1. The length of an inductor with Z
segments is given by
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where the function designated with (•) rounds the numbers to the nearest integers towards minus
infinity. Eq. 4.6 is derived for the specific construction rule used in this work. It is valid for
inductors with integer number of turns plus one additional segment, corresponding to
Z=5,9,13,17... The last term of the equation is used to calculate the length of the each turn and
the additional length in the first and the second terms accounts for the innermost segment and
additional interconnection segments.
The zeroth order approximation given in Eq. 4.5 is accurate enough for applications
below 1 GHz. However, when the skin-depth, S, becomes comparable to the thickness of the
metal strips, t, than the resistance increases proportional to the frequency, usually with a
functional dependency given by f c n i with /k0.6. In this expression,/g#- is the frequency given
in turns of GHz. Theoretically, the constant, /?, is 0.5, however, measurements indicate values as
small as 0.2. There are various ways to include such effects [46]-[48]. There is considerable
effort in accurate calculation of skin-effect resistance not only for inductors but for transmission
lines, as well [49]-[52]. Wheeler's incremental inductance rule is one of the most widely used
expressions for this purpose [49]. Nevertheless, this formulation is valid only if the conductor
thickness, u is several times the penetration depth, 8. The phenomenological-loss-equivalence
method (PEM) approach introduced in [50] and the conformal-mapping technique described in
[52] are very complicated to include in this model. Instead, we preferred to use simple
where a and (5 are appropriate constants that are determined experimentally. Although in
preliminary simulations included (a, /?)-pair as (0.168, 0.60), later we realized that the frequency
dependence of the inductors varies with the geometrical factors as well. This is shown in
Fig. 4.11, although the DC resistance is smaller for the wider strips, its increase is very steep
compared to narrower lines.
The geometrical dependencies of the (a, /?)-pair are rather difficult to determine. Since
these variations appear because of the non-uniform distribution of the current along the
inductors. The geometry of a planar, spiral inductor is fairly complicated, which almost
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All inductors are
L, = 10.5±0.7 nH
s =2.4 jam. t - 1.0 |im. Z=2
Figure 4.11: Frequency dependency of the series resistance depends on the geometrical
factors. The measured curves up to 10 GHz are curve-fitted with the Eq. 4.7.
eliminates the possibility of analytical calculations. The parameters that are considered are w, s,
/, t, Z, and ct (conductivity of the strip). Out of all these, only four of them were investigated in
this work. Several inductor layouts are fabricated corresponding to the same inductance value of
10 nH with a 1.2 pm CMOS technology. After extensive measurements of these test structures,
the series resistance is extracted with the procedure described in section Then, the
measured values are curve-fitted to find the (a, /?)-pair for each inductor. The results of
measurements for nine inductors are shown in Fig. 4.12.
It should be stressed that since we decide to keep the value of the inductor constant, not
all the four parameters can be changed independently. In the designed inductors, the separation
between the strips is kept constant; therefore, the dependency on s could not be observed. The
main variables in the physical designs were w and Z and /. Furthermore, our investigation
showed that there is no significant dependence on the size of the outer dimension of the inductor,
i.e. /. Consequently, the measurement results shown in Fig. 4.12 show dependency on w and Z
only. The data is characterized with the linear expressions given below:
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All inductors are
= 10.5+0.7 nH
=2.4 nm. M.O (am
0.4 -
Figure 4.12: Observed dependency of ( a p) on geometrical factors.
/?(vv,Z) = l.2 + [o .0 3 2 5 -l.9 -1 0 '3 -(Z -1 3 )j-(w -l0 )
a(w .Z) = 0.07 + [0.0225-3.125 • KT4 •(Z - 13)J- (vv- 10)
These expressions are valid for only the measured inductors and without any numerical
verification cannot be generalized for wider range of Z and w. If these results are confirmed with
numerical studies then a more general expression can be derived. Nevertheless, these equations
report, for the first time, the relation between frequency dependency and geometrical factors for
the series resistance.
Resistance increase due to eddy currents in the inner segments of the inductor is also
considered an important source of loss [28], [43]. Nonetheless, so far, there is no closed-from
equations have been introduced to calculate this effect. It is also argued that by increasing the
inner radius of the inductor and the spacing between the segments, this effect can be minimized
Finally, at high frequencies, the discontinuities the non-uniform current distribution, or
current crowding, can be included in the calculation to increase the accuracy. However, the
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applications, that need high accuracy, use 2D or preferably 3D electromagnetic packages to
include all the high order effects.
In the micromachined inductors the parasitic capacitance to ground, Cs, is calculated by
using numerical techniques. The first analytic approximation for coplanar inductors has been
introduced in [40]. This formulation assumes that the ground capacitance for an inductor and
similar coplanar transmission line are the same. The capacitance is calculated by
C, = 2 • <?0 • (1 + £ „ ) • / • F{2a,2b.2c , ha ) ,
where ess and h„ are the dielectric constant and the thickness of the supporting polyimide film,
the dimensions, a, b, and c correspond are calculated as:
a = (-j(w + s)-s
b =a +lx
c=b + w
The function F(- ) in Eq. 4.8 is defined as
where K(k) is the complete elliptic integral of the first kind and k is the argument of the integral
(k' is defined as k' = ^ i - k 2 ). The argument is obtained for a finite-extent coplanar transmission
line with proper scaling due to dielectric slab of thickness, h, is given as
,r,(/i) = sinh^—^'-C|
x3- ( h ) - Xl-(h)
for /= 1.2,3.
(4 .1 2 )
A more accurate formulation would use the same formulations borrowed from quasi­
static analysis of coplanar transmission lines, but instead of treating the segments as a block, it
might treat each segment individually. Such an approach is significantly more complicated, and
it would yield only slightly better approximation, since it does not include many discontinuities.
The capacitance, Cs, represents the feedback capacitance of the inductor. Capacitances
due to the underpass (or air-bridge) center-tap connection, inter-windings, and discontinuities are
the main sources for Cs. The first order calculation includes only underpass capacitance.
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( 4 - 13 )
C u = Z p a s s - w -w u - C pass
where Zptm is the number of crossovers between spiral and center-tap and Cpass is the capacitance
between two metals that make up the spiral and underpass per unit area. For the type of
construction considered here, the inductors has
v . = (f)
Inter-winding and discontinuity capacitances are usually calculated by using numerical
techniques [47], [54]. The latter contribution is very small at frequenciesbelow
therefore it can be neglected.
10 GHz,
On the other hand, the inter-winding capacitance canbesignifican
It has been calculated by using even- and odd-mode analysis [55], [56]. In these calculations,
only the coupling between adjacent segments is considered. The inter-winding capacitance is
given by
where C„ and Ct are odd and even mode capacitances for a coupled coplanar lines. For coplanar
inductors, the odd-mode capacitance can be approximated as
C„ ~ C pp + Ccp, + Ct
where Cpp is the parallel-plate capacitance between the lines and Ccps is the equivalent
capacitance between the surfaces of the lines. The parallel-plate capacitance between the
adjacent lines is given by
Cpp =£■0 beisolation
,4 jy,
v * .1 ' )
If the dielectric between the segment is SiCF, then £iSoainon=3.9. Coplanar strips has a
capacitance of
(4 . 18)
Based on these approximations, the feedback capacitances is calculated as
Cf . C. + C"’ * C^ .
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Ind 2
Ind 3
Ind 4
Ind 1
Cs C max
(fF) (fF) (GHz)
12.3 10.3 10.2
12.3 17.8 11.8
16.4 28.2 9.3
16.5 25
16.4 28.2 4.6
15.6 23
f max
f res
Table 4.2: Experimental verification of the scalable model for micromachined
inductors supported b a low-k polyimide film.
Experimental Verification
The developed model is experimentally verified for two different fabrication process. In
both cases, the measurements are performed by a HP8510 network analyzer with SOLT (shortopen-line-thru) probe-tip calibration. The contact pads and other parasitic are de-embedded by
using simple procedure outlined below.
The pads and transmission lines characterized independently by using short and open test
structures. The s-parameter measurements are converted into A.BCD matrices. Then pads are de­
embedded as
ABCDmeiss ■ABCD^ ,
where ABCDde is the de-embedded results and ABCDmtus are measured results. ABCDpad is
obtained by independent measurements.
The de-embedded measurements are used to extract the values of the components in the
equivalent circuit, shown in the model in Fig. 4.5. An extraction procedure by using ^-parameters
is described in [40]. Here, the extraction is performed by using y-parameters.
The shunt impedance at the input has the value of T//+T/2 . Thisimpedance is a pure
capacitance, it will be
c r= llm (K l l + KI2).
2. Similarly the shunt output capacitance can be found as
£UM=J_im(y'22 + K,,).
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L .
Meas Model
10.888 10.052
11.022 9.9942
10.985 10.002
11.046 10.002
10.523 10.002
11289 10.002
11.006 10.008
11.04 10.123
11.192 10.066
10.928 10.002
10.657 10.002
10.657 10.002
11.427 10.112
11.405 10.072
11.081 10.036
12.664 10.002
11245 10.002
11.245 10.002
12.071 10.044
11.343 10.007
11252 10.013
11.773 10.002
11.543 10.002
11.709 10.002
C ,
R .
17 37
f max
Q max
Meas Model
f r „
Table 4.3: Experimental verification of the scalable model for micromachined
3. Since the capacitance C{ can be neglected at low frequencies, the DC value of series
resistance and inductance are found as
L, = —lm[— —
RJc = Re| -
^ .
4. The capacitance C/ is found by observing the self-resonance of the T?/
c -
where f r>0 is the resonance frequency given by
a / K-,,
5. If all the other circuit components are assumed constant, the frequency dependency of the
Rs can be obtained by
This curve is used to find the parameters, a and
for Rs given in Eq. 4.7.
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—V -
80 -
60 40 -
Inductor Area (A) ( mm2)
Figure 4.13: Inductance per unit area increases with number of turns used in the
18 -
16 -
14 Z=9
• O- Z=13
- Z=17
Inductors A rea (A) (mm2)
Figure 4.14: Calculated peak quality factors for the same set of 10 nH inductors
shown in Fig. 4.13.
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180 - 13
160 -
140 -
To 120<S
100 -
60 -
- 9
40 -
Figure 4.15: Qnuix depends strongly on C/. Although C/ can be minimized by using
narrow conducting strips, this increases /?, after certain point.
15 - 15.5
14 ■
- 15.0
13 12
- 14.5
- 14.0
- 13.5
Ig ip m )
Figure: 4.16 A relatively weak relation between Qimx and Cs is observed for a 10 nH
inductor with Z=21.
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The comparison of first set of measurements is shown in Table 4.2. The second set
includes 24 inductors. The predicted values of parasitic components and measured values are
compared in Table 4.3.
The measured quality factor can be calculated in two different ways, one is by taking the
ratio of the imaginary and the real part port of the input impedance transformed from the
measured two-port, which is given by
where is Yu is the y-parameter of the de-embedded inductor. Since the series resistance is the
only source of loss in this model, this calculation corresponds to the physical definition given in
Eq. 4.3. If there are other parasitics that are not modeled then the calculation of the Eq. 4.3 and
Eq. 4.26 would give different results.
The agreement between model and measurements is very good for hollow inductors. Based on
the characterization of the second set of inductors:
1) Generally, Ls is under-estimated by the described technique. The additional connections that
are not included in the calculation can only explain the part of the difference.
2) The model for the series resistance is, inherently, experimental, since the accurate calculation
is extremely complicated. The basic trends observed are summarized as.
a) The coefficient oris larger for wider segments, w.
b) The coefficient (3 is essentially constant for Metal2.
3) The capacitance, Cs, is predicted accurately in most of the cases.
4) The feedback capacitance, C/, is slightly higher than the model’s prediction. This is believed
to due to under-estimation of inter-winding capacitance.
If it is assumed that the developed model adequately describes the performance of the
inductor, the quality factor optimization can be performed. A meaningful comparison between
inductors might be done much easier if the value of the inductor is fixed. Therefore, in this
optimization, Ls, is chosen as 10 nH. The direct approach would be to insert the developed
formulation into Eq. 4.3, and to optimize the resulting equation as
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Qptak = Max[f{z, /, w, s, t, wu, w,., lg, hv, ea )| ^ =|Qn//.
If the optimization is performed for inductors realized in CMOS membrane as shown in
Fig. 4.5b, the optimization is performed in 9 dimensional space, since the thickness of the
metallizations cannot be controlled. However, this approach is significantly difficult than a sub­
optimum approach taken in this work.
Instead of optimizing the quality factor directly as stated above, the quality factor can be
optimized by minimizing each parasitic component separately. Some of the components are
virtually independent from each other, or some components have more pronounced effect in the
quality factor than others. It is clear that the most important component for wireless applications
is the loss due to Rs. The improvements in quality factor by increasing the self-resonance will be
considered later.
Inductance of a spiral inductor depends on four controllable parameters, according to the
presented model. They are Z, /, w, s. To further simplify the optimization, let the inter-winding
spacing, 5 , be fixed to the minimum possible distance in the technology. (For 1.2 pm CMOS
technology, this distance is 2.4 pm.) This should give the minimum area for any inductance in
this technology. The remaining three parameters are investigated in Figs. 4.13 and 4.14. Four
different numbers of segments, 9, 13, 17, and 21, with three different number of conductor
widths, 9.9, 19.8 and 30.0 pm, are investigated. This corresponds to 12 different layouts with the
same inductance value, while keeping all the other parameters the same. As shown in Fig. 4.13,
the inductance per unit area decreases with wider strips and less number of turns. The difference
between various implementations can be as high as 10 times, in terms of area density. On the
other hand, the inductors with high density have higher parasitics as well. Higher parasitics limits
the peak quality factor. There seems to be an optimum width for the inductors, for which wider
or narrower strips would have lower quality factors as seen in Fig. 4.14. Rjc decreases
monolithically with larger w. However, this model does not include vv-dependencies of
parameters a, /?.
Minimization of the capacitance, C/, can be accomplished by minimizing the area of
underpass, since the inter-winding separation, s, is fixed above. There are two ways that this can
be achieved, either by decreasing the number of turns or by minimizing the width of the
underpass strip (w„). Fig. 4.15 shows relation between wu and C/, Qnuu for a 51/4-tum (Z=21)
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inductor. For a constant number of segments, wu must be narrow, but too narrow lines increase
the overall series resistance. The optimum width usually lies between 3 pm-7 pm range for the
technology used in this work.
The capacitance to ground, Cs, is largely reduced by the process optimization, which involves
the use of low-k dielectric support structures. In addition, increasing inductor-to-ground-plane
separation, /„, reduces this parasitic component. However, the peak quality factor shows weak
dependence for the variations on lg (Fig. 4.16.). In order to get 100% change in C„ lg is changed
1000% and this yields less than 15% change in
Q m ax-
Based on the outlined optimization procedure above, the maximum quality factor of a 10
nH inductor is improved from 9.66 (in [40]) to 15.5 (in [41]). This is accomplished with 60%
increase in the area.
In general, the trade-off between the area and the peak quality is apparent in these
calculations. This is especially important when the inductor is designed within CMOS
membrane. If the inductor is designed outside the membrane as in the case of Fig. 4.6c and d,
then a lot larger areas can be used.
Future Work
The main goal in this effort is to demonstrate that inductors with quality factors, Rs/Ls <
0.33 Q/nH at 2.4 GHz can be fabricated by using the developed processing technology. Such a
10 nH inductor will have a quality factor of 45 at 2.4 GHz (!) assuming f res> 10 GHz. The
optimized inductor in CMOS, has /?s/LT-ratio of 1.4 Ci/nH at 2.4 GHz and corresponding quality
factor of only 10.7. This is limited by the conductor losses in Al wiring in a CMOS technology.
Beyond layout optimization, higher quality factors can only be achieved by using better
conductors. Resistivity of pure gold is 20% better than CMOS-caliber Al. A better choice would
be copper, because it has 40% less resistance for the same thickness. Additionally, the developed
post-processing supports depositions as thick as 10 (im. Almost 10 times thicker than anything
available in any CMOS process. The use of, modest, 5 pm thick Au lines for optimized inductor
would lower the RJLS-ratio below 0.33 Q/nH at 2.4 GHz. The skin effect of gold strips remains
to be seen.
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Beside the planar inductors discussed in this section, it is possible to fabricate 3D coils with
air-filled core. The quality of such inductors remains to be seen, but it is predicted that the
contact resistance between aluminum and gold will become an important factor.
Micromachined spiral inductors fabricated in CMOS by using standard aluminum
metallization are limited because of excessive conductor losses. By careful design the parasitic
effects can be pushed well beyond 10 GHz range, therefore, they can be totally ignored for
discussions for mobile applications. At this low frequencies, the quality factor is approximated
by ojLs/Rs. Either novel inductor topologies or new metallizations should be used to increase the
quality. It is proposed that the desired ratio of RJLS< 0.33 Q/nH at 2.4 GHz can be achieved by
using gold or copper electroplating. This will require additional optimization, because the design
rules are different from CMOS. It should also be pointed that there is no area cost of using these
inductors, since they won’t be on CMOS. This decreases the cost twofold, first the CMOS area is
saved, and second this area is used for additional circuits.
There are three important difficulties in the model development. Firstly, accurate
characterization of the frequency dependence of resistance is very difficult. The closed-form
expressions given by Pettenpaul et al. don’t work in this case. Therefore, an empirical approach
is used. This problem should be addressed, because the calculation of Rs is the most important
factor in determination of the quality factor. Secondly, the feedback capacitance is typically
under estimated if only underpass capacitance is used. The other contributions, such as inter­
winding capacitance and capacitance between vertical walls of the strips, add up to very large
capacitance values. Thus, in most of the cases the lower of these two numbers is used in the
calculations. Finally, the expanded Grover formula for the calculation of the inductance, usually,
underestimates the inductance. This is especially important because this formulation seems to be
the only physical expression available to find the value of an inductor.
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Figure 4.17: RF filters and duplexers are necessary to isolate the desired
frequency spectrum to minimize the interference from other channels.
RF Filters and Duplexers
communications. Currently, at operation-frequencies above 800 MHz, filtering individual
channels is impossible with any available filtering technology. Therefore, RF filters are used to
filter the desired frequency band, which contain many communication channels, as illustrated in
Fig. 4.17. Duplexers, on the other hand, consist of two RF filters with slightly different center
frequencies to provide necessary isolation between receive and transmit paths. The main
specifications for RF filters are:
1. Insertion loss.
2. Stopband rejection.
3. Cost (fabrication and integration).
The emerging micromachining technologies are set to change the current status in this
market by providing not only performance that has not been possible before but also by
presenting a new way of integration. In this section, the current-state of the art and recent
development in micromachined components are described.
Current state-of-the-art
Mobile applications usually require less than 5% bandwidth and more than 30 dB out-of-
band rejection [57]. High dielectric constant ceramic filters [58], [59], Iow-temperature cofiredceramic (LTCC) filters [60] and surface-acoustic-wave (SAW) filters [61], [62] are widely used
in current mobile applications. Even tough significant progress has been observed in these
technologies, these filters still has insertion losses 2-3 dB range at 1.8 GHz and they occupy
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a, -20
C=1.7 pF
L= 1.438 nH
42.1 GHz
0 « * 2 S .I
\ I
------- Measurement
------- Simulation (fls=0.75 Q)
0.78 GHz
------- Simulation (R=7.5 Q)
F req u en cy (G H z)
Figure 4.18: Measurement and simulation results of a series LC resonator
with£-=3.22 GHz.
substantial part of the board area. In fact, duplexers are the second largest electronic components,
after batteries, in cellular telephones.
The insertion loss is especially important for transmit path, since code-division-multipleaccess (CDMA) techniques require constant power transmission. Considering efficiency of
power amplifiers is less than 40%, 3 dB loss is significant. Any improvement in the efficiency of
power amplifiers or filters will increase the battery time of mobile phones.
Micromachined RF Filters
The RF filter requirements can also be satisfied by using high quality lumped or
distributed filters. This is demonstrated with preliminary results obtained from test structures that
fabricated by CM-MEMS technology.
Lumped circuits are based on inductor and capacitors. Lumped resonators are limited by
the performance of micromachined inductors. In fact, the requirements of RF filters is extremely
difficult to meet, therefore distributed alternatives are investigated as well.
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Figure 4.19: 3.7 GHz third order Butterworth bandpass filter is fabricated
with on-chip inductors using 1.2 pm CMOS technology.
LC Bandpass Filters
Several LC resonators, with resonance frequencies up to 5 GHz, are fabricated and
characterized. The LC resonator, shown in Fig. 4.18, has a resonance frequency of 3.22 GHz.
The capacitor is designed with Metal 1-Metal2 capacitance. With a capacitor density 43±2
aF/pm2 and low-loss dielectric, the capacitor is expected to have quality factors more than 50.
The limiting component in this resonator is the inductor. Various parasitics associate with
inductors, but if the inductor is not isolated from the substrate, the loss is usually dominated by
the substrate losses. Therefore, inductors must be isolated from the lossy silicon substrate. After
micromachining, the most important loss mechanism becomes the conductor losses, as described
in section 4.2.I.3.I. The inductor, given in Fig. 4.18, is designed to be 1.06 nH. Its estimated dc
resistance is 6.05 Q (including the underpass resistance of 1.43 Q, but excluding the contact
resistances). The parasitic capacitances are negligible at frequencies below 10 GHz. In fact, the
feedback capacitance, that causes the inductor to self-resonate at 42.1 GHz, is extracted as 10 fF.
The measured response of the resonator is slightly different from the predicted response,
which is based on the component models. Firstly, the capacitance density of the fabrication run is
found to be 45 aF/pm2, shifting the value of the capacitor almost 5% higher. Secondly, the value
of inductor is measured to be 1.428 nH, almost 35% higher than its design value. This is
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c -25 o>
2 -30 -35 -
Sim ulation o f
equivalent circuit
(no EM)
-40 -45
Frequency (GHz)
Figure 4.20: 3.7 GHz filter is simulated with the extracted circuit models
of inductors from series resonant test structures. The deviation above 5 GHz,
indicates that an em simulation is necessary to include coupling between
attributed to the modeling and measurement errors. Since there is no de-embedding performed,
the inductance of transmission lines are also included in the measured value. The series
resistance is extracted to be 7.5 Q, by curve-fitting around the resonance frequency. The increase
in resistance is due to small inner-spacing and resulting eddy currents in the inner line segments.
Consequently, the resonance frequency is shifted to 3.22 GHz, from the target value of 4 GHz.
Conductor losses are considerable even for micromachined inductors. In order to
demonstrate this the same resonant circuit is re-simulated with 10-times lower series resistance
in Fig. 4.18. This change causes only 0.5 dB improvement in the transmission loss, however, its
effect on system level is more evident.
By using micromachined inductors and capacitors, a third order Butterworth bandpass
filter, shown in Fig. 4.19, is designed. The target values are 50% bandwidth at center frequency
of 4 GHz. The series and shunt resonators, used to realize the filter, are separately characterized.
In fact, the series resistor shown in Fig. 4.18, is the shunt resonator used in the filter. The
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(7.5 Q. 17.8 Q)
(0.75 O, 17.8 £1)
(0.75 O. 1.78 Q)
(7.5 £2. 1.78 O)
-4 CO
Frequency (GHz)
Figure 4.21: Resistances on the series- or shunt-connected resonators have
different effects on the passband loss. Generally, the losses in the shunt-connected
resonators are more pronounced.
equivalent circuit models obtained from these resonators accurately predict the overall response
of the filter (see Fig. 4.20). The variation in transmission curve (Sit) is attributed to distributed
nature of the circuit. To verify this hypothesis, electromagnetic (EM) simulations of the circuit
are carried out by using Sonnet em suite [63].
The inductor on the series branch of the filter has predicted (measured) inductance of
8.3 nH (8.7 nH), series resistance of 17.6 £2 (17.8 £2) and self-resonance frequency of 31 GHz
(12 GHz). The measurement of the filter, included in Fig. 4.20, shows approximately 5 dB
insertion loss at the center frequency of 3.7 GHz. The re-simulation of the filter with various
resistance values (Fig. 4.21) indicates that 10 times less resistance on the shunt branches would
result in more than 2 dB improvement in insertion losses. The same level enhancement would
not be obtained with the same amount of change in the series branch.
The stopband rejection criterion for RF filters, implicitly, requires very high selectivity
with A/30dB/A/3dB<2 0 for 5% A/mb I f c - Based on the experimental study of LC bandpass filter,
feasibly of a 2.4 GHz filter with A/3dB=240 MHz, corresponding to 10% of the center frequency,
is theoretically investigated.
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£ 0~
-2 5
-30 -35 -40 -45
Frequency (GHz)
Figure 4.22: If inductors with resistance-to-inductance ratios less than
equal to 0.33 O/nH are used, the requirements for duplexers in mobile
communication can be met. Integrated CMOS filters, fabricated with these
inductors, will have less than 10% relative bandwidths and more than 30 dB
stopband rejection.
A third-order LC elliptic filter protype with 0.5 dB passband loss and 40 dB stopband
rejection has A/30dB/4/3dB<2.25. A fifth order elliptic filter with the same design criteria can
achieve A/3odB/A/3dB<l-5. Nevertheless, fifth order filters require twice the area of an third order
filter and their insertion losses are higher. The values of the components, for both cases, are in
the practical range: 0 .1 pF < C < 30 pF, and 0.1 nH < L < 40 nH. High quality capacitors can be
realized with Metal 1-Metal2 structure. Again, the critical components are inductors. According
to circuit simulations, the resistance-to-inductance ratio for the inductors must be lowered to 0.33
Q/nH level to obtain acceptable insertion loss at 2.4 GHz. The DC resistance can be lowered
simply by using wider lines, however, higher order effects, such as skin-effect and eddy currents,
limit the performance. It has been concluded that it is impossible to get this level of performance
with 1.2 pm CMOS technology with aluminum interconnects [41], [42]. Fortunately,
electroplated-gold gives low-ioss metallization option for these applications. According to
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- C2
z o fj
Figure 4.23: Frequency and impedance normalized bandpass prototype
(a), can be transformed into a network with only shunt-connected resonator with
the help of admittance inverters (b). The inverters with resonators at both ports
can be realized by using only quarter-wavelength-long transmission lines (c).
preliminary calculations, by using gold, with 3 times lower sheet resistance than Metal2, the
desired, high-performance inductors can be achieved integrated with CMOS [42].
Distributed Filters
Distributed filters, consisting of quarter wavelength long transmission lines, can also
achieve very high quality. The developed CM-MEMS technology provides an easy way to
fabricate and integrate the transmission lines with CMOS electronics, therefore, in this section,
the related study is summarized.
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Figure 4.24: Two configurations of coupled-line sections that are used for
bandpass applications. Note that the short-circuited version has the desired circuit
representation for the filter shown in Fig. 4.2Ic.
The Butterworth lowpass filter prototype, which forms the basis of the highpass,
bandpass and bandstop filters is a Cauer-type ladder network, whose topology is not always the
most practical circuit topology at high frequencies [64]. More desirable filter architecture would
be one involving only shunt or only series elements spaced by immittance inverters. Immittance
inverters provide one means o f replacing a Cauer-type network low-pass ladder network using
lumped L and C values by one using only L values and impedance inverters or one using only C
values and admittance inverters [65].
Various distributed filter design techniques have been demonstrated over the years [66].
In Fig. 4.22b, the use of admittance inverters, (Jn,n+i), to transform a bandpass filter prototype
into a ladder network using only shunt resonant circuits is shown. These inverters can be realized
by using negative lengths o f transmission lines. Usually, these negative lengths are incorporated
into the resonator structure itself [64]. Moreover, it is possible to use unit element (UE) and tplane capacitors or inductors to represent shunt-connected parallel resonator and admittance
inverters, as shown in Fig. 4.23c. The unit element is defined by the following ABCD matrix
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a/ i
- 5 -
Vl + Q :
jQ / ZQk
where S=jQ and from Richards’ transformation, Q=tan(^f/2/r). It is simply a lossless transmission
line of characteristic impedance 2o* that is one quarter-wavelength long at f r.
One of the most popular building blocks used in bandpass filters is the coupledtransmission line [66]-[69]. Their popularity can be understood by noticing that their circuit
representation corresponds to a section with UE and two shunt r-plane inductors, as shown in
Fig. 4.24. Therefore, the fabrication of the resulting distributed bandpass filter becomes very
Several third-order bandpass filters are designed with the proposed technology by using
micromachined coupled coplanar transmission lines. During the implementations, two major
problems have been faced:
1) Design issues: Available analytic and numerical models of coupled coplanar sections were
not adequate for the micromachined coupled-lines. These lead to development of a quasi­
static formulation and two-dimensional finite-element field solver.
The new analytical formulation of micromachined coupled-lines is necessary, because in
the existing formulas [70], [72]:
a) Strip thicknesses are neglected,
b) Dielectric film thicknesses are partially accounted.
Both of these items are important for current micromachined lines, because, often, in
order to obtain the desired even- and odd-mode impedance values the strips are placed very
closely. This has not been an issue, until very high-resolution photolithographic techniques
applied to pattern the lines. Currently, the minimum allowed distance between the metals and
the thicknesses of the surrounding dielectric layers are comparable in magnitude. Therefore,
these effects should be taken into account.
A closed-form analytical solution of the problem with all these parameters is impossible,
however, with the help of a computer to find zeros of two equations, practical formulation
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96.0 166.0 450 136.8 77.2
14.0 45.5
50.0 250 62.2 41.0
97.5 100.0 300 55.6 48.6
97.0 1 0 0 .0 300 58.8 51.0
65.0 260 207.4 92.2
32.0 150.0 265 267.4 143.2
40.5 125 61.2 35.2
50.0 165 64.8 37.0
50.0 165 76.4 65.4
90.9 122.7 125.1 250 54.2 47.6
149.7 203.7 206.1 125 50.8 44.4
Table 4.4: Numerical verification of the developed analytical formulation
for coupled coplanar transmission lines: a is the distance between coupled lines, b
is the total with of the coupled lines, c is the ground to ground separation and d is
the distance between outer edges of the ground planes.
can be obtained. The calculation that can be incorporated in a computer-aided-design (CAD)
package is briefly described in section and in [73].
A finite element method numerical solution for two-dimensional electromagnetic
problems is also developed [74]. This package is written on MATLAB [75]. Two distinct
features of this package are as follows:
1. A simple adaptive mesh refinement has been incorporated into the analyzer to
minimize the time and memory required for a solution with high accuracy. The
algorithm is based on discontinuities in the 2D profile.
2. A synthesis and optimization functionality is added to the package by including a
feedback loop around analysis code. The desired parameters can be selected and
optimized in a given range to obtain target impedance values. Several successful
synthesis examples for coupled microstrip and coplanar lines have been demonstrated
The comparison of analytical and numerical calculation for fabricated samples is given in
Table 4.4. Excellent agreement, observed in this table, could not be verified with
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S '-20 2.
■g -30 -
5 -40 -
-50 -
rar mq*
-60 -I
Kr Usi.tlali i
Frequency (GHz)
Figure 4.25: Optimized single section resonators have 0.8 dB loss at 40
GHz and 22 dB isolation at 10 GHz. The analytical, numerical calculations and
measured response agree very well over the frequency band of interest.
measurements. Most of the samples were not fabricated properly. However, an excellent
match for the first sample can be seen in Fig. 4.25.
The optimized single-section resonators exhibit less than 0.8 dB passband loss and 22 dB
loss at 10 GHz. The resonant frequency is above 40 GHz. The frequency response of this
resonator is shown in Fig. 4.25. The measurements, Sonnet em simulations and analytical
calculations agree very well up to 40 GHz.
High-order distributed filter research is focused in two architectures, both of which are
based on quarter-wavelength long coupled-coplanar line sections. The first architecture is
referred as "row connection of open-open resonator" is based on the section shown in Fig.
3.25. Open-open resonators are the ones with both of the unused terminals of the coupledline section are left open. There is a variation of this architecture that uses ground extensions
to overcome the design-rule limitation to achieve desired mode impedances. The experiments
of these filters show the importance of two issues:
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Frequency (GHz)
Figure 4.26: Inter-section discontinuity is minimized with the matrix
connection of open-open and short-open section (shown in the inset). The filter
still suffers from the lack of proper ground equalization.
1. Inter-section discontinuity: The layout of the row connection of sections requires long inter­
section lines. It is extremely difficult to determine the optimum compensations for
discontinuities even with the help of powerful EM field solver.
2. Ground equalization: The ground lines should be equalized to operate properly.
The solution for the first problem is a new layout architecture "matrix connection of
open-open short-open sections" (see the layout in Fig. 4.26). So far, even without proper
ground-equalization, this architecture has produced the best results. The way the coupled line
sections are connected and designed makes this filter unique because it does not have any
intersection discontinuities.
3. Fabrication issues: Two problems have been observed with the fabrication of distributed
4. The adhesion properties of stress-compensated layers become very important.
5. Ground-equalization fabrication.
Several different dielectric layers are investigated including various types of polyimide
and BCB (see section 3.2.7). It has been seen that gold protected pads greatly enhance the
adhesion properties. In the proposed process, this problem has been solved completely.
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Figure 4.27: CM-MEMS technology allows the fabrication of low-loss air­
The second issue deserves a longer discussion, since a capable coplanar technology must
assure high-quality coplanar-waveguide-mode propagation. The most important problem
with coplanar technology is the existence of two dominant modes of propagation (coplanar
waveguide mode CPW and coupled slotline mode CSL) [76]. It has been shown that the
unwanted coupled slotline mode, excited by asymmetrical discontinuities, drastically affects
the CPW circuit performance. To minimize the CPW-to-CSL conversion, groundequalization either by wirebonds or by air-bridges is preferred [76].
for ground-equalization,
equalization and internal equalization. The external equalization uses additional processing
steps to add the necessary connections between ground planes. Two widely utilized options
are wirebonds and air-bridges.
In many cases, even small process variations of the equalization structure can result in
significant changes in the response of a device. Therefore, it is necessary to have highly
accurate and reproducible fabrication techniques. The air-bridge technology satisfies these
requirements, and thus is usually favored over equalization by wirebonding in high
performance applications. However, with careful processing it is possible to include
wirebonds to the process. A Wilkinson-divider employing wirebonds has been already
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demonstrated in section Despite this demonstration of wirebonds [82], gold-airbridges are readily available with this process. Figure 4.27 shows the first examples of air­
bridges fabricated to equalize the same Wilkinson divider.
The internal equalization, on the other hand, is fairly new idea [83]. In this case, an
interconnect metal layer is used to connect the ground planes passing underneath the signal
line. This alternative is usually dismissed in MMIC designs, since metal interconnect layers
are separated by very thin layers of insulating films. The thin insulator drastically changes
the local propagation properties. Similar concerns, though less severe, have led to several
studies on the effects of air-bridges on wave propagation. In an experimental Ka-band branch
line coupler, ground equalizations are realized with a metal layer separated from the coupler
by a 0.75 pm thick SiO? layer. In addition, step compensations are employed to improve
return loss. The detailed discussion of the compensation method is given in section
Quality of distributed-filters is inherently higher than lumped components but still
conductor-loss limited [84]. Perhaps, a more serious problem with distributed filter designs is
their large size. Especially, micromachined filters see effective dielectric constants less than 2.5.
This corresponds to wavelengths of 7.8 cm<A.2.4GHz<12.5 cm. A small multi-section coupled-line
will measure larger than 2x2 cm. Compensation techniques can be used to reduce the area of a
filter to an total area of less than 1x1 cm [85]. However, this would degrade the quality of the
filters, canceling the gain. In fact, such use of lumped components for compact filter realizations
has been recently reported by Weller et al. [86], [87].
Another alternative is to use transmission line discontinuities. Powerful simulation
packages and well-controlled fabrication-techniques are driving forces behind this idea. Several
groups have reported compact high-frequency filter based on waveguide discontinuities [88],
[89]. These techniques, though promising, have not yielded very high quality filters.
Consequently, for applications below 5 GHz, high-quality distributed filters are not
practical because of their large size. Lumped filters are advantageous not only because of their
quality but also because of their compact size.
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Distributed Devices
X, K-band and millimeter-wave applications are growing with enormous rate. These
applications usually use monolithic microwave integrated circuits (MMICs) based on GaAs, InP,
or other esoteric substrates to obtain the desired frequency performance. Cost-effective
integration of passive distributed components and active circuits has been a challenge. Passive
components are too expensive to be fabricated on GaAs substrates. Often, they are fabricated on
microwave substrates, such as duroid, and subsequently integrated with active circuits. The
developed post-process allows flip-chip integration of external active components, as illustrated
in Fig. 3.33. Several distributed devices have been demonstrated with the CM-MEMS
technology. These include coplanar transmission lines, coupled lines, filters, branch line
couplers, Wilkinson dividers, phase delay networks and antennas. The main motivation behind
this work is the increased interest for satellite communications and K-band wireless
communications like LMDS. More recently, the development of low-cost phased array antennas
by using MEMS technology has become one of the major driving forces in this area [3].
Silicon CMOS substrate becomes extremely lossy at microwave frequencies. This
problem can be solved by selectively removing the silicon around the microwave components,
thus, electromagnetically isolating the components from the Si substrate. The first component
demonstrated was fabricated using a hybrid-etching technique [5]. The results show significant
improvements over unetched lines and performance comparable to that obtained by devices
fabricated on GaAs. In many respects, the micromachined coplanar transmission line (CTL) as
shown in Fig. 4.28 is preferable over the classical realization with a low-loss substrate.
Specifically, it is much less dispersive because the encapsulating layers create a nearly
homogenous environment for electromagnetic propagation. At the same time, the theoretical
formulation of propagation for such structures is more involved.
In this study, micromachined CTLs are analyzed considering both finite thickness
dielectric layers and finite thickness conductors, under quasi-static approximation and employing
conformal mapping techniques. More generally, a simplified approach to the calculation of
propagation characteristics of transmission lines is introduced for structures with comparable
cross-sectional dimensions. These theoretical results are compared with measurements and
numerical calculations.
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'ertical Walls
■ ■ ■ metal 1 (Al)l
- 3 Si substrate I
.1 Si02
Figure 4.28: Schematic cross-sectional view of a coplanar waveguide fabricated on a
CMOS chip using the hybrid etching technique.
Other passive microwave components that have been investigated can be listed as:
Filters: High-Q micromachined filters are one of our concentration areas. Currently, our
efforts is focused on the characterization of one of the crucial building blocks of filters,
namely, coupled coplanar waveguide. The theoretical, experimental and simulation results
agree very closely.
Couplers and dividers: Micromachined branch-line, coupled-line couplers, Wilkinson
dividers and broadband 180° hybrids are characterized.
Antennas: Several configurations of planar antennas, including coplanar and slot line flare,
bow-tie and dipole, have been successfully fabricated and measured.
Brief description of successful devices is given below.
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Coplanar Transmission Lines (CTLs)
Transmission lines are the most important building blocks for the construction of
distributed networks. Their significance has long been recognized, and they have been analyzed
extensively in each technology, such as microstrip, stripline, coplanar technologies. Particularly,
the coplanar transmission lines are investigated by several groups [90]-[98]. However, almost all
of the analytical treatment, until recently, assumes the presence of a high-dielectric-constant
substrate. This, together with low-resolution patterning techniques, makes the zero-thickness
strip assumption an obvious choice for subsequent analysis. Therefore, all of the previous
analytical techniques that rely on conformal mapping use the zero-thickness metallization
As illustrated in Fig. 4.28, micromachined transmission lines have practically no
substrate [97]. The effective dielectric constant for such structures is, generally, less than 2.0. To
achieve the necessary capacitance for characteristic impedance of 50 £2, the signal-to-ground line
separation must be decreased significantly. The resulting transmission line has very high
coupling at these gaps, and, most importantly, because of the proximity, the strip thickness can
not be neglected anymore.
In this section, supported and unsupported micromachined coplanar transmission lines
(CTLs) are analyzed under quasi-TEM approximation. New analytic approximations are derived
for the quasi-static capacitance and loss of coplanar waveguides with finite metallization
thickness. It is shown that neglecting the thickness of metallization in calculations may result in
significant error in characteristic impedance for the practical dimensions. Additionally, the
sensitivity of the characteristic impedance to the physical dimensions is considerably higher for
micromachined CMOS coplanar transmission line. The conductor loss of these structures is
investigated as a function of various physical parameters, such as thickness of dielectric
thicknesses. The analysis shows that the characteristic impedance value, which exhibits the
lowest conductor loss changes as a function of the dielectric layer properties. For micromachined
coplanar waveguides, the lowest conductor loss is observed around the impedance of 100 £2.
The proposed analytical expressions are well suited for CAD applications since they are
compact and scalable. Moreover, their accuracy is comparable with the fabrication tolerances
and measurement accuracy.
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For RF communications, two wave-propagation properties of micromachined CTLs are
especially important for a designer. These properties are the characteristic impedance and the
propagation constant of the transmission line.
The relation between the characteristic impedance of the line and its physical parameters
can be found with the quasi-TEM propagation approximation. Coplanar waveguides placed in an
inhomogeneous medium with conductors having finite conductance do not support the pure TEM
propagation, but, if the cross-sectional dimensions are much smaller than the operating
wavelengths then the amplitude of longitudinal field components become very small compared
to that of transverse fields [95]. For practical dimensions realizable in a CMOS technology, the
longitudinal fields in micromachined CTLs can be neglected (quasi-TEM approximation) for
operating frequencies below50 GHz. It should be noted that this approximation is equivalent to
assuming perfect conductors. Furthermore, we assumed the dielectric layers encapsulating the
micromachined transmission line are lossless in this frequency range.
The transverse field distribution can be found by the electrostatic formulation, simply,
solving the Laplace equation for the dielectric conductor system. One needs two capacitances to
evaluate the characteristic impedance of a CTL. These capacitances are the capacitance of the
complete structure (Cww/), and the quasi-static capacitance of the equivalent air-line structure
(C„r). Finally, the characteristic impedance, Zo, of a coplanar transmission line is given by the
following well-known expressions
is the speed of light and L is the inductance per-unit-length which is given by
L—l/(Cy Cair).
In this section, analytical results are derived for such structures based on conformal
mapping approach along with partial capacitance method. Because of the complex nature of the
problem, previous analytical methods for determination of CTL capacitance assume either zero
conductor thickness with finite thickness dielectric layers [89], [93], [94] or semi-infinite
dielectric layers with finite conductor thickness [95], [94]. These models do not suffice in the
case of the micromachined CMOS CTLs discussed in this work because of the encapsulating
glass and metal thickness, which cannot be neglected in comparison with other transverse design
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(a )
(c )
Figure 4.29: a) The line shown by with dash-dash in RQ-plane is mapped
onto real axis in ZQ plane, b) In this half-plane to half-plane Schwartz-Christoffel
transformation the coordinates in ZQ-plane can be found by using semi-numerical
approaches, c) An approximate method for the evaluation of capacitances is to
use partial capacitances corresponding to horizontal, and vertical surfaces and
comer discontinuity capacitance. The calculation of first two partial capacitances
is straightforward, but the last one is approximated with a nonlinear curve that is
obtained by curve-fitting the semi-numerical solution described,
dimensions. The calculation is carried out for finite thickness dielectric layers and finite
thickness metallization, and it is shown that, indeed, the thicknesses are important parameters,
which should be taken into account for characteristic impedance calculations.
On the other hand, the propagation constant, y, can be written as
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. 0 ) I----
r = a + j f i = a + j — yj £ eff
where the real pan, a, is the attenuation constant, the imaginary part, /?, is the phase constant,
and £eff is the effective dielectric constant. Since the effective dielectric constant is readily
available as the ratio of the two capacitances as %•= CfI)W//Cul>, we concentrate on the loss term,
a. In order find the loss, in this part of the analysis, we no longer assume perfect conductors, but
still keep lossless dielectric assumption.
In general, power might be lost due to dielectrics losses, conductor losses (also called
ohmic losses), radiation losses from parasitic modes a ruii, and coupling to surface waves a,K.
[94], In our case, the dielectric layers encapsulating the transmission line are very thin (<0.lXei)
pushing the cutoff frequency of the surface waves well into millimeter-wave range [93] and the
radiation losses are relatively small below millimeter wave frequencies. Since we also assumed
that dielectrics are lossless, we concentrate on the dominant loss mechanism at the frequency
range of interest, namely conductor loss:
a =a c
Quasi-TEM Approximation of Characteristic Impedance
Air capacitance of a CTL is defined as the capacitance when the dielectric constant of the
encapsulating layer (SiCK in Fig. 4.28) is set as £/=I. If the conductor boundary is conformally
mapped into a straight line as shown in Fig. 4.29b, either the resulting integrals should be
evaluated numerically or a system of nonlinear equations should be solved numerically [95],
[99], [100].
On the other hand, if we view C ^ r as consisting of three separate components as
illustrated in Fig. 4.29c, then the formulation can be simplified considerably. (Subscript Q stands
for quarter-plane, and air denotes that the particular capacitance is air-capacitance.)
L CnQair due to the horizontal surfaces
2. CvQair due to the vertical walls
3. CcQair due to comer discontinuity of conductors
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Figure 4.30: With partial-capacitance approach developed by Veyres and
Hanna [92], it is possible to calculate the individual capacitance contributions
from each layer in a multi-layered environment. For example, a coplanar
transmission line with two finite-extend dielectric layers can be decomposed in
three cases:
with infinite thickness, (£2 -£3 ) with thickness (hi+hptr), and (f/-£s)
with thickness {hi).
This is equivalent to treating the surfaces as zero-thickness CTLs and vertical walls as
ideal parallel plate capacitors. The only component that is hard to deal with is the comer
discontinuity capacitance. It becomes important when two main contributions are small (when a,
b, c are small and t «
a), corresponding very high impedances. For Zq < 150 Cl, CcQair is
assumed to be negligible.
The air capacitance of the horizontal lines can be found by
Here K(k) is the complete elliptic integral of the first kind, k is the argument and k ’ is defined as
k' = i]l—k z .
CvQair is simply
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a=24 |i.m. b=30 fun. c=l30 (i.m
•a 3
A n a ly tica l
N u m erica l
The thickness o f dielectric layers (hf=h u) (jam)
Figure 4.31: The calculated capacitances with analytical formulation
developed in this work. The formulations are verified with finite-elementformulation.
CvQair ~ e0
b —a
and finally the discontinuity capacitance is obtained by curve fitting approach:
CC(?<J,r = 0 .0 3 f0 (t + e - 5' / i )
The overall air capacitance for a general quarter CPW structure is approximately the sum
of the two capacitances [100]
K(k') + _ t
- 0.03(l+ e"5,/5)
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Capacitance with dielectric membrane
It is possible to calculate each contribution in dielectric-encapsulated case approximately;
hence, the total capacitance, Cww/, can be found by adding each contribution. The contribution
due to the capacitance due to horizontal surfaces (Ch) is easily found by using the same approach
as Veyres and Hanna in [92]. Let us first define the half-plane capacitance function C(h,e) for a
finite dielectric film of thickness h and dielectric constant of e (see Fig. 4.30 for a multi-layered
w ith
bi„ and a, are given by the transformation xh = sinh — for .t = a, b, c. CH is given in
terms of capacitance function as:
C H = [C (/i„ ,f|) + C(h / . £ \ )],
where the physical parameters a, b, c, t, hu, hi are illustrated in Fig. 4.28.
The contribution due to vertical walls and comer discontinuity is found by assuming all
the associated fields in the dielectric layer.
_ i _ + o.03(l+ e - 5,/' )
The total capacitances for a general symmetric CTL (in Fig. 4.28) can be summarized as:
Cwml =[C (/ja ,£ 1) + C(/l/ ,£ ,)] + 4C0f 1 —^— + 0.03(l + * 5,13
b —a
Figure 4.30 shows the computation results for CTLs with hu=hi=h for various
metallization thicknesses. The numerical calculations performed by using finite difference (FD)
method agree very closely with the results obtained from analytical results. Both of the
computation results indicate the importance of considering the conductor thickness at this realm
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Without approx.
With approx.
Gupta et al.
Zero thickness
with parallel plate
capacitor approx.
160 -
140 -
120 -
100 III
80 '
60 -
40 -
Figure 4.32: Coplanar transmission lines are analyzed with several
approximations, t/s and h/b are two important parameters to determine the
applicability of a given formulation. From the point of view of t/s, there are four
regions. In the first region for t/s < 0.002, the zero-thickness strips assumption is
valid. When 0.005 < t/s < 0.05, simple thickness correction formulas can be used.
In the fourth region, when 0.8 < t/s, then parallel plate approximation is
satisfactory. There is no formulation developed specifically for the 3 region. The
developed formulation is not only accurate in 3rd region but covers all four
of physical dimensions. The presented partial capacitance approach yields simple closed form
formulations that extends previous formulations to cover all four regions identified in Fig. 4.32.
This formulation stands as one of the most important contributions to the quasi-TEM CTL
Next the conductor loss of a micromachined CTL will be investigated.
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Figure 4.33: Conductor loss is calculated in terms of the current
distribution in the system. The current distribution on the surface of strips is
shown for the case of 3 < t. Because of the symmetry, the calculation considers
only one quadrant of the CTL cross-section.
Conductor Loss Calculation
In this section, the formulation to calculate the ohmic losses, in which the strip thickness
is assumed to be larger than skin depth, 3, and much smaller compared to the width of the center
conductor, a, and the separation between center and ground conductor, (b-a)l2, is extended to
deal with thick metal CTLs. If the strip thickness satisfies 3 5< t « a , (b-a)l2, we refer to the
CPW as "thin Film CTL"and similarly for 3 5< (b-a)/20 < t< a a s "the thick film CTL”.
The thin film formulation was originally developed by Owyang and Wu [91], and more
recently improved by Ghione [93]. In both cases, the power loss is calculated based on the
surface resistance approximation [101]. In this formulation, the conductor loss is given by:
where /?, is the surface resistance, I the total rms current carried by the line, J the longitudinal
current density on the line, and P corresponds to all the contours along the conductor surfaces.
By using the symmetry of the analyzed structure, this integral is integrated over the geometry
corresponding to a quarter of the CTL.
In Fig. 4.33, a representative electric field distribution for the whole CTL is given.
Because if the symmetry, the calculation is performed in for one quadrant shown in Fig. 4.34.
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Figure 4.34: Loss integral is taken between points I and 8. The position of
points 3 and 6 is given by the definition included in the text.
The dimensions of the sample are exaggerated to emphasize characteristics of the field
distribution for a general case. Notice that in Fig. 4.34, there is a region between the sidewalls of
two conductors where the E-field density is approximately uniform. The width of this region is
specified as the effective thickness, teg, and the rest of the area between the conductors where the
fields are not uniform is assigned to the comer thickness, tc. Finally, the field distribution
between top surfaces of the conductors is inherently non-uniform. Therefore, for a general CTL
structure, the field distribution can be viewed as a combination of uniform field and non-uniform
field areas. To distinguish these two field areas, we define a boundary between the two fields as
shown in Fig. 4.34. The position of this boundary can be found by a criterion which accounts for
the deviation from a perfect parallel plate capacitance which has a width of y' and thickness of
(b-a)/2. One possible definition for this deviation would be
% Deviation =
QrUf(y/)-gQg|2.v/ /(fc-a)
where y ’ is the width of the capacitor located between the sidewalls of the conductors (see Fig.
4.34), and Ctme represents the true capacitance corresponding to the specified area. Then, the
position of the field boundary (or equivalently the value of teg) can be found as the value of y ’
corresponding to certain %Deviation. As a result, it is possible to define, the position of such a
field boundary. In many practical cases, this boundary is very close to horizontal symmetry line,
in which case essentially no uniform field regions exists.
The true capacitance is calculated by using the charge distribution profile calculated by
mapping conformally the vertical area into a rectangle. After straightforward Schwarz104
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Christoffel mapping of real axis first into real structure and than into rectangle area, the
following charge distribution function is obtained (It is important to note that the fringe electric
fields are usually computed by including backside of the zero-thickness strips, in this case only
one side is used.).
which yields finite density on the edges. Employing this current distribution one may calculate
the real capacitance value.
An approximate boundary approach allows us to specify two points (3 and 6) at the
boundary along the sidewalls of the conductors. Then, following the notation given in Fig. 4.34,
the integration in Eq. 4.42 can be analyzed as follows:
where the factor 4 accounts for all the equivalent integration areas in the symmetric CTL. This
particular separation of the integration areas is attractive because it allows us to use well
developed thin film formulation [93]. The second and third integrals become negligible in the
thin film region, since teff ~ 0, but they turn out to be important when the strip separation
becomes comparable to the strip thickness.
Currently, there is no closed-form analytical expression available which expresses the
location of the boundary in terms of the physical parameters of the system. Thus, we decided to
use the maximum allowable thickness given by the thin film formulation to approximate the field
boundary. Since the published data suggests that the thin film formulation gives accurate results
for t< a, (b-a)HQ [93], [94], we assume that tc is smaller than or equal to C,=(b-a)/20. This
assumption is essential to get a closed form expression, since the general approach is analytically
unsolvable [95].
In order to assure that this condition is satisfied and at the same time to have a smooth
transition between the thin film and the thick film regions, we define the function/fr,£) as:
/ ( r , f ) = l /2 ta n h [ - A ( r- f )+ ll
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where the width of the transition region is controlled by the parameter A. We approximate the
comer thickness in terms of
'c = f M 'S ) + S
Before evaluating the integrals in Eq. 4.45 by using these definitions, the current densities
should be normalized. If we assume that the total current flowing trough the CTL as I, then,
because of the symmetry, the total current in one quarter of the structure (shown in Fig. 4.34)
would be /q=//4. Since the current density and charge density are related by the continuity
equation, the current density has the same functional form as the charge density [101].
Furthermore, by definition, the capacitance is linearly related to the total charge. Thus, we can
express the ratio of the amount of the current flowing over the section (I, 3) to the total current in
quarter section in terms of the capacitance values obtained in [100] as:
• rural
The proportionality constant, r, is used to scale approximately the loss contributions resulting
from uniform and non-uniform field regions. This scaling is performed below for the thin film
loss terms (corresponding to the non-uniform field)
a H = 4, —
-Z n l
J :‘" + T6 6—K"
The integrals in Eq. 4.49 are evaluated in [93] as:
au =
-x < 240;cK(A)Af(&,)(l —&2 ) \ a
In this expression,
it + log
4 ;z a ( l- £ )
te{l + k)
+— ;r +
r 4 *6 ( 1
rc (l + * )
is the effective dielectric constant, k=a/b and c is assumed to be
Similarly, the current density in the second and third terms in Eq. 4.45 should be scaled
by (1-r). In the evaluation of the power loss integral, we assumed that the electric fields are
uniform, which gives
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( 4 . 51 )
R5 J \ j f d l + j V | 2<//
a v —4, --------2Znl - 3-*4
1 ■’ )
2Z0I - {
86.8;r( I - r f
■Jf a Hz
where ac is the conductance of the metallization, and J ghz is the frequency expressed in GHz. In
this expression the surface resistance expressed using following expression
Under quasi-static approximation, since all other parameters areindependent
frequency, frequency relations for Eq. 4.50 and Eq. 4.52 can be summarized as
J J gh -
av = al} yjfcHz
(4 5 4 )
where a°n and a°v are appropriate constants. Finally, if two attenuation terms are summed, we
get approximate conductor loss term.
~ a H+av
= (a°; +cty )yjfci,:
dB / unit
In Fig. 4.35, the amount of contributions to cP from a°H and a°v are shown for a
set of values.
As expected the contribution from sidewalls vanishes for high
impedances wherethe thinfilm approximation is valid. At high impedances,the loss due to inner
sidewalls increases dramatically, and become dominating factor in overall loss. The loss
coefficient are calculated for CMOS CTLs as shown in Table 4.5.
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S et#l
Set #2
Set #3
Ctouiii Ann.)
C(0(b/( Meas)
dB/(cm (GHz)"2)
Table 4.5: CPW dimensions of experimental data sets and comparison of
computed and measured results.
The dispersion characteristics of CTLs improve significantly by micromachining and
according to the approximate theory presented here, the attenuation for most of the
micromachined CMOS CTLs will be very close to air-line values.
The examination of the conductor loss with the physical parameters suggests that the
micromachined CTLs have larger window for the low-loss operation. The value of the
characteristic impedance corresponding to the lowest conductor loss goes to higher values.
Therefore, standard 50 Q. micromachined CTLs are significantly more lossy compared to high
impedance CTLs. For a given impedance value, in general, the attenuation of a CTL can be
decreased by increasing b. Unlike the sensitivity of the characteristic impedance to the transverse
dimensions (r, hi, hu), the conductor loss depends slightly on these parameters for Zo< 150 Q.
Moreover, the dielectric constant of the surrounding layers does not change conductor loss
dramatically in the practical range of impedances given above. Finally, the use of high
conductance metals does not only improve the range of impedances, but also lowers the
conductor loss significantly.
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Characteristic Impedance, Zg, (Q)
Figure 4.35: Conductor loss factor of micromachined CMOS coplanar
CPW as a function of Zq for b=68 fan. The individual contributions (Xh and ccv°
are included appropriately scaled with parameter r. The conductor thickness
r= l.l5 {an and the dielectric layer thickness’ are hu=l.Q {an and hi=lA5 {an, with
£/=3.9. The aluminum metallization for the second level in 2.0 {on CMOS
technology has <xt—2.5xl07 S/m.
Analytical expressions for propagation characteristics of micromachined coplanar
transmission lines have been proposed. The expressions include the thickness of the conductors;
therefore, the effects of finite conductor thickness and finite dielectric thickness on the
characteristic impedance have been investigated. By using the proposed conductor attenuation
formulation, it was shown that the low impedances (-50 £2) exhibit significantly higher losses
compared to the high impedance values (-100 £2). The conductor losses can be lowered most
effectively by using larger ground to ground distances, b.
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^_axis of symmetry
. t.1
. . .
< ir-
a | ..
: * ! J2_
iv :
Figure 4.36: Cross-sectional view of the coupled coplanar section along x-axis. Stress
compensation layer and SiCri are shown with the dielectrics £ 1 and £2 , respectively.
Coupled Coplanar Transmission Lines (CCTL)
In this section, the quasi-static even and odd mode impedances of the CCTL structure
shown in Fig. 4.36 is derived based on the conformal mapping techniques. Because of the quasi­
static assumption, the impedance values can be calculated by evaluating two capacitance values
for each excitation mode. These are the capacitance when the strips are assumed in the air and
the capacitance in the presence of dielectric layers.
The coupled coplanar transmission lines (CCTLs) are one of the basic building blocks
used in various passive microwave structures [102]-[105]. As illustrated in Fig. 4.36, the
micromachined CMOS CCTLs consist of conductor strips surrounded with thin dielectric layers.
The assumptions mentioned above that are used in the derivation of the quasi-static formulations
with conformal mapping techniques such as described in [102], are not valid for the micromachined structures. Particularly, in many cases because of the low dielectric constant of the
dielectric layers, (c-b) or a, should be as small as possible to achieve the required odd and even
mode impedance values, which as a result increases the importance of the strip thickness.
Impedance Calculation
The air capacitances for the even mode can be obtained by
= 2 fo
—L -
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(4 .5 6 )
y (d
)(c - a
(4 -5 7 )
K(k) is the complete elliptic integral of the first kind, k is the argument and k' is defined as
k' =y j\-k : , and the parameters, a, b, e, d are the transverse dimensions of the CCTL as shown in
Fig. 4.36.
The exact solution for the air capacitance for the odd case is fairly complicated and
requires numerical computations if d is treated as finite. Therefore, for this case, we assume that
c « d . so that for practical purposes d can be treated as infinite, then the problem is reduced to
case given by Cheng in [106],
f t
c -fta
b y (c~ - a ~ )
On the other hand, in general, the capacitances in the presence of dielectric layers are
calculated with the "partial capacitance" approach [92]. In the even mode, this can be written as
l + e
0m [)
(Cl - 1 )
^ - + ( C t - 1)------- 7 —K C .
K(k'4 )
) ------ T~ +
K(k's )
C |--------
where the arguments kj, k4 and ks are evaluated with mapped a, b, c, d parametersby using the
same expression given in Eq. 4.59. The mapping is defined by
where x is a, b, c, and d and the mapping parameters for k3, ki and ks are h3, (hi+h2) and (hi),
The evaluation of odd mode capacitance in the presence of dielectric layers israther
complicated. The formulation given by Cheng for this case is modified as
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K(k )
CaJd =2£Q— p-+£Q(£l -l)F(ll3) +£0 (£1 -[)F(hl +ll1)
+ f 0Ur, - £, )F( h- , ) + £bf| — r + -
In Eq. 4.62, the function F(.) denotes the normalized capacitance found as a sum of
contributions from the ground plane and the electric wall on the symmetry axis. The calculation
of this function requires numerical evaluations and given in [106].
Then by using these capacitance values the impedances are calculated as (shown for the
even mode impedance)
z' - - L.y/ Lc air.even Lr even
In Table 4.4, the impedance values for several CCTL dimensions are calculated by using
the analytical formulation given above. Additionally, the structures are simulated by using a
commercial finite element electromagnetic simulation package (Maxwell by Ansoft Inc.).
The derived formulation has many simplifying assumptions that should be verified with
the numerical computations and the experimental results. The work especially concentrated in
understanding the effect of extreme conditions when the (c-b) and a are comparable with t.
In these cases the effect of metallization thickness become significant, for example, for
the 3rd data set if the strip thickness is neglected then the results would be 63.0 Q and 54.4 Q, for
even and odd mode impedances, respectively. In this case, the impedance values are off by more
than 10% from the ones given in Table 4.4. However, if we ignore the thin films designated by
thickness’ /t? and hj (in this work both are 1 (im) then the impedance values would change
insignificantly. This is because the thick hi dominates the response in these particular fabrication
settings. If instead hi was 20 pm and £i was 2.1, then the error in impedance calculation when
the thin layers are ignored would have been another 10 %. As a result, depending on the physical
parameters, it might be possible to ignore the strip thickness and the thin layers without
significant error, but in general the error in the calculation may be more than 20 % if these
assumptions are used.
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The other extreme condition when the a and b are much smaller than the c (assuming
2b<c), was studied with 5th and 6th data sets.
The micromachined CCTLs are studied extensively. The analytical formulas are
compared with numerical and experimental data. The agreement between results is very good.
However, for system implementations the transitions between CCTL sections should be
understood, as well. Furthermore, the attenuation characteristics of these structures should be
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Bond wires
Electrical probing
On-chip 50 Q
Figure 4.37: Micrograph of the Wilkinson divider before post-processinj‘g
Couplers and Dividers
The capability of the technology is demonstrated by using two devices. Especially the
ground equalization is a serious concern for coplanar devices. The power divider is fabricated by
very low-loop bondwires and the branch-line coupler employs novel internal ground equalization
technique. Detailed description of the devices are given below:
Power Divider
A broadband Wilkinson power divider is presented in CMOS technology as shown in
Fig. 4.37. The devices are realized by post-processing of chips that are fabricated in a standard
1.2 pm CMOS process. Proposed CM-MEMS fabrication includes wire bonding for ground
equalization, deposition of a stress-compensation layer and selective etching of the silicon
substrate. By employing coupled coplanar transmission lines, the area of dividers is minimized to
0.8 mm x 2.1 mm. A 20-35 GHz Wilkinson divider exhibits a coupling o f -3.8 dB ± 0.6 dB.
Cost-effective ways of fabrication of radio-frequency (RF) components and their
integration with analog and digital electronic circuits have become important issues recently with
the single-chip communications efforts [107]. In many cases, microwave active circuits, passive
microwave components and low frequency electronic circuits are fabricated in different
processes and integrated afterwards by using a chip scale integration technology [108].
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Thick Stress
Compensation Layer
Bond wires
CMOS Membra
Figure 4.38: Cross-sectional view of the post-processed CMOS chip with
enclosed bond wires and thick stress-compensation layer along x-axis.
In this section, a high-performance, low-cost Wilkinson power divider is presented. This
component is important for many applications including: high power amplifiers [109], signal
distribution networks [110], signal detection circuits [107], [111]. The presented divider structure
is very compact (0.8 mm x 2.1 mm) and exhibits a coupling of -3.8+ 0.6 dB over the frequency
range from 15 GHz to 35 GHz. In the same frequency range its predicted isolation is better than
15 dB.
To minimize the area of the power divider an approach based on coupled coplanar
transmission lines is preferred [105]. In this approach for 50 Q output ports, the desired even
mode impedance and the isolation resistor are 71 £2 and 100 £2, respectively. The isolation
resistor is realized by using 2nd level polysilicon of the CMOS process, which has an average
sheet resistance of 23.3 Q/sq. (see Fig. 4.37).
The mode impedance ratio of 1.6, r=Ze/Z„, which determines the bandwidth of operation,
is aimed. Then the cross-sectional dimensions of the coupled coplanar transmission lines as
illustrated in Fig. 4.36, are calculated by using thickness corrected analytical formulation (see
[106] for the calculation with zero-thickness metal strips). By taking into account of 1.2 itm
CMOS design rules, the dimensions (a,b,c,d) = (50,150,170,500) that yields the mode
impedances of (Ze,Z„)=(72.2 Q, 44.1 Q) are chosen. To minimize the conductor losses only 2nd
level metallization is used in the design.
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3 -20
-25 -30 -35 -
M easurement
S im ulation
Frequency (GHz)
Figure 4.39: Measured and simulated responses of the Wilkinson divider
Simulation of the final structure is performed on Sonnet em. The resistor is modeled as an
ideal high-resistive region with ideal contacts. The bond wires, illustrated in Fig. 4.38, used for
ground equalizations are also included in the simulations as 50 pm high 25 pm wide metal strips.
Fabrication with Bondwires
The devices are fabricated in a 1.2 pm 2poly/2metal analog CMOS process through
MOSIS service. The CMOS-fabricated devices are ground-equalized by using bond wires. Then,
the area that will be suspended is stress-compensated by using a single component, screen
printable polyimide, Epotek 600 (Epoxy Technologies). Curing is done in two steps. It starts
with a prebake at 150 °C for one hour and follows with a final cure at 275 °C for a 30 minutes.
This creates a fairly uniform, low-stress, low-k (£=2.4) dielectric film. The thickness of this layer
is controlled by the thickness of the stencil, but the minimum value that can be achieved is
dictated by loop heights of the wire bonds. Therefore, loop heights are kept to the smallest value
possible. Nonetheless, several different chips fabricated with different number of coatings. Each
coating adds approximately 100 pm thick film of polyimide. The results reported in this work are
from the chips with 5 layers of coating. Afterwards, the backside of the chip is patterned
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Figure 4.40: Frequency dependencies of three polysilicon test resistors Ri,
R2 , and R3 are measured up to 50 GHz. All three resistors are fabricated by using
2nd level polysilicon layer and have resistance of 63.6, 118.3, and 236.1 Ohms,
respectively, at DC.
photolithographically to expose the silicon only under the area that will be suspended. Finally,
the exposed silicon is etched by using XeFi. Fig. 4.38 illustrates cross-sectional view of a post­
processed CMOS chip.
All of the measurements are performed from the backside of the chips by using 50 GHz
HP 8510C Network Analyzer. SOLT (Short-Open-Load-Thru) calibration method is employed
in the probe tip measurements. During fabrication of the samples, one of the output ports of each
Wilkinson divider is terminated with a 50 £2 load by using bond wires. These termination loads
are designed right next to the output ports by using 2nd level polysilicon. As a result, all the
dividers are measured as two-port devices. The results shown in Fig. 4.38 exhibit good
agreement with the simulation results. Excellent divider characteristics are observed in the
frequency band of interest (20 - 35 GHz). The differences between measurement and simulation
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are due inaccuracies in bond-wire, dielectric and conductor modeling, ignorance of glass-Iayers
(shown with hi and h3 in Fig. 4.36), assumption of zero-thickness metallization and most
importantly due to probing difficulties in microwave measurements. CMOS pads are covered
with a thin layer of aluminum oxide that prevents high quality electrical contacts.
Isolation between output ports cannot be measured in the available test chips, since the
design is missing termination resistor next to input port. Bonding to an existing on-chip 50 ohms
termination is not possible because of the excessive distance to the nearest termination.
Therefore, we report only the simulation results for isolation. It is higher than initial estimations
due to variation in sheet resistance of polysilicon.
One of the difficulties with the fabrication of Wilkinson divider in CMOS technology is
that the isolation resistor can only be realized by using polysilicon available in CMOS processes.
The process-dependent variation in sheet resistance can be as large as 10 % from the mean value.
In this work, all polysilicon resistors are realized by using 2nd level polysilicon layer. In the run
from which the data in Fig. 4.40 is taken, the sheet resistance was 10 % higher than average. This
translates into 10 % increase in all resistors. The 50 Q terminations that are designed as 48 O and
measured as 52.1 Q at DC are used in the measurements and simulations. The isolation resistor
turned out to be 113 Q with contact resistances.
As expected resistor geometry is important at high frequencies. Parasitic effects are
minimized in 50 Q terminations by using the same width as for 50 Q transmission lines.
However, the width of the isolation resistor is determined by the impedance ratio of coupled
lines and the sheet resistance of poly layer. This results in undesired capacitive effects at high
frequencies as shown in Fig. 4.40 for the resistors Ri and R3 .
The frequency of operation can be extended without major changes of the structure. The
main limitation for the bandwidth of operation comes from the signal line to ground line
separation. Furthermore, when the metal strips are closely spaced, the analytical treatment of the
problem gets extremely difficult.
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Figure 4.41: Microphotograph of the micromachined Ka-band branch line
Branch Line Coupler
An internally ground equalized coplanar branch line coupler (BLC) is fabricated by post­
processing 2poly/2metal analog CMOS chips (see Fig. 4.41). The first level metallization is used
to equalize the ground planes at T-junctions of the coupler. Ground equalization is necessary to
suppress the unwanted coupled-slot-line mode propagation, however, since metal layers are
separated by a thin silicon oxide film, in the vicinity of the equalizers, characteristic impedance
of transmission lines varies considerably. Therefore, in the presented coupler, the signal lines are
compensated to improve return losses.
Fabricated CMOS chips are post-processed with a two-step procedure. First, a thick
polyimide film is screen-printed on the devices as a stress-compensation. Then, the silicon
substrate is selectively removed underneath the devices. The measured responses show very
good agreement with simulations. Fabricated devices exhibit return losses better than 15 dB and
maximum of 1 dB amplitude difference in the frequency range of 25-30 GHz. The phase
difference between the output port is less than 3.5°. The area is minimized by using L-shaped
lines to less than 1.6 mm x 1.6 mm.
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S u v s s o>m| viiSiiiion
A *
vicu .i:
Mela I I
Figure 4.42: SEM picture of the compensated membrane. Film thicknesses
are read from this picture. Metal 1-0.6 fim, Metal2~1.05 pm, Isolation 1-1.4 pm,
Isolation2~0.75 pm, Isolation3~0.45 pm.
High frequency technologies, such as microstrip, coplanar, strip-line, are usually
compared in terms o f the performance, cost and functionality of the systems that can be achieved
on them. Among these technologies, coplanar technology is praised mainly because it provides
low-cost access to ground [112]. However, this technology has other problems. Perhaps, the
most important of them is the existence of two dominant modes of propagation (coplanar
waveguide mode -CPW- and coupled slotline mode -CSL-) [112]. It has been shown that the
unwanted coupled slotline mode excited by asymmetrical discontinuities drastically affects the
CPW circuit performance [113], [114]. To minimize CPW-to-CSL conversion either equalization
by wirebonds or airbridges are preferred [112], [115]-[117].
In many cases, even small process variations in equalization can result in significant
changes in the response of a device. Therefore it is necessary to have highly accurate and
reproducible fabrication technique. Air-bridge technology satisfies all these requirements, thus it
is usually favored over equalization by wirebonding in high performance applications.
In this work, we explored a third option to equalize by employing an interconnect metal
layer to connect the ground planes passing underneath the signal line. This alternative is usually
dismissed in MMIC designs, since metal interconnect layers are separated by very thin layers of
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Figure 4.43: Illustration of a compensated ground equalization section
used in BLC. The bridge-like structure is 1st metal layer (Metal 1). The
discontinuities in the signal are symmetric with respect to Metal 1. Coplanar
transmission is symmetric and realized by using 2nd metal layer (Metal2).
insulating films. This changes the local propagation properties drastically. Similar concerns,
though less severe, have led to several studies on the effects of air-bridges on the wave
propagation [114]-[L17]. In the presented work, ground equalizations are realized with a metal
layer separated from coupler by 0.75 (im thick SiOi layer (Isolation2 in Fig. 4.42). Step
compensations are employed to improve return loss [115].
The internal ground equalization is demonstrated in the design of a branch line coupler
(BLC). Three dB 90° hybrids are widely used in microwave application such as balanced mixers,
amplifiers, PIN switches, detectors, and patch antennas [66].
The devices are fabricated by post-processing CMOS chips. Notable progress has been
made in post-processing CMOS chips to achieve operational passive microwave devices
integrated with CMOS electronic circuits and sensors. The devices are fabricated with
2poly/2metal 1.2 qm CMOS technology through MOSIS service. The SEM picture of the layers
of the process is shown in Fig. 4.42. Polysilicon thin films are used to realize on-chip termination
resistors. Afterwards, CMOS dies are post-processed by using two low-resolution masks (20 |J.m
minimum feature size and ±20 |im placement accuracy) to realize robust mechanical membranes
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■4— \letal2
Metal 1
Figure 4.44: One of the T-junctions showing compensated 2nd level
metallization and ground equalizers realized by Ist level metallization.
System Design
The micromachined BLC is designed by using the conventional approach. It consists of
two branches with characteristic impedance of Zo (assuming the port impedances are Zb) and the
remaining two branches with Z0/V2. All of the four branches are 90° long at the center
frequency of operation. In order to minimize the area of the BLC, the branches are laid out with
L shaped configuration as seen in Fig. 4.41. This allows a more efficient use of silicon area.
The physical length of the quarter-wave long lines is determined after microwave
properties of the micromachined CMOS membrane is measured. From the test structures
fabricated previously, effective dielectric constant is measured as 3.8.
50 Q. BLC system requires coplanar transmission lines (CTLs) with characteristic
impedances of 50 Q and 35.4 Q. The dimensions for these impedances are calculated by using
the thickness-corrected quasi-TEM formulation given in [100]. To minimize the conductor losses
at high frequencies, thicker one of aluminum interconnect layers (Metal2 in Fig.3.42) is preferred
to realize the CTLs.
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(pm) dB(mag) dB(mag) dB(mag)
Table 4.6: 3D em simulations show that T-junction is fairly insensitive to
the indicated parameters (d, /). Simulations are performed at 30 GHz.
The fourth port is terminated with on-chip 50 Q load as shown in Fig. 4.41. This load is
realized with the second level polysilicon (Poly2) and it is fully integrated with the system. It
should be pointed that polysilicon is not an ideal resistor material, since it exhibits power
dependent non-linearity especially after it is thermally isolated from silicon. This limits its use to
low power applications. Additionally, process variations in CMOS fabrication should be taken
into consideration. The data from the previous runs of the 1.2 pm CMOS process suggest that the
sheet resistance (/?Sheet) of Poly2 varies ±10 % from its mean value of 23.3 Q/sq. This variation
can be effectively zeroed by annealing after post-processing. We are able to lower the average
sheet resistance more than 30% by simple annealing procedure. Therefore, the design should be
performed by using the maximum value of /?she« rather than the mean value. The branch line
coupler is a particularly good device for the application of such an annealing process, since one
can apply DC power to the resistors through the bias port of the network analyzer without any
additional process.
Internal Ground-eqaalization
The first level of metallization (Metal 1) is used to realize the underpasses for ground
equalization. Since this does not require any additional processing, it is termed as the internal
ground equalization. Such an underpass is illustrated in Fig. 4.43.
Without a proper compensation, internal ground equalizers would cause considerable
increase in the return losses. To improve the return loss, the width of the signal line is adjusted
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Metal 1
Region I
Region II
Region III
Figure 4.45: Capacitance contributions from sources identified in Fig. 4.45
as a function of the length of the compensated section (/)• The width of the
equalizer and the transmission line are 15pm, and
pm respectively.
near the underpasses to lower the capacitance. Only three of the parameters, /, d, and w, can be
controlled by the designer and the rest are fixed for a given CMOS process (see Fig. 4.43).
In this work, the internal ground-equalizers are modeled as shunt capacitances. Since the
compensated length of the transmission line, /, is kept shorter than X/1 0 0 , this approximation is
accurate. Analytical calculation of capacitances is very difficult for the geometry considered in
Fig. 4.43. The strip thicknesses cannot be ignored. Therefore, a quasi-static 3D solver is used to
determine capacitances between various parts of the system. These simulations indicate that
there are four major contributions to the overall capacitance
as shown in Fig. 4.45.
For a fixed width of underpass connection (u«15 pm), two sets of simulations are
performed two observe the change in the Cge as a function of I and d. First, the width of the
signal line (d) is fixed to 10 pm, and / is changed from w to 4w. The results are plotted in Fig.
4.46. Although, in this case, the overall capacitance is dominated by C//.B in many cases, if I is
<2 vv then the contributions from C/.b and Cui-b become substantial. If />3 vv, on the other hand,
then C//.G should be considered as well. The parallel plate capacitance (Cpp) between the signal
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I (pm)
Figure 4.46: Ground equalizers are modeled with a shunt lumped
capacitance Cxe. Although, this quasi-static capacitance is dominated by Cu.g in
many cases, if / is <2 w then the contributions from C/.b and C///.s are substantial.
If l>3w, on the other hand, then C//.c should be considered as well.
line and the underpass is independent of 1 and constant as 7.1 fF. This shows that Cge is much
larger than Cpp.
In the second set of simulations, the length of the compensated section (I) is fixed to 35
pm and the width of the signal varied from 4 |im to 50 pm. The results are shown in Fig. 4.47. In
this case, the Q e/Cw ratio goes down from 3.5 for d=4 (im to 1.3 for d=50 pm. According to
these simulation results, when d<a/2, Cge is dominated by the fringe capacitances and as d gets
smaller these contributions increase.
To minimize interference to the CPW-mode propagation the ground equalizers should
have minimal overall capacitance. Our design criterion is to have at least 10 dB return loss at 30
GHz for a lossless transmission line, when it is equalized with 5 identical connections each
separated by 100 pm. This can be achieved if a single section has Cge < 16 fF for 50 Q
transmission lines. For (w,l,d) = (15 pm, 35 pm, 10 |im), this requirements is satisfied, therefore
it is used in the subsequent design of T-junctions
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40 -
30 -
20 -
d (p m )
Figure 4.47: Capacitance contributions from sources identified in Fig. 4.45
as a function of the width of the transmission line (d ). The width of the equalizer
and the length of the compensated section are 15pm, and 35 pm respectively.
Figure 4.48: Equivalent circuit of the T-junctions with internal groundequalizers.
T-junction Design
The design of T-junctions is important for the presented branch line coupler. The
schematic of the design with internal equalizers is illustrated in Fig. 4.48. From spectral domain
simulations, it is known that the equalizers should be very close to the discontinuity to minimize
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MoM Simulation
3D Quasi-static Simulation
-3.0 -
-7.5 -
-8.5 -9.0 -9.5
Frequency (G H z)
Figure 4.49: The T-junctions with (/,z/)=(35,10) for 50 Q and (35,20) for
35 Q are simulated by using the capacitances from a 3D quasi-static field solver.
If these results are compared with
‘/ 2 D simulation results (with zero-thickness
strips), significant difference is observed at frequencies above 10 GHz.
the mode conversion. Therefore (h is much smaller than wavelength at the center frequency
( 6 b<5°).
The considered T-junctions have 50 Q transmission lines in the first and third port and 35
Q lines in the second port. Quasi-static capacitances obtained from 3D simulation are used in the
simulations of the circuit in Fig. 4.48. However, these simulations with 0/,#?~4° do not include
the discontinuity at the junction. To include these effects, whole T-junction is simulated by a
2!/zD simulation package [63]. Although this package accurately predicts the overall response
prior the addition of equalizers, it underestimates the capacitance between the signal and ground
planes when the equalizers are included. This is a direct consequence of zero-thickness
metallizations used in the calculations. The results of these two approaches are compared in
Fig. 4.49. The difference between calculated responses is especially significant at high
frequencies, but both techniques predict around -3.6 dB S21 and -3.7 dB S31 at 30 GHz.
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35 Ohm
50 Ohm
50 Ohm
35 Ohm
Figure 4.50: Each subsection is simulated separately and then subsections
are simulated together.
■i 58
5 56
Frequency (GHz)
Figure 4.51: Measured and simulated response of an on-chip 50 £2
termination. The resistance exhibits approximately 4% deviation from the design
value because of process variation in CMOS.
Additional optimization of the location of the equalizers did not improve this results appreciably,
therefore we decided to use the design shown in Fig. 4.44.
Because of the memory constraints of the computer, the optimum T-junction, L-shaped
50 Q and 35.4 Q CTLs are simulated separately with high spatial resolution by Sonnet Em (2l/2D
simulator) [63]. The overall response of the BLC is obtained by using the resulting S-parameters.
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2 , -1 0 -
Frequency (GHz)
Figure 4.52: Measured and simulated response of the BLC when 3rd port is
These values are used as initial guesses in subsequent 3D em simulations of the Tjunction shown in Fig. 4.44. Optimization of return losses by using an em field solver requires a
considerable amount of sophistication because of software, computing power and memory
limitations. In practice, many simplifications are utilized to obtain reasonably accurate results.
During our simulations of the T-junction, zero-thickness metallizations and edge via connections
are used.
Simulations showed that overall response of a T-junction is fairly insensitive to the
variations in / and d. The results for various values of these parameters are included in Table 4.6.
They are surprising considering the significant amount of change in the quasi-static capacitance
in the simulated cases. For example, the first case in Table 4.6 has almost half of the static
capacitance of the third case, but the behavior of the T-junctions for both cases is essentially the
same. We believe the main reason for this is that the discontinuities at equalized sections are
symmetrical and much shorter than the wavelength of operation. Furthermore, the lack of
thickness in simulated metal layers results in underestimated fringe capacitances. This explains
the weak dependence to changes in the length /.
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2 , -10
S.. am
S,t sim.
— S.. am.
• s*3™
Sn Meas.
Sh Meas.
Frequency (GHz)
Figure 4.53: Two-port measured and simulated response of the
micromachined BLC when 3rd port is open. Measured response of 50 £2
termination is used in the simulation.
Because of the memory constraints, the optimum T-junction, L-shaped 50 Q and 35.4 Q
CTLs are simulated separately with high spatial resolution. The overall response of the BLC is
obtained by using S-parameters of these blocks. Fig. 4.50 illustrates the circuit used for this
The membrane that should be stress-compensated is usually larger than 1 mm x 1 mm in
size. 20 fim resolution and placement accuracy is enough to define such an area. Here, a screenprintable polyimide film, EPO-TEK 600, by Epoxy Technology, Inc. is used for the stresscompensation. A 100 pm thick polyimide film is coated on the area that will be suspended by
using a steel stencil. Each coating is prebaked one hour at 150 °C and followed by final bake at
225 °C for 30 minutes. This gives dielectric constant of 6.6.
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After stress compensation, the backside of the chip is patterned photolithographically to
expose the silicon substrate underneath the devices that will be suspended. Finally, the silicon is
removed by using highly selective isotropic silicon etchant xenon difluoride (XeFi). It takes 54
pulses o f 2 Torr-XeFi to suspend the BLC.
Frequency response of the BLC is measured with HP 85 IOC Network Analyzer. SOLT
(Short-Open-Line-Thru) probe-tip calibration is performed using calibration substrate in 0.1-50
GHz frequency range.
Three sets of measurements are performed on the BLC. First, 50 Q polysilicon
termination resistors are characterized up to 50 GHz. Later, BLCs are measured as two port
devices when the 3rd is open and externally terminated with on chip 50 Q load.
Low power measurements of the on-chip loads are shown in Fig. 4.51. Excellent match
between measured and simulated values is observed. The sheet resistance of the Poly2 is
measured to be 21.6 Q/sq. At high frequencies, as expected by simulations, inductive parasitics
First set of two port measurements is taken between ports 1 and 2 while 3rd port is left
open. These results are shown in Fig. 4.52. The simulation data is matched to measurement by
changing the capacitance at the open port. Acceptable level of match between measurement and
simulation is obtained for a 20 fF capacitor in parallel with 1 k£2 resistor. High reflection from
the first port is due to over-compensated comer shown in Fig. 4.52.
Finally, previous measurement repeated after the 3rd port of the device is wirebonded to a
50 Q load. The measurement data of the resulting two port device is shown in Fig. 4.53. In the
displayed simulations, measured response of the load for terminated ports used but the wirebonds
are not included for the 3rd port.
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2.5 -
0.5 -
20 21
24 25 26
Frequency (GHz)
Figure 4.54: Simulated magnitude and phase difference between 2nd and
3rd ports.
As shown in Fig. 4.53, the measurement agrees well with the simulation except the return
loss from the first port. This mismatch is mainly caused by the external termination of the 3rd
port. On-chip load used for this purpose was more than 200 Jim away, and the wirebonds used
two connect two components have significantly higher impedance than 50 £2. It is difficult to
include this section into the simulation since its exact geometry is not known and cannot be
repeated manually. Instead, in the simulations, we used 200 |im lossy 50 £2 transmission lines
and measured response of the load to simulate the termination at this port. Additionally, the first
port of the device has extended transmission line section, which includes an over-compensated
comer. Em simulations have confirmed that this comer contributes to the deviation observed in
Figs. 4.52 and 4.53. In future designs this section of transmission lines will be avoided
Measurements show that at the center frequency, the coupling to the output ports is
almost 1.5 dB less than desired 3 dB. Only small part of this loss can be attributed to equalized
and compensated T-junctions. According to em simulations, these junctions contribute less than
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0.3 dB to insertion loss at 27.5 GHz. The conductor loss for 50 Q. CTLs is characterized with
independent experiments. Data is curve-fitted with the following formula up to 50 GHz
Lossjo = 0 . 7 7 9 (dB/cm)
Accordingly, a quarter wavelength long 50 Q CTL has 0.37 dB loss at 27.5 GHz. This
includes dielectric, radiation and acoustic losses. The loss due to 5% mismatch in the loads is
negligible. Polysilicon resistors affect the bandwidth and frequency behavior of BLC more than
the insertion loss because of the inductive loading. The most important loss comes from the
mismatch at the first port due to over-compensation of the comer. The elimination of this
problem will give much better return losses and better than 3.8 dB coupling at 27.5 GHz.
Internal ground equalization by using an interconnect layer is shown to be a feasible
alternative to equalization by wirebonding and air-bridge. The micromachined BLC has better
than 15 dB return loss and isolation between the output ports and ±1 dB amplitude difference
over the frequency range from 25 GHz to 30 GHz. In Fig. 4.54 the simulated amplitude and
phase balance between the output port is shown.
The sheet resistances of polysilicon films vary due to process variation in CMOS. This
variation can be substantial, as much as ±10% from the mean value, for a typical CMOS process.
On the other hand, for some of microwave applications, terminations should have less than I %
resistance tolerance. Without annealing on-chip polysilicon resistors this level of tolerance is
extremely difficult to achieve. Depending on the thermal conductivity of the stress-compensation
layers, polysilicon resistors can be self-annealed simply by applying dc current. This process can
be controlled with high accuracy to lower the resistance to desired levels.
Additionally, the sheet resistance of polysilicon films increases with the applied power. It
is desired to keep the operation power much less than the power level used in the annealing
process. If the operation power on the polysilicon resistors exceed this level the annealing
continues further decreasing the sheet resistance. Thus, the polysilicon resistors are particularly
suitable for Iow-power applications, although it is possible to operate the resistors with a
constant resistance circuit, which stabilizes the resistance for a range o f power levels [20].
A 25-30 GHz internally ground equalized micromachined branch line coupler is designed
and fabricated by using 1.2 jim CMOS technology. Coupled slot-line mode propagation that is
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excited at T-junctions is suppressed by using first level metal underpasses, which are separated
by 0.75 |im SiOi from 2nd level metal. Capacitive loading due to these ground equalizers is
mitigated by using step compensation and high impedance CTL sections.
Planar and robust CMOS membranes are bulk micromachined after they are stresscompensated with a screen printable polyimide film (EPO-TEK 600). Membranes are suspended
by removing the silicon from backside of the chip by using XeFi.
We believe that this fabrication procedure along with the ground equalization technique
is a cost-effective way of fabricating CMOS analog/digital circuits integrated with passive
microwave components.
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The demonstration of traditional fixed-response microwave components by using CM-
MEMS is an important step towards proving the feasibility and capability of such a technology.
Moreover, these achievements open the door to circuit enhancements to achieve cheap, high
quality tunable microwave components. Traditionally, electronically tunable microwave
components have been realized using nonlinear crystals like YIG or variable capacitance
devices. Nonlinear crystals are expensive, slow, bulky and hard to integrate with a system, so
they are not preferable for low cost applications. On the other hand, the quality factors of the
variable capacitor components are not good enough for a high-performance system. The MEMS
technology offers electronically controllable mechanically tunable structures, which have very
high quality factors, and in the case of CM-MEMS, inherently integrated with the control
circuits. This option is the most exciting facet of this new technology. In this chapter, three
devices (tunable capacitor, mechanical switch and mechanical filter) are described that can be
used in various demanding communication applications.
Tunable Capacitor
Improvement in the quality of inductors is so dramatic that the variable capacitors have
become the limiting component in the LC-tanks. The best varactors should exhibit:
1. High quality factor.
2. High capacitance tunability (CmJCmn) over given voltage range (usually as low as
3. Uniform capacitance change.
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Hung at al. 1998
Castello e ta l. 1998
Andreani et al. 1999
Porret et al. 1999
Hui e t al. 1998
Eldridge e ta l. 1990
Young et al. 1997
Dec e t al. 1997
Wu et al. 1998
Feng et al. 1998
Quality Factor
0.8 pm CMOS
0.35 pm CMOS
24-47 © 3 GHz
17-33 © 1.8 GHz
1.5:1 © 3 V
2:1 © 3 V
0.8 pm CMOS
0.5 pm CMOS
20 © 2.4 GHz
>30 © 2 GHz
2:1 © 3 V
1.6:1 © 1 V
0.5 pm CMOS
>50 © 1GHz
1.3:1 © 3 V
1.0 pm SOI
8-12 0 1 GHz
2:1 © 1 V
11:1 © 1 0 V
1.16:1 © 5.5 V
1.25:1 © 3 V
GaAs (Custom)
CMOS (Custom) electrostatic MEMS
electrostatic MEMS
thermal MEMS
thermal MEMS
62 © 1 GHz
9.6 © 1 GHz
25 6 © 1 GHz
7:1 © 1 V
2:1 © 5 V
Table 5.1: Comparison of state-of-the art tunable capacitors.
4. Small silicon area.
5. Low power consumption.
Traditional Methods
Traditionally, tunable capacitance has been obtained either by junction devices or by Metal
(or Polysilicon)-Oxide-Semiconductor (MOS) capacitors. In both cases, floating devices are
obtained by placing them in separate wells.
Junction devices, such as P+/N' diodes, are used in reverse-bias. The applied DC bias
determines the depletion region and the capacitance of the device. The practical capacitance
variation for junction devices is poor, because the steepest change is obtained by forward-biasing
the diode. This is limited by the degradation of quality factor due to parallel conductance and by
signal clipping.
On the other hand, the MOS capacitance can be used in different regimes. Accumulationmode-MOS capacitors relies on the fact that the by the surface population (in the semiconductor
side) can be changed from accumulation ( C ^ ) to depletion (Cm„) by applying DC voltage
[119]-[121]. In inversion-mode operation, the capacitance change between strong inversion and
depletion regimes is exploited [122].
Current state-of-the-art
There has been great interest to obtain electronic varactors satisfying the specification given
above [119]-[128]. The results are summarized in Table 5.1. Perhaps, the most promising results,
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Figure 5.1: Electrostatic actuation is based on capacitive forces between
the plates. This can be used to move the upper plate, approximately 1/3 of the
original distance.
by using the standard CMOS have been announced by Porret et al. in [122]. They investigated
three different topologies by employing differential nature of VCOs. Quality factors more than
30 at 2 GHz are reported. The quality factors and tunability can be increased by changing the
process as well. Eldridge et al. showed that by slightly changing the doping profile, it is possible
to obtain 11:1 capacitance ratios [124]. However, the process changes rarely yield high-quality
devices [123].
Mechanical Tunable Capacitors
A new class of high-quality tunable capacitors has been emerging with the use of MEMS
fabrication techniques [ 125]-[ 128]. Microscale membranes and plates can be actuated either by
electrostatic or thermal forces. Simple air-filled, parallel-plate capacitors can easily be fabricated
by using these techniques. Usually, one of the plates is fixed on the substrate and the position of
the other plate is controlled by one of the actuation mechanism. There are two main actuation
principles that are widely used:
1. Electrostatic actuation [125]-[126].
2. Thermal actuation [127]-[128].
The maximum capacitance ratio (CmaJCmn) of micromachined capacitors depends on the
actuation technique. With electrostatic actuation, the distance between the plates can be
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Figure 5.2: Thermal expansion differences between two arms cause the tip
of the beam to move in the direction of cold arm. Although both of the arms are
made of polysilicon, their operational temperatures depend essentially on their
controlled in a very limited range. This gives maximum of 50% increase in capacitance value
(see Fig. 5.1) [126].
By using thermal actuation, much higher capacitance ratios can be obtained. Ratios up to 7:1
have been already demonstrated by using MUMPS process. Thermal actuation relies on the
expansion differences between two materials. Wu et al. and Feng et al. used the thermal actuator
shown in Fig. 5.2 [129].
Both of the arms of the actuators are made of polysilicon. Since they carry different
current densities, narrow arm gets hotter, therefore, it expands more compared to cold arm.
Consequently, the tip of the arm moves towards the cold arm. By cascading these actuators, it is
possible to move the top plate up to 2 (im in vertical direction. Feng et al. demonstrated quality
factors more than 250 for 0.1 pF capacitor at 1 GHz, However, their designs require relatively
large area because of the actuators. In addition, thermal actuators consume power during
operation unlike the electrostatic counterparts. Thus, this approach of actuation is not suitable for
Iow-power mobile applications.
Reported tunable capacitors are compared in Table 5.1.
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► Metal2
Metal I
Figure 5.3: A novel tunable capacitor with integrated thermal actuator is developed. The
physical parameters that are used in modeling are shown in topside 3D model of the capacitor
(a). The bottom-side view shows the heater underneath the bottom plate of the capacitor (b).
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Micromachined, Thermally-actuated Capacitor in CM-MEMS Technology
In this work, a new type tunable capacitor is introduced. The actuation is based on the
thermal expansion differences between different materials. This allows the integration of
actuators to the plates, minimizing the overall area. Additionally, with the described fabrication
procedure, these devices can be fabricated on CMOS integrated with electronic circuits
eliminating additional integration steps.
The proposed architecture for new tunable capacitors is illustrated in Fig. 5.3. In this
simple parallel-plate capacitor, top and bottom plates are realized by a thick, electroplated gold
film and the 2nd metallization layer (Metal2) of the CMOS, respectively. The top plate is
supported by the low-k polyimide layer, so it cannot move, whereas, the bottom plate is
suspended and free to move in vertical direction. As illustrated in Fig. 5.3b, a polysilicon heater
is placed underneath the bottom plate. Although this plate is supported by three arms (2 Metal 1
and 1 Metal2), for practical purposes, it can be analyzed as a fixed-fixed beam ignoring MetaI2
connection. The thermal isolation of this beam is critical to achieve highly efficient actuation.
When no power is applied, the internal stress of the thin-films causes the beam to buckle in a
well-characterized manner [130]. Direction of the buckling is determined by the stress
distribution in the membrane. If the field-oxide present in the membrane, it assures the buckling
toward the top plate. Fig. 5.4a shows a suspended beam. The profile of this beam agrees well
with the developed theory as shown in Fig. 5.4b.
Simple electromechanical description of the actuator is described in the following
section. Then, an equivalent electrical model of the tunable capacitor is given with an emphasis
on the quality of the capacitor. The de-embedding and parameter extraction is described in the
measurement section. Finally, further improvements of the tunable capacitor are discussed.
Fixed-Fixed Beam Thermal Actuator
A realistic description o f the actuator is very difficult because of the coupling between
electrical, thermal, and mechanical domains. Therefore, we assume that the bottom plate and the
heater can be described by a fixed-fixed beam (FFB) with a uniform cross-section.
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-4 00
-6 00
60 0
-8 00
-10 00
-11 8 6
150 0
100 0
250 0 283
y (um)
Figure 5.4: Surface profile of an actuated bottom plate, (a) 2D view of the
interferometric measurement, (b) Profile along y-axis and the predicted curve
Fig. 5.5 illustrates the simplified geometry considered in this work. It is very difficult to
treat the conformal thin-films shown in Fig. 5.6, therefore, a simpler profile is assumed. All the
SiCb layers are assumed to have the same mechanical properties.
After these simplifications, the deflection at the center of a FFB, Vm, as illustrated in
Fig. 5.5, can be calculated as [131]:
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Suspended Area
Figure 5.5: Actuated plate of the mechanical capacitor is modeled as a fixedfixed-beam (FFB). Views of the released beam from the topside and along y-axis are
shown. The maximum amount of deflection, at the center of the FFB is Vm.
P ass
Metal 1
Figure 5.6: Cross-sectional view of the FFB has a non-uniform profile, therefore,
it is very difficult to analyze. Instead, a simplified view is used to find the mechanical
stress in the film.
where t is the suspended length of the beam and the coefficient a0 is given by
a1 ,
fl° = 7 r ” T r ’
In this equation, the strain of the composite beam, e, is calculated for the no-power case as:
_ a _ f.-L
£ ~~E
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( 5 .3)
Meta 12
a (MPa)
E (GPa)
Table 5.2: Mechanical properties of thin-films. Measured valued of residual
stress, £7, Youngs modulus, E, and Poisson’s ratio are measured given in [132].
where L is the unreleased length of the FFM. The composite stress, <r, and Young’s modulus, £,
are approximated as follows;
£7=4, E = ~
✓ -£ < 7 ,
r = £ E ,- ,,
In Eq. 5.5, oi, r„ and £, are the stress, the thickness and Young’s modulus in the i'h film,
respectively (see Fig. 5.6). The longitudinal stress values for each thin film can be determined by
using integrated MEMS test structures on the same die [130]. Material properties are given in
Table 5.2.
When the power is applied the Eq. 5.2 should be modified in order to take thermally
induced changes. As a first order approximation, the temperature is assumed uniform over the
beam. This leads to
e = — +a-AT{p)
where a is the coefficient of thermal expansion (CTE) of the composite beam and AT(P) is the
temperature change in the beam when a power of P is applied to the polysilicon heater. The CTE
of the composite beam is approximated as
Perhaps, the most difficult part of the simplified problem is the determination of the
relation between AT and P[133]. The calculation of average
complicated boundaryproblem
that includes all types
temperature requires solution of a
of thermaldissipation
radiation and convection) and nonlinear behavior of the polysilicon. Therefore, in many cases,
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V W V \A - t M
Figure 5.7: Equivalent circuit of mechanical tunable capacitor.
empirical relations are used [133]. At small power levels, the relation can be described with a
linear relation as
where P is in mWs and y is aconstant with a unitof K/mW. This coefficient is yet to be
determined for 1.2Jim CMOS process used in this work.
Once the thermal effects are included in the system, Eq. 5.1 can be written as
^ = * 0 (P)-f
Based on this simplified treatment, we define the efficiency of a thermally actuator, yihenmi, as
The maximization of this efficiency is crucial for low-power applications.
Consequently, if y is known for a specific FFB, than Eq. 5.8 can be used to calculate V„,
the deflection at the center of a beam. This parameter alone determines the overall profile of the
FFB, which is given as [130]:
c(v) = - f - l - c o s f ^
The curve for P=0 is included in Fig. 5.4b for the fabricated systems.
Equivalent Electrical Model for the Mechanical Tunable Capacitors
Equivalent electrical model of a micromachined tunable capacitor is given in Fig. 5.7. In
this model, Rs is due to the resistive losses in the plates, Ls is the inductance of the strips and Cg
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V =6.2
Top plate
Bottom plate
y(m )
Figure 5.8: Capacitance per unit length on .t-axis is calculated by using parallel-plate
approximation. The plates are separated by the distance z(y). Plates have a projected width of a,
centered on the center of the beam.
is the parasitic capacitance between plates. A scalable physical model of the tunable capacitor is
developed based on the following assumptions:
1) Eq. 5.10 describes the beam profile accurate enough for OKPKPnuu, i.e. when Eq. 5.7 is valid.
2) Profile function in Eq. 5.10 is valid for every x.
3) The top plate is assumed planar and parallel to the chip.
4) Fringe fields contributing to capacitance C and Cx are assumed negligible.
5) All capacitances due to discontinuities are assumed small and neglected.
The capacitance can be calculated with the variables shown in Fig. 5.8. The calculated
profiles of the bottom plate for several Vm values are shown. In general, only certain portion of
the FFB may be covered with Metal2. Since maximum change occur at the center of the beam, a
length of a<L positioned at the center of the beam is assumed to be metallized. Then, the
capacitance per unit length along .r is given by:
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Figure 5.9: The non-linear profile of the bottom plate is critical in the
capacitor design, (a) Capacitance ratio increases with narrower plates, since they
see larger actuation on the average, (b) However, smaller the plate area, the
smaller the capacitance density.
j W ) dy
L -a
where the distance between the plates, z(y) is given as
where d is the distance between Metal2 surface and electroplated gold surface. Therefore:
c =-
{ d - V m). t a n ^ - ^
J d ( d - V m)
M d ~ vJ
-a rcta n
* J d ( d - V m)
The effects of parameters are calculated based on this equation. Fig. 5.9a shows the
calculation results for various values of a<L=220 pm. As expected the capacitance change is
maximum for narrow strips placed at the center of FFB. If the spacing between the plates, d, is
7.0 pm and the maximum deflection (at P=0) is 6.0 pm, are assumed 3.0 pm actuation at the
center can yield as high as 4:1 capacitance ratios. However, narrow strips have very small
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5 -
<1=7.00 pm
4=6.75 um
4=6.50 jim
—*• 4=6,25 pm
19 -
Figure 5.10: {d-Vnmax) is the minimum distance between two plates, (a)
Smaller minimum distances are necessary to achieve higher capacitance ratios.
(b) The capacitance density is weakly depends on this parameter.
absolute capacitance densities as shown in Fig. 5.9b, thus, to achieve large capacitances the area
should be increased.
The minimum spacing between plates {d-Vnuniax) is important parameter in these
calculation. A I pm of minimum spacing, used in this set of calculations, is very conservative.
One advantage of having large minimum distance is that the value of the capacitance can be
controlled more accurately.
Next, the minimum spacing between the plates is varied while the strip width, a, is fixed
at 80 pm. The normalized capacitance for a 3 pm actuation at the center is given in Fig. 5.10a. A
modest capacitance ratio o f 2.8 for d - V ^ ^ ^ l pm increases more than twice when the minimum
distance decreased to 0.25 pm. The change in capacitance density is not that impressive, it is less
than 30% for the same case as shown in Fig. 5 .10b.
Power requirements rather than the voltage determines the maximum actuation that can
be achieved in a system. The mechanical efficiency of the actuator is defined as
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( 5 . 14)
depends on the spacing between the plates, d-V,„. Accordingly, /mechanical of the actuator can be
optimized independent from /thermal, by decreasing the minimum distance between the plates.
Based on Eq. 5.13, capacitance ratios larger than 10:1 can be obtained with less than 3 pm
actuation at the center of the beam.
Performance of a tunable capacitor is limited by the parasitic components. Perhaps, the
most important parameter is the resistive losses in the system. With the increased area, not only
the resistive losses but also the parasitic reactive components become significant.
There are several different layouts that can meet a given set of requirement (C/mw,
Cmax/Cmin ratio and maximum available power to the actuator). The series resistance, /?„ is
calculated using the worst case estimates. By using the dimensions given Fig. 5.3a, the resistance
can be calculated as
= R n,p +
where Rc,muu:t is the contact resistance between the Metal2 and electroplated gold,
are the sheet resistances of the top and bottom plates, respectively. Since the space
between the plates is filled with air, the inter-plate losses can be neglected. This important
because the inter-plate losses is the dominant loss mechanism in junction and MOS-type
The sheet resistance of Metal2 is 0.03 Q/sq. The thickness of the top plate varies between
2 pm and 5 pm, consequently, the sheet resistance changes depending on the plating thickness.
The worst case, it would be 2.35xl0'8/2xl0'6=0.01 Q/sq. The contact resistance is more difficult
to estimate, however, for 40x40 pm2 contact area, resistance values less than 0.1 Q are regularly
obtained by commercial gold-bumping processes.
The series inductance, Ls, and the shunt capacitors, Q , are important to find the selfresonance frequency of the tunable capacitor. There has been no previous study reported, in
analytic calculation of these components. Here, only the self inductance of the metal strips is
calculated. The self-inductance of a flat-wire with length, I, width, w, and thickness, t, is given
by [134] as:
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+ 0.5 + 0.223:
£ « , / ( / , W,t) = 2 .0 x 10~3 • /• In
;5l - j
The total self-inductance is then calculated as
= ( l iW/(/, + d. w, ,r A“ )+ Lself(l2, a , t Au))+ (z,.w /(/, , vv, , f ’
Additional parasitic inductances such as discontinuity, coplanar waveguide mode, and
mutual inductances, may add up to a comparable value to the one obtained from Eq. 5.17.
Currently, there is no experimental verification is available to assess the accuracy of this
The capacitance to ground, Cs, is calculated for the bottom plate only. The calculation
assumes that the plate is planar, and the capacitance contribution from the top surface of top
plate can be approximated with the contribution from the same area of the bottom plate. The
quasi-static capacitance for a finite-ground coplanar transmission line is given as: [135]
where a is the width of the signal line, b is the ground-to-ground separation, c is the overall
width of the ground planes and I is the length of the transmission line. In this equation, K(A-) is
the complete elliptic integral of the first kind and k is the argument of the integral {k' is defined
) calculated by
If the physical parameters illustrated in Fig. 5.3a are used, Cs is found as
The quality factor based on this model can be written as
( 5 .21 )
qjC R s
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L (pm;
a (pm;
d (pm;
d~V (nmax (P**i)
/1 (pm)
12 (Pm)
C max (pF)
C maxiC min
Table 5.3: Two capacitors with identical capacitance ratios and maximum
The quality of such a device is conductor loss limited. Therefore, they are suitable for
high-frequency applications. For operation frequencies above 10 GHz, the sheet resistance in Eq.
5.15, is no longer valid. Nonetheless, by multiplying the sheet resistance by a frequencydependent term (e.g. ot/\ with appropriate constants a and fi), it is possible to extent the
formulation to higher frequencies. Additionally, the self-resonance frequency of a tunable
capacitor is important (it can be used at frequencies f « f c). It is given by
Planar inductors are usually limited by the self-resonant frequencies, because of high
parasitic capacitances. Mechanical tunable capacitors, on the other hand, have much simpler
geometry and smaller parasitic components. This allows a wider range of application for tunable
Example Design of a Tunable Capacitor
Requirements: Cmux=2 pF, CimJCmin= 10, Q>50 at 2.4 GHz and PnUu<5Q mW
Based on the simplified models of actuator and tunable capacitor, the capacitance ratio
and the capacitance value are maximized by decreasing the distance, {d-V^max). The distances
less than I pm is difficult to achieve with high yield. Therefore, from the fabrication point of
view, the thickness of the cavity, d, is chosen less than or equal to estimated Vnmax. This allows
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Figure 5.11: Tunable capacitor prior to post-processing fabrication. The
dimensions of the bottom plate are 50 pm x 200 pm.
very small or no separation under no-power condition. During operation, the actuator should be
always powered to assure the desired value of the capacitance. Therefore, although it is not
possible to fabricate devices with 0.1 pm minimum separation under zero-power, the equivalent
operation can be easily achieved under low-power operation conditions.
Two different realizations satisfying first two requirements are given below in Table 5.3.
Both of the realizations occupy larger than 0.2 mm' of plate area. They employ essentially the
same amount of actuation and high YmedwnicaiA quality factor for 50 at 2.4 GHz requires a series DC resistance of 0.66 £2 or smaller.
The resistances for these cases A and B are given as (/?twIMc,+0.321) £2 and (Rammer+0-121) £2,
respectively. Even contact resistances as high as 0.5 £2 is acceptable to satisfy the quality
requirement. This shows that the contact resistance may become the dominant factor in this
design. A surface cleaning is essential to obtain small resistance values. In a standard 2.0 pm
CMOS process, contact resistances of 0.55±0.15 £2 are regularly achieved for a 2 x 2 pm contact
area. In this case, the contact area is 40 x 40 pm, therefore, at least 10 times smaller values of
Ramtaa are possible. Even assuming Rcontact as 0.15 £2 the design A can reach quality factors as
high 70, and 170 at 2.4 GHz and 1 GHz, respectively. The design B has the quality factors of,
phenomenal, 122 and 293 at 2.4 GHz and 1 GHz, respectively.
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Y ^Y
Figure 5.12: (a) Parasitic elements due the pad and the transmission line
section that are used to de-embed the capacitance measurements, (b) De­
embedded s-parameters are converted into v-parameters to isolate the shunt and
the series branch of the parasitic components shown in Fig. 5.7.
Frequency response of the tunable capacitors is measured with a HP 85IOC network
analyzer. A SOLT (Short-Open-Line-Thru) probe-tip calibration is performed using calibration
substrate in the 0.1-50GHz frequency-range.
The calibration substrate is used to extend the reference plane to the probe tips. While
accurate for large structures is not sufficient for accurately measuring small devices and devices
on lossy substrate. If the series parasitics are negligible, a simple procedure, called y-parameter
subtraction, can be used to de-embed shunt parasitics. This requires one additional measurement
of the same setup with the DUT (device-under-test) replaced with the opens. Then, the yparameters of this measurement are subtracted from the measurement with the DUT. If the series
parasitics are not negligible, the setup with the DUT replaced with the shorts is used for the zparameter subtraction [136].
Figure 5.11 shows a tunable capacitor prior to the 2nd step of CM-MEMS process. In
order to obtain an accurate measurement of the tunable capacitor, the reference planes should be
extended approximately 200 pm toward the capacitor. A simple three-step method [136] or the
multiline calibration [137] can be employed for de-embedding these transmission line sections.
In both cases, additional test structures should be fabricated on the same die.
In this work, the de-embedding of the pads and coplanar transmission lines is performed
by subtracting the parasitics of corresponding transmission line sections (shown in Fig. 5.12a).
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M easu rem en t
M o d el
Frequency (GHz)
Figure 5.13: Measurement and curve-fit result for a tunable capacitor
under P=0 condition. The extracted capacitance is very small (5 fF) because
d=\QA pm is very large.
The calculation is based on the independent measurement and characterization of coplanar
transmission lines on the same die. The extracted RLGC model of the transmission lines is given
by R=6A Q/cm, L=2.84 nH/cm. G=0 S/cm. C= 1.09 pF/cm. These values are used to calculate the
lumped parasitics shown in Fig. 5.12a.
Two-port S-parameters for different various actuation conditions are taken in the 0.1-50
GHz frequency range. Since we are interested in the performance of the series branch, the yparameters of the de-embedded system used to isolate the series branch impedance. As illustrated
in Fig. 5.12b, -Y 21 represents overall response of the serial branch. The capacitance is given by:
The parasitic components, shown in Fig. 5.7, can be found by circuit optimization. By
using Sonnet 3D EM suite, an optimization process is performed for the preliminary data shown
in Fig. 5.13. The design has L=200 pm, a=200 pm and d=10.4 pm with VnunuLx=6.2 pm. This
gives a capacitance of 5 fF at P=0. The parasitics dominates the parallel plate capacitance. The
resulting curves for measurement and model for the first tunable capacitor is shown in Figs. 5.13
and 5.14.
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Voltage (V)
Figure 5.14: Measured capacitance change obtained from thermally
actuated tunable capacitor.
Tunable capacitors with unprecedented quality factors and tunability ratios can be
realized by post-processing CMOS dies. Particularly, thermally actuated capacitors have
enormous potential not only in low-frequency communication systems but also in high frequency
applications up to Q band frequencies. The integration of actuator and capacitor in very compact
area is essential for the high-frequency applications. Therefore, the presented thermal actuation
method is superior compared to the other thermal actuation methods.
Extremely high tunability ratios can be achieved with these systems, eliminating the need
for capacitor banks for tunable LC filters.
The biggest concern with the presented approach is the thermal efficiency of the actuator.
It was shown that even for the most challenging applications, 3 pm actuation is adequate.
However, more study is needed to determine the thermal efficiency for fixed-fixed beam
actuators. In a related study, it has been shown that the most dominant loss for a cantilever type
actuator is the natural convection from the surface of the beam [138]. The convection losses can
be virtually eliminated by operating under vacuum conditions (<50 mTorr). The next important
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source of thermal loss is the conduction through the metal connections. Several improvements
are in development to minimize the conduction losses, as well.
The second important concern is that the temperature distribution on the bottom plate
may not be uniform, especially, for large capacitances. Although the improvement of thermal
efficiency will alleviate this problem, additional design changes should be made to assure the
uniformity of temperature over large areas. The maximum temperature should not exceed 500 °C
during the operation to prevent the aluminum thin films from melting. The desired actuation
must be accomplished with approximately 400 °C change in the beam temperature.
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Mechanical Switch
Switches are widely used in various communication applications to select antennas or to
isolate transmit and receive paths. The best switches should exhibit:
1. Low-loss transmission in ON-state.
2. Very high isolation in OFF-state.
3. Broadband operation.
4. High-power handling.
5. Low-cost fabrication and integration.
6. Low-power consumption.
Traditionally, switches are realized by using FET and PIN technologies to satisfy these
FET Switches
Principle of operation
When no gate bias is applied, the channel is open except for the zero-field-depletion-
layer thickness. Hence, for current levels less than the saturated channel current, /</„, the FET can
be modeled as a linear resistor.
When a gate voltage Vc is applied between gate and source so that |Vc|>|VH the channel
can be completely depleted of free charge carriers as shown in Fig. 5.15. Under this bias
condition, The FET can be modeled by series and parallel combination of resistors and
No Gale Bias
|V,J > |V ^
Figure 5.15: FET switches operate by controlling the channel resistance
via applying DC voltage to the gate of the transistor.
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4 tP
— 11— 1
0.5 4.0
21 pH
- ^ m
4 fF
r -
21 pH
H--------- 1
0.5 Q
2 IF
V-=-10 v
0.46 V
Figure 5.16: Small signal equivalent models for PIN diodes fabricated by
Alekseev et al. [148].
In either state, virtually no dc bias power is required. Therefore, switches can practically
be classified as passive as far as the overall power consumption is concerned: this leads to
enormous simplifications in driver requirements [139]. Although the FET itself is a threeterminal device, the switch is bi-directional.
Current state-of-the-art
The parasitic capacitances limit the performance of FET switches. However, this limitation
can be minimized by utilizing several design techniques [140]-[144]. Perhaps, the most
promising of all is a technique called "quarter-wave shunt design", in which the FETs are placed
quarter-wave away from the through signal line [144]. This greatly reduces the parasitic
modeling difficulties encountered in the traditional shunt architectures. A summary of current
state-of-the-art FET switch designs is given Table 5.4. Currently, insertion losses slightly higher
#of Stages
F. Range (GHz)
Isolation (dB)
Input RL(dB)
Output RL(dB)
Schindler et al.
unterm. SPOT
unterm. SPOT.
> 20
unterm. SPDT
< 3.2
> 23
Ingram et al.
unterm. SPDT
X/4 shunt
> 12
> 12
Ingram et al.
unterm. SPOT
X/4 shunt
2 @ 40 GHz
10 @ 40 GHz
13 @ 40 GHz
Table 5.4: State-of-the-art FET switches.
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> 10
> 12
# o f Stages
F. Range (GHz)
IL (dB)
Isolation (dB)
Input RL(dB)
Output RL (dB)
U. Mich
Bellantoni et ai.
GaAs (vertical)
unterm. SPDT
< 1.5
Teeter etal.
unterm. SPST
Kobayashi et al.
GaAs (vertical)
unterm. SPDT
2 shunt/1 series
> 45
> 15
Alekseev etal.
InP (vertical)
unterm. SPDT
> 25
Table 5.5: State-of-the-art PIN switches.
than 1 dB and isolations more than 35 dB is possible in relatively widebands up to center
frequencies of 50 GHz.
PIN Switches
Principle of operation
PIN-diodes are used in forward and reverse-bias operation conditions to obtain the desired
impedances similar to FETs. Equivalent electrical models for a high-performance PIN diode is
shown in Fig. 5.16. When the diode is forward biased, the intrinsic region becomes a lowresistance channel (4 G in the model). In the high-impedance state, the diode is reverse biased,
resulting a capacitance (2 fF in the model) in the intrinsic region. The other components shown
in the model are parasitics of the PIN diode.
Current state-of-the-art
PIN diodes have excellent characteristics for high-power, low-loss applications. Several
switches based in PIN diodes have been reported with frequency of operation ranging from dc to
90 GHz [ 145]-[ 148]. The performance of these switches is summarized in Table. 5.5. The most
important drawback of this technology is the need for complicated fabrication processes.
Because, the performances are obtained with a vertical PIN fabrications [147], [148], and they
make extensive use of non-standard techniques. These fabrication techniques allow the
optimization of intrinsic layer thickness for specific needs as well as addition of air-bridges to
minimize the parasitics [145], [147], [148]. Consequently, insertion losses approximately I dB
and isolations more than 40 dB up to 50 GHz become possible. It is possible to use HBT
technology to fabricate vertical PIN diodes. In fact, Teeter et al. have demonstrated the first
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# of Stages
F. Range (GHz)
Isolation (dB)
Input RL (dB)
A ct Vol (V)
U. Mich
U. Illinois
Z J. Yao et al.
Hi-res Si, Al
shunt, SPST
35 @ 40 GHz
Hyman et al
GaAs, Au
series, SPST
J. J. Yaoetal.
GaAs, Au
series, SPST
< 0.5
> 25
Pacheco et al.
Hi-res Si, Au
shunt, SPST
< 0.4
> 20
GaAs, Au
shunt, SPST
Table 5.6: Comparison of state-of-the art mechanical switches.
Electrode Dielectric
Figure 5.17: Shunt-type, electrostatically actuated SPST switch operates
with very high capacitance ratios between two states.
monolithically integrated PIN diode by using HBT technology [146]. They used the lightly
doped collector region as the intrinsic region of the diode.
Mechanical Switches
Principle of operation
The mechanical switches rely on the actuation of a membrane to achieve high and low
impedance states. In is illustrated with a shunt fixed-fixed-beam (FFB) design in Fig. 5.17. When
there is no power applied, the beam can be modeled as an air-bridge with very small capacitance
to ground. Essentially, this eliminates the losses in ON-state. When the membrane is pulled
down the shunt capacitance increased as high as two orders of magnitude depending on the
dielectric thickness. It is possible to remove the dielectric between the bottom electrode and top
electrode (FFB), in which case the through signal-line (bottom electrode) can be shorted.
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Therm al
Type-1 l-a
Type-1 l-b
Table 5.7: Four switch configurations are investigated.
Current state-of-the-art
Several different mechanical switches are demonstrated [149]-[ 153]. Since careful control of
the membrane position is not necessary for switch applications, electrostatic actuation is the only
actuation technique that has been used. Arguably, the most attractive features of the mechanical
switches are their extremely Iow-loss and very broadband operation. This is evident with the
comparison given in Table 5.6. The insertion losses less than 0.15 dB and isolations higher than
35 dB in the frequency range from dc to 40 GHz has been demonstrated [149], [150]. It should
be pointed out that this level of performance is attained by using a single device. Additional
improvement in the isolation performance can be readily obtained by utilizing multistage
architectures [140].
When an AC voltage is applied to the switch at frequencies much less than the natural
frequency, the membrane follows the ac waveform. This behavior is not observed when the
frequencies much higher than the natural frequency, instead, it responds to root mean square
value of the voltage. Therefore, the mechanical switches are inherently linear unlike the active
There seems to be three issues that should be resolved before this technology is accepted by
the mainstream applications.
1. Actuation Voltage: The necessary actuation voltage is very high for CMOS applications. The
next generation systems are designed for supply voltages as low as 1 V. The lowest
actuation voltage reported as 16 V [152], [153].
2. Reliability: This concern has been diminishing with the recent reports that accelerated tests
are not yielding any failures. Even after 500 million switching cycles, no mechanical failure
was detected in shunt FFB switch with aluminum membrane [149]. Similarly, no
degradation in switch performance has been observed after more than 1 billion cycles for a
cantilever-type beam [150].
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Suspended Area
Figure 5.18: Topside view and cross-sectional view along .t-axis for a thermally actuated
cantilever. Polysilicon is used as a heater and differences in thermal expansion coefficients
cause the beam to change its curvature.
3. Fabrication and integration: The compatibility of fabrication techniques to standard CMOS
process remains to be a problem. In all of the processes, the starting material is a high
resistivity substrate. Then, the membrane is formed on top of a sacrificial layer either by
electroplating or by sandwiching several layers.
Flip-chip techniques are also used for integration purposes [154], [155]. Although,
these techniques seem to be best to obtain the optimum performance and low-cost, the
reproducibility remains a serious concern with the integration of mechanical structures.
Proposed Switch Implementations
Several switch architectures are considered for various microwave applications including
Iow-power applications and reconfigurable networks. The fabrication is based on the post­
processing of CMOS chips developed in this work. This will be the first time integrated
mechanical switches that are demonstrated in CMOS with integrated active circuits and low-loss
microwave environment.
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P a ss
M etal2
S 1O2
16 pm
12 pm
12 pm
12 |im
M etall
Poly 2
16 (im
Figure 5.19: Cross-section view of the fabricated cantilevers along y-axis.
Four possible configurations of beam structures and actuation methods are investigated as
listed in Table 5.7. Both shunt and series configurations of these switches are possible.
Principle of operation for thermal actuation
Operation principle of a fixed-fixed-beam actuator is explained in previous section. A
thermally actuated cantilever works essentially the same way. As illustrated in Figs. 5.15-5.19, a
polysilicon strip is used to heat the beam. Increased temperature generates mechanical actuation
in the perpendicular direction to the substrate. In a beam fabricated through CMOS process, the
generated heat usually causes the beam to buckle toward the substrate.
Cantilever type thermal actuators are particularly well suited for switch applications.
Very high actuation can be obtained at the tip of the cantilever with relatively low input power.
The profile of a given beam is determined by several factors: input power, pressure, and
material properties. The temperature distribution along the beam is one of the critical parameters
in determining the profile. It is rather complicated to compute because of the complicated
relations between nonlinear nature of the heat generation, loss, and material properties. It has
been experimentally observed that, at low power levels at I atm pressure, the beam profile can be
described by second-order polynomials. Depending on operation conditions, beyond certain
input power, the temperature distribution can not be described a linear function after which third
or higher order terms should be used to characterize the beam profile.
Extensive experiments with the beam geometry shown in Fig. 5.18 are performed [138].
Various other configurations are under investigation as well.
The designs are simple pull-down switches to characterize the capabilities of the
developed CM-MEMS Technology. The process allows fabrication of two different coplanar
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transmission lines (CTLs), namely, aluminum lines inside a CMOS membrane and electroplated
gold lines supported by polyimide film. All of the presented designs are realized with aluminum,
except the Type-O-a switch. All the beams are realized with CMOS layers, whereas plated gold
is fixed with supporting superstrate.
In contrary to common trend in the mechanical switch fabrication, in the presented
architectures the added gold structures (cantilevers or fixed-fixed beams) are fixed. This should
not thought as a limitation of the CM-MEMS technology, in fact, there are various modifications
that can be done without adding a new mask that can be used to release the gold films.
The developed architectures for mechanical switch operation are new. In the sense that
they are the first ones fabricated in a CMOS medium without any flip-chip operations. The
switches based on electrostatic actuation share the same principles with previously demonstrated
switches in the literature. However, the thermally actuated switches are the first switches shown
with beam structures. Therefore, we believe that these switches are not only novel because of the
their fabrication but their operation principles as well.
The reliability of mechanical switches is the most important concern in demanding
applications. In our experiments, we had difficulty in fabricating some of the electrostatically
actuated switches because of the required high-aspect-ratio. Therefore, no measurements will be
reported in this work regarding their performance. On the other hand, the thermally actuated
cantilevers are characterized extensively, both under room operation conditions and under
vacuum conditions. It has been observed that if the polysilicon heater is annealed at elevated
with high power prior to test, and the operation power is kept less than less than annealing
power, no change is observed in the quality of the beam performance in a week long test.
The operation of thermal actuators depends on the mechanical and thermal properties of
all the thin films that form the movable beams. It is reasonable to expect different properties
from different processes, as well as slight variations between different runs of the same process.
Such variations should be considered in the design to get the desired performance.
The fabricated samples of shunt Type Ila switches with thermally actuated cantilever is
described in detail without including any modeling. Other architectures are still in development
and are topics of future research.
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Bias Pad
Figure 5.20: Proposed layout of Type-Ia switch. The contact pad on FFB
shorts two signal lines.
Some of the best results for mechanical switches are reported for electrostatically
actuated cantilevers [150], [151]. In both cases, to minimize the contact losses, gold
metallizations are preferred. In addition, the signal lines are fixed, and membrane is actuated
either by a separate electrode or by using a ground-plane of the CTL. This kind of operation can
be accomplished with the proposed process only if the CTLs are fabricated with electroplated
gold layer.
This particular architecture is only architecture that has not been fabricated by using the
CM-MEMS technology.
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Figure 5.21: Type-Ib series switch prior to post-processing. This design
requires high-resolution patterning.
Perhaps the most popular electrostatic mechanical switch use FFB developed by
Raytheon/TI [149]. This type of switch is realized very easily, if the CTL and the membrane are
not on the same plane. However, if both of these parts are fabricated on the same plane, the
design becomes very complicated. Fig. 4.21 shows such a design, where the actuator electrodes
are realized with plated-gold. This particular design requires relatively small features to be plated
with gold. Therefore, the yield of fabrication is low compared to the other switches.
This switch architecture can be improved in two ways:
1. Increasing the aspect ratio of the gold features.
2. By using two gold metal layers instead of one.
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Figure 5.22: Micrograph o f Type-IIa switch prior to post-processing.
Figure 5.23: Micrograph of shunt-Type-IIa switch prior to post-processing.
Thermal actuation is not very popular with switch designs, because of its continuous power
consumption. Nevertheless, they might become important for high power applications.
Cantilevers are thermally more efficient than the fixed-fixed beams, therefore, more compact
switches can be realized. The switch, shown in Fig. 5.22, can be post-processed by using two
different sets of masks to get series or shunt switches. These switches are explained in detail in
the next section.
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Figure 5.24: Micrograph o f Type-IIb switch prior to post-processing.
Two types o f shunt FFB switches are fabricated. The first one, shown in Fig. 5.23, is
constructed with an air-bridge on the signal line. When no power is applied, the FFB will short
the signal line, otherwise, it will be modeled as a shunt capacitances. With slightiy different post­
processing, this device can be fabricated either as a shunt type-O-b switch, or series type-O-b
The second architecture uses a part of the signal line as a FFB actuator. A meander type of
heater can be seen on the signal line in Fig. 5.23 This configuration is very attractive because of
continuous signal line, it gives one of the lowest insertion losses. The air-bridge between ground
planes is plated, and without the power, the device will be shorted to the ground. When the
power is increased, the contact between the air-bridge and the signal line will loose. It is very
similar configuration to electrostatic, shunt, type-1-b switches, except that the actuated part is
signal line instead of air-bridge.
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i^ g o ld
Metal 1
Figure 5.25: Series (a), and shunt (b), Type-II-a switches that can be
fabricated with the design given in Fig. 51. The illustrations on the left show the
view from the topside and the ones on the right show the view from the bottomside.
Thermally-actuated, cantilever type, microwave switches (Type-II-a)
The operation of switches are very similar, as an example only type-Q-a switches are
discussed. The CMOS layout given in Fig. 5.22 can be post-processed to fabricate either series or
shunt switches as illustrated in Fig. 5.25. In the first case, the cantilever is controlled to have
contact with signal line via electroplated gold. Whereas, in the second case, it is essentially a
one-port device and the termination of the port is either open or short depending on the applied
power. Both cases require very small contact resistance during contact and very small
capacitance in OFF-case.
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•448 3
400.0 ■
350 0 ■
13 00
10 00
300 0 •
250 0 200.0
7 00
Si e n a l
4 00
150 0 ■
toco ■
500 00
Bi as P a d
-3 02
1 00
500 0
604 4
-11 00
-14 00
R e l e a s e d be am
■16 24
50 0
250 0 283 1
Figure 5.26: Interferometric measurements of the shunt Type-II-a switch
fabricated, a) The view from the topside before the seed-layer is stripped, and b)
the view from the bottom-side after the device is fully fabricated.
A high quality contact can not be guaranteed, if one of the contacts is aluminum. On all
aluminum surfaces, a thin layer of aluminum oxide forms, lowering the quality of contact
considerably. Fortunately, for microwave signals, large capacitances are acceptable, as well. In
fact, some of switches do not have metal-to-metal contact, eg [149]. On the other hand, other
designs employ gold-to-gold contacts because gold has the greatest documented resistance to the
formation of insulating tribocompounds [150]. In the experiments, the contacts on the CMOS
membrane are aluminum, whereas the plated-gold has very thin chromium layer at the bottom
surface of the bridges.
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a. -3 -
x (nm)
Figure 5.27: Profile of the released cantilever shown in Fig. 55b. The
buckling is toward the electroplated air-bridge.
Figure 5.26a shows non-contact surface profile of the top-surface before removal of the silicon.
The cavity is defined with the sacrificial photoresist. In this case, the thickness of this cavity is
more than 10 [im. The released cantilever is shown in Fig. 5.26b. The profile of the beam shows
that it is curved toward the electroplated plate.
Despite the non-uniform cross-sectional profile the profile can be described with a second
order polynomial function as shown in Fig. 5.27. The maximum deflection at the tip of the beam
is 6.2 [im. In this particular example, since the cavity is thicker, no-contact is observed even in
maximum deflection case (when no power is applied). Additional devices should be fabricated to
characterize the contact and switching properties.
A common measure used to compare switches realized by using different technologies is
to use the cut-off frequency defined as
fc =
'L'X'Ron 'Caff
where Ron is the resistance in ON-state and C0ff is the capacitance in OFF-state of the switch. A
comparison based on this criterion is shown in Table 5.8. It is clear that mechanical filters are
better than active switches (PIN and FET). In general, PIN switches have second place, since
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Table 5.8: Comparison of switch technologies in terms of the cut-off frequencies.
they have lower insertion losses and distortion than FET switches [156]. This criterion covers
first three requirements for a good switch. The last three is discussed next:
1. Power Handling Capability: Although electrostatically actuated mechanical switches are
linear, they cannot handle high powers because of RF induced switching. This is a direct
consequence of their electrostatic nature. One of the critical properties of electrostatic forces
is that they are always pull. When a high power RF signal is applied, the rms voltage
between two electrodes might exceed the threshold voltage and cause the switch to close.
Such unwanted state changes can be avoided only by making sure that the rms value of
maximum RF power is less than the threshold voltage. However, this would certainly
translates to higher actuation voltages, which is not desired, either. On the other hand,
thermal actuators are inherently less susceptible to this effect.
2. Cost of Fabrication: This is very important factor for many applications. At first, FET
switches may seem to be the cheapest, since they do not require any additional processing
steps and fully-integrated with other circuits. HBT PIN technology can be considered next
best option, with a similar argument [146]. And almost certainly non-standard PEN
fabrication technology is the most expensive one (see Fig. 5.28).
Nevertheless, a re-examination of FET switches shows that a multistage FET switch
might be quite large (5x2 mm Q-band switches in [144]). If this is compared to the cost of
mechanical switch, it can be seen that MEMS switches are almost 100 times cheaper than
FET switches [150]. This does not include any integration cost required for MEMS devices.
3. Power Consumption: Due to capacitive nature of this type of actuation, the switches do not
require continuous dc current for operation. This makes them very attractive components for
low-power applications. Electrostatically actuated switches consume power only during
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Figure 5.28: Vertical PIN diodes with air-bridge connection require very
sophisticated fabrication technology [148].
switching, like CMOS inverters. On the contrary, thermally actuated switches require
constant dc power during OFF-state, like NMOS switches. Their application is limited with
their thermal efficiency.
Additionally, mechanical switches can be biased by using simple resistive networks,
unlike PIN switches, which need complicated biasing networks.
Mechanical switches are very good switches except the power handling difficulties. With
the solution of that problem, these components have a potential to be used in various
demanding applications.
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Figure 5.29: Intermediate frequency (IF) filters are necessary to filter
closely spaced channels.
Mechanical Filters
Perhaps, the most critical component in the quest of single-chip transceiver is a high-
quality channel filter illustrated in Fig. 5.29. The European mobile communication systems,
GSM and Personal Communication Networks (PCN), call for passband widths of 200 kHz. The
IF frequencies range from 45 MHz to more than 200 MHz. This can only be achieved with
resonators with quality factors more than 1000. This seems to be out of reach even by using the
high-quality passive components presented in this work. Therefore, there is a strong belief that
no such component can be integrated into CMOS chips, and these ultra-high-quality components
will remain as external to CMOS [157]. However, there are three emerging technologies, in
which transceivers with integrated channel filters are already demonstrated. These technologies
are quartz-on-silicon [158], mechanical filter [159] and high-temperature superconductor
technology [160].
Surface-Acoustic-Wave (SAW) Filters
In applications of the surface acoustic wave phenomenon to electronic devices,
piezoelectric materials are required to convert the incoming electromagnetic signal to an acoustic
one, and vice-versa.
In its simplest form, a transversal SAW filter consists of two transducers with interdigital
arrays of thin metal electrodes deposited on a highly-polished piezoelectric substrate such as
quartz or lithium niobate. The electrodes that comprise these arrays alternate polarities so that an
RF signal voltage of the proper frequency applied across them causes the surface of the crystal to
expand and contract. This generates surface waves. These interdigital electrodes are generally
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Acoustic Electromechanical Temp. Coef.
Coupling Coef.
of Delay
4 .5 0
0 .1 1
0 .0 7
Table 5.9: Properties of common acoustic materials.
spaced at 1/2 or 1/4 wavelength of the operating center frequency. Since the surface wave or
acoustic velocity is 10-5 slower than the speed of light, an acoustic wavelength is much smaller
than its electromagnetic counterpart. Only very narrow band of frequency is generated by the
source. The frequency selection is performed by the electrode spacing both in generator and in
transducer. The transducer is essentially the same device except the surface waves are converted
into electromagnetic waves.
Current state-of-the-art
The traditional approach for channel filtering is to use acoustic domain resonators. The low
propagation speeds allow construction of ultra-high-quality resonators. Various filter topologies,
such as Z-path, inline and transverse mode coupled, have been developed for IF filtering [161],
[162]. The relative bandwidths less than 0.2% and out-of-band rejections more than 40 dB are
fabricated regularly. Insertion losses as high as 20 dB are reported for surface-acoustic-wave
(SAW) filters. However, this is not a big problem since the plenty of amplification is available at
these frequencies. Perhaps, the most important problem is their large size, >5x5 mm, and their
integration with CMOS circuits. Yatsuda et al. described a flip-chip packaging technique to
miniaturize the overall package of a SAW filter [163]. More recently, Eo et al. showed a SAW
oscillator integrated polylithically with CMOS circuits. Quality factor of 10,000 and insertion
loss of 11 dB at 289 MHz achieved with this procedure [158].
Monolithic integration of SAW resonator with CMOS is impossible, since none of the
materials exhibit good piezoelectric properties. Table 5.9 lists common piezoelectric materials
that are used for the SAW filter fabrication. The material properties suggest that the only suitable
substrate for monolithic integration is GaAs, in spite of the low-electromechanical coupling
coefficient. In fact, Baca et al. demonstrated the first monolithically integrated SAW oscillator
on GaAs substrate [164].
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' in
Figure 5.30: Typically, mechanical filters employ a mechanical resonator
to achieve high quality factor. Here, a fixed-fixed-beam (FFB) resonator is shown.
Mechanical Filters
Principle of operation
Another promising development is the fabrication of high-quality mechanical filters. The
principle of operation for mechanical resonators is illustrated in Fig. 5.30. A mechanical
resonator is nothing but a suspended beam that can be electrostatically actuated. To drive the
and an ac voltage, vin is applied using the
resonator, the beam is biased with a dc voltage,
drive electrode [165]. The input voltage generates electrostatic forces, inducing mechanical
vibration when the frequency of the excitation comes within the resonance frequency of the
beam. This vibration creates dc-biased, time-varying capacitors between the beam and sense
electrodes, which sources output currents given by
dC dx
V b ,a s
3 (
where .r is displacement of the beam. The output currents are sensed by using on-chip
electronic circuits. Under vacuum operating conditions, the efficiency of mechanical resonators
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A m plifier
(In p u t)
C om b-Transducer
' Mass
’ S u sp e n sio n
A n c h o rs J
Figure 5.31: Topside view of a fully integrated micromechanical resonator oscillator [159].
E lectrode
C ou p lin g
S p r in g ,
t .
_ t_ _______
u R e so n a to r s
- ■■
. ____:___i l t 7''-’
E lectro d es
20 am
Figure 5.32: SEM of a spring-coupled bandpass micromechanical filter using FFB
resonators [166].
is very high [159], therefore such structures can be used to achieve quality factors desired by
mobile communication systems.
Current state-of-the-art
Three different mechanical resonators have been demonstrated with operation frequencies up
to 100 MHz:
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E lectro d e
Q u a rter-W av e le n g th
T o rsio n al B e a m
13 3"m
A nchor
A nchor
Flexural-M ode
G round Plane and
S e n s e E lectro d e
Figure 5.33: SEM of a free-free-beam micromechanical resonator [167].
1. Folded beam resonator with quality factors close to 50,000 at 20 mTorr pressure ((9=27 at
I atm pressure) has been demonstrated [159]. An integrated oscillator utilizing a folded
beam resonator is shown in Fig. 5.31.
2. Fixed-fixed-beam resonators are used for filter designs with center frequencies from 310MHz [166]. The reported quality factors vary between 10-400. The basic resonator
with a coupling spring is shown in Fig. 5.32.
3. Free-free beam resonators extend the frequency range up to 100 MHz utilizing nonintrusive support as shown in Fig. 5.33 [167]. Quality factors as high as 8000 has been
reported, however, the insertion loss in these filters is extremely high (more than 45 dB)
and out-of-band rejections are as low as 5 dB.
These mechanical filters are fabricated by using simple surface-micromachining techniques.
All of the mechanical beams are realized with low-stress polysilicon films. Fabrication of such
polysilicon beams requires high-temperature anneal (835 °C) [159], therefore it is not suitable as
a post-processing for standard CMOS process. This has been solved by using tungsten
metallization with TiSij drain/source contact barriers, rather than aluminum This process is
termed as Modular Integration of CMOS and microStructures MICS.
The future of the mechanical filters depends on several factors:
I. Fabrication: MICS process is not attractive for couple of reasons. First, the industry is
reluctant to adopt a new set of metallizations. Until recently, all CMOS fabrication processes
have been based on aluminum as an interconnect metallization. Even the recent push for
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copper-interconnect technology has encountered significant resistance by the industry. It
seems extremely difficult to convince semiconductor manufacturers to invest on a non­
standard CMOS process. Therefore, the acceptance of "first-CMOS" type surfacemicromachining process is very unlikely. Much attractive alternatives based on "firstmicromachining" techniques are gaining tremendous popularity among MEMS designers.
The most successful example of this trend is Modular Monolithic MEMS (M3S) developed
by Sandia National Laboratories, Albuquerque, NM [168]. Currently, this technology allows
as many as 5 layers of surface micromachined polysilicon layers integrated with standard
CMOS process.
However, prevalent applications for these technologies operate at low-frequencies
(<1 GHz). High-frequency applications require bulk micromachined described in this work.
The mechanical properties of the materials used in mechanical filters are extremely
important. Currently, polysilicon is the only material used for the fabrication, and possible
use of electroplated metals remains to be seen.
2. Frequency Scaling: Although feasible systems have been demonstrated with operation
frequencies up to several megahertz. The current techniques are not promising for
frequencies above 10 MHz. One of the problems is related to the frequency scaling of the
resonators. According to scaling rules given in [166], a 100 MHz FFB resonator requires an
air-gap of 40 nm! The small gaps are extremely difficult to fabricate with any given
Beside the fabrication limitations, there are serious concerns about the use of
polysilicon scaling. Polysilicon films are made up by small silicon crystals with various
shape, size and orientation. One of the frequency-scaling rules calls for sub-micron width for
coupling springs [166]. Obviously, this raises questions regarding the reproducibly and
reliability of such structures.
3. Mechanical limitations: Cleland et at. studied fundamental resonance frequencies of
nanoscale single-crystal resonators [169]. They are able to fabricate mechanical resonators
with size scales of less than 100 nm in all three dimensions. These engineered structures have
fundamental mechanical resonance frequencies approaching 1 GHz [170]. These studies
show ultimate performance limits that can be achieved by using mechanical structures.
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Consequently, the use of mechanical resonators is novel idea that has tremendous
implications for communications technology. It offers not only ultra-compact, ultra-high-quality
IF filters but also a possible monolithic integration with CMOS circuits.
High-Temperature-Superconductor (HTS) Filters
Principle of operation
High temperature superconductors (HTS), were discovered in late 1986 when Miller and
Bednorz of IBM's Zurich Lab announced a superconducting oxide at 30K. In the spring of 1987,
Paul Chu of the University of Houston announced the discovery of a compound. Yttrium Barium
Copper Oxide ("YBCO") that became superconducting at 90K. The next months saw a race for
even higher temperatures that produced bismuth compounds ("BSCCO") superconductive up to
110K and thallium compounds ("TBCCO") superconductive up to 127K. These discoveries
superconductivity because when the transition temperatures of superconductors went well above
77K this allowed the use of a readily available, low cost, easy to use coolant - liquid nitrogen.
Fabrication of thin-film superconductors is demonstrated. Today, several companies offer
HTS filters designed based on distributed filter techniques.
Current state-of-the-art
The third alternative technology is based on recent discovery of high-temperature
superconductors. This technology offers virtually lossless metallization (1000-times lower losses
than high purity copper at I GHz [171]). As a result, the quality factors of standard resonators
have reached to 160,000 [171]. Q of HTS resonators has been increasing at a rate of
approximately 55% a year, and it is expected to surpass Q of 1,000,000 in 5 years. Naturally, this
technology is not applicable for handheld systems, since most systems operate at temperatures
below 77 K, under vacuum conditions. Nonetheless, very elegant systems are already
demonstrated for wireless base-transceiver-stations [160].
The resistive losses in electrical domain have long forced designers to look for other
physical domains to isolate very tight signal bands. The techniques based on filtering in acoustic
domain have gained acceptance in spite of the fact that their fabrication is incompatible with
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other electrical blocks. The discovery of HTS materials and the thin-film fabrication is very
promising for base-station applications but requires not only a cooling system but a lot of power.
On the other hand, the operation of high-quality mechanical resonators requires modest level of
vacuum, which can be achieved and maintained very easily and without additional cost.
Furthermore, with the developed technology, it is possible to integrate these resonators with
CMOS electronics. This is, arguably, the most important development in mobile communications
in recent years.
Fedder et al. have developed a new CMOS micromachining process, in which they use
three-metal CMOS process, to fabricate folded-beam resonators in standard CMOS process
[172], [173]. The conventional stacked via approach is not appropriate to fabricate such
mechanical filters because of the non-uniform profile and the fabrication limits set by the design
rules. Therefore they are using the third metal layer as a mask to perform RJE operation and very
high-aspect ratio and closely spaced beams. Such an dry micromachining approach is in fact
needed to achieve the low-frequency folded-beam architectures, however it suffers from
mechanical stress of the beams. The addition of dry etching will greatly enhance the capabilities
of the CM-MEMS technology.
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The semiconductor industry has been looking ways to increase the functionality of the
systems that are fabricated by using new fabrication ideas. Arguably, the most revolutionary
ideas came from the emerging field of MEMS. Numerous new methods, such as thick film
processing, electroplating, CMP, have revolutionized the field. It has become possible to
fabricate devices that are never thought possible. The presented technique is the first example of
a complete coplanar microwave CMOS technology. It has been demonstrated by several
components that by using this technology, it is possible to fabricate devices with the state-of-theart performance. The development of this process is definitely in favor of mobile
Ultimate goal of mobile communication technology is the monolithic integration of a
complete transceiver system. This has not been possible in CMOS, either because some of the
critical components cannot fabricated in CMOS or, if they are fabricated, their quality is too poor
to be used in modem .ystems. These critical components are RF and IF filters, inductors, tunable
capacitors, and mechanical switches. The developed technology solves all the performance
problems. Perhaps, the first time in the history, it has become possible to have a single-chip
CMOS transceiver chip. According to recent market studies, communication applications
doubled their share in the chip market. And, they will surpass all computing platforms as a
semiconductor consumer by the end of this decade. Therefore, the developed RF-CMOS-MEMS
technology is positioned to take off with enough support.
Drastic improvements have been demonstrated for inductors. The quality factors at
2.4 GHz is increased almost 10 times. Such inductors can lower the phase noise of the PLLbased frequency synthesizer 10 dB or more. Perhaps, more importantly, they can be used in
lumped RF filter realizations. Such filters have never been demonstrated with integrated
inductors in CMOS. Even the direct conversion approaches employ external RF filters, since
they are impossible to be realized in CMOS.
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The tunable capacitor has variety of applications from mobile applications up to
millimeter wave applications. The demonstrated capacitor has a potential of more than 10:1
capacitance ratio with less than 1.0 V voltage variation. Predicted self-resonance frequencies are
above 30 GHz. At low frequencies, this is ideal to tune voltage controlled oscillators. Ultra­
broadband operation, to cover frequencies from 800 MHz to 2.4 GHz is possible. Furthermore,
such capacitors are indispensable for tunable filter applications that frequencies and bands that
have not imagined before. At millimeter-wave applications, tunable capacitors are used to
control the wave-propagation along transmission lines. In the terminal-control configuration,
tunable capacitors are used as adaptive signal processors. The response of dividers, couplers and
filters can be altered electronically. This will greatly reduce the complexity of the some of the
designs that employ multiple frequencies.
Reconfigurable microwave systems are the most promising development in microwave
arena. These smart systems are able to adjust their physical configuration to optimize their
functionality. High quality switches are the single most important components to achieve the
desired configuration changes. This work outlines four different configurations that are possible
to fabricate in the developed technology. These are the first mechanical switches presented in
CMOS medium. Since the control electronics can be integrated monolithically, they are cheaper.
High quality and reproducibility of the presented switches make them the best choice for the
reconfigurable microwave networks.
A major problem in mobile communications is the difficulty of channel separation. Only
passive technology that can satisfy the quality requirements was surface-acoustic-wave
technology. The filters utilizing this technology are very large, and have to be discrete that can
only be integrated externally. Mechanical filters with fixed-fixed beams can potentially solve this
problem. However, the mechanical properties of the films in the current process should be
characterized, before making the final decision.
The process developed is proven to be feasible for passive microwave components such
as transmission lines, coupled lines and coupler. Several components are demonstrated with
successfully. Serious consideration is paid to assure the coplanar waveguide mode propagation,
in spite of asymmetrical discontinuities. Techniques to suppress the slotline mode propagation
are investigated extensively. These techniques are wirebonding, air-bridge, intemal-ground-
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equalization. Passive microwave devices with these ground-equalization techniques are realized
in the CMOS membrane. All of these devices are conductor-loss limited, and in many cases, the
quality can be increased further by using gold lines instead of aluminum wiring.
Finally, we would like to point out that the developed process has a great potential at low
frequency applications such as sensors and microfluidic systems. Fundamental components
necessary for microfluidic applications such as microchannels, microactuators, sensors,
reservoirs can be fabricated. Again, the system has the advantage of integrated electronics.
Although several sensors based on thermal isolation and piezoresistive effects have been shown,
no microfluidic system has been shown integrated with sensors demonstrated yet.
The combination of microfluidic systems, chemical sensors, CMOS electronics and highfrequency communication circuits makes the developed process very promising process for
future systems.
There are several limitations of the CM-MEMS process currently. The problems in each
step of the developed technology is discussed below:
1. Stacked vias: Standard CMOS processes does not allow stacked vias used to realize open
holes. This is important to minimize the non-uniformity in the subsequent process steps. In
the case of the 2.0 pm CMOS technology used in this work, the thickness of the open can be
as large as 5 pm. Such thicknesses are very difficult to deal with in thin-film processing
technology, therefore the results are not guaranteed. The common solution is to use larger
open areas to increase the fabrication yield. Nevertheless, this decreases the aspect ratio and
limits the minimum size of the beams.
This problem can be solved by using a reactive ion etch step (RIE) as described in [172].
Because of the low selectivity of this method, a special masking has to be used. This mask is
usually a metallization layer with thickness more than 1 pm. Fedder et al. employed the last
layer of metallization as the RIE mask [172]. The same technique can be used in the first step
of the CM-MEMS to improve the minimum feature size without sacrificing the non­
uniformity. After the patterning the mask should be removed, and this might be problematic,
since aluminum films are usually etched by wet etchants. Therefore, the mask removal
should be timed so that there is still metallization left for electrical contacts.
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Additionally, the utilization of such high-aspect-ratio CMOS beams is a challenge because of
their internal stresses. The beams curl up. Either novel architectures that work in spite of the
bucking or the beams should be stress compensated. In this case, if stress-compensation is
used, it must be used after the removal of the sacrificial mask.
2. High-aspect-ratio thick-film patterning: One of the weaknesses of the CM-MEMS is the low
aspect ratio. It is the natural result of thick film processing without any CMP. The
planarization techniques such as the CMP are widely used multilayer MEMS technologies.
However, the planarization is an expensive process. The aspect ratio is not only limited by
the surface profile but also by the photoresist chemistry. High energy light sources such as Xray has been used to expose very thick resist to obtain high aspect ratios. In general, the
improvement comes from the new photoresist chemistries. The current generation of
photoresist can only give aspect ratios of as high as 5.
A possible solution is to use two photoresist films instead of one. This should be investigated
to reach aspect ratios 10 or higher.
3. Step coverage: The quality of the electroplating depends many factors. One of the important
factors is the thickness of the seed layer. Because of the extreme surface profile, a
straightforward evaporation might not be good enough. Necessary adjustments have to be
made to improve the step coverage.
In addition, the setup developed for in-situ cleaning and evaporation should be improved.
Currently the cleaning by scanning the ion beam is cumbersome. The beam width should be
larger than at least 10 mm x 10 mm so that even the largest CMOS chips cleaned without
scanning. The characterization of the ion beam is necessary to assess the duration of the
beam in the worst case. In current setup, the focusing problem along with the oscillation in
the current source remains to be serious issues. These improvements should also include the
solutions for step coverage as well.
4. a) Electroplating non-uniformity: As described in chapter 4, the uniform electroplating is
desired. This can be accomplished by a good agitation control and a uniform current density.
The current plating setup is very basic one. The control of critical parameters: the
temperature, agitation, and contamination must be addresses for repeatable and reliable
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Non-planar surfaces are problematic to perform several important functions. Even in the
single layer gold processing, the electroplating is very complicated. For a simple air-bridge
fabrication, the thickness of the metallization is expected to vary between 2 (im and 7 pm
depending on the position the measurement is taken. With the current setup, consistent
results are obtained with constant human interference and control of the parameters.
b) Plating solution and photoresist interaction: Long plating at elevated temperatures causes
cracks in the photoresist mold. If the plating continues, the seed layer exposed through the
photoresist is plated. These unwanted plating may cause unwanted electrical shorts. This
should be considered to determine the proper current density and the plating solution
appropriate for the applications. In the current setup, the pH of the plating solution is not
monitored. In the last experiments, the plating rate dropped considerably, therefore the
plating duration increased to more than 30 minutes, which in turn resulted in photoresist
5. Selectivity of the wet etchant systems: Another problem due to non-planarity of the
processing surface is that the stripping of the seed layer require longer duration. This along
with the low selectivity of the chemicals used for the stripping becomes a very serious issue
in the CM-MEMS process. Because, Au and Cr etchants not only severely attack the plated
gold but they also aluminum in the exposed parts of the CMOS chip. At this point, it seems
that only cost-effective solution is to use a RIE system with an appropriate chemistry.
6. Compatibility of screen printing: Although the screen-printing is widely used in the industry
and have cost advantages compare to photolithographic processes, it is not compatible with
semiconductor fabrication. Moreover, the minimum feature size is large and the alignment of
its mask is difficult. However, if single layer gold process is used, we believe it is
advantageous compared to other deposition techniques. If multilayer gold processes are to be
developed than the screen-printing is difficult to use in the intermediate steps, but it is still
indispensable after the last metallization step.
Beside the improvements in each step, there are several high level improvements of the
overall process:
1. Characterization procedure for CMOS processes: A standard characterization procedure is
needed to compare different CMOS processes. Such procedure is also useful to transfer the
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designs between different technologies. This is especially important for sensors and actuator
applications that use the mechanical and thermal properties of the suspended layers. Such a
characterization will have three distinct but coupled parts. Firstly, the test structures that
allow the measurements of a set of properties combined. These measurements do not include
necessarily simple mechanical measurements but also other advanced methods that might
give better accuracy and information about the measured system. One thing is almost certain
that none of the procedures would give direct value for the required parameters. Therefore, as
the second part of the characterization procedure, a sound theory based on the first principles
must be developed, so that a set of measurement can be interpreted. The developed
formulation essentially will take the set of measurements results and give the desired thermal,
electrical and mechanical constants. Finally, simulation tools should be developed which
takes these fundamental constants and predicts the dynamic response of a fabricated structure
under any practical condition (i.e. no quantum effects, supercooling, and similar extreme
conditions). The completion of such a trilogy is a major accomplishment and it will be
extremely useful in development of new optimized devices.
2. Multilayer gold electroplating: Currently, the CM-MEMS technology includes only one layer
of gold as a low-loss medium. It is conceivable, even at this stage some of the devices can
utilize a movable gold beam. There are also other applications such as the phased-array, that
can traditionally using multilayer architectures that need multilayer gold metallization. The
movable gold feature can be easily achieved with the CM-MEMS, potentially without
increasing the mask count. In special cases, another mask can be used to pattern a third layer
of thick film photoresist, which will define the regions where the gold will be released after
polyimide stress-compensation. The only requirement is that this photoresist must be
accessible through a open hole from the backside of the chip similar to the TFPR-l.
The development of multilayer CM-MEMS technology is not very difficult either. However,
a good multilayer process almost certainly requires the addition of a CMP planarization step.
The CMP can not be used with screen-printable polyimide, but there are several lowtemperature, low-k dielectric materials that can be used as an interlayer dielectric.
3. Gray-scale lithography: One of the most exciting developments in the MEMS community is
the development of the gray-scale lithography. In this type of lithography, the thickness is
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coded with the gray levels. Although theoretically continuous tone is possible, practically
probably 8 or 16 levels are enough for many applications. Such lithography is a natural part
of a multilayer thick-film CM-MEM process, because this will allow the designer to specify
the thickness of certain layers (such as TFPR-1, TFPR-2, etc). During fabrication, because of
the gray-scale mask, in one exposure several thickness can be defined. This is very important
for the devices fabricated in the CM-MEMS, because it will eliminate of the limitation of the
single thickness (i.e. the designer can specify only one TFPR-l thickness all over the chip).
The CM-MEMS technology is very capable technology, but it has several shortcomings that
should be improved as described above.
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