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Micromachined broadband thermocouple microwave power sensors in CMOS technology

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MICROMACHINED BROADBAND THERMOCOUPLE MICROWAVE POWER
SENSORS IN CMOS TECHNOLOGY
by
Veljko Milanovic
B.S. M ay 1994, The George Washington University
M.S. January 1997, The George W ashington University
A Dissertation submitted to
The Faculty of
The School o f Engineering and Applied Science
of The George W ashington University in partial satisfaction
of the requirements for the degree of Doctor o f Science
January 29,1999
Dissertation directed by
M ona Elwakkad Zaghloul
Professor o f Engineering and Applied Science
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TJMI Number: 9919792
Copyright 1999 by
Milanovic, Veljko
All rights reserved.
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ABSTRACT
M icrom achined B roadband Therm ocouple Microwave Pow er S e n so rs in
CMOS Technology
by Veljko Milanovic
Directed by Professor Mona Elwakkad Zaghloul
This dissertation reports on the design, fabrication, and characterization o f broadband
thermocouple-based microwave power sensors implemented in standard CMOS technology
followed by silicon micromachining. These thermal converters detect true rms value of unknown
microwave signals by converting the signals to heat in a terminating resistor, and measuring the
resulting temperature increase with thermocouples.
The devices are based on coplanar waveguide (CPW) transmission lines fabricated with
CMOS aluminum, matching termination resistors of CMOS polysilicon, and aluminum-
polysilicon thermocouples. This transmission line based design with a matching termination is
responsible for extending the operating frequency well into millimeter wave range. The result is
a first CMOS compatible sensor with gigahertz operation, which significantly extends previous
achievements of thermoconverters that operate up to several hundred megahertz.
A low cost maskless post-process was developed to allow for the removal of silicon
substrate in selected areas of the IC chip. The process was improved and modified from the
previous Master’s thesis work by incorporating ultrasonic mixing. This ultrasonically enhanced
hybrid etch is a two-step post-process of isotropic etching using xenon difluoride, followed by
ultrasonically enhanced anisotropic etching using ethylenedyamine pyrocatechol in water.
The CPW transmission lines, a vital part of the overall structure, were modeled
analytically and experimentally characterized both before and after the post-process. Test sets of
CPWs were fabricated through a number of standard CMOS processes and characterized over the
frequency range from 0.1 GHz to 50 GHz. It was shown through accurate measurements and a
new quasi-static model that the highly lossy nature of propagation is due to both transverse and
longitudinal currents induced in the conductive silicon substrate, and that design o f broadband
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low-loss components requires removal of the lossy substrate directly beneath the structures. A
similar model is given for the improved fully-suspended CPWs to allow fully analytical design
for desired characteristic impedance, and predicting performance. The fully-suspended CPWs
achieve attenuation below 4 dB/cm at 40GHz, dominated by metallic losses. A low measured
effective permittivity of -1.8 is very uniform over all frequencies of interest.
Two types of power sensor design were fabricated and characterized using
electromagnetic and thermal models and measurements. Such fully-suspended sensors achieve
very high thermal and electromagnetic efficiency by selective removal of silicon directly beneath
the CPWs, the termination, and the hot thermocouple junctions.
Both types o f sensors operate
efficiently up to 50 GHz, with maximum sensitivity of 3.04 V/W for Sensor 1, which slowly
decreases with frequency to arrive at 2.22 V/W at 50 GHz. Thermal time constant of both
devices is -1.5 ms, which is sufficiently long for very accurate measurements at frequencies well
below 1 MHz. Throughout the 50 GHz frequency range the devices’ input reflection is below 10 dB. Below 35 GHz, it is below -2 0 dB, both of which are exceptional results for CMOS
integrated components.
A simple thermoelectric model of the best configuration sensor was developed. The
model was adapted and improved from previous work on SPICE equivalent modeling of thermal
CMOS microsensors. The modeled results match thermal and electrical measurements well and
help explain sources of non-linearity and error in measurements. The model further provides a
tool for optimization of the sensitivity and signal-to-noise ratio for the devices.
iii
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Kriya
This work (Kri) is dedicated to the True in-dwelling Doer (Ya).
Ovo djelo (K ri) je posveCeno Istinskom unutraSnjem PokretaCu (Ya).
iv
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ACKNOWLEDGEMENT
I would like to thank my advisor, Professor Mona Zaghloul, for initiating and providing
the extraordinary opportunity for me to work and grow in the inspiring research environment at
the National Institute of Standards and Technology. The success and the timeliness of the
research presented herein are largely due to her leadership and guidance over the years.
At NIST, I am grateful to Dr. Michael Gaitan who introduced me to the remarkable area
of microelectromechanical systems, and provided guidance and first-class resources throughout
the study. Also, I am grateful to many other colleagues whose work and collaborations both
aided and inspired me daily, particularly Dr. Jon (Heist, Dr. John Suehle, Dr. Prasad Chaparala,
and Dr. Nim Tea. Many others include Dr. Richard Cavicchi, Chris Zincke, Matthew Hopcroft,
M. Yaqub Affidi, Mehmet Ozgur, and Dr. Santos Mayo.
I also want to thank Professor Walter K. Kahn, Professor Can Korman, and Professor
Wasyl Wasylkiwskyj, of The George Washington University for participating in my Dissertation
committee, and influencing me as extraordinary teachers to seek a career in academia.
Throughout graduate education, I was funded from RF Microsystems, Inc., in San Diego.
I want to thank the many people there who were always exceptionally supportive and responsive
to my needs, and allowed me to travel worldwide to present our work at international
conferences. Most notably, the collaboration and friendship with Edwin Bowen, currently of La
Jolla MEMS Institute, were of utmost importance in my progress.
Many of the measurements in this work were performed at REMEC, Inc. in San Diego,
where I am most thankful to Joey Lopresti. The work was funded by the Space and Naval
Warfare System Center, San Diego, where I am very thankful to Joseph Weber for support and
encouragement, as well as many travel opportunities.
During graduate studies, to the very last exam, I have been continuously, fully, and
lovingly supported by my mother Ksenija JuraniC-MilanoviC, my sister Iva Milanovic-Lovell,
grandmother Marija Juranie, and others in my family.
I am also thankful for the inspiring
memories of my father Jovan Milanovic who taught me selfless and loving work by daily
example.
V
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TABLE OF CONTENTS
Page no.
ABSTRACT
ii
DEDICATION
Iv
ACKNOWLEDGEMENT
v
TABLE OF CONTENTS
vi
LIST OF FIGURES
ix
LIST OF TABLES
xiv
LIST OF SYMBOLS
xv
CHAPTER 1 - INTRODUCTION
1
1.1
IMPORTANCE OF POWER MEASUREMENT
1
12
UNITS AND DEFINITIONS
2
13
MICROMACHINING IN HIGH-FREQUENCY APPLICATIONS
1.3.1 SILICON MICROMACHINING FOR MICROWAVE APPLICATIONS
1.3.2 SILICON MICROMACHINING IN STANDARD CMOS
4
4
5
1.4 PROBLEM DEFINITION
6
1.5 SOLUTION OPTIONS
1.5.1 DIODE DETECTORS
1.5.2 THERMISTOR SENSORS
1.5.3 THERMOCOUPLE SENSORS
7
7
8
9
1.6
PREVIOUS ART
9
1.7
CONTRIBUTION OF THE DISSERTATION
CHAPTER 2 - MICROWAVE POWER SENSOR DESIGN
10
13
2.1 THERMOELECTRICITY
2.1.1 SEEBECK EFFECT
2.1.2 PELTIER EFFECT
2.1.3 THOMSON EFFECT
2.1.4 THERMOPILE
13
13
15
16
16
22.
INDIRECTLY vs. DIRECTLY-HEATED THERMOCOUPLE SENSORS
19
23
INDIRECTLY-HEATED THERMOCOUPLE DEVICE-SENSOR 1
20
2.4
DIRECTLY-HEATED THERMOCOUPLE DEVICE - SENSOR 2
23
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2-5 PERFORMANCE MEASURES
2.5.1 SENSITIVITY
2.5.2 SIGNAL-TO-NOISE RATIO
2.5.3 DYNAMIC RANGE
2.5.4 THERMAL TIME CONSTANT
25
25
25
26
27
CHAPTER 3 - POST-PROCESSING METHODOLOGY
3.1
STANDARD CMOS FABRICATION
28
28
3.2 SILICON MICROMACHINING
3.2.1 ISOTROPIC ETCHING WITH XENON DIFLUORIDE (XeF:)
3.2.2 ANISOTROPIC ETCHING OF CRYSTAL SILICON
3.2.3 ETHYLENEDIAMINE PYROCATECHOL WATER (EDP)
29
31
37
38
33
41
44
45
HYBRID ETCH
3.3.1 ULTRASONICALLY ENHANCED ANISOTROPIC ETCH IN HYBRID ETCH
3.3.2 TEST STRUCTURES FOR MONITORING THE HYBRID ETCH
3.4
FABRICATED SENSORS
49
3.5
CONCLUSIONS
50
CHAPTER 4 - CHARACTERIZATION OF COPLANAR WAVEGUIDES ON CMOSGRADE SILICON SUBSTRATE
52
4.1
COPLANAR WAVEGUIDES ON SI SUBSTRATE
53
4.2
TEST SET DESIGN
55
43
MICROWAVE MEASUREMENT SETUP AND PROCEDURE
57
4.4
MEASUREMENTS OF CPWs ON CMOS-GRADE SI SUBSTRATE
59
4 3 QUASI-TEM MODEL FOR CPWs IN CMOS
4.5.1 SERIES IMPEDANCE EQUIVALENT CIRCUIT
4.5.2 SHUNT ADMITTANCE EQUIVALENT CIRCUIT
61
63
68
4.6 COMPARISON OF MODEL AND MEASUREMENT FOR CPWs ON SILICON
SUBSTRATE
71
4.7 DISCUSSION
74
CHAPTER 5 - DESIGN OF FULLY-SUSPENDED COPLANAR WAVEGUIDES
5.1
DESIGN FOR 5 0 0 CHARACTERISTIC IMPEDANCE
5 3 DESIGN FOR MICROMACHINING AND CMOS CONSTRAINTS
5.2.1 TYPES OF CPW DESIGNS FOR MICROMACHINING
5.2.2 DETAILED DESCRIPTION OF THE BEST DESIGN
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76
76
80
81
84
5-3 ETCH-DEPTH CRITERION FOR SUFFICIENT SUBSTRATE ISOLATION
86
5.4 FULLY-SUSPENDED CPW CHARACTERIZATION
88
CHAPTER 6 - CHARACTERIZATION OF THE SENSORS
94
6.1 NUMERICAL CHARACTERIZATION USING FINITE-ELEMENT SIMULATORS
94
6-2 DC MEASUREMENTS
6.2.1 CURRENT-VOLTAGE (I-V) MEASUREMENTS
6.2.2 POWER SENSITIVITY MEASUREMENTS AT DC INPUT
95
95
97
6-3 RESPONSE TIME MEASUREMENTS
99
6.4 MICROWAVE CHARACTERIZATION
6.4.1 MICROWAVE MEASUREMENT SETUP
6.4.2 BROADBAND MATCHING CHARACTERISTICS
6.4.3 SENSITIVITY MEASUREMENTS
6.4.4 DYNAMIC RANGE AND LINEARITY MEASUREMENTS
CHAPTER 7 - THERMAL CHARACTERIZATION AND MODELING
101
101
102
108
110
113
7.1 MEASUREMENT SETUP AND PROCEDURE
113
7.2 MODEL EQUATIONS
7.2.1 NOMENCLATURE
7.2.2 CONDUCTION
7.2.3 CONVECTION
7.2.4 RADIATION
114
114
115
115
116
73 SPICE EQUIVALENT CIRCUIT FOR THERMAL MODEL
7.3.1 REPRESENTATION OF DEVICE ELEMENTS BY SPICE ELEMENTS
116
120
7.4 SIMULATION SETUP
120
73 RESULTS AND DISCUSSION
7.5.1 MEASUREMENT RESULTS
7.5.2 MODEL RESULTS
122
122
125
CHAPTER 8 - CONCLUSIONS AND FUTURE WORK
133
8.1 CONCLUSIONS
133
8.2 FUTURE WORK
134
REFERENCES
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137
LIST OF FIGURES
Page no.
Figure 1. Schematic o f the power-measurement problem.____________________________________ 6
Figure 2. Structure o f the HP 8481A thermocouple chip [1]._________________________________ 10
Figure 3. Single thermocouple sensor composedfrom two different materials incontact. ___________ 14
Figure 4. Schematic ac-dc thermoconverter based on twelve series thermocouples._______________ 17
Figure 5. SEM micrograph o f ac-dc thermoconverter based on 12 series thermocouples,
schematically described in Figure 4 ._______________________________________________ 17
Figure 6. Schematics o f the two sensors' configurations: (a) indirectly-heated configuration, and
(b) directly heated configuration._________________________________________________19
Figure 7. Layout o f the indirectly-heated thermocouple microwave power sensorfo r CMOS MEMS
fabrication —Sensor 1 .__________________________________________________________ 21
Figure 8. Equivalent circuit representation o f the direct-heating implementation using two series
thermocouples, such as in the commercial HP 8481A device.____________________________ 23
Figure 9. Layout o f the directly-heated thermocouple microwave power sensor fo r CMOS MEMS
fabrication —Sensor 2 .__________________________________________________________ 24
Figure 10. Schematic circuit o f the thermopile representing thermal noise as a series voltage
source._______________________________________________________________________26
Figure 11. Schematic top view and a cross-section o f isotropic etching o f silicon by gaseous XeF2
using Si02 as the m ask._________________________________________________________ 32
Figure 12. Schematic diagram o f the XeF2 etching station. __________________________________ 33
Figure 13. (a) Micro-heater designed fo r XeF2 etching; (b) test structure fo r monitoring micro­
heater and microwave coplanar waveguide in XeF2 etching. Pad size is 100 pm x 100 pm.
35
Figure 14. Top view and cross section o f etched pit bounded by <111> planes fabricated by
anisotropic etching using highly boron doped silicon as the etched stop.___________________ 37
Figure 15. Micro-hotplate conductometric chemical gas sensors etched in EDP from (a) a CMOS
process; (b) a specialized process with tungsten contacts.______________________________ 40
Figure 16. Anisotropic post-processing etching o f microwave coplanar waveguide._______________ 42
Figure 17. Hybrid Post-processing etching, (a) microwave coplanar waveguide as fabricated by a
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commercialfoundry; (b) after XeF2 etching; (c) after hybrid etching.__________________
_43
Figure 18. Test structure with two circular opens after (a) hybrid etch, and (b) ultrasonically
enhanced hybrid etch.________________________________________________________
_44
Figure 19. Test structure fo r 120 42 CPWs with very small opens after (a) hybrid etch, and (b)
ultrasonically enhanced hybrid etch.____________________________________________
.45
Figure 20. Optical etching test structure fo r monitoring progress and success o f hybrid etch._____
-46
Figure 21. Use o f optical etching test structure fo r determination o f depth o f etch pit.___________
-47
Figure 22. Fully-suspended CPW test structure fo r optical verification o f the post-process, and
measurement o f etch pit depth._________________________________________________
-48
Figure 23. Microphotograph o f the indirectly-heated thermocouple microwave power sensor by
CMOS MEMSfabrication —Sensor I . ___________________________________________
49
Figure 24. Microphotograph o f the directly-heated thermocouple microwave power sensor by
CMOS MEMSfabrication —Sensor 2 .___________________________________________
JO
Figure 25. CPW test structure (a) GSG (Ground-Signal-Ground) layout and (b) cross-sectional
view with pertinent dimensions.________________________________________________
54
Figure 26. Thru-Reflect-Line CPW test set fo r de-embedding measurements o f propagation
constant and characteristic impedance per unit length. Thru length is ~ 0.8 mm, and Line2
length is - 4 mm.____________________________________________________________
55
Figure 27. Measured complex propagation constantfo r data sets listed in Table I: (a) attenuation,
and (b) normalized phase fa ctor._______________________________________________
.60
Figure 28. Measured complex characteristic impedance fo r data set 2._______________________ .61
Figure 29. Quasi-TEM equivalent circuit (a) theoretical model (Model A), and (b) empirical
model (Model B). ___________________________________________________________
.62
Figure 30. Schematic depiction o f a quarter-symmetry part o f the air-line CPW, (a) actual
structure, (b) structure conformally mapped into a parallel plate capacitor.______________
.64
Figure 31. Simplified crosssection o f zero-thickness CPW, (a) fictitious finite-dielectric structure
fo r computing F(h), (b) combining two fictitious structures to obtain multilayer solution, and
(c) superposition o f two such finite-dielectric structures.____________________________ .69
Figure 32. Comparison o f measured and modeled (a) attenuation and (b) normalized phase factor
fo r data set 2 .______________________________________________________________
72
Figure 33. Comparison o f measured and modeled RLGC parameters fo r data set 2. ____________
.73
Figure 34. CAD layoutfo r the fully suspended CMOS CPW thru element. ____________________
.77
Figure 35. Schematic cross-section o f the fully suspended CMOS CPW.______________________
77
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Figure 36. Quasi-TEM equivalent circuitfo r fully-suspended CMOS CPW._____________________ 78
Figure 37. SEM micrograph o f a CPW section o f the first type o f design fo r hybrid micromachining
with opens between signal and ground planes (G—ground, S=signal)._____________________ 81
Figure 38. Microphotograph o f a CPW section o f the second type o f design fo r hybrid
micromachining with opens on either side o f CPW (G=ground, S=signal)._________________ 82
Figure 39. Microphotograph o f a CPW section o f the third type o f design fo r hybrid
micromachining with opens embedded within the ground planes (G—ground, S=signal).______ 83
Figure 40. Microphotograph o f a CPW section o f the fourth type o f design fo r hybrid
micromachining or only isotropic micromachining with opens embedded in signal conductor
(G—ground, S=signal).__________________________________________________________84
Figure 41. Layout o f the end o f a CPW designed fo r micromachining, with micromachining design
dimensions outlined.____________________________________________________________85
Figure 42. Measured real part o f effective permittivity for three CPW layouts from Table 2 .________ 89
Figure 43. Measured imaginary part o f effective permittivity for three CPW layouts from Table 2.
90
Figure 44. Measured normalized phase velocity fo r three CPW layouts from Table 2 ._____________ 91
Figure 45. Measured attenuation fo r two CPW layouts from Table 2 .__________________________ 92
Figure 46. Measured characteristic impedance fo r two CPW layouts from Table 2 ._______________ 93
Figure 47. Measured input voltage vs. current fo r Sensor I termination in ambient air and in
vacuum._____________________________________________________________________ 96
Figure 48. Measured input power vs. input dc resistance o f the termination on Sensor I in ambient
air and in vacuum._____________________________________________________________97
Figure 49. Measured input power vs. output thermopile voltage o f Sensor 1 in ambient air and in
vacuum._____________________________________________________________________ 98
Figure 50. Measured thermopile output voltage o f Sensor 1 as a function o f time for applied
sinusoidal input voltage at 10 Hz —measured instantaneous power. _____________________ 100
Figure 51. Measured thermopile output voltage o f Sensor 1 in ambient air and in vacuum, as a
Junction o f time fo r applied step input power._______________________________________ 101
Figure 52. Measured and simulated magnitude o f input reflection parameter o f Sensor 1._________ 103
Figure 53. Reflection chart o f the measured input reflection parameterfor Sensor I._____________ 103
Figure 54. Measured and simulated magnitude o f input reflection parameter o f Sensor 2._________ 104
Figure 55. Reflection chart o f the measured input reflection parameterfor Sensor 2._____________ 105
Figure 56. Compared magnitude o f input reflection parameter fo r commercial thermocouple
xi
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sensor HP8487A, Sensor 1, and Sensor 2.
.106
Figure 57. Reflection chart o f the measured input reflection parameterfo r a variation o f Sensor 1
when dc bias is applied at portl o f a ) 0 mW, b) 10 mW, c) 34 mW, d) 53.5 mW, e) 76 mW,
and f) 100 mW .________________________________________________________________107
Figure 58. Measuredfrequency vs. sensitivity fo r both sensors._______________________________109
Figure 59. Compared frequency response HP8487A commercial device. Sensor I, and Sensor 2.
Each plot is normalized to sensitivity at lowestfrequency.______________________________110
Figure 60. Measured input power vs. output thermopile voltage o f Sensor 1 at various frequencies.
111
Figure 61. Measured input power vs. output thermopile voltage o f Sensor 1 at 20 GHz. plotted to
show response throughout the dynamic range. ______________________________________ 111
Figure 62. Nodal network representation o f two dimensional conduction in discrete form. _________ 117
Figure 63. Symmetry portion o f the thermopile layout, showing the pertinent dimensions o f the
microwave termination and adjacent thermocouples. Below is an outline o f that layout
showing thefour types o f elements and subdivisions used in simulations.__________________ 118
Figure 64. Equivalent electrical circuit representation o f an element o f Figure 63, including
convection, conduction and heat generation terms, by nonlinear resistors and current
sources._____________________________________________________________________ 119
Figure 65. Measured temperature distribution o f Sensor 1 at dc bias o f 20 mW.__________________ 122
Figure 66. Measured temperature distribution o f Sensor I along a-a ’ cut in Figure 65 at dc bias o f
20 m W ._____________________________________________________________________ 123
Figure 67. Measured temperature distribution o f Sensor 1 along b-b' cut (solid plot) and c-c’ cut
(dottedplot) in Figure 65 at dc bias o f 20 mW .______________________________________ 124
Figure 68. Measured temperature distribution o f Sensor I along b-b’ cut fo r three different types
o f excitation which shows the effect o f Peltier heating and cooling at aluminum-poly
junctions.____________________________________________________________________ 125
Figure 69. Compared results o f temperature distribution across one termination resistor arm fo r
model and measurement. With convection included in model, it matches measurements well.
126
Figure 70. Computed temperature distributions across the resistor and hot thermocouple junctions
fo r one thermocouple only.______________________________________________________ 127
Figure 71. Computed sensitivity as a function o f the distance o f hot thermocouple junctions from
the resistor.__________________________________________________________________ 128
Figure 72. Computed sensitivity as a function o f the suspended length o f the thermocouples
(N=16)._____________________________________________________________________ 129
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Figure 73. Computed 1 Hz bandwidth SNR fo r 24 thermocouples in series and sensitivity as
computed by model, as a function o f suspended thermocouple length Ltsus.________________ 130
Figure 74. Computed sensitivity as a function o f the number o f thermocouples tightly distributed
about the center o f the resistor.__________________________________________________ 131
Figure 75. Computed 1 Hz bandwidth SNR computed by model, as a function o f the number o f
thermocouples N ._____________________________________________________________ 132
Figure 76. System-on-a-chip EIRP measurement chip in CMOS, outline and sample photograph.
135
Figure 77. Recent measurements o f sensitivity vs. frequency o f the sample EIRP sensor chip shown
in previous figure. Measurements performed at SSC, San Diego, antenna range.___________ 136
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LIST OF TABLES
Page no.
Table I. Dimensions raid parameters o f experimental CPW sets. _____________________________ 56
Table 2. Designed lanout dimensions fo r fully-suspended CPW sets based on process parameters
and given analy_is.____________________________________________________________ 80
xiv
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LIST OF SYMBOLS
CMOS
Complimentary Metal Oxide Semiconductor
IC
Integrated Circuit
MEMS
Microelectromechanical Systems
CPW
Coplanar Waveguide
PEM
Phenomenological Equivalence Method
rms
Root Mean Square
EDP
ethylenediamine-pyrocatechol in water
NIST
National Institute o f Standards and Technology
TRL
Thru-reflect-line
CDF
Caltech Intermediate Format
ANA
Automatic Network Analyzer
tC R
Temperature Coefficient of Resistance
EIRP
Effective Isotropic Radiated Power
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CHAPTER 1 - INTRODUCTION
Wireless communications at microwave frequencies is a developing technology currently
undergoing major growth. Behind it on the growth curve is the monolithic integration of sensor
and signal processing electronics on the same CMOS (Complimentary Metal Oxide
Semiconductor) IC (Integrated Circuit) chip. At first glance, it would seem natural to meld these
two technologies. Among the potential benefits of doing this are miniaturization and batch mode
fabrication of microwave systems. One obstacle has been that transmission line and power
sensor devices available through the standard CMOS process cannot operate satisfactorily at
frequencies above a gigahertz.
The work of this Dissertation was focused on overcoming this obstacle, and achieving
efficient transmission lines and sensor devices that operate well into the gigahertz frequency
range. Because the sensors are based on thermoelectric conversion, no active components are
needed which would limit the high frequency performance.
We report on the design, modeling, fabrication, and characterization of CMOS
microwave power sensors, and demonstrate that they can be achieved through simple CMOS
compatible maskless post-processing such that these devices can be readily fabricated for
commercial applications.
This Chapter contains the background definitions of true root mean square and
microwave power measurements, and states the problem of this work.
Various possible
implementations of microwave power measurement systems are presented and compared with
respect to their performance and application fields.
Also, the motivation for these novel
implementations is stated along with arguments of the benefits of co-integration of such sensors
on CMOS chips.
1.1 IMPORTANCE O F POWER MEASUREMENT
System output power level is commonly the critical factor in the design, performance
verification, and purchase o f virtually all radio frequency and microwave equipment Because
the output power level of a complete microwave system is so important, it is also critical when
1
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specifying the performance of components that build up the system itself. Each component o f a
signal chain must receive proper signal level from the previous component. In many cases,
measurement of output power of subsystems is desired continuously, in order to monitor the
overall performance.
Monitoring the output “signal level” of an electrical system can be achieved in terms of
voltage or current measurements, or some method of direct power measurement. In general, 1
GHz is the highest frequency where one attempts direct measurement of voltage or current.
Above this frequency, output signal level is usually monitored by some method of direct power
measurement.
At frequencies above 1 GHz, one can distinguish two broad situations in which power
measurements are carried out. In the first, power itself is the electrical quantity of interest. For
example, signal-to-noise performance of a radio communication system depends on the
transmitted and noise power; similarly the heating effect of a microwave oven depends on the
dissipated power. In the second broad situation power is measured in order to deduce some other
electrical quantity which would be more difficult to measure direcdy. Thus voltage and current
are often obtained by indirect methods based on power and impedance measurements. The
number of possible applications of this second kind is relatively large and includes not only
measurements in coaxial lines and waveguides, but also some measurements in free space.
Field strength meters, for instance, are often calibrated by means of a standard
electromagnetic field, which is set up by feeding a measured power into an antenna of known
gain. Field strength measurement, and the application of this work in that context, will be
discussed in more detail as part of the future work in Chapter 8.
1.2 UNITS AND DEFINITIONS
Root mean square (rms) value is an important parameter in the description of periodic
time-dependent signals, since it gives a measure of the signal level that is independent of the
waveform [1], The rms value of a periodic alternating current (ac) signal is defined as the
equivalent direct current (dc) signal that produces the same time averaged heating power in a
resistor as the unknown ac signal:
2
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where x(t) is the time-dependent ac signal, Tp is the averaging time, and Xma is the rms value.
While the above mathematical definition shows Tp tending to infinity, in general Tp should be as
long as many periods of the lowest frequency of x(t).
The fundamental definition of power is energy per unit time, or in other words the energy
transfer rate. Hence, to obtain average power, the energy transfer rate is to be averaged over
many periods of the lowest frequency involved. For example, for an amplitude modulated wave,
the power must be averaged over many periods of the modulation component of the signal. In a
more mathematical sense, average power can be written as:
^v=-V jW )/(0[W ],
(2)
n ' •*/ 0
where 7/ is the period of the lowest frequency component of instantaneous power p(t)=v(t)i(t). In
terms of power dissipated in a load resistor R l, average power can also be written as V2^ / RL or
as I2rms ■R l- This shows that, given a known load resistance R l, direct measurement of average
power implies some form of direct measurement of the square of current or the square of voltage,
averaged over a relatively long period.
It is for this reason that direct power measurement
employs either thermal or mechanical conversion where temperature or torque, respectively, are
proportional to the square of the current; or it employs a non-linear (squaring) circuit element
such as a low-barrier Schottky diode in the square-law region.
The International System of Units (SI) has established the watt (W) as the unit of power;
one watt is one joule per second. Electrical units do not enter into the definition of power, in fact
some are derived from the watt, such as volt which is one watt per ampere. In many cases, when
measuring gain or attenuation, the ratio of two powers, or the relative power, is the frequently
desired quantity rather than absolute power. This ratio of one power level P to some other
reference level Pref. The ratio is dimensionless, and is usually expressed in decibels (dB):
3
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p
dB = 10Iogl0
(3)
Popular usage has added another convenient unit, decibel-milliwatt or dBm. The formula is
similar to (3) except the reference power is always one milliwatt:
dBm = 101ogIO
\
1mW
(4)
1.3 MICROMACHINING IN HIGH-FREQUENCY APPLICATIONS
With constantly increasing frequencies in communications and integrated circuits, there is
a great demand for easier low-cost, miniature microwave components. In many applications,
there is also a need for easy integration with analog and digital circuits. The planarization of
transmission lines to microstrip, stripline, and coplanar waveguide has provided much flexibility
in design, reduced weight and volume, and cost of production. Planar components have reduced
in size so much that their fabrication by conventional machining techniques has become too
costly and difficult. It is for this reason that the recent advances in micromachining techniques
have been finding numerous applications in the microwave field.
1 3 .1 SILICON M ICROM ACHINING FOR MICROW AVE APPLICATIONS
Because of the many benefits of microfabrication techniques such as miniaturization and
design/fabrication cost-lowering, micromachining has also been introduced as a tool for the
fabrication of miniature passive microwave components. A class of microshield components has
been developed at the University of Michigan, with competitive characteristics and miniature
size [5]. In that and other previous work [6], many photolithographical masking steps are needed
for micromachining and metal deposition.
Backside etching is often used to fabricate the
devices, requiring masks both on the top and bottom side of the wafer. These processes are not
compatible with commercially available CAD tools and CMOS foundries. Consequently, they
do not provide for easy integration with analog and digital circuits, and require costly fabrication
facilities.
Silicon micromachining processes have also been utilized to fabricate discrete
thermoelectric microwave power sensors as will be described in more detail in Section 1.6.
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13.2 SILICON MICROMACHINING IN STANDARD CMOS
The recent development of CMOS-compatible micromachining at the National Institute
of Standards and Technology (NIST) has allowed integration of a class of electromechanical
devices with CMOS electronics [7]. Using CMOS-compatible MEMS process techniques, one
can manufacture MEMS structures in a standard CMOS foundry process, such as available
through the MOSIS service [35],[7]. Previous to 1994, there were no microwave structures for
propagation and power measurement available through CMOS technology. By that time, thermal
displays, gas sensors, and similar MEMS devices had been implemented in CMOS by utilizing
post-processing micromachining techniques, which released these devices from the underlying
substrate.
At the same time, researchers from ETH Zurich achieved integration of ac-dc
thermocouple sensors, which measured true rms power of signals up to 600 MHz [8].
While the state of the art at that time showed much promise, there were no single devices
available, or the methodology present, to achieve devices in CMOS with operation above a
gigahertz. No methodology was available to design sensors which do not have such severe
frequency limitations, but would in fact operate in a broadband range from dc to 50 GHz, or
higher. Most importantly, there was no methodology present for suspending large elements such
as e.g. microwave transmission lines, sensors, and radiating elements;
In a Master’s thesis, I described the design and fabrication of coplanar waveguide (CPW)
microwave transmission lines through a standard CMOS process with subsequent maskless top­
side etching [9], [10].
This was achieved by utilizing a novel methodology developed to
overcome the problems that arose when attempting previous methods, which worked well for
small devices and sensors. The design was fully compatible with commercial CAD tools, CMOS
fabrication done through the MOSIS service, and the micromachining was achieved with no
additional photolithographical steps using what we later termed the hybrid etch method [11].
It was also experimentally shown that the removal of the silicon substrate material in the
vicinity of the microwave structures significantly improves the insertion loss characteristics,
frequency response bandwidth, transmission line dispersion characteristics, phase velocity, and
impedance control capability. The developed methodology of obtaining microwave transmission
lines on silicon substrates is comparatively simple and low-cost. In addition, fabricating the
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microwave components through commercial CMOS foundries now gives the capability for
monolithic integration with standard CMOS circuits.
The previous work therefore presented for the first time a method for fabricating
microwave transmission lines in standard CMOS technology, which now allows us to develop
complete microwave power sensor structures, and in some applications even integrate them with
radiating elements for EIRP sensors.
1.4 PROBLEM DEFINITION
The problem this Dissertation addresses is that of measurement of average microwave
output power of an unknown generator. A schematic illustration of the problem is shown in
Figure 1.
Sensor chip+package
Figure I. Schematic o f the power-measurement problem.
We are given an unknown microwave power source, the equivalent circuit of which is
shown schematically in the gray area on the left. This source can be an RF synthesizer, an
antenna, output of a coupler, output of an attenuator pad, or any other device which outputs
microwave power to at least one port. The signal available at this port is of unknown frequency
content, and level. The source is configured in such a way that the port provides output through a
50 Q transmission line. The problem is to measure the average power delivered by such a source
to a matched load.
The goal of the proposed solution of this problem is both in terms of signal limitations,
and technology.
The solution should be device(s) monolithically integrated in standard IC
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technology, should provide proper connection to the monitored port, and should achieve the
following specifications:
•
Frequency range from 100 MHz to 50 GHz
•
Power range from -30 dBm (1 ftW ) to 10 dBm (10 mW)
1.5 SOLUTION OPTIONS
There are three popular devices for sensing and measuring average power at microwave
frequencies. Each of the methods uses a different kind of device to convert RF power to a
measurable dc or low frequency signal. The devices are the thermocouple, the thermistor, and
the diode detector. Each method has some advantages and disadvantages over the others, and
requires a different fabrication technology.
In the past four years of conducting research on the topic of microwave power
measurement, we have attempted all of the three above-mentioned methods as potential
candidates for the goal of a frilly integrated CMOS microwave power sensor. There is also on­
going work on thermistor sensors, although it is expected that the sensitivity of such devices
would be substantially lower than that of our preferred devices - thermocouple sensors.
1.5.1 DIODE DETECTORS
Diodes convert high frequency energy to dc by way of their rectifying properties, which
arise from the nonlinear current-voltage (i-v) characteristics. The square-Iaw detector property
can be shown by expanding the ideal diode current equation about the origin, obtaining:
/ = a 0 -V+ocl V 2 +a2 V3 +...,
(5)
where a, are geometrically decreasing coefficients which arise from the ideal diode equation, but
also depend on the type of diode used.
For very low input voltages, usually below 40 mV peak, higher order terms, not shown in
(5), are negligible. Since the square-law diode is followed by a capacitor, only the even power
terms contribute to the stored energy in the capacitor, which is then simply the a/ V2 term of (5).
In our research, we investigated ways to implement Schottky contacts in CMOS
technology, and integrated them with our fully-suspended coplanar waveguides in a complete rf
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detector circuit [12]. As expected, the diode detector proved to be very inefficient at microwave
frequencies, and was measured with cutoff of 600 MHz. Following these results, we developed a
technique of electrochemical etching to isolate the diode from bulk substrate, and achieved a
cutoff o f 2 GHz, still insufficient to meet our design goals, although an interesting result for other
applications.
1.5.2 THERMISTOR SENSORS
Thermistor sensors operate by sensing the change of resistance due to a change in
temperature in temperature-dependent resistor RF terminations. For most temperature-dependent
resistors, including ones encountered in CMOS MEMS technology, the equation of resistance as
a function of temperature is approximated as:
R (T)= R0(l+ tCK(T -T 0)),
(6)
where Ro is the resistance at a reference temperature To, T is the resistor temperature, and tcr is
the temperature coefficient of resistance.
As in [17], we assume that the temperature of the heating resistor T is constant across the
heater area, and the heat sink and the surroundings stay at the temperature To. Also, we consider
that radiation and conduction losses to the surroundings are restricted to the heater area and that
the radiation losses can be negligible or linearized for sufficiently small temperature differences,
i.e. (T,-T0y r 0« l . Then, the steady-state temperature increase (Tt-T 0) is [17]:
(7)
where Pdiss is the power dissipated in the resistor, and G j is the total thermal conductance
between the heater and a heat sink (e.g. chip package). The change in resistance is therefore
proportional to the change in input power.
One of the major disadvantages of using thermistors as microwave power sensors is the
fact that the change in resistance due to dissipated power causes mismatch with the microwave
power source and therefore significantly limits the dynamic range.
This problem can be
eliminated at the cost of large bias power dissipation (and shorter device lifetime) by integrating
the device in a self-balanced Wheatstone bridge.
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1.5 3 THERMOCOUPLE SENSORS
In microwave thermocouple sensors, a matching resistor dissipates the microwave energy
in the form of heat, which is measured by thermocouples that convert the temperature of the
resistor to a dc voltage. The measurement of the temperature differential caused by the resistive
heating provides an accurate measure of the true rms power absorbed by the terminating resistor
[13]. The terminating resistor should have a small tcR in this configuration to avoid the problem
of resistance change at higher input powers.
As shown earlier, RF power dissipated in a terminating resistor causes a proportional
steady-state temperature difference between the resistor and reference ambient. This temperature
difference is probed by thermoelectric sensor which are based on the Seebeck, Peltier, and
Thomson effects, which link current and heat flows in conductors. These will be explained in
detail in Section 2.1.
1.6 PREVIOUS ART
Thermal converters provide the most accurate link between ac and dc voltage and current
[4]. Single junction thermal converters (SJTC), and multi junction thermal converters (MJTC)
are widely used for accurate measurement of ac signals. They consist of a simple straight wire
heater element made of e.g. nicrome, and copper/constantan thermocouples with hot junctions
placed adjacent or in contact with the heater. These types of sensors have been optimized for
high sensitivity, and low transfer differences [13][62], and have even been implemented in
CMOS technology utilizing micromachining techniques. However, the performance of these
sensors has been limited to frequencies below 1 MHz [62]. In a recent implementation, with
better high-frequency optimization ac performance limit of 600 MHz was achieved [8]. In all the
cases, these sensors would not be suitable for the given problem of broadband microwave
measurement.
In 1974, Jackson of Hewlett Packard reported one of the first silicon microwave power
sensors [3].
Their concept of two tantalum-nitride/n+-silicon thermocouples, optimized as
microwave terminations, which dissipate power and sense temperature differentials has been
successfully used since in many commercial applications. The “HP thermocouple” is shown
schematically in Figure 2.
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Si (n+)
Insulating
layer
Hot
junction
Si
substrate
Figure 2. Structure o f the HP 8481A thermocouple chip [1].
More recently, devices based on the same principle were developed using advanced
micromachining steps [66]. These steps include silicon fusion bonding, buried silicon nitride
layers, and epitaxy on fusion bonded wafers, and are therefore not commercially available and
compatible with standard IC processes. While these custom made devices show impressive
performance characteristics they are nevertheless bulkier, cost more to fabricate, and lack circuit
integration capability.
1.7 CONTRIBUTION OF THE DISSERTATION
This Dissertation presents for the first time a method for fabricating broadband
microwave power sensors in standard CMOS technology. Design of the microwave sensors is
fully compatible with commercial CAD tools for CMOS design, and the integrated circuits can
be fabricated through any CMOS processing facility. The fabricated CMOS precursors are
thereafter micromachined by a low-cost maskless etch procedure. The emphasis on CMOS and
simplicity of post-processing should make such technology readily available to other research
institutions, and a variety of military and commercial applications.
The description of the two novel devices is given in Chapter 2. The main contribution of
this chapter is the novel integration of fully-suspended transmission lines, matched terminations,
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and thermocouples in two different working configurations to achieve broadband microwave
performance and sufficient sensitivity. Moreover, the chapter introduces the implementation of
the devices utilizing standard CMOS layers and CMOS precursor fabrication.
In Chapter 3, the complete fabrication procedure is given. The basic parts of the post­
processing methodology were previously introduced in Master’s thesis work [9], as well as the
hybrid etch which allows micromachining of larger and longer structures such as transmission
lines. In this chapter, the isotropic and anisotropic etch steps are described in considerably more
detail. However, the main novel contribution in this chapter is the introduction of the ultrasonic
enhancement in the anisotropic etch to enable the power sensors’ fabrication, and achieve
relatively high yield in research environment.
For the first time, in Chapter 4, coplanar waveguides on standard CMOS-grade silicon
were accurately characterized and modeled from 0.1 GHz to 40 GHz. This, first part o f the
chapter, which includes most recent techniques for characteristic impedance measurement, and a
quasi-TEM model, provides a thorough description of microwave properties of such transmission
lines on CMOS-grade silicon substrate.
This in turn explains that integration of efficient
microwave sensors is unrealizable without the removal of the lossy silicon substrate from the
vicinity of high-frequency structures. On the other hand, the models and measurements can be
very useful in predicting performance of VLSI interconnects at exceedingly high clock
frequencies. In the second part of Chapter 4, a detailed description of the design procedure o f the
fully-suspended CPWs is provided including analysis and numerical computation of performance
for the fully-suspended structures. The work substantially extends the first introduction of the
micromachined CPWs in Master’s thesis [9] in the following ways. New configurations of fullysuspended CPWs are introduced, as well as detailed description o f design for micromachining.
The models in this work are fully analytical and do not require any numerical code to obtain
effective permittivity as in [9], such that design for desired characteristic impedance is
simplified. Also, the analysis introduces a rule of thumb of necessary etching depth for sufficient
isolation of CPWs from lossy silicon substrate, and supports it with similar analysis. Finally, a
numerical integral equation technique is used to verify the model equation, and based on the
given analysis, electrostatic Green’s functions are derived for the glass-encapsulated, fullysuspended CPWs.
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Another significant contribution of the Dissertation is the thermoelectric modeling and
optimization of a sensor.
The simple, but sufficiently accurate thermoelectric model helps
explain sources of non-linearity and transfer differences in the devices, but is also a very useful
tool for optimization of the devices’ sensitivity and long-term performance.
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CHAPTER 2 - MICROWAVE POWER SENSOR DESIGN
This chapter introduces the top-down methodology of the designs of thermocouple
microwave sensors both from thermoelectric and electromagnetic aspects. The main concepts of
thermoelectricity are introduced to better understand the basic design and functioning of the
sensors, as well as to subsequently understand the sources of error and non-linearity in the same.
A low-frequency thermoconverter example is used to describe the operating principle, and derive
simple equations that predict sensitivity.
The achievement of microwave frequency operation is due to the integration of
transmission lines and matched terminations, while thermocouples are utilized as actual sensing
elements. Following this design flow, we arrived at two types of configurations, the indirectlyheated and directly-heated thermocouple sensor. Two sensors are then described in detail,
corresponding to the two types, the indirectly-heated thermocouple device - Sensor 1, and the
directly-heated thermocouple device - Sensor 2. The basic design constraints relating to the
dynamic range, input mismatch error, and reliability are discussed.
2.1 THERMOELECTRICITY
Thermoelectricity is electricity generated by heat [70].
As mentioned earlier in the
introductory chapter, we distinguish three thermoelectric effects that govern the relationship
between current and heat flows in conductors: Seebeck, Peltier, and Thomson effects. In 1857,
Thomson (Lord Kelvin) formulated the first thermodynamic theory of thermoelectricity, and
derived the relations between the thermoelectric effects. The theory was firmly established in
1931 by Onsager. For a detailed theory of thermoelectricity, we refer to available literature, e.g.
[69],[73],[81].
Thermoelectric effects are used in a wide range of sensor and actuator
applications, e.g. thermocouple power sensors, radiation and flow sensors, pressure gauges,
thermoelectric power generators, and Peltier heaters/coolers.
2.1.1 SEEBECK EFFECT
In the thermoconverter type applications, the dominating effect is the Seebeck effect
[73],[81]. In 1821, Seebeck reported some experiments which showed that he had observed the
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first of the thermoelectric effects. He had produced potential differences by heating the junctions
between dissimilar conductors. The Seebeck effect is present in bulk material, and it results from
the temperature dependence of the Fermi energy £>, where it holds for the Seebeck coefficient eta
that [73]:
a
1 dEc
(8)
qdT
where q denotes an elementary charge, and T temperature. Although this effect is a bulk property
of a material, it is only useful in temperature measurements when two different materials (with
different Seebeck coefficients) are combined into a thermocouple, as shown schematically in
Figure 3. In the figure, on the left side is the junction of the two materials at raised temperature
T2, which is termed the hot-junction. The right hand side at temperature Tt is not shown in
contact, but contact is implied either in terms of voltage measurement probes, or additional
thermocouples in series, and is therefore termed the cold-junction.
Figure 3. Single thermocouple sensor composedfrom two different materials in contact.
The output voltage of the thermocouple is then Vlc = (a a —a b) ( T 2 —Tl ) =
-A T .
Here, the Seebeck effect was combined into a single coefficient for the thermocouple, Q^, which
is given as the difference of the bulk Seebeck coefficients for each of the materials forming the
thermocouple.
In the setup where such a thermocouple is used to sense the temperature
difference due to the dissipated heat in the resistor, we assume that the hot junction of the
thermocouple is in direct proximity of the resistor at temperature (7*2=7), and that the cold
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junctions are at reference temperature (Ti - T q). The total voltage output in terms of dissipated
incident power then is:
v « = « * - c r - r 0)
-
a
.
,
(9)
g t
where the relation in (7) was used to express the temperature difference in terms of dissipated
power. In micromachined CMOS transducers, Seebeck coefficients ranging from less than 10
juV/K up to 851 fiV /K are feasible from the various possible combinations of p-doped
polysilicon, /i-doped polysilicon, and metal [17]. The processes through which our devices were
fabricated did not provide a variety of polysilicon doping and type, and therefore all of the
devices were designed using polyl or poly2 and metal 1, which results in Seebeck of roughly 110
pV/K.
2.1.2 PELTIER EFFECT
The Peltier effect [73],[81] is related to current and temperature at a junction of two
materials. When a current flows through a junction of two different conductors, heat is either
absorbed or released, the effect depending on the direction of the current flow. The rate of
absorbed or released Peltier heat qp is proportional to the current flow I and the relative Peltier
coefficient JCab'-
qP =**(?)• I .
(10)
The first Kelvin relation relates the Peltier coefficient with the Seebeck coefficient as [73],[81]:
* a* (r )= a a*-:r.
(11)
In [17], Peltier coefficient of -32 mV was reported at 300K for their CMOS process. This is
relatively high coefficient, due to the high Seebeck coefficients achievable in that process.
Therefore, in a thermoconverter application, Peltier effect can at higher currents (high power
measurement) result in significant deviation from linearity. On the other hand, in high frequency
applications, the Peltier heat changes sign much faster than the thermal time constant of the
system and the effect is therefore canceled.
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2 .1 3 THOMSON EFFECT
The third, Thomson effect arises from the temperature dependence of the Seebeck
coefficient [73],[81]. When a temperature difference A T is applied along the conductor of finite
resistance, in which a current flow causes the generation of Joule heat, an additional amount of
heat q,h is absorbed from or released depending on the relative direction of the current flow and
the temperature gradient direction. The Thomson heat generation or absorption rate q,h is defined
as:
02)
where Yth denotes the Thomson coefficient. The second Kelvin relation connects the Seebeck
effect with the Thomson effect as:
r.
=7 ^§|P-
<13>
As for the Peltier coefficient, Thomson coefficient of -61 pV/K was computed at 300 K for the
polysilicon heating resistor in [17].
2.1.4 THERMOPILE
An advantage of using thermocouples as voltage sources proportional to the dissipated
power is that a large number of such thermocouples can be connected in series into a thermopile
configuration to obtain significantly larger output voltage. This is schematically shown in Figure
4, and a microphotograph of such a device fabricated in CMOS MEMS is shown in Figure 5.
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Etch pit for
thermal
isolation
Figure 4. Schematic ac-dc thermoconverter based on twelve series thermocouples.
Etch pit
Thermocouples
in series
Figure 5. SEM micrograph o f ac-dc thermoconverter based on 12 series thermocouples, schematically
described in Figure 4.
For the thermopile such as in Figure 4, the voltage output is a linear combination of outputs from
each thermocouple:
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V „ = ’£ a l*-(TI - T I) T I .
(14)
;=!
As seen in (14), the total output of the thermopile is not simply a multiple of that from one
thermocouple since the resistor has a certain temperature distribution over its length, resulting in
temperatures 7/ in direct vicinity of each hot thermocouple junction. Moreover, coefficients r,
signify the fact that the hot junction is some distance d away from the heater and is actually at
some lower temperature such that the total temperature difference across the thermocouple is
weighed by this number. These coefficients and the temperature distribution, therefore, need to
be determined from the structure, perhaps using numerical computation, to be able to predict
total voltage output of such a sensor a some given applied power.
The configuration in Figure 5 achieves good performance only in the megahertz
frequency range, similarly as the various configurations of Jaeggi et al [8].
To adapt the
thermoconverter concept for microwave power measurement, we based the configurations in this
work on carefully designed transmission lines and matched terminations.
Namely, in 50
£2 transmission lines, the capacitance and inductance per unit length balance in such a way to
obtain very small frequency dependence, mainly due to imperfect metals. Such a structure based
on 50 £2 lines requires large ground planes which are otherwise undesirable since they behave as
heat sinks. When properly terminated in 50 £2 resistance with very small parasitic reactance it
can be a very broadband matched device and can therefore be operated well into gigahertz
frequency.
Integration with transmission lines is significant for a number of reasons. Ultimately, it
allows for integration of the sensors with larger systems, such as in our effort to achieve low-cost
passive receivers in CMOS for EHF applications. From the measurement standpoint, the input
transmission line was used as the de-embedding element which thereby allowed us to measure
the sensor performance without packaging/probing parasitics. Lastly, the input CPW attenuates
all parasitic non-CPW modes spurring from the packaging/probing area. The details o f this
integration will be shown in many subsequent sections. Firstly, we will introduce two basic
configurations that result in somewhat different device implementations.
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2.2 INDIRECTLY v s. DIRECTLY-HEATED THERMOCOUPLE
SENSORS
In this Dissertation, we distinguish two types of thermocouple power sensor design, the
directly-heated, and indirectly-heated thermocouple sensors. Both types are often used, and were
therefore investigated in this work. The indirectly-heated thermocouple sensor was conceptually
described in Section 2.1.4 and is the main focus of the work. The integration of the new
microwave implementation of that sensor is depicted in Figure 6a. In this case, microwave
transmission lines convey input RF power to a resistor which is heated by the dissipated rf
power. The generated heat flow raises the temperature of the nearby hot thermocouple junctions
which are not in direct electrical contact. The resulting steady-state temperature difference is
directly proportional to amount of dissipated RF power.
Transm ission lines
Termination
T herm ocouples
Thermal contacts
(a)
Transm ission lines
Termination/ T herm ocouples
DC Blocking
C apacitor
(b)
Figure 6. Schematics o f the two sensors’ configurations: (a) indirectly-heated configuration, and (b)
directly heated configuration.
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Directly heated thermocouple sensors (see Figure 6b) are also very often used in
microwave applications. In this case, the RF termination which dissipates the incoming RF
power at the same time performs as a thermocouple which is therefore directly heated. One can
imagine a simple implementation where the 50 Q terminating resistor consists of two different
materials, which are tapered thin toward their point of contact, such that a Seebeck dc voltage is
generated across the termination when RF signal generates heat. In most applications, however,
a somewhat more complex design with two thermocouples in series is usually found, first
patented at Hewlett-Packard in 1971. The two-thermocouple configuration is accomplished by
adding a dc blocking capacitor, as shown in Figure 6b, and splitting the termination into two
resistors. An example is the structure shown previously in Figure 2. Our implementation o f the
device structure will be discussed in detail in Section 2.4.
2.3 INDIRECTLY-HEATED THERMOCOUPLE DEVICE - SENSOR 1
In terms of indirect-heating thermoelectric design, Sensor 1 is based on the low-frequency
counterparts, such as shown in Figure 5, and described in [8]. However, the proposed new type
of micromachined thermoelectric converter is comprised of a new arrangement of transmission
lines, resistive terminations, and thermocouple contacts, such that it is operable at microwave
frequencies in a very broadband range. The power actually dissipated in the termination Pdiss (the
sensed power) is a function of incident power, reflections at input and load, and attenuation in the
CPW. The power dissipated in the load as a function of the load reflection coefficient is [21]:
where Yq is the characteristic admittance of the transmission line (Yo=I/Zo), and V* is the rms
voltage of the forward travelling wave before the load. The rms of the forward travelling wave is
an attenuated version of the wave leaving the source, due to reflection losses at the input pads
approximated as (1- l r pads I2), and propagation losses in the CPW transmission line
approximated as exp(-occpwLcpw), where LCpw is the CPW length, and acpw is the real part of the
CPW propagation constant, characterizing the loss.
In this work, we assumed the reflection losses at the input pads negligible in the
characterization of the sensors, due to application of proper de-embedding of input pads.
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Namely, through proper calibration, we mathematically impose (1- I r ^ l 2)~I on any
measurements of the sensor structure. In a final, fully packaged device these reflection losses
would be an important part of optimization.
Finally, to obtain good efficiency and small
frequency dependence, we concentrated on achieving low CPW loss and as low as possible load
mismatch reflection coefficient II/mb/I. The details of CPW design, analysis and characterization
are given in Chapter 5, and we concentrate on the broadband match in the following.
The broadband aspect of the layout depicted in Figure 7 is based on the carefully designed
CPWs, terminated in a matching 50 Q resistance of very small electrical size, such that it has
negligible frequency dependence. In the approximate limit, the termination and the CPW should
have negligible reactance, such that the only source of inefficiency comes from the possible
resistance variations in the termination:
r
-
(16)
~ ? SL
* l+ Z o '
This resistance variation is present in device’s operation due to the thermistor effect, and may
even have time dependence, and will be discussed in more detail in Section 6.2.1.
termination
RF input
Metal 1 (Al)
Metal2 (Al)
Probing pad
Polysilicon
thermopile
DC output
J Open area
Ohmic contact
Figure 7. Layout o f the indirectly-heated thermocouple microwave power sensor fo r CMOS MEMS
fabrication —Sensor 1.
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To accomplish the above goals, a low-loss 50 £2 micromachined CPW, described in detail
in Chapter 5, provides the input connection to the matched resistive load, which converts the
incident RF energy into heat, as shown in the layout of Figure 7. This accurately matched
resistive load is formed by a distributed network tee-transmission line as shown.
The
characteristic impedance of the transmission lines in each of the distributed arms of the tee is 100
£2. The resistive value of the center conductor in each arm of the tee is also 100 £2 at dc. The net
input impedance of the complete thermoelectric sensor assembly as seen by a CPW source is
therefore 50 £2, as desired. As a result of the tee-configuration, the RF input is satisfied in terms
of broadband matching, while at the same time we provided a simple way of combining the
termination with a large number of adjacent thermocouples.
Namely, the longer length of
resistors necessary to obtain 100 £2 at dc, as well as the fact that we need two resistors provide
almost entire side length of the CPW for thermocouple temperature sensing.
Because of the required resistance of 100 £2 at dc, and the given sheet resistance of
polysilicon in the chosen CMOS process (usually around 25 £2/sq,) we are locked into a
particular length-to-width aspect ratio of the resistors. However, we can design larger or smaller
resistors with this aspect ratio and obtain same 100 £2, so it is important to understand the effect
of varying the resistor size on overall performance.
The effect is multifold, and proper
optimization is a difficult multidimensional problem that will be addressed in part in Chapter 7.
Nevertheless, there are some guidelines to follow in the designs which are known to improve
performance.
Firstly, the size of the resistor directly affects the operating input power range o f the
device, since it changes current density, and therefore resulting temperature at constant power.
Since we are interested in measuring very small powers below 1 fiW, the size of the resistor
should be very small, such that the small power results in measurable temperature difference
(sufficient signal to noise ratio). This however badly affects the higher end of the power range.
Namely, at maximum power o f 10 mW, such a small resistor would heat to temperatures where it
may be destroyed. Even before the resistor bums, the resistance will be increased so much by the
thermistor effect, that the device will be badly mismatched, as given by (15) and (16). Therefore,
once we have defined maximum allowable deviation of termination resistance from nominal
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cold-resistor value Ro, we have effectively set the maximum average temperature, and thereby
resistor size.
From a microwave perspective, we wish to make the resistor as small as possible, such
that it is electrically independent over the wide frequency range.
Figure 7 also shows two sets of closely spaced thermocouple junctions located on the
right-hand-side of the RF-heated resistive elements of the RF termination. Each of these hot
junctions is in series with a cold junction located above the base silicon material, forming a 24element thermopile. To better stabilize the temperature of the cold junctions to that of the
ensemble, the aluminum-polysilicon contacts of the cold junctions are covered with second-layer
metal. Thus, the thermoelectric sensor efficiently converts RF electrical energy to an output dc
voltage.
2.4 DIRECTLY-HEATED THERMOCOUPLE DEVICE - SENSOR 2
Our implementation of this device structure utilizes only aluminum and polysilicon
conductors, as for the indirectly heated device, instead of the custom layers usually used in
commercial devices. The operation of our implementation of the directly-heated thermocouple is
best described with an equivalent electrical circuit diagram as shown in Figure 8.
cold
poly
r-
metal1
hot
poly
metall
cold
TC,
Figure 8. Equivalent circuit representation o f the direct-heating implementation using two series
thermocouples, such as in the commercial HP 8481A device.
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Each thermocouple is an aluminum-polysilicon junction consisting of two resistors,
and Rmaaii, as illustrated in Figure 8. The combined series resistance of one thermocouple is
Rp^y + R metaI1=100 Q. The thermocouples are connected in series as far as the dc output is
concerned, which increases the output voltage while still maintaining very low resistance, and
therefore low noise. Looking from the microwave input, however, the two are in parallel,
together forming a 50 Q matching impedance termination. This is accomplished by connecting
the lower node of the left thermocouple (in Figure 8) directly to ground, and connecting the lower
node of the right thermocouple to “rf ground” through bypass capacitor Cb. Half the rf currents,
therefore, flow through each thermocouple, heating them proportionally to the rf power at the
input. The heat, however, is dissipated unevenly due to the layout, therefore forming the hot and
cold junctions necessary to generate the dc voltage.
RF input____________________________ sensor_______ dc blocking capacitor
Metal 1 (Al)
Probing pad
Metal2 (Al)
Polysilicon
DC output
BwwaaMI Open area
Ohmic contact
Figure 9. Layout o f the directly-heated thermocouple microwave power sensor for CMOS MEMS
fabrication - Sensor 2.
The layout in Figure 9 shows how the thermocouples/terminations are integrated into the
overall device that includes the input CPW, and output dc blocking capacitor. The CPW signal
line is split into two arms which continue straight, with very small separation between them.
This region is very small electrically, and the two sides have approximately same propagation
characteristics, including 100 £2 series resistance. Therefore we assume no significant field in
the gap is created, but the gap serves well as the dc circuit isolator such that we obtain two series
thermocouples. Following one arm of the split, the termination ends in the ground plane, which
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is also the lower plate of the output capacitor. Following the other arm (upper arm in Figure 9) is
the upper plate of the capacitor which is not connected anywhere, and provides output dc voltage
to the electrical probing pads shown. In the region of the thermocouples, we wish to create hot
and cold junctions by additional thermal isolation of the middle part (hot junctions) of the
termination, and additional heat-sinking of the outer contacts (cold junctions). This is done by
creating a wider gap of ground planes in the center region, with large opens on either side, and
therefore only air conducts heat in lateral directions from the hot junctions. On either end,
metal2 is utilized to cover the cold junctions and sink them effectively with the rest of the CPW
structure which remains near ambient temperature due to its high conductivity to surrounding
silicon substrate.
2.5 PERFORMANCE MEASURES
2.5.1 SENSITIVITY
The sensitivity of the sensor is defined as the slope of the output characteristic curve [70],
More generally, it is the minimum input of physical parameter (input power) that will create a
detectable output change. While the definitions can vary in different sensing applications, the
sensitivity of the microwave power sensor is defined as the ratio of the output voltage of
thermocouples
and the incident microwave power Pm, S=Vtj/Pm [V/W],
It can be seen from equations (7), (9), and (14), that increasing the sensitivity of the
thermopile power sensor requires the number of thermocouples to be high, the total thermal
conductance to be very low, and the thermocouples to be in close proximity with the heating
resistor.
These are conflicting requirements that establish the first trade-off, since the
thermocouples significantly increase thermal conductance. At the same time, lowering thermal
conductance results in higher temperatures which results in termination mismatch as defined in
(15) and (16), due to thermistor effect. This establishes the second important trade-off.
2.5.2 SIGNAL-TO-NOISE RATIO
For the thermopile-based sensor, main sources of noise are charge carriers in the resistive
thermocouples [13][17]. This thermal noise is white Gaussian in the frequencies of interest, and
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therefore frequency independent, and can be represented as a series voltage source in the
thermopile circuit, as depicted in Figure 10.
O
R tp
Figure 10. Schematic circuit o f the thermopile representing thermal noise as a series voltage source.
The thermal rms noise voltage Vn is defined as Vn=(4kTRvB)i/2, where k is the Boltzmann
constant, T is the absolute resistor temperature, B is the bandwidth of interest, and Rq, is the
thermopile resistance. The signal-to-noise ratio (SNR) depends on input power, and so it is
given in form normalized to input power as SNR=S/Vn [ W 1], or in decibel scale SNR=20
log(S/Vn).
This presents another important trade-off in the power sensor design. Namely, to reduce
thermal conductance through the thermopile, the thermocouples should be made very small in
width and very long in length.
Also, to increase output signal we wish to use as many
thermocouples as possible in series. Both of these in turn increase the series resistance in the
thermopile and therefore lower the achievable SNR.
2J53 DYNAMIC RANGE
The dynamic range of the power sensor is defined as the ratio of the maximum and
minimum input power, and is therefore a dimensionless parameter often expressed in decibels
(dB). As described above, the minimum detectable input power is limited by the noise of the
thermopile. Also affecting its measurement are ambient temperature changes, the problem that
can usually be successfully addressed with more complex configuration utilizing more than one
sensor.
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The maximum detectable input power is usually determined by structural and resistance
changes in the heater materials due to excessive heating. In the case of the microwave power
sensor, we define the maximum allowable deviation from desired 50 £2 termination resistance
due to thermistor effect, and find maximum measurable power where this occurs. This is yet
another trade-off in the design that promotes larger resistor design and higher thermal
conductance for colder temperatures at high power. This results in lower SNR and increases the
minimum detectable power. Therefore, the dynamic range is largely pre-determined by the
materials, in particular the CMOS layers. The CMOS polysilicon has significant tcR, and CMOS
aluminum has a relatively low melting temperature, therefore limiting performance to roughly 40
dB of dynamic range unless compensating interface circuitry is used [17].
2.5.4 THERMAL TIME CONSTANT
The thermal time constant of a thermocouple sensor defines the response time of the
sensor output to changes in input signal. Since the average power is defined in (2) by a long
integration, it is important for the thermal time constant to be much longer than the slowest input
signal time constant.
frequency.
Therefore, this performance measure defines the lowest measurable
It is governed by two thermal circuit equivalent parameters, the total thermal
conductance Gy. and the total thermal capacitance of the suspended converter membrane and
encapsulated layers Cy. As expected, analogous to electrical circuits, the thermal time constant
can be expressed as x,h=Ci/Gr.
Usually in micromachined thermoelectric sensors [8] [62], as well as in the earlier
versions of our microwave power sensors [67], the thermal time constant is a few milliseconds or
longer. Since the frequencies of interest (100 MHz and higher) exhibit time constants well below
a microsecond, this performance measure is not a major concern, and does not require trade-offs
with other measures above.
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CHAPTER 3 - POST-PROCESSING METHODOLOGY
A major challenge in the pursuit of smart sensor systems is integration with electronics on
single substrates. In past, through many custom fabrication methodologies of MEMS, various
miniature sensors and actuators have been achieved, but often without the capability for
monolithic integration with circuits. For these reasons, it is very desirable to utilize the standard
CMOS process as the technology of choice, and find ways to adapt it to allow fabrication of
sensor and actuator systems, and the integration of microwave components.
Various
micromachining techniques have been proposed for the post-processing of fully-fabricated
CMOS ICs, which allow thermal and mechanical sensors and actuators to form.
In this Dissertation, building on the achievements of Master’s thesis work, these
micromachining techniques were combined in a unique way to achieve electromagnetic and
thermal isolation of large areas on CMOS chips, for the integration of miniature passive
microwave components and sensors. A major limitation in the fabrication of microstructures as a
post-CMOS process has been therefore overcome by the development of the ultrasonically
enhanced hybrid etching technique which combines both an isotropic and an anisotropic etch
step.
In this Chapter, the complete methodology is described for the fabrication of the
microwave power sensors. Firstly, the design for maskless post-processing is introduced. Two
etchants are explored in detail for top-side maskless post micromachining of (100) silicon wafers
to obtain the microstructures. The isotropic etchant used is gas-phase xenon difluoride (XeF2 ),
while the wet anisotropic etchant is ethylenediamine-pyrocatechol in water (EDP), implemented
with ultrasonic liquid micromixing that allows undercutting of larger passive microwave
components and sensors.
3.1 STANDARD CMOS FABRICATION
The essential part of the fabrication of the microwave transmission lines and sensors is
standard CMOS process fabrication. This was done through the MOSIS foundry service [35]
which offers full CMOS fabrication of small, as well as large, projects in one of the offered
technologies. In this Dissertation work, various processes, offered by MOSIS, were used. Most
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frequently, devices were fabricated through the Orbit’s 2.0 fim n-well double-poly double-metal
process. We have also fabricated devices through HP’s 1.2 fim n-well process, AMI 1.2 jim. nwell process, and others.
Typically, layouts o f the designs were created in a standard VLSI CAD tool, such as
Cadence or Magic. The conductor strips were designed using in some cases the first layer metal
(aluminum), in some cases the second layer metal, and in some cases both metals, to provide less
series resistance. All of the structures were fabricated on p-substrates in analog n-well processes.
Since CMOS processing includes field oxide above the substrate, several interlayer oxides as
isolation layers, as well as top level passivation, any such fabricated microwave structures are
encapsulated in the dielectric of varying thickness, as depicted in Figure 25b.
Finalized layouts for process masks were stored in one of the standard formats, Caltech
Intermediate Format (CIF), or binary stream (GDS) format. These files were then submitted to
the MOSIS service, where they were verified and queued for fabrication. The fabrication cycle
took anywhere from 8 to 12 weeks. At that point, diced chips with fully fabricated CMOS
circuits, and precursors for sensors, returned to us for testing and post-processing as described in
detail in Chapter CHAPTER 2.
3.2 SILICON MICROMACHINING
In recent years, there has been growing interest in the research and development of
integrated microelectromechanical systems (MEMS).
Various pressure sensors
and
accelerometers [42], and millimeter-wave components [6],[43] have been fabricated using
specialized processes with backside micromachining.
Specialized processes may not
automatically allow for on-chip integration of electronics and require the development and
implementation of a circuit process along with the MEMS process.
Backside etching also
involves additional masks and alignment, as well as backside polishing, and therefore adds more
complexity.
Concurrently, there is also strong interest for developing microtransducers that are
compatible with commercial CMOS processes. Compatibility with CMOS allows for monolithic
integration of analog and digital circuits, which provide signal conditioning, interface control,
and capability for wireless remote communication. After receiving the precursor chips from the
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foundry, the micro-sensors or micro-actuators are then released by an additional maskless front­
side post-processing etch. The maskless aspect of the post-process comes from the fact that no
additional masks are required to define areas for micromachining since standard CMOS contact
layers are used to expose silicon substrate in selected areas, such that the precursors are ready for
etching immediately after CMOS fabrication.
Examples of these CMOS-compatible
microsystems are: temperature sensors [44], flow sensors [45], infrared thermal displays [46],
microwave components [10], [47] and solid-state conductometric chemical gas sensors [48].
Silicon micromachining is the key technology to fabricate micro-transducers and
actuators. To realize micro-transducers at low cost, there are several requirements on the post­
processing etching.
The chemical etchants must be compatible with materials used in the
commercial CMOS processes, namely, silicon dioxide, silicon nitride, and exposed aluminum.
The etchants must not contaminate the gate dielectrics with impurities such as mobile alkali ions,
which shift the flatband voltage and affect the circuits otherwise. Commonly used anisotropic
etchants are ethylenediamine-pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH),
ammonium hydroxide, and potassium hydroxide. More recently, xenon difluoride (XeF2 ) has
become a popular isotropic etch for micromachining. Depending on the design, the suspended
micro-transducers can be realized using either an isotropic or an anisotropic etch. Finally, other
requirements for these etchants are ease of handling and safety.
While the above mentioned CMOS-compatible micro-transducers with size ranging from
40 /Jm to 200 fim can be readily realized with either isotropic or anisotropic etching, larger or
longer microstructures, such as passive microwave components and sensors, cannot be achieved
with either etch alone. Large structures require unacceptably long anisotropic etch times, which
in turn cause many negative effects. By the time long structures such as the coplanar waveguides
are fully suspended, the aggressive EDP etchant attacks the glass layers and etches away the
exposed aluminum on the bonding pads, making the device mechanically unstable. Therefore,
etching is the limiting factor in realizing large suspended microstructures.
In the following sections, we introduce silicon etching in more detail, and present a novel
micromachining methodology which combines an isotropic etch step and an ultrasonicallyenhanced anisotropic etch step to release large or long suspended microstructures.
Length
independent microstructures can be achieved with clever design. Also, using this methodology,
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design placement of dielectric openings that expose the substrate to the etchant is significantly
simpler, and allows much more flexibility in the layout This in turn results in significantly
improved mechanical robustness since larger areas of supporting glass remain.
3.2.1 ISOTROPIC ETCHING WITH XENON DIFLUORIDE (XeF2)
The use of XeF2 for plasma etching of silicon and etching silicon with XeF2 without
plasma has been studied extensively for the last 15 years. Silicon is isotropically etched by
exposure to gaseous XeF2 at room temperature.
Only recently has XeF2 without plasma
enhancement been used to micromachine silicon to create micro-transducers [63]. Chang et al.
[49] have performed a detailed study of the etching characteristics of XeF2. An investigation of
the mechanisms of the etching of silicon with vapor XeF2 was given by Houle [50], Winters and
Cobum [51]; hence, this section only gives a brief description of the etching mechanisms.
The isotropic removal of bulk silicon substrate is schematically shown in Figure 2. The
figure shows a portion of a silicon substrate with silicon dioxide passivation which also acts as
the etch mask, and is therefore not present in the areas were etching is desired. These areas were
termed open areas or opens for easier reference and open was added as a design layer in Magic
CAD [7]. They are formed by superposing all of the contact oxide cuts in CMOS, namely for
MOSIS technologies active_area, active_contact, via, and glass (passivation cut).
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Figure 11. Schematic top view and a cross-section o f isotropic etching o f silicon by gaseous XeF2 using
Si02 as the mask.
Xenon difluoride is a white crystalline solid with a vapor pressure of about 600 Pa (4.5
Torr) at room temperature [50].
The reaction between XeF2 and silicon occurs through a
sequence of steps. Gaseous XeF2 is first absorbed on the silicon and then reacts to form a thick
layer of fluorosilyl consisting of SiF, Sip?, and SiF4 . The fluorosilyl product desorbs into the gas
phase. The principal gas-phase product has been determined to be S 1 F4 , which is volatile at room
temperature. The reaction equation for XeF2 and silicon is approximately given by:
2XeFz + Si 2Xe + SiF4.
(17)
It is relatively easy and inexpensive to set up the apparatus for XeF2 etching because XeF2
sublimes at a pressure of -600 Pa (4.5 Torr) at 300 K. The system used is schematically shown
in Figure 12. It consists of a short stainless steel vacuum chamber connected through a gate
valve and a liquid nitrogen cold-trap to a mechanical vacuum pump. Also attached to the
chamber, as shown in Figure 12, is a pressure gauge, and two valve-equipped inlets, one for
nitrogen gas, and the other for the XeF2 source compartment. The chamber is also equipped with
a removable flange door that enables easy sample interchange and also provides electrical
feedthroughs.
On the top of the chamber is a glass viewport equipped with an optical
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microscope, which provides visual monitoring of the etching process. XeF2 vapor is introduced
into the vacuum chamber by opening and closing a valve that provides isolation of the solid XeF2
from the vacuum. Since XeF2 reacts with moisture to form highly corrosive hydrofluoric acid,
the XeF2 source should be kept in a dry box. The entire system is located in a fumehood and the
etching process is fully automated. All valves are controlled by a PC computer through an I/O
interface. The power needed to open and close the valves is provided by a voltage source, a
simple switching circuit, and a high-pressure air source for the pneumatic valve action.
A -S -
N,
L.
m
m
B B bbH
1
/
ETCHINGCHAMBER
W/ VIEWPORT
REMOVABLE FLANGE
W/ ELECTRICAL
FEEDTHROUGH
ROUGHING
PUMP
9
Air operated
valve N/C
Gate valve
Needle valve
Figure 12. Schematic diagram o f the XeF2etching station.
A XeF2 etch is performed in short cycles of 30 s duration, consisting of the following.
The vacuum chamber is first pumped down to 2.7 Pa (20 mTorr) before opening the XeF2 valve.
After closing the vacuum valve, XeF2 flows into the chamber until a target pressure of 3.0 Torr is
reached. This may take up to about 10 s, at which point the XeF2 valve is closed, and a waiting
time of about 20 s is allowed for etching. Silicon does not start etching instantaneously upon
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exposure to XeF2 ; it first requires the formation of a few fluorosilyl layers. The chamber is then
backfilled with nitrogen gas and the dominant volatile byproduct, SiF4, is pumped from the
chamber until its pressure is below 2.7 Pa (20 mTorr) before the next cycle begins. In this
method, which is called the pulse method, the actual etch rate of silicon varies depending on the
amount of exposed silicon and other parameters such as pressure and temperature. The effect of
silicon loading and temperature dependence has been examined by Chang et al [49]. Most of the
parameters in the above procedures can be set up differently on the computer, depending on
particular goals of the etch. For example, for very good control of distance and high uniformity,
the etch is performed at significantly lower pressure, usually less than 1 Torr.
XeF2 is fully compatible with materials used in commercial CMOS processes. Namely,
no noticeable attack of silicon dioxide, silicon nitride, and aluminum is found. Consequently, a
thin layer of silicon dioxide can be used as a mask for the etching of silicon. XeF2 is extremely
selective to silicon and, thus, is perhaps an ideal post-CMOS etchant. However, in this work
XeF2 was found to attack iridium and gold. About 30 nm of gold was etched away after ten
pulses of XeF2 etch. This contradicts the finding of Chang et al [49] who reported that XeF2
does not attack gold. In addition, a commercial vacuum gauge with a gold-plated sensor, which
was connected to the XeF2 etching chamber, became nonfunctional after exposure to several
pulses of XeF2 gas. It is unusual to find that XeF2 attacks both gold and iridium since they are
relatively inert materials. We have also observed XeF2 attack on tungsten and silver films, but
have not yet quantified the effects.
Etching with XeF2 is applicable to packaged as well as unpackaged chips.
For
unpackaged chips, photoresist can be used to protect the back-side and peripheries of the chip
because XeF2 will etch any exposed silicon, resulting in significant thinning of the chip. The
glass openings {open areas in Magic CAD), defined by the superposition of an active area, an
active-contact cut, a via, and a glass cut in the layout file, are areas where the silicon surface is
exposed for etching. If the glass openings are fabricated from the foundry according to the
design specifications, the silicon surface in those areas is covered only with a very thin layer of
native oxide. In most cases, no stripping of the native oxide layer is necessary, and the chips are
readily etched. In some cases, however, due to process modifications at the foundry, sufficient
glass remains in the openings to prevent etching. To assure etching of the desired areas, it is
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recommended that the thin layer of native oxide be removed by a 10 s dip in buffered HF before
etching. In addition, since moisture reacts with XeF2 to form hydrofluoric acid, which attacks
SiC>2 , the chips are baked at 120 °C prior to etching.
open
area
. Etched
pit
Very thin
oxide
(a)
Etched
Diffusion
resistors
(b)
Figure 13. (a) Micro-heater designed fo r XeF2 etching; (b) test structure fo r monitoring micro-heater
and microwave coplanar waveguide in XeF2 etching. Pad size is 100 pm x 100 pm.
Microtransducers that are designed for XeF2 etching should reflect the isotropy of the
etching profile. Because of the high silicon selectivity of XeF2 in CMOS processes, Si02 may be
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used as the mask. The isotropic etching creates small cavities around each glass opening which
propagate radially outward, resulting in an etched pit shaped like a bathtub as shown in Figure
13. Shown in Figure 13a is an example of a new micro-heater design which takes advantage of
the isotropy of the XeF2 etch. A small 20 pm diameter glass opening exposes the silicon for
etching. The etching undercuts the microstructure, which is 80 pm in diameter, and suspends it.
For better thermal isolation, only a thin layer of Si02 about the thickness of the gate oxide is left
suspended between the micro-heater and the substrate. This is incorporated into the design with
the glass cut, the via cut, and the active-layer in the layout file.
XeFi etches silicon very rapidly, making dimensional control very difficult. Determining
when etching is complete often simply requires a visual inspection through a microscope
mounted over the etching chamber viewport.
However, for better automation, and tighter
dimensional control, an on-chip test structure can be monitored. An example of a test structure
for monitoring the micro-heaters and coplanar microwave transmission lines is shown in Figure
13b.
Two quadrants are designed with parallel /i-diffusion resistors that are electrically
monitored. When XeFi etches away the first ^-diffusion resistors in either the vertical or the
horizontal directions, about 5 pm more etching is needed. At this point, the pulse duration is
reduced to provide better control. Since the etch rate of silicon is more linear at pressures over
the range 10"6 Pa (10'8 Torr) to 66.6 Pa (0.5 Torr), another way to terminate the etching with high
precision is to etch at a lower pressure. In either case, when an open circuit is detected in the
second n-diffusion resistor, etching is automatically terminated. This test structure allows for
micrometer-precision control of XeF2 etching. For most micromachined transducers, this level
of control is sufficient. An advantage of employing gas-phase XeF2 over liquid anisotropic
etchants like EDP or TMAH is improved reliability giving yields close to 100%.
In wet
anisotropic etching, thin membranes cannot be fabricated due to hydrogen bubbles adhering to
the surface. These problems do not occur in gas-phase etching using XeF2 , and gate oxides (-40
nm thick) have successfully been used as membranes to suspend structures as far as 25 pm from
the edge of the etch pit, as shown in Figure 13a.
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3.2.2 ANISOTROPIC ETCHING OF CRYSTAL SILICON
In anisotropic etching, silicon is selectively removed at a rate which depends on the
orientation of the crystal lattice structure, hi general, etch rate of {100} crystal planes is more
than twenty times faster than the etch rate of the {111} planes for most anisotropic etchants.
Silicon substrates used in CMOS processes are (100) oriented and anisotropic etching therefore
forms an inverted, truncated pyramid type pit, as shown in Figure 14. The sidewalls of the pit are
bounded by the {111} planes, which make a 54.7° angle with the substrate surface.
Highly boron
doped silicon
Highly boron
doped silicon
Figure 14. Top view and cross section o f etched pit bounded by <111> planes fabricated by anisotropic
etching using highly boron doped silicon as the etched stop.
In standard CMOS foundries, the wafers are supplied with a flat parallel to the {110} planes
which is used for alignment. The design considerations to achieve suspended micro-transducers
with front-side maskless post-processing etching have already been reported extensively [13] and
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are not discussed here. Also shown in Figure 14 is a highly boron doped silicon ring (pdiffusion/guard ring) which is added into the precursor layout as a lateral etch stop. This is
because the etchant used in that case (EDP, following section) etches highly boron-doped silicon
at a substantially slower rate than the bulk substrate.
Commonly used wet anisotropic etchants can be classified into three types: alkali metal
hydroxides [14], diamines-based [15], and quaternary ammonium hydroxides [16]-[19]. Alkali
metal hydroxides such as potassium hydroxide (KOH) have a high silicon etch rate and
anisotropy. Unfortunately, KOH is not post-CMOS compatible because it attacks aluminum and
SK>2 , and contaminates the gate oxides with mobile alkali metal ions. EDP is a commonly used
etchant and is discussed in Section 3.2.3. The quaternary ammonium hydroxides fulfill the
requirements of CMOS-compatibility and are still being investigated for micromachining
applications. In this group, tetramethylammonium hydroxide (TMAH) is the prefered etchant
because it has a fairly high silicon etch rate. However, despite many reports in the literature [16][19], it is still not well understood, and reproducibility is still a big problem. While TMAH was
used in many trial fabrications, it was not nearly as successful at fabricating the microwave
sensors and related passive microwave structures as EDP. This is believed to be mainly due to
the lack of ultrasonic mixing, which will be discussed in detail in Section 3.3, and not due to the
etchant itself which performs well for some other applications. As a result, TMAH etching is not
described here, but details of the process are given in [11].
The apparatus for anisotropic etching is very simple. The entire system, which consists of
a hotplate, a magnetic stirring bead, a pyrex glass beaker, a thermometer, a nitrogen gas bubbler,
and a reflux condenser to minimize the loss o f water, is placed inside the fumehood. Hotplate is
connected in closed loop with a thermocouple sensor which monitors the etchant temperature
through an immersed glass tube, such that temperature can be tightly controlled during etching.
In addition, the glass beaker can be placed inside an ultrasonic cleaner half-filled with deionized
water, which then gives micromixing capability when used at small powers.
3.23 ETHYLENEDIAMINE PYROCATECHOL WATER (EDP)
Ethylenediamine-pyrocatechol-water with a small amount of pyrazine is a wellestablished etchant for the anisotropic etching of single-crystal silicon and finds extensive
38
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application in silicon micromachining [14],[15]. There are several types of EDP etchants with
different compositions, known as types B, T, S, and F. Types T and F have a high silicon etch
rate while type B and S have a low silicon etch rate. They are readily commercially available.
Only types S and F are used in this work. Type F has a higher water and pyrocatechol content
than type S. We used type F almost exclusively because type S attacked exposed aluminum (e.g.
bonding pads) more vigorously during the longer etch time required for type S to fully release the
structures. This finding contradicts results of Lenggenhager [21], who reported that type S is the
preferred anisotropic etchant for CMOS-compatible micro-transducers because it has the highest
selectivity between silicon and aluminum. This apparent contradiction may be caused by the
differences between the chip-fabrication processes at the respective foundries used.
Fresh EDP type F etchant has a pale amber color which darkens after a few hours of use
and exhibits a deep red color when it becomes unusable. Etching is generally performed in the
temperature range 92°-100°C which gives an etch rate of about 70 /an/h for (100) silicon. The
etch rate increases as the solution is exposed to air for some time. EDP etching is a relatively
awkward process and chips etched with EDP tend to deteriorate over a long period of time unless
they are rinsed very well for many hours after etching. The problem with EDP, when used at
lower temperatures, is the formation of a thin layer of insoluble residue. If this residue is not
washed away, it will destroy all the structures on the chip by corrosion. The cleaning procedure
starts with rinsing in a low flow rate of deionized (DI) water for 20 min. The chips are then left
in a large bath of DI water for 8 hours to 12 hours. Significantly shorter time in the DI water
bath does not remove all of the adsorbed EDP from the chip and/or package, resulting in long­
term residue build-up and undesired further etching. Care must be taken to avoid damaging the
suspended microstructures during cleaning. No visible residue was observed for type F when
etched in the above temperature range. An SEM picture of a CMOS-compatible micro-hotplate
designed to detect gases is shown in Figure 15a, and a customized version of this chip with
tungsten contacts is shown in Figure 15b. Unlike the quaternary ammonium hydroxide etchants,
EDP has no problem with the formation of “hillocks” which tend to stop the etching prematurely.
The etched surfaces of (100) (bottom of the etched pit) and (111) (side walls of the etched pit)
oriented silicon are quite smooth as shown in Figure 15b.
39
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W contacts
(b)
Figure 15. Micro-hotplate conductometric chemical gas sensors etched in EDP from (a) a CMOS
process; (b) a specialized process with tungsten contacts.
One main advantage of using EDP is that etching is self-terminated by highly boron-doped
silicon which is a very effective etch stop. EDP type F is only moderately selective against
aluminum (metall and metal2 in the MOSIS 2 fJm process) and will etch away all the aluminum
on the bonding pads in 2 h; therefore, this must be taken into consideration when designing
micro-transducers for EDP etching, or pads must be protected during the etch.
40
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3.3 HYBRID ETCH
The hybrid micromachining technique presented in the Master’s thesis [9] was motivated
by the work on the development of microwave coplanar waveguides (transmission lines). In this
work, the technique was modified and improved to allow fabrication of more advanced CPWs
and power sensors. These structures can now be significantly more mechanically robust, and
fabricated at a high yield for a research environment. This method is also very general and can
be applied to fabricate any large microstructure.
For commercial applications, these microwave sensors must meet two stringent
requirements: good low-loss and high sensitivity performance and mechanical robustness. The
performance of the first generation CPWs [10] with 50 Q nominal characteristic impedance met
the design goals of 2 dB/cm to 4 dB/cm attenuation over the frequency range 1 GHz to 40 GHz.
Without micromachining the silicon underneath the waveguides, as shown in [10], the observed
loss of over 40 dB/cm at 40 GHz was too high and rendered the waveguide impractical. Thus,
removing the lossy silicon is essential to obtaining good microwave frequency performance.
Since the waveguide is completely suspended, its mechanical robustness is an important issue.
In earlier experiments, attempts were made to fabricate 2 mm to 3 mm long waveguides
using only anisotropic etching. The design requirements to achieve the overlapping of etch pits
to form one long etch pit beneath the waveguide were very strict, and allowed very little variation
in metal linewidths. A SEM micrograph of an early coplanar waveguide in CMOS is shown in
Figure 16. In the figure, a number of disadvantages are apparent. The supporting glass remains
in relatively small areas, due to the overlapping etch design requirements. This weakens the
structure. Also, as pointed out in Figure 16, in order to etch beneath the waveguide, and connect
all individual etch pits into one large pit, a dielectric open must be placed in the center o f the
waveguide resulting in awkward and reflective pad connections. More importantly, the etching
progressed along the length of the waveguides, which took many hours, and required different
etching procedure for different waveguide lengths. Due to the very long time in EDP, chips
accrued substantial damage to the bond pads and supporting passivation. The longer waveguides
were usually broken during wet anisotropic etching even at very low stirring rates, and the yields
41
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were very low. Moreover, excessive care had to be taken during cleaning and handling of those
chips that survived the wet etch.
Figure 16. Anisotropic post-processing etching o f microwave coplanar waveguide.
Combining the isotropic and anisotropic etch as a hybrid etch into the post-fabrication
processing has many advantages. The design requirements are much more flexible due to the
inherent undercutting of the isotropic etch. This means that the placement of opens no longer
dictates the layout, and the opens can have significantly smaller areas, leaving more mechanical
support and more area for devices. On the other hand, the desirable etch stop control and depth
of etch pits of the anisotropic etch are also obtained, but with significantly less etch time
required.
The hybrid etching method consists of a two-step process in which an isotropic etch
undercuts the masks to remove all the silicon and an anisotropic etch forms a well-controlled
deep V-shape channel. Because the first step is isotropic etching to remove all the silicon
beneath the waveguides, the opens should be placed in such a way that the etched regions formed
by two adjacent openings on opposite sides of the waveguides merge together directly beneath
the center of the device. A section of a completed waveguide before and after XeF^ etching is
42
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shown in Figure 17a and Figure 17b, respectively. Even though most of the lossy silicon was
removed, the bottom is still close enough for the microwave fields to “see” the silicon substrate.
The second step consists of an anisotropic etch in EDP to create a well-defined deep V-shape pit
as shown in Figure 17c.
The hybrid micromachining technique allows for fabrication of CMOS coplanar
microwave devices by significantly reducing the etch time, yet preserves the anisotropic
characteristics of the micromachining. This technique is very general and can be applied to make
large microstructures of any size and length, including T-shaped structures such as power
dividers, etc.
We have used this etching technique to fabricate microwave power sensors,
antennas, and microfluidic channels [74]. Because this etching method is fully compatible with
CMOS technology, it allows for on-chip integration of electronics for signal conditioning and
communications. Future work will focus on using this hybrid micromachining technique to
develop various CMOS-compatible microwave coplan ar components and antennas for
applications in telecommunications and well-defined long microfluidic channels for biochemical
applications [74].
(a)
(b)
(c)
Figure 17. Hybrid Post-processing etching, (a) microwave coplanar waveguide as fabricated by a
commercialfoundry; (b) after XeFi etching; (c) after hybrid etching.
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33.1 ULTRASONICALLY ENHANCED ANISOTROPIC ETCH IN HYBRID
ETCH
While investigating the hybrid etching procedure for the passive microwave structures, a
problem was encountered that was not previously observed in CMOS MEMS sensor work such
as in references [7] [62]. Namely, the hybrid etch presents the anisotropic etchant with a much
more difficult “task”, since it must etch large volumes of silicon which are not directly exposed
to the etching solution, but are accessed through relatively small opens. This is shown in the test
structure example of Figure 18. The area of the opens is much smaller than the total area of
desired etch pit. The effect of this is that the etchant must efficiently exchange through these
limited openings to access the large surfaces of silicon, which need to be etched.
(a)
(b)
Figure 18. Test structure with two circular opens after (a) hybrid etch, and (b) ultrasonically enhanced
hybrid etch.
This is augmented by the fact that in wet anisotropic etching of silicon, hydrogen is
released in bubbles, which can effectively plug the openings through which the etchant accesses
the silicon. We have not observed this problem with the gaseous isotropic etch, although when
opens are limitingly small, uniformity of etching becomes difficult to achieve. One solution to
the problem which we implemented is to perform the etch in an ultrasonic cleaner powered
through a voltage regulator so we can control the amplitude of ultrasonic waves in the bath and
prevent cavitation. When observed, etching in ultrasonically excited environment removes the
44
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bubbles that adhere to the chip surface and prevent access of new etchant to the structures. The
final results of such etching have clearly significantly improved our fabrication yield, and in
some cases enabled microfabrication of some device structures that were otherwise impossible.
As expected, regulating power is essential as ultrasonic stirring will destroy all membranes when
excessive power is applied. This depends on the individual unit used and its frequency, and must
be adjusted with test etches of dispensable structures.
Another example shows an extreme situation, where opens were made very small and
placed between signal and ground plane of CPWs. This type of structure for designing ultrafast
CPWs with higher characteristic impedance will be discussed in more detail in 5.2.1. A test
structure shown in for these CPWs, however, reveals the necessity o f ultrasonic micromixing
during the hybrid etch.
(a)
(b)
Figure 19. Test structure fo r 120 £2 CPWs with very small opens after (a) hybrid etch, and (b)
ultrasonically enhanced hybrid etch.
3.3.2 TEST STRUCTURES FOR MONITORING THE HYBRID ETCH
As described earlier in Section 3.2.1, the progress of the isotropic etching can be observed
by optical monitoring through the viewport on the etch chamber, or by using electrical etch test
structures as depicted in Figure 13b.
On the other hand, monitoring the progress of the
anisotropic etch as second part of a hybrid etch is not as straightforward. The etch-for-depth
aspect of the second step would require a depth monitoring electrical structure, which is not
45
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available.
Moreover, EDP etching presents a much harsher (and more hazardous to user)
environment for any sort of electrical, optical, etc. monitoring. However, unlike for isotropic
etching where etching pressure and amount of XeF2 in storage chamber can vary the speed of
etching significantly, the speed of anisotropic etching is very consistent, as long as we provide
good temperature control and use fresh EDP for every process. Therefore, it is possible to
achieve the needed depth o f etch-pit by simply monitoring etching time. The significance of the
etching depth for sufficient electromagnetic isolation will be discussed in detail in Section 5.3.
The most important and basic test structure for monitoring the progress and final success
of the hybrid etch for CPWs and thermoelectric power sensors is one based on the actual layout
of the device. As shown in Figure 20, a CPW design which will be described in detail in Section
5.2.2 is made transparent by removing metal in most of the layout such that undercutting etching
can be monitored optically. Moreover, a number of polysilicon lines are drawn which mark the
limits of the etch, such that the isotropic etch can be stopped on time before going to the
anisotropic part.
substrat
Etched pit
Etched pit
& ZZ£Lza& l
substrate
Polysilicon edge marker
Figure 20. Optical etching test structure fo r monitoring progress and success o f hybrid etch.
Design of such structures is very straightforward and does not require any in-depth
explanation. One should note in the example of Figure 20 that etch control of within 1-2 /urn is
possible to achieve by optically monitoring such a test structure during the isotropic etch. This
exceptional example comes from the substrate on which most of the devices characterized in
Chapter 5 were fabricated.
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33.2.1 MONITORING DEPTH OF HYBRID ETCH PIT
In this section, we introduce the simple method for measuring actual depth of etched pit
after a completed hybrid etch. This is mostly necessary to verify whether the post-process was
successful, but can also be inserted as part of the post-process, since etching can be continued
after such verification.
Figure 21. Use o f optical etching test structure fo r determination o f depth o f etch pit.
Shown in Figure 21 is a test structure from a chip which included the fully-suspended
CPWs, and thermoelectric power sensors. This is a test structure for visual monitoring of the
post-processing for one type of CPW, which will be described in Section 5.2.1. After 70 minutes
of EDP etching as part of the hybrid etch, at 92 °C, this chip was rinsed thoroughly and inspected
under a microscope. Then, two images were taken, with focus on the top surface of the chip and
the surface of the pit-bottom, as shown in Figure 21. By measuring distances di and d2 in the
images, and recognizing that the {111} walls of the pit have an angle of 54.7° to the top {100}
plane, we compute the depth as following:
(18)
which can be very accurately approximated as:
(19)
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The above final approximation is easy to remember and apply quickly, and is less than 0.4 %
deviant from the correct formula in (18). One must be careful in employing these formulas
directly, without proper reference length which provides the chip to image scale. In our case, we
utilized dc electrical probing pads which are 100 p m on each side, to accurately set this scaling,
such that distances dt and d 2 measured from photographs can be expressed in actual micrometer
dimensions.
Clearly, maximum depth is achieved when ^ is zero, i.e. the (111) planes meet at
a line (or a point for a square shape structure), as in Figure 15b at the very center o f the pit, for
which case h ^ - d i ^2/2.
Figure 22.
Fully-suspended CPW test structure fo r optical verification o f the post-process, and
measurement o f etch pit depth.
Another example is the CPW structure in Figure 22, where the structure of opens is
extended beyond the CPW probing pads to allow visual inspection of the post-processing
success. In that particular structure, the length di is clearly per design for micromachining, i.e. it
is known a priori providing the isotropic etching was stopped at correct time. Then, reference
length measurement is not necessary. For this case, di = 350 pm, d 2 = 185 pm, and therefore hpu
= 115 pm.
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3.4 FABRICATED SENSORS
The above CMOS fabrication and post-processing methodology resulted in a relatively
high yield for a research environment. This came after numerous trials with variations of above
methodology, and particularly after the ultrasonic enhancement was added to the anisotropic
etch. While the post-processing could certainly still be improved and perhaps other etchants
could be used, the described methodology allowed us to fabricate numerous devices for
characterization. One such representative Sensor 1 device is shown in the microphotograph of
Figure 23.
CPW RF Input
dc Output Pads
Figure 23. Microphotograph o f the indirectly-heated thermocouple microwave power sensor by CMOS
MEMSfabrication - Sensor 1.
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The directly-heated device is significantly larger due to the integrated dc blocking capacitor, and
therefore only the termination section and the beginning of the capacitor is shown in the
microphotograph of Figure 24.
rf Tenninations/Thermocouples
Open Areas
Figure 24. Microphotograph o f the directly-heated thermocouple microwave power sensor by CMOS
MEMSfabrication - Sensor 2.
3.5 CONCLUSIONS
We have described a novel post-processing etching technique for fabricating large
suspended microstructures in CMOS technology. Glass openings exposed the silicon for front­
side etching and require no additional mask. The suspended microstructures were realized by a
combination of isotropic etching with gas-phase XeF2 and anisotropic etching in EDP. The
advantages and disadvantages of these etchants with respect to selectivity, reproducibility, and
process compatibility were described in detail. Further, a unique approach to hybrid etching was
introduced where ultrasonic micromixing is used to significantly improve the yield of such post­
processing methodology.
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Simple test structures were introduced for monitoring the progress and final success of
the post-processing, based on optical and electrical measurements and inspection. The test
structures are very simple to design as they are entirely based on the layout of the actual
structures being fabricated.
Implementation in CMOS technology allows the integration of
electronics for signal processing and communications on the same chip as the suspended
microstructures.
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CHAPTER 4 - CHARACTERIZATION OF COPLANAR
WAVEGUIDES ON CMOS-GRADE SILICON
SUBSTRATE
Historically, integration of microwave components in CMOS technology has not been
possible due to the excessive electromagnetic losses in the silicon substrate. The integration of
passive components by micromachining the silicon substrate in this Dissertation is motivated by
this assumption. Therefore, accurate characterization of microwave propagation was needed to
verify and model the assumption, and to show clearly that without the novel microfabricarion,
which includes silicon micromachining, implementation of the microwave power sensors would
not be possible.
Accurate characterization of microwave propagation on transmission lines in CMOS
integrated circuits was traditionally unessential because the circuits operated at relatively low
frequencies and could be modeled sufficiently accurately by simple lumped element RC models.
Today, the demand for integration of wireless communication circuits on CMOS chips prompts
the need for more accurate characterization and modeling of microwave propagation properties
of CMOS-grade silicon substrates.
This chapter reports on the characterization of the microwave properties of coplanar
waveguides (CPW’s) on silicon substrates with resistivities in the range of 1 fl-cm, fabricated by
commercial CMOS foundries through MOSIS [35]. In Section 4.3, we describe accurate onwafer measurement and calibration techniques to acquire frequency-dependent propagation
constant and characteristic impedance data for our coplanar waveguides (CPWs). Using these
measured data, we calculated RLGC parameters as functions of frequency.
Further, in Section 4.5, we describe a general quasi-TEM model based on the physical
parameters of the mentioned CMOS process to account for the two loss mechanisms on either
side of the silicon relaxation frequency, and then compare this model to the measured RLGC
parameters. The result is a model that circuit designers can use to estimate loss and phase factors
as well as the characteristic impedance of their CMOS transmission lines given the starting
process parameters.
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4.1 COPLANAR WAVEGUIDES ON SI SUBSTRATE
Planar microwave transmission lines on lossy substrates such as silicon can exhibit a
wide range of propagation characteristics in different frequency regimes and with different
resistivities.
Although transmission lines on silicon substrates have been explored both
experimentally and theoretically [29]-[34], in most cases the lines were fabricated on highresistivity silicon and by special processes. With constantly increasing frequencies in digital
circuits, down-scaling of semiconductor processes, and increasing demand for integrated RF
components in CMOS, it is necessary to characterize propagation behavior on lossy silicon
substrates with resistivities in the range of 1 Q-cm.
Many of the proposed models for integrated circuit transmission lines refer to the
different “modes” or mechanisms of propagation. The “modes” were identified by Hasegawa et
al [30], using the values of loss tangent (o/coe). They identified a “slow-wave” mechanism for
large losses when the signal frequency was less than the Si relaxation frequency, and a “quasiTEM” mechanism for low losses when the frequency exceeded the Si relaxation frequency.
Kwon et al [34] showed the so-called slow-wave “mode” to be a quasi-TEM waveguide mode by
adequately describing their transmission lines with a single distributed resistance, inductance,
conductance, and capacitance (RLGC) model.
Williams and Marks also examined lossy
transmission lines in their general theory of waveguides [25]. Their direct expressions for RLGC
values, based on the quasi-TEM fields, show the distributed, frequency-dependent, circuit
parameters to be an exact description of a quasi-TEM transmission line. They also examined
phase velocity on transmission lines and showed it to increase in general for increasing losses.
While the current literature describes the high-loss regime as a slow-wave “mode”, distinct from
quasi-TEM propagation, it appears that transmission lines on lossy silicon actually support a true
quasi-TEM waveguide mode over very broad bandwidths, and can be adequately described with
an appropriate RLGC model for certain ranges of substrate resistivity.
S3
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(a)
Probing pad
M e tal
Ohmic contact
(b)
SiOo
ISi substrate
Aluminum
Figure 25. CPW test structure (a) GSG (Ground-Signal-Ground) layout and (b) cross-sectional view with
pertinent dimensions.
In previous work [9], we characterized the propagation constant for sample CPWs on Si
substrate, and introduced a simple and approximate model for their behavior. This model was
based on conformal mapping which neglected the presence of oxide encapsulation, and metal
thickness. Also, with only measured propagation constant, the four model RLGC parameters
54
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could not be verified independently.
In this Chapter, the previous work was significantly
advanced in the following ways: we measured and modeled the propagation constant and
characteristic impedance of many CPW sets on CMOS-grade Si substrates, utilizing accurate
recently introduced on-wafer measurements techniques.
Moreover, the improved model in
Section 4.5 accounts for glass encapsulation and metal thickness, and each parameter is
independently verified by measured counterparts.
The model and measurements presented in subsequent sections help predict behavior of
the coplanar structures on lossy substrate, and can also aid in the analysis of VLSI interconnects.
Most importantly in this work, however, the analysis is used in the design and modeling of the
fully-suspended CPWs in Chapter 5, which are an integral part of the overall microwave sensors.
4.2 TEST SET DESIGN
For the experimental characterization, five test sets of CPWs with different dimensions
were fabricated through three different standard CMOS processes available through the MOSIS
service. The CMOS fabrication was described in Section 3.1. The test sets differ in transverse
line dimensions and in substrate resistivities to give a wider range of data for a better
understanding of the propagation characteristics. The line dimensions and other parameters, as
outlined in Figure 25b, are listed in Table 1 for all the sets.
Delay line 2
I
[
n
n
c
r
r
c
-
n
n
Thru
e
r
r
c
-
n
n
r
c
-
n
r
-
n
n
c
r
f
c
-
n
r
-
r
i
r
r
c
-
r
c
-
c
n
r
c
-
i
r
-
r
r
n
r
c
r
n
-
n
Delay line 1
c:
t
-
r
n
-
a
n
r
n
'
Short
-4.0 mm
Figure 26. Thru-Reflect-Line CPW test set fo r de-embedding measurements o f propagation constant and
characteristic impedance per unit length. Thru length is ~ 0.8 mm, and Une2 length is ~ 4 mm.
For the necessary de-embedding of the measured 5-parameters, we designed complete sets of
transmission line standards, as shown in the layout snapshot of Figure 26. The thru standard sets
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the resulting de-embedding reference plane at its middle, such that any subsequently measured
structures, which include this section before the DUT, can be very accurately de-embedded. The
procedure will be described in detail in the next section.
Measurements were made on five separate calibration sets located on three distinct chips.
These sets varied in metal thickness, conductivity, and geometry. The longest delay line (delay
line 2 in Figure 26) for all of the layouts was approximately 4.0 mm in length, while the through
lines were close to 0.8 mm long. Probe placement on the contact pads had to be performed with
micron scale precision in order to ensure accurate measurements.
Due to standard CMOS processing, the center conductor is fully encapsulated in layers of
glass, while the ground planes make ohmic contacts to the underlying substrate as illustrated in
Figure 25.
This is done to provide distributed ground equalization and prevent parasitic
propagating modes.
Set
1
2
3
4
5
a [pm] b[pm] c[pm]
24
30
130
60
68
300
68
60
300
60
68
300
69
60.9
364.2
Metal
ml
ml
m2
m1m2
m1m2
t [//m] hulpm] Iil [// m] pa [Ocm] NaHO'W*] Process
0.7168
Orbit 2.0 pm
0.6
1.65
1Z5
1.45
0.6117
0.6
1.65
11.5
Orbit 2.0 pm
1.45
0.6117
1.15
1
11.5
Z1
Orbit 2.0 pm
0.6117
1.75
1
11.5
1.45
Orbit 2.0 pm
HP 1.2 pm
1.35
1.4
0.434
3.885
1.03
Table /. Dimensions and parameters o f experimental CPW sets.
The waveguides connect with electrical probing pads in th e . GSG (Ground-SignalGround) configuration with 100 pm pitch, and in some cases, 150 pm . The pads consist of both
first- and second-layer metal connected by many vias. As shown in
Table 1, test sets 1 through 4 were fabricated in a 2 pm CMOS n-well process; test set 5 was
fabricated in a 1.2 pm n-well process. For accurate measurement characterization, all of the
necessary TRL components were designed in the same transverse geometry: lines of different
lengths and reflection standards (short and/or open).
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4.3 MICROWAVE MEASUREMENT SETUP AND PROCEDURE
We characterized the CMOS transmission lines at frequencies from 100 MHz to 40 GHz
using a commercial automatic network analyzer, a microwave probing station, and the multiline
through-reflect-line (TRL) calibration technique [22],[23].
We measured the propagation
constant (attenuation and phase factors of the lines), and by implementing the calibration
comparison method [24], determined the characteristic impedance of the lines. Finally, knowing
the propagation constant and characteristic impedance of the lines, we calculated the total
resistance R, inductance L, capacitance C, and conductance G per unit length of the transmission
lines [25].
The multiline TRL calibration method provides an exact solution for the propagation
constant accounting for all the transmission and reflection parameters (S,y) from two or more
lines of varying lengths, hi contrast to other propagation constant measurement techniques,
multiline does not make any port-match assumptions. As shown in previous work, it provides
accurate frequency-dependent propagation constants even when the characteristic impedance of
the lines differs significantly from the reference impedance of the system [36].
To determine the propagation constant in this study of CMOS transmission lines, we
measured two lines of different lengths. Then, using the NIST MultiCal® software with an
estimate of the effective dielectric constant, we solved for the propagation constant according to
the multiline TRL equations [23]. The propagation constant is determined irrespective of the
system calibration, so the accuracy is limited only by the random errors encountered in measuring
the two lines and by the accuracy of the length difference. For 5-parameter measurements with
our system, the magnitude of the worst case repeatability bound is typically less than 0.01 over
the frequency range studied here [24]. The propagation constant data are shown in Figure 27 as
the attenuation factor (a ) and normalized phase factor (jSc/icu).
We made use of the calibration comparison technique [24] to determine the characteristic
impedance of our lines. This method was chosen over conventional techniques since it has been
shown to generate more accurate results over broad bandwidths [24]. By measuring the Sparameters of our transmission lines with respect to a reference multiline calibration (GaAs CPW
referenced to the probe-tips), we could apply this method to directly determine the characteristic
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impedance of our unknown lines.
Finally, with the propagation constant and characteristic
impedance known, we could calculate the frequency-dependent equivalent circuit parameters per
unit length of line (R, L, C, and G) by
jcoC+G = ^ -
(20)
j(oL + R = y -Z 0,
(21)
and
where y is the complex propagation constant, and Z q the complex characteristic impedance of the
CPW.
While the propagation constant measurements are limited only by system repeatability,
the RLGC parameters are limited to two sources of uncertainty. The first is the valid range of
calibration based on the multiline TRL standards. The transmission lines were designed to have
a minimum error at 20 GHz, with increasing errors at low frequencies due to the short line
length, and increasing errors around 40 GHz due to the half wavelength approaching that of the
differences in line length [23]. From the measurements, we determined the range of valid
calibration to extend from 3 GHz to 40 GHz. For frequencies decreasing below 3 GHz, the data
will be susceptible to increasing calibration errors.
The lack of probe pad compensation is the second major source of uncertainty in the
RLGC measurements. Thecalibration comparison methodof determining Zq requires the pads
for the test lines to exactly match that of the reference calibration structures, orto be
symmetrical. If not, a separate measurement of the pads must be made to compensate for the
differences.
In the test chips, we did not have access to an isolated pad, and could not
compensate our Zo measurements accordingly [26].
Consequently, in comparing models to
measurement, we consider the probe pad contribution as uncertainty in the data. This source
exceeds the calibration and repeatability limits over our frequency range.
58
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4.4 MEASUREMENTS O F CPW s ON CMOS-GRADE SI
SUBSTRATE
The measurements of attenuation for each line are shown in Figure 27a. As seen in the
figure, the attenuation becomes very high for frequencies above 10 GHz, and exceeds 20 dB/cm
at 20 GHz.
This is mainly due to the currents in the relatively highly conductive silicon
substrate, as will be shown in the following analysis. Also, by referring to Table 1, we observed
that CPWs on substrate of higher conductivity exhibited significantly higher attenuation, such as
for data set #5.
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70
Data S e t 1
Data S e t 2
Data S e t 3
Data S e t 4
Data S e t 5
as
3
§
«E
15
20
25
Frequency [GHz]
(a)
D a ta S e t 1
0
5
10
15
20
25
30
Frequency [GHz]
(b)
Figure 27. Measured complex propagation constant fo r data sets listed in Table I: (a) attenuation, and
(b) normalized phase factor.
Figure 28 shows the real and imaginary parts of the measured complex characteristic impedance
for set 2, which allows us to compute the RLGC parameters from equations (20) and (21) and
verify the model given in the following section.
60
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30
251
20
w
E
x:
O
-10
-1 5
-20
0
5
10
20
15
25
30
35
40
Frequency [GHz]
Figure 28. Measured complex characteristic impedance fo r data set 2.
4.5 QUASI-TEM MODEL FOR CPW s IN CMOS
At higher frequencies, modeling of transmission lines in VLSI circuits in terms of the
simple RC model is insufficient. To account for the propagation effects in the CPW structures,
we use a physical equivalent circuit of a differential line length dz, which models the effects of
the transverse electric and magnetic fields.
From the equivalent circuit we obtain the four
transmission line components of a corresponding RLCG transmission line model.
The
components are expressed as real and imaginary parts of the series impedance per unit length,
and shunt admittance per unit length of the transmission line. Such lumped element models have
been widely used in transmission line design and theory, and although approximate, are simple
and computationally efficient. However, they are only accurate for quasi-TEM mode analysis.
The main assumption of the analysis is that the transverse fields carry the majority of the
electromagnetic energy. This assumption is valid as long as the transverse CPW dimensions are
much smaller than the shortest wavelength of the applied signals, and the losses are not
excessive. In our experimental test sets, the largest transverse dimension is nearly 400 pm,
satisfying the former criteria well throughout the experimental frequency range.
61
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Figure 29. Quasi-TEM equivalent circuit (a) theoretical model (Model A), and (b) empirical model
(Model B).
To analyze the CPW of Figure 25, we developed the equivalent circuits in Figure 29. The
circuit in Figure 29a includes elements from the model of Shibata and Sano [32], which was
derived from a full-wave computer analysis of a similar metal-insulator-semiconductor (MIS)
structure. The results of the full-wave analysis in [32] show that two different regimes of
propagation take place, thereby leading to the model as shown in Figure 29a, where the
relaxation between two modes is taken into account in terms of circuit elements Cs, and Gs/.
Capacitors Cssi and Csg represent the signal-to-silicon substrate and signal-to-ground plane
capacitances, respectively. The conductance Gst is due to transverse currents induced in the
silicon substrate by the electric field, while Cst similarly represents transverse displacement
currents. Both Cs, and Gs, are given by the electrical energy stored in the substrate, and can be
combined in a complex element Is, by introducing complex permittivity, or complex
conductivity, of the substrate.
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4.5.1 SERIES IMPEDANCE EQUIVALENT CIRCUIT
The effects of the longitudinal currents and transverse magnetic field are modeled in
terms of components Rs and L. Elements L and Rs are the inductance and resistance of the
aluminum conductors, respectively.
However, the longitudinal losses cannot be adequately
described by considering only the conductor losses. We used an additional resistance, /?/, in series
with Rs to represent longitudinal current losses in the silicon beneath the signal strip.
The shunt capacitors Cs» Cssi, and Csg model the transition from the slow-wave “mode”
at lower frequencies to the dielectric quasi-TEM “mode” at higher microwave frequencies.
Namely, in the low frequency limit, the conductance G$i effectively shunts Cs, and the total
capacitance is mainly the glass capacitance Css/. In the limit of frequency equal to infinity, the
capacitances make up the total dielectric quasi-TEM limit capacitance Cj.
The CPW cross-section with multilayer dielectrics as shown in Figure 25 can be analyzed
by conformal mapping [37],[15].
This will be discussed in detail in Section 4.5.2, for the
computation of equivalent shunt admittance circuit.
However, a simple conformal mapping
application is required for the computation of the series impedance circuit elements as well.
Namely, for a loss-less transmission line with perfect conductors and no magnetic materials, the
equivalent air-capacitance is employed to obtain per-unit-length inductance L~, with the same
dimensions:
where c is the velocity of light. This inductance is subsequently adjusted to account for currents
within the conductor due to its finite conductivity, and is in general also a function of induced
currents in the substrate. With no surrounding dielectrics, the conductor structure of the CPW
air-line is symmetrical across both axes around the origin in Figure 25. Conformal mapping is
applied to transform the quarter-symmetry structure as shown in Figure 30a into easily computed
parallel plate capacitance (with no fringing field) in Figure 30b. For the zero-thickness CPW,
this requires two conformal mappings, due to the finite extent of the ground planes [15]. As a
result, we obtain a geometry factor (F=W/L in Figure 30b) from which we can compute the
capacitance per unit length Co of an equivalent air-filled line.
63
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(b)
Figure 30. Schematic depiction o f a quarter-symmetry part o f the air-line CPW, (a) actual structure, (b)
structure conformally mapped into a parallel plate capacitor.
For the zero-thickness CPW structure with finite-extent ground planes
the
geometry factor is expressed in terms of a ratio of elliptic integrals, as derived by Veyres and
Hanna [15]:
K{k')
K{k)
„
(23)
where K(k) is the complete elliptic integral of the first kind, and k is the argument of the integral,
expressed in terms of the CPW dimensions as:
b
(24)
Vc - a
k' = -Jl~k2
The accuracy of the computation of capacitance therefore depends on the validity of the
approximation to the solution of the ratio of the elliptic integrals of first order. The ratio of
elliptic integrals in (23) can be obtained by computation, or approximated by the following
expressions [39]:
64
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2 .0
K {k ')_
K(k)
In
k
0.707 < A: <1.0
vr+r+V4.o-ifc
(25)
^ |^ + k - ^ 4 .0 -k
7
-Jl+ k'+ tj4 .0 -k
1
•In 22.0-K
VlTF-V4FF
\
0.0 < k <0.707
/
The capacitance of the structure in Figure 30b is simply Feo. Since the complete CPW
air-line contains four such symmetric sections, the capacitance for zero-thickness is Co.to=4Feo.
This calculation is insufficient to reach Co, due to the finite-thickness of our CPWs. For CPWs
with finite-thickness metals and finite-extent ground planes, even in the case of air dielectric,
three sequential conformal transformations would be required to obtain simple expressions for
capacitance [14],[38]. In general, it is very difficult to obtain closed form expressions for all
three stages of the transformation, and various approximations are often employed [38]. In this
work, we use a simple and sufficient approximation for the finite-thickness metal contribution to
the capacitance by adding the capacitance between the metal sidewalls to the zero-thickness
capacitance. Namely, we add the parallel-plate capacitance between points 2,5 and 3,6 in Figure
30a to the above expression for Co,to- This gives better results than simply assuming a zero­
thickness case, and does not require additional computation. Hence, the capacitance per unit
length Co of an equivalent air-filled transmission line can be found from the following
expression:
C0 —4 • £0
F+
{b-a)_
(26)
While we found the above approximate expressions of (23)-(26) sufficiently accurate for
our application, there are other proposed expressions for CPWs with finite-extent ground planes
available in the literature [40],[41]. Also, simpler expressions are often found which use only
two parameters, a and b [34],[14]. In those cases, infinite ground planes on both sides are
assumed, which is often an adequate assumption. In the case of our experimental CPWs, the
ground planes extend for a limited distance. Therefore, all three parameters, a, b, and c, are
included in the computation of F.
The presented structures have very small dimensions and have very thin conducting layers
(less than 1.5 pm thickness, t, therefore, the sheet resistance of the metal cannot be neglected.
65
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The series resistance in the metal conductor is normally not a function of frequency, and the
value could actually be looked up from MOSIS parameters which are provided after fabrication
(included in Table 1). However, as frequency increases, the skin depth in the metal becomes less
than the metal thickness, so the resistance becomes a function o f frequency. In order to find the
frequency dependence of Rs, we first calculated the internal impedance for each conductor by
using the PEM method introduced in [16]:
Zi
= 0 - + j ) -Ktface ‘ S-GOth
(l + y ) g A
8 Al
(27)
where RSUrface is the surface resistance of the aluminum conductors (R Iluface = 1/(0^ 8M) ),
parameter A is the cross-sectional area of the conductors (for center conductor A = a t M, and
each ground conductor A = (c —b) tAl/ 2 ), 8Al is the skin depth in the aluminum conductor
defined as:
K == J
■
(28)
The geometrical factor g in (27) is shown in [16] to be the derivative of external inductance with
respect to the incremental recession in conductor walls as a function of frequency. Namely, due
to the finite conductivity of the metal, the inductance and resistance contribution from the
currents within the conductors is represented by the factor g as follows. At each frequency, the
skin depth is computed by Equation (28), and Equations (22)-(26) are applied on the resulting
equivalent, perfectly conducting CPW, with the dimensions of all three conductors recessed by
8a/2 from each side. As a result we obtain frequency dependent external inductance Lg. Lastly,
we compute the factor g as:
(29)
n d8
Then Rs is given by the real part of the total impedance in the metal conductors
^ “ S f z .^ + iz ^
V
A
/
while L is given by the sum of L°° and the imaginary part of the same impedance
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(30)
L = L „+ 3 (Z
'i.ground
(31)
In order to take into account the longitudinal losses in the substrate Kwon et al. [34] proposed a
parallel resistor Ri which is calculated in terms of the skin depth inside the substrate, linewidths,
and substrate resistivity. Seguinot et al. [28] used a series resistor in their model to account for
the same losses. But for the skin effect to become significant, the conductivity of the substrate
must be much higher than 1 S/cm for the substrate thicknesses from the commercial processes.
On the other hand, the measurements indicate that the resistance in the longitudinal circuit
increases with larger slope than Rs does (Figure 33a). The skin-effect resistors both for conductor
and substrate give J f -type increase with frequency [38]. In this work, we added a series
resistor Ri which changes linearly with frequency and gives almost the same slope as the
measurement. The empirical Rt is given in Eq. (32) and the resulting circuit is illustrated in
Figure 29b.
(32)
This expression approximately corresponds to two-sided skin effect in the substrate. Therefore,
the total impedance per unit length of the longitudinal circuit is given by:
Z = R ,+ R ,+ jw L .
(33)
Capacitance Css/ is the capacitance found between the center conductor and the
underlying substrate which is simply found from the linewidth a and the oxide permittivity.
However, due to the relatively small widths of the lines, the effects of the fringing fields should
not be neglected. To obtain a more accurate value for the capacitance Css/, we computed it
numerically by using commercial finite-element two-dimensional electrostatic simulations. From
numerically obtained results for Css/, using several linewidths a, we arrived at an approximate
equation which accounts for the extra capacitance from the conductor edges. Capacitance Css/ is
therefore found from:
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where the first part of the equation defines the capacitance when fringing effects are neglected.
The relation in Eq. (34) is only approximate; methods for more accurately computing the fringing
effects can be found in [27].
4.5.2 SHUNT ADMITTANCE EQUIVALENT CIRCUIT
4.5.2.1 MULTILAYER CAPACITANCE DETERMINATION BY CONFORMAL
MAPPING
The transverse field effects in the substrate are approximated as a parallel GSi and CSi
equivalent circuit. The field distribution in the substrate and the total electric energy stored are
approximated by the conformal mapping of the multilayer dielectric structure in Figure 25b. It
was shown by Veyres and Hanna [15] that the geometrical factor in (23) can be defined in a more
general way as a function of the thickness of the nearest dielectric layer. Namely, to compute
capacitance of a zero-thickness CPW with dielectrics, they firstly found a simple expression for a
hypothetical structure with a single dielectric with thickness h and no further dielectric extending
from it, as depicted in Figure 31a. The geometrical factor for such a structure is given in [15] as:
F(h) = — ^ (/t)),
K{k(h))
(35)
where the arguments are expressed in terms of the dimensions
c{h) lb2( f t ) - a 2(h)
=T
rrfi/y c2(h)
2~/»\ —a 2(h) •
b(h)
<36>
Here a(h), b(h), c(h) are the transformed dimensions and the transformation defined as
x(h) = sinh(^-^) x —a ,b ,c.
(37)
2h
The transformation in (37) achieves the conformal mapping from the structure in Figure 31a with
a finite thickness dielectric, to a structure with the dielectric filling the entire half-space, which
can be easily computed by the ratio of elliptic integrals as done previously. As h approaches
infinity, the transformation in (37) becomes an identity transformation, such that each parameter
a,b, and c remains unchanged and same relations as in (23)-(25) apply.
68
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(a)
(b)
Figure 31. Simplified crosssection o f zero-thickness CPW, (a) fictitious finite-dielectric structure fo r
computing F(h), (b) combining two fictitious structures to obtain multilayer solution, and (c)
superposition o f two such finite-dielectric structures.
The multilayer structures can be expressed as a superposition of the hypothetical of
Figure 31a. For example, the structure in Figure 31c can be expressed as a superposition of two
layers depicted in Figure 31b: one with thickness
and dielectric constant £,, and one with hi
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and (£ ,-£ ,), respectively. Then using these hypothetical layers the capacitance of the real
structure is calculated. In our case, the total half-plane capacitance for the structure in Figure
31(b) is
Ctar-ptm, = £o k
F(h2) + (el - e 2) F { h ,)l
(38)
or
Chalf-plane ~ ^ 0
[e, •(F(A2)-F (A ,))+ e , -F(A,)].
(39)
A3J..2 EXPRESSIONS FOR SHUNT COMPONENTS
Using the partial-capacitance approach and conformal mapping method, as described
above, we find the geometry factor Fsi.
Ff i = F H - F ( A ) .
(40)
The transverse drift current flow, represented by conductance Gs„ is approximated by:
Gy, = 2 • a Si • FSi.
(41)
Because the analysis must be valid at frequencies where the substrate acts as a dielectric, i.e.,
where the assumption o Si » ( o e Si is not valid, the transverse capacitance Csi is included in the
model. The capacitance is also approximated from the geometric factor F as:
CJ(- = 2 •£Si - FSi.
Capacitance betweenthe
(42)
signalline and the ground lines in the slow-wave limit,Csc,should be
determined such that the totalcapacitance in the limit of frequency equal to infinitycorresponds
to Q :
c , - c * + t-'ss
*;* +W
fr / ■
(43)
The capacitance in the high-frequency limit for a coplanar waveguide is commonly found from
the air capacitance Co and the high-frequency effective dielectric constant:
C ,= C i- S „ = C i~ f e ^ .
(44)
This capacitance, however, can be found much more accurately by again referring to the method
described in4.5.2.1, and computing the total capacitance of a uniformtransmission
superposition of partialcapacitances due to each dielectric layer. Because
of thedifferent
structures above and below the CPW, the total capacitance C</can be expressed as:
70
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line as a
^up p er _ half + ^Cower _ half
+ ^6a
p p t
= *.{2[(*ot - O ' rf e ) + ' r (“ )l}+eo{2fe<,x-% )-Ffa)+ei,F(~)]}+ 4- • ■« - .
b —a
(45)
In (45), Q a corresponds to the capacitance between the vertical wails of conductors. The
propagation constant measurements showed a slower phase velocity than is predicted by the
circuit. This can be seen in the simulation results in Figure 32 and Figure 33. To account for this
in the empirical model of Figure 29b, we changed Csg to
C'SG=Cd .
(46)
From the shunt circuit elements, the total shunt admittance per unit length is found from:
Y = -----------------—----------- H-------------------j •to •
j ■co • Cfi + Gs
The complex propagation constant y
+j ( 0 - C sc.
(47)
and the complex characteristic impedance Zq are
determined from Z and Y :
y = a + j-P = J Z Y
(48)
z ^ z i+ j- z ; ^ .
(49)
4.6 COMPARISON OF MODEL AND MEASUREMENT FOR CPWs
ON SILICON SUBSTRATE
We have simulated our transmission line using the models from the previous sections for
the given line dimensions and calculated the complex propagation constant and complex
characteristic impedance at interval frequencies from 0.1 GHz to 40 GHz. For the simulations,
values for line dimensions and process parameters from Table 1 were used. The results of the
calculations of the complex propagation constants for data set 2 are shown in Figure 32 in terms
of the loss per centimeter length and normalized phase factor, respectively.
The attenuation measurements reflect the change from slow-wave propagation to
dielectric quasi-TEM propagation. The attenuation rises nearly linearly with increasing
frequency. The different regions of propagation are seen with different slopes. The same trend is
found in the models, where the transition was imposed by properly selecting shunt circuit
71
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capacitances. The model A (Figure 29a) exhibits excellent agreement with measurement at low
frequencies but in the quasi-TEM dielectric “mode” it becomes inadequate. The improved
empirical model (Figure 29b) shows excellent agreement at high frequencies.
50
45
Model A
M easurem ent
Model B
40
£
o
35
§L
30
§
25
"S
3
20
a>
% 15
0
5
10
20
15
25
30
35
40
Frequency [GHz]
(a)
60
M odel A
M easurem ent
M odel B
50
40
O<Dl
(0
<D
30
CL
20
10
0
0
5
10
20
15
25
30
35
40
Frequency [GHz]
(b)
Figure 32. Comparison o f measured and modeled (a) attenuation and (b) normalized phase factor fo r
data set 2.
The transition from the slow-wave “mode” to the dielectric quasi-TEM “mode” is more
evident in the effective permittivity measurements and model results. The effective permittivity
is extremely high at the lower end of frequencies, where very low phase velocities were expected
72
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and measured. At frequencies above 20 GHz, the permittivity became nearly level, with a phase
velocity expected from a mixed dielectric of silicon and air. But the comparison of phase
velocities in Figure 32b shows a clear difference at high frequencies. The measurements indicate
more capacitance than the models do. In the empirical model we increased Csc to Cd to meet the
additional capacitance requirement. Also, the transition region between the slow-wave “mode”
and the quasi-TEM dielectric “mode” is much wider in the measurement.
M easured
M odel A
Model B
E 100
,0
X
c
TJ
C
(0
E
.o
CO
E
cc
10
1
Frequency [GHz]
(a)
100
M easured
Model A
Model B
E
o
10
CO
O
“O
c
(0
oE
1
u.
Q.
o
0.1
0.01
10
1
Frequency [GHz]
(b)
Figure 33. Comparison o f measured and modeled RLGC parameters fo r data set 2.
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Figure 33 compares the RLGC parameters computed from the equivalent circuit models
to those extracted from Zq and /measurements. Though Model A is better at predicting G, and is
not significantly different than Model B in predicting L, the empirical model, Model B, is
significantly better at predicting the measured R and C values. For the particular test set under
consideration (test set #2), Model B predicts the frequency-dependent transmission line
parameters within the measurement uncertainty limits from 1 to 18 GHz, and remains close all
the way to 40 GHz. Model A (primarily in R values) exceeds the measurement uncertainty limit
for frequencies greater than 5 GHz.
4.7 DISCUSSION
Two deviations from the theoretical expectations were observed. The change of the
attenuation and the phase velocity above 20 GHz differs significantly from the previous
theoretical expectations [32],[34]. The observed linear increase of attenuation in dB/cm with
frequency cannot be modeled using a skin effect resistor in series in the longitudinal circuit
alone. On the other hand, the physical nature of the problem requires that the longitudinal losses
in the substrate be included in series in the longitudinal circuit. We used an empirical resistance
Ri which roughly corresponds to two dimensional skin effect independent from the geometry of
the CPW.
Another important result is that the capacitance in the transverse circuit of Model A did
not fully account for the measured propagation constant of the lines. The additional capacitance
in Model B provided the necessary correction while improving the agreement with measured R
and C data. However, the additional capacitance required here may indicate a missing delay
element in the longitudinal model, such as an inductive term related to the induced currents in the
semiconductor. At present, such a term could not be determined in closed form.
A result that is particularly interesting due to CMOS fabrication is the large difference in
attenuation among the three data sets #2, #3, and #4. All three of those CPW designs have the
same transverse (CAD layout) dimensions, but were designed using different combinations of the
two metal layers available through the CMOS process. Firstly, as expected for data sets #2 and
#4, the attenuation data is almost the same, with a slightly larger attenuation for data set #2. This
is due to the thicker conductors used in data set #2, which are made by combining first- and
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second-layer metals. However, data set #3 has the lowest attenuation of all five sets. This is also
expected, since in this case only the second-layer metal was used which is higher above the
silicon substrate, as shown by the largest parameter
in Table 1. This again shows that the
substrate losses dominate our transmission lines, and that the propagation characteristics for
CPWs in CMOS are largely a function of the type and thickness of dielectric in the process.
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CHAPTER 5 - DESIGN OF FULLY-SUSPENDED
COPLANAR WAVEGUIDES
The detailed characterization of CPW propagation on CMOS-grade silicon in the
previous chapter points out the key impediments in implementing microwave devices in standard
CMOS.
Namely, the very high attenuation and undesirably high dispersion due to the
longitudinal and transverse current in the substrate render the technology unusable for microwave
applications. After the removal of the substrate beneath the CPWs as described in Chapter 3,
however, we achieve significantly improved fully-suspended coplanar waveguides in CMOS.
In this Chapter, the design of fully-suspended CPWs, which are the foundation of the
sensors’ microwave performance, is explained in detail.
The design is based on analytical
equations that predict characteristic impedance and propagation constant, as well as on
micromachining constraints related to the post-processing details given in Chapter 3. The fullysuspended coplanar waveguides for CMOS power sensor application were designed to operate in
quasi-TEM mode, with 50 Q characteristic impedance.
Section 5.1 describes the design
procedure based on quasi-static field analysis as previously used in Section 4.5, and in Section
5.2 based on micromachining considerations.
The analysis of this chapter is verified by
numerical computation, which includes new electrostatic Green’s functions for the glassencapsulated CPWs. A rule of thumb is also given which allows us to estimate the necessary
etch pit depth from the basic CPW dimensions.
Several designs were considered, as they evolved in terms of better electromagnetic and
mechanical properties. Measurements of propagation constant, characteristic impedance, and
other related parameters are reported in Section 5.4, showing the significant improvements over
the CPWs before etching, as well as the overall satisfactory performance for implementation of
microwave power sensors.
5.1 DESIGN FOR 50 Q CHARACTERISTIC IMPEDANCE
Simplified diagram of the fully-suspended CMOS CPW layout is shown in Figure 34,
showing the three coplanar waveguide strips in GSG-configuration (ground-signal-ground), the
electrical probing pads, and the open areas which are necessary for micromachining of fabricated
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ICs as described in Chapter 3. The main difference from the structure discussed in Chapter 4 is
the removed substrate beneath the CPW as depicted in Figure 35.
The design procedure
therefore uses an approximate electromagnetic model and an approximate etch model to obtain
design dimensions a, b, and c, as well as open area placement, for the CPW as shown in Figure
35.
■ ■ ■ Metal 1 (Al)
Metal2 (Al)
■ 1 H I Probing pad
H H H Polysilicon
Open area
Ohmic contact
Figure 34. CAD layoutfo r the fully suspended CMOS CPW thru element.
IAluminum
ISi substrate
3SiCL
Figure 35. Schematic cross-section o f the fully suspended CMOS CPW.
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The design for desired characteristic impedance follows a very similar analysis as given
previously in this chapter with CPWs on Si substrate.
Namely, through the methods of
conformal mapping and partial capacitance computation, the capacitance for the CPW crosssection of given dimensions is found.
Similarly, the capacitance of the equivalent airline
structure, inductance, as well as other distributed circuit parameters are found. Characteristic
impedance and the propagation constant of a transmission line are related to the equivalent
circuit RLGC parameters as following:
(50)
Y = tJ(R + j-c o -L )(G + j o a - C ) .
(51)
For a given set of dimensions and material parameters, the four per-length transmission lines
components can be computed, from which we therefore attain a nominal characteristic
impedance.
R
L
Figure 36. Quasi-TEM equivalent circuitfo r fully-suspended CMOS CPW.
The quasi-static analysis follows exactly the same procedure as that in Section 4.5, the
only difference being the removal of the lossy silicon substrate. This allows us to neglect both
longitudinal and transverse substrate losses, represented in Figure 29a as resistances Ri and GsiThe main source of remaining losses is the finite conductivity of the metal represented in Figure
36 simply as R.
Also in Figure 36, we include the conductance per unit length G, which
represents losses in the dielectric, and may include losses in silicon if it is not sufficiently etched
away.
In the design stage, however, we neglect this parameter assuming sufficient silicon
removal, and recognizing that losses in the remaining thin glass membrane will be negligible in
comparison with metallic losses in aluminum conductors. This allows us to arrive at simpler
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relations between line dimensions and characteristic impedance which is what we desire for
efficient design.
First, we start by finding the capacitance per unit length of the equivalent air-line
structure with all dielectrics removed. As explained earlier, it is found from a simple and
approximate expression:
(52)
C0 = 4 -e 0
where the factor F(oo) is the general geometry factor as defined in Section 4.5.2.1.
capacitance is used to obtain equivalent perfect conductor, air-line, inductance
This
by Equation
(22). The total capacitance per length for the fully-suspended CPW as shown in Figure 35 is
given by:
c = c upper_haif + c Imoer_haif
^
T
~
'-'ba
(53)
=
- l ) F (A „)+ F (“ )IKeo{2[(«or
b —a
The conductance per unit length is assumed to be due to loss tangent in the encapsulating glass
dielectric (finite conductivity <Jox)»and can be found from:
C = Cupperhalf + Glmer_fuUf + Gfo
/ \/ \
<T«v -t »
= 2(Toj. ■F f c )+ 2 a ox ■F(hL)+ 4 •- f — .
b —a
(54)
however, as mentioned earlier, this parameter was assumed negligible in the design phase. This
is clearly justifiable due to extremely small conductivity values for glass.
The impedance per unit length, consisting of parameters R and L is found more accurately
by employing the PEL method [16], as done previously in Section 4.5.1. In the design for a
particular characteristic impedance in a low-loss CPW, however, this accuracy in modelingis not
needed. Namely, under the low-loss assumption, the inductance per unit length of the CPW can
be assumed equal to that in which perfect conductors are used, as substrate losses are negligible:
i = A , = -c r •VCq-
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(55)
At this point, we simply assume the quasi-TEM relation Zo ~ (UC)l/2 and find such values for a,
b, and c layout parameters such that Zo~ 50 Cl. Computed sets of dimensions are given in Table
2 below for the different MOSIS processes through which the devices were fabricated.
MOSIS
P ro cess
S e t #1, 0 2 .0
S e t #2, 0 2 .0
S e t #3, 0 2 .0
S e t #4, 0 2 .0
S e t #5, 0 2 .0
S et #6, 0 1 .2
S e t #7, A1.2
P ro c e ss param eters
t [pm]
hL [pm]
0.6
1.45
0.6
1.45
0.6
1.45
0.6
1.45
1.1
1.45
0.6
1.2
1.15
0.6
h0 [pm]
1.65
1.65
1.65
1.65
1.65
1.55
1.6
Designed layout dim ensions
c [pm]
b [pm]
a [pm]
145
50
20
135
24
30
180
35
30
394
68
60
394
60
68
300
67.8
60
300
67.8
60
Nominal
Zo [Q]
120
50
50
50
50
50
50
Table 2. Designed layout dimensions fo r fully-suspended CPW sets based on process parameters and
given analysis.
With the dimensions determined by the given procedure, a more accurate model is used to
predict overall performance of such a CPW design, based on all four transmission line
parameters, R, L, C, and G. While the shunt components were already determined in (53) and
(54), the series components are found through the same PEM method described in detail in
Section 4.5.1, by first finding the internal impedance for each metal conductor, Z,. Then, R is
given by the real part of the total impedance in the metal conductors
* = 3*1 Z.
+ |z ;
(56)
while L is given by the sum of L~ and the imaginary part of the same impedance
L —Lq+ 3(Z I%CCTIW
r+ Zigmuiut).
(57)
5.2 DESIGN FOR MICROMACHINING AND CMOS CONSTRAINTS
Previously described procedure for the determination of layout dimensions a, b, and c,
does not complete the design of fully-suspended CPWs. Namely, to achieve the necessary
removal of silicon substrate beneath the CPW using post-processing etching as described in
Chapter 3, the layout of the CPW and other structures must include carefully placed open areas.
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The positioning of the open areas, in terms of distances and alignment with respect to crystal
lattice of the substrate determines the needed length of isotropic undercutting etching, and the
final shape of the etched area.
5.2.1 TYPES OF CPW DESIGNS FOR MICROMACHINING
Many variations of the design were attempted in this work, mostly changing with the
adjustments taking place in the post-processing methodology. A number of different designs will
be presented in this section, all successful in some ways, and in need of improvement in other
ways.
Figure 37. SEM micrograph o f a CPW section o f the first type o f design fo r hybrid micromachining with
opens between signal and ground planes (G=ground, S=signal).
In Figures 28 through 31, the four basic types of layout are shown in the chronological
order of their design. Figure 37 is a scanning electron micrograph of the earliest structure in
which the open areas are placed between the signal conductor and the two ground conductors on
either side. The small spaces between successive opens are silicon dioxide bridges, which
provide the mechanical support for the center conductor. It is because of the very small opens
with respect to undercutting area that this structure was mentioned in Section 3.3.1 where
ultrasonic micromixing is introduced. This particular kind of design has severe limitations in
terms of design for low characteristic impedance (e.g. 50£2) since the introduction of opens
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between signal and ground limits the minimum distance to around 15 pm , which results in very
small capacitance per unit length and therefore high impedance. The actual fabricated structure
of Figure 37 was designed and measured for 120Q characteristic impedance. An advantage of
such a structure on the other hand is extremely low effective dielectric constant, such that the
performance of the structure approaches that of an equivalent air-line [10].
Figure 38. Microphotograph o f a CPW section o f the second type o f design fo r hybrid micromachining
with opens on either side o f CPW (G=ground, S=signal).
Second type of design is shown in Figure 38, where the opens are placed on the outside of either
ground plane. An advantage is capability of design for low impedance. On the other hand, with
opens spaced at such a distance, isotropic etch undercutting of the CPW also results in much
undercutting away from the CPW such that a much larger total suspended membrane results than
necessary for the CPW itself. This is in some sense wasted chip area, but the problems were
more serious even for small-scale integration. The structures were on very large membranes
supported by smaller intermittent Si0 2 legs and therefore mechanically fragile and susceptible to
internal stress in the CMOS layers.
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Figure 39. Microphotograph o f a CPW section o f the third type o f design for hybrid micromachining
with opens embedded within the ground planes {G—ground, S=signal).
A major improvement was achieved by moving the opens closer together, within the
CPW ground planes, and extending the ground planes to utilize all of the suspended area for
improved transmission properties. This is shown in Figure 39, and is the basis of all of the final
designs presented in this Dissertation. In this case, the overall suspended area could be decreased
to improve mechanical robustness, while the conducting strips could be made larger. This is the
fully fabricated structure corresponding to the test structures introduced in Section 3.3.2.
While this type of design was chosen as best suiting for the microwave power sensor and
other microwave applications, another type of layout was also investigated. In this, fourth type,
shown in Figure 40, the open is inserted in the signal conductor which is made extremely wide,
such that the current distribution would be negligible in the area where the cuts are inserted. This
design was investigated because it could be successfully fabricated by only topside isotropic
etching, which is very advantageous. Clearly, the major disadvantage is the expected increase in
attenuation due to the opens.
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Figure 40. Microphotograph o f a CPW section o f the fourth type o f design fo r hybrid micromachining or
only isotropic micromachining with opens embedded in signal conductor (G—ground, S=signal).
5.2.2 DETAILED DESCRIPTION OF THE BEST DESIGN
As stated above, the third type of design shown in the microphotograph of Figure 39 was
found to be most suitable for the microwave power sensor application. The design has variations
in the type of metal used, shape of open area, spacing between opens, and many other parameters,
as outlined in Figure 41. In the design, the first parameter which must be chosen is dopen, the size
of the open area. This choice comes from the understanding of the post-processing methodology,
and has to satisfy minimum size requirements that correspond to the CMOS process used, such
that the area will certainly have exposed silicon substrate. Once this value is chosen, the next
important parameter is dos, distance open to something. This distance is important to keep above
certain minimum such that the post-processing steps do not attack any exposed metal or other
layers near an open area. For a good safety margin, this should be > 6 pm on any process.
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Figure 41. Layout o f the end o f a CPW designed fo r micromachining, with micromachining design
dimensions outlined.
Once dopen and dos are chosen, the next parameter in the design is dco, or the distance from
beginning of ground plane to open metal cut. This distance has to be large enough, such that the
return signal path through the ground plane is not affected in terms of significantly higher
attenuation, and filtering effects. Since the CPW is designed for microwave frequencies, and has
highest field regions between signal and ground planes, the dense current distribution is found
only in the first few skin depths away from the ground plane beginning. However, for good lowloss performance down to kilohertz frequencies, the distance should always be as big as possible.
This distance is limited by another factor, which is the total cross-section of the etched pit, since
etching progressing away from the open toward edges of the CPW as well as toward the center.
Therefore, in order to keep the overall size to a certain reasonable number, and avoid bad
mechanical effects of very large membranes, the opens should be as close as possible to signal
conductor which must be sufficiently undercut.
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With the above parameter in place, and given dimensions a and b, we can determine how
much isotropic etching will be needed in the post-process, or the distance dm. However, first we
must decide how much isotropic etch overlap dot is needed for the etch progressing from either
side of the CPW. Enough overlap is needed to ensure enough room for anisotropic etchant to
exchange and etch freely, and to decrease necessary anisotropic etching time. Therefore, with dm
in place around -15 jum, the total isotropic etch needed is dm = doi/2 + doc + b/2.
Although it was previously described in Section 5.1 that all three parameters of the CPW
(a, b, and c) are chosen to satisfy characteristic impedance requirements, parameter c is also
affected by the design for micromachining as shown in this section. Namely, when creating a
circle around each open, with radius dm + dopen/2 + dos, and connecting the perimeters into a box
such as the anisotropic etch does, we find the overall size of the etch pit to an error margin of
anisotropic etch undercut. The design for c CPW dimensions is such that the CPW extends at
least 10 //m away from the pit, such that there is sufficient room for the metal to silicon ohmic
contacts for grounding o f the substrate, and equalization of the two grounds on either side.
5.3 ETCH-DEPTH CRITERION FOR SUFFICIENT SUBSTRATE
ISOLATION
The total capacitance, C, derived in Section 5.1, was expressed in (53) with assumption
of perfect isolation from the substrate. In general, C depends on the air-gap between the CPW
and the substrate {hpit) as can be seen in Figure 35. To determine sufficient gap height hpu, the
effect of the substrate coupling on the bottom-side is calculated approximately in this Section,
assuming zero thickness conductors. Furthermore, we assume the {111} silicon crystal walls in
Figure 35 which form the sides of the etch pit are far away from the center conductor, hence,
their effect on this calculation can be neglected. The lower half-plane capacitance, Chaif-piane, for
the multilayer dielectric case as a function of hpit is calculated using the same methodology as
described in Section 4.5.2.1. Namely, in terms of the conformal mapping geometry function
F(h), defined in Equations (35), (36), and (37), we define Chaif-Pume(h) as:
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C .* - K - K ) “ e .
• n ~ ) + ( 1- e * ) • F(V ) + - 1) • F (A ,) J
(58)
This expression includes silicon substrate, which extends from hpu to infinity, air between hi and
hpu, and oxide dielectric between the zero-thickness CPW and ht, and it is a continuous function
of hPi,. However, the expression is more general since the upper half plane without substrate is
simply Chaif-piane(°°)- Therefore, there exists a minimum
for which any value hpi,>=hPit.min
results in capacitance values within some error margin y % of that of hpa=oo. In other words,
given the above assumptions are acceptable, and actual etch pit depth is greater than or equal
hpfcmub the error in computation which entirely neglects the substrate, as in Section 5.1 above, is
less than or equal y %:
=y.
(59)
As an example, we set y for sufficient isolation as 1.84%. The reason for this particular number
follows. For any two-conductor system in a simple dielectric medium, the electrostatic energy
stored per unit length is We = CV^/2, where C is the capacitance per unit length, and V is the
voltage between the conductors. Since a CPW can be regarded as a two-conductor system, this
allows us to interpret the capacitance relation of (59) in terms of the electromagnetic energies
stored inside the dielectric layer. For example, when hpit = hPiUmin, the ratio of the energy inside
the substrate to overall energy is:
(60)
where Csubs is the capacitance contributed by the substrate when the depth of the pit is exactly
hpiumn• In the expression for total capacitance, we utilized Chaif-piane(°°) to represent upper half
plane contribution (substrate at infinity), and Chaif.piane(hpit.min) to represent the lower half plane
contribution (substrate exactly at hPittmin ). While these expressions can be evaluated by the
conformal mapping equations given in Section 4.5.2.1, we rewrite them as follows, separating
contributions of each dielectric. Lower half plane:
(61)
and upper half plane:
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(62)
subs
where Csioi and Cpit are the contributions of the oxide dielectric and air dielectric in the space
between the oxide and hpitjnin> respectively. If Csubs from Equations (61) and (62) and Chaifpiane(hPil.min)/ChaifPiane(00) from (59) are substituted into Equation (60), we obtain:
( 2 + /) - Cm . ^ (oo)
(2 + /)• { e ^ - 1)'
(63)
For the value of /given earlier, and permittivity of substrate 11.7, we find that WSUb/W,Otai=0.01,
or that for any hpi,>=hpit,mn the ratio of energy in silicon substrate to total stored electrostatic
energy is less than or equal 1%. This is our criterion for sufficient isolation, and therefore
achieving fully-suspended CPWs in CMOS.
The above criterion is somewhat difficult to intuitively relate to line dimensions, since the
relationship is through elliptic integrals. Hence, as a very simple and approximate rule of thumb,
which results from more rigorous analysis and experimentation, we state the following rule for
fully-suspended CMOS CPWs:
V ^1 -5b + ( b - a ) .
(64)
5.4 FULLY-SUSPENDED CPW CHARACTERIZATION
The various types of CPW layouts were tested with an automatic network analyzer from
0.1 GHz to 40 GHz, using the measurement setup and procedure described in Section 4.3. Of
interest were four parameters, which can be represented as complex characteristic impedance and
complex effective permittivity, or as the complex characteristic impedance and complex
propagation constant.
The parameters are not directly obtained from the four measured s-
parameters, because the TRL calibration can not provide a measurement of Zq. However, using
the reference GaAs substrate with well known, low-loss lines, as described in Section 4.3, we
could obtain Z# as well. These parameters gave us all of the desired information about the
CPWs, the most important of which are their dispersion characteristics and insertion loss.
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4.0
—O— S et #2
Set#1
-S7— Set #5
3.5
fj
.
&
>
£
E
©
£L
§
3.0
25
25
2.0
O
a>
Ui
1.5
I
1.0
<0
<r
=
0.5
0.0
0
5
10
15
20
25
30
35
40
Frequency [GHz]
Figure 42. Measured real part o f effective permittivity fo r three CPW layouts from Table 2.
It was shown in Section 4.3 that for unetched CPWs on CMOS-grade silicon, the
effective permittivity is a strong function of frequency, and therefore the lines were not only very
lossy but also dispersive. On the other hand, measurements of three different configurations
(from Table 2) of fully-suspended CPWs, shown in Figure 42, exhibit very little dispersion,
particularly set #2 and set #5 for which the real part of permittivity is nearly perfectly flat over
the wide frequency range.
The variation at low frequencies for set #1 is attributed to
measurement errors. This, earlier CPW set, did not include sufficiently long delay lines for
accurate TRL measurement below 10 GHz.
The imaginary part of the effective permittivity represents the losses in the lines, and is a
very helpful parameter when observing change of CPW propagation with depth of etching. The
measurements of the above three sets are shown in Figure 43.
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0.0
®
a.
>
%
£
■5
tr
(0
Q.
d>
<0
E
*1'5
-2-0
—o — S et# 2
S e t# l
—^7— Set #5
-2 5
^-5
-3.0
0
5
10
15
20
25
30
35
40
Frequency [GHz]
Figure 43. Measured imaginary part o f effective permittivity fo r three CPW layouts from Table 2.
The measured effective permittivity can also be expressed in terms of phase velocity,
which allows us to see more directly the benefits of designing the lines in very thin lowpermittivity dielectric, such that phase velocities close to air-line are achieved. The plot of
normalized velocities for the same three sets is given in Figure 44.
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1.0
0.9 -
o
&
oo
0.8
-
>
•rrYrrTXcgoooooJXcocmTrTrrrxxaxo^P
0.6
—O— Set #2
Set#1
- v - Set #5
.I
J
Q5 ll i i i I i i i i I i i i ■
i I i i i i I i ■i ■I ■■i ■I i ■i i l i i ■i
0
5
10
15
20
25
30
35
40
Frequency [GHz]
Figure 44. Measured normalized phase velocity fo r three CPW layouts from Table 2.
The configuration listed as set #1 in Table 2 corresponds to an earlier design which was
subsequently abandoned for the microwave power sensor application. This configuration was,
however, very interesting because of its unique characteristic of opens inserted between signal
and ground planes, as discussed in Section 5.2.1 and shown in Figure 37. This results in nearlowest obtainable real part of permittivity CPW, as well as the CPW with velocity closest to that
of light, as seen in Figure 44. While such a structure can not be implemented with low enough
characteristic impedance, it can be seen from these measurements how it can be very useful in
other applications, such as non-linear delay lines for picosecond pulse generation [75].
The attenuation measurements for representative transmission lines are shown in Figure
45. While the attenuation still exceeds 3 dB/cm for frequencies above 20 GHz, this attenuation
is due to the metallic losses that can not be significantly improved in such miniature designs.
Beside miniature dimensions, the CMOS aluminum is also slightly less conductive than more
standard aluminum, which is itself not the most desirable conductor for microwave applications.
This was, of course, part of the expected trade off of slighdy lesser performance with the
provision of monolithic integration with CMOS circuits. Nevertheless, these CPWs are ordersof-magnitude improved from the corresponding unetched CPWs (Figure 27.) This was the most
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important result that led to the investigation of microwave sensors in CMOS MEMS. More
recently, we have been probing further into the loss mechanisms of the etched CPWs and the
relationships of loss-effective permittivity, and loss-characteristic impedance [76].
8
7
—O— Set #2
—
Set #5
6
m
4
o
3
<
2
1
0
5
10
15
20
25
30
35
40
Frequency [GHz]
Figure 45. Measured attenuation fo r two CPW layoutsfrom Table 2.
Figure 46 shows measured characteristic impedance for two representative sets from
Table 2. In both cases, where metal 1 (set #4), and metal 2 (set #5) were used, the measured Z q is
slighdy higher than desired. At 40 GHz, e.g. measured Z# for set #5 is 51.6 G, and for set #4 Zo =
52.5 Q. That particular results compares well with values measured at 20 GHz, where Zq - 52.1
Q. for set #5 and 53.2 Q. for set #4. The consistently measured higher impedance than designed
for is attributed to the lack o f flatness in the dielectric passivation over the CPW conductors, due
to layer stacking of these older CMOS processes. Namely, in the region where metal is missing,
the total membrane thickness is decreased by approximately metal thickness, such that the
capacitance in the region between the signal and ground conductor is always slightly less than
that predicted with the flat hu model (Figure 35).
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80
—O— S et #4
Set #5
S,
70
rsf
<D
O
C
OS
*o
<D
g
60
o
to
O
50
40
0
5
10
20
15
25
30
35
40
Frequency [GHz]
Figure 46. Measured characteristic impedance fo r two CPW layouts from Table 2.
Because of the consistency o f this error in older processes, we hope to adjust this design
error with a parameter.
In most recent CMOS processes, chemical-mechanical polishing is
utilized to flatten the chip surface after each layer’s deposition, where our modeling will be much
more accurate. Errors are also attributed to the process variations, since the actual fabricated
thicknesses vary as much as 0.1 p m from their expected values. We have investigated the effect
of such variations in [37], and found that due to the very thin membranes, our CPWs are
extremely sensitive to such small variations in terms of resulting variation in Z q. Therefore, as
stated before, careful process control is needed, such as has become introduced in most recent
CMOS processes.
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CHAPTER 6 - CHARACTERIZATION OF THE SENSORS
During the course of the presented research, a large number of CMOS microwave power
sensors were designed, analyzed, fabricated, and experimentally characterized. We have tried a
number of varying types of designs, different CMOS technologies and fabs, variations in post­
processes, and even different measurement setups and procedures. In the end, two types of
designs were focused on, as described in detail in the previous chapter. Some of the earlier
results for the less optimal designs are summarized in [67] and [68]. In this chapter, the results
for the more optimal, recentiy fabricated devices are presented. The measured results for the
directly and indirectly heated sensors are compared against each other, against previously
reported results of other authors, and against representative commercially available devices.
In Section 6.1, results based on the dc measurements are given, namely the device’s
sensitivity, linearity, and dynamic range when dc power is dissipated in the termination. Section
6.3 presents the ac measurements, which were performed to obtain the devices’ thermal time
constants, as well as to verify the effects of convective cooling on the devices. The main results
of overall microwave power measurements performance are given in 6.4.
6.1 NUMERICAL CHARACTERIZATION USING FINITE-ELEMENT
SIMULATORS
The assumptions, approximations, and final model equations in the previous chapters
were verified by numerical computation of capacitances in Maxwell 2D electrostatic finiteelement simulator [77]. Simulations of the CPW cross-sections, with and without the underlying
silicon substrate matched the modeled results very closely. Some comparisons were discussed in
detail in [37].
A commercial electromagnetic simulator was also frequently utilized to help predict
performance of CPWs, polysilicon terminations, and overall devices. The Sonnet EM simulator
suite [78] is not a true 3D full-wave simulator, but utilizes some approximations due to the
planarity of designs (it is geared for microstrip structure simulation) and is therefore regarded as
a 2.5D simulator. It computes ^-parameters for each desired frequency, and therefore provides
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outputs which are immediately comparable with network analyzer measurements. Since our
structures are always planar in nature due to the CMOS implementation, the simulator was
considered appropriate.
Firstly, the fully-suspended CPW was simulated, also utilizing the deembedding feature
of Sonnet, to obtain per length 5-parameters of the CPWs. Subsequently, we simulated the
overall structures of Sensor 1 and Sensor 2, to predict their input mismatch error over all
frequencies, therefore only considering su results. These results are included with measured
results in the subsequent sections.
6.2 DC MEASUREMENTS
Many characteristics of the sensors were obtained under direct current driving. From
simple current-voltage (I-V) measurements, many characteristics of the terminating resistor can
be extracted, including its resistance as a function of applied power, thermal efficiency, etc. In
all of the dc measurements, the thermopile output was observed as well to obtain sensitivity and
linearity of the sensors. These measurements are also essential for correct thermal modeling of
the device as will be described in detail in Chapter 6. In most cases of dc measurements, only
Sensor 1 was considered since the second type of sensor includes the dc blocking capacitor at
output nodes.
6.2.1 CURRENT-VOLTAGE (I-V) MEASUREMENTS
Measurements of the I-V characteristics were performed in a vacuum chamber in which
we could control the pressure and gas content. This was interesting because with pressure
control, we could obtain results for the devices when convective heat transfer is made negligible,
and compare those results with operation in air.
Measurements were performed by applying a ramping input voltage from 0 to 1.5 Volts,
such that the total power dissipated would never exceed 40 mW. Input current was monitored, as
well as thermopile output voltage.
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25
20
15
<
E
10
5
—• — In vacuum
—O-- In ambient air
0
0.0
0 .4
0.6
1.0
0.8
1.4
1.6
Figure 47. Measured input voltage vs. currentfo r Sensor I termination in ambient air and in vacuum.
The graph in Figure 48 shows the results of the same measurements plotted as power vs.
termination resistance, where resistance was obtained simply as V/I, and power as V*I. The plots
in Figure 48 are nearly linear, which is expected from the first order thermistor model. Namely
the termination resistance increases proportionally with dissipated power due to the positive tcR
as:
K(r)=R0(i+rcs
(r-r0)),
(65)
where Rq is the resistance at a reference temperature To, T is the resistor temperature. Since the
temperature difference is proportional to input power via total thermal conductance, as in (7), we
can rewrite (76) as:
f
R(T)=Ro
p
1+ tCR —
gt
\
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(66)
70
68
66
64
62
G
60
g
of 58
56
54
52
—
In vacuum
--O -- In ambient air
50
48
0
10
20
PiJmW]
30
40
Figure 48. Measured input power vs. input dc resistance o f the termination on Sensor I in ambient air
and in vacuum.
Consequently, these measurements and equation (76) and (77) allow us to extract both the
average resistor temperature T, as well as the total thermal conductivity of the sensor. The
extracted intercepts and slopes of the plots in Figure 48 are 49.6 Q and 0.486 Q/mW, and 49.6 Q
and 0.386 Q/mW, respectively. Therefore, we compute the total thermal conductivity G j of
0.091 mW/K, and 0.116 mW/K, for vacuum and ambient air, respectively. The increase in
ambient air is expected, due to additional thermal conduction and convection via air.
6.2.2 POWER SENSITIVITY MEASUREMENTS AT DC INPUT
During the I-V ramp measurements, the output of the thermopile was also recorded. This
allows us to interpret the senstivity of the device by plotting the measurements as V*I vs. output
voltage. This is shown in Figure 49. From the measurements, a sensitivity of 2.87 mV/mW was
extracted which is exceptionally linear for powers up to 10 mW after which the measurements
start including more and more non-linearity.
In vacuum, sensitivity of 3.13 mV/mW was
extracted for the same device. This measurement unfortunately could only be performed for
Sensor 1 since the configuration o f Sensor 2 with its output dc blocking capacitor does not allow
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simultaneous dc input and output. The sensitivity at microwave frequencies will be given in
6.4.3.
140
120
100
80
E
Q.
>
fin
40
—• — In vacuum
--0 -- In ambient air
20
0
5
10
20
15
25
30
35
40
Pin [mW]
Figure 49. Measured input power vs. output thermopile voltage o f Sensor 1 in ambient air and in
vacuum.
The slowly increasing slopes of both curves at higher powers in attributed to Peltier
effect.
Namely, with dc excitation, Peltier heat is generated at the aluminum/polysilicon
contacts. This effect is much more pronounced at the contacts on the inside of the device (signal
conductor to resistors), where heat is added. The outside contacts are thermally well connected
to the substrate and therefore do not exhibit significant changes in temperature due to Peltier
heat. Consequently, at powers above 10 mW the response becomes increasingly non-linear. The
effect at 10 mW (upper power limit specification) can be approximated as follows.
The
coeffcient of 31 mV and a current of 14.1 mA produce 0.4371 mW of heat. Directly observing,
this would mean an approximate error of 4.4%. In terms of temperature, using the measured G j
of 0.116 mW/K and (7), Peltier heat increases temperature at the center 3.8°. In the real device,
the power added at the very inside junctions is mostly observed by the near thermocouples, and
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not by the more distance ones, so the actual percentage error is actually below 1% as the
measurements showed.
6.3 RESPONSE TIME MEASUREMENTS
The thermal time constant of the thermocouple power sensor determines integration
capability, and sets up the device’s low frequency limit, as explained in Section 2.5.4. In the
design of ac-dc thermal converters for low-frequency measurement applications, this is a critical
parameter, and sensors are thermally loaded to achieve very slow thermal time constants. In this
case, however, the frequency range of interest is 100 MHz to 50 GHz, and the thermal time
constant should be much longer than 10 //s for adequate averaging.
For signals of relatively low frequencies, such that their time constants are longer than the
thermal time constant of the sensor, the sensor temperature follows the trend of the instantaneous
input power. We applied an input signal at -20 mW power and 10 Hz to Sensor 1 to show
operation well below cutoff frequency for average power measurement. The measurements are
shown in Figure 50. Because input voltage is sinusoidal, the output voltage essentially behaves
as sin2(t). The plot of output voltage displays small differences at peak values for the positive
part of input waveform and the negative part of the input waveform. The differences are on the
order of a few percent and are due to thermoelectric effects, which generate or absorb heat
depending on the current direction. These effects no longer affect the device at frequencies
above cutoff, where only average power is measured due to relatively longer thermal time
constant. The effect of Peltier and Thomson heating and cooling on the Sensor 1 structure will
be discussed in more detail in Chapter 7.
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-1
H -80
Input voltage
Thermopile Output
-i -ioo
-! -120
■*—T -140
-100
-50
0
50
100
Time [ms]
Figure 50. Measured thermopile output voltage o f Sensor I as a Junction o f time fo r applied sinusoidal
input voltage at 10 Hz —measured instantaneous power.
To measure the thermal time constants of the sensors, we measured their response with
applied input step function. The graphs in Figure 51 show the response of the sensor to a 1.5 V
step function, both in ambient air and in vacuum. From an exponential fit of thermopile voltage
given by [17]:
(67)
the approximate thermal time constants of r,* = 1.37 ms and %,h = 1.49 ms were extracted, in air
and vacuum respectively. The 99% settling time for the two cases is 7.42 ms and 7.85 ms.
For the alternative configuration, Sensor 2, thermal time constant of %\h = 1.77 ms was
extracted. A slightly higher value was expected for this design, due to the better isolation o f the
two heating resistors from the substrate. In the case of Sensor 1, the outer ends of each resistor
effectively remain at substrate temperature because of their very close proximity to the unetched
silicon.
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180
160
140
120
>
E
100
80
60
•
Measured in ambient air
—°— Measured in vacuum
Model fit in air
Model fit in vacuum
40
20
0
2
6
4
8
10
12
Time [ms]
Figure 51. Measured thermopile output voltage o f Sensor 1 in ambient air and in vacuum, as a function
o f time fo r applied step input power.
6.4 MICROWAVE CHARACTERIZATION
6.4.1 MICROWAVE MEASUREMENT SETUP
Microwave measurements were performed with a variety of experimental setups,
depending on the measurements being extracted. For the network analysis, i.e. extraction of sparameters of the CPWs, or one port s }1 of the sensors, a Wiltron 360 automatic network
analyzer was utilized with frequency range from 0.01 GHz to 60 GHz. The setup included dc67GHz GSG configuration probes, and 2.4 mm cables. This is a different set of hardware than
utilized in the CPW characterization on silicon given in Chapter 4, but in both cases same de­
embedding methodology (TRL calibration) was utilized. All the details of the procedure are
given in Section 4.3. The reference plane in most of the measurements presented was half of a
thru element (Figure 26) away from the probe contact area. In some cases, however, such as in
the measurements of individual power sensors, reference plane was calibrated at the probe tips
utilizing a reference calibration substrate.
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For the characterization of the power sensors conversion linearity, frequency vs.
sensitivity, and similar measurements, a different setup was used. A separate synthesizer source
was used which has a frequency range from 10 MHz to 50 GHz, and can output up to 20 dBm of
power at all the frequencies. The power was applied to the sensors through the 2.4 mm cable and
dc-67 GHz GSG probes. However, before connecting the cable to the probe on the probing
station, a commercial HP8487A 50GHz power meter was connected to the port which was used
to calibrate power flatness over all frequencies for the synthesizer. The synthesizer subsequently
recorded calibration factors for each frequency.
Having thus connected the probe to the
calibrated source, we could be confident of the actual power output of the probe tips, since we
had available the insertion loss measurements for the probe, as well as the calibration factors for
the HP8485A power meter.
These were taken into account in the post-processing o f the
measurements.
6.4.2 BROADBAND MATCHING CHARACTERISTICS
In order to operate devices with microwave sources from 100 MHz to 50 GHz, the
sensors should provide a good RF match to the sources over all the frequencies. In some cases,
badly matched devices can cause sources to fail due to high reflected power. Therefore, over the
very broadband frequency range, the input reflection parameter should remain below -10 dB.
This was achieved for both Sensor 1 and Sensor 2 configurations up to 40 GHz, as shown
in the subsequent plots. Figure 52 and Figure 53 show the measured and simulated reflection
parameter su for Sensor 1, and Figure 54and Figure 55 for Sensor 2. Above 40 GHz, the
performance does not degrade rapidly, although the reflection for Sensor 2 exceeds -10 dB. The
device is still considered operable up to 50 GHz unless the particular application provides more
strict specifications.
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0
—v — Measured
Simulated
-10
-20
CQ
-o
co
-30
-40
-50
0
10
20
30
40
50
Frequency [GHz]
Figure 52. Measured and simulated magnitude o f input reflection parameter o f Sensor 1.
10GHz
25GHz
40GHz
50GHz
Figure 53. Reflection chart o f the measured input reflection parameterfo r Sensor 1.
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At 10 GHz, the measured voltage standing wave ratio (VSWR) was 1:1.043, at 25 GHz VSWR
was 1:1.14, at 40 GHz VSWR was 1:1.54, and at 50 GHz VSWR was 1:1.96. The measured vs.
simulated plots in Figure 52 show a difference of up to 10 dB. Throughout the fiequency range,
the measured results showed a seemingly better match than those expected from simulations.
This is attributed to the lossy nature of the real structure, particularly the probing pad area, and
the CPWs, which were both not included in the Sonnet EM simulations. The actual differences
in reflected power are however extremely small, when not viewed on log scale.
—v — Measured
Simulated
-10
m
"D
-20
m
of
-3 0
-4 0
-5 0
0
10
20
30
40
SO
Frequency [GHz]
Figure 54. Measured and simulated magnitude o f input reflection parameter o f Sensor 2.
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Figure 55. Reflection chart o f the measured input reflection parameterfo r Sensor 2.
At 10 GHz, the measured voltage standing wave ratio (VSWR) for Sensor 2 was 1:1.038, at 25
GHz VSWR was 1:1.25, at 40 GHz VSWR was 1:1.80, and at 50 GHz VSWR was 1:2.22. In
the case of Sensor 2, the measured input reflection shows two notable differences from the
simulation plot in Figure 54. Firstly, at the low frequency end, the measured input mismatch
increases substantially, although still remaining below -20 dB. This is due to the finite size of
the dc blocking capacitor which is not a virtual short circuit at the 100 MHz frequency, but
introduces impedance in the termination. As frequencies increase, the inserted impedance due to
the blocking capacitor, \Zcb\=I/(co Cb), becomes insignificant and the output port is truly
virtually shorted for RF energy. In the simulations, the structure of Figure 9 was simplified for
sake of simulation time, such that the output capacitor is removed, and output is simply shorted.
Therefore, the increase in reflection at lower frequencies is not present. This also explains the
difference between simulation and measurement at -13 GHz, where measured results show a
resonance of nearly perfect matching.
This resonance is not very well understood at this time.
However, we believe that it is due to both the input mismatch at the probing pads, as well as the
output mismatch due to the finite capacitor size which result in a resonant standing wave at this
frequency, the energy of which is dissipated in the resistors.
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For comparison, we also include the input reflection parameter measurements for a
commercial dc-50 GHz thermocouple sensor fabricated by Hewlett-Packard [1], HP8487A. The
data shown in the plot in Figure 56 is listed on the back of the sensor, and can be used for
calibration purposes. It can be seen that the commercial device, based on a custom fabrication
process with appropriate packaging performs better above 30 GHz, and remains below —15 dB.
At frequencies below 30 GHz, Sensor 1 and Sensor 2 perform comparable, and in some regions
better. In this range, however, all of the devices are below —20 dB, and differences of a few dB
are not very significant.
—• — Sensor 1
--O -- S en so r2
—▼— HP 8487A
-10
C
O
"O
-20
CO
-30
-40
-50
0
10
20
30
40
50
Frequency [GHz]
Figure 56. Compared magnitude o f input reflection parameter for commercial thermocouple sensor
HP8487A, Sensor 1, and Sensor 2.
6.4.2.1 BROADBAND M ATCH UNDER DC BIAS
To obtain information about the performance of the broadband matched termination with
varying resistance, we measured the reflection sn parameter of a slight variation of Sensor 1
from 0.1 GHz to 50 GHz while applying dc bias to portl of the ANA.
This raises the
temperature of the sensor which in turn increases the termination dc resistance. In other words,
we can obtain information about the matching performance at maximum power of 10 mW, as
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well as a general idea of how the CPW and termination structure behaves since only R,enn is
varied.
b cdef
10GHz
25GHz
40GHz
50GHz
-10
M
a
9
n
-1 5
t
-20
u
d
e
-2 5
(dB)
-3 0
-3 5
0
5
10
15
20
25
30
35
40
45
50
Frequency (GHZ)
Figure 57. Reflection chart o f the measured input reflection parameter fo ra variation o f Sensor I when
dc bias is applied at portI o f a) 0 mW, b) 10 mW, c) 34 mW, d) 53.5 mW, e) 76 mW, andf) 100 mW.
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In Figure 57, measured su parameters for one Sensor 1 termination under various dc bias
conditions are shown in a reflection chart and a log magnitude plot. At no applied bias, at 0.1
GHz, this termination measured 53.1 £2 impedance. At 10 mW dc bias, it measured 57.5 £2, at 34
mW dc bias 66.4 £2, at 53.5 mW dc bias 74.7 £2, at 76 mW dc bias 82.3 £2, and at 100 mW dc
bias 88.5 £2. Therefore, at the specified maximum input power of 10 mW, the deviation from
cold impedance is 4.4 £2. This is consistent with the results obtained simply from current-voltage
measurements in Section 6.2.1. Namely, in those measurements, a slope of 0.386 £2/mW was
measured for a 49.5 £2 cold termination. That would equal 0.414 £2/mW for the above tested
termination, and would therefore predict a total 4.14 £2 deviation at 10 mW.
In terms of the reflection coefficient at the load, the maximum percent error due to
resistance increase at maximum power of 10 mW is found as:
% error = 100
|rtoarf pnax|2.
(68)
For most of the tested devices, the resistance increase was roughly 4 £2, for 50 £2 terminations,
which results in //7oad_pmar / ^=0.038, and therefore only 0.15% error. To extend the dynamic
range significantly (e.g. a decade) would require a resistor material with a lesser tat-
6.4.3 SENSITIVITY MEASUREMENTS
As mentioned earlier, the frequency vs. sensitivity measurements were obtained with a
synthesizing source which had power flatness calibration performed using a commercial dc50GHz power meter.
While the measured devices were fully fabricated, they nevertheless
included small probing pad regions that were not suspended. Therefore, the small area of
conductor on silicon substrate increases the reflection coefficient slightly, as well as introduces
some small uncertainty about the actual power delivered to the sensor.
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3.5
Sensor 1
Sensor 2
3.0
~ 25
.E
> 2.0
>.
>
co
c
1.5
®
CO
1.0
0.5
0.0
0
10
20
30
40
50
Frequency [GHz]
Figure 58. Measuredfrequency vs. sensitivity for both sensors.
The measured sensitivity as function of frequency for both sensors is shown in Figure 58.
It is evident that while Sensor 1 exhibits significantly higher sensitivity, it also exhibits more
frequency dependence, which is undesirable. When we apply a linear regression to both curves,
we obtain the following parameters. Sensor 1 sensitivity at the low frequency end is 3.04 V/W,
and it drops approximately linearly at the rate of -0.01 (V/W)/GHz. Sensor 2 sensitivity in the
low frequency limit is 0.67 V/W, and its linear rate of decrease is -0.0048 (V/W)/GHz.
As in the previous section, we compare the above frequency response of our sensors with
the commercial HP8487A thermocouple device. The data of the sensor’s normalized sensitivity
as a function of frequency, as shown in Figure 59 is extracted from the back of the sensor (for use
in calibration). The data in the plot was normalized to the low-frequency sensitivity of the
device, and the normalized frequency response decreases at the approximate linear rate of 0.002
(V/W)/GHz. When the data for our sensors is normalized similarly, as also shown in the figure,
the decrease for Sensor 1 is 0.0033 (V/W)/GHz, and for Sensor 2 is 0.0072 (V/W)/GHz.
Sensitivity for sensors 1 and 2 decreases much more linearly. This leads us to believe that due to
the CMOS integration, a compensation algorithm for measurements could be implemented based
on estimated measurements of input frequency range.
Overall, the performance is very
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competitive with the commercially available devices, which are very bulky, extremely costly, and
require much additional circuitry integration off-chip.
1.0
o
0.9
cPo
>
CO
c©
CO
E
k_
o
z
0.8
0.7
•
Sensor 1
- - 0 - - S en so r2
HP 8487A
0.6
0.5
0
10
20
30
40
50
Frequency [GHz]
Figure 59. Compared frequency response HP8487A commercial device. Sensor 1, and Sensor 2. Each
plot is normalized to sensitivity at lowestfrequency.
6.4.4 DYNAMIC RANGE AND LINEARITY MEASUREMENTS
Plots of input power vs. output voltage for Sensor 1 are shown at different frequencies in
Figure 60.
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30
25 -
20
—
--0-*
—T —
—<7-—
Freq = 1 GHz
Freq = 10 GHz
Freq = 20 GHz
Freq = 30 GHz
Freq = 40 GHz
-
5*
E
15
10
Pin [mW]
Figure 60. Measured input power vs. output thermopile voltage o f Sensor I at various frequencies.
100
10
Sensor 1
S ensor 2
0.1
0.01
0.001
0.0001
-30
-10
-20
0
10
Power [dBm]
Figure 61. Measured input power vs. output thermopile voltage o f Sensor 1 at 20 GHz, plotted to show
response throughout the dynamic range.
Ill
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The plots in Figure 61 are shown on log scale, for better verification of the curves througout the
dynamic range. When plotted linearly, such as in Figure 58, we extracted slope of the Sensor 1
plot in Figure 61 is 2.522±0.0032 V/W, i.e. over the design 40 dB dynamic range, Sensor 1 has
maximum linearity error of 0.128 %.
On the other hand, the slope of Sensor 2 plot was
0.609±0.0015, showing maximum linearity error o f0.245 %.
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CHAPTER 7 - THERMAL CHARACTERIZATION AND
MODELING
In past IC implementations of thermoelectric sensors using micromachining techniques,
the main design emphasis was to obtain as high sensitivity as possible. In the case of this work,
however, the main objective is to attain good broadband microwave matching such that the
devices can be sufficiently accurate up to 50 GHz. This comes at the cost of lowered sensitivity,
since the numerous thermocouples in very close proximity of the microwave termination resistor
affect the sensor’s microwave matching performance.
It is still possible to attain higher sensitivity by clever layout of the thermocouples, and
proper adjustment of parameters such as: number of thermocouples, their suspended length, their
proximity to the termination resistor, their lateral position with respect to the resistors’
temperature distributions, etc.
The trade-offs in layout related to these parameters were
described in detail in Section 2.5.
This chapter reports on the results of both experimental and analytical thermal
characterization of the micromachined microwave power sensors, which provides insight into the
proper adjustment of the above parameters to optimize device sensitivity. Experimental results
were obtained by indirect measurements of the sensor temperature distribution under various
applied power conditions. A simple and approximate model was developed, and adjusted based
on experimental results, which was then used to show the effects of the variations in any of the
above mentioned layout parameters on the overall device sensitivity.
The model converts the thermal aspect of the physical layout of the device to a simple
SPICE model where electrical resistances represent thermal resistances, while current sources
represent heat generation from input power.
7.1 MEASUREMENT SETUP AND PROCEDURE
Thermal measurements of sensors were performed using a Barnes EDO Thermal Imaging
Microscope. Suspended power sensors were prepared as described in Chapter 3 and packaged in
40-pin dual inline packages (DIPs). The packages were mounted on a copper block and attached
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to the microscope stage. Heat sink paste was used to ensure good thermal connections between
the package and the stage. Power was applied to the sensor using a variable voltage source.
Voltage sources were set up such that both positive, negative, and sinusoidal ac voltage
Both
applied voltage and current were monitored to record exact input power during measurements.
The thermal imaging microscope records 2-D images of radiance in the 3000 nm to 6000
nm wavelength range. Before the measurements were taken, the inherent radiance of the chip was
recorded. This data was used by the microscope to compensate for the inherent radiance during
imaging. These images were exported and analyzed using a mathematical software package.
A zero-input
radiance image was used to align the thermal images with the actual devices.
Images were taken with various power levels applied.
7.2 MODEL EQUATIONS
In general study of thermal and thermoelectric microsensors, there are three forms of heat
transfer that occur: conduction, convection, and radiation [69]. All three are initially considered
here, although in subsequent sections, the analysis will be greatly simplified based on some
assumptions of the sensors’ operation.
7.2.1 NOMENCLATURE
Following nomenclature is used in this section, in agreement to that used by Swart and
Nathan [72]:
A
Area (m2)
p
Perimeter length (m)
c
Specific heat/unit mass (J/kg K)
h
Heat-transfer coefficient (W/m2K)
I
Current (A)
/
Length (m)
q
Heat transfer/unit area (W/m2)
q’
Heat transfer/unit volume (W/m3)
T
Temperature (K or °C)
t
Time (s)
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with permission of the copyright owner. Further reproduction prohibited without permission.
a
Temperature coefficient (1/K)
e
Surface emissivity
k
Thermal conductivity (W/mK)
a
Stefan-Boltzmann constant (W/m2 K4)
Ro
Resistance at room temperature
p
Density (kg/m3)
7.2.2 CONDUCTION
The equation governing heat transport by conduction in general form is given as [69]:
v - 0 c v r ) + ? ' = cp ^ ,
at
(69)
where K c, q\ and p can all be functions of temperature. In the simulations of interest here, we
are only interested in steady state case, which turns Equation (69) into the well-known Poisson
equation:
(70)
The transient case would be of interest as well if we wanted to optimize the devices’ thermal
time constant. However, as shown in the measured performance in Section 6.3, the devices
thermal time constants, although very short for ac applications, are sufficiently long for all
frequencies of interest.
7 .2 3 CONVECTION
Convective heat transfer represents the portion of the thermal energy transport resulting
from the motion of a fluid. If the motion of the fluid is due to external forces such as a fan, then
the process is termed forced convection. If, however, the fluid motion is a result of density
differences in the fluid caused by temperature gradients, the process is termed free or natural
convection. In both cases, the total heat transfer from a surface is given by [69]:
Q = h A (T ,-T ,),
(71)
where Ts is surface temperature and 7/ is the free stream temperature in the case of forced
convection, or simply ambient temperature.
The parameter h depends on several other
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parameters,
including the type of convection. There are many waysof finding appropriate values
for h, and
theone that isperhaps most suited is the following relation which includes an
important dimensionless parameter known as the Nusselt number [69]:
N
u
=
(72)
K
where
k
is the thermal conductivity of the fluid surrounding the surface, and Lc is the
characteristic length of the body, often defined as:
Lc = area/ perimeter = — .
P
(73)
7.2.4 RADIATION
Heat loss through radiation is governed by the Stefan-Boltzmann law, which for a gray
surface is given as [69]:
q ^ = e a ^ - T ‘ ),
(74)
where Ts is absolute surface temperature and T„the absolute temperature in the far field. This is
a simplified case of a gray body far away from other such bodies, such that no interaction occurs.
Heat loss through radiation can usually be neglected in microsensors that operate at temperatures
less than -200 °C, but becomes very significant as temperature increases past -500 °C, due to the
fourth power in (74).
7.3 SPICE EQUIVALENT CIRCUIT FOR THERMAL MODEL
In contrast to an analytical solution, which allows for temperature determination at any
point of interest in a medium, a numerical solution enables determination of the temperature at
only discrete points.
Determination of the temperature distribution numerically requires that an
appropriate conservation equation be written for each of the nodal points of unknown
temperature. When we subdivide a 2D system into a number o f small regions, as shown in
Figure 62, and assign to each a reference point that is at its center (a nodal point or node), we
arrive at a nodal network or mesh.
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Figure 62. Nodal network representation o f two dimensional conduction in discrete form.
Using a network for which Ax=Ay, and assuming no heat generation (q ’=0 in (70)), the twodimensional, discrete form of (70) gives [80]:
"*■^m+!.n + ^m-I,n ~ ^m ji = ®»
(75)
The finite-difference form of the heat equation given in (75) is a result of applying conservation
of energy to a control volume about the nodal region, and is thereby equivalent to Kirchoffs
current law in electrical systems. This alludes to the fact that resistive electrical networks can
represent such a thermal systems adequately. Moreover, application of the energy conservation
results in expressions of Fourier’s law, which can in one dimension be written as
q = - K d T /d x ,
and is therefore a thermal equivalent of Ohm’s law in resistors.
The methodology for thermal modeling and optimization using SPICE has been
introduced by Swart and Nathan [72]. In their work, the thermal model equations from above
sections are translated into equivalent SPICE circuit elements, through the finite-difference form
of the equations. Heat flow is represented as current, temperature as voltage, and heat power as
electrical power.
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^TSU S
I El 1 .- Metal 1
] El. 3 - Glass
El. 2 - T.couple
El. 4 - Polysilicon
Figure 63. Symmetry portion o f the thermopile layout, showing the pertinent dimensions o f the
microwave termination and adjacent thermocouples. Below is an outline o f that layout showing the four
types o f elements and subdivisions used in simulations.
Our analysis in this work is simplified from [72] in the following ways. In the convection
model, only natural convection is of interest, and all convective losses from a small surface
element are lumped into one thermal resistance term.
Another simplification is in the
subdivision of the actual structure in a relatively small number of regions in a two-dimensional
plane, as outlined in Figure 63b, since we are more interested in observing optimization trends,
rather than attempting to predict device performance very accurately. Finally, as an additional
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simplification, radiation losses are neglected.
This is easily justified since the devices are
specified to operate up to 10 mW maximum input power for which case maximum temperature
on the device is found to be <100 °C, and radiation is negligible.
Figure 64. Equivalent electrical circuit representation o f an element o f Figure 63, including convection,
conduction and heat generation terms, by nonlinear resistors and current sources.
The three-dimensional thermopile structure is treated as 2D in the layout plane, due to the
fact that only air is present above and below the structure, and the convective losses in those
directions can be combined into one resistive circuit element at each element in the plane. The
2D layout is further subdivided into smaller elements, each being one of four types as shown in
Figure 63. Since the modeling was not aimed at high accuracy, the subdivisions are relatively
large, as outlined in Figure 63. Only the polysilicon resistor and the hot thermocouple junctions
are subdivided into many sections to find the temperature distribution with greater accuracy.
Each element is then represented as the equivalent circuit of Figure 64, with particular values
depending on the element type, and size. In general, the resistors in the figure are non-linear, and
may depend on temperature or other parameters.
The current source in Figure 64 is only
applicable for resistive elements in the device structure where dissipated power generates heat,
and may also have temperature and other dependence.
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7 3 .1 REPRESENTATION OF DEVICE ELEMENTS BY SPICE ELEMENTS
In accordance with Swart and Nathan [72], each of the circuit elements shown in Figure
64, representing heat transfer, is described by a voltage-controlled current source (VCCS). The
form used here is simply:
I= a Q+a1V+a2Vz + ...,
(76)
since it sufficiently describes the thermal resistances shown in the figure, the temperaturedependent heat generation in polysilicon, radiation losses, as well as thermoelectric effects
defined in Section 2.1.
As a result of the above mentioned Fourier law, in the simple case where there is no
variation in parameters due to change in temperature, the conductive transfer of the left-hand-side
of (70) is simply represented as thermal resistance:
(77)
Rlh= l / K - A .
This assigns the coefficients of the VCCS in (76) with aj=KA for the conduction elements, while
ao is zero. This sets up the four conduction resistors R/ and R2 which differ from element to
and cross-sectional area A. Theconvectionresistor Rh isa
element by the
conductivity k;
represented by
a VCCSwithai=hA. The heat generation termon theright-hand-side of (70)
represents the input power, which if constant, can be modeled by a constant-current source.
However, the input power to the resistive microwave termination is dissipated by the thin-film
polysilicon heater, whose resistance is a strong function of temperature. Due to this strong
temperature dependence, the input power is implemented as:
^ ) = / 2/?o + / 2/?0-a(7’- 7 ’0),
(78)
which sets up ao=I2Ro and aj= aI2Ro.
7.4 SIMULATION SETUP
Simulations were set up by forcing constant current excitation 21 at power sensor input,
therefore nominally forcing input power (2 lfR Urm- The even symmetry condition, as outlined in
Figure 63, was set up by doubling values of resistors Rj in the bottom row, and cutting off lower
resistors R 2 in that same row. The constant input current I was therefore forced into the resistor,
120
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which enters (77). After the network of VCCSs is created and simulated in SPICE, the resulting
node voltages are treated as temperatures, and the heater temperatures are fed back to obtain the
adjusted termination resistance:
= * ,I & + < w G r ,-T Q%
(79)
I
since each i-th subdivision has increased resistance. Hence, the actual power dissipated in the
termination resistors is:
(*°)
The thermopile output voltage is a sum of temperature differences of all hot and cold junctions
with See beck coefficient as weighing function:
and finally, sensitivity is simply S = Vou,/Pdiss[V/WJ.
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7.5 RESULTS AND DISCUSSION
7.5.1 MEASUREMENT RESULTS
Figure 65. Measured temperature distribution o f Sensor 1 at dc bias o f 20 mW.
Measurements obtained with the thermal imaging microscope were very useful in
improving the understanding of the power sensors’ operation.
In Chapter 6, we obtained
approximate values of average resistor temperature, as well as of the total thermal conductance
by observing the thermistor effect in the current-voltage characteristic. However, those values
were lumped for the entire termination area, and did not give any insight on the temperature
distribution on the heater, and its implications on linearity and sensitivity.
In Figure 65,
measured distribution for Sensor 1 at 20 mW is shown in a 3D plot of isotherms. The figure also
outlines the relative position and size of the sensor layout. As expected, the hottest points are in
approximate middles of each resistor, and the distribution is even symmetric across the middle of
signal conductor. This confirms the model setup with only Vz the structure simulated.
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120
110
100
oo
0i—
3
<0
0
Q.
e
0
h40
200
250
300
350
400
450
500
550
Position [pm]
Figure 66. Measured temperature distribution o f Sensor I along a-a’ cut in Figure 65 at dc bias o f 20
mW.
A cut in the surface of Figure 65 along a-a’, as outlined in the figure is shown in Figure
66.
This view shows the temperature decrease in the direction of the CPW ground and
thermocouples (to the left) from the hottest, center point on the heater. This rapid temperature
drop off on the left side shows the necessity of modeling the sensitivity as function of
thermocouple distance.
At the same time, this decrease is also directly influenced by the
thermocouple proximity, due to heat sinking effect.
Similarly, in the orthogonal plane cuts were made through the polysilicon resistors and
hot thermocouple junctions, b-b’ and c-c\ respectively. The two resulting plots are shown in
Figure 67. It can be seen that the temperature at the hot thermocouple junctions for this sensor
reaches roughly % of the maximum temperature found on the polysilicon resistors.
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110
Poly resistor
100
Hot junctions
oo
CD
3
CO
aC>L
E
CD
I-
50
100
150
200
250
300
350
400
450
500
Position [/mi]
Figure 67. Measured temperature distribution o f Sensor I along b-b’ cut (solid plot) and c-c’ cut (dotted
plot) in Figure 65 at dc bias o f 20 mW.
The measurements, however, must be interpreted carefully.
Namely, the miniature
dimensions of the sensor present a difficulty for the thermal microscope even at highest
resolution. Because the approximate pixel size is 10 jum, the measured temperature distribution
is significantly smoother than the actual distribution is expected to be. Nevertheless, the results
were very useful in fine-tuning the SPICE equivalent model, and gaining insight on device
operation.
When measuring the temperature distributions of Sensor 1, we applied three different
types of excitation at the input to verify the presence of “parasitic” thermoelectric effects.
Namely, we measured the temperature distribution for Sensor 1 with applied ac signal, positive
dc signal of equivalent power, and negative dc signal of that same power level. The result are
three curves of Figure 68. It can be seen in the figure that the temperature distributions are
notably different, especially in the middle of the device where two suspended aluminum-poly
junctions are found. These two junctions are strongly affected by Peltier heating and cooling. As
expected, the ac case gives average temperature value in the middle, the positive dc case gives
124
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higher temperature due to Peltier heating, and negative dc case gives lower temperatures due to
Peltier cooling.
140
120
o
O
)
<D
•
100
TJ
n>
2
<D
a.
E
(D
F
80
60
ac
positive dc
negative dc
40
20
0
50
100
150
200
250
300
350
Position y [pm]
Figure 68. Measured temperature distribution o f Sensor 1 along b-b' cut fo r three different types o f
excitation which shows the effect o f Peltier heating and cooling at aluminum-poly junctions.
7.5.2 MODEL RESULTS
After running the SPICE simulation on the equivalent electric representation of the
structure, we identified the nodes that belong to center cut through the polysilicon resistors, as
well as the nodes at the hot thermocouple junctions, since those two sets produce most of the
needed information for analysis. The modeled results were compared with measured ones. To
verify the model further, we simulated the system with convection and without convection, since
we could refer those results to the measurements of current-voltage characteristics in the vacuum
chamber. The comparison of model and simulations for the b-b’ cut through the sensor structure
of Figure 65, is shown in Figure 69.
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160
140
O
120
d
>
®
2,
<D 100
3
2
®
cl
E
®
H
80
60
Measured
Complete model
Model w/o convection
40
20
0
20
40
60
80
100
120
140
160
Position y [pm]
Figure 69. Compared results o f temperature distribution across one termination resistor arm for model
and measurement. With convection included in model, it matches measurements well.
In the figure, it can be seen that the modeled temperature distribution with convection accounted
for closely resembles the measured distribution. The main points of matching are the nearly
equal top temperature, and the distribution toward the middle of the signal conductor, where
temperature remains well above the substrate temperature, but is significantly colder than the
middle of the heater. On the other hand, there are some differences evident. Firstly, due to the
limited resolution of the thermal microscope, the measured temperature distribution shows
slowly decreasing tails and does not have sharp features the model predicts at material
boundaries. This is accompanied by the slightly different shape toward the peak temperature
which we attributed to “parasitic” Peltier and Thomson effects. The above comparison results, as
well as other similar comparisons nevertheless showed that this simple model could be utilized to
obtain information about the effect of parametric variations to optimize the device.
As mentioned earlier, and essential part in the optimization of the sensor is the heat
sinking effect of each thermocouple. To show this more clearly, we resort to simulations, as
significant temperature differences on <4 p m scale can not be resolved with the thermal
126
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microscope. Figure 70 shows the computed distributions for the same device structure, except
only a single thermocouple is integrated. The solid plot in the figure shows the temperature
distribution across the poly resistor and CPW connectors, as shown earlier, while the dashed plot
shows the temperatures in the line that cuts through the thermocouple hot junctions (in this case
one). Clearly, the significantly higher thermal conductivity of thermocouple materials (metal and
Si), compared to that of oxides, results in substantial temperature decrease at the very junction,
and therefore lowers the device sensitivity.
It can be seen in the results that placing of
thermocouples is a non-trivial problem, which requires this kind of analysis.
30
29
O
d)
28
25
Poly heater
Hot junctions
Power = 1 mW
24
0
20
40
60
80
100
120
140
160
180
Position y [pm]
Figure 70. Computed temperature distributions across the resistor and hot thermocouple junctions fo r
one thermocouple only.
Further, were interested in the effect of thermopile distance from the termination resistor.
At first glance it may seem that nearest is best, due to effectively ~ l/r type of temperature
decrease away from the heater.
However, we were already aware of at least two possible
detriments of very close proximity. One has to do with the broadband match of the termination
which looks like a 50 Q resistance to a microwave source in a very wide range of frequencies.
This is in part due to approximate 100 Q characteristic impedance (as well as 100 Q. resistance)
in each arm of the tee, as described in Section 2.3. That proper capacitance is established
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between the resistor in each tee and the adjacent ground plane. Hence, moving the thermopile
too closely would increase the capacitance in the arms and detune the termination from its best
match, as well as increase detrimental frequency dependence. The second possible detriment
was expected to be due to increase of thermal conductance with closer thermopile, and therefore
decrease of thermal efficiency (conversion of power to temperature difference).
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0
5
10
15
20
25
30
35
Distance Drt [pm]
Figure 71. Computed sensitivity as a function o f the distance o f hot thermocouple junctions from the
resistor.
The results in Figure 71 are plotted on a normalized scale with unity sensitivity for D„ of
12 /tm, as in the sensor for which results were reported in previous Chapters. The reason for
normalized plots in this
and subsequent figures is
to
simplify dealing with the
multidimensionality of the optimization problem, as well as to compare easily with the reported
sensor. As the figure shows, there is an actual optimum distance for the thermopile which trades
off the thermal phenomena, and would hopefully be compatible with electromagnetic
requirements. Maximum sensitivity could actually be achieved with a slightly closer thermopile,
namely 9 microns.
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A parameter which is understood to have an improving effect on sensitivity is the
suspended length of the thermopile. Namely, for increased Luus, the thermal conductance of the
thermopile decreases, and the sensor becomes more thermally efficient. This effect is shown in
Figure 72. Although significant, the effect nevertheless makes relatively small improvements,
asymptotically approaching twice the sensitivity for thermopile of many millimeters. This was
expected as well, since in the microwave sensors herein, the total thermal conductance is largely
dominated by large ground planes.
The effect is reported more significant in ac-dc
thermoconverters below a gigahertz [17] [62].
1.10
1.05
&
>
CO
c
<D
CO
*o
s(0
1,00
E
o
z
0 .9 5
0 .9 0
50
60
70
80
90
100 110 120 130 140 150 160 170 180
Distance
[pm]
Figure 72. Computed sensitivity as a function o f the suspended length of the thermocouples (N=I6).
The trade-off for the length is the very important signal-to-noise ratio. The effect of the increase
of thermopile resistance is seen in Section 2.5.2 to lower the SNR.
The resistance in the
thermocouples is dominated by polysilicon resistance, which for our sensors was roughly 6.8
Q/fim length.
Since a total of 24 thermocouples in series was utilized, the total resistance
entering into the calculation of SNR is 163.2
Q. The computed SNR is shown in Figure 73,
in convenient W 1 units. For the structure shown in Figure 23, the length is 85 //m, for which the
true computed 1 Hz bandwidth SNR at minimum input power of 1 pW reads 11.3. For Sensor 2,
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the total resistance of the thermopile (two series thermocouples) always remains 200 £2, as
depicted in Figure 8, and the computed SNR at minimum power is 21.2. In terms of SNR,
Sensor 2 performs consistently better than Sensor 1 due to the significantly lower series
resistance of the thermocouples, even though the sensitivity is 3-5 times lower.
1.6e+7
1.4e+7
1.0e+7
6.0e+6
50
60
70
80
90
100 110 120 130 140 150 160 170 180
Distance
[pm]
Figure 73. Computed 1 Hz bandwidth SNR fo r 24 thermocouples in series and sensitivity as computed by
model, as a function o f suspended thermocouple length Lao,.
We also performed a parametric variation on the number of thermocouples in series for
Sensor 1. The number was varied from 1 to 12 for Vt section, and sensitivity plotted in Figure 74
normalized with respect to the 24-thermocouple Sensor 1 reported on in previous Chapters. At
first in the plot, additional thermocouples significantly increase the sensitivity in an almost linear
fashion. This trend is changed at 14 thermocouples after which improvement is much slower.
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1.0
5
08
*35
c
<D
CO
T3
®
N
0.6
OS
§
O
0.4
0.0
2
4
6
8
10
12
14
16
18
20
22
24
Thermocouples in series
Figure 74. Computed sensitivity as a function o f the number o f thermocouples tightly distributed about
the center o f the resistor.
Nevertheless, the sensitivity continually increases, even though additional thermocouples
increase total thermal conductance. The overall performance effect is, however, not all positive.
Namely, the resistance increase with each additional pair of thermocouples significantly
decreases the SNR, as shown in Figure 75. Because the SNR plot was normalized to sensitivity,
the plot shows that there is an optimum number of thermocouples for Sensor 1, 14
thermocouples with SNR over 1.2xl07.
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l.3e+7
1.1e+7
1.0e+7
7.0e+6
5.0e+6
2
4
6
8
10
12
14
16
18
20
22
24
Thermocouples in series
Figure 75. Computed 1 Hz bandwidth SNR computed by model, as a function o f the number of
thermocouples N.
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CHAPTER 8 - CONCLUSIONS AND FUTURE WORK
8.1 CONCLUSIONS
We demonstrated the operation of thermocouple microwave power sensors, based on lowIoss transmission lines and broadband-matched terminations, in CMOS technology. The devices
were designed using standard VLSI CAD tools, fabricated in a commercially available CMOS
process, and were subsequently micromachined in a maskless post-process. This Dissertation
has therefore shown that microfabrication of integrated microwave transmission lines and sensors
in standard CMOS technology is feasible. Moreover, such fabrication is fully compatible with
standard IC processing, and can therefore be provided at low-cost and with no major changes to
present processing infrastructure.
Two different types of thermocouple sensors were fabricated and compared. First type
was based on indirectly-heated thermocouples, and the second type on directly-heated
thermocouples. In both cases, only the standard CMOS layers were used, i.e. oxide membranes,
aluminum, and polysilicon, and good results were obtained up to 50 GHz of frequency, which is
very exceptional in the context of CMOS.
In the first part of the work, microwave properties of coplanar waveguides on CMOSgrade silicon substrates were characterized and modeled.
It was shown that such passive
microwave structures are excessively lossy due to the induced transverse and longitudinal
currents in the relatively highly conductive substrate, and could not be used as building blocks
for microwave sensors and systems. It was therefore concluded that removal of the silicon
substrate is necessary in the vicinity of the microwave components to obtain efficient
components. The analysis in that section applies more generally to CPWs on lossy substrates and
will be useful in characterizing VLSI interconnects in CMOS. Similar analysis and approach
was used to design fully-suspended CPWs for integration with the power sensor. The analysis
further aids in defining the necessary etch depth to achieve complete electromagnetic isolation
from the underlying substrate.
Both types of sensors operate efficiendy up to 50 GHz. The indirecdy-heated device,
Sensor 1 measured highest sensitivity, up to 3.04 V/W, which slowly decreases with frequency to
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arrive at 2.22 V/W at 50 GHz. The sensitivity is approximately an order of magnitude lower than
that of previously implemented thermoconverters in CMOS which operate up to megahertz
frequencies. This was expected due to the trade-off in the design for microwave frequencies
which includes large ground planes and is adversely affected by placing thermocouples too
closely to the terminating resistor, and is therefore less efficient.
Thermal time constant o f both devices is -1.5 ms, which is sufficiently long for very
accurate measurements at frequencies well below 1 MHz. Throughout the 50 GHz frequency
range the devices’ input reflection is below —10 dB. Below 35 GHz, it is below -2 0 dB, both of
which are exceptional results for CMOS integrated components.
To achieve adequate thermal and electromagnetic isolation from the silicon substrate
while keeping the fabrication process very simple and as close as possible to standard CMOS, we
developed a post-processing methodology with two maskless etch steps: isotropic etch with
xenon difluoride, and anisotropic etch with EDP. The ultrasonically enhanced anisotropic etch,
following the isotropic etch undercutting significantly improves yield for less demanding
structures, and enables post-processing of more demanding etch structures previously impossible
to achieve.
8.2 FUTURE WORK
In the future, these devices will be integrated with CMOS circuits to achieve a number of
functionalities. Chopper-stabilized amplifiers will be designed and implemented to amplify the
thermopile output signals with very low bias error. The amplifiers will subsequently be followed
by sigma-delta A/D converters, and digital display circuitry.
The goal is to complete a
microwave power measurement system which is usually comprised of a separate sensor package,
cables, and a large control/readout box, on a single CMOS chip. This also requires research and
work on appropriate packaging for such a device.
Another important future direction is to integrate the power sensor with a broadband
micromachined antenna element, as well as other needed passive microwave components, and
implement a complete passive receiver at millimeter-wave frequency.
The application is
monitoring radiated power (EIRP) of a parabolic EHF antenna on US Navy submarines, to
ascertain whether proper power is outgoing from the satellite communication equipment
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onboard. Because the signals o f interest are very broadband, from roughly 42 GHz to 47 GHz,
with center frequency at 44.5 GHz, the application will require the broadband aspect of the
presented sensors, as well as a very broadband antenna element. The system on a chip that would
perform this function is outlined in Figure 76. The figure also shows a photograph of a recently
fabricated demonstration sample of this system. It consists of a CPW flare antenna directly
connected to a matching stub, band-pass filter, and the microwave power sensor (Sensor 1). In
Figure 76, the area of the chip where the sensor is placed is circled to show that it occupies the
smallest area, and also does not require back-side etching as seen for the larger microwave
components.
CMOS EIRP chip
Figure 76. System-on-a-chip EIRP measurement chip in CMOS, outline and sample photograph.
135
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This early version of the system which utilizes the work in this Dissertation must be improved
significantly before it is ready for production. However, some early measurements are shown in
Figure 77 which demonstrate that the chip indeed measures impinging radiation in the desired
frequency range, peaking at 33 GHz for this particular design.
ceo
CD
CO
30
32
34
36
38
40
42
44
46
48
50
F requency [GHz]
Figure 77. Recent measurements o f sensitivity vs. frequency o f the sample EIRP sensor chip shown in
previous figure. Measurements performed at SSC, San Diego, antenna range.
In general, the above and other future efforts will require a complete library of (and/or
methodology for designing) passive microwave components implemented in CMOS MEMS,
which can be integrated as needed in systems for various applications.
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REFERENCES
[1]
Hewlett-Packard Company, “Fundamentals of RF and Microwave Power Measurement,”
Application Note AN 64-1A, USA, Apr. 1997.
[2]
C. F. Coombs Jr. Electronic Instrument Handbook, McGraw-Hill, New York, 1995.
[3]
W. H. Jackson, “A thin film/semiconductor thermocouple for microwave power measurements,”
Hewlett-Packard Journal, vol. 26, pp. 16-18, 1974.
[4]
M. Klonz, “Current developments in accurate ac-dc transfer measurements,” IEEE Trans. Instrum,
and Meas., vol. 44, pp. 363-366, 1995.
[5]
L. P. B. Katehi, G. M. Rebeiz, T. M. Weller, R. F. Drayton, H.-J. Cheng, and J. F. Whitaker,
“Micromachined Circuits for Millimeter- and Sub-millimeter-Wave Applications,” IEEE Antennas
and Propagation Mag., vol. 35, no. 5, Oct. 1993.
[6]
W. R. McGrath, C. Walker, M. Yap, and Y.-C. Tai, “Silicon Micromachined Waveguides for
Millimeter-Wave and Submillimeter-Wave Frequencies,” IEEE Microwave and Guided Wave
Letters, vol. 3, no. 3, Mar. 1993.
[7]
J. C. Marshall, M. Parameswaran, M. Zaghloul, and M. Gaitan. “High-Level CAD Melds
Micromachined Devices with Foundries,”
IEEE Circuits and Devices Magazine, vol. 8, no. 6, pp.
10-17, Nov. 1992.
[8]
D. Jaeggi, H. Baltes, and D. Moser, “Thermoelectric AC Power Sensor by CMOS Technology,”
IEEE Electron Device Letters, vol. 13 (7), Jul. 1992.
[9]
V. Milanovid, “Design and Fabrication of Micromachined Microwave Transmission Lines in
Commercial CMOS Technolgoy,” Master’s Thesis, EECS Dept., The George Washington
University, Jan. 1997.
[10] V. Milanovid, M. Gaitan, E. D. Bowen, and M. E. Zaghloul, “Micromachined Microwave
Transmission Lines in CMOS Technology,” IEEE Transactions on Microwave Theory and
Techniques, vol. 45, no. 5, pp. 630-635, May 1997.
[11] N. H. Tea, V. Milanovid, C. A. Zincke, J. S. Suehle, M. Gaitan, M. E. Zaghloul, and J. Geist,
“Hybrid Post-processing Etching for CMOS-compatible
MEMS,” Journal o f
Microelectromechanical Systems, vol. 6, no. 4, pp. 363-372, Dec. 1997.
[12] V. Milanovid, M. Gaitan, J. Marshall and M. E. Zaghloul, “CMOS Foundry Implementation of
Schottky Diodes for RF Detection,” IEEE Transactions on Electron Devices, vol. 43, no. 12, pp.
2210-2214, Dec. 1996.
[13] J. R. Kinard, J. R. Hastings, T. E. Lipe, and C. B. Childers, AC-DC Difference Calibration, NIST
Special Publication, vol. 250-27, May 1989.
[14] K. C. Gupta,, R. Garg, I. Bahl, and P. Bhartia, Microstrip Lines and Slotlines, Norwood, MA,
Artech House, 1996
[15] C. Veyres and V. F. Hanna, “Extention of the Application of Conformal Mapping Techniques to
Coplanar Lines with Finite Dimensions,” Intemat. J. Electron., vol. 48, pp. 47-56, Jan 1980.
137
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[16] H-Y. Lee and T. Itoh, “Phenomenological Loss Equivalence Method for Planar Quasi-TEM
Transmission Lines with a Thin Normal Conductor or Superconductor,” IEEE Trans, on
Microwave Theory and Tech, vol. MTT-37, pp. 1904-1909, Dec. 1989
[17] D. Jaeggi, “Thermal Converters by CMOS Technology,” Doctoral thesis, ETH Zurich, Diss. ETH
No. 11567, 1996.
[18] V. Milanovid, M. Ozgur, D. C. DeGroot, J. A. Jargon, M. Gaitan, M. E. Zaghloul,
“Characterization of Broadband Transmission for Coplanar Waveguides on CMOS Silicon
Substrates,” IEEE Transactions on Microwave Theory and Techniques, vol. 46, no. 5, May 1998.
[19] V. Milanovid, M. Gaitan, E. D. Bowen, N. H. Tea, and M. E. Zaghloul, “Thermoelectric Power
Sensor for Microwave Applications by Commercial CMOS Fabrication,” IEEE Electron Devices
Letters, vol. 18, no. 9, pp. 450-452, Sep. 1997.
[20] V. Milanovid, M. Gaitan, M. E. Zaghloul, “Micromachined Thermocouple Microwave Detector by
Commercial CMOS Fabrications,” IEEE Transactions on Microwave Theory and Techniques, vol.
46, no. 5, May 1998.
[21] R. Collin, Foundations fo r Microwave Engineering, McGraw-Hill: USA, 1992.
[22] G. F. Engen and C. A. Hoer, “Thru-Reflect-Line: An Improved Technique for Calibrating the Dual
Six-Port Automatic Network Analyzer,” IEEE Trans, on Microwave Theory and Tech., vol. MTT27, no. 12, pp. 987-993, Dec. 1979.
[23] R. B. Marks, “A Multiline Method of Network Analyzer Calibration,” IEEE Trans, on Microwave
Theory and Tech., vol. 39, no. 7, pp. 1205-1215, July 1991.
[24] D. F. Williams and R. B. Marks, “Comparison of on-wafer calibrations,” 38fh ARFTG Cong. Dig.,
pp. 68-81, March 1992.
[25] D.F. Williams and R.B. Marks, “Accurate Transmission Line Characterization,” IEEE Microwave
and Guided Wave Letters, vol. 3, no. 8, Aug. 1993.
[26] D.F. Williams and R.B. Marks, “Compensation for Substrate Permittivity in Probe-Tip
Calibration,” 44th ARFTG Conference Digest, pp. 20-30, Dec. 1994.
[27] A. E. Ruehli and P. A. Brennan, “Accurate metallization capacitances for integrated circuits and
packages,” IEEE JSSC, vol. SC-8, no. 4, p. 289, Aug. 1973.
[28] C. Seguinot, P. Kennis, and P. Pribetich, “Desktop Computer Appraisal of Potential Slow-Wave
Propagation Characteristics for Schottky Coplanar Line”, Electronics Letters, vol. 19, no. 25, pp.
1065-1067, Dec. 1983.
[29] A. C. Reyes, S. M. El-Ghazaly, S. Dorn, M. Dydyk, and D. K. Schroder, “Silicon as a Microwave
Substrate,” Digest o f 1994 Microwave Theory and Tech. Symposium, San Diego, pp. 1759-1762,
May 1994.
[30] H. Hasegawa, M. Furukawa, and H. Yanai, “Properties of microstrip line on Si-SiC>2 system,”
IEEE Tran. Microwave Theory and Tech., vol. MTT-19. pp. 869-881, 1971.
[31] S. Zaage and E. Grotelueschen, "Characterization of the Broadband Transmission Behavior of
Interconnections on Silicon Substrates," IEEE Trans, on Components, Hybrids and Manufacturing
Tech. vol 16, no. 7, Nov. 1993.
[32] T. Shibata and E. Sano, “Characterization of MIS Structure Coplanar Transmission Lines for
Investigation of Signal Propagation in Integrated Circuits,” IEEE Trans, on Microwave Theory and
Tech., vol. 38, no. 7, pp. 881-890, July 1990.
138
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[33] E. Tuncer and D. Neikirk, “Highly Accurate Quasi-Static Modeling of Microstrip Lines Over
Lossy Substrates,” IEEE Microwave and Guided Wave Letters, vol. 2, no. 10, pp. 409-411, 1982.
[34] Y.R. Kwon, V.M. Hietala, and K.S. Champlin, “Quasi-TEM Analysis of ‘Slow-Wave’ Mode
Propagation on Coplanar Microstructure MIS Transmission Lines, ” IEEE Trans, on Microwave
Theory and Tech.., vol. MTT-35, no. 6, June 1987.
[35] C. Tomovich. “MOSIS - A Gateway to Silicon,” IEEE Circuits and Devices Magazine, vol. 4, no.
2, 1988.
[36] D. C. DeGroot, D. K. Walker, and R. B. Marks, “Impedance mismatch effects on propagation
constant measurements,” 5th IEEE Topical Meeting on Electrical Performance o f Electronic
Packaging, pp. 141-143, Oct. 1996.
[37] M. Ozgur, V. Milanovid, C. Zincke, M. Gaitan, and M. E. Zaghloul, “Quasi-TEM Characteristic
Impedance of Micromachined CMOS Coplanar Waveguides,” prepared fo r Trans, on Microwave
Theory and Tech., 1997.
[38] W. Heinrich, “Quasi-TEM description of MMIC Coplanar Lines Including Conductor-loss
effects,” IEEE Trans, on Microwave Theory and Tech., vol. MTT-41, pp. 45-52, Jan 1993.
[39] W. Hilberg, “From Approximations to Exact Relations for Characteristic Impedances,” IEEE
Tran, on Microwave Theory and Techniques, Vol. MTT-17, No. 5, pp. 259-265, May 1969.
[40] G. Ghione and C. U. Naldi, “Coplanar waveguides for MMIC applications: effect of upper
shielding, conductor backing, finite-extent ground planes, and line-to-line coupling,” IEEE Tran.
ofMTT, vol. MTT-35, no. 3, pp. 260-267, Mar. 1987.
[41] G. E. Ponchak, E. M. Tentzeris, and L. P. B. Katehi, “Characterization of finite ground coplanar
waveguide with narrow ground planes,” IMAPS Int. Journal of Microelectronics & Electronic
Packaging, vol. 20, no. 2, pp. 167-173, Feb. 1997.
[42] J. Bryzek, K. Petersen, and W. McCulley, “Micromachines on the march,” IEEE Spectrum, p. 20,
May 1994.
[43] R. F. Drayton, N. I. Dib, and L. P. B. Ketehi, “Design of Micromachined High Frequency Circuit
Components,” Int. Journal o f Microcircuits and Electronic Packaging, Vol. 18, No. 1, pp. 19-28,
1995.
[44] E. H. Klaassen, R. J. Reay, G. T. A. Kovacs, “Diode-based thermal r.m.s. converter with on-chip
circuitry fabricated using CMOS technology,” Sensors and Actuators A, Vol. 52, p. 33, 1996.
[45] D. Moser, R. Lenggenhager, H. Baltes, “Silicon gas flow sensor using industrial CMOS and
bipolar IC technology,” Sensors and Actuators A, vol. 25-27, pp. 577-581, 1991.
[46] M. Parameswaran, A. M. Robinson, D. L. Blackburn, M. Gaitan, and J. Geist, “Micromachined
thermal radiation emitter from a commercial CMOS process,” IEEE Electron Device Letters, Vol.
12, No. 2, p. 57, 1991.
[47] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1 GHz CMOS RF Front-End
IC for a Direct-Conversion Wireless Receiver,” IEEE J. Solid-State Circuits, Vol. 31, No. 7, p.
880, 1996.
[48] J. S. Suehle, R. E. Cavicchi, M. Gaitan, and S. Semancik, ‘Tin Oxide Gas Sensor Fabricated Using
CMOS Micro-Hotplates and In-Situ Processing,” IEEE Electron Device Lett., Vol. 14, No. 3, p.
118,1993.
139
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[49] F. I-J. Chang, “Xenon Difluoride Etching of Silicon for MEMS,” M.S. thesis, University of
California at Los Angeles, 1995.
[50] F. A. Houle, “A reinvestigation of the etch products of silicon and XeF2: doping and pressure
effects,” J. Appl. Phys., Vol. 60, p. 3018,1986.
[51] H. F. Winters and J. W. Cobum, “The etching of silicon with XeF2 vapor,” Appl. Phys. Lett. Vol.
34, p. 70, 1979.
[52] H. Seidel, L. Csepregi, A. Heuberger, and H. Baumgartel, “Anisotropic Etching of Crystalline
Silicon in Alkaline Solutions,” J. Electrochem., Vol. 137, No. 11, p. 3612, 1990.
[53] N. F. Raley, Y. Sugiyama, and T. Van Duzer, “(100) Silicon Etch-Rate Dependence on Boron
Concentration in Ethylenediamine-Pyrocatechol-Water Solutions,” J. Electrochem. Soc: SolidState Science and Technology, Vol. 131, No. 1, p. 161, 1984.
[54] O. Tabata, R. Asahi, H. Funabashi, K. Shimaoka, and S. Sugiyama, “Anisotropic etching of silicon
in TMAH solutions,” Sensors and Actuators A, Vol. 34, p. 51, 1992.
[55] L. M. Landsberger, S. Naseh, M. Kahrizi, and M. Paranjape, “On Hillocks Generated During
Anisotropic Etching of Si in TMAH,” J. Microelectromechanical Systems, Vol. 5, No. 2, p. 106,
1996.
[56] E. H. Klaassen, R. J. Reay, C. Storment, J. Audy, P. Henry, A. P. Brokaw, and G. T. A. Kovacs,
“Micromachined Thermally Isolated Circuits,” Solid-State Sensors and Actuator Workshop, Hilton
Head, South Carolina, Jun. 1996.
[57] S-S. Tan, M. L. Reed, H. Han and R. Boudreau, “Mechanisms of Etch Hillock Formation,” Vol. 5,
No. 1, p. 66, 1996.
[58] U. Schnakenberg, W. Benecke, and B. Lochel, “NHtOH-based Etchants for Silicon
Micromachining,” Sensors and Actuators, Vol. A21-A23, p. 1031, 1990.
[59] R. Lenggenhager, “CMOS Thermoelectric Infrared Sensors,” Doctoral Dissertation No. 10744,
Swiss Federal Inst, of Technology (ETH), Zurich, 1994.
[60] J. Y.-C. Chang, A. A. Abidi, and M. Gaitan, “Large Suspended Inductors on Silicon and Their Use
in a 2-|im CMOS RF Amplifier,” IEEE Electron Device Letters, vol. 14, no. 5, 1993.
[61] P. Kopystynski, E. Obermeier, H. Delfs, and A. Loser, “Silicon Power Microsensor with
Frequency Range from DC to Microwave,” 6th Int. Conference on Solid-State Sensors and
Actuators Technical Digest (Transducers ’91), San Francisco, CA, pp. 623-626, Jun. 1991.
[62] M. Gaitan, J. Kinard, and D. X. Huang, “Performance of Commercial CMOS Foundry-Compatible
Multijunction Thermal Converters,” 7th Int. Conference on Solid-State Sensors and Actuators
Technical Digest (Transducers ’93), Yokohama, Japan, 1993.
[63] F. I-J. Chang, R. Yeh, G. Lin, P. B. Chu, E. Hoffman, E. J. J. Kruglick, and K. S. J. Pister, “Gasphase Silicon Micromachining with Xenon Difluoride,” SPIE 1995 Symp. on Micromachining and
Microfab., Austin, Texas, 1995.
[64] S. Kodato, T. Wakabayashi, Q. Zhuang, and S. Uchida, “New Structure for DC-65 GHz Thermal
Power Sensor,” Proc. Sensors and Actuators Symposium (Transducers’97), Chicago, IL, Jun.
1997.
[65] M. E. Goff and C. A. Barratt, “DC to 40 GHz MMIC Power Sensor,” 12th Annual GaAs IC Symp.
Tech. Digest, pp. 105-108, Oct. 1990.
140
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[66] L. A. Christel and K. Petersen, “A Miniature Microwave Detector Using Advanced
Micromachining,” Tech. Digest, IEEE Solid-State Sens, and Actuator Workshop, pp. 144-147,
Jun. 1992.
[67] V. Milanovid, M. Gaitan, E. D. Bowen, N. H. Tea, and M. E. Zaghloul, “Implementation of
Thermoelectric Microwave Power Sensors in CMOS Technology,” Proceed. Int. Symposium on
Circuits and Systems - ISCAS’97, Hong Kong, pp. 2753-2756, Jun. 1997.
[68] V. Milanovid, M. Gaitan, and M. E. Zaghloul, “Micromachined Thermocouple Microwave
Detector in CMOS Technology, ” Proceedings o f the Midwest Symposium on Circuits and Systems
- Ames, Iowa, pp. 273-276, Aug. 1996.
[69] H. B. Callen, Thermodynamcis and an Introduction to Thermostatics, 2nded., John Wiley & Sons,
New York, 1985.
[70] J. J. Carr, Sensors and Circuits, Prentice-Hall, Inc, USA, 1993.
[71] P. Silvester, “TEM Properties of Microstrip Transmission Lines,” Proceedings o f I EE, vol. 115,
no. 1, pp. 43-48, Jan. 1968.
[72] N. R. Swart and A. Nathan, “Flow-rate microsensor modelling and optimization using SPICE,”
Sensors and Actuators A, vol. 34, pp. 109-122, 1992.
[73] G.C.M. Meijer, A.W. van Herwaarden, Thermal Sensors, Institute of Physics Publishing, Great
Britain, 1994.
[74] A. Rasmussen, L. E. Locascio, M. Gaitan, V. Milanovid and M. E. Zaghloul, “Characterization of
Standard CMOS Layers for Microfluidics,” accepted fo r presentation at IMECE'98 MEMS
Symposia, Anaheim, CA, Nov. 98.
[75] U. Bhattacharya, S. T. Allen, and M. J. W. Rodwell, “DC-715 GHz Sampling Circuits and
Subpicosecond Nonlinear Transmission Lines Using Elevated Coplanar Waveguide,” IEEE
Microwave and Guided Wave Letters, vol. 5, no. 2, pp. 50-52, Feb. 1995.
[76] M. Ozgur, V. Milanovid, C. Zincke, M. E. Zaghloul, “Characterization of Micromachined CMOS
Transmission Lines for RF Communications Applications,” submitted to IEEE Tran, on Circuits
and Systems.
[77] Ansoft Corporation, Maxwell 2D Field Simulator, http://www.ansoft.com/. 1997.
[78] Sonnet Software, Inc., High-Frequency 3D Planar EM Solvers, http://www.sonnetusa.com/. 1998.
[79] S. Middelhoek and S. A. Audet, Silicon Sensors, Academic Press Ltd., Bury St Edmunds, Suffolk,
UK, 1989.
[80] F. P. Incropera and D. P. DeWitt, Fundamentals of Heat and Mass Transfer, John Wiley & Sons,
Inc, USA, 1996.
[81] H. J. Goldsmith, Applications o f Thermoelectricity, John Wiley & Sons, Inc, New York, USA,
1960.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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