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Novel synchronization techniques and FPGA designs for RF/microwavetransceivers

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NOVEL SYNCHRONIZATION TECHNIQUES AND FPGA DESIGNS
FOR RF/MICROWAVE TRANSCEIVERS
by
Munir Ahmad Tarar
Submitted in partial fulfilment of the requirements
for the degree of Doctor of Philosophy
at
Dalhousie University
Halifax, Nova Scotia
February 2010
© Copyright by Munir Ahmad Tarar, 2010
1*1
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To comply with the Canadian Privacy Act the National Library of Canada has requested
that the following pages be removed from this copy of the thesis :
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Appendices
Copyright Releases (if applicable)
This work is dedicated to my respected parents: mother Khurshid Begum and father
Muhammad Sharif; caring brother: Shabbir Ahmed; and my loving wife: Nazia Munir,
for giving me unlimited love, support and encouragement. May their lives be full of love,
health and happiness.
iv
TABLE OF CONTENTS
LIST OF TABLES
viii
LIST OF FIGURES
ix
ABSTRACT
xiv
LIST OF ABBREVIATIONS USED
xv
ACKNOWLEDGEMENTS
xvi
CHAPTER 1
INTRODUCTION
1
1.1 The State-of-the-Art
1
1.1.1 Injection-Locked Techniques
2
1.1.2 Phase-Locked Loop (PLL) Techniques
6
1.1.3 Retrodirective Systems
8
1.2 Thesis Objectives
9
1.3 Thesis Contributions
10
1.3.1 Injection-Locked Oscillator and Its Applications
10
1.3.2 Design and Implementation of a New ADPLL
12
1.3.3 Design and Modeling of 4-Channel High Data Rate
Retrod i recti ve Transceiving System for Digital
Wireless Communications
12
1.4 Thesis Organization
CHAPTER 2
12
INJECTION-LOCKING TECHNIQUES
2.1 Introduction
14
14
2.1.1 Injection-Locking Phenomenon
15
2.1.2 The State-of-the-Art
23
2.2 An Injection-Locked Low-Noise/-Cost Oscillator
24
2.2.1 The Oscillator Circuit
24
2.2.2 Stability Analysis
26
2.2.3 Simulation Results
28
2.2.4 Measurement Results
31
2.3 An Injection-Locked Phase-Locked Loop for BPSK-to-ASK
Conversion
V
36
2.3.1 The Second-Harmonic Injection-Locked PLL (SHILPLL)
36
2.3.2 BPSK-to-ASK Conversion
2.3.3 Design and Simulation Results
2.4 An Injection-Locked Carrier and Coherent Demodulation
Receiver
40
43
46
2.4.1 Carrier Recovery using Injection-Locked Oscillator
(ILO)
47
2.4.2 The Proposed Direct Down-Conversion Receiver
Front-End Architecture Using ILO
51
2.4.3 Receiver Performances
52
2.5 An Injection-Locked Carrier for Multichannel DirectConversion Receiver
56
2.5.1 Dielectric-Resonator ILO (DRILO) Design
57
2.5.2 The Proposed Multi-Channel Receiver Architecture
Using DRILO
59
2.5.3 Receiver Performances
61
2.5.4 Discussions
64
2.6 Conclusions
CHAPTER 3 ALL-DIGITAL PHASE-LOCKING TECHNIQUES
64
67
3.1 Introduction
67
3.2 A Low-Cost All-Digital PLL: Design and FPGA
Implementation
68
3.3 Design
69
3.4 FPGA Implementation
74
3.5 Test Setup
75
3.6 Measurement Results
76
3.7 Conclusions
78
CHAPTER 4
RETRODIRECTIVE TRANSCEIVER SYSTEM
4.1 Introduction
80
80
4.1.1 Retro-Directive Antenna Arrays
81
4.1.2 Smart Antenna System
89
4.1.3 Summary of the Classical and Advanced Antenna
Arrays
90
vi
4.2 The FPGA-Based Retrodirective Transceiving System (RTS)....90
4.2.1 Revisit of Retrod i recti ve System Design Theory
91
4.3 System Design Specifications
92
4.4 System Architecture
93
4.5 System Modeling
97
4.6 Simulation Results
100
4.6.1 Automatic Gain Control Test
102
4.6.2 EVM Pattern Simulations
108
4.6.3 Performance Summary of the Simulated
Retrod i recti ve Transceiving System
118
4.7 Hardware Implementation of the Retrod i recti ve
Transceiving System
119
4.7.1 Hardware Used, Design Notes, and Signal Processing.. 119
4.7.2 Test Setup
122
4.8 Test and Measurement Results
123
4.8.1 Baseband (BB) Test
123
4.8.2 RF Downconverter MAX2701EVKIT and Baseband
Test
128
4.8.3 Baseband and RF Upconverter MAX2830EVKIT
132
4.8.4 A Complete Prototype of Retrod i recti ve Transceiver
System using RF/DC MAX2701EVKIT and RF/UC
MAX2721EVKIT
134
4.8.5 Discussion on RTS Pattern Measurements
148
4.9 Conclusions
148
C H A P T E R 5 S U M M A R Y AND P R O P O S E D FUTURE WORK
149
5.1 Summary
149
5.2 Proposed Future Work
151
BIBLIOGRAPHY
154
vii
LIST OF TABLES
Table 2.1 Comparison of the locking range of the converter
45
Table 4.1 Parameter settings for testing the retrodirective trasnceiving system (RTS)
with AGC - No impairments in the wireless channel
103
Table 4.2 Performance results of the retrodirective trasnceiving system (RTS) with
AGC - No impairments in the wireless channel
104
Table 4.3 Parameter settings for testing the retrodirective trasnceiving system (RTS)
with AGC - Impaired channel
105
Table 4.4 EVM pattern of retrodirective transceiving system (RTS) without phase
conjugation (channel frequency offset, foffset, of 1.200KHz, and noise
level, N , of 0.1)
114
Table 4.5 EVM pattern of retrodirective transceiving system (RTS) with phase
conjugation (channel frequency offset, foffset, of 1.200KHz, and noise
level, N , of 0.1)
115
Table 4.6 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 0i =0°
138
Table 4.7 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 6t = 10°
142
Table 4.8 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 6i = -30°
147
viii
LIST OF FIGURES
Figure 1.1 Circuit schematic of a second harmonic ILO [1-11]
3
Figure 1.2 Circuit block diagram of BPSK to ASK converter [1-11]
4
Figure 1.3 Circuit block diagram of ILO-based BPSK signal carrier recovery and
coherent demodulation [1-13]
5
Figure 1.4 Block diagram of mixed-mode carrier recovery in direct-conversion
receiver
5
Figure 2.1 General model for a free-running oscillator [2-3]
16
Figure 2.2 Free-running oscillator loop
16
Figure 2.3 Graphical representation of operating point of a free-running oscillator
17
Figure 2.4 Common model for injection-locked oscillator
18
Figure 2.5 Vectorial representation of injection locking phenomenon
19
Figure 2.6 ILO block diagram
20
Figure 2.7 Graphical representation of the injection locking
21
Figure 2.8 Impedance movement with variation of the injected frequency
22
Figure 2.9 Schematic of the proposed subharmonic ILO
25
Figure 2.10 Simulated frequency response of the free-running oscillator
28
Figure 2.11 Phase noise of the oscillator before locking
29
Figure 2.12 Simulated frequency response of the subharmonic ILO
30
Figure 2.13 Simulated noise of the injection-locked oscillator with different noise
levels present in the injected signal
31
Figure 2.14 Picture of the ILO Prototype Circuit
32
Figure 2.15 Test setup with oscillator working in the free-running mode
33
Figure 2.16 Test setup with oscillator working in the locked mode
34
Figure 2.17 Measured spectrum of the free-running oscillator
35
Figure 2.18 Measured spectrum of the subharmonic ILO
35
Figure 2.19 Circuit diagram of the proposed SH-ILPLL
37
Figure 2.20 Phasor diagram of the proposed SH-ILPLL
39
Figure 2.21 Block diagram of the proposed BPSK-to-ASK converter circuit built
using two SH-ILPLLs
41
Figure 2.22 ASK output of the converter built using two SH-ILPLLs
44
Figure 2.23 converter
ASK output of a SH-ILPLL circuit functioning as a BPSK-to-ASK
46
ix
Figure 2.24 15MSPS 8PSK modulated signal spectrum
50
Figure 2.25 Carrier recovered from the 2.1 GHz 20MSPS 8PSK modulated signal
51
Figure 2.26 Direct down-conversion receiver using ILO
52
Figure 2.27 I-Q constellation (not locked) recovered by the proposed receiver with an
input signal of 2.1 GHz 8PSK at 27MSPS
53
Figure 2.28 The I-Q constellation (not locked) recovered by the proposed receiver
with the input signal of 2.1 GHz QPSK at 130MSPS
54
Figure 2.29 The I-Q constellation recovered by the proposed receiver with the input
signal of 2.78 GHz QPSK at 160MSPS
55
Figure 2.30 The constellation of the input signal of 2.78 GHz QPSK at 160MSPS
55
Figure 2.31 Dielectric-resonator ILO (DR-ILO) Schematic Diagram
57
Figure 2.32 50MSPS QPSK 3.63GHz modulated signal spectrum and recovered
carrier signal
59
Figure 2.33 Direct-conversion receiver using selectable frequency DRILO
60
Figure 2.34 The I-Q constellation recovered by the proposed receiver with the input
signal of 3.63 GHz QPSK at 50MSPS (RF input and DRILO output
spectrum shown in Figure 2.32)
61
Figure 2.35 The I-Q constellation of the input signal of 3.63 GHz QPSK at 50MSPS
62
Figure 2.36 RF input and DRILO output spectrum (top) and the I-Q constellation
recovered (bottom) by the proposed receiver with the input signal of 3.58
GHz QPSK at 50MSPS
63
Figure 3.1 Matlab Simulink model of the ADPLL
69
Figure 3.2 Phase detector and loop filter
72
Figure 3.3 Simulation results of the ADPLL from MATLAB Simulink
73
Figure 3.4 (close view). Simulation results for the numerically controlled oscillator
( N C O ) outputs I_feedback
and Q_feedback
75
Figure 3.5 The ADPLL test setup
76
Figure 3.6 I-Q constellation transmitted with the input signal of 2.4 GHz QPSK at
16.272114KSPS (random data type PN23)
77
Figure 3.7 I-Q constellation recovered by the proposed ADPLL with the input signal
of 2.4 GHz QPSK at 16.272114 KSPS (random data type PN23)
77
Figure 4.1 Van Atta Array phase conjugation phenomenon
82
Figure 4.2 Block diagram for heterodyne phase conjugation concept
83
Figure 4.3 The block diagram of a basic retro-directive SILSOMs unit [4-6]
85
Figure 4.4 Block diagram of one-dimensional retro-directive antenna array [4-6]
86
x
Figure 4.5 Measured and calculated retransmitted radiation patterns of the retrodirective antenna [4-6] with illumination antenna at the incident angles of
(a) -30°, (b) -15°, (c) 0°, (d) 15°, (e) 30°, and (f) 45°
88
Figure 4.6 Sample smart antenna system [4-7]
89
Figure 4.7 Block diagram retrodirective system Base Station End_MAX2721EVKIT...94
Figure 4.8 Block diagram retrodirective system Base Station End_MAX2830EVKIT...95
Figure 4.9 Block diagram of retrodirective system Mobile User End or Source
96
Figure 4.10 Retrodirective transceiving system: source incident angle 6>, antenna
array orientation angle 0a and signal path phase offsets (pp], (pp2, (ppi,
and <pp4
97
Figure 4.11 Error Vector: Phase Error and Magnitude Error
99
Figure 4.12 Simulated performance results of the retro-directive transceiving system ..101
Figure 4.13 Test results of the retrodirective transceiving system with the AGC for a
signal power Pt of 1 .OmW transmitted from the source - Impaired
channel
106
Figure 4.14 Test results of the retrodirective transceiving system with the AGC for a
signal power Pt of 0 . 0 l m W transmitted from the source - Impaired
channel
107
Figure 4.15 RTS EVM results for cppl_DL, cpp2_DL , <ppi_DL, <pp4_DL =
90°,50°,-50°,-90°
Ill
Figure 4.16 RTS EVM results for <ppl_DL, yp2_DL,
<pp3_DL, q>p4_DL = 0°,0°,0°,0°
112
Figure 4.17 RTS EVM results for <ppl_DL, <pp2_DL, cpp3_DI, <pp4_DL =
- 9 0 ° -50°,50°,90°
113
Figure 4.18 Test results of the system, (ppX_UL, (ppl^UL, <Pp3.ul, (PP4-ul =
40°,20°,-20°,-40°, and <ppl_DL, <pp2„DL, <pp3_DL, <pp^DL =
90°,50°-50°,-90°
117
Figure 4.19 Test setup of 4-channel retrodirective transceiving system prototype with
MAX2721EVKIT RF-Upconverter
122
Figure 4.20 Test setup of 4-channel retrodirective transceiving system prototype with
MAX2830EVKIT RF-Transceiver
123
Figure 4.21 Measured results: BB Ch-1 output with input datatype 41s40s
124
Figure 4.22 Measured results: BB Ch-1 output with input data type 41s40s - Data
pattern observed locked (white strip in the bottom left quadrant)
125
Figure 4.23 Measured results: BB Ch-1 output with input data type PN23
125
xi
Figure 4.24 Measured results: BB Ch-2 phase conjugated output with input data type
PN23
126
Figure 4.25 Measured results: data type PN23 read from Scope at VSA software set
with a power range of negative 1 OdBm
127
Figure 4.26 Measured results: data type PN23 read from Scope at VSA software set
with a power range of negative 28dBm
127
Figure 4.27 Measured results: RF/DC-BB Ch-1 output with input data type 41s40s
129
Figure 4.28 Measured results: RF/DC-BB Ch-1 output with input datatype random
PN23
129
Figure 4.29 Measured results: RF/DC-BB Ch-2 phase conjugated output with input
datatype 41s40s
130
Figure 4.30 Measured results: RF/DC-BB Ch-3 phase conjugated output with input
data type random PN23
130
Figure 4.31 Measured results: RF/DC-BB Ch-4 phase conjugated output with input
datatype 41s40s
131
Figure 4.32 Measured results: BB-RF/UC output with input data type random PN23 ... 132
Figure 4.33 Measured results: BB-RF/UC output with input data type 41s40s
133
Figure 4.34 Measured results: Retrodirective transceiving system (one channel only) ..136
Figure 4.35 Measured results: Retrodirective transceiving system - Source incident
angle
= 0 and RTS transmission angle 0 a = 0°
136
Figure 4.36 Measured results: Retrodirective transceiving system - Source incident
angle Vt = 0 and RTS transmission angle 0a = 20°
137
Figure 4.37 Measured results: Retrodirective transceiving system - Source incident
angle q9i = 0 and RTS transmission angle 6a = - 2 0 °
137
Figure 4.38 Measured results: Retrodirective transceiving system (one channel only) ..139
Figure 4.39 Measured results: Retrodirective transceiving system - Source incident
angle 0, = 10° and RTS transmission angle Ga = 0°
139
Figure 4.40 Measured results: Retrodirective transceiving system - Source incident
angle 0t = 10° and RTS transmission angle 6a = 15°
140
Figure 4.41 Measured results: Retrodirective transceiving system - Source incident
angle Gt = 10° and RTS transmission angle 6 a = - 1 5 °
140
Figure 4.42 Measured results: Retrodirective transceiving system - Source incident
angle 6\ = 10° and RTS transmission angle Ga = -60°
141
Figure 4.43 Measured results: Retrodirective transceiving system - Source incident
angle 0, = 10° and RTS transmission angle 6 a = -85°
141
xii
Figure 4.44 Measured results: Retrodirective transceiving system (one channel only) ..143
Figure 4.45 Measured results: Retrodirective transceiving system - Source incident
angle 0, = - 3 0 ° and RTS transmission angle 0a = 0°
143
Figure 4.46 Measured results: Retrodirective transceiving system - Source incident
angle 0t = - 3 0 ° and RTS transmission angle 0a = 15°
144
Figure 4.47 Measured results: Retrodirective transceiving system - Source incident
angle 6> = - 3 0 ° and RTS transmission angle 0a =30°
144
Figure 4.48 Measured results: Retrodirective transceiving system - Source incident
angle 0, = - 3 0 ° and RTS transmission angle 0a = 45°
145
Figure 4.49 Measured results: Retrodirective transceiving system - Source incident
angle 0i = - 3 0 ° and RTS transmission angle 0a = -30°
145
Figure 4.50 Measured results: Retrodirective transceiving system - Source incident
angle 0i = - 3 0 ° and RTS transmission angle 0a = - 4 5 °
146
Figure 4.51 Measured results: Retrodirective transceiving system - Source incident
angle <9, = - 3 0 ° and RTS transmission angle 0a = - 6 0 °
146
xiii
ABSTRACT
Accurate wireless data transfers at hundreds of Mbps require high signal synchronization
speeds embedded in transceiving architectures. Many techniques have been developed in
the past and the right choices have become application specific. Along this line, this
dissertation first reviews the present synchronization techniques, and then proposes novel
injection-locked techniques, a new all-digital phase-locked loop developed using a low
cost FPGA, and a novel implementation of a retrodirective system for digital wireless
applications.
More specifically, the thesis consists of three parts:
Part I presents (a) a new low-noise injection-locked oscillator (ILO), (b) an injectionlocked phase-locked loop for BPSK signal demodulation with a wide locking range, (c) a
single-frequency ILO for 160MSPS QPSK detection, and (d) a frequency-selectable
dielectric resonator ILO-based coherent receiver for multi-frequency 63MSPS QPSK
signals. These techniques are distinguished from the classical ones by being fast and
simple.
Part II presents (a) the design of a new all-digital PLL (ADPLL), (b) its implementation
in a FPGA, and (c) an experimental demonstration in complete wireless transceiver
architecture. All math functions of the circuit algorithm are structured as sub-modules,
and the received data were passed through a timing recovery loop to reduce the BER. In
this way, ADPLL is easily implemented in a low-cost FPGA platform.
Part III presents the modeling and development of a novel digital retrodirective
transceiving system (RTS). Its distinction from a classical retrodirective array and
modern smart antenna systems lies in the fact that, in addition to having the capability of
retrodirectivity of transmitting signals back towards their source, it can be used to
demodulate and recover the digital information signal embedded in the modulated RF
carrier.
It is concluded that the above ILO-based techniques present creative approaches to signal
synchronization implementable in modern broadband digital wireless applications. Also,
FPGA-based baseband digital synchronization techniques are an excellent choice for
reconfigurable high speed intelligent wireless transceiving systems.
It is envisioned that a future system hybridized with these techniques will be a
breakthrough for wireless communications over 100s of Mbps. Characterizing and
developing such an efficient hybrid system are recommended future research directions.
xiv
LIST OF ABBREVIATIONS USED
ADC
Analog to Digital Converter
AGC
Automatic Gain Control
BB
Baseband
BL/BR
Bottom Left/ Bottom Right
BPSK
Binary Phase Shift Keying
DAC
Digital to Analog Converter
DF
Direction Finding
DL
Downlink (RTS to Source)
DSP
Digital Signal Processor
EVM
Error Vector Magnitude
FE
Front-End
FGS
Faculty of Graduate Studies
FPGA
Field Programable Gate Array
ILO
Injection-Locked Oscillator
ILPLL
Injection-Locked PLL
MSaPS
Mega Sample per Second
MSPS
Mega Symbol per Second
PLL
Phase-Locked Loop
QPSK
Quadrature Phase Shift Keying
RAA
Retrodirective Antenna Array
RF/DC
Radio Frequency Downconverter
RF/UC
RF Upconverter
RTL
Register Transfer Level
RTS
Retrodirective Transceiving System
SH-ILPLL
Second-Harmonic ILPLL
TL/TR
Top Left/Top Right
UE
User End or Source (or MU for Mobile User)
UL
Uplink (Source to RTS)
VGA
Variable Gain Amplifier
xv
ACKNOWLEDGEMENTS
The work presented in this dissertation is achieved with the generous help and
contribution from many people and institutions. It is the result of their ultimate
professional guidance, technical leadership, untiring efforts and financial support that
helped accomplish the set goals.
I would like to express my deep gratitude to my academic supervisor and companion, Dr.
Zhizhang (David) Chen, for his generous support and skillful coaching from many
aspects in my day-to-day grooming as a PhD candidate. I want to convey my warm
appreciation and applause to him in enhancing my research interests and motivation,
technical soundness and professional solidarity.
I am also in debt to Dr. Ezz El-Masry and Dr. Lagis Roy for always being available
whenever needed and for their valuable guidenaces and advice as my supervisory
committee members.
I would like to convey special thanks to former and current members or associates of the
Microwave and Wireless research Laboratory, Ji Sun, Adam Sampson, Dr. Hong
(Jeffrey) Nie, Dr. Iftikhar Ahmed. I am also very much thankful to the current members
of the Laboratory, Dr. Yiqang Yu, Profy Fernandes, Ryan Wilcox, Jet'aime Lowe, Chen
Wei, Scott Melvin, and Michael Christopoulos. Discussions and interactions with them
have not only been technically valuable for my research but have also made my life on
campus pleasant and enjoyable. In addition, my warm appreciation goes out to Chris Hill
and Mark LeBlanc in the departmental workshop for helping me build circuit/system
prototypes and test setups.
I would like to extend my special thanks to Dr. Jacek Ilow (Graduate Coordinator) for
helping recognizing my technical as well as volunteer contributions in the department,
and to Dr. Sunny Marche (Associate Dean, Faculty of Graduate Studies) for his expert
xvi
training in preparing a good thesis, building effective CVs, and guiding me towards being
an efficient and successful professional.
I would also like to say thank you to Selina Cajolais and Nicole Smith in the department
office for their friendly help in day-to-day correspondence matters such as for teaching
assistanship.
My family deserves a lot of recognition for getting me to this point. Without the prayers
of my respected father, Muhammad Sharif, and mother, Khurshid Begum, I would not be
able to achieve what I have achieved. I am grateful to my father for being an inspiring
example of how to get things done, and to my mother for teaching me to be honest and
decent both in my work and with people. My ultimate and heartiest appreciation goes to
my caring eldest brother, Shabbir Ahmed, and my loving wife, Nazia Munir, who
inspired me through their persistence, hard work and giving natures. Special gratitude
goes to my brothers and sister for sparing me from other family chores while I was busy
with my studies. Last but not least, I am obliged to my loving children, Juweriah, Rehmat
and Sumayah, who sometimes missed out on a warm hug before sleep.
The author would like to acknowledge financial support from the Atlantic Innovation
Fund administrated by the Atlantic Canada Opportunities Agency as well as support from
the Natural Science and Engineering Research Council of Canada.
CHAPTER 1
INTRODUCTION
The purpose of this chapter is to provide the background of the research work carried out
in this thesis, define the thesis objectives, and outline the thesis contributions as well as
the thesis organization. The first section of this chapter (Section 1.1) outlines a review of
the state-of-the-art synchronization and demodulation techniques and retrodirective
systems.
The next section (Section 1.2) provides the thesis objectives, while the
following section (Section 1.3) summarizes the thesis contributions. Finally, the last
section (Section 1.4) shows the organization of the thesis.
1.1
The State-of-the-Art
High data rates, wide signal bandwidths and wideband wireless communication systems
have developed as solutions to meet the unprecedented communication needs of current
and future societies. The driving force behind these is the continuous demand by private
and public sectors including industrial companies and governmental agencies for
communications and networking. Cost, weight, size, power consumption, complexity,
adaptability, and multi-mode/multi-band capability have thus become key factors for the
design success of a communication system's transmitter and receiver.
In a communication receiver, signal synchronization is an important component as it can
control the overall transceiver performance linked to many of the aforesaid factors for a
successful design. For instance, in an orthogonal frequency division multiplexing
(OFDM) receiver, channel estimation is critical and depends on the training symbols
embedded in OFDM data streams. The more of these symbols that can be estimated
accurately in a time variant channel, the better the bit error rate (BER) can be obtained;
however, this requires a high signal syncronization speed to lock to these training
symbols for better receiver performance.
In other words, for high data rate transmission and good receiving performance, fast and
accurate synchronization is required. There is a wide variety of state-of-the-art
synchronization and synthesis techniques to choose from, with more being worked on
every day. While the choices can be very application specific, these techniques can be
categorized in a number of ways. Our focus is on the facets of simplicity,
reconfigurability and retrodirectivity. Together with their current status and technical
challenges, these are described below.
1.1.1 Injection-Locked Techniques
Phase-locked loop (PLL) oscillators and modern direct digital synthesizers (DDS) are
components that can be employed in signal syncronization. However, PLL has relatively
slow acquisition speed, high power consumption and large phase noises [1-1], and DDS
has problems with nonlinearities associated with the digital-to-analog converter (DAC)
[1-2], Furthermore, both PLL and DDS systems are relatively complex in circuit
configurations.
Injection-locked oscillators (ILO) [1-3] [1-4] [1-5] have been used for many decades in
microwave synchronization. Injection locking is a process by which an injected signal of
related frequency locks a free-running oscillation. This process often reduces the phase
noise of an oscillation, which is a central figure of merit of any oscillator. The ILO output
signal phase noise constitutes partly of the phase noise of the free running oscillator and
the phase noise of the injected signal. Controlling the phase noise contribution of the
circuit itself is a challenge for a given application of the ILO.
Various ILO schemes [1-6] [1-7] [1-8] [1-11] have been developed to enhance the phase
noise and application performance, but they have respective disadvantages of application
limitations, high component count, and cost. An example normally built circuit from [111 ] is shown in Figure 1.1. The circuit has two transistors, two varactors and an inverter
transformer (two inductor coils) to form the basic structure of an ILO.
2
Figure 1.1 Circuit schematic of a second harmonic ILO [1-11]
For an ILO to be used in a RF front-end, a wide locking range for fast signal acquisition
and minimized phase noise for error reduced signal detection is required.
From a
practical design point of view, this is contradictory, as a wider locking range normally
needs a larger loop bandwidth, which usually lets through larger phase noises.
The ILO can be combined with self-mixing and PLL functions in the fundamentalharmonic injection-locked phase-locked loop (ILPLL) [1-9]. It consists of a low-pass
feed-back loop from output to input.
Consequently, it can have fast acquisition through
wide bandwidth but low noise due to injection-locked oscillations.
One of the important applications of the ILO schemes was the direct digital demodulation
that does not require an actual process of carrier recovery, leading to smaller number of
required components.
One approach was reported where two cross-coupled dual-
transistor second-harmonic ILOs (SH-ILOs) were used [1-10] [1-11]; in it, BPSK (Binary
Phase Shift Keying) signals were synchronously converted to ASK (Amplitude Shift
Keyiny) for detection. The circuit of the BPSK-to-ASK converter from [1-11] is shown in
Figure 1.2.
In Figure 1.2 the power divider at the left was used to split a received BPSK signal into
two parts. One part was used as input to the top second harmonic ILO (SH-ILO1) circuit
with a free running frequency greater than the locked frequency. Other part was used as
input to the bottom SH-ILO (SH-IL02) with a free running frequency lesser than the
locked frequency.
3
Figure 1.2 Circuit block diagram of BPSK to ASK converter [1-11]
It was shown that at each consecutive phase transition of 180 degree present in the input
received BPSK signal the two outputs one from each section combine once constructively
and the next time destructively. Thus a pattern of ASK would be generated at the output
of the power divider in the right hand side of the figure. However, the circuit was
complex and the locking range was not large. For instance, the locking range is maximum
10MHz in simulated results at 3.4GHz carrier [1-11].
To improve speed and reduce power consumption associated with the PLL, and to
mitigate the complexity and high cost associated with the complete digital systems, there
have been continuing efforts in exploring new ways to achieve signal synchronization or
carrier recovery. Carrier detection of PSK signals using nonlinear methods to generate
the 2/and 4/components was reported in [1-12], but only at the IF frequency of 70MHz.
Carrier recovery from BPSK signals at 1GHz was reported in [1-13]. The schematic
block diagram of this design is shown in Figure 1.3. The BPSK signal received is split in
to two parts: one part is sent directly to a mixer and the other part is used as an input to
the surface acoustic wave (SAW) ILO for carrier recovery. The recovered carrier this
way is multiplied in the mixer with the received signal to recover the data. It is
implemented in the analog domain for handling low bit rate (simulated at only 50kbps
BPSK) [1-13]. Further this design was tested for BPSK demodulation only.
4
SAW-ILO
Figure 1.3 Circuit block diagram of ILO-based BPSK signal carrier recovery and
coherent demodulation [1-13]
For QPSK signals, standard direct conversion receiver architecture is normally used and
is shown in Figure 1.4. (RF direct conversion itself is a quite mature technique for the
front end design and can be found in any wireless communications receivers' handbook.)
This architecture is implemented in mixed-signal domain where, based on the inphase, I(t), and quadrature, Q(t), signals received, a feed feedback signal is generated in
the digital domain to control the frequency of the VCO , output of which after filtering
out the harmonics and splitting into LO-I and LO-Q ( n i l phase shifted) is used to lock
on to the carrier frequency present in the modulated received RF signal. Then outputs of
mixers are low pass filtered to extract the baseband information signals. But the circuit is
very complex. Also, the latency in the mixed-signal loop becomes a major limitation to
handle wideband high speed signals, both single channel and multichannel.
Mix-Q
RF
Modulated
Sigial
Received
signal
nil
2-way
Divider
<SH
LPF
Amp
Q(t)
Base
Band
LO-Q
Phase
Shifter
BPF
DPLU
DOS
VCO
LO-I
RF
LPF
signal
Amp
1(f)
DSP
Mix-I
Figure 1.4 Block diagram of mixed-mode carrier recovery in direct-conversion receiver
5
1.1.2 Phase-Locked Loop (PLL) Techniques
Analog PLL: The phase-locked loop, classically implemented in purely analog domains,
is the best-known
and established
technique for signal
synthesis as well
as
synchronization in almost all types of communications transceivers. Over the years, many
developments have been made to keep up with modern system requirements, but these
still have certain limitations. They are briefly discussed as follows.
Analog/Digital PLL (DPLL): It is designed to work in the analog/digital mixed signal
domain. Simulating the mixed signal is a challenge, but equivalent behavioral models [116] are employed to resolve this issue. A DPLL consists of five major blocks: a phasefrequency detector (PFD), a charge-pump (CP), a loop-filter (LF), a voltage controlled
oscillator (VCO), and a frequency divider by ratio N. The error signal generated by PFD
is converted to a low frequency control signal by CP and LF. The VCO frequency is
adjusted by the control signal. Dividing this by N provides the required frequency for
comparison with the reference signal at the input of PFD.
While a DPLL can have a wide locking range of up to 15% of the carrier frequency, it
has poor phase noises that have a direct impact on bit error rate (BER). Adaptive PLL has
been implemented to reduce the noise at wider locking bandwidths [1-17] [1-18] [1-19]
but with increased power consumption and system complexities. A good settling time of
229jisec reported in [1-19] is still large which limits the achievable data rates. In addition,
achievable frequency resolution is also poor.
Direct Digital Synthesis (DDS): The DDS and all-digital PLL (described below) are
technically very similar and rely on high speed digital electronics like DSP and FPGA;
hence, frequency handling capabilities are also comparable and limited. The main
difference is that the output of the DDS, as in [1-20] [1-21], is normally a time domain
analog signal, unlike the numerical output of NCO in ADPLL. The DDS is primarily
used for synthesis purposes at the transmitter side. However, for the synchronization
6
needs it has been combined with PLL [1-22] but at the expense of higher complexity, cost
and power consumption, which surpasses the added benefits.
All-Digital PLL (ADPLL): This is designed to work purely in the digital domain. Phase
extractor, loop-filter and numerical controlled oscillator (NCO) are the main components.
In a phase comparator, the reference phase is compared with the phase of the signal from
the input and an error signal is generated. The loop filter gives the averaged error signal
to the NCO, which consequently can generate the required frequency signal locked to the
reference signal, as discussed in [1-23].
An ADPLL can be implemented on digital signal processors (DSP) or field
programmable gate arrays (FPGA) platforms to offer re-configurability. For better
performance using ADPLL, complex system designs and software routines have to be
configured in the receivers at baseband frequencies of maximum only around 1GHz
(FPGAs from Xilinx, Inc. and Lattice Semiconductor Corp.). With this, the acquisition
times are still poor, e.g. 50^isec [1-23].
In a receiver, a local oscillator signal was synthesized with the well-known phase lockedloop (PLL). However, there were issues with the conventional phase lock loop (PLL)
based systems: low speed and high noise [1-24] [1-25]; and with the adaptive PLL of
circuit complexity [1-17] [1-18] [1-19]. Later, digital techniques employing direct digital
synthesizers (DDS) were used, but these exhibited signal distortions and frequency
limitations associated with the systems [1-26]. The more recent and advanced
synthesizers combined PLL with DDS for better performance at the expense of greater
component counts and higher power consumption [1-27].
In summary, the present synchronization and synthesis techniques have poor phase noises
and low acquisition speeds. To meet modern demands for high data rates and wideband
applications with better performances, combinations of these can be made, but this
increases complexity and cost.
7
1.1.3 Retrodirective Systems
A retrodirective system can transmit signals back towards the sources originating the
signals. It has been implemented in analog domains using different techniques. Its
classical forms are designed not to demodulate and process the signal information; thus, it
can have only a limitated intelligence level.
Retrodirective systems work on the principle of phase conjugation, i.e. the signal
retransmitted from each element of its antenna array bears a phase conjugate relationship
with the signal received by that element [4-1]. In the following paragraphs, a brief
background of available retrodirective systems with corresponding limitations is
presented.
Classical Van Atta Array: This is a passive array based on the interconnecting
transmission line method and is comprised of a linear array of reflectors. Transmission
lines of equal lengths interconnect these elements [4-2]. However, this classical array
requires array symmetry, uniformity of wave front, and single frequency operation. To
partially overcome these limitations (e.g. wave front uniformity), antenna arrays using
heterodyne method can be used.
Heterodyne Array: The basic concept of the heterodyne array is that each element of the
antenna array takes samples of the incident wave front at various positions and then
mixes with a local oscillator that has double the frequency of the incoming signal [4-3].
The conjugated phase is then generated at each antenna element. The superposition of
these phase-conjugated signals and re-radiation of them produce a combined signal
traveling back towards the source. In this approach, a single frequency is operated on and
an external LO at twice the frequency rate is needed. In addition, all the antennas and
mixers must have the same behavior. Orthogonal or dual polarized antennas [4-1],
minimal frequency offsets, directional couplers or two-stage mixing [4-2] can be used to
improve isolation between receive and transmit signals with the same array.
8
Sub-harmonically Injection-Locked Oscillators (SILO) Array: The sub-harmonically
injection-locked oscillator (SILO) was introduced in [4-4], Using a balanced circuit
structure with sub-harmonically injection-locked self-oscillating mixers (SILSOMs) [4-5]
phase conjugation can be achieved. No external LO is required, and the output signal is
locked at the same frequency as the input signal [4-6].
The three types of arrays mentioned above can work as RF/Microwave signal reflectors.
However, they can be implemented in the analog domain only. The modulated RF signal
is not easy to be demodulated and baseband information is not easily recovered.
Smart Antenna System: To incorporate signal processing intelligence and to increase
system user capacity and reduce interference, smart antenna systems with a multiple
antenna array were developed [4-7]. The radiation beam from a smart antenna system can
be directed towards a target with a priori knowledge of its position or the beam can be
scanned at discrete angular intervals to estimate the direction of arrival of the signal. This
beam-forming functionality is heavily dependent on the software algorithms and
hardware used especially for their signal processing speeds; thus, the complexity and cost
of the system can be high.
1.2
Thesis Objectives
The overal objective of the thesis is to overcome the limitations of the existing
RF/microwave transceiving systems described in the previous sections by developing
new techniques
and devices for high speed signal reception,
synchronization,
demodulation and transmission.
More specifically, we focus on three aspects: 1) development of new injection-locking
techniques and their applications; 2) exploration of possible all-digital transceiver
architectures, and; 3) digital implementation of a multichannel retrodirective transceiver
system on FPGA platform.
9
Not only have theoretical studies been performed, but also the experimental work has
been carried out as much as possible.
1.3
Thesis Contributions
The thesis work has presented the original contributions that can be considered as the
further extension and combined applications of the concepts and ideas of injection-locked
oscillator, phase-locked
loop, superharmonic
injection and direct
BPSK-to-ASK
conversions, direct-down conversion receivers, digital PLL, phase conjugation, linear
antenna arrays, retrodirective transceiver systems, etc. The contributions of the thesis can
be divided into three parts:
(1) Simple injection-locked oscillation (ILO) techniques and their applications
(2) All-digital phase-locked loop (ADPLL) systems
(3) FPGA implementation of retrodirctive transceiving systems (RTS)
They are described in detail below.
1.3.1
Injection-Locked Oscillator and Its Applications
This part of the work can be further divided into the following parts.
1.3.1.1 A Simple Injection-Locked Oscillator
In this thesis, a new low-noise, low-component-count and hence low-cost, injectionlocked oscillator (ILO) is designed and presented. It also helps understand the injectionlocking concept [1-3] [1-4] [1-5] and provides an insight for further ILO extensions and
applications in the thesis. For this work, this thesis proposes a sub-harmonically
injection-locked oscillator that uses the low cost and low jitter HBT transistor. The
emitter of the HBT is loaded with capacitive feedback impedance and the base is loaded
10
with an inductive load. The resulting circuit is simple and has a low phase noise that is
almost the same as the injection signal generated by an external source. Since the external
source produces an injection signal that is half of the oscillation frequency, it can be
relatively easily developed. The test results for the developed prototype are discussed.
We also published the results in [1-29].
1.3.1.2 ILPLL for BPSK-to-ASK Converter with Enhanced Locking Range
The ILO capabilities of carrier recovery and tracking the digitally modulated RF signals
in its entirety in the case of BPSK signals was described in [1-1]. There, the carrier was
recovered and used for coherent demodulation of BPSK signals with limited locking
range at 1GHz carrier. The tracking capability of ILO was also used for BPSK-to-ASK
coherent conversion with limited locking range [1-10] [1-11].
This thesis, for the first time, extends the locking range of BPSK-to-ASK converter in [133] up to 20 times. The ILPLL discussed in [1-30] is modified and a second-harmonic
injection-locked phase-locked loop (SH-ILPLL) is designed. Then, the SH-ILPLL with
the BPSK-to-ASK converter in [1-33] to get enhanced locking range is combined. The
results have been published in [1-14].
1.3.1.3 ILO-Based Carrier Recovery and Demodulation Receiver for Single-Channel
OPSK Signals
Moving towards higher order modulation schemes, this thesis also presents for the first
time the synchronous demodulation of single-carrier QPSK signals using receiver
synchronizing signals recovered by ILO method, as discussed in [1-15]. ILO-based
carrier recovery and its use for QPSK demodulation at very high rates of up to 160MSPS
are presented.
1.3.1.4 ILO-Based Carrier Recovery and Demodulation Receiver for Multi-channel
QPSK Signals
11
This thesis further extends the ILO-based carrier recovery and demodulation scheme to
synchronous demodulation of multichannel QPSK modulated signals [1-31]. The carrier
is recovered from 3.58GHz to 3.68GHz QPSK signals of 50MSPS to 63MSPS, and the
coherent extraction of baseband IQ signals is shown with multi-frequency direct
conversion receiver architecture.
1.3.2
Design and Implementation of a New ADPLL
The analog domain ILO-based systems mentioned in sections 1.3.1 have the advantage of
being simple and high-speed. But they are not easily reconfigurable. For this purpose, in
this thesis, a new reconfigurable FPGA-based high-speed all-digital PLL is developed,
and testing in complete wireless transceiver architecture in the real wireless environment
is practically demonstrated and presented.
1.3.3
Design and Modeling of 4-Channel High Data Rate Retrodirective
Transceiving System for Digital Wireless Communications
For the first time, this thesis models, designs, and implements on a low-cost
reconfigurable FPGA platform a complete reconfigurable retrodirective transceiver
system (RTS) with high-symbol-rate signal demodulation and processing capability. Such
a system does not need prior knowledge of the target position and allows beamforming
and adaptability for high data rate wireless communications. After that, the hardware
implementation and experimental validation of the retrodirective transceving system
(RTS) is carried out, and recommended future research directions are outlined.
1.4
Thesis Organization
The thesis is organized in the following manner. Chapter 2 presents the new designs and
applications of injection-locked oscillators; they include (a) a simple low noise injectionlocked oscillator (ILO) circuit, (b) modeling and simulation of an second-harmonic
injection-locked phase-locked loop (SH-ILPLL) for BPSK to ASK conversion with
12
improved frequency locking range, (c) developments of ILO-based carrier recovery and
coherent demodulation of QPSK signals in direction conversion receiver architecture, and
(d) application of ILO-based carrier recovery for a multi-channel dierect-conversion
receiver. Chapter 3 covers the design of a new all-digital PLL (ADPLL), its
implementation on a low cost FPGA, and its testing in a real wireless transceiver
prototype. Chapter 4 describes a retrodirective transceiving system (RTS) with a fourelement patch antenna array for digital wireless applications and its new digital
implementation on a FPGA platform. Chapter 5 provides a summary and proposes future
work.
13
CHAPTER 2
INJECTION-LOCKING TECHNIQUES
The objective of this chapter is to develop new injection-lock oscillation techniques and
applications. The first section of this chapter (Section 2.1) describes the fundamental
theory of the injection-locked oscillation on which the research of this thesis is based.
Thereafter, each section (i.e., Section 2.2 to Section 2.5) presents new designs and'
applications of the injection-locked oscillations. Finally, the last section (Section 2.6)
summarizes the work presented in this chapter.
2.1
Introduction
An oscillating loop can be kept running and locked to an external signal injected into the
loop. It requires that the injected signal power level and frequency be within certain
limits of differences, so that the nonlinearity of the oscillating loop can adjust the loop for
these differences.
An injection lock is analogous to a swing in a park. Suppose the swing is already
oscillating; then, a person keeps politely pushing it at regular time intervals that are very
close to the swing period.
After a while, the swing will swing at the time intervals
pushed by the person - in other words, the swing is now locked into the swing-pushing
frequency of the person. Injection-locked oscillations work on a similar principle. A freerunning oscillator is injected with an external signal and, after a while, the oscillator will
oscillate at the frequency of this external signal.
In a wireless system, significant overhead is usually required for allowing reliable
recovery of the received signal parameters such as carrier frequency and phase,
transmitter clock and signal amplitude [2-1]. For example, the carrier recovery in a burst
data transmission system with a WLAN 802.1 lb standard is very critical. It is also vital
in point-to-multipoint TDMA reverse transmission, in ad-hoc TDMA wireless networks,
14
and in TDMA transmission over fast-fading channels [2-1]. Uses of the injection-locking
schemes are able to perform these functions.
The phenomena of injection-locked oscillations are well-known and have been
investigated by many researchers. Since an injection-locked oscillator can perform many
functions, such as FM or PM demodulation, frequency division and multiplication,
AM/PM conversion, and phase-shifting [2-2], amplification with limiting, frequency upconversion, frequency and phase modulation [1-1] [2-14], the injection locking technique
are expected to grow to meet the needs of the wireless communications market.
In the next few subsections, the fundamentals of the injection-locking are reviewed.
2.1.1 Injection-Locking Phenomenon
Injection Locking is a process by which an injected signal of similar frequency is tracked
and locked by a free running oscillator. When an oscillator is locked or synchronized
with an external signal, any transient disturbance will vanish with time, giving rise to a
steady state. This results in a constant phase difference between injected and oscillator
signals.
This concept was first presented by B. van der Pol [1-3] in the 1920s. Researchers
continued his work and, in 1946, R. Adler [1-4] defined the requirements for small-signal
injection locking and analyzed the locking phenomenon.
Later, in 1973, K. Kurukawa [1-5] came up with a distinguished extension, and analyzed
processes for both small-signal as well as large-signal injection locking. He also worked
on the resulting stability and oscillator noise.
In the following, we describe the theory of injection locking and the basic concepts
pertinent to injection-locked oscillations.
15
a) Free-Running Oscillators
An oscillator that operates itself without external influence is called a free-running
oscillator. A general model for a free-running oscillator is shown in Figure 2.1. It
contains nonlinear gain block '/', which depends on the output signal level ' v 0 ' and a
linear filter block ' / / ' , which is a function of loop frequency 'co'. According to the
Barkhausen Criterion [2-3], when the loop gain is unity and phase change around the
loop is zero or a multiple of 2n radians, it would oscillate and the output would be equal
to its natural frequency of oscillation ' eo N '.
v
products
n
/(V0)
{j
0
@ o
N
tv)
Figure 2.1 General model for a free-running oscillator [2-3]
The circuit model for this model is shown in Figure 2.2 [1-5], which is a freely running
oscillator at frequency cdn without any injected signal.
Z
M
Figure 2.2 Free-running oscillator loop
16
Here - Zd(A)
is the effective dynamic resistance of the nonlinear device (ref. b l o c k / i n
Figure 2.1) which depends only on amplitude lA' of the loop current ' / ' . Zd(A)
is not
frequency dependent because the locking-bandwidth under consideration is very small.
Zc (co) is the effective static impedance of the circuit passive components (linear filter
block H in Figure 2.1) and is linear but frequency-dependent. The loop equation for the
steady oscillation can be written as:
[Z»-Zrf(4]./ =0
(2.1)
Note: 'A' is taken as amplitude of the loop current, not of the voltage ' v 0 ' .
From (2.1), it can be observed that when Zd(A)
is equal to Zc (co), loop oscillations will
occur.
The impedance presentation for the oscillation can be sketched graphically as in Figure
2.3 [1-5]. Note that Zd(A)
reduces as the signal current amplitude increases from 0 to A,
i.e., it has negative dynamic resistance behavior.
i
•
Re Z
Figure 2.3 Graphical representation of operating point of a free-running oscillator
17
As can be seen, when Zc(co) intersects Zd(A)
, (2.1) is satisfied and steady-state
oscillation occurs. The real and imaginary parts of the loop impedance cancel each other
out and the loop oscillates at its natural frequency ' a>N ', which we can call the free-
running frequency of the oscillator 'co0' (i.e. co0 = coN).
b) Injection-Locked Oscillation
When an external signal is injected into a free-running oscillator, the oscillator can
become an injection-locked oscillator where the phase and frequency of the oscillation
currents and voltages are locked to the external injected signal. If the injected signal is
strong enough and fulfills the locking requirements of bandwidth and power, the
oscillator would be locked or synchronized with the injected signal.
In the following, we review the phenomenon of injection locking or more precisely
Quasi-Static Injection Locking, with discussion restricted to small-signal injection only,
for sake of simplicity. Further details on injection locking, such as Dynamic Injection
Locking and Large-Signal Injection, can be found in [1-5].
When a small external signal is injected, the mechanism of injection locking can be
depicted in Figure 2.4 [2-3], which is basically a free-running oscillator of Figure 2.1 but
with addition of injected signal, v,.
e
V 7 <a (%
praducts
m
y
H(jlti)
dl
Figure 2.4 Common model for injection-locked oscillator
18
Vq
@
ll)a
Suppose in Figure 2.4 | v ^ | « | v 0 | and the injected frequency, CDj, is very close to the
free-running oscillation frequen cy, a>0,. Then, the oscillator (generally with negative
dynamic resistance) is frequency-locked to the injected signal which is within the phaselock-bandwidth of the former. We see that this is a kind of fast amplitude limiting
mechanism because loop nonlinearity suddenly adjusts for the small power of the injected
signal.
If the injected signal, Vj , is zero, then output frequency is equal to free-running
frequency, COq , and if the Vj is not equal to zero, then output frequency, co, is shifted to
COj and this shift is proportional to Vj jV Q [2-4],
Figure 2.5 shows how complex signals vectorially combine [2-5],
Figure 2.5 Vectorial representation of injection locking phenomenon
In Figure 2.5, an injected signal voltage ' VINJ ', very low in level, shifts the phase of
oscillator loop. The injected signal interacts with the non-linearity of the device and the
loop adjusts for
<f>x
such that oscillation conditions (2.1) are met. (Note that free-running
loop signal VA is taken as a reference for phase.) Consequently, the loop is locked at
injected frequency ' a>!nj '. A locked oscillator would illustrate a constant angle
between oscillator and the impressed signals.
19
To get an insight on how locking actually happens, Figure 2.2 is re-drawn as Figure 2.6
with the addition of the injected signal source, E .
zc¥)
Figure 2.6 ILO block diagram
Now the loop oscillation equation can be written as below:
(2.2)
As signal E under consideration is small, therefore RF current amplitude would
approximately be the same as free-running amplitude. Thus if ' / ' i s taken as the noisefree oscillation amplitude A0 times some phase vector and <>
/ is taken as the phase
difference between E and I, then (2.2) can be written as below,
(2.3)
An
where, ' coj' is the injected frequency.
This means that, under the locking condition, the distance between Zc (o)j) and Zd (A) is
| E\/A0 with phase angle '</>". This locking condition can be sketched graphically, as
shown in Figure 2.7 [1-5].
20
We see that there are two points, one on each side, of the device line Z d (A) , which
satisfies (2.2). Vector relations are shown for both of them. The one on the right side of
circuit line Zc(co) with the dotted arrow corresponds to an unstable condition [1-5].
Thus, only the solid arrow, which we call the 'injection vector', is considered. The loop
adjusts for phase angle tf> and gets locked with the injected frequency ' a>i '.
The largest distance between the injected frequency 'coi ' and the free-running frequency
'<» 0 ' of the oscillator without losing synchronization is called locking bandwidth 'Aa>0 '.
The total locking range would be double of the locking bandwidth as ' coi' can equally
vary on both sides of 'oj0 '.
The locking bandwidth ' Aco0' is related to both the quality factor 'Q' of linear element of
the oscillator loop (i.e. filter block H) and the injected signal voltage E (i.e. Vj =E and let
denote v 0 as E0 in Figure 2.4). When Zd (A) becomes greater than '\E\/A0'
below ' <y,'
and above ' co2', the relation of (2.3) is not satisfied any more and locking cannot happen.
From ' cox ' to ' a>2 ' phase ' (f> ' changes approximately 180°. Maximum Locking
21
Bandwidth ' A o 0 m a x ' is discussed in [1-1] and is given by (2.4) below. Graphically, it
is shown in Figure 2.8.
Figure 2.8 Impedance movement with variation of the injected frequency
A co. m a x
,
2 e v
°
'
<2-4)
Vl-(v;/v0)2
Based on (2.4), to obtain a larger locking bandwidth, one can increase input signal
voltage Vj or reduce the quality factor Q. Also, the higher the operating frequency 0)Q ,
the greater the locking range (locking range is double the locking bandwidth). However,
the higher the natural frequency of the oscillator, the worse the temperature stability and
intrinsic FM noise of oscillator. A trade-off needs to be considered [2-6].
In terms of power, the injected signal power required is discussed in [1-1] is given as:
rP
i
~P
r
o
A con
(2.5)
K / 2 0 .
22
Here, P0 is the output power when the oscillator is in free-running mode. In addition, it is
assumed that v 7 / v 0 ( ( l .
If the impressed signal does not fulfill the above-mentioned requirements to injection
lock the oscillator, it can barely interact with the free-running frequency to produce beat
frequencies [1-4] near free-running frequency. This is called Threshold or Carrier
Recovery mode, which is of great interest for applications in wireless communications.
2.1.2 The State-of-the-Art
Various ILO schemes have been developed to enhance the phase noise performance [1-6]
[1-7] [1-8], but they have respective disadvantages of low power efficiency, high
component count and cost. For instance, in [1-8], a dual gate FET was used which can
cause more overheads (e.g. in terms of providing circuit connection to it) and eventually
will cost more. Hence, there is a need to develop simple low-noise and low-cost ILO
circuits suitable for applications in the modern wireless communication hardware.
The techniques where BPSK signals were synchronously converted to ASK for detection
are presented in [1-10] [1-11]. However, the circuits developed there were complex and
the locking range of the BPSK-to-ASK converter was not large. For instance, the locking
range is maximum 10MHz in simulated results at 3.4GHz carrier. More research is
therefore required on how to increase the locking range of the converter so that it can be
used for practical wireless applications where the requisite locking range can exceed
100MHz.
The injection-locked oscillator (ILO) technique, although researched for several decades,
is still in its infancy from a practical viewpoint. In spite of this, it still presents as a good
candidate for modern communication systems, as the injection-locking circuits can be
synchronized to the incoming signal and phase information can be extracted entirely in
the analog domain.
This could lead to the possible direct demodulation of digital
RF/microwave signals.
With a properly designed locking and dynamic range, digital
23
information contained in the RF/microwave signals can be converted directly down to
baseband for further processing. As a result, issues related to the low speed and high
noise of conventional-PLL based systems and distortion and frequency limitations of
pure digital-based systems can be resolved. In addition, the application of ILO scheme
for coherent demodulation of RF modulated signals has so far been limited to only BPSK
signals [1-28]. However, real world communication systems use not only BPSK but
QPSK and higher order modulation schemes. Therefore, extension of ILO to other
modulation schemes is a recommended research topic.
2.2 An Injection-Locked Low-Noise/-Cost Oscillator
In order to resolve the issues mentioned above, in this thesis, a simple 2.095GHz
subharmonically injection-locked oscillator (ILO) using an HBT (Hetero-junction Bipolar
Transistor) transistor is developed. A subharmonic signal of 1.0475GHz frequency is
injected into the oscillator to lock the oscillation at 2.095GHz. With the capacitive
feedback impedance at the transistor emitter, and inductive load and the resonator at the
transistor base, a low phase noise of - 9 2 dBc/Hz at the lOKHz offset was obtained.
Simulation results show that the phase noise of the oscillation output is only about 0.5dB
higher than that of the injected signal. In the following subsections, we will describe the
details of our oscillator design.
2.2.1
The Oscillator Circuit
The schematic of the proposed subharmonic ILO is shown in Figure 2.9. The heterojunction bipolar transistor (HBT-NESG2030M04) was used because its parameters fit
with our test prototyping requirements for proof-of-concept. NEC's lead style "M04"
package is of low profile and easy to mount on a PCD board. Also this transistor is
recommended by NEC for oscillator designs for mobile communication systems.
24
•K> •
-•O-C
-111-219/
-98.6-52.3/
T
33 + 523/
2200pF
Input
C
- t -
Output
2200pF
— o — ) |
B
stub
-J
HBT
E
NESG2030 MO 4
^g:
31.3nH
0.5pF
SOOhm
6.8nH
SOObm
lOOOhm > r
1.5pF
3.6nH
Resonator
oscillator loop
Figure 2.9 Schematic of the proposed subharmonic ILO
In Figure 2.9, a LC resonator, one transistor (HBT-NESG2030M04) and one feedback
impedance, ZF , form the basic free-running oscillator having a natural free-running
frequency of f0 (i.e., 2.095GHz in this case). The injected signal source impedance ZG
and load impedance ZL are both set to be 50 Q . For an oscillation to occur, a negative
RF resistance {Re ( - Zd(A))
in equation (2.1)) is required at either the base or collector
of the transistor. To achieve this, the capacitor in ZF impedance were adjusted such that
an impedance of - 9 8 . 6 - 5 2 . 3 / Q was obtained at the base of the transistor. An
impedance of - 1 1 1 - 2 1 9 / Q was obtained at the collector of the transistor. Transistor
output was matched to ZL through an inductor of 31.3nH and a matching stub of
quarterwave length as shown in Figure 2.9. The resonator impedance was adjusted so
that the total loop imaginary part was zero and the real part less than 98.6 Q to ensure
that start-on oscillation conditions were satisfied [2-7]. Total impedance, including the
25
resonator, looking from the transistor base towards generator is thus set to 33 + 52.3/ Q .
The resonator impedance helps stabilize the oscillation frequency at f0.
When the signal was injected, the transistor adjusted itself and locked to the double of the
injected frequency of fjnj (i.e., 1.0475GHz in this case, subharmonic injection locking)
according to the well-known theory of injection locking [1-5].
2.2.2 Stability Analysis
Suppose that the locking has been established and the steady state current / , at injected
frequency &>,(= 27tfinJ), is flowing into the base of the transistor. Let Vt be the weak
injected signal, and the effective impedance of the passive part of the oscillator loop be
denoted as Z(coi), with the active part denoted as Z(A), where A is the amplitude of the
current I . The impedance Z(<y,)is taken as 33 + 52.3/ Q which is being used to balance
the effective impedance of - 98.6 - 52.3/ Q at the input of the active device (HBT) shown
in Figure 2.19. Here, point to be noticed is that the negative resistance of - 9 8 . 6 Q starts
increasing towards 33 Q as discussed in the above section (Section 2.1.1) from the onset
of oscillation, through the transient stage, to the locking condition. The locking equation
can then be written as [1-5]
[ Z (Oj)-
Z(A)]I
=
(2.6)
Vr
Assume that I is perturbed by a small amount of current A/. If A/ decays with time, the
injected oscillation is stable. To determine the behavior of AI, suppose that / and AI
can be expressed as
/ = Aeja>i' andA/ = |A/|e y(<v+0
(2.7)
26
where cop and the magnitude of AI are slow varying functions of time compared to the
RF cycle. The currents I and AI add up vectorially in the case of injection locking. The
angle between I and AI is given by
O = (0pf+C-G>lt.
(2.8)
Since the magnitude of AI times cosO corresponds to the increase AA in the RF current
amplitude A due to AI, the perturbed equation becomes [1-5]
{Z(co) -[Z(A)
+ (dZ(A)ISA)
| A/1 cosO]}.(/ + A/) = V,.
(2.9)
The terms in the square brackets are the first two terms of the Taylor series expansion of
Z(A + AA). Neglecting the second order term in (2.9) and applying (2.6) to (2.8), one can
have the simplified equation:
[Z(a>) - K]AI = 0
(2.10)
where
K = Z(A) + (dZ(A)/dA) .(A^il
+ e2^"^"0)
(2.11)
The value of K varies with A but is considered as constant with respect to cop since it is
a slow varying function of time compared to RF cycle. Therefore, whether or not
AI decays with time could be determined by investigating the locus of Z(co). According
to the Nyquist stability criterion [1-5], AI decays if Z(co) (for co ranging from -oo to
+ oo) does not enclose the locus of K on the Smith chart. In other words Z{co) never
equals K and the term [Z{co) - K] do not diminish to zero but the perturbation A/.
This condition, for the proposed ILO, is achieved by adjusting capacitive feedback, ZF,
and inductive load in the resonator at the base of the transistor to ground. The simulation
27
results given below show that the oscillation conditions were met and that the oscillator
designed was found having stable oscillations.
2.2.3 Simulation Results
Agilent-ADS 2004a was used to simulate the proposed oscillator. First, the oscillator was
simulated at the natural frequency of 2.095GHz. The simulated frequency response of the
free-running oscillations without injection is shown in Figure 2.10.
3
o
(X
E
m
•o
6
8
10
12
14
16
freq, GHz
Figure 2.10 Simulated frequency response of the free-running oscillator
In Figure 2.10, oscillator output power (dBm, vertical axis) is plotted against some of its
prominent harmonic frequencies (GHz, horizontal axis). Each bar line represents a
frequency harmonic. The level of the natural frequency (marker m l ) is about 12dB higher
than that of the second harmonic frequency at 4.19GHz (marker m2). A strong second
harmonic signal present at the free-running oscillator output is very normal for oscillator
being a nonlinear device. A lOdB to 15dB below the fundamental signal is very practical.
The maximum the difference value the better the design is. In simulations, the oscillator
draws 11mA of current from a single 5V DC supply.
28
Figure 2.11 shows the simulated phase noise performance of the oscillator. Oscillator
output phase noise (dBc, vertical axis) is plotted against noise frequencies (Hz offset,
horizontal axis) occurring around the natural frequency. The slanting red line obtained
indicates that the larger the frequency offset, the better the phase noise, which is very
pragmatic. At lOKHz offset the carrier, the noise is found to be -87.24dBc/Hz.
1E1
1E2
1E3
1E4
1E5
1E6
F r e q u e n c y offset from carrier, Hz
Figure 2.11 Phase noise of the oscillator before locking
Next, a weak signal (-5dBm) of subharmonic frequency of 1,0475GHz was injected at the
input. An auxiliary generator (AG) method as described in [2-14] was used to simulate
this circuit. The oscillator was then found locked at 2.095GHz (the second harmonic of
the injected signal). Figure 2.12 shows the simulated frequency response of the
subharmonic ILO.
29
D
O
E
CO
x>
3
4
5
freq, GHz
Figure 2.12 Simulated frequency response of the subharmonic ILO
It is different from Figure 2.10 without the injection in two ways. First, the injected signal
now appears at the output and the power is more evenly distributed in harmonics.
Secondly, the difference between the signal level of 2.095GHz (double the injected
frequency as desired in a subharmonic ILO) and the level of any other harmonic is about
25 dB. This shows that oscillator is very stable and is also able to suppress the unwanted
signals successfully.
Figure 2.13 shows simulated phase noise performance of the injection-locked oscillator
with three different noise levels of the injected signal, -90dBc, -95dBc, and -lOOdBc,
each at lOKHz offset.
30
Output phase noise with injected signal
phase noise (atlOkHz offset) of:
1E1
1E2
1E3
-90dB c
-95dBc
-lOOdBc
1E4
1E5
1E6
Frequency offset from carrier, Hz
Figure 2.13 Simulated noise of the injection-locked oscillator with different noise levels
present in the injected signal
It can be seen that noise levels at the oscillator output are -89.47dBc, -94.47dBc, and 99.47dBc, respectively, each at lOKHz offset, respectively. They are only about 0.5dB
greater than those of the injected signal. This is perhaps due to filtering effects of the
capacitive and inductive components and the thermal noise of the HBT used. This fact
makes the proposed ILO distinguishable from the circuits reported so far in the literature
for phase noise reductions.
2.2.4 Measurement Results
A prototype of the oscillator shown in Figure 2.9 was developed on a general-purpose
substrate FR4 (er = 4.26). All component values are same as in Figure 2.9 except the
inductor of 31.3nH (with the output stub) was replace by a 27nH inductor (Part# 27NX-L
from CoilCraft). The oscillator design was carried out with the methodology described in
[2-7],
31
First, the oscillator free running frequency response was measured. It was found similar
to the simulated one shown in Figure 2.10. The oscillator drew a current of 11mA from a
5V DC supply, which is the same as predicted by the simulations. The circuit for the
prototype is shown in Figure 2.14.
DC Supply
Figure 2.14 Picture of the ILO Prototype Circuit
A test setup with an oscillator working in the free-running mode is shown in Figure 2.15
(prototype circuit connections as shown in Figure 2.14). Observe at the display screen of
the Agilent's ESG vector signal generator (bottom left in Figure 2.15) that RF output of
the generator is turned OFF (greyed out). The oscillator output is shown at the Agilent's
PSA Specrum Analyzer (center in Figure 2.15) display screen. A close view of the freerunning mode is shown in Figure 2.17.
32
Figure 2.15 Test setup with oscillator working in the free-running mode
A test setup with the oscillator working in the locked mode is shown in Figure 2.16
(prototype circuit connections as shown in Figure 2.14). Observe at the display screen of
the generator (bottom left in Figure 2.16) that its RF output is turned ON (dark black).
The oscillator output is shown at the Agilent's PSA Specrum Analyzer (center in Figure
2.16) display screen. A closer view of the locked mode is shown in Figure 2.18.
Figure 2.17 shows the measured spectrum response in the free-running case. With a
frequency span of 5.946MHz, it is observed that the output signal is not very stable and
the phase noise performance is very poor. Measuring the phase noise at a close frequency
offset was difficult due to the continuing drift and instability of the frequency.
33
Figure 2.16 Test setup with oscillator working in the locked mode
Nevertheless, the phase noise performances observed are different than the simulated
ones (Figure 2.11). The differences can be attributed to difficulty in accurate modeling of
HBT in simulations (transistor nonlinear models from component vendors imported into
ADS can differ from the actual transistor used on board), poor tolerances, Q-factors of
the components used, cross talks between signals from input and output signal tracks on
the prototype board, and fabrication errors in developing the prototype.
Next, a weak signal (OdBm) of 1GHz frequency was injected. Locked oscillator
frequency response was found similar to the simulated one shown in Figure 2.12. Figure
2.18 shows the measured spectrum of the prototype.
34
Agilent 21:56:23
Jan 13, 2 1 6 1
Figure 2.17 Measured spectrum of the free-running oscillator
Mkrl
Rat « d&m
Norm i
Log
i
fltten
~T
1 0 dB
1.999 9 r i9
GHz
- 6 . 5 1 dBm
'
18
Systeii,
dB/
ftgntr^nts.
Align fill Now. N^edee
Marker
1.999999900 6Hz
L-jflv - 6 . 5 1 dBm
HI <•>
S3 F1
fH
Crf):
K501
i
h/w-'IA
Cent-r 2 m® i M W GHz
Res DH 18U Hz
VBN 180 Hz
Span 20 kHz
Sweep 257.7 ms (601 p t s )
Figure 2.18 Measured spectrum of the subharmonic ILO
35
The output frequency is well stabilized in the spectrum and phase noise is reduced to
about -92dBc at an offset of 10kHz (phase noise of the injected signal was measured as 92.55dBc at 10kHz offset, in this case). The improvement of more than 20dB in phase
noise was obtained in comparison with the free-running oscillation (see Figure 2.17). Due
to the limit of our testing equipment, we were not able to set up different noise levels for
the external source. Therefore, the oscillator could not be tested with different noise
levels in the injected signal. However, in light of the above results, it is believed that the
prototype should behave in a similar way as that shown in Figure 2.13.
2.3 An Injection-Locked Phase-Locked Loop for BPSK-to-ASK Conversion
In this section, the injection-locked phase-locked loop (ILPLL) is explored for the first
time for the BPSK-to-ASK coherent conversion. Two circuit architectures are proposed,
one using two second-harmonic ILPLL (SH-ILPLL) and the other using a single SHILPLL. In the case of the two SH-ILPLL version, feedback loop amplifiers are used and
an increase of 20 times in the locking range of the converter is achieved. In the case of
the single SH-ILPLL, direct BPSK-to-ASK conversion is also achieved but found with
smaller locking and dynamic ranges. However, it is very simple and easy to develop.
With the addition of an envelop detector, both circuit architectures can be used as a
complete and compact RF front-end receiver that can direct demodulate digital
RF/microwave signals without many intermediate components and devices. Such a lowcost and low-complexity receiver can be employed in many wireless applications such as
RFID and sensor networks.
2.3.1 The Second-Harmonic Injection-Locked PLL (SH-ILPLL)
The fundamental-harmonic ILPLL was proposed and discussed in [1-9], while the
second-harmonic injection-locked oscillator (SH-ILO) was discussed in [1-10] [1-11].
Here, for the first time, a simple SH-ILPLL is proposed and its schematic diagram is
shown in Figure 2.19.
36
loop
j
_amplifier
voltage gain p
m
V
cc
-
Rrcc
(/, = 2/,)
uQ
injected signal
Vt = ACosdnft
+ V) ^
Vloop*apCos(V-2<p(t)+<&)
RF short
)b
O
Q
- y
Vul
output signal
= AoutCos{2nf\t +
BJTVCO
V0 = A^Cos(2nf4 +
„ „ , reference
DC feed
+
Varactor
)
voltage
mm
Figure 2.19 Circuit diagram of the proposed SH-ILPLL
The BJT VCO in Figure 2.19 is the oscillator which, in the free-running case, can have
output signal
V0=A0Cos(2xf0t
(2.12)
+ {?')
where A0 is the output signal voltage amplitude, / 0 is the free-running frequency,
and # is instantaneous phase angle of the oscillator signal.
In Figure 2.19 the loop-
amplifier has a voltage gain of /?.
Now, let the injected signal is
V,=A,Cos(27flt
+ W),
(2.13)
and the oscillator output signal is
Vout=Aou,Cos(27rflt
(2.14)
+ (p(t))
37
where Ai and Aout are the injected and oscillator output signal amplitudes, respectively.
/ is the injected signal frequency and fl is the output frequency of the oscillator in the
locked state.
The phase
is the phase of the injected signal and (pit) is the time
dependent phase of the oscillator output signal which takes into account the development
of the oscillator frequency from the free-running to the locked state. This means that at
t = 0, 2rfl = d<p(t) / dt + 27f0.
It is well known [1-28] that the locking range of the ILO (no feedback loop) is given as
A«,=K/20*(4M)
(2-15)
where Q is the quality-factor of the VCO resonator circuit.
Now, with the loop, the low-frequency mixing product at the loop- amplifier output can
be approximated as
Vhop * afiCosW
where a = -RCCICCA0AI
- 2<p(t) + <D)
/V^.:{ON) , Rcc
(2.16)
is the collector bias resistance, and Icc
and
VBE{ON) are the collector current and turn-on voltage of the transistor, respectively. O is
the phase term that includes phase shift from emitter to collector (trasnsister is used in
common-base topology: emitter is input, collector is output) and any phase shift around
the loop.
This could be determined empirically if accurate nonlinear models are not
available for the device [1-9].
Figure 2.20 shows how the injected, free-running and loop signals act together vectorially
to form the steady-state output signal.
38
Suppose K0 is the VCO tuning sensitivity. Then, after some mathematical manipulations,
an equivalent Adler's equation [1-4] for the SH-ILPLL can be written as
dO{t) / dt = Aco0 - Aa, sin <9(0
(2.17)
0(0 = 2 ^ ( 0 - ^ - 0 ' ,
(2.18)
where,
Aco0 = 2o0 - =
2*2^-2*2^
=>Acoa = 4tt(/ 0 - / , ) ,
Aa, = yj(2 apK^f
+ (Aa>,)2 + 4a/3KaAo)l sinO
(2.19)
(locking range with the feedback loop)
(2.20)
_lr
2a/3K0 cos O
O = tan [ — ^ 0
].
Aco, + 2a/3K 0 sin O
(2.21)
and
Because of the fact that O is the phase of the low frequency feedback signal, its
dependence on time can be considered negligible when compared to 6(t) or (pit).
39
With
this assumption, i.e.,
~ 0 > analysis of SH-ILPLL becomes similar to SH-ILO as in
[1-10] with the difference that A co, being replaced by A co,; this in turn ensures that
locking range of SH-ILPLL can be larger than SH-ILO.
In the steady state, dO(t)/ dt = 0 and 6(t) can be denoted by 6S as the steady-state phase
angle. The solutions of (2.17) are two fixed values given by
9S =sin _ 1 [Affl 0 /Affli],
and
(2.22)
Om — u — 0S.
(2.23)
As a result, 0S can vary between - n 12 and n 12 .
Also, maximum locking range
IAco
as
I un II maxis given
°
224
(-)
KLxHH
where A co] is given by (2.20) and is directly proportional to the injected signal amplitude
and inversely proportional to the Q of the oscillator resonator circuit through Aco,. To get
Aco] > A co,, one can set j3 > -2 Acd, sin&/aK0
in (2.20).
2.3.2 BPSK-to-ASK Conversion
a) The conversion using two SH-ILPLLs
From (2.18), it is clear that the differential phase change in <p(t) will be half of that
in 6(t).
Now consider an input signal with the phase of ¥ . With a phase change of n
i n 1 ? , 6s will change to 6S + n that will cause a differential phase change AO of n in
6(t); in turn, it results in a differential phase change Acp of n 12 \ncp(t).
40
By using the above results, a converter using two second-harmonic injection-locked PLLs
is proposed, as shown in Figure 2.21.
SH-ILPLL-1
loop amplifier
S H - I L O X
BPSK
foi>f,
v m
Vn
power divider
Ml 1
ASK
Val@fi
S H - I L 0 2
/02
< fl
'•jjower combiner
loop amplifier
SH-ILPLL-2
Figure 2.21 Block diagram of the proposed BPSK-to-ASK converter circuit built using
two SH-ILPLLs
The top PLL is with / 0 = / 0 1 > f
(i.e.,0 < 0S <nl2,
using (2.22)) and the bottom PLL
is with / 0 = / 0 2 <.// ( i . e . , - n i l < 0S < 0 , again using (2.22)).
signal at / = 2 ft
power divider.
Assume that a BPSK
with certain data rate is input to both oscillators through a balanced
Then, as in BPSK signal T changes in n , A<p = 7t/2 for the first
oscillator and Acp = - 7 r / 2 for the second oscillator are generated.
For instance,
when0 sX = n t A , 0 s 2 = - n l 4 , ^F = n and O' = ^ / 2 , ( 2 . 1 8 ) gives
<psl = 0J2 + 3tt/4 , and cps2 = 0 J2 + 3tt/4 .
The signals at the oscillators' outputs can be written as
41
(2.25)
Voun = A, zxp(j(2nf,t
+ GJ2 + 3/r/4))
(2.26)
Km2 = A exp(j(2rf;t
+ 6J2 + 3?z/4)).
(2.27)
As the outputs of the two oscillators are combined at the end, an output signal with a
magnitude of
KI
= A-J2 yjl + cos((# sl - 0s2 ) 12)
(2.28)
then results.
If there is a differential phase change of n in T , the outputs of the oscillators can be
written as
Voun = A, exp<J(2af,t + 0J2 + 3^/4 + jd2))
(2.29)
Vout2 = A, e x p ( j ( 2 ^ r + 6J2 + 3 ^ 4 - a/2)).
(2.30)
An output signal with a magnitude of
\Km | = A
-y/l - cos((^ Jl - 0 s 2 ) / 2)
(2.31)
then results.
Equations (2.28) and (2.31) show that the outputs of the two SH-ILPLLs add either
constructively or destructively.
change of n in
In other words, each consecutive differential phase
will result in an ASK signal at the output, completing the BPSK-to-
ASK conversion.
With the conversion scheme described above, advantages of both an enhanced locking
range as depicted by (2.20) and direct BPSK-to-ASK conversion are both utilized,
leading to a system of potentially better performance.
42
b) The conversion using one SH-ILPLL
The BPSK-to-ASK conversion can also be completed with the use of a single secondharmonic injection-locked PLL. Consider a converter that is made of the circuit shown in
Figure 2.19. By careful selection of the DC feeds, in the range of 70nH to 470nH, ASK
signals can also be obtained.
A simple analysis can be made as follows. Consider that the SH-ILPLL is locked at
/ ; ( > / o ) a t steady-state. Now with a transition of n in
, two independent and equal in
frequency but opposite in phase self-mixing products will appear at the circuit output.
First, f , appears at the output with a differential phase shift of - n / 2.
Secondly, the
oscillator itself attempts to oscillate at f0 while producing floop = f , - f0.
shift around the loop is adjusted through the loop-amplifier to n/2,
If the phase
this floop can again
mix with / 0 to produce ft at the circuit output but with the phase of n 12.
These two
ft components can generate constructive and destructive interference at the output at each
next input phase transition, resulting in an ASK signal.
2.3.3 Design and Simulation Results
a) Design
For the SH-ILPLL, a basic VCO circuit was designed using a microwave NPN transistor
AT41411 in the common base configuration (NESG2030 can be used as well).
A
varactor with a large tuning range was used, since a free-running frequency range of the
oscillator can be a factor that limits the locking range of the ILPLLs and hence the
BPSK-to-ASK conversion. The loop amplifier was constructed using a high frequency
NPN transistor 2N3904.
DC voltage gain of the loop amplifier is 12dB and 3dB
bandwidth is 40MHz.
43
The converter using two SH-ILPLLs was constructed in parallel, as shown in Figure 2.21.
The injected signal was split equally and then fed to each of the two SH-ILPLLs. The
outputs were combined using a balanced power combiner. To create a good isolation
between the outputs of the divider at injected frequency f\ and inputs of the combiner at
half the injected frequency (i.e. / , ) , the source and load ports of the circuit had to be
properly matched [2-8]. If not, mutual coupling of both ILPLLs will occur, and they can
start oscillating at their fundamental or second harmonic frequency instead of being
locked to the frequency of the injected signal.
For the converter using single SH-ILPLL, parameters of the loop-amplifier such as gain,
bandwidth and especially DC feed inductors, were carefully adjusted in order to obtain
ASK at the circuit output.
b) Simulation Results
Results with the two SH-ILPLLs are shown in Figure 2.22. The input signal is 2Mbps
3.4GHz BPSK signal. As the settling time is around 50nsec, the theoretical data rate can
be 10Mbps. Bits shown in the Figure 2.22 are 00010110. This ASK signal can be easily
detected by a simple envelop detector.
>
a
oo
111 111
111 1111 11111
11111j 1111
| 1111j 1111
1111111
1111| 1111
11111
—1111
1 111
1111111
D5 1fl
2X1 25 3fl 35 I
time (|j,sec)
Figure 2.22 ASK output of the converter built using two SH-ILPLLs
44
Result comparisons for the locking range of the proposed conversion circuit with and
without the loop-amplifiers are tabulated in Table 2.1. First, the feedback loops were
removed and the circuit biasing conditions were adjusted to fit with those of the
measurements. Then the loops were put back properly so that the biasing conditions are
not disturbed.
From the results, it is clear that, with the loops, the locking range is
enhanced by about 20 times (the rightmost column of Table 2.1), which constitutes a
significant improvement at high-injected powers. Notice that the power level required for
direct conversion of BPSK to ASK is large but conversion is done in a very simple
manner with a wide frequency locking range. If a wideband loop amplifier were used
(e.g. MPS911, 3dB BW of 300MHz), the locking range is expected to further increase.
Table 2.1 Comparison of the locking range of the converter
Injected
power
(dBm)
Locking range
without loops
(MHz)
Locking range
with (proposed)
loops (MHz)
Locking range
improvement ratio
15
0.1
1
10
18
3.0
50
17
21
5.5
100
18
24
10.0
200
20
Results with a single SH-ILPLL circuit for a BPSK-to-ASK conversion are shown in
Figure 2.23. With an injected power of 21dBm, ¥ of 0°, f0 of 1.588GHz and f , of
1.7GHz and DC feeds of 200nH, ASK signal output was observed. As the settling time
is more than that with the two SH-ILPLLs, the allowable data rate is lower. The locking
range is only 30 KHz with the injected power of 21dBm. The single SH-ILPLL circuit is
also sensitive to the value of injected signal p h a s e d . However, the circuit is very simple.
45
I I I I I I I I I I I I II I I I I I I I I II I I I I I I I' I I I I II I I
DJ3
05
1.D
1.5
ZD
2.5
3.D
35
III
time (usee)
Figure 2.23 ASK output of a SH-ILPLL circuit functioning as a BPSK-to-ASK converter
It should be mentioned that in both types of converters discussed above, output signal
levels depend on the initial phase of the injected signal; therefore, a preamble data stream
with known bits is required for carrying out accurate detection.
2.4 An Injection-Locked Carrier and Coherent Demodulation Receiver
In today's digital wireless communications, the direct down-conversion receiver is
becoming a favorite choice due to its overall simplicity and low cost. However, carrier
recovery of the received digitally modulated RF signal for clear IQ signal extraction at
high symbol rates is not so simple. Until now, phase-locked loop (PLL) and/or directdigital synthesizers (DDS) or a combination of both have been used for better
performance but at the expense of high complexity or cost. In this section, for the first
time, we propose a direct down-conversion receiver that uses an injection-locked
oscillator (ILO) for carrier recovery and frequency synthesizing. The results are shown
for carrier recovery of a 2.1GHz 20MSPS 8PSK signal and coherent demodulation of a
2.78GHz 160MSPS QPSK signal.
The receiver presented is of low cost and low
complexity and is applicable to any kind of digitally modulated signal reception. Thus, it
can be used in many wireless applications, such as WiMax, RFID and sensor networks.
46
More specifically, we use the digitally modulated RF signals as the injected signal of the
ILO and obtain the carrier from the ILO output. The recovered carrier can then be used
as a synthesized LO signal for coherent direct down-conversion demodulation to I and Q
baseband signals. As a result, high data rates, low power, and low system complexity are
achieved. The design presented can be used for coherent demodulation of virtually any
kind of digitally modulated signals.
In the following subsections, we will first describe the carrier recovery scheme and then
its use that leads to the design of the receiver.
2.4.1 Carrier Recovery using Injection-Locked Oscillator (ILO)
The digitally modulated RF signal is used as the injected signal to the oscillator. If the
signal level and bandwidth are within the locking range specified by (2.34), the oscillator
will get locked to the injected signal. There are different locked modes of operation.
First, if the injected signal is well within the locking range, ILO can follow the abrupt
phase changes present in the modulated signal and possibly can amplify the signal as
well. This mode is considered as a locked amplifying mode.
Secondly, if the signal
symbol rate is too high and thus the signal bandwidth exceeds the locking range, the
oscillator will not be locked to the injected signal in its entirety; rather, it will be locked
to the signal carrier only. This is called the carrier recovery mode. To recover the carrier
from a RF digitally modulated signal at a given symbol rate, an injection-locked
oscillator has to operate in this mode for which the injected signal power level, and the
oscillator resonator quality factor need to be carefully adjusted.
A received digital RF signal can in general be expressed as:
r(t) = 4 sin{27rf,t + 0d(t) + (p{t)} + n(t)
(2.32)
where A, is the amplitude and f (co, = 2 ^ ) is the carrier frequency of the received signal,
0d(t) the phase modulation, for QPSK, 0d(t) = (0,n/2,n,—7t/2) , with a given symbol
rate, R (= (1 / 2n) * dOd(t) / dt),
q>(t) the surplus phase noise, and n(t) is the thermal
noise.
In the frequency locking analysis, n(t) is assumed negligible. As (pit) can be a slowvarying function of time as compared to the symbol rate and hence is ignored as well.
The received signal can be written as
r
(t)=
AjSm^lrfjt
+ 0d(t))-
(2.33)
Now, consider an oscillator with a free-running frequency of f{) (close to f ) with its
resonator quality factor Q . If digitally modulated RF signal at frequency f and amplitude
of At is injected to the oscillator the locking range Aco, (= ®0 "
°f the ILO as described
in [1-28] is given as
Affl;=(fflo/20*(4M)
(2.34)
where co(l (= l7ifa) is the free running frequency of the oscillator, Q is the quality-factor
of the oscillator resonator circuit, and Al and A0 are the injected and oscillator output
signal amplitudes, respectively.
Equation (2.34) shows that with the given parameters Al and Q, one can calculate the
locking range of injection-locked oscillator. The locking phenomenon is explained in [115].
For a binary phase-shift-keyed (BPSK) signal (for every data transition from 0 to 1 or
vice versa the signal experiences a phase change of 180°), the ILO can track the input
signal phase transitions only if the symbol duration T(= 1 / R) is enough for a 180° phase
48
change to occur in the oscillator [1-1]. This gives the minimum symbol (to be tracked)
duration of
min_ BPSK
(2.35)
)tt/Ao), = 1/2Af, •
If r i s significantly small such that each next symbol appears before 180° phase change
could occur in the circuit, the ILO will not lock the signal in its entirety; rather it will
most likely lock only to the signature of the carrier present in the signal. The details about
the carrier recovery can be found in [1-1].
The above concept is extended to the QPSK signal carrier recovery where for generating
carrier frequency signature at the ILO output, symbol duration must end long before 90°
phase change could happen at the oscillator output. This gives minimum track-able
symbol duration of
(2.36)
)nj2Acol = 1/4A/J •
Now, if the symbol rate is high enough and ILO remains unable to track all four QPSK
phase transitions, it can lock to the carrier in the modulated signal. The output of the
oscillator sout (t) after filtering unwanted harmonics and inter-modulation products can be
expressed as
(2.37)
In short, in an ILO with the conditions just discussed above, the signal sout (t) is purely
sinusoidal at the injected signal frequency.
An injected-locked oscillator was designed with a free-running frequency of 2.09 GHz. In
the oscillator, the common emitter configuration was used, as it has a smaller locking
range compared to the common base type [2-9]. This configuration was chosen because
our experience has shown that at a certain receivable symbol rate, the final system
49
performance is sensitive to the balance among the carrier recovery capability and locking
range and phase noises.
A prototype of the circuit was built on a FR-4 substrate. A picture of the ILO circuit
prototype is shown in Figure 2.14. To ensure that the designed ILO worked properly, it
was tested without any injected signals and then with a pure non-modulated clean RF
signal. As expected, the ILO output signals with the injected signal were much more
stabilized and clean than those without the injected signal. This proved that the ILO
worked.
A 2.1GHz 8PSK modulated RF signal now replaced the pure non-modulated clean RF
signal as the injected signal to the oscillator. The data rate was 15MSPS and the injected
signal carrier power was -lOdBm. The measured output signal spectrum is shown in
Figure 2.24. The spectrum shows that ILO was locked in the amplifying mode but the
carrier was yet not recovered.
The rate of the injected signal was then switched to
20MSPS. In this case, ILO was found locked to the carrier only and the carrier signal was
recovered. The recovered carrier was measured and the results are shown in Figure 2.25.
Agilent 00:21:84 4m
7, 2001
Mkr2
Ref 0 dBm
fltten
2.095 22 GHz
- 8 3 . 0 8 dBm
10 dB
Norm
Log
10
;
System, Alignments, Align All Now, N e e d e d
dB/
Center
2.100000000 GHz'
LgAv
C e n t e r 2.100 00 GHz
Span 16.47 MHz
m
Res BH 160 kHz
Marker
1
2
3
Trace •
a>
CD
<1>
Type
Freq
Freq
Freq
160 kHz
X
2.899
2.895
2.134
ftxis
97 GHz
22 GHz
78 GHz
Sweep 1 ms (601 p t s )
Amplitude
-35.19 dBm
-83.08 dBm
_nc ^ o
Figure 2.24 15MSPS 8PSK modulated signal spectrum.
50
•S
Agilent 60:04:10 Jun ?, 2001
Figure 2.25 Carrier recovered from the 2.1 GHz 20MSPS 8PSK modulated signal.
In other words, with the proper setup and parameters, the proposed ILO was able to
recover the carrier from the modulated RF signals directly.
2.4.2 The Proposed Direct Down-Conversion Receiver Front-End Architecture
Using ILO
In this subsection, we propose a new direct-down conversion receiver as shown in Figure
2.26, where the ILO we designed in the previous section was used to synthesize the
required carrier. For QPSK signals, standard direct conversion receiver architecture as
shown in Figure 1.4 is normally used and is discussed in Section 1.1.1 with its
limitations.
51
Mix-I
Figure 2.26 Direct down-conversion receiver using ILO.
The operational principle of Figure 2.26 is as follows: first, the received digitally
modulated RF signal is split into three parts. One part goes as the injection to the ILO,
which recovers the carrier, while the other two parts are used as the RF signals to the
mixers for generating the IQ signals. Since the recovered carrier may contain harmonics
and other inter-modulation products, a bandpass filter is used to remove them. This
carrier coming out of the ILO is split into two: one goes directly to a mixer to generate
the I-signal, and the other undergoes a phase shift of n 12 and then goes to the second
mixer to produce the Q-signal. Since the outputs of the mixers contain the baseband IQ
signals as well as other higher order inter-modulation products, low pass filters are used
to filter the unwanted products. The cutoff frequencies of filters are set according to the
received signal symbol rates. These baseband signals can then be amplified to be the final
I&Q signals.
2.4.3 Receiver Performances
Simulations of the designed receiver were carried out as outlined below to examine the
performance of the designed receiver. The proven ILO with a free running frequency of
2.09 GHz natural frequency was used in the receiver. A 2.1 GHz modulated RF signal
was sent into the receiver. To investigate at what data rate and with what power level the
ILO can recover the carrier and produce at the receiver output a locked IQ signal
52
constellation the data rate was varied in steps from 10MSPS to 150MSPS and the signal
power was varied between -lOdBm and 20dBm.
Figure 2.27 shows the I-Q constellation at the receiver output when the carrier power was
16dBm, the signal type was 8PSK, and the data rate was 27MSPS. The constellation was
not locked and was rotating because of the different delays or phases between of the ILO
path and the RF signal path.
Figure 2.28 shows the results when the carrier power was lOdBm, the signal was QPSK,
and the data rate was 130MSPS. The constellation was still not locked and the similar
rotating was observed.
6
Time (0.0 usee to 4.741 usee)
Figure 2.27 I-Q constellation (not locked) recovered by the proposed receiver with an
input signal of 2.1 GHz 8PSK at 27MSPS.
53
Time (0.0 usee to 769.2 nsec)
Figure 2.28 The I-Q constellation (not locked) recovered by the proposed receiver with
the input signal of 2.1 GHz QPSK at 130MSPS.
To investigate the possible impact of the frequency, an ILO with a free-running
frequency of 2.75 GHz was designed and used in the receiver. A 2.78 GHz QPSK
modulated RF signal was sent into the receiver. The data rate was 160MSPS and the
signal power was 1 OdBm.
Figure 2.29 shows the constellation recovered with the receiver. It is not rotating this
time. The carrier was recovered quite well and IQ data obtained were of a good quality.
Note that the hardware test could not be performed in this case because of the
unavailability of a high symbol rate Vector Signal Generator in our laboratory.
54
Time (0.0 nsec to 6250 nsec)
Figure 2.29 The I-Q constellation recovered by the proposed receiver with the input
signal of 2.78 GHz QPSK at 160MSPS.
For comparison of the constellation recovered, shown in Figure 2.29, with the original
data, Figure 2.30 shows the constellation in the modulated RF signals sent into the
receiver.
Time (0.0 nsec to 625.0 nsec)
Figure 2.30 The constellation of the input signal of 2.78 GHz QPSK at 160MSPS.
55
As can be seen from Figure 2.29 and Figure 2.30, the IQ signals recovered by the
receiver are very close to those of the input modulated signal with rotation of a fixed
angle. The angle can be attributed to the signal path delays of the receiver.
In general, the small locking range of the ILO can limit the capability of the receiver for
wideband applications. However, to overcome this problem, we had combined PLL
mechanism with ILO technique and presented the analysis in [1-14]; such a technique can
be implemented in the receiver presented in this work. In the case of any interference or
presence of jammers, the frequency agile mitigating techniques as discussed in [2-10] can
be applied to generate required tuning function for the ILO used in this work.
In any way, the above results show that the proposed ILO based direct down-conversion
receiver provide a simple and effective way of coherently demodulating the digitally
modulated signals carrying a digital signal of a data rate of up to 160MSPS.
The
complete hardware design and test are currently under way.
2.5
An
Receiver
Injection-Locked
Carrier
for
Multichannel
Direct-Conversion
Synchronization is a challenging issue facing industrial designers that has not been
researched often by academic researchers. The conventional techniques are phase-locked
loop (PLL), digital PLL, or direct-digital synthesis (DDS). With any one or a
combination of these techniques, high performance can be achieved at the expense of
complexity or cost. For example for multichannel demodulation the standard receiver
shown in Figure 1.4 can be used with a tunable VCO or multiple VCOs at the frequency
of a desired channel. But the issues of overall system complexity and limitation of
handling fast data rate signals still remain. In addition multiple VCOs can increase the
power consumption of the system.
56
In this section, the injection locking technique discussed above (Section 2.4.1) is used to
provide synchronization for a direct-conversion receiver for more than one frequency
channels. More specifically, signal synchronization is achieved with a selectable
dielectric-resonator injection-locked oscillator (DRILO) designed at a free-running
frequency of 3.634GHz. The receiver developed was able to recover the carrier and IQ
signals from 3.58GHz, 3.63GHz and 3.69GHz with 50MSPS to 63MSPS QPSK
modulated signals.
The receiver designed as such is novel and simple, and caij find
applications in many modern communications such as WiMax. It can also overcome
frequency synchronization problems faced in OFDM systems.
2.5.1 Dielectric-Resonator ILO (DRILO) Design
In this subsection, a high-Q dielectric resonator (DR) [2-13] and a narrow-band PBF is
used to form a small locking-ranged dielectric-resonator ILO (DR-ILO). This limitation
of the small locking range supports the carrier recovery capability of the ILO from the
high symbol-rate digitally modulated RF signals. The schematic block diagram of the
DR-ILO is shown in Figure 2.31. Here, the dielectric-resonator is tuned at the carrier
frequency of the RF modulated injected signal, in the injection-locked mode the oscillator
core oscillates at the injected signal frequency and additionally generates at the output
related harmonics, the filter at the DRILO output filters out the harmonics and other
unwanted distortions. The final out put is then a clean version of the carrier signal.
DRILO
Dielectric
Resonator
Osc
BPF
m .
Modulated
RF Signal
Received
Carrier
Recovered
^
Figure 2.31 Dielectric-resonator ILO (DR-ILO) Schematic Diagram
57
The design features of the ILO are discussed in [1-29], The working of ILO for carrier
recovery is as explained in Section 2.5.1 above. However, the difference is that, having a
high Q resonator, the DR-ILO would be able to recover carrier, as explained in (2.36), at
a data rate lower than 160MSPS. This is because a high symbol rate waveform generator
was not available in our lab at this time. Also, the implied application is a multifrequency signal reception in a wide frequency band. We can trade data rate for wide
frequency band. A DR-ILO was designed with resonator's Q of 933 and oscillator'sf Q of
3.634GHz.
An injected-locked oscillator was designed with an NPN transistor (common emitter)
oscillator core and a dielectric resonator. The oscillator free running frequency, fQ, was
found 3.634 GHz with Aout of lO.ldBm. A dielectric resonator with a quality factor Qof
933 was used for better stability of the ILO output signal and to recover the carrier at a
reasonably high symbol rate.
Using the above parameters and the injected signal of OdBm in (2.34), Aco, is found to be
approximately 0.2 MHz. According to (2.36), for the ILO to track the QPSK signal in its
entirety, the tracking time, Tmin
QPSK,
can be approximately 1.25 //sec.
A 3.63 GHz QPSK modulated lOdBm RF signal was injected into the oscillator. The
data rate was 40MSPS (T=25nsec) and the injected signal carrier power was lOdBm.
Although Tmm
QPSK
was greater than T, the oscillator output was not found locked to the
carrier. After the signal power was increased to 12dBm and symbol rate to 50MSPS with
a filter roll-off factor of 0.35 at 3.63GHz, the carrier was recovered, as shown in Figure
2.32.
58
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o
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o
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d Bra { t a< I LOou t ) )=7 . 647
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ao
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Frequency (GHz)
Figure 2.32 50MSPS QPSK 3.63GHz modulated signal spectrum and recovered carrier
signal.
The spectrum shows that DRILO was not locked to the signal in its entirety but the
carrier signature, as expected. In other words, with the proper setup and parameters, the
proposed DRILO was able to recover the carrier from the modulated RF signals directly.
The locking time was noted at around 35nsec, which is at least 100 times faster than the
PLL based systems [1-1]. This fast carrier recovery capability at the front end can enable
high data rates and save/eliminate huge signal synchronization workloads of the baseband
DSPs in digital communications.
It was also observed that when a carrier o f f . H z carrying a symbol rate of R symbols per
sec (or Hz) with f , + R ~ f0 or ft - R = / 0 , is injected, the nonlinear action and selfmixing property of the ILO can result in the locking to these carrier signals.
2.5.2 The Proposed Multi-Channel Receiver Architecture Using DRILO
The DRILO with three switchable DRs and a tri-band selectable filter were employed to
form the selectable frequency dielectric resonator injection-locked oscillator (DRILO)
and were used to construct the direct-conversion receiver. The overall architecture is
shown in Figure 2.33.
59
Figure 2.33 Direct-conversion receiver using selectable frequency DRILO.
To avoid any reverse affects, an isolator was placed between the three-way divider output
and the input of the oscillator. For each carrier signal of the tri-bands, a resonator and a
filter section was tuned electronically by a predefined procedure. Similar to the one
discussed in [2-11] [2-12], an algorithm can be tailored to avoid interference.
The operational principle of Figure 2.33 is as follows: first, the received digitally
modulated RF signal, at, say, frequency f , is split into three parts. One part goes as the
injection to the pre-selected branch of the DRILO, which recovers the carrier, while the
other two parts are used as RF signals to the mixers for generating the IQ signals. A preselected BPF is used to remove inter-modulation products in the recovered carrier. This
carrier coming out of the DRILO is split into two: one goes directly to a mixer to
generate the I-signal, and the other undergoes a phase shift of tt/2 and then to the
second mixer to produce the Q-signal.
Since the outputs of the mixers contain the
baseband IQ signals as well as other higher order inter-modulation products, low pass
filters are used to filter the unwanted products. The cutoff frequencies of filters are set
according to the received signal symbol rates. These baseband signals can then be
60
amplified to be the final I & Q signals. In a similar fashion, two other RF signals at f a
and f i 3 were down-converted.
2.5.3 Receiver Performances
Simulations in ADS2006A were carried out on the receiver designed above. It was
observed that, in any channel, when the carrier recovery conditions are not satisfied, the
carrier is not recovered and LO signals are not synchronized with mixer input signals.
Thus, IQ constellations are not found at all, or are found rotating. To investigate possible
impacts of frequency, data rate, and injected power, a variety of QPSK-modulated RF
signals were sent to the receiver.
Figure 2.34 shows the I-Q constellation recovered by the receiver with the input signal of
3.63 GHz QPSK at 50MSPS. Figure 2.35 shows the constellation in the original
modulated RF signals. The two constellations are very close to each other but with an
angle. The angle can be attributed to the signal path delays of the receiver.
Time (0.0 usee to 2.0 usee)
Figure 2.34 The I-Q constellation recovered by the proposed receiver with the input
signal of 3.63 GHz QPSK at 50MSPS (RF input and DRILO output spectrum shown in
Figure 2.32).
61
Time (0.0 usee to 2.0 usee)
Figure 2.35 The I-Q constellation of the input signal of 3.63 GHz QPSK at 50MSPS.
Figure 2.36 shows the results at 3.58GHz. It indicates that the carrier was recovered quite
well from a QPSK signal at 50MSPS modulating a 12dBm carrier. IQ data were obtained
in a good quality. Results obtained for the case of 3.68GHz 63MSPS QPSK signal were
very much the same.
Next page
62
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Figure 2.36 RF input and DRILO output spectrum (top) and the I-Q constellation
recovered (bottom) by the proposed receiver with the input signal of 3.58 GHz QPSK at
50MSPS.
In summary, the results show that the proposed DRILO-based direct-conversion receiver
provides a simple and effective way of coherently demodulating the digitally modulated
signals of multiple frequencies carrying a digital signal of a data rate of up to 63MSPS.
The complete hardware design and test are currently under way.
63
2.5.4 Discussions
The receiver designed as shown in Figure 2.33 is novel and simple. With such
characteristics, the proposed technique presents as a good candidate for high quality
video reception at multiple frequencies (e.g. 5-20Mbits/sec with MPEG-2 or JPEG
compression). This frequency selectivity capability can be further programmed according
to a known algorithm, which can be helpful to avoid any harmful interference in the
medium.
The designs proposed can find applications in many modern communications systems,
such as WiMax or UWB. As there is faster synchronization capability in ILO-based
systems at selectable frequencies, the data rates are achievable up to 63MSPS and higher
even in time-variant fading channels (resolvable multipath channels). The presented
receiver can overcome frequency synchronization problems of OFDM systems but may
require complex equalization.
2.6 Conclusions
This chapter presents the first part of the original contributions by this thesis (also
mentioned in Section 1.3): developments of new injection-locked oscillation techniques
and their applications for advanced communications systems. They can be summarized as
follows.
A subharmonic injection-locked oscillator using a hetero-junction bipolar transistor has
been proposed. It is found that the injection locked oscillator has a phase noise
performance similar to that of the injected signal with a slight degradation of 0.5dB. The
proposed circuit is simple and can produce a phase noise of lower than -92dBc at lOKHz
offset. Therefore, it presents strong potential in having combined advantages of low
phase noise, simplicity, and low cost, and can thus be used for designing low-cost
wireless communication transceivers.
64
Two circuit architectures using the injection-locked PLLs for direct BPSK-to-ASK
conversions were proposed and simulated.
The significance of the work is two-fold.
Firstly, two SH-ILPLLs with their feedback loops can be used, which improves the
locking range by up to 20 times compared with those of the conventional BPSK-to-ASK
converters without loops. Secondly, it is shown that with careful selection of feedback
loop parameters, a single SH-ILPLL can also function as a direct BPSK-to-ASK
converter. Although it has limitations of small locking and dynamic ranges, it does show
the potential constructions of a simple direct BPSK-to-ASK converter with acceptable
performance. With the addition of a simple envelop detector, the proposed circuits can
fully function as a simple compact RF front-end receiver with fast acquisition speed
while operating entirely in the analog domain. Further work on hardware implementation
is underway and may lead to a novel microwave front-end terminal.
A direct down-conversion receiver using an injection locked oscillator has also been
proposed to achieve coherent digital demodulation. The injection-locked oscillator was
built and tested for carrier recovery for a reception of 8PSK 2.1 GHz signals at 20MSPS,
while the complete receiver was simulated for a 2.78 GHz 160MSPS QPSK signal. The
coherent IQ demodulation was observed. This showed excellent potential in using the
ILO as the synthesized source for direct down-conversion receiver. The significance of
the work is that the front-end will become very simple without issues inherent to PLL and
DDS. Further work on hardware implementation is underway and may lead to a novel
microwave front-end terminal.
A multi-frequency direct conversion receiver using injection locked oscillator (ILO) for
signal synchronization purposes is presented for the first time. The receiver works from
3.58GHz to 3.69GHz for 50MSPS to 63MSPS QPSK coherent IQ signals demodulation.
The distinction of the proposed architecture from other receiver architectures lies in the
fact that for high symbol rate receptions dielectric resonator ILO-based synchronization
can have faster signal acquisition than PLL and can recover the carrier for coherent
demodulation. Further, the data processing burden on ADC/ DAC/ DSP and latency in
baseband loops that limit high speed communications can be eliminated. Added benefits
65
are the circuit simplicity, lower component count, power-saving and low cost.
Interference problems can be dealt with easily by exploiting the multiple-frequency
operation capability of the receiver presented. One potential application is in retrodirective antenna system where Rx and Tx frequencies have to be situated closely for
performing phase conjugation on the received signal and transmitting required
information signal back towards the source.
In short, it has been shown that ILO-based synchronization techniques applied purely in
the analog domain can be used for direct detection of the BPSK and QPSK signals. Also
with a careful design ILOs, the weakness of small locking range can be turned into
potential strength of carrier recovery from digitally modulated signals. Thus DSP's or
FPGA's computational loads of signal synchronization to recover IQ signals can be
reduced or eliminated. High data rate digital signals of up to 160MSPS in a singlefrequency system or up to 63MSPS in a multi-frequency system are coherently
demodulated in ISM bands. In a nutshell, an ILO-based synchronization technique for
simple and high throughput transceivers for wireless communication systems and
networks has been presented.
The benefits of the signal processing in the analog domain as described in this chapter lie
mainly in the two facts: 1) signals processing speeds theoretically are in 100s of GHz
with RF transistors, 2) the circuits can be simple for a given specific application.
However, there are weaknesses of the analog domain, such as difficulty in reconfiguring
a circuit or system based on its needs and demands.
In terms of reconfigurability, digital solutions, especially with very high speed DSPs and
FPGAs of clock speeds in the GHz range, are the way to go.
Along this line, a new all-digital PLL is developed in Chapter 3.
66
CHAPTER 3
ALL-DIGITAL PHASE-LOCKING TECHNIQUES
The objective of this chapter is to develop all-digital phase-locking techniques for highspeed reconfigurable communication systems. The first section of this chapter (i.e.
Section 3.1) describes the background information for the all digital systems. After that,
each section (i.e. Section 3.2 - Section 3.6) presents the design and measurement of a
new FPGA-based all-digital PLL system. Finally, the last section (i.e. Section 3.7)
summarizes the work presented in this chapter.
3.1
Introduction
It is well known that high data rates, and consequently wideband communication
systems, are the preferred solutions to meet increasing demands for telecommunications,
and that these solutions are already major requirements in the areas of Ad Hoc networks,
intelligent antenna systems, broadband wireless networks, and mobile communication
systems.
In any communication system, there is a front-end transceiver in which the received RF
signal is first down-converted to a low frequency or baseband signal and then
demodulated. To extract data information, signal synchronization between the receiver
carrier frequency and the local oscillation frequency is required.
The signal synchronization can be achieved in two ways: 1) the synthesizer is locked to
the carrier frequency of the received/transmitted signal in the pass-band, 2) the phase and
frequency offsets around zero frequency are removed from the down-converted baseband
signal in the baseband. There is a wide variety, of the state-of-the-art synchronization and
synthesis techniques to choose from, such as analog/digital PLL (DPLL) [3-1] [3-2],
direct digital synthesis (DDS) [3-3] [3-4] [3-16] and, more recently, the injection-locked
67
oscillator (ILO) [3-5] [3-6], A brief review of the state-of-the-art synchronization
techniques was presented in Section 1.1.2.
Over the past decade, researchers have focused on implementing the all-digital
reconfigurable PLL (ADPLL) purely in the digital domain to remove the phase and/or
frequency offsets at the baseband around zero carrier frequency. Plenty of literature has
been published on the operation and simulation of the ADPLL [3-7] [3-8], For improved
performance using ADPLL, complex system designs and software routines have to be
configured in the receivers at baseband frequencies. This requires high-cost DSPs or
FPGAs. Further, no detailed real life implementation challenges have thus far been
explicitly described.
3.2
A Low-Cost All-Digital PLL: Design and FPGA Implementation
All digital normal design practice is to use a hybrid algorithm structure where part of the
circuit math, such as multiplications, clock generations, and frame recovery PLLs, is
implemented in the top module file of a hardware description language (HDL) and some
functions are called from submodules from within the top module. This gives the
designer flexibility to handle the design issues easily but the area occupied by the circuit
in a programmable device such as FPGA would be increased and timing issues will be
tedious to work around.
In this subsection, a novel user-friendly implementation of an all-digital phase-locked
loop (ADPLL) is presented. Its novelty lies in the fact that the very basic functions of the
ADPLL are kept in the top module Verilog file. Against the normal design practice, all of
the main math functions are implemented using the sub-modules placed outside but
called from within the top module. Furthermore, the received data were passed through a
timing recovery loop to reduce the BER. In this way, ADPLL can be easily implemented
in a low-cost FPGA. Further, the implementation details of an ADPLL, which have not
been reported previously in a single report, are described together for the first time.
68
The reconfigurable ADPLL is then implemented in a transceiver architecture and tested
with real signals received wirelessly. The recovered IQ constellation EVM of 9.0336% is
obtained, which is quite practical. This proves the feasibility of the ADPLL not only in
simulations but in a real-life communication system. An ADPLL designed this way can
be used in any communication system, although preferably for high data rate transceiver
applications.
3.3
Design
The ADPLL comprises a mixer, a phase detector, a loop filter and a numerically
controlled oscillator. The working principle of these components has been discussed in
many publications [3-7] [3-8].
The proposed ADPLL is comprised of mainly three modules: phase detector, loop filter
and a numerically controlled oscillator. It was designed and simulated in Matlab
Simulink. The schematic model of an ADPLL is shown in Figure 3.1. In the mixer and
phase comparator, the reference phase is compared with the phase of the feedback signal
from NCO and an error signal is generated.
•
LF output
'
E L
PD_output
Rx_l
cos
pdout
• filter in filter out
theta
sin
Rx_Q
P h a s e Detector
Loop Filter
Rx P o s t - F e e d b a c k CH
IQ
feedback
R a n d o m Integer
Generator
Figure 3.1 Matlab Simulink model of the ADPLL
69
>
f edback
, eedback
Following are the key points to the design and implementation of the ADPLL.
1)
The phase error (p between the standard constellation point and the received signal
points should be recovered by the phase detector (PD).
2)
A loop filter (LF), with both a proportional path and an integral part, is required for
low pass filter and smoothen the phase error signal generated by the PD. A firstorder infinite impulse response (IIR) filter can do the required job. It includes the
equivalence of R1 and CI in the analog version of the LF, which defines a pole at
the cut off frequency and the loop bandwidth. Careful selection of the LF
coefficients is necessary to control loop parameters such as settling time, PLL lock
in range and loop BW, and phase noise.
3)
A numerically controlled oscillator, which can be a sine and cosine lookup table, is
needed to take in the averaged phase error signal from the LF and to output a
feedback signal that, when added negatively with the received signal, can cancel
the phase and frequency offsets present in the received signals.
4)
A complete ADPLL can be a second order circuit.
5)
The loop bandwidth and lock time should be chosen in consideration of the RF
channel properties. Coherence time is in the order of 0.07sec at 2.4GHz in our lab
environment; so the lock time should be better than that.
6)
The lock range (roughly twice the loop bandwidth) is derived from the maximum
frequency offset presented to the ADCs
7)
Loop bandwidth can be estimated as 1200Hz (half of the maximum frequency
offset which can be 2400Hz for a 2.4GHz LO, with a 10MHz reference having
frequency stability of lppm).
8)
Phase ambiguities inherent in the carrier-suppressed modulation schemes can be
removed by transmitting some known data to the antenna. This way any known
phase offset can be compensated by multiplying the subject data with the
conjugate of the phase offset found. To further reduce BER, the recovered data can
be passed through a matched filter and a timing recovery loop.
9)
Geometry or carrier phase near baseband can be recovered for the channel using an
ADPLL.
70
10) ADPLL is implemented with FPGA, Lattice ECP2, fixed point DSP with software
ispLEVER v7.2 using Verilog HDL.
11) Uplink (transmitted from user end to receive at FPGA-based transceiving system)
is at 2.43GHz with 10MSPS in QPSK.
12) Downlink (transmitted from FPGA transceiver side and received at user end) is at
2.43GHz with 455.619KSPS.
As discussed in [3-9], suppose (I 0 ,Q 0 ) is the normalized standard constellation point.
withV77^7=v?,
9«sinp
1
=
.(I0Q,„ - ImQ0)
(3.1)
w'+a-)
where(/,„,£),„) is the received data, (I0,Q0)is
the ideal standard data and (p is the phase
error between (7 0 , Q0) and (/,„, Qm).
When normalized, (3.1) can be further simplified to be
(3-2)
<P = hQm~ImQo
The loop filter gives the averaged error signal (control signal) to the NCO that
consequently can generate the required frequency signal locked to the reference signal, as
discussed in [3-10]. Further design details of a baseband PLL can also be found in [3-13].
From Figure 3.1, the breakdown of Phase Detector and Loop Filter blocks are shown in
Figure 3.2.
71
Out1
In1
Gainl
Gain2
Unit Delay
1
Sign2
Products
Figure 3.2 Phase detector and loop filter
The slicers Signl and Sign2 in the phase detector decide whether each next coming
sample has a positive or negative drift in phase as compared to the previous one. The
differential instantaneous phase error (p appears at the output. The loop filter averages it
and generates a low-pass-filtered and smooth control signal based on its gain coefficients
G l , and G2. These coefficients can be calculated as in [3-11] [3-12]. In our design, G1
and G2 are 0.007813. This Simulink model of ADPLL is designed to work for 200KSPS
baseband IQ input signals (QPSK only). The ADPLL was tested for a phase offset of 45
degrees and frequency offset at 100Hz. These values are very practical to test the
behavior of the ADPLL's locking capability and stability.
The simulations results of the ADPLL from MATLAB Simulink are shown in Figure 3.3.
72
File
Axes
Channels
Window
• S B
Help
File
Axes
Channels
Scatter Plot
Window
Help
Scatter Plot
1
-Q.5
0
05
1
-0.5
In-phase Amplitude
0
05
In-phase Amplitude
Figure 3.3 Simulation results of the ADPLL from MATLAB Simulink
In Figure 3.3, at the top left comer, the IQ constellation of input signals (I i n ,Q i n ) is
shown. It was observed rotating, not locked. Next to it, on the upper right corner, is the
constellation of the output IQ signals (7 0 , Q 0 ) , which is fixed at positions and therefore
locked. Shown at the bottom is the phase detector damping output, loop filter integrating
output, and NCO stable cos and sin outputs. All these observed facts show the behavior
of ADPLL being locked. Finally, in the ADPLL locked mode, BER was found less than
0.1%, which meets most wireless communication system requirements for data and voice
transmissions.
73
3.4
FPGA Implementation
Normally in industry, the structure of PLL is implemented as one top module (Verilog
file) that does part of the PLL math, and calls some sub-modules from outside the top
file. It therefore gives a programmer some flexibility in handling math for each
component of the PLL. However, it is normally difficult to implement these on low-cost
FPGAs because of placement and routing of DSP circuits for complicated math routines
of the top module.
Instead, we developed a new user-friendly approach to the implemenetation. In our
implementation, we put the very basic functions, such as shifting the data left or right in
registers and delaying a given data sample for known clock cycles, in the top module
Verilog file. All the main math functions, such as multipliers, in the sub-modules are then
placed outside but called from within the top module. This way, ADPLL is easily
implemented in low-cost FPGAs such as LatticeECP2. Secondly, to reduce the BER, the
received digital data were passed through a timing recovery loop using a PLL on board
FPGA.
As an example pertaining to the math functions, to implement the decimal value gain
coefficients such as G1 of the loop filter of Figure 3.2, first, an integer value gain_y needs
to be obtained by multiplying the decimal value G1 with 2 x where x can be any integer.
The gain y is implemented using a sub-module multiplier in Verilog. Later the
multiplication factor 2X present in the result of the multiplier can be removed by shifting
its decimal point rightward by x bits.
The ADPLL was coded in the Verilog language and its functional and time domain
testing was done in ModelSim from Mentor Graphics. A close view of the simulation
results for the numerically controlled oscillator (NCO) outputs I_feedback
and
Q_ feedback is shown in Figure 3.4. It is clear from the Figure 3.4 that ADPLL is locked
74
to the input signals, and I _ feedback and Q_ feedback signals become pure sinusoids as is
in Matlab simulation results in Figure 3.3 (bottom-right).
Figure 3.4 (close view). Simulation results for the numerically controlled oscillator
( N C O ) outputs I _ feedback and Q_ feedback
3.5
Test Setup
The ADPLL designed was tested in a complete transceiver setup as shown in the Figure
3.5 below. A digital RF signal of 2.4GHz QPSK at 2.5MSPS was transmitted using an
Agilent's ESG Vector Signal Generator (E4438C) as source with an omni-directional
monopole antenna. In a wireless lab environment with a plenty of test equipment,
computers, test benches and working personnel, the wireless signal was received, using a
patch antenna, RF down-converter and an Analog to Digital Converter (ADC), at a
distance of approximately 3m. The received data was processed with the designed
ADPLL implemented on the FPGA. In the locked mode of the designed ADPLL 1020
samples (on-board FPGA memory limit for the current design) of the processed data were
stored
and then retransmitted
through a DAC/RF up-converter
at a rate of
16.272114KSPS (limitation of the currently available DAC). This signal was upconverted
using Agilent's E4438C ESG Vector Signal Generator with MUX setting at Ext 6000hm
and then received by an Agilent Spectrum Analyzer (PSA) and IQ diagrams were plotted
using Agilent Vector Signal Analysis (VSA) 89600 software.
75
PC with
Lattice
ispLEVER7.0
ispDOWNLOAD cable
i'p«;a
Alll'l I
l.iltiit r.C'1'2 iiiiplenu'iiu'd
Advanced
Evaluation liunrd on l l'(i\
1
l)\(
Local Oscillator
Signal
o
-
•
iOn
.
\sill-nl\si; h'443S(
MI X luurcr l.\l. O
htnioiim
Dirccl-fonvmiiui
R\
2.4GHz
16.272Ksps QPSK
patch antenna
mounted on tripod
Anient Sped nun
Analyzer
o
PSA E4440A
V
Wireless Channel
O
.
P C with
Agilnet VSA89600
software
s
Mono-pole Antcnnii
mi tuhlf*
Agilent VSG E4438C
MUX source Int.
BBG1
ADPLL Test Setup (FPGA based transceiver)
Munir Tarar
February 23, 2009
A 1
2.4GHz
2.5Msps QPSK
1 of 1
Figure 3.5 The ADPLL test setup
3.6
Measurement Results
IQ constellations of the original input modulated signal transmitted are shown in Figure
3.6. The IQ constellation recovered by the proposed ADPLL with this input signal is
shown in Figure 3.7.
76
Figure 3.6 I-Q constellation transmitted with the input signal of 2.4 GHz QPSK at
16.272114KSPS (random data type PN23)
Figure 3.7 I-Q constellation recovered by the proposed ADPLL with the input signal of
2.4 GHz QPSK at 16.272114 KSPS (random data type PN23)
77
Regarding results, the random data type PN23, shown in Figure 3.6 and Figure 3.7, are
very similar. In Figure 3.7, for the recovered IQ constellations, an EVM of 9.0336% was
obtained; it is very practical although not very close to 5.0513% of the data originally
transmitted (as shown in Figure 3.6). The BER and SER performance can be tested, as
shown in the RTS modeled results in Chapter 4. With the EVM results presented,
however, it is expected to be good. The difference between the recovered signal
constellations shown in Figure 3.7 and the transmitted signal in Figure 3.6 is due to four
reasons: 1) only 1020 samples of the data recovered with ADPLL were repeated. The
instance when data from the FPGA RAM repeats a few samples does not make a
complete symbol time duration and hence causes a scatter near each symbol point in the
quadratic constellation, just as expected and observed in Figure 3.7; 2) FPGA RAM (as
per documentation of the RAM IP module used) itself causes some errors in the stored
data; 3) without affecting the data recovery process of the ADPLL the settings of the
measurement filters in VSA software are done as user defined type and reference filter as
rectangular type (instead of root raised cosine) in order to see a clear picture of the
constellation. However, these settings technically have no impact on the reliability of the
recovered
data;
4)
lastly,
the
noise
and
distortion
contribution
from
the
RF/downconverter, ADC and DAC in the system prototype.
3.7
Conclusions
This chapter presents the second part of the orginal contributions by this thesis (also
mentioned in Section 1.3) comprising designs and measurements of a new all-digital
system for advanced communications systems. These designs and measurements can be
summarized as follows.
A new simply-structured ADPLL has been proposed and implemented. The novelty of
the proposed design flow is that such designs are implementable on low cost FPGAs such
as LatticeECP2. It has been shown that the IQ constellation recovered by the ADPLL
from a received signal of 2.4GHz QPSK at 2.5, 6, 8 and 12MSPS was very similar to the
78
originally transmitted RF signal constellation in the realistic environment in a complete
transceiver architecture. Additionally, the ADPLL is a good candidate for singlefrequency high data rate communication systems.
Based on the results presented in this chapter, it is concluded that the ADPLL design can
be used in any communication system at a low cost. This work also presents a one-stopshop
for those
who
wish
to
understand
synchronization
requirements
for a
communication system covering all engineering design and hardware implementation
issues.
79
CHAPTER 4
RETRODIRECTIVE TRANSCEIVER SYSTEM
The objective of this chapter is to develop a digital implementation of a retrodirective
transceiving system on a FPGA platform that can also extract information in addition to
signal retrodirectivity towards an unknown source location. The first section of this
chapter (Section 4.1) describes the background information for the conventional
retrodirective systems. Thereafter, each section (i.e., Section 4.2 to Section 4.8) details
the design, implementations and tests of the newly implemented
retrodirective
transceiving system. Finally, the last section (Section 4.9) summarizes the work presented
in this chapter.
4.1
Introduction
A radio frequency transceiving system can be defined in classical terms as a complete
chain of hardware that can transmit and receive modulated signals. It may not be able to
demodulate the signal and extract the signal information for processing. With some
software control and digital design algorithms embedded especially for the system's
baseband part, a classical transceiving system can be enriched with the capability of
signal processing. This capability of signal processing in a communication system can
incorporate flexibility in the system performance such as capability of coherent signal
demodulation. To this end, signal processing in multiple antenna arrays can extend the
use of communications to advanced applications such as beam forming.
A
single
element
antenna
transceiver
can
normally
transmit/receive
signals
omnidirectionally or in a certain one direction if antenna is directive. But in today's
crowded frequency spectrum and power spectral mask regulations, beam forming can
play an excellent role. Beam forming can help finding the direction of arrival of the
signal. This can have excellent performance in a particular direction or can be
reconfigured in another.
80
In this chapter, a communication transceiving system with four element patch antenna
array that can retransmit signals in the direction back towards the source of the signal is
presented. This new system, a kind of smart antennas, is introduced as retrodirective
transceiving system (RTS).
Starting with an overview of the theoretical concepts, major benefits, some challenges,
key assumptions, modeled results, at the end hardware implementation, a retrodiretive
system is proposed and tested in this chapter.
4.1.1 Retro-Directive Antenna Arrays
A retro-directive antenna array is the simplest version of a retrodirective transceiving
system (RTS). Generally speaking, a retrodirective antenna array is considered to be
reflecting the incident signals back in the the direction of their arrival. It has been
implemented in analog domain using different techniques. The retrodirective antenna
array in classical terms is designed not to demodulate and process the signal information
in the digital domain. Thus it can have only a limitated intelligence level.
A retro-directive antenna array works on the principle of phase conjugation, i.e. the signal
retransmitted from each element in the array bears a phase conjugate relationship with the
signal received by that element [4-1]. In the following sections, a brief background of a
retro-directive antenna array is presented to establish a solid ground for understanding the
RTS discussed later in sections, Section 4.2 to Section 4.8.
1) Classical Van Atta retro-directive antenna array
This passive array is based on interconnecting transmission line method and is comprised
of a linear array of reflectors. Transmission lines of equal lengths interconnect these
elements as shown in Figure 4.1 [4-2].
81
tp- 3A
p-2K
<b-A
p-0
Relative received
signal phases
Interconnecting transmission
lines of equal length
Outgoing plane wave
q>- C
<3J-1\
tp-
2A
<p- 1A
Relaii\e transmitted
signal phases
Figure 4.1 Van Atta Array phase conjugation phenomenon
Incident signals travel through these symmetric (equal) lines and are retransmitted. If an
array is constructed in a linear fashion, the signals will be phase conjugated and reradiated in a retro-directive manner.
However, this classical array requires array symmetry, uniformity of wave front and
single frequency operation. To partially overcome these limitations (e.g., wave front
uniformity), antenna arrays using heterodyne method can be used. The method is outlined
as below.
2) Heterodyne retro-directive antenna array
The basic concept is that the antenna elements of array take samples of the incident wave
front at various positions and then mixes with the local oscillator that has twice the
frequency of the incoming signal. Then the phase conjugated signals are generated at
each antenna element. Finally, the superposition of these fields generated by the phaseconjugated signals results in a phase conjugated wave front traveling towards their
originating source.
82
This concept for microwave phase conjugation using mixers (the heterodyne system) is
illustrated in Figure 4.2 [4-3].
Figure 4.2 Block diagram for heterodyne phase conjugation concept
Take for example m as the incoming signal frequency with geometric phase <pk at an
antenna element. The local oscillator has a frequency double of it (i.e., 2a> ). Then, after
nonlinear mixing, the following IF signal (to be retransmitted) can be obtained [4-3]:
ej(cot+(pk)
0^7(2^0
= >
ej{2cot-cot-(pk)
=>
ej(cot-(pk)
This result shows that the signal, after mixing, has the same frequency (RF=IF) as that of
the input signal but is phase conjugated. This phenomenon is carried out simultaneously
at all the antenna elements and the outgoing wave front then retro-directly propagates
towards its source.
83
In this approach, a single frequency is operated on and an external LO at double of the
frequencies is needed. Also, all the antennas and mixers need to have the same behavior.
In addition, good RF/IF isolation is needed. Orthogonal or dual polarized antennas [4-1],
minimal frequency offsets, directional couplers or two stage mixing [4-2] can be used to
improve the isolation.
To overcome the above problems, a novel technique based on injection locking has been
developed to efficiently accomplish the desired objective of Phase Conjugation.
3) Retro-Directive Antenna Arrays based on Sub-harmonically Injection-Locked
Oscillators (SILO) [4-4]
The sub-harmonically injection-locked oscillator (SILO) was introduced in [4-4]. Active
frequency doubling is a favorite application of SILO. When SILO is appropriately biased,
it can also function as a self-oscillating mixer due to the transistor nonlinear effect. This
kind of mixer is called the sub-harmonically injection-locked self-oscillating mixer
(SILSOM) [4-5], Using a balanced circuit structure with SILSOMs phase conjugation can
be achieved. No external LO is required and the output signal is locked at the same
frequency as the input signal [4-6],
A retro-directive antenna array is constructed by loading the anticipated phase
conjugation circuit with active antennas. Very good isolation between receive and
transmit signals can be obtained by using a circulator with two dual polarized active
antennas and unilateral amplifier in series of each of them. Exploiting the locking
characteristics of the SILO frequency modulation operation is also possible. It can be
used in mobile communications where tracking of simultaneous users is required. Below
is an example for retro-directive antennas, the design details about this method can be
found in [4-6].
Example: A retro-directive antenna array with phase conjugation circuit using
subharmonically injection-locked self-oscillating mixers [4-6]
84
The design is basically the same as that of a heterodyne retro-directive antenna array with
the exception that phase conjugation circuit topology has sub-harmonically injectionlocked oscillators (SILOs).
SILOs are the key components and are mutually coupled to and from the overall array.
When properly biased, SILOs become sub-harmonically injection-locked self-oscillating
mixers (SILSOMs). A balance circuit structure, with in-phase coupling between the
SILSOMs at the fundamental frequency, can realize good isolation between input and
outgoing waves.
The block diagram of the single element of the array is shown in Figure 4.3. For building
the circuit block a quadrature hybrid is used with two SILSOMs coupled in-phase at the
fundamental frequency co.
Amplifier
Receiving antenn
(vertical polariza,
Transmitting antenna
(horizontal polarization)
In-phase
coupling
,(2)
V,
port 2
A
o
Termination
SILSOM 2
Phase conjugation circuit
Figure 4.3 The block diagram of a basic retro-directive SILSOMs unit [4-6]
85
Cascading many of the above single antenna element can make an one-dimensional
antenna array as shown in Figure 4.4, with all the SILSOMs coupled in-phase.
Figure 4.4 Block diagram of one-dimensional retro-directive antenna array [4-6]
86
Output signal for an N element array can be written as:
*
V inj,I
*
V
inj, 2
= c2 ALO eJ&
(4.2)
V inj,N
This result shows that, after processing, the output signal is proportional to the input
signal but with the conjugated-phase. More details of the phase conjugate circuit and
prototype of retro-directive array can be found in [4-6]. Measured and calculated
retransmitted radiation patterns of the retro-directive antenna with illumination antenna at
various incident angles are shown in Figure 4.5.
Next page
87
(0
id)
Kl
11)
Figure 4.5 Measured and calculated retransmitted radiation patterns of the retro-directive
antenna [4-6] with illumination antenna at the incident angles of (a) -30°, (b) -15°, (c) 0°,
(d) 15°, (e) 30°, and (f) 45°
Finite ground plane of patch antenna resulted in slight differences in radiation pattern at
extreme angles of ±90° as shown in Figure 4.5(c).
88
The above described restrodirective systems are developed in the analog domain for
reflecting the RF signal back towards its sourse. There is no intelligence incorporated in
the systems. Such intelligence can be built comparatively easily in the digital domain and
can help steer the antenna array radiation beam in some known direction(s) in addition to
other added benefits such as direction finding (DF).
4.1.2 Smart Antenna System
Smart antenna systems can help steer the antenna beam in some known direction(s) and
are used for advanced applications such as direction finding (DF). Further, to increase the
system user capacity and reduce interference in the wireless environment, smart antenna
system with a multiple antenna array was developed [4-7] and still is under the process of
further improvements. A smart antenna can be designed to focus electromagnetic energy
in a certain direction or directions. A sample smart antenna system [4-7] is shown in the
Figure 4.6.
Feedback Control
Figure 4.6 Sample smart antenna system [4-7]
89
The radiation beam can be scanned at discrete angular intervals to estimate the direction
of arrival of the signal. This is done by putting complex weights on the signals received
from each antenna element of the array as shown in the Figure 4.6. The system design
details can be found in [4-7].
The smart antennas are heavily dependent on the software algorithms and hardware used
especially for their signal processing speeds; this increases the complexity of the systems
and eventually cost.
4.1.3 Summary of the Classical and Advanced Antenna Arrays
As described previously, classical retrodirective antenna arrays can be used only in the
analog domain for reflecting the RF signal back towards its source. It cannot be used for
receiving and demodulationg the digitally modulated microwave signals and processing it
for extracting the relative phase information embedded in the signals of the individual
channels (elements of the antenna array). Also it cannot find and process a conjugate of
relative phase beween the successive digital channels and send the received digital signal
(or carry a new digital signal with its own information) back into in the direction of the
remote user end or source.
Further, smart antenna systems can help steer the antenna beam in some known
direction(s) and are used for advanced applications such as direction finding (DF).
However, prior knowledge of the source location is required and the beam is scanned at
the fixed angular intervals at the cost of system complexity and speed.
4.2
The FPGA-Based Retrodirective Transceiving System (RTS)
The objective of our work here is to provide a complete retrodirective transceiving
system designed to work in an indoor wireless environment. The added specifications
are: (1) a symbol rate of 1MSPS (extendable upto 10MSPS), (2) AGC in the baseband to
90
enhance the ADC dynamic range, (3) a carrier recovery PLL in a reconfigurable FPGA,
and 4) a complete reconfigurable retrodirective transceiver system.
4.2.1
Revisit of Retrodirective System Design Theory
The retordirectivity theory is revisited and reformulated here for the sake of FPGA-based
design. The important points are summarized below.
1)
A complex baseband signal transmitted from the mobile user (Source, Figure 4.9)
with a carrier frequency of a>c can be represented as:
St=(I0+jQ0)e^'
2)
(4.3)
Assume the uplink channel geometry or carrier phase i s ^ , ( 0 and the gain is a
then after direct down conversion at the receiver end (RTS BSE, Figure 4.7) with
an LO of frequency coc , the baseband signal can be written as:
srec=(I0+jQ0)ae^(,)
3)
(4.4)
The signal in (4.4) is in analog domain and used as input to an analog to digital
converter (ADC). At the ADC output the signal comes in digital domain and is
represented by Iin + jQm as is taken as input to the ADPLL in Chapter 3.
4)
The geometry angle e J ^ s(t) can be recovered by the numerically controlled
oscillator (NCO) as discussed in ADPLL in Chapter 3. The conjugate of it which
ise^
( 0
is compensated in the ADPLL channel one (channel-1) mixer and
phase detector respectively.
5)
If the same
is used in the remaining three channels (channel-2, channel-3
and channeI-4) of the array the carrier is effectively recovered for them similar to
the channel-1. Thus the baseband data recovered by the channel-1 should be at
91
the standard constellation points I0 + jQ0 as mentioned in Chapter 3 and the
remaining three channels would have their phase information relative to the
reference channel i.e. channel-1.
6)
The gain a for each of the four channels can be compensated at RF frontend
using AGC, which can be implemented in the ADS2009 system model.
7)
The data from ADPLL channel-1 output is kept as it is (which after locking
should be at the standard constellation points, so the phase conjugation does not
really matter) and the data from the resting three channels can be phase
conjugated in the digital baseband in the FPGA.
8)
The signal to be transmitted from the RTS for each respective channel becomes:
srelr„=(h+Qo)e~JM,)
9)
(4-5)
This data signal from all four channels can then be sent to four RF/UP-converter
transmitters through DACs correspondingly for downlink towards user end or
source through four-patch antenna array. (Note: New information data can be
generated as well at the RTS transceiver side for transmission.)
10)
The downlink signals after passing through the same channel (assumed reciprocal)
then ideally can add constructively at the user end or source as explained in the
previous section (Section 4.1).
4.3
System Design Specifications
The retrodirective transceiving system designed and presented in this chapter is at
2.4GHz ISM band for a proof of functional testing. For this purpose system's general
specifications, selected for its performance testing in indoor wireless environment [4-8],
are outlined below.
1)
Carrier frequency:
2.4 GHz ISM Band
2)
Modulation scheme:
QPSK
3)
Environment:
indoor wireless channel
92
4)
Constraints:
Wireless flat faded multipath channel
5)
RMS delay spread:
50ns
6)
ISI:
negligible
7)
Symbol Rate:
1MSPS or 2Mbps [4-8]
8)
Samples per symbol:
20
9)
Channel frequency offset:
1.2KHz
10)
PLL Loop bandwidth:
1.2KHz
(Half of the maximum frequency offset which can be 2400Hz for an 2.4GHz LO,
with a 10MHz ref having frequency stability of lppm) [3-13]
11)
Direct-conversion transceiver front-end (FE):
a.
gain imbalance:
O.ldB
b.
phase imbalance:
l.Odeg
12)
AGC received signal power variation: within 3 OdB
13)
AGC settling time:
< 8^sec [4-9]
14)
Communication duplexing:
half-duplex (time-division duplex) digital
communications
15)
Antenna type:
Retrodirective trans, system (RTS): 4-element patch antenna;
Source or user end: single monopole antenna
16)
4.4
Uplink (UL): Source to RTS; Downlink (DL): RTS to Source
System Architecture
The system architecture of the RTS under investigation is designed and shown in Figure
4.7 to Figure 4.10. The block diagrams are quite self explanatory. In Figure 4.7
retrodirective transceiver system (RTS) end (named as base station end, BSE) is shown
using
MAX2701EVKIT
and
MAX2721EVKIT
upconverter respectively.
93
as RF
downconverter
and
RF
o
AD5449 control software
ADS5282 control software
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Wireless Channel
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FPGA-based 4-element retro-directive system BSE
+ 2 8 V , 5A
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Regulated P o w e r Supplies Board
Munir Tarar
May 31, 2008
1 of 1
B 1
Figure 4.7 Block diagram retrodirective system Base Station End_MAX2721 EVKIT
94
In Figue 4.8 the RTS system is shown with MAX283OEVKIT as RF transceiver.
MAX2831 control software
AD5449 control software
ADS5282 control software
PC with
ispLEVER7.0
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Regulated P o w e r Supplies Board
Munir Tarar
May 8, 2008
1 of 1
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Figure 4.8 Block diagram retrodirective system Base Station End_MAX2830EVKIT
95
In Figure 4.9, the source (named as mobile user end, MUE) is shown which is required to
complete the functional testing of the retrodirective transceiver system (RTS).
Wireless Channel
s
Mono-pole Antenna
Ix/Rx
RF Switch
Ix/Rx
switch control from Matlab
Half-duplex system
with switch and Matlab
software control
o
Signal Generator
ESG E4438C
Spectrum Analyzer
PSAE4440A
t
T
PC with
VSA 89600,
LabView 7.1 and
Matlab 8.0
o
DAQ card output
o
FPGA based Retro-directive System MUE
Munir Tarar
May 31, 2008
1 ofl
B-l
Figure 4.9 Block diagram of retrodirective system Mobile User End or Source
96
Figure 4.10 shows source (with illumination antenna) incident angle 6>, antenna array
orientation or transmission angle 9a, and four signal-path phase offsets cpp{, <pp2, <pp3,
and cppA for channe-1 to channel-4, respectively.
Array A n g l e
0U
Figure 4.10 Retrodirective transceiving system: source incident angle 6 t , antenna array
orientation angle 6a and signal path phase offsets cpp], cppl, <ppl, and <pp4
4.5
System Modeling
The retrodirective trasnceiving system shown in Figure 4.7 to Figure 4.10 was simulated
with Agilent ADS2009 package which has, in addition to Analog/RF simulators, all the
DSP (numeric and timed, and co-sim with RF) modeling capabilities. The system model
supported with the design theory and system specifications would provide a solid ground
to know what exact hardware is required for a complete retrodirective transceiver system.
97
A custom QPSK waveform data from a timed source was input to the system. Multipath
channels, including additive white Gaussian noise (AWGN) channel noise model, and
random phase-frequency offset blocks were used to model the random wireless channel.
The ADPLL discussed in Chapter 3 was used for signal synchronization and phase
frequency offset recovery. The recovered data was then processed (with channel-1 data
kept as it is and remaining three channels phase conjugated) and transmitted through the
RF upconverters towards the remote source using a 4-element antenna array.
The uplink (UL) signal is originated from the source end with a single RF modulated
envelop signal output. The channel frequency offset is induced at the source. This signal
is split into four parts and passed through four channels with individual or independent
impairments such as phase offset. These signals are received then at the retrodirective
transceiving system with the direct down conversion receivers. These RF downconverted
signals are then, to compensate respective channel gain a and to bring them all to a
known fixed power level, input to the baseband automatic gain control (AGC) circuits.
This would help increase the dynamic range of the analog to digital converter (ADC)
following the AGC in the real system. Output I and Q signals (/,„, Qm) from the AGC in
channel-1 are sent to the input of a baseband ADPLL to recover the carrier near zero
frequency, thus removing the frequency and phase offsets present in the baseband signal.
This PLL is designed to recover small instantaneous phase errors. Once the PLL is locked
to the input signal the output is the error signal from channel-1. This error/feedback
signal (internally in the PLL is conjugated, by multiplying the sine part of the complex
signal by negative one within the NCO) is multiplied by the incoming signal to
compensate for channel impairments and bring the constellation at stable standard points.
This error/feedback signal from channel-1
PLL is multiplied individually with the
outputs from AGCs of all the remaining three channels thus effectively locking them to
the same reference signal (signal of channel-1). The outputs of multipliers of the three
channels are phase conjugated with reference to the signal of channel one.
The locked signals, output from the multiplier of the channel one and the phase
conjugated outputs of the other three channels, are sent as downlink (DL) through the
98
channels having the same characteristics as those for uplink (UL). After passing through
the modeled reciprocal channel these signals are supposed to add constructively at the
user end or source. As a performance comparison, the output of channel one and nonphase-conjugated signals from the other three channels are also transmitted towards the
source.
As a performance measure the EVM (illustrated in Figure 4.11) and SER of the received
signals at the source were recorded. In addition to this the signal Constellation Diagram
and Phase Error Sequence were plotted. The Phase Error Sequence, not normally plotted,
can be expressed as
Phase Err Sequence =
R e{E(k)}
+
j*]m{E(k)}
(4.6)
RMSQ S(k) |)
Where S(k)
is defined as the ideal reference symbol (normalized such that its maximum
energy symbol falls on the unit circle) at sampling instant k . E(k)
vector error on sample S(k)
is the residual
(in Volts).
Ideal IQ point, S(k)
Magnitude Error
Error Vector, E(k)
Received IQ point, S
I k )
•Phase Error
-1.0
Figure 4.11 Error Vector: Phase Error and Magnitude Error
99
4.6
Simulation Results
The system was tested at a carrier frequency, fc,
of 2.4GHz, symbol rate, R ,
of
1MSPS. The sample rate, Rsamp, for signal processing in the digital domain, was set at 20
samples per symbol. The channel noise mean, /u, was set to zero and variance, Var,
0.005. The power transmitted, Pt, from the source end and power transmitted, PRTS, from
the retrodirective transceiving system (RTS) end was kept constant at lmW. The uplink
channel frequency offset, foffset, is 200Hz. Channel random phase shift, (prandom , is varied
between 0° and 15°.
Signal parameters such as EVM, SER, and Phase Error Sequence are captured to
characterize performance of 4-channel RTS having phase conjugating capability with
reference to a single antenna transceiver and 4-channel transceiver without phase
conjugation. Note: the wireless channel path loss is not considered in simulations.
Continuous time records of 2(j,sec duration were recorded for EVM analysis.
A screen shot of the simulated performance results with a source antenna incident angle
6t (shown in Figure 4.10), of 0° is shown in Figure 4.12. The retrodirective system
antenna array transmission angle 9 a (shown in Figure 4.10) is also 0°. The signal fix
phase offsets in uplink channel-1 to channel-4, (pp]_u;, <pp2-ui.> ( P p ^ul >
an
d
(
Ppa-ui.
are
10, 25 and 40 degree respectively. Channel random phase shift, (prandom, is set to 0°for
this test.
From Figure 4.12, it can be seen that channel one output signal constellation 'ChlSignal-Received' is found rotating with the frequency offset / phase offset of the signal
received. After removing the phase and frequency offsets, the outputs (phase conjugated
signals are plotted in Figure 4.12) of the baseband ADPLL for chl to ch4 are observed
locked. Finally, the signals retransmitted from all four channels after passing through the
same (assumed reciprocal) channel are added constructively at the source (TOP right
corner Figure 4.12). It has larger I and Q magnitudes of around 1 (linear units) than
0,
around 0.2 (linear units) for individual received channel signals. The In-Phase symbols
(BOTTOM right corner Figure 4.12) of the net added signal at the source are clearly
square wave, instead of distorted/noisy shaped, of random data which is a second proof
for the correct performance of the RTS system.
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'Chl_Output_Locked_NotPhConj' is the output signal constellation of channel-1 without phase
conjugation.
'Ch2_Output_Locked_PhConj' is the phase conjugated output signal constellation of channel-2 and the
same is implied for channel-3 and channel-4 outputs.
'Signals_Received_added_atUserEnd' is the constructively added signal IQ constellation output at the
source end.
'Received-I symbols_atUserEnd' is the waveform of the Inphase-symbols, in ones and zeros form, at the
source end.
Figure 4.12 Simulated performance results of the retro-directive transceiving system
101
In the following subsections, the test results of the retrodirective transceiving systems in
several aspects are presented.
4.6.1 Automatic Gain Control Test
The automatic gain control (AGC) is implemeneted in RTS in all four channels after RF
downconversion (ref Figure 4.7). The uplink received signal power level in the range of
O.OlmW to l.OOmW can be controlled (within ldB) by AGC; such variation amounts to
100 times, or 20dB change in power. Without channel impairments, the noise
performance is better. However, with the other impairments such as high frequency
random noise in the channel, the received signal EVM measured at the source end is poor
especially at power transmitted, Pt, of O.OlmW from the source.
There are some important points to be considered to observe reliable results for the
retrodirective phenomenon. In ADS simulations, EVM modules' update periods has to be
smaller than the period at which a new phase offset is introduced as a channel
impairment. The bit period and symbol period are of same value equal to ljxsec.
For instance, an EVM simulated value for an impaired channel signal processed at the
retrodiretive end without having phase conjugation implemented can still be good. This
can happen because phase in UL channels was switched between 10 and -10 degrees for
example (can be random values) at a pace of 100|isec and EVM modules update period is
set to lOOO^sec which is greater than the above period of 100|isec. EVM module will be
updated only after 1000|xsec without showing any interim instantaneous EVM changes.
Also, the symbol burst length 'SymBurstLerf in EVM module should be made large to
span the whole length of simulation to observe the effect of EVM variations due to
mismatch of phase offsets in UL and DL channels. Also updating the phase offset after
known length of symbols ' Ne w Phase Aft erSym bols' should be less than the symbol burst
length 'SymBurstLen'. Only then the retrodirective phenomenon can be observed.
102
To meet the above requirements and to observe the results of the RTS accurately for the
wireless channels with random and discrete impariments, some adjustmnets were done:
for the symbol burst length 'SymBurstLen' of 1000 symbols the length of data flow
controller (DF) simulation was changed from 2000 symbols to 1000 and phase update
rate 'NewPhaseAfterSymbols' was changed from 10000 to 100.
a) AGC test without channel impairments
The channel noise level, N , of value zero is considered in these results. The parameter
settings for AGC testing of the retrodirective trasnceiving system with a clean wireless
channel, with no channel impairments, are given in Table 4.1. In addition the intention is
to identify all parameter names that will be considered for the testing of the system in the
sections below.
Table 4.1 Parameter settings for testing the retrodirective trasnceiving system (RTS) with
AGC - No impairments in the wireless channel
Channel noise
Channel frequency
RF/DC Phase
RF/DC
level' N'
offset Uplink
imbalance
gain imbalance
' PKbaiance' (degree)
' G,mhakmce' (dB)
' f offset ' (KHZ)
0
0
0
0
Uplink Ch-1
Uplink Ch-2 phase
Uplink Ch-3 phase
Uplink Ch-4
phase offset
offset' <pp2_UL'
offset' <pp3_UL'
phase offset
'<PP\-ul' (degree)
(degree)
(degree)
' PPA-vL' (degree)
0
0
0
0
Downlink Ch-1
Downlink Ch-2
Downlink Ch-3
Downlink Ch-4
phase offset
phase offset
phase offset
phase offset
'<PPi-DL' (degree)
0
T(
>P3-dl ' (degree)
PP2-DL' (degree)
0
0
103
' <PP4-dl ' (degree)
0
The system with AGC was tested for signal power level transmitted, Pt, from the source
in the range from 0.00 lmW to lO.OmW. System test results for this power range are
summarized in the Table 4.2.
Table 4.2 Performance results of the retrodirective trasnceiving system (RTS) with AGC
- No impairments in the wireless channel
Power transmitted
from the source 'P t '
(mW)
10
Power received at the
source 'P r ' with Phase
Conj at the RTS (dBm)
13.042
EVM of the data with
Phase Conj at the
RTS (%)
1
10.957
2.917
0.1
11.644
2.030
0.01
10.620
1.556
0.001
5.613
1.299
5.350
From the results in Table 4.2, it is clear that AGC can control the power level in the range
from O.OlmW to 1.0 mW power transmitted from the user end or source. AGC output for
this range is around a fix value of around lldBm. The levels of lOmW or 0.00lmW are
out of the implemented AGC dynamic range and hence are not brought to the fixed level,
b) AGC test with the channel impairments
The channel noise level, N, of OA is considered in these results. Channel random phase
shift,
Vrandom'varied between 0°and 15°. Further parameter settings for AGC testing of
the retrodirective trasnceiving system with the impaired channel are given in Table 4.3.
The system implemented with AGC was tested for signal power level, Pt, transmitted
from the source in the range fromO.OOlmW to lO.OmW.
104
Table 4.3 Parameter settings for testing the retrodirective trasnceiving system (RTS) with
AGC - Impaired channel
Channel noise
Channel frequency
RF/DC Phase
RF/DC
level' N'
offset Uplink
imbalance
gain imbalance
' foffset '(KHz)
' PKbatance' (degree)
^imbalance (dB)
0.1
0.2
1.0
0.1
Uplink Ch-1
Uplink Ch-2 phase
Uplink Ch-3 phase
Uplink Ch-4
phase offset
offset' (pp2_UL'
offset' <pp3_UL'
phase offset
(degree)
(degree)
0
0
0
0
Downlink Ch-1
Downlink Ch-2
Downlink Ch-3
Downlink Ch-4
phase offset
phase offset
phase offset
phase offset
' <PPX-DL' ( d e g r e e )
' Vpi-DL' (degree)
0
0
' <Ppx-uL' (degree)
i(
PPi-DL'
(degree)
0
' <PPA-UL
' (degree)
' <,VPI-DL ' (degree)
0
Shown in Figure 4.13 and Figure 4.14 are the sample results of the system with other
impairments in the channels. When the phase offsets on all four uplink (UL) and
downlink (DL) channels were independent of each other: UL phase offsets of 0, 5, 10, 15
degree randomly varied in the full plus minus ranges but DL always kept at 10 degree,
the following (Figure 4.13(b) TL constellation ) results were observed at the user end or
source. The signal from all channels are not observed adding constructively at the source
end. Over the test run time, an EVM of 23.081% is captured, which is not a practicle
value, and the phase error observed is huge with an absolute value of about 35 (Figure
4.13(b) TR). When the phase offsets of corresponding UL and DL channels were same
always: UL 0, 5, 10, 15 randomly varied in the full plus minus range and DL channels
always followed them instantaneously, the following (Figure 4.13(b) BL constellation)
results were observed at the source. The signal from all channels are observed, over the
run time, adding constructively at the source, with an EVM of 6.421%, a very practicle
value, and phase error is minimal with an absolute value of about 9 (Figure 4.13(b) BR).
105
EVM without phase
conjugation (%)
23.081
EVM with phase
conjugation (%)
SER without phase
conjugation
2.0E-23
SER with phase
conjugation
6.421
2.0E-23
RF mean power without phase
conjugation (dBm)
10.851
RF mean power ' PR' with phase
conjugation (dBm)
11.016
(a) Test results of the system: EVM, SER and Power Level
Time (828.1nsec to 999.8usec)
Time (828.1nsec to 999.8usec)
(b) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj;
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
Figure 4.13 Test results of the retrodirective transceiving system with the AGC for a
signal power Pt of 1 .OmW transmitted from the source - Impaired channel
106
EVM without phase
conjugation (%)
29.561
EVM with phase
conjugation (%)
SER without phase
conjugation
0.011
SER with phase
conjugation
39.555
0.118
RF mean power without phase
conjugation (dBm)
10.705
RF mean power ' PR' with phase
conjugation (dBm)
10.828
(a) Test results of the system: EVM, SER and Power Level
Time (175.0nsec to 999.2usec)
Time (175.0nsec to 999.2usec)
(b) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj;
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
Figure 4.14 Test results of the retrodirective transceiving system with the AGC for a
signal power Pt of 0.0 l m W transmitted from the source - Impaired channel
107
Note from the test results shown in Figure 4.14 that for transmitted signal power, Pt, of
value O.OlmW from the source, AGC does not work when there are other impairments in
the channel. EVM is 39.555% which is very large and is not a practical value. The small
power level with the high levels of channel noise, channel frequency offset, and
imbalances in direct conversion receiver gain and phase, shown in Table 4.3, make PLL
behaviour worse because the PLL was designed only for small offsets.
The mean power level received, Pr, at the source with phase conjugation, shown in Figure
4.13(a) and Figure 4.14(a), for Pt values of l.OmW and O.OlmW, is 11.016dBm and
10.828dBm respectively. The EVM values are 6.421% and 39.555% respectively. The
later is not a practicle one hence the corresponding mean power, effectively noise, is
useless.
From the results presented above for the AGC tests, it can be concluded that the uplink
received signal power level can be controlled (within ldB) by the AGC in the range of
O.OlmW to l.OOmW; such variation amounts to 100 times, or 20dB change in power.
Without channel impairments the noise performance is better. However, with the other
impairments such as high frequency random noise, the signal EVM measured at the
source is poor especially at power transmitted, Pt, of O.OlmW from the source. This may
be because of the AGC large settling time of around 5^sec in the simulated system
model. It can handle other channel impairments but with poor noise performance.
4.6.2 EVM Pattern Simulations
EVM pattern of the retrodirective transceiving system was measured for given angles of
signal reception from the source.
For pattern testing, the carrier frequency was taken as 2.4 GHz, with a symbol rate of
1MSPS (QPSK signal) and 20 samples per symbol. Power transmitted from both the
108
source, Pt, and the retrodirective transceiving, PRTS, ends is set at lmW. The AWGN
noise level, N, set to 0.1, the channel frequency offset, foffset, is set to be 1.2KHz, phase
offset sensitivity to a maximum of ±15 degree, direct-conversion receiver gain
imbalance, Phmhakmce, of 0.1 dB and phase imbalance, Gimbalance, of 1 degree. Simulation
data was collected for 2p.sec. For the results given below all channels are set without
AGC.
The random phase noise, (prandom, is generated as follows. A variable phase offset for
each channel is generated by a voltage control signal (+1V, 0, -IV) and phase shift
sensitivity (maximum ±15 degree/volt in our case). In other words, with a control signal
of IV and phase shift sensitivity of +15 degree phase shift added to the instantaneous
phase value of a data symbol transmitted from the source would be +15 degrees. For
example, a transmitted data symbol with an instantaneous phase of 45 degree will be
rotated and will have phase angle of 60 degrees in the IQ constellation diagram at the
receiver (RTS) side.
It normally would be necessary to see the system performance for different incident
angles 6t of the received wave front from the illuminating source and RTS antenna array
transmission angle Qa varied in the range of ±180 degree.
In our simulations this mechanism is achieved by varying channel phase offset values in
uplink paths (<ppl_UL, <pp2_UL, <pp3.UL, cppA-UL) and downlink paths (<ppl_DL, (ppl.DL, <Ppi-DL,
VpA-Di )• The system radiation pattern is indirectly tested for 6 a in the range of ±90 degree.
The system retrodirectivity performance with a negligible beam pointing error over
random phase offsets range of ±15 degree is tested.
Detailed radiation and EVM pattern test results of the RTS system with four channels for
incident uplink channels's phase offsets q>pX_UL, (pp2-ui. > cPPi-nL >
°f 0°,0 o ,0 o ,0° ,
and the RTS downlink transmission phase offsets (ppi_DL, <pp2_DL, (pp3_0/j, (PP4-DL varied
109
(manually
in
steps
of
maximum
30
degree)
from
90 o ,50 o ,-50 o ,-90°
to
-90°,-50°,50°,90° respectively, were plotted. Example results are shown in Figure 4.15
to Figure 4.17. The channel noise level of 0.1 is considered in these results.
Channel noise
Channel
RF/DC Phase
RF/DC
level
frequency offset
imbalance
gain imbalance
Uplink' foffm '
' Phimbalance '
(KHz)
(degree)
0.1
1.2
1.0
0.1
Uplink Ch-1
Uplink Ch-2
Uplink Ch-3
Uplink Ch-4
phase offset
phase offset
phase offset
phase offset
Ppi-uL' (degree)
' ^PpA~uL' (degree)
0
0
'N'
i(
Pp\-vi (degree)
0
t(
i(
PP2-uL' (degree)
0
^imbalance
'
(dB)
(a) Parameters for radiation pattern testing of the retrodirective trasnceiving system
EVM without phase
conjugation (%)
44.912
EVM with phase
conjugation (%)
SER without
phase conjugation
0.093
SER with phase
conjugation
13.453
2.0E-23
RF mean power without phase
conjugation (dBm)
0.152
RF mean power ' Pr' with phase
conjugation (dBm)
-0.586
(b) Test results of the system: EVM, SER and Power Level
110
Time (228.1nsec to 999.2usec)
Time (675.0nsec to 999.7usec)
Time (228.1nsec to 999.2usec)
Time (28.1nsec to 999.2usec)
(c) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
4.15 RTS EVM results for <ppl_DL, (pp2_DL, cpp2„DL, cpp,_DL= 90°,50° -50°
EVM without phase
conjugation (%)
23.143
EVM with phase
conjugation (%)
SER without phase
conjugation
2.0E-23
SER with phase
conjugation
6.857
2.0E-23
RF mean power without phase
conjugation (dBm)
10.129
RF mean power ' Pr' with phase
conjugation (dBm)
10.118
(a) Test results of the system: EVM, SER and Power Level
Time
Time (631.2nsec to 999.6usec)
Time (75.0nsec to 999.1usec)
(631.2nsec
to
999.6usec)
Time (75.0nsec to 999.1usec)
(b) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj;
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
Figure 4.16 RTS EVM results for <ppX_DL, <pp2_DL , <pp3_DL, q>pA_DL = 0°,0 o ,0 o ,0°
112
EVM without phase
conjugation (%)
44.743
EVM with phase
conjugation (%)
SER without
phase conjugation
0.754
SER with phase
conjugation
13.35
2.0E-23
RF mean power without phase
conjugation (dBm)
0.146
RF mean power ' Pr' with phase
conjugation (dBm)
-0.589
(a) Test results of the system: EVM, SER and Power Level
T i m e
Time (662.5nsec to 999.7usec)
Time (721.9nsec to 999.7usec)
(662.5nsec to 999.7usec)
Time (721.9nsec to 999.7usec)
(b) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj;
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
Figure 4.17 RTS EVM results for <ppX_DL, q>pl_DL , <pp3_DL, <ppA_DL = - 90°,-50°,50°,90°
113
Note that for EVM results, for (ppl_DL, q>pl_DL, g>p3.DL, <PP^DL = 0o,0°,0o,0° (broadside),
shown in Figure 4.16 that SER with and without phase conjugation is the same as 2.0E23. However, EVM in case of phase conjugation, 6.857%, is much improved when
compared with the corresponding value of 23.143% obtained without phase conjugation.
This is because, at broadside, the signal strength is strong enough so that, even without
phase conjugation, system is able to recover all data quite accurately, although with a
very poor EVM.
From Figure 4.15 to Figure 4.17 and some measurements that are not plotted the system
EVM and radiation pattern results in terms of of EVM, SER, and RF power received at
the source end are sammarized in Tables 4.4 and 4.5.
Table 4.4 EVM pattern of retrodirective transceiving system (RTS) without phase
conjugation (channel frequency offset, foffsel, of 1,200KHz, and noise level,
N , of 0.1)
Received
Signal
Incident
Angle*
(degree)
0, 0, 0, 0
Retransmitted
Signal Angle**
(degree)
EVM
without
Phase Conj
(%)
RF power
without
Phase Conj
(dBm)
SER
without
Phase Conj
90, 50, -50, -90
44.912
0.152
0, 0, 0, 0
60, 30, -30, -60
28.832
5.919
0.093
0.001
0, 0, 0, 0
40, 20, -20, -40
25.378
7.742
2E-23
0, 0, 0, 0
20, 10,-10, -20
23.686
8.745
2E-23
0,0,0, 0
0, 0, 0, 0
23.143
9.066
2E-23
0,0,0,0
-20, -10, 10, 20
23.585
8.745
2E-23
0, 0, 0, 0
-40, -20, 20, 40
25.180
7.741
2E-23
0, 0, 0, 0
-60, -30, 30, 60
28.681
5.917
0.001
0, 0, 0, 0
-90, -50, 50, 90
44.743
0.146
0.754
The* (PPx-i,L, (Ppi-ui> <PP3-u,., <PP4-ui., and ** <ppX_DL, (pp2_DL, (pp3.DL, <pp4^DL are channel
phase offset values in uplink and downlink paths, respectively.
114
Table 4.5 EVM pattern of retrodirective transceiving system (RTS) with phase
conjugation (channel frequency offset, foffsel, of 1.200KHz, and noise level,
N , of 0.1)
Received
Signal
Incident
Angle*
(degree)
0, 0, 0, 0
Retransmitted
Signal Angle**
(degree)
EVM
with
Phase Conj
(%)
RF power
with
Phase Conj
(dBm)
SER
with
Phase Conj
90, 50, -50, -90
13.453
-0.586
2E-23
0, 0, 0, 0
60, 30, -30, -60
8.140
5.891
2E-23
0, 0, 0, 0
40, 20, -20, -40
7.368
7.813
2E-23
0, 0, 0, 0
20, 10,-10, -20
6.952
8.858
2E-23
0, 0, 0, 0
0, 0, 0, 0
6.857
9.192
2E-23
0, 0, 0, 0
-20,-10, 10, 20
6.948
8.858
2E-23
0, 0, 0, 0
-40, -20, 20, 40
7.279
7.812
2E-23
0, 0, 0, 0
-60, -30, 30, 60
8.113
5.890
2E-23
0, 0, 0, 0
-90, -50, 50, 90
13.350
-0.589
2E-23
The * <ppX
-IN > (PPI-UL* <PPI-UL' (PP4~I/I.'
an
d
**
<PP\-DL> (PP2-DI.
'
(
PPI~I)I'
(
PP4-DI.
are channel
phase offset values in uplink and downlink paths, respectively.
Comparing the results of EVM and SER shown in Tables 4.4 and 4.5, it is very clear that
the system performance is very much improved when implemented with phase
conjugation. The EVM values with the phase conjugation in Table 4.5 are very much
improved when compared with the EVM values without phase conjugation in Table 4.4.
Also, the SER with phase conjugation is negligible. At broadside (both incident and
retransmission phase angles are 0, 0, 0, 0 degrees), the system implemented with phase
conjugation has the best EVM of 6.857%. This value is several times better than the
EVM value of 23.143% obtained with a system without phase conjugation. There is not
much difference in power finally received at the source because the system impairments
are introduced only in terms of random phase at known instances, which results in poor
EVM or Phase Error Magnitude not in Mean Power at the source end (in the case without
phase conjugation applied at the RTS end).
115
To investigate system performance further, the channel noise power and frequency offset
were changed. Channel noise level was increased from 0.1 to 0.2. The frequency offset
was varied between 0.2KHz to lOKHz. It was observed that strong random noise caused
increase of EVM but the retrodirective transceiving system could handle bigger channel
frequency offsets up to 2KHz easily. It was also noticed that settling time of 625nsec in
the current test did not change by altering the frequency offset and keeping the noise
level at 0.2. This is because the ADPLL is sensitive to abrupt phase offset and higher
noise levels but not to frequency offsets. To improve the system performance, an faster
ADPLL, with the low settling time AGC in the baseband, that can handle higher noise
and fast channel phase offsets, is then required.
Figure 4.18 shows a special case where the random phase offsets generated for the
system testing are increased beyond the limits of the ADPLL implemented for the
retrodirective system.
Channel noise
Channel frequency
RF/DC Phase
RF/DC
level
offset Uplink
imbalance
gain imbalance
' foffset '
(degree)
(KHz)
' Gimbalance ' ( d B )
0.1
1.2
1.0
0.1
Uplink Ch-1
Uplink Ch-2
Uplink Ch-3
Uplink Ch-4
phase offset
phase offset
phase offset
phase offset
'(Ppx-uL' (degree)
' <Ppi-ul ' (degree)
40
20
-20
-40
Downlink Ch-1
Downlink Ch-2
Downlink Ch-3
Downlink Ch-4
phase offset
phase offset
phase offset
phase offset
' <Pp\-dl ' (degree)
' VPI-DL' (degree)
90
50
4
^Pp3~uL' (degree)
' <PP3-dl ' (degree)
-50
'Vpa-ul* (degree)
I(
PPA-DL' (degree)
-90
a) Parameter settings for testing the retrodirective trasnceiving system
116
EVM without phase
conjugation (%)
55.853
EVM with phase
conjugation (%)
SER without phase
conjugation
0.803
SER with phase
conjugation
38.261
0.662
RF mean power without phase
conjugation (dBm)
-5.026
RF mean power ' Pr' with phase
conjugation (dBm)
6.755
(b) Test results of the system: EVM, SER and Power Level
Time (718.7nsec to 999.7usec)
Time (718.7nsec to 999.7usec)
(c) TL: Data without Phase Conj; TR: Phase Err Sequence without Phase Conj;
BL: Data with Phase Conj; BR: Phase Err Sequence with Phase Conj
Figure 4.18 Test results of the system, <ppX_UL, <pp2_UL, cpp3_UL, (pp^UL =
40°,20°,-20°,-40°, and <ppX_DL, cpp2_DL, <pp,_DL, <ppA_DL= 90°,50°,-50°,-90°
117
The channel frequency offset, foffset, of 1.200KHz, and noise level, N, of 0.1 was set for
this measurement.
Parameter settings are shown in Figure 4.18(a). Maximum channel
phase shift (prandom is set to be of ±15 degrees, which can add up in the uplink phase shift
of ±40 degrees to make a total phase shift of ±55 degrees at a given sampling instant.
This phase value is more than ±45 degrees, the maximum allowed phase shift in the
ADPLL currently implemented in the system. Figure 4.18(c) shows these settings do not
let the ADPLL recover the signal and phase conjugate it properly. Hence, data, even with
the phase conjugation, is not recovered and phase error sequence is also spanned over a
larger scale.
From the results presented in Figure 4.15 to Figure 4.18, and Table 4.4 and Table 4.5, it
is concluded that the system redirects the signal back towards the source and works
properly within the design specifications.
4.6.3 Performance Summary of the Simulated Retrodirective Transceiving System
Based on the foregoing analysis, we summarize the simulation results as follows.
Maximum workable channel phase shift is around 10 degrees (absolute value) with other
channel/receiver impairments in the system. If present, the fixed rotation in the
constellation is due to the fact that any phase offset in channel 1 is removed from the
signal and the equivalent offset is removed from the other three channels as well. This is
because the error signal/feedback signal generated from ADPLL in channel 1 is used for
all four channels. For example, the four-channel uplink phase offsets of 5, 10, 15, 20
degrees would effectively become 0, 5, 10, 15, respectively, but with the retransmission
phase offsets of 5, 10, 15, 20 degrees, the constellaton will rotate 5 degrees clockwise. As
this can be removed at the source end receiver, it would not cause system degradation .
For a noise level of 0.2 on all the uplink and downlink channels, required power
transmitted at the source end of l m W is sufficient but 0.1 mW is not.
118
At lower noise levels even at higher frequency offsets, the retrodirective transceiving
system performs well. Higher noise levels with higher rates of change can cause bigger
phase offsets at faster rates, which is more than the coherence bandwidth of the channel.
Further, they cannot be controlled by the structure of ADPLL (employed in the RTS)
which is currently designed for handling small phase errors.
For a channel frequency offset of 1.200KHz, EVM is poorer and phase error sequence
level larger than with the frequency offset is 0.200KHz. Nevertheless, SER is the same
because this is tested for QPSK signaling, and poorer EVM is still within a limit such that
the resulting symbols remain in the desired quadrants.
4.7 Hardware Implementation of the Retrodirective Transceiving System
The system shown in Figure 4.7 to Figure 4.9 was developed. Following is the
description of precisely what was used to build the prototype and how the testing was set
up.
4.7.1 Hardware Used, Design Notes, and Signal Processing
Following is the breakdown of the hardware used, performance measures taken, and a
procedure for the system signal processing.
a)
Hardware Used
1) Source end: UL signal generator: Agilent's E4438C ESG signal generator. Carrier
power P, = 24dBm (ESG output of 2dBm with Mini-Circuits amplifier ZQL2700MLNW+ having a power gain of 22dB)
2) Source antenna: Monopole
3) RTS end antenna array: 4-element patch antenna array, mutual gap between
elements is half wavelength
119
4) RTS front-end (FE) receiver: Each channel uplink (UL) direct conversion RF/DC
at 2.4GHz, MAXIM MAX2701EVKIT, at 2.4GHz LNA gain of 1 ldB
5) ADC: TI ADS5282EB 8-channel 12bit serial output ADC with 10MHz to 60MHz
external frame clock, 1MHz to 10MHz analog baseband IQ signals input to ADC
6) DSP
Implementation
Advanced
of RTS: processor,
LATTICE
LatticeECP2
FPGA
Evaluation Board, reconfigurable DSP; Programming software,
Verilog programming using ispLEVERv7.2; Register transfer level (RTL) design
and time domain simulation done with Mentor Graphics' ModelSim and Aldec's
Active HDL; Architecture, reconfigurable IOs onboard FPGA;
7) DAC: Analog Devices's AD5449EB dual channel 12bit serial input DAC, used
four evaluation boards
8) RTS front-end (FE) transmitter: Each channel downlink (DL) direct conversion
RF/UC at 2.4GHz, MAXIM MAX2721 EVKIT and MAX2830EVKIT (with
MAX2831 IC placed on it)
b)
Design Notes
1) DSP processing (ADPLL settling time and data storing time, etc.)
should be
multiple times faster than the inverse of the coherence bandwidth of the channel
(RMS delay spread of around 50nsec in the indoor channel) [4-8]
2) ADPLL lock-in frequency range, roughly twice the loop BW, should be enough to
lock within the frequency offsets present in the carrier rendered by VCO reference
frequency sources on both transmit and receive sides including the Doppler drifts
in case if the channel dynamics are changing.
3) Considering channel coherence time in the order of 0.07sec [3-13] at 2.4GHz in
the lab environment for half-duplex communications a time division duplexing
scheme that switches between the transmit and receive functions within the
coherence time must be employed.
4) SAW filters should be used before the LNAs in order to select ISM frequency
band. External LPF should be employed between the VGAs on board RF/DC
120
MAX2701 EVKIT. This will help minimize the interference from the adjacent
channels.
5) AGC should be used used to average the power level of all four channels to the
same value. This will help increase the dynamic range of the ADC and effectively
ADPLL lock in range.
c)
Signal Processing
1. Signals received by four-patch antenna array were downconverted to baseband
and then baseband IQ signals were digitized by ADC. This digital data was passed
on to FPGA for further processing.
2. Frame clock recovery was done using IP cores obtained from FPGA vendor.
Complex carrier recovery (CR) near baseband was performed with all-digital
phase-locked loop (ADPLL) designed in FPGA and discussed in Chapter 3.
3. Geometry/carrier phase near baseband was recovered from the reference channel,
ch-1, using the ADPLL. The conjugate of this phase was implemented in the
mixer multipliers of the ADPLL. The same process was applied to the remaining
three channel mixers.
4. Phase recovered from the reference channel was used in the remaining three
channels
thus
effectively
locking
on
to
the
same
phase.
The
signal
information/message phase recovered for the remaining three channels was thus
relative to the reference channel (in the locked mode at the standard constellation
points) phase. Thus any constant phase multiplier existing for all four channels
will be hidden and will not also matter for the beam pointing. The data received
was phase conjugated.
5. IQ data symbols were recovered and stored in the FPGA RAM after conjugation
6. Stored IQ data were transmitted through DACs (AD5449EB) at a rate of 455.69
KHz (maximum achievable with the current architecture) for direct up-conversion
atRF.
121
4.7.2 Test Setup
The system prototype was built according to the system architecture shown in Figure 4.7
to Figure 4.10. Figure 4.19 shows a snapshot where MAX2721 EVKIT RF upconverters
were used for the system testing. Figure 4.20 shows a snapshot where MAX2830EVKIT
RF transceivers were used for the system testing. The user end or source is shown as a
monopole antenna placed on a table shown in the right side of the Figure 4.19.
Patch antenna array
Source or User End
(Monopole antenna)
RF Downconverters
Figure 4.19 Test setup of 4-channel retrodirective transceiving system prototype with
MAX2721 EVKIT RF-Upconverter
122
Figure 4.20 Test setup of 4-channel retrodirective transceiving system prototype with
MAX2830EVKIT RF-Transceiver
4.8 Test and Measurement Results
4.8.1 Baseband (BB) Test
To verify that the system can receive the clean baseband signal, the baseband signal is
first digitized with ADC, processed with the designed FPGA platform, and then
converted back to analog domain using the DAC. The following tests were performed.
Refer to the system architectural diagram of Figure 4.7. This test was performed by
replacing the RF direct downconverter MAX2701 EVKIT with a standard baseband
123
waveform generator. The signals were pro cessed through the FPGA based-baseband
firmware developed. The DAC5449EB outputs were received and analysed at a standard
digitizing scope.
The In-Phase and Quadratue signals, without comprizing any internally generated signal
impairments from a standard source such as Agilent's Vector Signal Generator, were split
into 4 In-phase and 4 Quadraure signals. These signals were then input to ADC with eight
input channels (chl-I, chl-Q, ch2-I, ch2-Q, ch3-I, ch3-Q, ch4-I, ch4-Q). The digitized
output signals were then processed using the ADPLL embedded in the FPGA. The output
I and Q signals from all the four channels were stored in FPGA RAM and then input to
four dual channel DACs (DAC ch-1 to DAC ch-4). The outputs of the DACs were
observed at the Agilent's Infiniium 5483 ID MSO 600MHz 4GSa/s scope and read
through VSA89600 software at a PC. The results are shown in Figure 4.21 to Figure 4.24.
Received signal
IQ constellation
Received signal
Error Vector vs Time
Received signal
Symbol rate
Sjiftgifeflt896G0 Vector Sg
i nal
Figure 4.21 Measured results: BB Ch-1 output with input datatype 41s40s
124
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observed locked (white strip in the bottom left quadrant)
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125
Figure 4.24 Measured results: BB Ch-2 phase conjugated output with input data type
PN23
The results in Figure 4.21 to Figure 4.24 for Channel-1 and Channel-2 show that the
baseband part works well as data type 41s40s and random data type PN23 can be
reproduced clearly after processing through the system. The system behavior for
Channel-3 and Channel-4 was observed with similar performances. In Figure 4.22, the
received QPSK symbol rate at ADC input is 10MSPS and transmitted rate from DAC
output is 455.6915KSPS. It is observed that the data pattern that was originally sent into
the system is searched and found locked when analyzed at output of DAC. A white strip
in the bottom left quadrant shows locked data pattern of 41s40s.
Vigilance is required when using the test equipment for measurements of level and phase
critical signals. For example, in Figure 4.25 and Figure 4.26, a scope signal constellation
read at VSA software is captured for investigation.
126
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a power range of negative 1 OdBm
i
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a power range of negative 2 8 dBm
127
Selecting a proper sensitivity range for a given signal level and digital phase information
to be captured is very critical. A sample data-constellation captured on the VSA software
with a power range of negative lOdBm (Figure 4.25) is observed as good. When the
range is set to negative 28dBm (Figure 4.26), the constellation is observed as distorted.
This is because fixed phase noise offset from the signal spectrum side bands can add up
and result in a bad signal which might be meaningless in the true sense. Similarly
measurement frequency span is very critical: it must be set at least twice the bandwidth of
the input signal to be measured.
4.8.2 RF Downconverter MAX2701EVKIT and Baseband Test
The behavior of the system with RF direct downconverter (RF/DC) MAX2701 EVKIT
was studied as explained below. A RF downconverter was put in each channel as in the
system described in Figure 4.7. In this, the RF front panel output of the Agilent's
generator E4438C was used. The RF modulated signal, 2.43GHz QPSK at 10MSPS, was
split into four and each part was input to the corresponding channel downconverter. The
downconverted baseband (BB) outputs including the signal impairments introduced by
the downconverters were digitized by the ADC. It is observed that the IQ gain and phase
imbalances introduced by the downconverters distort the signal and increase the EVM as
depicted by the results in the Figure 4.27 to Figure 4.31.
128
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129
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Figure 4.29 Measured results: RF/DC-BB Ch-2 phase conjugated output with input data
type 41s40s
Figure 4.30 Measured results: RF/DC-BB Ch-3 phase conjugated output with input data
type random PN23
130
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Figure 4.31 Measured results: RF/DC-BB Ch-4 phase conjugated output with input data
type 41s40s
From the results shown in Figure 4.27 to Figure 4.31, when compared with the results in
Figure 4.21 to Figure 4.24, it can be noticed that RF/DC's amplitude and phase
imbalance is not completely compensated by ADPLL. ADPLL is designed with a
limitation to recover only small valued phase errors and also is not meant to deal with the
amplitude imbalance. An AGC is required to deal with the amplitude impbalance. The
system was modeled with AGC in Agilent's ADS2009 simulation package but it has not
been yet implemented in the hardware. The system prototype performance is expected to
be improved by AGC.
When the clean baseband signals were RF upconverted by MAX2721 EVKIT similar kind
of effects was observed in the signals at the output of the converter.
131
4.8.3 Baseband and RF Upconverter MAX2830EVKIT
The behaviour of the RF updown converter in the transceiver MAX2830EVKIT was
explored as well. In this test, the IQ output of the Agilent's signal generator was used as a
baseband signal. A QPSK signal at 10MSPS was split into four and each part was input
to the corresponding channel of ADC. The data processed in baseband was input to
DACs, and the output signals were upconverted at a frequency of 2430MHz. The
upconverted signals were received at Agilent's PSA series Spectrum Analyser E4440A,
further LAN connected to a PC with VSA 89600 software installed. The test results are
shown in Figure 4.32 and Figure 4.33.
Figure 4.32 Measured results: BB-RF/UC output with input data type random PN23
132
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Figure 4.33 Measured results: BB-RF/UC output with input data type 41s40s
Transmitted symbol rate from FPGA cannot be increased more than 455.6915KSPS
because of the FPGA and DACs specification limitations. MAX283OEVKIT has RF/UC
with low pass filter (LPF) cutoff of 7.5MHz. So the signal of 455.6915KSPS is distorted
a lot in RF/UC. This distortion increases the EVM, as depicted by the results in Figure
4.32 and Figure 4.33, and is evident when compared with the results in Figure 4.21 to
Figure 4.24. All four channels had the same type of behavior. This distortion was more
evident here than when introduced by the RF/UC MAX2721 EVKIT.
This left us with the choice of testing the retrodirective transceiving system (RTS)
implemented with the MAX2701 EVKIT as receiver RF downconverter (four RF/DCs)
and the MAX2721 EVKIT as transmitter RF upconverter (four RF/UCs). Only two of
MAX2721 EVKIT boards commercially built were available in the lab (this product is
obsolete from the market now). Four prototypes of MAX2721 EVKIT evaluation boards
were built in the lab, but on the first try did not work well. So the final test of RTS was
performed using only two of them for two channel upconverter. This transceiver test is
discussed in Section 4.8.4.
133
4.8.4 A Complete Prototype of Retrodirective Transceiver System using RF/DC
MAX2701EVKIT and RF/UC MAX2721EVKIT
A complete system prototype was built according to the system architecture shown in
Figure 4.7 and Figure 4.9. The test setup is shown in Figure 4.19. MAX2701EVKIT was
used as RF/DC, with RF ports optimized for use at 2.4GHz. MAX2721 EVKIT was used
as RF/UC which is optimized for 2315MHz however at 2.43GHz its RF ports has input
reflection coefficient S l l of around -5dB which is quite poor (the only available
hardware at the time of test). To test the system functionality and proof of concept in half
duplex mode at the same Rx/Tx RF frequency the available hardware with poor RF
matchings was used. The system performance is expected to improve considerably with
the hardware specifically designed according to the system requirements. The antenna
array patch antennas input impedance is matched for use at 2.43GHz. So the RF/UC to
antenna ports are not matched well hence distortion because of multiple reflections from
the ports is expected. Due to the fact that not all the required hardware with the specs as
per the design was used in the prototype, the presented RTS has a limited performance.
With this available hardware, the transceiving system was tested the results for two
channels are presented below.
The signal generated from the source using Agilent's Vector Signal Generator, a medium
power amplifier and a monopole antenna was 2.43GHz QPSK at 10MSPS. At a wireless
distance of 1.5meter, this signal was received by the 4-channel retrodirective system
using a 4-element patch antenna array. Then it was down converted by direct conversion
receiver in each channel. It was then converted to digital domain by the eight channel (4
Is and 4 Qs) 12 bit serial ADC. These digital signals were passed on to the FPGA board
for processing. The signals were frame aligned by using clock recovery PLL on board
FPGA. This helps reducing the noise floor and increasing the SNR and eventually results
in an improved SER and BER. The digital I and Q signals from channels were used as
input to ADPLL discussed earlier. The locked output of channel one was used as
reference and the remaining channels' data was processed for finding their relative phase
134
w.r.t. channel-1. FPGA RAM was used to hold 1024 samples of channel-1 output data.
Final data from channel-2 to channel-4 was phase conjugated and 1024 samples time
aligned with channel-1 were also stored in the FPGA RAM. These digital signals were
then converted to the analog domain using four dual-channel 12 bit serial DACs. Four
(chl_I, chl_Q, ch2_I, ch2_Q) out of these eight analog signals (41s and 4Qs) were
upconverted using direct upconverters and transmitted from RTS at 2.43 GHz QPSK at
455.6915KSPS (maximum possible with current hardware). For transmission the same
patch antenna array was used in a half duplex fashion. These processed, phase conjugated
signals and transmitted from RTS system were received back at the source. After passing
the assumingly reciprocal channel, the signal was sent to and analyzed at Agilent's PSA
Spectrum Analyzer. The data was captured at a PC using VSA 89600 software to analyze
the accuracy of the signal constellation received, to measure EVM, and to see if a known
sent data pattern can be recovered from the received signal. The screen shots of the
results are shown in the figures below. The measured radiation pattern performances of
retrodirective transceiving system (RTS) with phase conjugation for various illumination
angles of the source antenna are presented below.
a) Retrodirective system with the source incident angle 9t = 0° - data type 41s40s
The results of the retrodirective system with the source incident angle 6. = 0° and data
type 41s40s are shown in Figure 4.34 to Figure 4.37 below.
135
Figure 4.34 Measured results: Retrodirective transceiving system (one channel only)
- Source incident angle 6> = 0° and RTS transmission relative angle 0a = 0°
Figure 4.49 Measured results: Retrodirective transceiving system - Source incident angle
6> =-30°and RTS transmission angle 0a = -30°
136
Figure 4.36 Measured results: Retrodirective transceiving system - Source incident angle
<9, = 0° and RTS transmission angle 0a = 20°
Figure 4.49 Measured results: Retrodirective transceiving system - Source incident angle
6> =-30°and RTS transmission angle 0a = -30°
137
The results of the retrodirective system with the source incident angle 0i = 0° and data
type 41s40s shown in Figure 4.34 to Figure 4.37 alongwith some extra observed test
values which are not plotted in the figures are summarized in Table 4.6.
Table 4.6 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 0t = 0°
Received Signal
Incident Angle
(degree)
Retransmitted
Signal Angle
(degree)
EVM with
Phase Conj
(%)
0
0+45
0
0
0+20
9.9381
0+10
6.1636
0
0+0
2.7368
0
0-10
6.3402
0
0-20
9.2513
0
0-45
-
The EVM of 2.7368% (shown in Figure 4.35) at the source obtained with the 2-channel
RTS is better than 3.6313% (Figure 4.34) which is obtained with single channel
transmission only. Further it is clear that the best EVM is achieved when RTS
transmission is oriented in the direction of reception of the wavefront from the Source.
b) Retrodirective system with the source incident angle di = 1 0 ° - data type random
PN23
The results of the retrodirective system with the source incident angle 0t =10° and data
type random PN23 are shown in Figure 4.38 to Figure 4.43 below.
138
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- Source incident angle 0t =10° and RTS transmission relative angle 6 a = 0°
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139
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6>= -30° and RTS transmission angle 0a = -30°
140
Figure 4.42 Measured results: Retrodirective transceiving system - Source incident angle
0t = 10° and RTS transmission angle 9 a = - 6 0 °
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6>
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141
The results of the retrodirective system with the source incident angle 6> = 10° and data
type random PN23 shown in Figure 4.38 to Figure 4.43 along with some extra observed
test values which are not plotted in the figures are summarized in Table 4.7.
Table 4.7 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 6• =10°
EVM with
Phase Conj
(%)
Received Signal
Incident Angle
(degree)
Retransmitted
Signal Angle
(degree)
10
10+30
10
10+15
12.087
10
10+0
9.9193
10
10-15
11.115
10
10-30
12.557
10
10-45
10
10-60
17.467
10
10-85
16.142
-
-
The EVM of 9.9193% (Figure 4.39) at the source obtained with the 2-channel RTS
having implemented init phase conjugation technique is better than 11.129%, shown in
Figure 4.38, which is obtained with single channel transmission only. Further, is it clear
that the best EVM is achieved when RTS transmission is oriented in the direction of
reception of the wavefront from the source.
c) Retrodirective system with the source incident angle 0t = -30° - data type
random PN23
The results of the retrodirective system with the source incident angle 6, = -30° and data
type random PN23 are shown in Figure 4.44 to Figure 4.51 below.
142
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- Source incident angle 6i = - 3 0 ° and RTS transmission relative angle 6a = 0°
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6>
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143
Figure 4.46 Measured results: Retrodirective transceiving system - Source incident angle
9, = - 3 0 ° and RTS transmission angle 9a= 15°
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6>
= - 3 0 ° and RTS transmission angle 0a = -30°
144
Figure 4.48 Measured results: Retrodirective transceiving system - Source incident angle
0, = - 3 0 ° and RTS transmission angle 0a = 45°
Figure 4.49 Measured results: Retrodirective transceiving system - Source incident angle
6> = - 3 0 ° and RTS transmission angle 0a = -30°
145
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<9, = - 3 0 ° and RTS transmission angle 0 a = -45°
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6> = - 3 0 ° and RTS transmission angle 0a = - 3 0 °
146
The results of the retrodirective system with the source incident angle 0 = -30° and data
type random PN23 shown in Figure 4.44 to Figure 4.51 are summarized in Table 4.8.
Table 4.8 Measured EVM of retrodirective transceiving system (RTS) with phase
conjugation - Source incident angle 0, = -30°
Received Signal
Incident Angle
(degree)
Retransmitted
Signal Angle
(degree)
EVM with
Phase Conj
(%)
-30
-30+60
-30
-30+45
18.193
-30
-30+30
47.664
-30
-30+15
13.150
-30
-30+0
10.812
-30
-30-15
15.999
-30
-30-30
27.208
-30
-30-45
18.559
-30
-30-60
40.086
-
The EVM of 10.812% (Figure 4.45) at the source obtained with the 2-channel RTS
having implemented init phase conjugation technique is better than 14.670%, shown in
Figure 4.44, which is obtained with single channel transmission only. Further, it is clear
that the best EVM is achieved when RTS transmission is oriented in the direction of
reception of the wavefront from the source. In Figure 4.47 the sudden unexpected
change/fading (EVM 47.664%) may be is caused by human movement in the lab
environment.
147
4.8.5 Discussion on RTS Pattern Measurements
Some EVM measurement values at angles away from the direction of the incident angle
are not what is expected theoretically; it should be poorer than the value with reference to
the one at the receive angle. The unexpected behavior of improvement in EVM such as
18.559% in Figure 4.50 at higher offset (6 a = - 4 5 ° ) from the incident angle (6> = - 3 0 ° )
can be attributed to multiple factors such as sudden changes in channel conditions, as
receive and transmit processes were done in a half duplex fashion. Manually, the antenna
at the Source was connected from a Generator (source in transmit mode) to the Spectrum
Analyzer (source in receive mode) in finite time of around one minute (processed data
was held in the FPGA RAM for that time) which can be more than the coherence time of
the channel.
4.9
Conclusions
This chapter presents the third part of the orginal contributions by this thesis (also
mentioned in Section 1.3): a complete 4-channel retrodirective transceiver system (RTS)
with digital signal demodulating capabilities for a symbol rate of 1MSPS (extendable
upto 10MSPS) QPSK. The system was implemented on a reconfigurable low-cost field
programmable gate array (FPGA) platform and experimentally validated with limited
performance results for two channels in a real wireless lab environment. More
specifically, in comparison with existing systems, the following distinctions have been
made:
a) Digital demodulation capabilities at high data rates of upto 10MSPS QPSK
b) Implementation on a low-cost reconfigurable FPGA platform
c) Complete retrodirective transceiver system (RTS) practical demonstration
148
CHAPTER 5
SUMMARY AND PROPOSED FUTURE WORK
The original contributions of the thesis lie mostly in the development of new techniques
and technologies for advanced communication systems; the contents are diverse in nature
and more work can be done in the future.
These contributions and future
recommendations are summarized as follows.
5.1 Summary
Based on the background and the-state-of-art of the synchronization, signal demodulation
and retrodirective classical transceivers outlined in Chapter 1, further advancements
needed novel signal synchronization and digital designs and techniques for digital and
microwave transceivers. Such needs formed the motivations for this thesis, leading to
new research and development in injection-locking techniques for high-speed signal
synchronization, all-digital solutions for radio reconfigurability and modern digital
implementation of a multi-channel retrodirective system on a low cost FPGA platform. A
summary of this work has been presented at the end of Chapters 2, 3, and 4, and therefore
needs not to be repeated here. Neverthless, the key points are summed up as follows.
In Chapter 2, simple injection-locked oscillator (ILO) has been developed with a low
noise feature. It has presented potentials in developing fast RF synthesizer and simple
front-ends for low-cost wireless and mobile communication transceivers.
Next, the direct carrier recovery, from PSK signals, using ILO technique has been
proposed. It is shown to have tremendous potential to perform coherent demodulation of
wideband signals just at an RF front-end in a very simple way. The limitation of small
locking range is considered to be the biggest hindrance in using the ILO at the very front
end. On the other hand, it can make carrier recovery possible from high data rate analog
or digitally modulated signals. The weakness is turned into a quality feature of carrier
recovery and it is used for high speed coherent demodulation.
149
This ILO-based technique of direct carrier recovery and synchronization has also been
implemented in a direct conversion receiver architecture for the single channel digitally
microwave signal such QPSK. Further, with the careful design and integration of
multiband dielectric resonators and sharp cutoff multipass bandpass frequency-tunable
filters, it has been extended to a multi-channel high symbol rate of upto 63MSPS
receiver. It is expected that receiver synchronization achieved this way just at the frontend will, in addition to reducing the computational burdens on the digital communication
systems processors, improve its performances such as S/N ratio, BER and EVM.
Chapter 3 presented a complete suite of implementing a novel practical ADPLL working
with the actual hardware in the realistic wireless environment. The implementation
details, engineering and maths of the ADPLL for all the design and implementation
stages have been shown.
In Chapter 4, a complete retrodirective transceiving system (RTS) with 4-channel
functionality with new hardware is built. First, the system with complete 4-channel
retrodirective functionality was modeled including an automatic gain control (AGC) in
the baseband. Then, the system was simulated and programmed into a digital code. In the
next step, it was embedded in a reconfigurable low-cost FPGA board. Finally, the
complete system prototype including RF front-end and analog baseband hardware was
built. Performance measurements of the system were obtained and experimentally
demonstrated for two channels only in the real wireless environment. This is a first
working prototype implemented on a FPGA platform particularly for a complete
retrodirective transceiver system (RTS).
Different setups for system testing have been discussed. Individually baseband, RF
upconverter, down converter and finally a complete transciving system prototype has
been presented. The test results presented are encouraging and uncover the potentials of
the retrodirective systems for the applications where the source location is unknown.
System implemented this way with high speed reconfigurable platform such as FPGA can
150
find applications in many advanced applications for adaptive multi-channel multimode
wireless communications, e.g. cell phone basestations or hotspot access points.
5.2 Proposed Future Work
Parametric performance analysis of the proposed ILO-based direct carrier recovery and
demodulation schemes has not been done. Specifically, system parameters such as
receiver electrical power consumption (especially for battery operated applications),
received signal level sensitivity and dynamic ranges, signal acquisition time, and
frequency locking range are to be considered.
For a given wireless application, the
evaluations of such parameters for each circuit model and actual prototype are desired.
This work is crucial for detailed functional comparisons of these ILO-based schemes with
the state-of-the-art synchronization and demodulation schemes. It should play a
fundamental role before moving towards the commercialization of these new systems.
Injection-locked direct down-conversion receivers are expected to function in a variety of
higher order modulation formats such as 16QAM and is a recommended part of future
work.
Adaptable all-digital PLL should have a great value for the future multiband wireless
transmissions,
especially
for software defined radio applications. This requires
developing complex but efficient algorithms in programmable digital platforms such as
FPGAs. This is also recommended as future work.
The development of a complete retrodirective transceiver system with IC chips for the
advanced wireless communications is likewise recommended as future work.
In addition, a hybrid system can be further pursued: in it, the fast speed acquisistion of
the ILO technique in the passband is combined with the reconfigurable ADPLL and DDS
151
in the baseband to produce a high speed and multiband intelligent transceiver for digital
wireless communications.
More specifically, ILO techniques discussed in Chapter 2 can be used in the analog
domain to recover the carrier from digitally modulated RF signals. Then, the baseband
ADPLL dicussed in Chapter 3 will be used to further enhance the SNR to improve the
BER. Finally, for transmission, an advanced version of DDS in combination with ILO
will be used as a stable LO source.
The second-harmonic-ILPLL-based BPSK-to-ASK converter and ILO-based direct
carrier recovery receivers for QPSK signals, discussed in Chapter 2, have not been
demonstrated in a real wireless environment yet. This should be a part of future work.
The all-digital PLL discussed in Chapter 3 and retrodirective transceiver system (RTS)
discussed in Chapter 4 hardware prototypes do not have automatic gain control (AGC)
circuitary implemented. An AGC is mandatory for real-world applications of these
systems. It has been shown that modeling the RTS with AGC can improve the
performance results. However, its implementation is challenging especially for wideband
signals in noisy wireless environments alongwith imperfections of the hardware used.
Implementation of AGC in the system prototypes should also be part of future work.
Applications of the retrodirective transceiving system (RTS) using injection locked
oscillator (ILO) for carrier recovery at the analog RF front-end for broadband wireless
access (BWA) networks are expected in future work as well.
It is apparent that the millimeter-wave transceiver with a very short sample period is
vulnerable to frequency offset, timing drift, and any nonlinearity caused by the instability
of 60 GHz RF components such as a low noise amplifier (LNA), voltage controlled
oscillator (VCO), and phase locked loop (PLL) [5-1]. In this line, at 60GHz with channel
bandwidth up to 7GHz (3.5GSPS QPSK), with line-of-sight (LOS)
directional
transmission, ILO-based direct carrier recovery (CR) can be very feasible. This is
152
because wider the channel BW is better the possibility for the direct carrier recovery, for
a given signal power level. This study is recommended as future work.
153
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