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Submicron gate indium gallium arsenide/indium phosphide microwave power transistors

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Order N um ber 92S2S48
Submicron gate indium gallium arsenide/indium phosphide
microwave power transistors
Johnson, Gregory A., Ph.D.
University of Cincinnati, 1992
UMI
300 N. Zeeb Rd.
Ann Arbor, M I 48106
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SUBMICRON GATE INDIUM GALLIUM ARSENIDE/INDIUM PHOSPHIDE
MICROWAVE POWER TRANSISTORS
— -
A Dissertation submitted to the
Division of Graduate Studies and Research
of the University of Cincinnati
in partial fulfillment of the
requirements for the degree of
DOCTOR OF PHILOSOPHY
in the Department of Electrical and Computer Engineering
of the College of Engineering
1992
by
Gregory A. Johnson
B.S.E.E., University of Cincinnati, 1 9 8 4
M .S ., University of Cincinnati, 1987
Committee Chair: Professor Vik J. Kapoor
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UNIVERSITY OF CINCINNATI
19J l
June 2
I hereby recom m end that the thesis prepared under
m y supervision by Gregory A. J o h n s o n _____________
entitled
Submicron Gate Indium Gallium Arsenide/Indium
Phosphide Microwave Power Transistors
be accepted as fu lfilling this part o f the requirements f o r
the degree o f
Doctor of Philosophy____________________
A pproved b'
iM & rn
J \ \ a vJQy)
f.
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SUBMICRON GATE INDIUM GALLIUM ARSENIDE/INDIUM PHOSPHIDE
MICROW AVE POWER TRANSISTORS
Abstract
by
Gregory A. Johnson
Indium gallium arsenide on indium phosphide (InGaAs/lnP) metalinsulator-semiconductorfield-effect transistors (MISFETs) with submicrometer
gate lengths were investigated for microwave power applications up to K-band
(18 - 2 6 .5 GHz) frequencies.
In order to gain experience with InGaAs/lnP processing technology,
depletion mode InGaAs microwave power MISFETs with 1 fjm gate lengths and
up to
1
mm gate widths were initially fabricated using an ion implanted
process. The devices employed a plasma deposited silicon/silicon dioxide gate
insulator. The RF power performance at 9 .7 GHz was investigated. The output
power, power-added efficiency, and power gain were determined as a function
of input power. An output power of 1.0 7 W at 9 .7 GHz with a corresponding
power gain and power-added efficiency of 4 .3 dB and 3 8 % , respectively, was
obtained.
The large gate width devices provided over twice the previously
reported output power for InGaAs MISFETs at X-band
( 8
- 1 2 .5 GHz).
In
addition, the first measurement of RF output power stability of InGaAs MISFETs
over a 2 4 hour period was also preformed. An output power stability within
1 .2 % over 2 4 hours of continuous operation was achieved.
A fter gaining processing experience with the one micron gate ionimplanted devices, depletion mode InGaAs microwave power MISFETs with
i
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0 .7 jjm gate lengths and 0 .2 mm gate widths were fabricated using an epitaxial
process.
The devices employed a plasma deposited silicon dioxide gate
insulator. The RF power performance at frequencies of 18 GHz, 2 0 GHz, and
23 GHz was investigated.
An output power density of 1 .0 4 W /m m w ith a
corresponding power gain and power-added efficiency of 3 .7 dB and 4 0 % ,
respectively, was obtained at 18 GHz. This is the highest output power density
obtained for an InGaAs based transitor on InP at K-band. Record output power
densities for an InGaAs MISFET were also obtained at 20 GHz and 2 3 GHz. An
output power density of 0 .8 9 W /m m with a corresponding power gain and
power-added efficiency of 3 .0 dB and 32% , respectively, was obtained at
20 GHz.
An output power density of 0 .7 7 W /m m was obtained at 23 GHz.
The corresponding power gain and power-added efficiency were 3 .4 dB and
2 7 % , respectively.
The output power was also demonstrated to be stable
within 3 % over 17 hours of continuous operation at 18 GHz.
Scatter parameter measurements were also performed on the submicron
gate InGaAs MISFETs over the frequency range of 10 - 20 GHz.
A thru,
reflect, line (TRL) calibration procedure was implemented in order to perform
the scatter parameter measurements.
Maximum stable gains of 13 dB and
10.5 dB w ere obtained at 10 GHz and 20 GHz, respectively. The maximum
unilateral transducer power gain cutoff frequency (fm a x ^ was about 50 GHz.
ii
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ACKNOWLEGDEMENTS
The author would like to thank Professor Vik J. Kapoor, his advisor, for
suggesting this dissertation topic and providing his guidance and support during
the course of this research. His initiative in recommending the preparation of
research proposals, submission of publications, and presentation of research
results at technical conferences is also greatly appreciated. Thanks are also
extended to the other members of the dissertation committee, which include
Dr. Pratim Biswas, Dr. Altan M. Ferendeci, Dr. H. Thurman Henderson, and
Dr. Kenneth P. Roenker.
The financial support provided by the National Aeronautics and Space
Administration - Lewis Research Center in Cleveland, OH, is gratefully
acknowledged. The encouragement of this research by Dr. Regis Leonard and
the use of NASA - Lewis facilities is also greatly appreciated. In addition, the
author would like to thank Dr. Sam Alterovitz, Dr. John Pouch, Dr. George
Ponchak, Mr. Bob Romanofsky, Dr. Charles Raquet, and Mr. Kurt Shalkhauser
of NASA - Lewis Research Center for their helpful suggestions, assistance,
encouragement, and use of equipment.
Thanks are also extended to Dr. Louis Messick and Mr. Richard Nguyen
of the Naval Ocean Systems Center in San Diego, CA, for encouragement of
this research and the use of NOSC facilities.
In addition, their technical
suggestions and assistance during the course of this research is greatly
appreciated.
The author would also like to thank Dr. Mike Biedenbender, Mr. Mohsen
Shokrani, Mr. George Lemon, Mr. Gurunathan Subramanyam, Mr. Alan
Hoofring, Dr. Paul Young, Dr. George Valeo, Mr. Jim Nahra, Dr. Dan Xu, Mr.
Dan Pantic, Mr. Peter Koeppe, and Mr. Dan Sater their help and suggestions
during various parts of this research.
The author also thanks Ms. Teresa
Hamad for assistance during the preparation of this dissertation.
Finally, the author thanks his w ife, Catherine, and his parents and family
for their love, support, and encouragement.
iv
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TABLE OF CONTENTS
PAGE
i
iv
v
vii
x
ABSTRACT
ACKNOWLEDGEMENTS
TABLE OF CONTENTS
LIST OF FIGURES
LIST OF TABLES
CHAPTER 1 INTRODUCTION
1.1 InGaAs Epitaxial Growth
1.2 InGaAs MISFET Technology
1.3 Research Objectives
10
CHAPTER 2 EXPERIMENTAL PROCEDURES
2.1 Ion Implantation
2 .2 Plasma Deposition
2 .3 One Micron Gate InGaAs MISFET Fabrication
2 .4 Submicron Gate InGaAs MISFET Fabrication
13
13
18
20
25
CHAPTER 3 RF MEASUREMENTS
3.1 Output Power Measurement Systems
3.1.1 One Micron Gate InGaAs MISFET
3 .1 .2 Submicron Gate InGaAs MISFET
3 .2 Scatter Parameter Measurements
3.2.1 Network Analysis Accuracy Enhancement
3 .2 .2 Thru, Reflect, Line (TRL) Calibration
3 .2 .2 .1 TRLCAL Program Development
3 .2 .2 .1 TRL Calibration Theory
32
32
32
36
39
40
44
46
51
CHAPTER 4 ONE MICRON GATE InGaAs MISFET RESULTS
4.1 InGaAs MISFETs with Silicon Dioxide Gate
Insulators
4 .1 .1
DC Characteristics
4 .1 .2 RF Characteristics
4 .2 InGaAs MISFETs with Silicon/Silicon Dioxide
Gate Insulators
4 .2 .1 DC Characteristics
4 .2 .2 RF Characteristics
63
CHAPTER 5 SUBMICRON GATE InGaAs MISFET RESULTS
5.1 InGaAs MISFETs with Silicon Dioxide Gate
Insulators
5.1.1 DC Characteristics
5 .1 .2 RF Characteristics
5 .1 .3 Scatter Parameter Measurements
80
v
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1
1
6
63
63
65
67
67
72
80
80
8 6
97
CHAPTER
6
DISCUSSION OF RESULTS AND CONCLUSIONS
6.1 One Micron Gate InGaAs MISFET
6.2 Submicron Gate InGaAs MISFET
6.3 Publications and Presentations
6 .4 Suggestions for Future Research
BIBLIOGRAPHY
119
119
121
127
129
133
vi
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LIST OF FIGURES
FIGURE
PAGE
Source/drain implant profile for one micron gate InGaAs
MISFET.
16
2 . 2
Channel implant profile for one micron gate InGaAs MISFET.
17
2.3
Schematic of plasma system chamber.
19
2 .4
Schematic cross section of one micron gate InGaAs MISFET.
2 1
2 .5
Fabrication process cross sections of one micron gate InGaAs
MISFET.
24
Schematic cross section of submicron gate InGaAs MISFET.
27
2 .7
Fabrication process cross sections of submicron gate InGaAs
MISFET.
29
3.1
Block diagram of RF measurement system used to charac­
terize one micron gate InGaAs MISFET.
33
3 .2
Block diagram of RF measurement system used to charac­
terize submicron gate InGaAs MISFETs.
37
3 .3
Photograph of H P 8 3 0 4 0 modular microcircuit package.
41
3 .4
Tw elve error term model.
43
3 .5
Eight error term model.
53
4.1
I-V characteristics of 1 //m gate InGaAs MISFET with silicon
dioxide gate insulator.
Horizontal: 0 .5 V/div. Vertical: 20 mA/div.
Gate (VGS): -2 V/step.
64
4 .2
Photograph of fabricated 1 prr\ gate InGaAs MISFET with
1
mm total gate width.
4 .3
l-V characteristics of 1 fjm gate InGaAs MISFET with silicon/
silicon dioxide gate insulator.
Horizontal: 0 .5 V/div. Vertical: 20 mA/div.
Gate (VGS): -2 V/step.
2 . 1
2 . 6
vii
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6 8
69
4 .4
Drain current drift measurement of 1 //m gate InGaAs MISFET
w ith silicon/silicon dioxide gate insulator.
71
4 .5
Output power, power-added efficiency vs. input power at
9 .7 GHz (VDS = 5.0 V, V QS = 0 V).
73
4 .6
Power gain vs. input power at 9 .7 GHz
(VDS = 5 .0 V, VGS = 0 V).
74
4 .7
Time dependence of output power and drain bias current at
9 .7 GHz.
76
5.1
I-V characteristics of submicron gate InGaAs MISFET
Horizontal: 0 .5 V/div. Vertical: 20 mA/div.
Gate (VGS): -2 V/step.
81
5 .2
Transconductance vs. gate voltage (VDS = 2 .5 V).
82
5 .3
Drain current drift measurement of InGaAs MISFET with
silicon dioxide gate insulator.
85
5 .4
Output power, power-added efficiency vs. input power at
18 GHz (VDS = 6.0 V, VGS = -3 .5 V).
87
5 .5
Output power, power-added efficiency vs. input power at
2 0 GHz (VDS = 5.5 V, V GS = -2 .5 V).
89
5 .6
Output power, power-added efficiency vs. input power at
2 3 GHz (VDS = 5.8 V, V GS = -3 .5 V).
90
5 .7
Time dependence of output power and drain bias current at
18 GHz.
96
5 .8
THRU standard - measured Sn data from 1 0 - 2 0 GHz.
93
5 .9
THRU standard - measured S 1 2 data from 1 0 - 2 0 GHz.
1 0 0
5 .1 0
THRU standard - measured S2 1 data from 1 0 - 2 0 GHz.
1 0 1
5.11
THRU standard - measured S2 2 data from 1 0 - 2 0 GHz.
1 0 2
5 .1 2
THRU standard - extracted Sni data from 1 0 - 2 0 GHz.
103
5 .1 3
THRU standard - extracted S 1 2 data from 1 0 - 2 0 GHz.
104
5 .1 4
THRU standard - extracted S 2 1 data from 1 0 - 2 0 GHz.
105
viii
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5 .1 5
THRU standard - extracted S 2
2
data from 10 - 2 0 GHz.
106
5 .1 6
S n data for submicron gate InGaAs MISFET ( 1 0 - 2 0 GHz).
108
5 .1 7
S 1 2 data for submicron gate InGaAs MISFET (10 - 2 0 GHz).
109
5 .1 8
S 2 1 data for submicron gate InGaAs MISFET ( 1 0 - 2 0 GHz).
110
5 .1 9
S 2 2 data for submicron gate InGaAs MISFET ( 1 0 - 2 0 GHz).
111
5 .2 0
Gain (MSG) vs. frequency for submicron gate InGaAs
MISFET (Lsd = 3 /;m ).
114
5.21
Gain (GTUmax) vs. frequency for submicron gate InGaAs
M ISFET (Lsd = 3 A /m ).
116
ix
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LIST OF TABLES
TABLE
Material properties of ln0
2.1
Implant profile equations.
15
2.2
Source/drain and channel implant profile statistics.
15
3.1
Equipment contained in RF measurement system used to
characterize one micron gate InGaAs MISFETs.
34
3 .2
Preparation of chromium and gold etching solutions.
36
3 .3
Equipment contained in RF measurement system used to
characterize submicron gate InGaAs MISFETs.
38
3 .4
Error coefficients in full two-port error model.
44
3.5
Full tw o-port error model equations.
45
3 .6
Reserved GPIB Instrument Addresses.
48
3 .7
Reserved files within TRLCAL program.
50
3 .8
Reserved file names (filename.extension) used by TRLCAL
program.
50
3 .9
Error term translations between
54
4.1
One micron gate InGaAs MISFET results (silicon dioxide gate
insulator).
4 .2
One micron gate InGaAs MISFET results (silicon/silicon dioxide
gate insulator).
77
5.1
Submicron Gate InGaAs MISFET l-V results after RF packaging.
84
5 .2
Highest output power densities for submicron gate InGaAs
MISFETs.
92
5 .3
Highest power-added efficiencies for submicron gate InGaAs
MISFETs.
93
5 3
Ga0 >4 7 As.
PAGE
2
1.1
8
and 12 term models.
x
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6 6
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CHAPTER 1
INTRODUCTION
1.1
InGaAs Epitaxial Growth
The lll-V ternary alloy indium gallium arsenide (lnxG a i.xAs) is a promising
semiconductor
material
for
high
frequency
device
and
optoelectronic
applications. In particular, lattice matched ln0 .5 3 Ga0 47As on indium phosphide
(InP) has demonstrated a higher low field mobility (1 2 0 0 0 cm 2/V sec), peak
electron velocity (3 x 10 7 cm/sec), and intervalley separation (0 .5 5 eV) than
gallium arsenide (GaAs) and indium phosphide (InP), and, thus, is ideal for high
speed field-effect transistors. In addition, the bandgap energy (0.7 5 eV) makes
InGaAs an ideal material for fabricating detectors for fiber optic systems
operating in the optimum wavelength range of 1 .3 - 1.5 pm.
Material
properties of lno.5 3 Gao.4 7 As are listed in Table 1.1 [1]-[6].
Epitaxial layers of I n ^ a ^ A s were first grown on gallium arsenide
(GaAs) using an open tube system with elemental As and In-Ga sources [7].
Subsequently, growth by chloride vapor transport of gallium and indium from
elemental sources produced alloys over the entire composition range.
A
mobility of 3 0 0 0 cm2/V sec was obtained for lnxGa-,_xAs (x = 0.4) [8 ].
Since then, high quality InGaAs has been grown by a variety of
techniques which include liquid phase epitaxy (LPE), hydride vapor phase
epitaxy (HVPE), AsCI3 VPE (CIVPE), molecular beam epitaxy (MBE), and
organometallic VPE (OMVPE) [3].
OMVPE is presently the most promising
technique for applications which require the large area growth of high quality
material with multiple abrupt changes in composition and doping. The basic
reaction
used
in the deposition
of
lll-V
semiconductors
involves the
1
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Table 1.1
Material properties of lno.53Gao.47As
Bandgap (E )
(@ 3 0 0 K)
0 .7 5 eV
Intrinsic Carrier Concentration (nj)
(@ 3 0 0 K)
7 x 10 1
Electron Effective Mass (me)
0.041 m 0
Electron Affinity Of)
4 .3 5 eV
Intrinsic Fermi Level (Ej)
(@ 3 0 0 K, measured from valence band)
0 .4 2 eV
Static Dielectric Constant (es)
13
Low Field Mobility (//)
(@ 3 0 0 K)
1 2 0 0 0 cm2/V sec
M aximum Drift Velocity (vD MAX)
(@ 3 0 0 K)
3 x 10 7 cm/sec
Electric Field at Max Drift Velocity
(@ 3 0 0 K)
5.5
T-L Intervalley Separation (Ar_L)
0 .5 5 eV
Lattice Constant (a)
(@ 3 0 0 K)
5 .8 6 9 4 A
Density
5 .4 6 9 g/cm 3
Thermal Conductivity
0 .6 6 W /cm K
1
cm ' 3
kV/cm
2
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simultaneous thermal decomposition of a group III organometallic compound
and a group V hydride. The presence of more than one group III organometallic
allows lll-V alloys such as InxGa-,_xAs to be formed.
composition range
( 0
< x <
1
Alloys over the whole
) can in principle be formed by varying the
relative concentrations of the group III elements in the gas phase [9].
Tw o important considerations in the OMVPE growth of InGaAs lattice
matched to InP are the following. First, a large group V species overpressure
(e. g. phosphine PH3) is required at elevated temperatures in order to prevent
decomposition of the InP surface.
A t temperatures greater than 5 5 0 C, InP
decomposes rapidly in an H 2 atmosphere in the presence of PH3. Thus, care
must be taken when switching from a PH3 overpressure to protect the InP
surface to an arsine (AsH3) overpressure required for InGaAs layer growth in
order to obtain layers with high crystal quality. Second, the In/Ga ratio in the
growing layer must be accurately controlled in order to obtain InGaAs lattice
matched to InP [10].
VPE growth of InGaAs alloys using organometallic sources of gallium and
indium was first performed by M anasevit and Simpson in 1973 [11]. Triethylindium (TEl), trimethylgallium (TM G), and arsine (AsH3) were used to prepare
InGaAs alloys on Al 2 0 3 and GaAs substrates. The growth rates were less than
0 .1 5 pm /min and the alloy composition was confined to midway between GaAs
and InAs. The average mobility obtained for a 11.7 fjm thick alloy on Cr doped
(111) GaAs was 4 5 0 0 cm2/V sec.
lnxGa1.xAs alloys spanning the entire composition range (0 < x < 1)
were subsequently grown on (100) GaAs to a thickness of
1
- 2 ^ m [12]. The
mobilities were generally a third of the bulk values. The low growth efficiencies
and poor material quality in these studies were attributed to parasitic gas phase
3
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reactions upstream from the substrates between the TE1 and AsH 3 [9].
A major improvement was made by switching from atmospheric pressure
to a low pressure regime in order to reduce parasitic gas phase reactions. Low
pressure OMVPE (LP-OMVPE) in a horizontal reactor was used to produce the
first high quality lattice matched InGaAs on InP substrates at a reduced
pressure of 7 6 Torr [13]. Triethylindium (TEI) and triethylgallium (TEG) were
used as the Ga and In sources with palladium diffused hydrogen and pure
nitrogen as carrier gases. The group V source was AsH3. The InP substrates
used w ere misoriented
2
° from the ( 1
0 0
) plane.
The optimum growth conditions were a growth temperature of 5 5 0 C
and a total gas flow of 7 l/min. The N2/TEl bubbler flow rate was 4 5 0 cm3/min
and the H2/TEG bubbler flow rate was 180 cm 3 /min. The AsH 3 flow rate was
90 cm 3 /min. The InGaAs growth rate was 3 0 0 A/m in. A relative variation in
lattice parameter between ±
2
x
1 0 ' 3
was obtained over the temperature range
of 5 20 - 6 5 0 C. The total impurity concentration was as low as 3 x 1 0 1 4 cm'3.
The mobilities of a 0 .6 6 fjm thick layer at 3 0 0 K and 7 7 K were 1 2 0 0 0 and
6 0 0 0 0 cm 2/V sec, respectively.
The growth rate was linearly dependent on the TEI and TEG flow rates
and independent of the AsH 3 flow rate and substrate temperature over the
range of 5 0 0 - 6 5 0 C.
Thus, the epitaxial growth was determined to be
controlled by the mass transport of the group III species [14].
The source purity was determined to have a great effect on the quality
of the InGaAs layers as indicated by mobility and photoluminescence (PL)
measurements.
The 2 K PL spectra of layers grown using high purity and
ordinary starting materials were obtained.
The ordinary starting materials
produced a w eak near bandgap exciton line and donor/acceptor pair bands due
4
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to carbon (C), zinc (Zn), and silicon (Si) acceptors.
Growth at atmospheric pressure was subsequently reinvestigated using
T M I. The improved material results were due to the availability of higher purity
TM I and the associated reduction of parasitic gas phase reaction problems
compared to previous work [3]. High quality layers were grown on (100) InP
substrates in a horizontal, IR heated system. The TM G and solid TM I sources
were maintained at -1 1 .5 C and 10 C, respectively, using temperature
controlled baths. The TMI and TMG H2 carrier gas flow rates w ere 120 seem
and 0 .9 seem, respectively. The group V source (10% AsH 3 /H 2) flow rate was
6 0 seem.
A growth rate of 0 .0 5 //m/min was obtained using the above conditions.
The growth efficiency was about 10 4 //m/mole. The carrier concentrations of
1 - 2 fjm thick layers were approximately 1 0 1 5 cm"3. The mobilities at 3 0 0 K
and 7 7 K were 7 5 0 0 - 1 0 0 0 0 and 3 0 0 0 0 - 4 0 0 0 0 cm 2/V sec, respectively.
The key growth parameter responsible for the high quality was a relatively high
substrate temperature of 6 50 C. At a substrate temperature of 5 4 0 C, carbon
was determined to be a major source of contamination as indicated from. 4 K
PL measurements and an associated degradation in mobility { < 3 0 0 cm2/V sec
at 77 K).
At 6 5 0 C, good surface morphology was obtained for V/lll ratios
greater than 31 [15].
Similar results have also been obtained by others that
indicate the necessity of using high substrate temperature (6 4 0 C) to obtain
high quality and high mobility layers [ 1 0 ].
In summary, growth of lattice matched InGaAs on InP by OMVPE has
been investigated since 1973. However, the greatest improvements in materia!
quality have occurred only over the last 7 years. High quality InGaAs has been
grown by low pressure and atmospheric pressure OMVPE.
Layers with the
5
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highest mobility and lowest net impurity concentration have been grown by LPOMVPE. The highest crystal quality as determined from x-ray diffraction and
photoluminescence measurements, however, has been obtained using chemical
beam epitaxy (CBE) which combines the advantages of OMVPE and molecular
beam epitaxy (MBE) [1 6 H 1 9 ]. Present areas of research include obtaining high
quality layers using alternative arsine sources such as tertiarybutylarsine (TBA)
[20], [21].
1 .2 InGaAs MISFET Technology
As mentioned above, ln0
5 3
Ga0-47As lattice matched to semi-insulating
(SI) InP has higher low field mobility (1 2 0 0 0 cm2/V sec), peak electron velocity
(3 x 1 0 7 cm /sec), and intervalley separation (0 .5 5 eV) than InP, and is thus
ideal for high frequency field-effect transistors. Because of the low Schottky
barrier height of InGaAs, development of a metal-semiconductor field-effect
transistor (MESFET) technology is not feasible. Consequently, much emphasis
has been placed on the development of a metal-insulator-semiconductor fieldeffect transistor (MISFET) technology.
A MISFET device structure provides
high input voltage swing, which is advantageous for power devices. Bipolar
gate voltage swings are also possible which provide improved linearity [2
2
].
In addition, high gate breakdown voltages and low gate leakage currents are
associated with the deposited gate insulator. Because of the above mentioned
materials properties, InGaAs MISFETs have potential for superior microwave
performance compared to InP MISFETs. However, because InGaAs has lower
ionization coefficients and a lower breakdown field than InP, high frequency
device operation may be attained at the expense o f reduced power output.
N-channel inversion mode MISFETs first demonstrated the feasibility of
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a MISFET technology on InGaAs [23], [24].
These early devices were
fabricated on p-lnGaAs layers grown latticed matched to InP using liquid phase
epitaxy (LPE). The devices which employed plasma deposited silicon dioxide
and silicon nitride gate insulators exhibited transconductances (gM) of
1
-
2 mS/mm of gate width. The low values of transconductance w ere attributed
to poor source/drain junctions and Schottky contacts.
Depletion mode InGaAs MISFETs were subsequently demonstrated [25],
The devices were fabricated on n + /n InGaAs layers grown lattice matched to
semi-insulating InP using hydride vapor phase epitaxy (VPE). Low temperature
chemical vapor deposition (CVD) was used to deposit a silicon dioxide gate
insulator at 3 5 0 C.
Capacitance-voltage (C-V) measurements indicated an
interface trap density of about 1 0 1 2 cm'2 e V 1. The MISFETs had a gate length
of 3 //m and 4 gate stripes of 1 5 0 //m width in parallel for an overall gate width
of 6 0 0 fjxxx. Effective field effect mobilities as high as 5 2 0 0 cm2/V sec were
measured.
Inversion mode InGaAs MISFETs with native oxide gate insulators have
also been reported [26], [27]. The devices were fabricated on epitaxial layers
grown by molecular beam epitaxy (MBE). A transconductance of 4 0 mS/mm
was obtained for devices w ith 3 fjm gate lengths.
Accumulation mode InGaAs MISFETs have also been demonstrated [28].
The residual donors of the LPE grown InGaAs were compensated using deep
level Fe'acceptors. The electron density of the compensated InGaAs layer was
2 .5 x 1 0 1 2 cm " 3 and the Hall mobility was 6 2 0 0 cm2/V sec. The device had
a
8
//m channel length and employed a 120 0 A S i0 2 gate insulator deposited
using a low temperature RF plasma assisted CVD process.
The effective
threshold
mobility
voltage
of the
device
was
-0 .3
V
and
the
7
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
was
7 9 3 cm 2/V sec. The low mobility of the device compared to the Hall mobility
value
was
attributed
to
interfacial
scattering
caused
by
a
poor
insulator/semiconductor interface.
The first reported submicrometer gate length InGaAs MISFET employed
a self-aligned recessed gate structure [29].
The fabrication of the depletion
mode device required complex techniques such as angle evaporation and
sputter etching/wet chemical etching to achieve the submicron channel recess
structure.
The n + /n InGaAs layer was grown on semi-insulating InP using
molecular beam epitaxy (MBE).
A 0.5 //m x 100 fjm gate device had a
transconductance of 2 5 0 mS/mm gate width. The improved gM compared to
prior devices was attributed partly to the reduced source series resistance
achieved using the self-aligned recess gate structure. The cutoff frequency of
the device was estimated to be 20 GHz.
Although encouraging results were obtained with the above mentioned
devices, early InGaAs MISFETs exhibited drain current drift similar to InP
MISFETs.
For example, InGaAs MISFETs employing unannealed CVD S i0 2
deposited at 3 5 0 -4 0 0 C as a gate insulator displayed a drain current drift of
about 5 0 % over 10 sec [30]. However, rapid thermal annealing (RTA) of the
gate oxide at 7 0 0 C drastically improved the short term stability of the drain
current drift over 10 sec.
The long term stability of the annealed device,
though, w as comparable to the unannealed device. Improvement in the long
term stability was achieved by reducing the deposition temperature of the
silicon dioxide to 2 5 0 C. The low temperature deposition in conjunction with
the 7 0 0 C RTA produced a drain current drift of < 5% over 10 4 sec. Similar
results were obtained for annealed low temperature (170 C) PECVD S i0 2 used
in self-aligned gate ion implanted MISFETs [1]. The n-channel inversion mode
8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
devices displayed less than
2
% drain current drift over
1 0 3
sec.
The use of low temperature deposited S i0 2 gate insulators has enhanced
InGaAs MISFET performance recently.
Inversion mode, self-aligned gate,
InGaAs MISFET ring oscillators have been demonstrated [31].
oscillators employed enhancement driver ( 1
. 2
The ring
;/m gate length) and load devices.
The nine stage ring oscillator demonstrated a propagation delay of 50 ps.
More recently, depletion mode InGaAs MISFETs with 1 pm gate lengths
have demonstrated a transconductance of 3 0 0 mS/mm [3 2].
The carrier
velocity was estimated to be 4 x 10 7 cm/sec. InGaAs MISFETs have also been
fabricated on n + /n layers grown by metal organic chemical vapor deposition
(M O CVD) [33], [34].
Enhancement mode devices with 1 .5 pm gate lengths
exhibited a transconductance of 300 mS/mm. The effective channel mobility
and
carrier
velocity
were
determined
to
be
5800
cm2/V sec
and
3 .5 x 10 7 cm/sec, respectively [34]. Depletion mode InGaAs MISFETs with an
ultrathin MBE silicon interfacial layer between the InGaAs and photo-CVD
silicon dioxide gate insulator have recently demonstrated an effective channel
mobility of 1 7 0 0 cm2/V sec [35],
Low temperature deposited S i0 2 gate insulators have also been used in
InGaAs power MISFETs.
Depletion mode InGaAs MISFETs with 3 pm gate
lengths first demonstrated microwave power performance a t
6
GHz [25]. Ion-
implanted InGaAs MISFETs with 1 pm gate lengths have since demonstrated
output power densities of 0 .4 9 W /m m of gate width with corresponding poweradded efficiencies of 4 8 % and 39% at 4 GHz and
8
GHz, respectively [22].
InGaAs power MISFETs with 1 pm gate lengths have also been fabricated using
a non-ion-implanted process [32]. Microwave performance was demonstrated
in the frequency range from 4 GHz to 3 2 .5 GHz.
Output power densities
9
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
obtained from
devices w ith
0 .5 6
mm
gate widths were
1 .5 3 W /m m ,
0 .7 6 W /m m , 0 .7 4 W /m m , and 0 .2 0 W /m m at 4 GHz, 12 GHz, 2 0 GHz, and
3 2 GHz, respectively. The corresponding power-added efficiencies w ere 5 3 % ,
4 0 % , 2 6 % , and 7% .
Recently, the wide-band microwave power performance of InGaAs
MISFET amplifiers has been reported [3 6 ].
Output power densities of
0.41 W /m m and 0 .4 7 W /m m with corresponding power-added efficiencies of
3 3 ± 3 % and 3 0 ± 3 % , respectively, w ere obtained over the 7 - 1 1
band.
GHz
In addition, an output power density of 0 .3 9 W /m m w ith 2 9 ± 4 %
power-added efficiency was obtained over the 6 - 1 2 GHz band.
In
comparison to
InGaAs
MISFETS,
InP MISFETs
have
recently
demonstrated impressive output power densities. Ion implanted InP MISFETs
with 1 //m gate lengths have produced output power densities o f 2 .9 W /m m
and 2 .4 W /m m at X-band [37], [38]. Similar geometry epitaxial InP MISFETs
have produced output power densities of 4 .5 W /m m [39].
In addition, an
epitaxial InP MISFET with a 0 . 3 //m gate length has achieved an output power
density of 1.8 W /m m at Ka band [40].
1 .3 Research Objectives
The overall objective of the research was to investigate InGaAs on InP
compound semiconductor technology for high frequency power applications.
A survey of the literature indicated that a submicron gate length power metalinsulator-semiconductorfield-effect transistor (MISFET) on InGaAs had not been
reported.
Thus, the main objective of the research was the fabrication and
characterization o f InGaAs/lnP microwave power MISFETs with submicron gate
lengths.
10
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
However, the formation of submicron gates by optical lithography is
quite technologically challenging. Thus, it was decided to first investigate the
fabrication and characterization of one micron gate length devices in order to
gain experience with InGaAs/lnP processing technology.
The ion-implanted
devices w ere characterized by performing both DC and RF measurements. The
DC device characterization included the measurement of the output currentvoltage (l-V) characteristics, transconductance, drain breakdown voltage, gate
leakage current, and drain current drift.
The microwave characterization
included the measurement of output power, power gain, and power-added
efficiency as a function of input power and bias conditions. In addition, output
power stability
measurements
were
also
performed.
The
microwave
characterization was performed at a frequency of 9 .7 GHz.
After gaining experience with the one micron gate ion-implanted devices,
epitaxial InGaAs MISFETs with submicron gate lengths were fabricated and
characterized.
The depletion mode MISFETs had source/drain spacings of
5 pm, 3 pm, and 2 pm in order to investigate the effect on device performance
and breakdown characteristics. The DC and RF characterization was similar to
that described above for the one micron gate, ion-implanted InGaAs MISFETs.
However, the devices were RF power tested over the frequency range of 18 23 GHz.
In addition, the devices were further characterized by performing
scatter parameter measurements over the frequency range of 10 - 2 0 GHz. A
thru, reflect, line (TRL) calibration procedure was implemented in order to
perform the scatter parameter measurements.
11
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
12
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 2
EXPERIMENTAL PROCEDURES
This chapter describes the experimental procedures used in the research.
The fabrication processes covered are ion implantation, which was used in the
fabrication of the one micron gate length InGaAs MISFETs, and plasma
deposition, which was used in the fabrication of both one micron and
submicron gate InGaAs MISFETs. Finally, the one micron gate, ion implanted
InGaAs MISFET and the submicron gate, epitaxial InGaAs MISFET fabrication
processes are described in detail.
2.1
Ion Implantation
Ideally, it is best to fabricate InGaAs transistors on doped epitaxial active
layers since the doping can be incorporated during the epitaxial growth step.
However, InGaAs doped epitaxial layers on InP substrates were not available
at the start of the research. The only material on hand was unintentionally
doped InGaAs/lnP on InP substrates. The thickness of the InGaAs layer was
0 .5 fjm, and the thickness of the InP buffer layer was 0.1 fjm. Thus, in order
to investigate InGaAs/lnP processing technology, an ion-implanted process was
first developed.
Depletion mode InGaAs power MISFETs with one micron gate lengths
w ere investigated. Thus, highly doped source/drain and channel regions were
needed. The implants were performed by Leonard Kroko, Inc. located in Tustin,
CA. The implant species was singly ionized mass 28 silicon (Si28 + ). Silicon
is typically an n-type (donor) dopant in InGaAs [41], [42].
The source/drain and channel implants were intended to be similar to
13
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
those used for InP power MISFETs [37], [43], [38].
For the source/drain
implants, it w as desired to obtain a uniform silicon concentration of 2 x 1 0 19
cm '3 to a depth of 0 .2 //m .
Consequently, multiple implants were required.
The source/drain implant energies and doses ranged from 4 0 - 2 4 0 keV and
1 .6 x 1 0 12 -
1 x 1 0 13 cm '2, respectively.
For the
channel implant,
a
concentration of at least 1 0 17 cm'3 to a depth of 0 .3 5 j/m was desired.
Multiple implants were again used.
The channel implant energies and doses
ranged from 4 0 - 2 4 0 keV, and 1 . 6 x 1 0 12 - 1 x 1 0 13 cm '2, respectively.
The implant energies and doses were determined empirically using LSS
(Linhard, Scharff, and Schiot) statistics [44].
The source/drain and channel
implant profiles determined from LSS statistics are shown in Figures 2.1 and
2 .2 . Four implants w ere used for both the source/drain and channel implants.
The profiles were obtained using LSS range statistics for silicon in gallium
arsenide that w ere adapted for InGaAs. The Gaussian profiles w ere calculated
using the equations listed in Table 2 .1 . Third moment ratio values w ere not
used in calculating the profiles [44], [45].
The projected range (Rp) and
projected standard deviation (a) values for Si in GaAs were adapted for InGaAs
by multiplying the values by the ratio of the densities of GaAs to InGaAs. The
density value used for GaAs was 5 .3 2 g/cm3 [46]. The density value used for
InGaAs (5 .4 6 9 g/cm 3) was interpolated from the densities of GaAs and InAs
[6]. The energy, dose, projected range, and projected standard deviation values
used for the source/drain and channel implants are listed in Tables 2 .2 .
14
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 2.1
Implant profile equations
N(x)
=
-lx 2
N m ax e 2
Dose
A/
_
n m a x
--------------o
Table 2 .2 Source/drain and channel implant profile statistics
Source/Drain
Channel
Dose (cm'2)
Dose (cm'2)
Rp (//m)
a (//m )
40
4 .5 x 1 0 13
1 .6 x 1 0 12
0 .0 3 3 4
0.0207
80
9 .0 x 1 0 13
3 .2 x 10 12
0 .0 6 5 9
0.0360
160
1.5 x 1 0 14
6 .3 x 10 12
0 .1 3 4 2
0.0620
240
3 .0 x 1 0 14
1.0 x 10 13
0 .2 0 4 0
0.0836
Energy (keV)
15
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
.19
10
CO
I
E
o
.18
10
X
.17
.16
10
0
0.1
0.2
0.3
0.4
0.5
DEPTH (um)
Figure 2.1
Source/drain implant profile for one micron gate InGaAs MISFET
16
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
N(x) (cm-3)
.15
0
0.1
0.2
0.3
0.4
0.5
DEPTH (um)
Figure 2 .2 Channel implant profile for one micron gate InGaAs MISFET
17
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2 .2
Plasma Deposition
The gate insulators used in the InGaAs MISFET fabrication were plasma
deposited silicon dioxide and silicon dioxide with a thin silicon interfacial layer.
The films were deposited on the InGaAs/lnP substrates using a Technics Planar
Etch IIA parallel plate reactor modified for 1 3 .5 6 MHz operation as shown in
Figure 2 .3 . The substrates were placed on a grounded lower electrode which
could be heated. The electrode separation was about 3 cm. Reactant gases
flowed radially inward from a gas distribution ring below the lower electrode to
an exhaust port in the center of the lower electrode. The gas flow rates were
controlled by digital mass flow controllers and the deposition pressure was
independently controlled by a throttle valve in the exhaust line. The substrate
temperature was measured and controlled by a thermocouple in contact with
the lower electrode.
The deposition procedure consisted of the following. The chamber was
initially etched for about 30 min using a 1 5 0 W carbon tetrafluoride (CF4)
plasma to remove deposits from previous depositions. The chamber was then
baked by heating the lower electrode for at least 10 min a t 2 5 0 C.
The
samples were then loaded and the chamber was baked for 4 0 min at 2 5 0 C
The purpose of the bakeouts was to prevent oxygen contamination of the
deposited films [47]. The reactant gases w ere then introduced. The flow rates
and pressure were allowed to stabilize for 5 min prior to the deposition.
The silicon dioxide films were deposited using silane (SiH4), and nitrous
oxide (N20 ) as reactant gases.
The films were deposited at a pressure of
3 5 0 mTorr using 50 W of RF power and a substrate temperature of 2 5 0 C.
The gas flow rates were 19 seem SiH4, and 55 seem N20 .
The films were
typically deposited to a thickness of about 5 0 0 - 9 0 0 A using a power density
18
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X
RF 13.56 MHz
TEFLON RING
CHAMBER
MATCHING
NETWORK
yfr
TOP ELECTRODE
GAS FLOW
WAFER
LOWER ELECTRODE
HEATER /
T U C O M A P n i 1QI c
i i lu n iv iw w w r u .
TO VACUUM PUMP
FEEDTHROUGH
Figure 2 .3
Schematic of plasma system chamber
19
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
of approximately 100 m W /cm 2.
The refractive index and thickness of the
silicon dioxide films were determined from ellipsometric measurements at
6 3 2 8 A (HeNe). The refractive index was typically 1 .4 6 as expected [46].
The silicon interfacial layer was deposited using silane (SiH4) as a
reactant gas.
The interfacial layer was deposited at 3 5 0 mTorr and 2 5 0 C
using a 10 W plasma. The SiH4 flow rate was 17.5 seem. The interfaciai layer
was typically deposited to a thickness of about 3 0 A [48] using a power
density of approximately 20 m W /cm 2.
2 .3 One Micron Gate InGaAs MISFET Fabrication
A schematic cross section of the 1//m gate length InGaAs MISFET with
a silicon/silicon dioxide gate insulator is shown in Figure 2.4 . The devices were
fabricated on InGaAs layers grown lattice matched on semi-insulating (SI) InP
substrates with resistivity greater than 107 Q-cm.
The thicknesses of the
InGaAs layer and InP buffer layer were 0 .5 fim and 0.1 fim, respectively. The
ohmic contacts were Au:Ge/Au of 0.35 fjm thickness and the thickness of the
Au overlayer was 0 .4 fim.
The gate meta! was Ti/Au of 0 .4 3 fjm thickness.
The source/drain implant spacing was 5 fjm and the length of the gate recess
was 2 fjm. The completed InGaAs MISFETs had 6 to 10 parallel gate fingers
with individual gate widths of 100 or 125 fjm. The individual gate finger width
was limited to the above values in order to avoid possible gain degradation
associated with larger gate widths [38]. The total gate widths were 0 .7 5 mm,
0 .8 mm, or 1 mm.
The average separation between the gate fingers was
1 1 4 fjm. The large spacing between the gate fingers was necessary in order
to facilitate wire bonding to the individual drain regions.
The InGaAs and InP layers were grown unintentionally doped (n = 1 -
20
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Hi
1-
<
CC
F*
CO
m
CC
UJ
3
CO
CL
_c
cc
UJ
U_
LL
CO
3
lO
CL
c
Figure 2 .4
Schematic cross section of one micron gate InGaAs MISFET
21
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2 x TO15 cm*3) on Sl-lnP substrates using metalorganic chemical vapor
deposition (M O CVD) [49].
The Sl-lnP substrates were liquid capsulated
Czochralski (LEG) grown wafers tw o inches in diameter with (100) orientation.
The substrates were cleaned using organic solvents and then etched using a
H2S 0 4 :H20 2:H20 solution. The layers w ere deposited using a vertical, low
pressure {60 Torr), rotating (1 5 0 0 rpm) disk reactor w ith a 3 - 2 inch diameter
w afer capacity (EMCORE G S /3200).
The growth chamber was of stainless
steel construction and contained a resistively heated, molybdenum susceptor.
The wafers rested directly on a wafer carrier which w as transferred between
an ultra high vacuum, stainless steel loadlock and the heated susceptor in the
growth chamber.
The temperature was monitored by a thermocouple or
infrared pyrometry.
The In and Ga metalorganic sources w ere trimethylindium (TMIn) and
triethylgallium
(TEGa).
The
As
and
P
hydride
sources
were
arsine
(10% A s H3/H 2) and phosphine (PH3). Hydrogen was used as a carrier gas. A
high temperature bakeout was performed with temperatures of 6 5 0 -6 9 0 C for
15 min. prior to growth. The growth rate for the InGaAs and InP layers was
1.9 //m /hr. The growth temperature was 6 2 0 C. Typical values for InGaAs
and InP thickness uniformity across a 2 inch w afer were < ± 2% . The lattice
mismatch variation was < ± 10*4 across the 2 inch w afer.
The InGaAs
mobility at 3 0 0 K. was 1 2 0 0 0 cm2/V sec.
For the InGaAs MISFET fabrication, the samples were initially cleaned by
first degreasing in acetone and methanol followed by a Dl water rinse. The
samples were then dipped for 15 sec in a 10:1 H20:H F solution followed by a
Dl w ater rinse and then blown dry in nitrogen.
The cross section of the fabrication sequence of the 1 //m gate InGaAs
22
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
MISFETs is illustrated in Figure 2 .5 .
After the initial clean, the first
photolithographic step was performed. Alignment marks were made by etching
the InGaAs in a 1:1:38 H2S 0 4 :H20 2:H20 solution. Source/drain implants were
then performed using photoresist as an implant mask as shown in Figure 2.5A .
Si28+ was implanted at energies of 4 0 , 8 0 , 160, and 2 4 0 keV with doses of
4 .5 x 1 0 13, 9 x 1 0 13, 1.5 x 1 0 14, and 3 x 1 0 14 cm'2, respectively. Multiple
implants were performed in order to achieve a uniform silicon concentration of
2 x 1 0 19 cm '3 to a depth of 0 .2 //m as determined from LSS statistics. After
stripping the photoresist, a second photolithographic step was performed and
the channel was implanted at energies of 4 0 , 80, 160, and 240 keV with doses
of 1 .6 x 1 0 12, 3 .2 x 1 0 12, 6 .3 x 1 0 12, and 1 x 1 0 13 cm'2, respectively.
Multiple implants were again performed in order to obtain a concentration of at
least 1 0 17 cm'3 to a depth of 0 .3 5 £/m.
A fter stripping the photoresist, the w afer was again cleaned and then
encapsulated with silicon dioxide plasma deposited to a thickness of about
1 40 0 A as shown in Figure 2.5B [50]. The implants were then rapid thermal
a m m a m I a ( 4
”7 O O
a iin c a ic Q a t / \ j \ j
was 2 l/min.
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After stripping the oxide, source/drain ohmic contacts were
defined by evaporating Au/Ge 12 w t.% eutectic and Au to 'a thickness of
2 0 0 0 A and 1500 A, respectively, and using a liftoff process as shown in
Figure 2 .5C . Ohmic contacts were obtained by alloying for 5 min at 4 0 0 C in
forming gas (10% H2/N 2).
A mesa etch was then performed for device
isolation using a 1:1:38 H2S 0 4:H20 2:H20 solution. The gate region was then
chemically
recessed,
as
shown
in
Figure
2.5D ,
using
a
1:1:100
H2S 0 4:H20 2:H20 solution.
A fter stripping the photoresist, the w afer was again cleaned and a silicon
23
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Si.• +
Si
I
I
RESIST
InGaAs
A)
IMPLANT
InP
sZ
B)
SiO,
SOURCE/DRAIN
C)
\\
r
n
m
r
n
CONTACTS
GATE RECESS
JZZZ
MESA
D)
SI/SiO ,
E)
GATE METAL
Au OVERLAYER
F)
Figure 2.5
z
7777771
Fabrication process cross sections of one micron gate InGaAs
MISFET
24
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
dioxide gate insulator with a silicon interfacial layer was plasma deposited to
a thickness of about 9 0 0 A as shown in Figure 2.5E [48].
The films were
deposited using a Technics PlanarEtch IIA plasma system modified for
1 3 .5 6 M Hz operation. The silicon interfacial layer was deposited at a pressure
of 105 mTorr using 10 W of RF power, a SiH4 flow rate of 17.5 seem, and a
substrate temperature of 2 5 0 C. The silicon dioxide films were deposited at
3 5 0 mTorr and 2 5 0 C using a 50 W plasma. The SiH4 and N20 flow rates
were
19 seem and 55
seem,
respectively.
The
gate insulators were
subsequently annealed at 3 0 0 C for 3 0 min in hydrogen.
The gate metal was then defined by evaporating Ti and Au to a thickness
of 3 0 0 A and 4 0 0 0 A, respectively, and using a liftoff process.
Finally,
source/drain oxide windows were opened and a Au overlayer was deposited to
a thickness of 4 0 0 0 A using a liftoff process as shown in Figure 2.5F. The Au
overlayer assisted the current handling of the devices and facilitated wire
bonding to the drain regions.
The InGaAs MISFETs with silicon/silicon dioxide gate insulators were
n ro n arp H
IV*
■for RP
n p rU p n
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jyUV/iNU
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VI IV* WUVlWlVV
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th o
H C I:H N 03:H20 solution to improve thermal resistance and then scribing the
sample into individual MISFETs. Backside metalization was then performed to
aid heat dissipation of the MISFETs by evaporating Ti and Au to a thickness of
3 0 0 A and 4 0 0 0 A, respectively. The completed MISFETs were then packaged
and w ire bonded for microwave characterization at 9 .7 GHz.
2 .4 Submicron Gate InGaAs MISFET Fabrication
The submicron gate length InGaAs MISFETs were also fabricated on
layers grown lattice matched on semi-insulating (SI) InP substrates using metal
25
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
organic chemical vapor deposition (MOCVD). A schematic cross section of the
submicron gate length InGaAs MISFET with a silicon dioxide gate insulator is
shown in Figure 2 .6 . An InP buffer layer was grown unintentionally doped to
a thickness of 0 .2 //m .
The thickness of the InGaAs active layer (n = 2 -
3 x 1 0 17 cm'3) was 0 .3 //m . The submicron gate length devices were similar
in design to the 1 //m gate length devices described above. The completed
submicron gate InGaAs MISFETs had 2 parallel gate fingers w ith individual gate
widths of 1 0 0 //m . The individual gate finger width was limited to the above
values in order to avoid possible gain degradation associated with larger gate
widths [38]. The total gate width was 0 .2 mm. The separation between the
gate fingers was 1 1 4 jjm.
The large spacing between the gate fingers was
necessary in order to facilitate wire bonding to the individual drain regions. The
source/drain contact spacing was 5 jjm, 3 /vm, or 2 //m and the length of the
gate recess was 1 //m . The device gate length was 0 .7 /jm.
The Sl-lnP (Fe doped) substrates used for the layer growth were liquid
encapsulated Czochralski (LEC) grown wafers with a tw o inch diameter. The
i rfo^Q
S tU
l laoc
Ariftn+o+iArt
UllOlllQUUII
**»00
W
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O
t
11
*
1
F
1
1
\ t \ J \ J i
m ir
IC
IU
C
U
O0
iuvVqiu
U
IC
I IC
O
IC
O
L
\l
1 H1
I\ j }
direction. The layers were grown in a horizontal, low pressure reactor (Aixtron
model A IX 200). The precursors for the InP layer growth were trimethylindium
(TMIn) and phosphine (PH3). The precursors for the InGaAs layer growth were
TM In, trimethylgallium (TMGa), and arsine (AsH3). The dopant source for the
InGaAs active layer was diluted silane (2% SiH4/H 2).
Palladium diffused
hydrogen was used as a carrier gas. The TM In and TM Ga precursors were
transported from stainless steel cylinders with thermostatically controlled
temperatures of 17 C and -1 0 C, respectively. The cylinders were electronically
pressured controlled for extremely stable evaporation rates.
26
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
i
to
d
i
«
o
i
CSI
d
C
/3
U
J
UJ
U
J
H-
U
J
u.
u.
C
O
Figure 2 .6
Schematic cross section of submicron gate InGaAs MISFET
27
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
All gas flows were accurately controlled by electronic mass flow
controllers and pneumatically operated valves. For extremely sharp interface
formation all precursors were switched by a zero dead volume high speed
vent/run switching manifold.
The layers were grown at a reactor pressure of 2 0 0 0 Pa. The growth
temperature was 6 0 0 C. The total gas flow rate was adjusted to obtain a gas
velocity of 2 .2 m/sec.
For the InP layer growth, the TM In and PH3 partial
pressures were 0 .2 5 6 Pa and 148 Pa, respectively.
For the InGaAs layer
growth, the TM In, TMGa, AsH3, and SiH4 partial pressures were 0 .2 5 6 Pa,
0 .1 4 7 Pa, 59 Pa, and 0 .0 5 5 Pa, respectively.
The growth rates for the InGaAs and InP layers were 2 .9 //m /hr and
1.3 //m /hr, respectively.
The lattice parameter was matched to within
< ± 5 x 10 '4. The InGaAs mobility at 3 0 0 K was 5 5 0 0 cm2/V sec.
A cross section of the InGaAs MISFET fabrication process is shown in
Figure 2 .7 . The samples were initially cleaned by first degreasing in acetone
and methanol followed by a Dl water rinse. The samples were then dipped for
15 sec in a 1 Or 1 H20:HiF solution followed by a D! w ater rinse and then blown
dry in nitrogen. After the initial clean, a mesa etch was performed using a
1 :1:38 H 2S 0 4:H20 2:H20 solution in order to define the device active area
(Figure 2 .7A ). Source/drain contacts consisted of Au/Ge 12 w t. % eutectic and
Au evaporated to thicknesses of 1600
A and
1400
A,
respectively.
The
contacts were defined using a liftoff technique (Figure 2.7B). Ohmic contacts
were obtained by alloying for 5 min at 4 0 0 C in forming gas (10% H2/N 2).
Channel recess etching was then performed using a 1 :1 :1 0 0 H2S 0 4:H20 2:H20
solution (Figure 2.7C ).
A fter stripping the photoresist, the w afer was again cleaned and a silicon
28
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
RESIST
InGaAs
A)
MESA
InP
JZZZZ2
SOURCE/DRAIN
B)
CONTACTS
GATE RECESS
JZ7ZZ7.
. I
1777771
C)
SiO„
7777
E -B E A M SiO.
D)
GATE METAL
Au OVERLAYER
/ ..77727
M
E)
Figure 2 .7
V
Fabrication process cross sections of submicron gate InGaAs
MISFET
29
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
dioxide gate insulator was plasma deposited to a thickness of about 5 0 0 A.
The films w ere deposited using a Technics PlanarEtch I1A plasma system
modified for 1 3 .5 6 MHz operation [51].
The silicon dioxide films were
deposited at a pressure of 3 5 0 mTorr using a 50 W plasma. The substrate
temperature was 2 5 0 C. The SiH4 and N20 flow rates w ere 19 seem and 55
seem, respectively. The gate insulator post deposition treatm ent consisted of
a 3 0 0 C anneal for 3 0 min in a pure hydrogen ambient. The mesa area was
then planarized by evaporating silicon dioxide to a thickness of 3 5 0 0 A and
using a liftoff process (Figure 2.7D ).
The purpose of the e-beam oxide
planarization step was to facilitate submicrometer gate length definition in the
subsequent photolithographic step.
The gate metal consisted of Ti and Au evaporated to a thickness of
2 0 0 A and 4 4 0 0 A, respectively, and defined using a liftoff process. Finally,
source/drain oxide windows were opened and a Au overlayer was deposited to
a thickness of 4 5 0 0
A
using a liftoff process (Figure 2.7E ). The Au overlayer
assisted the current handling of the devices and facilitated wire bonding to the
drain regions.
The InGaAs MISFETs were prepared for RF packaging by first thinning
the sample backside using a (10:1:1) HCl:HN03:H20 solution. The substrates
were thinned to about 100 fjm to improve the thermal resistance and then
scribed into individual MISFETs. Backside metalization was then performed by
evaporating Ti and Au to a thickness of 2 0 0 A and 4 5 0 0 A, respectively, in
order to aid heat dissipation of the MISFETs. For the RF power measurements,
the devices were mounted on a test fixture using silver epoxy and subsequently
wire bonded.
30
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31
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 3
RF MEASUREMENTS
This chapter describes the RF measurement systems used in the
research. First, the output power measurement system used to test the one
micron gate InGaAs MISFETs at 9 .7 GHz is described. The RF measurement
system used to test the submicron gate InGaAs MISFETs at 18 - 23 GHz is also
described.
Scatter parameter measurements were also performed on the
submicron gate InGaAs MISFETs. The network analysis system is described.
In addition, the thru, reflect, line (TRL) calibration procedure, program
development, and theory are also described.
3.1
3.1.1
Output Power Measurement Systems
One Micron Gate InGaAs MISFET
Output power characterization of the 1 jjm gate length InGaAs MISFETs
was performed using a measurement system at Naval Ocean Systems Center
(NOSC) in San Diego, CA. The NOSC system had an upper frequency iimit of
10 GHz due to the bandwidth of the travelling wave tube amplifier (TW TA).
The 1 jjm gate length InGaAs MISFETs were characterized at 9 .7 GHz.
A block diagram of the NOSC microwave power measurement system
is shown in Figure 3 .1 . The system contained a signal generator which was
amplified by a TW TA . The incident power to the device under test (DUT) was
indicated by a power meter connected to a directional coupler which sampled
the output power from the TW TA . Bias networks (tees) at the input and output
of the DUT were used to apply DC gate and drain bias, respectively.
The
current limit of the bias networks was 5 0 0 mA. Input and output slide-screw
32
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u.
UJ
CO
o
LL
Figure 3.1
Block diagram of RF measurement system used to characterize one
micron gate InGaAs MISFETs
33
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 3.1
Equipment
contained
in
RF
measurement
system
used
characterize one micron gate InGaAs MISFETs
Hew lett Packard model 862 0A Sweep Generator
Hew lett Packard model 8 6 2 1 A RF Section
Varian model VZH 6970K 1D TW T A (4 .0 -1 0 .0 GHz, Gain: 35 dB)
Narda model 7 6 8 -3 medium power attenuator
Narda model 7 6 8 -3 medium power attenuator
Narda model 3202B -10 Directional Coupler (1 .0 -1 2 .4 GHz)
General Microwave model N 423 Power Head (3W AVG RF power)
General Microwave model 460B Thermoelectric Power M eter (5-3 5 dBm)
H ew lett Packard model 11590B Bias Network (1 -1 2 .4 GHz)
Microlab/Fxr model N 311A tuner (input)
N type female - SMA male adapter
SM A male - N type male adapter
Microlab/Fxr model N 3 1 1A tuner (output)
Hew lett Packard model 11590B Bias Network (1 -1 2 .4 GHz)
Narda model 7 6 6 -1 0 medium power attenuator (20W )
Hew lett Packard model 478A Thermistor Mount (0 .0 1 -1 0 GHz)
Hew lett Packard model 4 3 1 C Power Meter (Range: -2 0 -1 0 dBm)
Fluke model 88 0 0 A Digital Multimeter (Vds)
Hew lett Packard model 343 8A Digital Multimeter (Ids)
Hew lett Packard model 343 5A Digital Multimeter (Vds)
Keithley model 173A Multimeter (Ids)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
tuners w ere used to tune the DUT to the 5 0 ohm impedance of the
measurement system. Finally, the DUT output power was indicated by a power
meter. The results reported in Chapter 4 have been corrected for fixture losses.
A detailed list of the equipment contained in the system is shown in Table 3 .1 .
A fter preparing the 1 //m gate length InGaAs MISFETs for packaging as
described in Section 2.3, the MISFETs were mounted on an RF package using
a silver-filled, electrically and thermally conductive epoxy (Ablebond 606-2)
[52]. The device gate and drain pads were wire bonded to input and output
microstrip circuits using 1 mil diameter gold wire.
The source pad was
connected to the package ground using silver epoxy.
The RF package was machined from oxygen free, high conductivity
(OFCH) copper and then gold-plated. Nickel-plating was used as an interfacial
layer for adherence purposes. The RF package contained input and output
microstrip circuits to provide approximate impedance matching to the 50 ohm
system and ease of wire bonding [53]. The microstrip circuits were patterned
on 25 mil thick alumina substrates with Cr/Au metallization on both sides (TekW ave, Inc.).
The ground plane metaiiization was thicker than the top
metallization.
The microstrip patterning procedure is described in the following.
Shipley 1421 resist was spun (6000 rpm, 30 sec) on both sides of the
microstrip
to
give a
resist thickness of
about
0 .6 5
//m .
Standard
photolithography was then performed to pattern the top metallization.
The
Cr/Au metallization was then etched using the tw o solutions listed in Table 3 .2 .
The etched microstrip was then rinsed in Dl H20 . The remaining resist
was then stripped using acetone, followed by rinsing in methanol and Dl H20 .
The microstrip was then cut to size using a saw with a 8 or 20 - 30 mil blade.
35
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Prior to sawing, the microstrip was mounted on glass using machinist's w ax
with the etched side down. After sawing, the machinist's w ax was removed
by soaking in acetone.
Finally, the completed microstrip was rinsed in
methanol and Dl H 2 0 , and then mounted on the RF package using silver epoxy.
Table 3 .2
Preparation of chromium and gold etching solutions
Chromium (Cr) Etchant
Prepare saturated eerie sulfate (H ^ C e fS O ^ ) solution (i.e. heat up H20
and dissolve in eerie sulfate until no more will dissolve).
Mix 9 parts
saturated eerie sulfate solution with 1 part nitric acid (H N 0 3).
Gold (Au) Etchant
Dissolve 56 gm iodine (I) crystal and 112 gm potassium iodide (Kl) in
5 0 0 ml H 2 0 .
3 .1 .2 Submicron Gate InGaAs MISFET
Output power characterization of the submicron gate iengtn inGaAs
MISFETs was performed using a measurement system at NASA - Lewis
Research Center in Cleveland, OH. The NASA system enabled measurements
to be performed in the frequency range of 18 - 2 6 .5 GHz. The submicron gate
length InGaAs MISFETs were characterized at 18, 2 0 , and 23 GHz.
A block diagram of the NASA microwave power measurement system
is shown in Figure 3 .2 . The system layout is similar to that described earlier
for the one micron gate InGaAs MISFETs. However, an additional directional
coupler and power meter were included in the measurement system in order to
measure the reflected power prior to the test fixture.
In addition, bias tees
36
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UJ
Q .
CO
Ui
Figure 3 .2
Block diagram of RF measurement system used to characterize
submicron gate InGaAs MISFETs
37
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 3 .3
Equipment contained in RF measurement system used to
characterize submicron gate InGaAs MISFETs
H ew lett Packard model 8 35 0A Sweep Generator
Hughes model 1077H TW TA (18-26.5 GHz)
Arra model 42-220-1 OB waveguide, Systron Donner model DBE480A isolator
Hew lett Packard model K382A Variable Attenuator
Systron Donner model DBE-675 Waveguide Directional Coupler
Hew lett Packard model K752C Waveguide Directional Coupler
Right Angle Waveguide
Waveline model 801 -WLM right angle waveguide to coax transition
Male to male coax adapter, 3.5 mm to 2 .4 mm coax adapter
Male coax to microstrip launcher, Microstrip launcher to female coax
2 .4 mm to 3 .5 mm coax adapter, Male to male coax adapter
Waveline model 8 0 1 -W LM right angle waveguide to coax transition
Arra model 42-22 0-4 B waveguide, Systron Donner model DBE440A attenuator
W aveline model 8 0 1 -WLM right angle waveguide to coax transition
Hew lett Packard model 8 4 8 5 A Power Sensor (2 -2 6 .5 GHz)
H ew lett Packard model 436A Power Meter (input power)
Hew lett Packard model 8485A Power Sensor (2 -2 6 .5 GHz)
H ew lett Packard model 436A Power Meter (reflected power)
Hew lett Packard model 8 4 8 5 A Power Sensor (2 -2 6 .5 GHz)
H ew lett Packard model 436A Power Meter (output power)
4 - Fluke model 8 0 5 0 A Digital Multimeter (Vds, Ids, Vgs, Igs)
Systron Donner model TL8-3 power supply
Sorrenson model SRL20-12 power supply
38
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
were incorporated in the input and output microstrip circuits of the test fixture
in order to test devices with drain currents greater than 5 0 0 mA.
The
increased drain current limit, however, was not necessary for the InGaAs
MISFETs that were tested in this research. A detailed list of the equipment
contained in the system is shown in Table 3 .3 .
For the RF power measurements, the devices w ere mounted on the test
fixture using silver epoxy and subsequently wire bonded.
The test fixture
consisted of input and output microstrip circuits applied to a gold-plated brass
block using a sweat soldering technique. The microstrip circuits contained a
RF choke for applying DC bias while chip capacitors were used as DC blocks
across microstrip gaps.
Electrical connections between the test fixture
microstrip and measurement system were made using 2 .4 mm coax to
microstrip launchers. Impedance matching was done empirically using external
metal stubs close to the transistor. The NASA test system and the test fixture
have been described in detail previously [54], [55].
The results reported in
Chapter 5 have been corrected for fixture losses.
3 .2 Scatter Parameter Measurements
Scatter parameter measurements were performed on the submicron gate
InGaAs MISFETs using a Hewlett Packard model H P8720B network analyzer.
S-parameter measurements over a frequency range of 130 MHz to 2 0 GHz are
possible w ith the HP8720B.
However, S-parameter measurements on the
InGaAs MISFETs were only performed over the 1 0 - 2 0 GHz octave band.
In order to perform the S-parameter measurements, the InGaAs MISFETs
were mounted in a H P 83040 modular microcircuit package [56]. A photograph
of the package with a mounted device is shown in Figure 3 .3 . The package
39
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
contains 10 mil thick alumina microstrip substrates. The package consists of
tw o end blocks with 3 .5 mm coax to microstrip launchers th at contact the
microstrip launch circuits. The microstrip launch pins are factory bonded to the
launch circuits using a wrapped gold ribbon bond between the launch pin and
the circuit trace. Various size center sections of 1, 2, 5, 10, or 2 0 mm can be
used.
The end blocks and center section modules are clamped together.
Ribbon bonds (10 mil x 1 mil) are then used for connections between the
modules. Microstrip delay lines were mounted on the center sections using
silver epoxy (Ablebond 36-2) [52]. The InGaAs MISFETs were also mounted
using silver epoxy on
1
mm center sections and subsequently wire bonded.
Detailed instructions on the use of the microcircuit package are contained in an
Hew lett Packard product note [57].
3 .2.1
Netw ork Analysis Accuracy Enhancement
W hen performing network analysis (S-parameter measurements), some
type of vector accuracy enhancement is typically performed in order to
characterize systematic errors associated with the measurement system [58I,
[59]. Accuracy enhancement is also referred to as measurement calibration or
error correction. Systematic errors are the repeatable errors that the system
can measure. Other sources of network analysis measurement variations are
random or drift errors.
Random errors are non-repeatable errors which the
system cannot measure.
Measurement variations caused by noise and
connector repeatability are examples of random errors.
Drift errors are also
non-repeatable errors. Frequency drift, temperature drift, and other physical
changes in the test setup between calibration and measurement are examples
of drift errors.
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3 .3
Photograph of H P 83040 modular microcircuit package
41
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fortunately, systematic errors are the major source of uncertainty in high
frequency measurements. Since the systematic errors can be characterized,
their effect can be removed from the measured device under test (DUT) data
in order to obtain the actual DUT response. Once a calibration is performed,
the measurement accuracy and dynamic range is limited only by the system
noise and
stability,
connector repeatability,
and
the
accuracy of the
characteristics of the calibration standards that are used.
Ideally, a network analysis measurement system would have infinite
dynamic range, isolation, and directivity characteristics, as well as no
impedance mismatches in the test setup, and flat frequency response.
However, signal separation devices (e.g. directional couplers), interconnecting
cables, and the associated network analyzer measurement setup contribute
magnitude and phase errors in addition to the actual DUT vector response.
Error models typically classify these systematic errors as directivity,
source match, load match, isolation (crosstalk), and frequency response
(tracking) terms. The twelve term error model typically used in a full two-port
calibration is shown in Figure 3 .4 [60], [61]. The tw elve error terms are listed
in Table 3 .4 .
Six error terms are used in the forward direction (i.e. from port
1 to port 2).
Six corresponding terms are used in the reverse direction (i.e.
from port
2
to port
1
).
The most common full 2-port calibration typically used is referred to as
a short, open, load, thru (SOLT) calibration [58], [59]. Precision short, open,
and load standards with known characteristics are connected to the test set
ports wherever the calibration plane is intended to be established and then
measured. A precision thru standard is also connected between port 1 and port
2, and then measured. Since the expected performance of the standards is
42
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
'21 A
RF IN
XF
TF
'22 A
SF
11 A
RF
PORT 2
PORT 1
'22 M
RR
LR
'22 A
A
11A
V
e sr
A
e dr
TR
XR
Figure 3 .4
Tw elve term error model
43
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already known, a mathematical procedure is implemented in order to determine
the tw elve error coefficients associated with the system. A detailed discussion
of the algorithm is contained in reference [62]. Once the error coefficients are
determined, the actual DUT S-parameters are extracted from the measured DUT
S-parameters using the equations listed in Table 3 .5 .
A derivation of these
extraction equations is given in reference [60]. The full tw o-port error model
equations indicate that each actual DUT S-parameter is a function of all tw elve
error coefficients and all four measured DUT S-paramters.
Table 3 .4 Error coefficients in full two-port error model
Edf - forward directivity
Edr - reverse directivity
ESp - forward source match
Esr - reverse source match
Erf - forward reflection tracking
Err - reverse reflection tracking
EXp - forward isolation
EXr - reverse isolation
E|_p - forward load match
E|_r ‘ reverse load match
E7 f - forward transmission tracking
Ejr - reverse transmission tracking
The SOLT calibration is well suited for coaxial test sets. However, the
SOLT calibration is not easily implemented in microstrip because of the
difficulty of characterizing precision microstrip standards.
3 .2 .2 Thru, Reflect, Line (TRL) Calibration
The H P 830 40 modular microcircuit package was used as a test fixture
for the characterization of the InGaAs MISFETs because of the ease with which
a thru, reflect, line (TRL) calibration could be implemented [63], [64], A TRL
44
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Table 3 .5
Full tw o-port error model equations
_
A [ 1 + ID ) (ESR) ] - U B ) (C ) (El f ) ]
S l v > = ------------------------------- S-----------------------------_
[ 1 * D
(Es„ - El f ) 1 [31
*b21>4 ~ -----------------------7----------------------
.
[ 1 + A (E sf - El r ) ] [C l
5 12A ~ --------------------- 7-------------------
_
D [ 1 + [A ) (Es f ) } ~ [ { B ) ( C ) (El r ) ]
^ 2 2A ~ ----------------------------------- 7----------------------------------
A = [
1
+ (A ) [ESF) 1 I 1 + \D ) (Es r ) ] - [ IB) ( C ) [ELF) (ELR) ]
e df
A =
Erf
B = S 2Utf ~
exf
e tf
S \2 M ~ e x r
e tr
D = S 22M ~
e dr
e rr
45
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
calibration was used in order to move the calibration reference planes up to the
device under test (DUT). This was necessary since a full two-port calibration
at the netw ork analyzer measurement cables would produce results that
included the parasitics associated with the package and, thus, obscure the
actual DU T performance.
In order to perform the TRL calibration, the measurement of three
standards w as necessary. The THRU standard was obtained by ribbon bonding
the end blocks of the package together. The REFLECT standard was either an
OPEN or a SHORT. The OPEN was obtained using the tw o open end blocks.
The SHORT standard was obtained by ribbon bonding the end blocks to a
1 mm bare center section. Finally, the LINE standard was obtained by ribbon
bonding a 2 mm DELAY line between the end blocks.
3 .2 .2 .1
TRLCAL Program Development
Since network analysis measurements are time consuming and data
intensive, it was decided to automatically control the network analyzer using
a personal computer. An IBM PS/2 model 5 0 was used as the main controlling
computer. The PS/2 was equipped with a Capital Equipment Corporation (CEC)
general purpose interface bus (GPIB) card (model P S < > 4 8 8 ) , and was
configured as a GPIB controller.
In addition, an IBM X T computer equipped
with another CEC GPIB card (model PC< > 4 8 8 ) was connected to the bus and
configured as a GPIB talker/listener. The additional computer controlled a stack
of HP personal computer interface bus (PCIB) instruments.
The PCIB
instruments were used as gate and drain bias supplies. Other instruments on
the bus included a H P 7575A plotter for obtaining hard copies.
Finally, tw o
Keithley model 1 7 9 3 /6 4 2 3 digital multimeters were used to monitor gate
46
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
voltage and drain current. The gate and drain biases were applied to the DUT
using the internal bias tees of the network analyzer. A list of reserved GPIB
instrument addresses used w ith the measurement system as well as other
instruments connected to the bus is shown in Table 3 .6 .
A program w as w ritten using Microsoft QuickBasic 4 .5 in order to
implement a TRL calibration procedure and perform automated measurements
with data logging capabilities. The final program (TRLCAL.EXE) consisted of
the following seven program modules: 1) MENUTRL1 .BAS, 2) MENUTRL2.BAS,
3) TRL.BAS, 4) HP8720B.BA S, 5) TRLPLOT.BAS,
6
) PLOTHP.BAS, and 7)
PCIBCNTL.BAS. The MENUTRL1 .BAS program module was the main program
module
that
created
a
user
interface
using pull-down
menus.
The
M ENUTRL2.BAS program module controlled file management operations and
contained additional user interface routines.
The TRL.BAS program module performed network anaiyzer control
functions and all TRL calibration mathematics.
Source code contained in
reference [6 5 ], which w as w ritten in HP BASIC, was extremely helpful in
developing this program module.
The
HP8720B.BAS
program module
controlled data acquistion and transfer interface functions between the
computer and the netw ork analyzer. All data transfers between the computer
and netw ork analyzer were done using a binary format.
All screen and plotter graphics were controlled by the TRLPLOT.BAS
program module.
The PLOTHP.BAS program was a generic module for
controlling Hewlett-Packard
plotters using HP graphics language (HPGL)
commands. The procedures contained in PLOTHP.BAS were accessed only by
the TRLPLOT.BAS program module.
The PCIBCNTL.BAS program module controlled interface functions
47
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Table 3 .6
Reserved GPIB Instrument Addresses
0 = PS/2 model 50 computer (controller)
1 = XT computer (talker/listener: controls PCIB instruments)
2 = Keithley 177 Microvolt D M M non-trigger address (Vds)
3 = Keithley 177 Microvolt D M M trigger address (not used)
4 = Plotter
16 = H P8720B Network Analyzer (1 3 0 M Hz - 20 GHz)
17 = Analyzer display (not used)
2 4 = Keithley 177 Microvolt D M M non-trigger address (Ids)
25 = Keithley 177 Microvolt D M M trigger address (not used)
Cryogenic Measurement System instruments (not used)
5 = Keithley model 181 Nanovoltmeter
14 = Lake Shore model 805 Temperature Controller
1 9 = Keithley model 2 2 4 Programmable Current Source
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
between
the
controlling
computer and the
taiker/listener X T computer.
PCIB
instruments
via the
The final linked executable file (TRLCAL.EXE)
contained more than 260K bytes.
The program used a DOS device driver (CECHP.EXE) that allowed the use
of Hew lett Packard style commands to control the GPIB instruments. Once the
driver was loaded, it was opened as a file within the program and then
accessed using PRINT and INPUT commands.
Lists of reserved files used in
the program and reserved file names used by the program are shown in
Tables 3 .7 and 3.8 , respectively.
The program user interface generated seven main menus (File, Bus/ANA,
SetUp, Measure, Calculate, Send, and Plot) that were activated by pressing
"hot" keys and erased by pressing the Escape key. The menu options were
scrolled through using up and down arrow keys, and options were selected by
pressing the Enter key.
The File menu options controlled file management
operations, and the transfer of data between the controlling computer and the
network analyzer.
The file management options included the saving and
loading of TRL calibrations, DUT measured data, and DUT extracted data. In
addition, Touchstone 2-port files could be generated from DUT extracted data.
The transfer of data between the controlling computer and the network
analyzer included downloading and uploading of configuration files, error
coefficient sets (cal sets), and raw measurement data.
The Bus/ANA menu options controlled the GPIB, as well as, network
analyzer display options (log-MAG chart, phase, delay. Smith chart, polar,
linear-MAG chart, real, and SWR).
The Setup menu options prepared the
network analyerfor measurements, controlled the gate and drain bias supplies,
and also setup automatic measurement sequences. The Measure menu options
49
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Table 3 .7
Reserved files within TRLCAL program
File # 1 : (CECHP driver) output to IEEE-488 bus
File #2: (CECHP driver) input from IEEE-488 bus
File #3: (CECHP driver) binary input from or output to IEEE-488 bus
Table 3 .8
Reserved file names (filename.extension) used by TRLCAL program
*.C A L - TRL Calibration
*.C LS
- Calibration Set
*.F IG
- Configuration
*.M D T - Measured Data
*.E D T - Extracted Data
*.B IA
- Measurement Bias Data
*.S 2 P
- Touchstone 2-port file
T H R U .S 1 1, .S12, . S 2 1, .S22
- Measured THRU standard
REFLECT.S11, .S22
- Measured REFLECT standard
D ELA Y.S11, .S 12, . S21, .S22 - Measured DELAY standard
D U T M .S 1 1, .S12, . S 21, .S22 - Measured Device Under Test
t
D U TE.S11, .S12, . S 21, .S22
- Extracted Device Under Test
50
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controlled measurement of the THRU standard, REFLECT standard, LINE
standard,
and the
DUT.
After the
measurement,
the
corresponding
measurement data array was filled for later use within the program.
The Calculate menu options performed the TRL calibration mathematics
in order to determine error coefficients. In addition, actual DUT data could be
extracted from the measured DUT data and the calculated error coefficients.
The Send menu options allowed calibration sets (error coefficients) to be sent
to the netw ork analyzer, as well as, DUT raw or extracted data. Finally, the
Plot menu controlled the generation of screen or hard copy plots of the THRU,
REFLECT, DELAY, and DUT measurement data, as well as, DUT extracted data.
3 .2 .2 .2 TRL Calibration Theory
This section describes the theory of the TRL calibration algorithm [63],
[6 4], [65], [ 6
6
], [62]. Recently, efforts have been made to develop generalized
theories on network analyzer calibration that incorporate TRL and variations
such as line, reflect, line (LRL) calibration [67], [6
8
], [69], [70], [71], [72]. This
discussion, however, will concentrate on the straight-forward mathematics
used by the TRLCAL program described above.
In order to perform the TRL calibration at a single frequency, S-parameter
measurements must be performed with the THRU, REFLECT, and LINE (DELAY)
standards inserted at the reference plane.
Four measurements are obtained
from the THRU standard (S11MT, S2-|MT, ^ i 2 MT' ^ 2 2 mt^ Tw o measurements
are obtained from the
REFLECT standard
(S11MR, S22MR).
And» four
measurements are obtained from the DELAY standard (S11MD, S21MD, S 12MD,
s 22Md)Requirements for the standards include the following.
The THRU
51
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
standard must have a zero length. The reflection coefficient of the REFLECT
standard must be identical on both ports.
The magnitude of the reflection
coefficient is optimally 1.0, but does not need to be known. The phase of the
reflection coefficient must be known within ± 9 0 degrees in order to determine
a root choice in the solution of a quadratic equation.
The DELAY standard
characteristic impedance (typically 50 Q) determines the reference impedance
of the measurement. The DELAY standard insertion phase relative to the THRU
should be between 2 0 ° - 160° ± n x 18 0 °.
Errors are generated when the
insertion phase is 0 ° or integer multiples of 1 8 0 °. Optimal DELAY line length
is a quarter wavelength or 9 0 ° of insertion phase relative to the THRU at the
center of the measurement frequency span.
The usable measurement
bandwidth for a single THRU/DELAY pair is 8:1
frequency).
Other details of the standard
(frequency spamstart
requirements are given in
reference [73].
In developing the TRL theory, the tw elve term error model described in
Section 3 .2 .1 is modified to an eight term error model using the following
assumptions. First, the isolation error terms are assumed to be zero, which is
typically a good assumption. In addition, the forward source match is assumed
to be equal to the reverse load match. In a similar manner, the reverse source
match is assumed to be equal to the forward load match. The resulting eight
term error model is shown in Figure 3.5 [74].
The tw elve term error model
coefficients in terms of the eight term error model coefficients are listed in
Table 3 .9 [74].
Once the eight error terms are determined, the actual DUT
performance can be extracted from the measured DUT data using the twelve
term error model equations listed in Table 3 .5 .
Since the eight term error model shown in Figure 3 .5 consists of three
52
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
UJ
cc
CM
CO
CO
CM
111
CM
CM
UJ
o
£E
CC
Ul
UJ
ADAPTER
CO
CO
CM
I—
I
CC
o
Q.
<
CM
CM
DUT
<
co
CM
CM
co
co"
CO
F*
I
CC
cc
UJ
JEm
UJ°I A
o
o
o
UJ
o
cc
cc
UJ
ADAPTER
O
0.
UJ
Figure 3 .5
Eight term error mode!
53
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
cascaded tw o-port networks, it is convenient to convert the S-parameters of
the individual networks to wave-cascading (R) parameters. The definitions for
S-parameters
and
R-parameters are
listed
in Equations 3.1
and
3 .2 ,
respectively, [75], [76], [62]. The conversion equations from S-parameters to
cascade
parameters, and vice-versa, are listed in Eq's. 3 .3
and 3 .4 ,
respectively.
Table 3 .9
Error term translations between
8
and 12 term models
e sr
= e22
ERF = E10E01
e rr
= E32E23
e xr
= 0
e lr
= E11
e tr
= >=23^1
X
Tl
II
ESF ~ E 11
ELF -
o
= E33
m
o
o
UJ
II
u.
O
UJ
e dr
E22
ETF = E32E 10
The S-parameter matrix and cascade matrix for the THRU standard are
defined in Eq. 3 .5 . The S-parameter matrix and cascade matrix for the DELAY
standard, which assume a frequency independent 50 ohm match, are defined
in Eq. 3 .6 . The complex propagation constant is denoted as yand the DELAY
line length as I. The cascade matrices for error adapter X and Y are defined in
Eq. 3 .7 .
The use of cascade parameters allow the overall cascade matrix of the
error model (measured DUT data) to be determined from the product of the
individual cascade matrices (error adapter X, actual DUT data, error adapter Y)
as shown in Eq. 3 .8 .
The actual DUT data can, thus, be extracted and
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
converted back to S-parameters.
W hen the THRU standard is inserted, the measured THRU data (Rmj) is
obtained from Eq. 3 .9 . In a similar manner, the measured DELAY data (RMD)
is obtained from Eq. 3 .1 0 when the DELAY standard is inserted. Eq. 3 .9 can
then be solved for RY as shown in Eq. 3 .1 1 .
Using Eq. 3.11 in Eq. 3 .1 0
produces Eq. 3 .1 2 , which can be put in the form shown in Eq. 3 .1 5 using the
intermediate steps shown in Eq.'s 3 .1 3 and 3 .1 4 .
Expansion of matrix
Eq. 3 .1 5 produces the four "M " coefficient equations listed in Eq.'s 3 .1 6 3 .1 9 . Eq. 3 .1 6 and Eq. 3 .1 8 can be used to eliminate the e' * ' 1 terms, and then
form the quadratic equation shown in Eq. 3 .2 0 . In a similar manner, Eq.'s 3 .1 7
and 3 .1 8 can be used to obtain the quadratic equation shown in Eq. 3 .2 1 .
Since Eq. 3 .2 0 and 3.21 have the same coefficients (M 21,
and M 12), both equations have the same roots A and B, which are shown in
Eq.'s 3 .2 2 and 3 .2 3 .
These equations result from the cascade matrix
definitions in Eq.'s 3 .7 and 3 .3 . The tw o roots are also distinct [64]. In order
for the roots not to be distinct would require E1 0 E0 1
= 0 (S2 1 S 1 2 = 0) for error
adapter X , which cannot be true for a practical measurement system [64]. The
problem of root choice is resolved by choosing the greater magnitude root to
be equal to A [64], [62]. Eq.'s 3 .2 2 and 3 .2 3 can then be used to obtain Eq.
3 .2 4 .
In a similar manner, Eq. 3 .9 can be solved for Rx as shown in Eq. 3 .2 5 .
Using Eq. 3 .2 5 in Eq. 3 .1 0 produces Eq. 3 .2 6 , which can be put in the form
shown in Eq. 3 .2 9 using the intermediate steps shown in Eq.'s 3 .2 7 and 3 .2 8 .
Expansion of matrix Eq. 3 .2 9 produces the four "N" coefficient equations listed
in Eq.'s 3 .3 0 - 3 .3 3 . Eq. 3 .3 0 and Eq. 3.31 can be used to eliminate the e
terms, and form the quadratic equation shown in Eq. 3-34. In a similar manner,
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Eq.'s 3 .3 2 and 3 .3 3 can be used to obtain the quadratic equation shown in
Eq. 3 .3 5 .
The roots of the quadratic equations, C and D, are obtained in a
similar manner as described above for roots A and B, and are listed in
Eq.'s 3 .3 6 and 3 .3 7 . Eq. 3 .3 8 results from the use of Eq.'s 3 .3 6 and 3 .3 7 .
A t this point, the error coefficients E0
0
and E3
from the THRU and DELAY measurements.
3
have been determined
The REFLECT measurement
information (S11MR, S 22M r ) 's now necessary to resolve the remaining error
coefficients. Using Eq. 3 .3 9 , which is obtained from signal flow graph theory
of tw o-port networks [77], Eq. 3 .4 0 can to adapted for the eight term error
model when the REFLECT standard is connected to port 1 of error adapter X.
Eq. 3.41 is then obtained by rearranging Eq. 3 .4 0 and using Eq.'s 3 .2 2 and
3 .2 3 . Similarly, Eq, 3 .4 2 is obtained with the REFLECT standard connected to
port 2 of error adapter Y. Eq. 3 .4 3 is then obtained by rearranging Eq. 3 .4 2
and using Eq.'s 3 .3 6 and 3 .3 7 .
An equation relating E2 2 and En , which is
obtained from Eq.'s 3.41 and 3 .4 3 , is shown in Eq. 3 .4 4 .
Another equation relating E2 2 and E ^
is obtained from the THRU
measurement {St 1MT) and is listed in Eq. 3 .4 5 . Rearranging Eq. 3.45 and using
Eq.'s 3 .2 2 and 3 .2 3 produces Eq. 3 .46. The tw o equations relating E2 2 and
E1V Eq.'s 3 .4 4 and 3 .4 6 , can now be used to obtain Eq. 3 .4 7 . The sign ( ± )
of the square root can be resolved using Eq. 3.41 and knowledge of the
REFLECT standard. For example, an OPEN standard should produce a reflection
coefficient with a phase near 0 degrees, while a SHORT standard should
produce a reflection coefficient with a phase near 180 degrees.
N ow since E-,-, is known, E2 2 can be determined from Eq. 3 .4 6 (or Eq.
3 .4 4 ). The error terms E1 0 E0 1 and E3 2 E2 3 can then be determined from Eq.'s
3 .2 4 and 3 .3 8 , respectively. The error terms E0q and E3 3 are already known
56
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
from Eq.'s 3 .2 3 and 3 .3 7 , respectively.
E 1 0 E3
2
The remaining error coefficients,
and E23^ov are obtained from the THRU measurement transmission
terms (S2im t anc*
Applying signal flow graph theory to the eight term
error model and using Mason's Rule [77], Eq.'s 3 .4 8 and 3 .4 9 can be derived
fairly easily. Rearranging Eq.'s 3 .4 8 and 3 .4 9 produces Eq.'s 3 .5 0 and 3 .5 1 ,
respectively, which are then used to determine E 1 0 E3 2 anc^ ^23^01Since ten measurements were performed but only eight unknowns
determined, the redundant information can be used to determine the following.
The complex propagation constant (y) can be determined from Eq.'s 3 .1 6 3 .1 9 or Eq.'s 3 .3 0 - 3 .3 3 if the DELAY line length (I) is known accurately. In
addition, the reflection coefficient of the REFLECT standard (rAR) can be
determined from Eq. 3.41 or Eq. 3 .4 3 , and then used to verify the calibration
procedure, or as an absolute measure of the unknown REFLECT standard [62].
All calculations within the TRLCAL program w ere performed using a
double-precision format in order to maintain accuracy. Since QuickBasic can
not handle complex mathematics, all equations used in the TRL calibration were
spiit into real and imaginary components within the TRLCAL program.
57
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.1)
bi
^2
(3.2)
b]
a-j
— + S-12^2
= ^21*^1 + $22&2
= /?h32 + R 12^2
= /?21^2 + ^22^2
f l 12
^11
(3.3)
(3.4)
S1 2 S2 1
/? =
_1_
$21
=
/?21
/?22_
5 11
S l2
_ 5 i i S 22
- S 22
/?12
S-i-j
1
^11^22 " ^12^21
1
S =
CM
,C M
/?22
CO
S2i
1
-/?21
1
0
(3.5)
1'
Sr =
o'
_0
1_
; /?r -
_1
0
1
Q>
O
1*
1
SD =
;
e~y'
0
0
eY‘.
Rq -
O
.
1
CD
1
(3.6)
'1
* 1 1
(3.7)
X 12
Rx =
V'n
^12
^21
Y22_
; Ry *21
X 22_
58
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.8)
Rm -
(3.9)
rmt
(3 .1 0 )
R m D = ^X^AD^Y
(3.11)
R Y = Rx ^ m t
(3.1 2)
R m d = Rx Raq R x
(3.1 3)
RmdP mt - RxRadR x
(3 .1 4 )
Rmd Rmt ^ x = Rx Rad
-
r x ^ a 7^ y
= RxRy
rmt
Mu
(3.1 5)
M 12
MRX - Rx ^ ad ’ M - r m dr m t =
m 21 M 2 2
(3.1 6)
M n X ii + ^
1 2 ^ 2 1
= ^
1 1
® ^
(3.1 7)
^
+ ^
1 2 ^ 2 2
= ^
1 2
®^
(3.1 8)
M z i^ n + ^
2 2 ^ 2 1
= ^
2 1
® ^
(3.1 9)
A ^21^12 +
22^22
~
1 1 ^ 1 2
M
-^22®*^
2
(3.2 0)
(3.2 1)
M 21 ^ 1 1
X21
/w21
+ (yw22 - ^
(3.2 3)
*
=
*1 2
X 21
)
* 1 1
-
M 12 = 0
-
m
*2 1
(M 22 ~ ^
*2 2
(3.2 2)
1 1
1 1
)
*1 2
X 22
12 = 0
= Eoo - l l ?£ ^
■11
R -- —
* 12 -- El
F00
B
x 22
(3.2 4)
B - A _= *10*01
:11
59
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.25)
Rx = R m t *
(3.26)
R m d = Rm t ^
(3.27)
Rm j R m d ~ R y ^ ad R y
(3.2 8)
R y^ mt R m d = Rad ^
y
y
Ra d R y
y
Nu
(3.2 9)
RyN =
; /V =
/Vi2
=
yv2i N 22_
/ v 21y l2 = y 1i e -K /
(3.30)
NU Y„ +
(3.31)
ZVi2^11 + ZV2 2 V 12 = Y ,2e-y!
(3.32)
^ 11^21
(3.33)
^12^2 1 + N 22Y22 ~ Y22ey'
n
+
2, y 22 = Y2, e y‘
>2
(3.34)
n
,2
V 'll
r
+ W 22
-
/Vn)
Yu
/v21 = o
*1 2
[ /12J
-j 2
(3.35)
nm
*21
+ (/V22 - /V-| 1 )
*2 2
(3.36)
/v21 = o
*2 2
c
, E32E23
C = 111 _
- ~E33 + — P-----^12
(3.37)
*21
b 22
D = 1 1 1 ~ ~E33
*2 2
(3.38)
_ E32E23
C - D =
E22
(3.39)
f//v - S „
(3.40)
^ MRX ~ E00 +
+ ^ 2S2^ l
i - s 22r/.
fn01c
i^ ir>
10‘r AR _ s
11/W?
1 - Eh
1 1T'
60
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3 .4 1 )
r AR = _ L
b
- r AOTX
+
2 3
32
_ S2 2 /Wff
1 “ C22'AR
fcn
(3 .4 2 )
TM R y
(3 .4 3 )
r ,,* =
-
£ 3 3
* r MRY
c + r /w?y
d
'
‘-2 2
r
(3 .4 4 )
( 3 .4 5 )
(3.4 6)
(3.47)
(3 .4 8 )
£2
1
A - r MRX
2
=
^
1
D + t MRY
1
_b - r m r x _
_ c
+ r yw/?/
rr M 7X —
F
j. ^01^10^22 _ o
- to o + -=
p — c — - o 11/WT
' “ ^11^22
£ 2 2
=
1
B ~ r MTX
*11
A - •"MTX
b
C 11
c + r JW?/
d + r /w?y
- r mtx
A - f MTX
S 2 i/w r =
£ ~ r /W?X
- r /WflX
Biq E32
1 ~ ^11^22
(3.4 9)
S 1 2 /V/ 7 =
E2ZEQ\
1 _ ^11^22
(3.5 0)
£io^32 = $21/177 ( 1 _ ^ 1 1 ^ 2 2 )
(3 .5 1 )
£2 3 ^ 0 1
= $12/W7( 1 “ ^ 1 1 ^ 2 2 )
61
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
62
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 4
ONE MICRON GATE InGaAs MISFET RESULTS
This chapter describes the results obtained w ith the one micron gate
length, ion implanted InGaAs MISFETs. Devices with both plasma deposited
silicon dioxide and silicon/silicon dioxide gate insulators were fabricated.
Results obtained on the devices with silicon dioxide gate insulators were limited
for reasons described below. However, both DC and RF results are presented
for the devices w ith silicon/silicon dioxide gate insulators.
The DC results
include the device l/V characteristics and the result of drain current drift
measurements. The RF results obtained at 9 .7 GHz are also presented.
4.1
InGaAs MISFETs with Silicon Dioxide Gate Insulators
4 .1 .1 DC Characterization
The current-voltage (l-V) characteristics of an InGaAs MISFET with a
silicon dioxide gate insulator are shown in Figure 4 -1 . The l-V characteristics
were obtained using a Tektronix model 5 7 7 curve tracer. The gate width of the
device was 2 0 0 //m .
The horizontal scale is 0 .5 V/division and the vertical
scale is 2 0 mA/division. The gate voltage step is -2 V . The upper trace is for
a gate-source voltage of 0 V.
A t a drain-source voltage of 5 V, the drain
saturation current was about 75 mA, which corresponds to a drain current
density of 3 7 5 m A/m m . The device pinchoff voltage was about -1 4 V . The
transconductance (gM) is defined as the partial derivative of drain-source
current with respect to gate-source voltage (3IDS/3V GS) at a constant drainsource voltage. The device transconductance was typically about 4 0 mS/mm.
The devices had typical drain-source breakdown voltages of 4 -
6
V. The gate-
63
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I
Figure 4.1
l-V characteristics of 1 jjm gate InGaAs MISFET with silicon
dioxide gate insulator.
Horizontal: 0 .5 V/div. Vertical: 2 0 mA/div.
Gate (V GS): -2 V/step.
64
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
source and gate-drain breakdown voltages were greater than 23 V.
An
extensive investigation of breakdown properties was not performed, however,
in order to save devices for subsequent RF testing.
The devices were typically fabricated on 1 .0 cm x 1 .2 cm samples
because o f the small availability of substrate material for this research. Initially,
during the recess etching part of the device fabrication, target saturation
current densities were about 1 2 0 mA for a 2 0 0 //m gate width device (SD
S 0
=
6 0 0 m A/m m ), and were typically measured at drain-source voltages of 2 .5 3.5 V . This lDSo value was used as a starting point based on previous similar
device research on InP substrates [37], [38], [39].
The l-V characteristics displayed in Figure 4.1 were obtained at the
periphery of the sample. However, due to recess etch non-uniformities mainly
cause by photolithography variations, the saturation current densities were
greater in the center of the sample. The device saturation current densities
were as high as 7 0 0 - 9 0 0 m A/mm for these devices. As the saturation current
density increased above about 3 7 5 m A/mm, the devices could not be pinched
off. In addition, as the device saturation current density increased, the drainsource breakdown voltage tended to decrease with a resulting RF performance
degradation as described below.
4 .1 .2 RF Characterization
The goal of the output power measurements was to obtain high output
power w ith a power gain of at least 3 dB, which implies an output power of
about tw o times the input power.
A total of four devices were tested.
However, the best power gains obtained for the MISFETs with silicon dioxide
gate insulators at 9 .7 GHz were only 2 .2 - 2 .9 dB.
A summary of the best
65
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
results obtained is listed in Table 4 .1 . The device gate-source and drain-source
bias voltages are denoted as V GS and V DS, respectively.
The input power
applied to the device and the resulting output power are denoted as P!N and
P0 uT» respectively.
The input and output power units (dBm) are decibels
referenced w ith respect to a milliwatt (mW ). The conversion equation between
dBm and mW is, thus, (dBm) = 10 log (m W ). For example, 3 0 dBm is equal
to 1 W (i.e. 1 0 0 0 mW ). The power gain is defined as P q ut^in- W hen using
input and output powers specified in dBm, the power gain in dB is the
difference in output power and input power. The output power density (Pdout)
is defined as the output power per unit gate width (W /m m ). Finally, the poweradded efficiency (ePA) is defined as [(Pout ' pin^ *v ds x tas^' anc* is usua,,Y
given as a percentage.
Table 4.1
One micron gate InGaAs MISFET results (silicon dioxide gate
insulator)
\
gs
(V)
V DS
(V)
*DS
(mA)
PIN
(dBm)
(dBm)
Gain
(dB)
f PA
(%)
(W/mm)
POUT
PDOUT
0
4 .6
432
2 4 .0
2 6 .9
2 .9
1 2
0 .6 5
0
4 .6
411
2 5 .0
2 7 .6
2 . 6
14
0 .7 7
0
4 .6
382
2 6 .0
2 8 .2
2 . 2
16
0 . 8 8
The device summarized in Table 4.1 had a saturation current density of
about 8 3 0 mA/mm as determined from curve tracer measurements both prior
to and after RF testing. The device total gate width was 0 .7 5 mm. The device
transconductance was about 3 0 mS/mm.
It is believed that the low power
66
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
gains obtained were partially due to the device saturation current density being
to high in these devices, which placed an upper limit on the drain-source bias
that could be applied to the devices before a catastrophic breakdown occurred.
Typically, in orderto increase gain at a fixed drain-source bias, the device
saturation current density must be increased, which causes an increase in the
device transconductance (gM).
However, a tradeoff is involved in trying to
optimize the device for both gain and output power.
For example, as the
saturation current density is increased, the gain and output power will initially
increase. However, further increases in saturation current density will decrease
the device drain-source breakdown voltage w ith a corresponding reduction in
output power density and power gain.
Thus, a great empirical effort is
necessary in order to optimize the devices for output power density and gain.
Because the above RF results did not indicate power gains greater than
3 dB, extensive characterization of these devices was not pursued any further.
However, RF measurements of these early devices indicated an upper limit for
device saturation current densities in the remainder of the research.
4 .2
InGaAs MISFETs with Silicon/Silicon Dioxide Gate Insulators
4 .2 .1 DC Characterization
A photograph of a fabricated InGaAs MISFET with a 1 mm total gate
w idth is shown in Figure 4 .2 . The l-V characteristics of an InGaAs MISFET
w ith a silicon/silicon dioxide gate insulator are shown in Figure 4 .3 . The gate
width of the device was 2 0 0 //m . The horizontal scale is 0 .5 V/division and the
vertical scale is 20 mA/division. The gate voltage step is -2 V. The upper trace
is for a gate-source voltage of 0 V. At a drain to source voltage of 4 V, the
drain saturation current was 105 mA, which corresponds to a drain current
67
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4 .2
Photograph of fabricated 1 //m gate InGaAs MISFET with 1 mm
total gate width.
68
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4 .3
l-V characteristics of 1 //m gate InGaAs MISFET with silicon/silicon
dioxide gate insulator.
Horizontal: 0 .5 V/div. Vertical: 20 m A/div.
Gate (VGS): -2 V/step.
69
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
density of
525
mA/mm.
The transconductance was
typically
about
20 mS/m m. The devices had typical drain-source breakdown voltages of 5 7 V.
The gate-source and gate-drain breakdown voltages w ere greater than
23 V. Only a very slight hysteresis was present in the l-V curves. In addition,
complete pinch-off of the drain current was not achieved in a manner similar
to that observed by other workers [32], [33], [35]. The lack of DC pinch-off
may be due to the formation of an inversion layer which screens the undepleted
channel from further gate control [32], [35].
At microwave frequencies,
however, this phenomenon is not expected to degrade device performance.
The results of the drain current drift measurement o f an InGaAs MISFET
with a
2 0 0
//m gate width and a silicon/silicon dioxide gate insulator are shown
in Figure 4 .4 .
The drain-source bias was 2.5 V. The gate-source bias was
initially 0 V and the drain current was 8 4 .3 mA. Immediately prior to the start
of the drift measurement, the gate-source bias was switched to -5 V which
reduced the drain current to 5 7.5
mA.
Thus, during the entire drift
measurement, the channel w as partially depleted with the drain current at
approximately 7 0 % of its zero gate bias value. The drain current increased only
4 % over a period of 10 4 sec. The general trend of the data indicates an initial
increase in drain current over the first 3 5 0 sec followed by a decrease toward
the initial drain current value. The fact that the drain current can be held at a
reduced level with negative gate bias under strictly DC conditions is an
important result which reflects the potential usefulness o f the devices. The
results indicate that the devices can be maintained in a partially pinched
condition over extended time periods and, thus, provide a potential solution to
the RF burnout phenomenon described below.
70
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ELAPSED TIME (log sec)
^
CD
ih
O
iN a a a n o Nivaa a a z n v w a o N
Figure 4 .4
Drain current drift measurement o f 1 //m gate InGaAs MISFET with
silicon/silicon dioxide gate insulator.
71
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4 .2 .2 RF Characterization
Figure 4 .5 shows the output power and power-added efficiency as a
function of input power from 2 2 dBm to 2 6 dBm for a 1 //m gate length InGaAs
M ISFET w ith a total gate width of 1 mm. The measurements were performed
at a frequency of 9 .7 GHz using a gate-source bias of 0 V and a drain-source
bias of 5 V. The device saturation current density was 7 7 0 mA/mm of gate
w idth. An output power density of 1.07 W /m m of gate width was obtained
w ith a corresponding power gain and power-added efficiency of 4 .3 dB and
3 8 % , respectively, for an input power of 2 6 dBm.
demonstration of an output power greater than
1
This was the first
W for an InGaAs based
transistor on InP. The highest power-added efficiency obtained was 4 0 % with
a corresponding power gain and output power density of 4 .8
dB and
0 .9 6 W /m m , respectively, at a drain-source bias of 4 .5 V and an input power
of 2 5 dBm.
Variation of power gain as a function of input power in the range of
2 2 dBm to 26 dBm is illustrated in Figure 4 .6 . The gate-source bias and drainsource bias were 0 V and 5 V, respectively. The power gain decreases with
an increase in input power and, thus, indicates that the device is operating in
compression. At an input power of 22 dBm, the power gain was 6 .9 dB with
a
corresponding output power density and
0 .7 8 W /m m and 2 9 % , respectively.
power-added efficiency of
As the input power was increased to
2 6 dBm, the power gain decreased to 4 .3 dB.
In addition, the drain bias current decreased from 4 3 2 mA to 351 mA as
the m icrowave input power was increased from 22 dBm to 2 6 dBm.
This
effect arises from the nonlinearity of the device l-V characteristics at positive
gate voltages when the device is operated under large signal conditions in
72
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■a
CC
40
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29
35
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22
23
24
25
26
POWER-ADDED
45
£
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EFFICIENCY
(%)
50
25
27
INPUT POWER (dBm)
Figure 4 .5
Output power, power-added efficiency vs. input power at 9 .7 GHz
(VDS = 5 V, V GS = 0 V).
73
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
8
GAIN
(dB)
7
6
5
4
3
21
22
23
24
25
26
27
INPUT POWER (dBm)
Figure 4 .6
Power gain vs. input power at 9 .7 GHz (VDS = 5 V, V GS = 0 V).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
compression. Large positive RF signal excursions are not as effective in varying
the drain current as large negative signal excursions. Thus, as the RF input
power is increased, the drain bias current decreases on the average.
Results were not obtained at lower input powers because the devices
display a burnout phenomenon similar to that described previously for
comparable geometry InP power MISFETs [3 8]. As described above, the drain
current increases with a decrease in input power. In order to apply sufficient
drain bias voltage to yield high output power, a minimum input power level
must be applied to keep the drain current low enough to prevent a destructive
thermal breakdown. Therefore, the input power range is restricted to regions
that drive the device into compression.
Figure 4 .7 illustrates the output power and normalized drain bias current
(IDs /I dso ) variation of a representative 1 mm gate width device over a 2 4 hour
period. The RF input power, drain-source bias voltage, and gate-source bias
voltage were held constant at 25 dBm, 4 .8 V , and -5 V, respectively. The
measurement frequency was 9 .7 GHz and the initial drain bias current (lDso)
was 2 5 6 mA. The output power was stable to within 1 .2 % , and the drain bias
current increased less than 4% over 2 4 hours of continuous operation. This
was the first report of RF output power stability measurements on InGaAs
MISFETs.
A summary of other results obtained for the one micron gate InGaAs
MISFETs w ith silicon/silicon dioxide gate insulators is listed in Table 4 .2 . The
results of device A were described above. Devices B and C had gate widths
of 1 mm and 0 .7 5 mm, respectively.
The saturation current densities for
devices B and C were about 650 mA/mm and 7 7 0 mA/mm, respectively.
Device C also produced output power densities of about 1 W /m m . The highest
75
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
£
CURRENT
30
29
CD
28
DRAIN
m
BIAS
T3
o
CL
H
27
NORMALIZED
3
CL
H
3
O
OA
25
0
1
10
100
1000
ELAPSED TIM E (m in )
Figure 4 .7
Time dependence of output power and drain bias current at
9 .7 GHz.
76
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 4 .2
One micron gate InGaAs MISFET results (silicon/silicon dioxide
gate insulator)
V GS
V DS
*DS
PIN
POUT
Gain
€ PA
PDOUT
(V)
(V)
(mA)
(dBm)
(dBm)
(dB)
(% )
(W/mm)
0
5 .0
432
2 2 . 0
2 8 .9
6.9
29
0 .7 8
0
5 .0
411
2 3 .0
2 9 .3
6.3
32
0 .8 5
0
5 .0
382
2 4 .0
2 9 .7
5.7
36
0 .9 3
0
5 .0
366
2 5 .0
30.1
5.1
39
1 . 0 2
0
5 .0
351
2 6 .0
3 0 .3
4 .3
38
1.07
0
5 .0
382
2 2 . 0
28.1
6 . 1
26
0 .6 5
0
5 .0
350
2 3 .0
2 8 .4
5 .4
28
0 .6 9
0
5.0
340
2 4 .0
2 8 .7
4 .7
29
0 .7 4
0
5.0
308
2 5 .0
29.1
4.1
32
0.81
0
5.0
290
2 6 .0
2 9 .3
3 .3
31
0 .8 5
0
5.0
303
2 2 . 0
2 7 .9
5.9
30
0 .8 2
0
5.0
272
2 3 .0
2 8 .2
5 .2
34
0 . 8 8
0
5 .0
255
2 4 .0
28.5
4 .5
36
0 .9 4
0
5.0
234
2 5 .0
2 8 .6
3 .6
35
0 .9 7
0
5.0
215
2 6 .0
2 8 .6
2 . 6
30
0 .9 7
Device
A
B
C
77
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
gain and power-added efficiency were 5 .9 dB and 3 6 % , respectively. The
highest output power, gain, and power-added efficiency o f device B were
0 .8 5 W , 6.1 dB, and 3 2 % , respectively. The reduced performance compared
to device A is attributed to the lower drain current densities of device B.
78
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79
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 5
SUBMICRON GATE InGaAs MISFET RESULTS
This chapter describes the results obtained for the submicron gate
length, epitaxial InGaAs MISFETs. Both DC and RF results are presented for
the devices which had plasma deposited silicon dioxide gate insulators. The DC
results include the device l/V characteristics and the result of drain current drift
measurements. The RF results obtained at 18 GHz, 20 GHz, and 2 3 GHz are
also presented. Finally, scatter parameter measurements on the submicron gate
InGaAs MISFETs with silicon dioxide gate insulators are presented.
5.1
InGaAs MISFETs with Silicon Dioxide Gate Insulators
5.1.1 DC Characterization
The l-V characteristics of a submicron gate InGaAs MISFET with a silicon
dioxide gate insulator are shown in Figure 5 .1 . The l-V characteristics were
obtained using a Tektronix model 577 curve tracer. The gate length of the
device was estimated to be 0 .7 pm from optical measurements.
The gate
width of the device was 200 pm. The device source/drain spacing was 5 pm.
The gate voltage range is from 0 V to -1 4 V in -2 V steps. A t a drain-source
bias of 2 .5 V , the drain saturation current was 75 mA, which corresponds to
a drain current density of 375 mA/mm. The device pinchoff voltage was about
-1 4 V .
The devices had typical drain-source breakdown voltages of
6
-
8
V.
The gate-drain and gate-source breakdown voltages were greater than 20 V.
The breakdown properties of the devices were not extensively studied in order
to save devices for subsequent RF testing.
Figure 5 .2 shows the device transconductance per unit gate width as a
80
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 5.1
l-V characteristics of submicron gate InGaAs MISFET
Horizontal: 0 .5 V/div. Vertical: 20 mA/div.
Gate (V GS): -2 V/step.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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-3
-2
-1
0
GATE VOLTAGE (V)
Figure 5 .2
Transconductance vs. gate voltage (VDS = 2.5 V).
82
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function o f gate-source voltage. The results were obtained using a HP4145B
Semiconductor Parametric Analyzer. The drain-source bias was 2 .5 V. The
peak transconductance typically occurred at a gate-source bias of about -2 V.
The maximum device transconductance was typically about 7 0 - 80 mS/mm.
The l-V characteristics displayed in Figure 5.1 were obtained at the
periphery of the sample. However, due to recess etch non-uniformities mainly
cause by photolithography variations, the saturation current densities were
typically greater in the center of the sample. The device saturation current
densities for the 2 0 0 //m gate width devices were as high as about 130 mA,
which corresponds to a current density of 6 5 0 mA/mm.
As the device saturation current density increased above about
4 0 0 m A/m m, the device drain current could not be pinched off completely.
The lack of DC pinch-off has also been reported by other workers, and may be
due to the formation of an inversion layer which screens the undepleted
channel from further gate control [32], [33], [35]. At microwave frequencies,
however, this phenomenon is not expected to degrade device performance.
After packaging devices for RF testing, the l-V characteristics of the
devices were routinely checked using a curve tracer.
Drain-source voltages
from about 2 - 3 V were typically applied to the devices with gate-source
voltages ranging from at least 0 V to -10 V in -2 V steps. The drain-source
knee voltages of the devices were typically less than 1.2 V.
Examples of
results typically obtained for devices with source/drain spacings (LSD) of 5 fjm,
3 //m , and 2 //m are listed in Table 5.1 . The table lists the measured drainsource currents (lDS) as a function of drain-source (VDS) and gate-source (VGS)
voltages.
Again, the results indicate that the maximum transconductance of the
83
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devices typically occurred at gate-source voltages between 0 V and -4 V . From
the data in Table 5 .1 , the 2 //m devices generally appear to have a greater
transconductance, which is expected as the source/drain spacing is decreased.
The maximum average transconductances are in the range of 7 0 - 80 mS/mm.
However, the peak transconductances are probably greater.
Table 5.1
Submicron Gate InGaAs MISFET l-V results after RF packaging
Ids <m A )
l sd
(// m)
(VGS (V))
V DS
(V)
0
- 2
-4
- 6
- 8
-1 4
- 1 0
- 1 2
42
36
33
-
40
32
24
-
-
64
45
42
39
-
-
97
72
57
50
45
42
40
1 24
108
85
6 8
57
52
48
45
2 . 0
116
95
72
58
50
45
-
-
3
2 . 0
128
95
6 8
53
47
43
40
ww
H
2
1.5
128
96
6 8
53
44
39
36
34
I
2
2 . 0
128
1 0 0
71
52
43
37
34
32
J
2
1.5
125
95
6 6
50
42
37
34
32
Device
A
5
2 . 0
106
8 6
64
50
B
5
2 . 0
1 0 0
76
56
C
5
2 . 0
119
8 8
D
3
2 . 0
125
E
3
2 . 0
F
3
G
The results of a drain current drift measurement of an InGaAs MISFET
with a silicon dioxide gate insulator are shown in Figure 5 .3 . Prior to the start
of the measurement, the drain-source and gate-source biases were 2 .0 V and
0 V, respectively, and the drain current w as 8 8 .3 mA.
A t the start of the
measurement, the gate-source bias was switched to -2 .0 V. The initial drain
84
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
r i
i —I
O
iNaaano Nivaa Q3znvwaoN
Figure 5 .3
Drain current drift measurement of InGaAs MISFET with
silicon dioxide gate insulator.
85
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
current was 6 0 .0 mA. The drain current stabilized after about 1 0 0 0 sec. The
drain current variation over a period of 1 0 0 0 0 sec was 5 .8 % . The amount of
drain current drift is less than other reports on InGaAs MiSFETs with silicon
dioxide gate insulators [34], [35], Recently, a drain current drift of 4 % over a
period of 1 0 0 0 0 sec has been reported for 1 fjm gate length InGaAs MISFETs
w ith a silicon/silicon dioxide gate insulator [78].
Reduced drain current drift
may, thus, be possible for submicrometer gate length InGaAs MiSFETs by using
plasma deposited silicon dioxide with a thin silicon interfacial layer as a gate
insulator.
5 .1 .2 RF Characterization
The goal of the output power measurements was to obtain high output
power with a power gain of at least 3 dB, which implies an output power of
about tw o times the input power.
Typically, drain-source and gate-source
biases of 1 V and 0 V , respectively, were initially applied to the device under
test followed by the application of an input power of 12 dBm. The input and
output were then empirically tuned to obtain the highest output power. The
tuning process was then repeated after increasing the drain-source bias, varying
the gate-source bias, and increasing the input power in order to maximize the
output power. When the devices were tuned for high output power at high
drain-source bias, the input power was then varied to obtain the results
reported below.
Figure 5 .4 shows the output power and power-Hxded efficiency as a
function of input power from 9 dBm to 19.5 dBm for a 0 .7 jjm gate length
InGaAs MISFET with a total gate width of 0 .2 mm. The measurements were
performed at a frequency of 18 GHz using a gate-source bias of -3.5 V and a
86
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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POWER-ADDED
60
(%)
24
14
8
10
12
14
16
18
20
INPUT POWER (dBm)
Figure 5 .4
Output power, power-added efficiency vs. input power at
18 GHz (VDS = 6 .0 V, V GS = -3 .5 V).
87
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
drain-source bias o f 6 .0 V. The device saturation current density was about
5 7 0 m A/m m of gate width.
The linear gain was about 8 .5 dB.
An output
power density of 1 .0 4 W /m m was obtained at an input power of 1 9 .5 dBm.
The corresponding gain and power-added efficiency were 3 .7 dB and 4 0 % ,
respectively. This is the highest output power density obtained for an InGaAs
based transistor on InP at K-band.
The highest power-added efficiency
obtained was 4 5 % with a corresponding power gain and output pow er density
of 5 .8 dB and 0 .9 5 W /m m , respectively, at an input power of 17 dBm.
The gain compression curve obtained at 20 GHz using gate-source and
drain-source biases of -2 .5 V and 5.5 V, respectively, is shown in Figure 5 .5 .
The linear gain w as about 6.1 dB. An output power density of 0 .8 8 W /m m
was obtained with a corresponding power gain and power-added efficiency of
3 .0 dB and 3 2 % , respectively, at an input power of 1 9 .5 dBm. The highest
power-added efficiency obtained was 3 5 % with a corresponding power gain
and output power density of 4 .2 dB and 0 .8 3 W /m m , respectively, at an input
power
of
18 dBm.
The output power densities
obtained
are
record
performances for an inGaAs MiSFET at 2 0 GHz.
Output pow er measurements were also performed at a frequency of
2 3 GHz.
The results obtained using gate-source and drain-source biases of
-3 .5 V and 5 .8 V, respectively, are shown in Figure 5 .6 . The linear gain was
about 5.1 dB.
An output power density of 0 .7 4 W /m m was obtained at an
input power of 1 8 .5 dBm. The corresponding gain and power-added efficiency
were 3 .2 dB and 2 7 % , respectively.
The highest power-added efficiency
obtained was 2 8 % with a corresponding power gain and output pow er density
of 3.5 dB and 0.71 W /m m , respectively, at an input power of 18 dBm. This
is the first report of submicrometer gate length InGaAs MiSFETs with high
88
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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IN PU T POWER (dBm)
Figure 5 .5
Output power, power-added efficiency vs. input pow er at
2 0 GHz (VDS = 5.5 V, V GS = -2 .5 V).
89
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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INPUT POWER (dBm)
Figure 5 .6
Output power, power-added efficiency vs. input power at
23 GHz (VDS = 5 .8 V, VQS = -3 .5 V).
90
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
output power performance up to 23 GHz.
Of technological significance is the fact that the drain bias current of
these devices can be decreased and maintained for extended periods with
negative gate bias at a fixed drain bias.
The control of drain bias current
through the use of a negative gate bias allowed the device output power to be
optimized for the record output power densities reported here.
The RF results discussed above for a device with a source/drain spacing
(Lsd) of 5 /;m are listed in Table 5 .2 and Table 5 .3 under device A. Tables 5 .2
and 5 .3
summarize the best output power densities and power-added
efficiencies, respectively, obtained for the submicron gate InGaAs MiSFETs at
frequencies of 18, 20, and 23 GHz. Other results obtained for devices with
5 fjm source/drain spacings are included.
In addition, devices with source/drain spacings of 3 //m and 2 fjm were
also measured in order to determine the effect on device performance. The
highest linear gain obtained for a 3 //m device at 18 GHz was 8 .3 dB. The
highest output power density was 1 .0 2 W /m m . The corresponding gain and
power-added efficiency were 3 .6 dB and 4 0 % , respectively.
The highest
power-added efficiency was 4 5 % with a corresponding output power density
and gain of 0 .9 5 W /m m and 5 .8 dB, respectively.
displayed a linear gain of 6 .4 dB.
A t 2 0 GHz, device D
The highest output power density was
0 .8 9 W /m m with a corresponding gain and power-added efficiency of 3 .0 dB
and 3 2 % , respectively. The highest power-added efficiency was 3 7% . The
corresponding output power density and gain were 0 .8 4 W /m m and 4 .2 dB,
respectively.
At 23 GHz, the highest linear gain was 6.1 dB.
The highest
output power density was 0 .7 7 W /m m . The corresponding gain and poweradded efficiency were 3 .4 dB and 27% , respectively. The highest power-added
91
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 5 .2
Highest output power densities for submicron gate InGaAs
MiSFETs
(V)
(mA)
(dB)
(dBm)
PIN
Gain
(dB)
-3 .5
6 . 0
4 9 .5
8.5
19.5
2 0
-2 .5
5 .5
50.1
6 . 1
23
-3 .5
5 .8
4 8 .9
18
-1
6 . 8
2 0
-3 .0
23
LSD
f
5
18
(Am) (GHz)
A
B
5
ePA
PDOUT
3 .7
40
1 .0 4
19.5
3 .0
32
0 . 8 8
5.1
18.5
3 .2
27
0 .7 4
4 7 .8
6.3
19.5
3 .2
29
0 .9 2
7 .0
4 7 .8
5.1
1 9.0
3 .0
23
0 .7 9
-3 .5
7 .0
4 2 .5
4 .7
18.5
3 .0
23
0 .7 0
V GS
(V)
. 8
V DS
•d s
gl
(%) (W/mm)
C
5
18
-4 .0
6 . 2
5 5 .9
7.9
19.5
3 .9
37
1 .0 9
D
3
18
-3 .5
5 .2
5 6 .5
8.3
19.5
3 .6
40
1 . 0 2
2 0
-3 .5
5 .0
5 3 .6
6 .4
19.5
3 .0
32
0 .8 9
23
-3 .5
5 .0
5 4 .8
6 . 1
18.5
3 .4
27
0 .7 7
18
-3 .5
5 .2
5 5 .8
8 . 1
19.0
3 .6
36
0 .9 2
2 0
-3 .5
5 .2
5 6 .8
6.5
18.5
3 .4
28
0 .7 7
23
-3 .5
5 .2
61.5
5.3
18.5
3 .2
24
0 .7 5
E
3
F
3
18
-3 .5
5 .3
5 5 .9
6.7
19.0
3 .3
31
0 .8 5
G
3
2 0
-3 .5
5 .2
5 6 .4
5.8
18.5
3 .2
27
0 .7 5
H
2
18
-3 .5
4 .5
5 0 .4
7 .4
1 8.5
3 .5
38
0 .7 8
1
2
2 0
-3 .5
4 .8
5 3 .9
6 . 1
18.5
3 .3
31
0 .7 6
J
2
23
-3 .5
4 .5
56.1
5.2
18.0
3 .0
25
0 .6 3
23
-4 .0
5 .0
57.1
5.2
18.5
3.1
25
0 .7 2
92
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 5 .3
Highest power-added efficiencies for submicron gate InGaAs
MiSFETs
f
l sd
(pm) (GHz)
A
B
5
5
V GS
(V)
(V)
(mA)
•ds
Gl
(dB)
(dBm)
V DS
PIN
Gain PDOUT ePA
(dB) (W/mm) (%)
18
-3 .5
6 . 0
51.8
8.5
1 7.0
5.8
0 .9 5
45
2 0
-3 .5
5.5
4 8 .9
6.5
1 7.0
4 .8
0 .7 5
37
23
-3 .5
5.8
4 9 .5
5.1
18 .0
3.5
0.71
28
18
-1
6 . 8
4 9.5
6.3
18 .0
4 .3
0 . 8 6
32
2 0
-3 .0
7 .0
4 8 .4
5.1
18.0
3 .7
0 .7 3
25
23
-3 .5
7 .0
43.1
4 .7
17.5
3 .6
0 .6 4
24
. 8
C
5
18
-4 .0
6 . 2
58 .2
7.9
17.0
5 .9
0 .9 8
40
D
3
18
-3 .5
5.2
59 .0
8 .3
17 .0
5.8
0 .9 5
45
2 0
-3 .5
5 .0
56.5
6 .4
18 .0
4 .2
0 .8 4
37
23
-3 .5
5 .0
5 6.0
6 . 1
18 .0
3 .7
0 .7 5
31
18
-3 .5
5 .2
59.1
8 . 1
1 7.0
5 .4
0 .8 7
40
2 0
-3 .5
5 .2
62.2
6.5
1 7.0
4 .6
0 .7 2
29
23
-3 .5
5.2
63.5
5.3
18 .0
3 .6
0 .7 2
25
E
3
F
3
18
-3 .5
5.3
58 .2
6 .7
18 .0
4 .2
0 .8 2
33
G
3
2 0
-3 .5
5 .2
5 7 .4
5.8
18 .0
3 .6
0 .7 3
28
H
2
18
-3 .5
4 .5
53 .8
7 .4
1 7 .0
4 .9
0 .7 7
43
1
2
2 0
-3 .5
4 .8
57 .0
6 . 1
17.0
4 .5
0.71
33
J
2
23
-3 .5
4 .5
56.1
5 .2
1 8.0
3 .0
0 .6 3
25
23
-4 .0
5.0
59 .2
5.2
18 .0
3 .4
0 .6 9
26
93
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efficiency was 31% with a corresponding output power density and gain of
0 .7 5 W /m m and 3.7 dB, respectively.
The 2 pm devices displayed a linear gain of 7 .4 dB at 18 GHz.
The
highest output power density was 0 .7 8 W /m m . The corresponding gain and
power-added efficiency were 3 .5 dB and 3 8 % , respectively.
The highest
power-added efficiency was 4 3 % w ith a corresponding output power density
and gain of 0 .7 7 W/mm and 4 .9 dB, respectively. At 20 GHz, a linear gain of
6.1 dB w as obtained. The highest output power density was 0 .7 6 W /m m with
a corresponding gain and power-added efficiency of 3 .3 dB and 3 1 % ,
respectively.
The
highest
power-added
efficiency
was
33% .
The
corresponding output power density and gain were 0.71 W /m m and 4 .5 dB,
respectively.
At 23 GHz, the highest linear gain was 5 .2 dB.
The highest
output power density was 0 .7 2 W /m m . The corresponding gain and poweradded efficiency were 3.1 dB and 2 5 % , respectively. The highest power-added
efficiency was 26% with a corresponding output power density and gain of
0 .6 9 W /m m and 3 .4 dB, respectively.
The results indicate that as the device source/drain spacing was
decreased, the device drain-source breakdown voltages decreased as expected.
The best 3 pm device produced output power results comparable to the best
5 pm device at 18 GHz and 20 GHz. Slightly improved output power results
were obtained at 23 GHz. The 3 pm devices also displayed improved linear
gain as the frequency increased compared to the 5 pm devices. In addition,
improved power-added efficiency/output power density combinations were
obtained for the 3 pm devices as the frequency increased. The improvement
is a result of the increased gain obtained at lower drain-source biases for the
3 //m devices.
94
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The 2 fjm devices displayed degraded RF performance compared to the
5 fjm and 3 fjm devices. Results were difficult to obtain for the 2 fjm devices
since the measurements were performed at drain-source biases that caused the
devices to be on the verge of a catastrophic burnout. The 2 pm devices had
linear gains comparable to the 5 pm devices at 20 and 23 GHz.
However,
since high drain-source bias could not be applied to the devices, the output
power tended to saturate at lower values compared to the 5 /jm and 3 fjm
devices.
When performing the output power measurements, the drain-source
current would typically decrease as the input power increased for a fixed drainsorce bias. For example, referring to Figure 5 .4 , the drain-source current at an
input power of 9 dBm was 8 0 .3 mA. At an input power of 17 dBm, the drain
current had decreased to 5 1 .8 mA.
Then, as the output power started to
saturate, the drain current also started to saturate.
At an input power of
19.5 dBm, the drain current was 4 9 .5 mA.
The reduction in further decreases of the drain-source current as the
output power saturates appears to indicate that this is a self-biasing effect.
This effect results from the nonlinearity of the device l-V characteristics at
positive gate-source voltages when the device is operated under large signal
conditions. Large positive RF signal excursions are not as effective in varying
the drain current as large negative signal excursions. Thus, as the RF input
power is increased, the drain bias current decreases on the average.
Finally, the output power stability of these devices was also investigated.
The output power and normalized drain bias current Ods^dso) variation of a
representative device (LSD = 5 fjm) over a 17 hour period is shown in
Figure 5.7 . The measurement was performed at 18 GHz. Prior to the start of
95
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1.01
23
H
Z
LU
DC
E
CQ
■a
CC
3
O
22
CO
<
DC
in
0 .9 9
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oc
20
0 .9 8
3
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o
0 .9 7
DC
O
0 .9 6
0.1
Figure 5 .7
10
100
1000
ELAPSED T IM E (min)
1
Time dependence of output power and drain bias current at
18 GHz.
96
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the measurement, the gate-source and drain-source biases were 0 V . At the
start of the measurement, an RF input power, gate-source bias, and drainsource bias of 1 6 .2 dBm, -4 .0 V, and 5 .0 V , respectively, were applied. The
initial drain bias current was 50.1 mA. The output power and drain bias current
variation were 3 % and 3 .4 % , respectively, over a 17 hour period.
The
variation may be due to insulator interfacial traps and may be further reduced
by using a thin silicon interfacial layer [78], [48], [35].
5 .2
Scatter Parameter Measurements
Scatter parameter measurements were also performed on the submicron
gate InGaAs MiSFETs with plasma deposited silicon dioxide gate insulators.
M ost of the testable devices had already been used in obtaining the results
described above for the output power measurements.
Thus, limited S-
parameter results were obtained due to the low number of remaining devices.
As described earlier in Chapter 3, a thru, reflect, line (TRL) calibration
procedure was implemented in order to properly characterize the devices using
a H P 830 40 modular microcircuit package as the RF test fixture. The TRLCAL
program development required about 4 months to write the main core of the
program.
Some minor changes were required afterwards to correct errors,
which was not surprising considering the size of the final program.
In order to check the accuracy of the TRLCAL program in implementing
the TRL calibration procedure, the fixture was first calibrated using the THRU,
OPEN, and DELAY standards. In order to insure connector repeatability, the
fixture was always connected to the measurement system using an
torque wrench.
8
in.-lb.
The TRL error correction algorithm was then verified by
reinserting and measuring the THRU standard.
Ideally, referring to the
97
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definition of the THRU standard in Eq. 3.5 , the extracted THRU data should
indicate 0 dB insertion loss, 0 ° phase shift, and infinite return loss.
The raw measured S-parameter data obtained for the THRU standard are
shown in Figures 5 .8 - 5 .1 1 .
These four figures show the magnitude and
phase information for the four S-parameters (S11f S12, S21, S22), respectively.
The magnitude data is indicated by the bold line, and the phase data is
indicated by the regular line.
The x-axis displays the frequency span from
10 GHz to 20 GHz. The x-axis is divided into ten regions which corresponds
to a frequency step of 1 GHz per division.
The reference position for the
magnitude and phase data is indicated by the arrow on the y-axis.
The
references for the magnitude and phase data are 0 dB and 0 °, respectively.
The y-axis is divided into ten divisions. Thus, the magnitude scale ranges from
-5 0 dB to 50 dB.
Similarly, the phase scale ranges from -4 5 0 ° to 4 5 0 °.
Finally, it should be noted that the magnitude information is obtained from the
equation, log MAG (dB) = 20 log 1 0 |S |, where S refers to the corresponding
S-parametsr.
The S n and S 2
2
data shown in Figures 5 .8 and 5.11 show return losses
greater than about 15 dB. The S 1 2 and S 2 1 data shown in Figures 5 .9 and
5 .1 0 show insertion losses greater than about 3 dB.
In addition, the phase
shift varies between -1 8 0 ° and 1 8 0 °. Thus, the results obtained for the THRU
standard without error correction are far from ideal.
After performing the TRL calibration, the extracted S-parameter data
obtained for the THRU standard are shown in Figures 5 .1 2 - 5 .1 5 . After the
error correction, the S n and S 2 2 data shown in Figures 5 .1 2 and 5.15 indicate
return losses greater than about 55 dB.
The S 1 2 and S 2 1 data shown in
Figures 5 .1 3 and 5 .1 4 indicate insertion losses less than about 0.1 dB.
98
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In
o
o
GHz
u_
20
LU
DC
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STOP
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cn
CD
X3
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CD
GHz
<
cn
START
10
o
cn
Figure 5 .8
THRU standard - measured
data from 1 0 - 2 0 GHz.
99
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o
o
20
GHz
ULU
ac
STOP
o
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cn
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cn
<
x
a.
CD
■o
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<
2
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START
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Figure 5 .9
THRU standard - measured S 1 2 data from 1 0 - 2 0 GHz.
100
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o
o
GHz
Lt_
UU
20
cr
STOP
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2
START
10
cn
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Figure 5 .1 0
THRU standard - measured S 2 1 data from 1 0 - 2 0 GHz.
101
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o
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20
GHz
UJ
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STOP
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CD
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START
10
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CU
cn
Figure 5.11
THRU standard - measured S 2
2
data from 1 0 - 2 0 GHz.
102
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o
GHz
u_
STOP
20
LU
cn
UJ
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u_
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T3
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START
10
GHz
CVI
cn
Figure 5 . 1 2
THRU standard - extracted S-,-, data from 1 0 - 2 0 GHz.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
GHz
o
o
u
20
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CE
STOP
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CD
■a
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GHz
<
START
10
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Figure 5 .1 3
THRU standard - extracted S 1 2 data from 10 - 20 GHz.
104
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o
GHz
o
20
u_
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CO
STOP
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<
X
CL
CD
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GHz
<
START
10
cn
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cu
cn
Figure 5 . 1 4
THRU standard - extracted S 2 1 data from 1 0 - 2 0 GHz.
105
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GHz
u.
20
LU
STOP
O
LU
cn
o
U_
GHZ
T3
O
OJ
START
10
cn
Figure 5 . 15
THRU standard - extracted S2 2 data from 10 - 20 GHz.
106
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addition, the phase shift is within about ± 0 .6 ° . Thus, the results obtained for
the THRU standard with error correction indicate a high quality calibration.
Similar results were obtained when a SHORT was used as the REFLECT
standard. How ever, a SHORT standard required making tw o additional ribbon
bonds betw een the standard and the package end blocks. On the other hand,
additional ribbon bonds were not necessary when using an OPEN standard.
Thus, an OPEN standard was typically used in order to save time when
performing the TRL calibrations.
Typical S-parameter results obtained for a submicron gate InGaAs
MISFET are shown in Figures 5 .1 6 - 5 .1 9 .
The results were obtained for a
device with a source/drain spacing (LSD) of 3 pm. The gate-source (VGS) and
drain-source (V DS) biases were -3 .5 V and 4 .0 V , respectively.
The S-
parameter data shown in the figures are displayed in a polar format and, thus,
contain magnitude and phase information as a function of frequency.
The
scales for the S 1V S 12, S21, S 2 2 data shown in the figures are 1, 0 .2 5 , 2 .5 ,
and 1 units full scale, respectively.
It should be noted that based upon the
position of the calibration planes, the data inciudes the gate and drain bond
wire parasitics.
The S-parameter measurements were mainly performed in order to
determine the frequency response of the submicron gate InGaAs MiSFETs. A
useful parameter that can be calculated from the S-parameter data is the
transducer power gain (GT), which is defined as the ratio of the power delivered
to a load to the power available from the source (GT = PL/P Avs)- Equations for
the transducer power gain can be determined using signal flow graph analysis
[77].
Based on the definition of scatter parameters (see Equation 3 .1 ), the
107
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GHz
20
STOP
10
GHz
cc
<
o
START
CL
cn
Figure 5 . 1 6
data for submicron gate InGaAs MISFET (10 - 2 0 GHz).
108
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GHz
20
STOP
CD
L.
3
in
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GHZ
tx
<:
o
START
10
Q.
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Figure 5 . 1 7
S 1 2 data for submicron gate InGaAs MISFET { 1 0 - 2 0 GHz).
109
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GHz
20
STOP
CD
U.
in
cu
GHZ
CE
<
_J
o
START
10
CL
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CD
Figure 5 . 1 8
S 2 1 data for submicron gate InGaAs MISFET (10 - 2 0 GHz).
110
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Figure 5. 19
S 2 2 data for submicron gate InGaAs MISFET (10 - 20 GHz).
111
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square of the magnitude of the incident (a) and reflected (b) waves represent
power. Thus, the power delivered to the load (PL) is equal to the difference of
the incident and reflected power as shown in Equation 5. 1.
The power
available from the source (PAVs) 's defined as the power delivered by the source
to a conjugately matched load and is listed in Equation 5 .2 . Thus, Equation 5 .3
for transducer power gain (GT) follows.
The ratio b2 /bs can be determined
using M ason's rule, and the resulting expression for GT is listed in Equation 5 .4 .
Alternative expressions for GT are listed in Equations 5.5 and 5 .6 , and are
derived using Equations 5.7 and 5.8.
In order for a transistor (two-port amplifier) to be unconditionally stable
and not oscillate at a given frequency, the magnitude of the reflection
coefficients r s, r L, r,N/ and r 0UT must all be less than 1. In general, a tw oport netw ork will possibly oscillate when the input port or output port presents
a negative resistance (i.e. if |r,N| > 1 or I f o u t
I >
1 )* If the tw o-port network
is not unconditionally stable, the network is potentially unstable.
In other
words, some combination of passive source and load terminations could
produce input and output impedances with a negative real part.
The four requirements for unconditional stabiity described above follow
from the above considerations and the expressions for r !N and r 0UT listed in
Equations 5 .7 and 5 .8 .
The four conditions can be simplified into tw o
necessary and sufficient conditions for unconditional stability (K >
1
and
| A ] < 1), where the stability factor (K) and determinant of the S-parameter
matrix (A) are listed in Equations 5 .9 and 5 .1 0 .
In order to obtain maximum transducer power gain (GTmax), the transistor
(two-port) input reflection coefficient must be conjugately matched to the
source reflection coefficient (i.e.
r)N = rs*).
In addition, the transistor (two-
112
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port) output reflection coefficient must be conjugately matched to the load
reflection coefficient (i.e.
r0UT = rL*).
The expressions for input reflection
coefficient (r,N) and output reflection coefficient (l"0UT) are listed in Equations
5 .7 and 5 .8 .
Under simultaneously conjugate match conditions, it can be shown that
the maximum transducer power gain (G y ,^ ) is given by Equation 5.11. The
stability factor (K) is listed in Equation 5.9. The expression for GTmax assumes
that the tw o-port netw ork is unconditionally stable (K > 1 and |A | < 1) since
the radical becomes negative for K values less than 1. When K = 1, the value
of GTmax is defined as the maximum stable gain (Gmsg) and is listed in Equation
5.12. The maximum stable gain is a figure of merit that indicates the maximum
possible value for GTmax.
The maximum stable gain can be achieved by
resistively loading the tw o-port network or by using feedback in order to make
the stability factor (K) equal to 1.
If the devices are unilateralized to make S 1 2
=
0, the unilateral
transducer power gain (GTU), which is shown in Equation 5.13, is derived from
the expressions for GT, r iN, and r 0UT listed in Equations 5.5, 5.6, 5.7, and 5.8.
The maximum unilateral transducer power gain (GTUmax} occurs when the
source and load reflection coefficients are equal to the conjugate of
and
S22, respectively (l~s = S-,-,*, r L = S22*), and is listed in Equation 5.14.
Further explanation of the above development is contained in reference [77].
The extracted S-parameter data for the submicron gate InGaAs MISFETs
w ere analyzed using the unconditional stabilty conditions (K > 1 and jA | < 1)
and the equations for K, A, GTmax, Gmsg, and GTUmax. Another program was
actually written using Microsoft QuickBasic 4 .5 in order to perform this
analysis. A typical plot of gain (MSG) as a function of frequency derived from
113
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o
•<T
O
o
ru
S
2
2
^
°
(9P)
Figure 5 .2 0
°
^
~
o
N IV 9
Gain (MSG) vs. frequency for submicron gate InGaAs MISFET
(Lsd = 3 //m ).
114
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FREQUENCY
(GHz)
tn
the S-parameter data is shown in Figure 5 .2 0 . The device had a source/drain
spacing (LSD) of 3 //m . The gate-source (VGS) and drain-source (V DS) biases
w ere -3 .5 V and 4 .0 V, respectively.
The device was conditionally stable (K <
1) over the measured
frequency range from 1 0 - 2 0 GHz. Thus, the maximum stable gain (MSG) at
10 GHz was about 13 dB. At 20 GHz, the maximum stable gain had decreased
to about 1 0 .5 dB.
Similar results were also obtained for a device with a
source/drain spacing of 2 //m under the same bias conditions. However, the
maximum stable gain was slightly greater for the 2 fjm device. The maximum
stable gains were about 14 dB and 11.5 dB at 10 GHz and 2 0 GHz,
respectively.
An estimate of the maximum unilateral transducer power gain cutoff
frequency (fMAx) was obtained from the graph shown in Figure 5 .2 1 .
The
maximum unilateral transducer power gain displayed a roll-off of about
- 6
dB/octave.
By extrapolating to unity gain, an f^Ax
about 50 GHz was
obtained.
115
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o
m
LU
o cr
cvj
u.
o
o
OJ
OJ
OJ
(0P)
Figure 5.21
N IV 9
Gain (GTUmax) vs. frequency for submicron gate InGaAs MISFET
(Lsd = 3 //m ).
116
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(5.1)
Pl = I *2 I 2 -
(5.2 )
PA V S ~
(5.3)
=
(5.4)
7
(5.5)
2
I aG I
r*v s
I *2 I 2 = I b2 | 2 (1 -
I bG I
~
2
\ b s
=
| r L | 2)
\ 2
1 - I rs I 2
= T ^ T I (1 ■ 1
| bs I 2
1 2) (1 "
• r s I 2)
I s 2112 (1 - I rs | 2) n - | rt | 2)
I (1 - S n r jin - s 22rt i - s 21s 12rirs | 2
Gr-J_^l£iLL |S21,2 1- ' r‘ ' 2
1- V s |2
11 - s22r t | 2
(5.6)
G t ■ , 1 - | F s | 2 . I S21 12
1 - '
12
M -^nrsi2
| 1 - r 0UTrL\ 2
(5.7)
T//V - s „
(5.8 )
r O U T = $2 2 + -
5
1 2 5
2
i ri
1 - S22r Z.
5 12S2 lr S
0
r
1 “ s 11r S
(5.9 )
^ _ 1 ~ i S n 1 2 ~ 1 ^22 I 2 + I A I 2
2 | S1 2 S2 1 |
(5 .1 0 )
A = S t iS 2 2 - S 1 2 S 2 1
(5 .1 1 )
Grma*
=- j|^ |
(5 .1 2 )
r
_
(5 .1 3 )
(5 .1 4 )
«M SG “
I * ~ ^K2 -
1I
I s2 i I
|Si2 l
|1 - s u r s \ 2
G TUmax = -------------1 - |5 n
-=•
|
2
|1 - s22r L | 2
I $21 i
1 -
|S
2
2
|
2
117
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118
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER
6
DISCUSSION OF RESULTS AND CONCLUSIONS
6.1
One Micron Gate InGaAs MISFET
Depletion mode InGaAs MISFETs with one micron gate lengths were
fabricated using an ion implanted process. The devices w ere fabricated using
plasma deposited silicon dioxide gate insulators. In addition, plasma deposited
silicon dioxide with a thin silicon interfacial layer was also used as a gate
insulator.
The
MISFETs
were
then
packaged
for
microwave
power
measurements at 9 .7 GHz.
The devices with silicon dioxide gate insulators had saturation current
densities ranging from about 375 mA/mm at the sample periphery to about
7 0 0 - 9 0 0 mA/mm at the sample center. The variation was attributed to the
non-optimized photolithographic process used prior to recess etching.
The
device transconductance was about 30 mS/mm. Although a limited number of
devices was studied, a trend was not observed between transconductance and
saturation current density. The devices had drain-source breakdown voltages
of 4 -
6
V . As the device saturation current density increased, the drain-source
breakdown voltage tended to decrease.
The gate-source and gate-drain
breakdown voltages were greater than 23 V.
The InGaAs MISFETs with silicon dioxide gate insulators did not produce
power gains greater than 3 dB at 9 .7 GHz. The highest gains obtained were
2 .2 - 2 .9 dB. The highest output power density and power-added efficiency
were 0 .8 8 W /m m and 1 6 % , respectively.
In retrospect, it is believed that better results could have been obtained
with these devices if gate-source biases in the range of -2 V to -4 V were used
119
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instead of a 0 V gate bias. This conclusion is based on the results obtained
later with submicron gate devices and the one micron gate device I-V
characteristics shown in Figure 4 .1 . The l-V characteristics indicate that the
maximum transconductance occurs at a gate-source bias around -2 V. Thus,
improved power gain would probably be obtained at this bias. In addition, the
application of negative gate bias would have decreased the device drain-source
current and, thus, allowed possibly greater drain-source bias to be applied with
a corresponding increase in output power.
The InGaAs MISFETs with silicon/silcon dioxide gate insulators had
saturation current densities ranging from about 525 - 7 7 0 mA/m m.
The
variation was attributed to the non-optimized photolithographic process used
prior to recess etching.
The device transconductance was typically about
2 0 mS/mm. The devices had typical drain-source breakdown voltages of about
5 - 7 V. As the device saturation current density increased, the drain-source
breakdown voltage tended to decrease. These devices also had gate-source
and gate-drain breakdown voltages that were greater than 2 3 V.
Dram current drift measurements 'were also performed. Using strictly DC
gate bias voltage (i.e. with no RF signal present), device drain current was held
at approximately 7 0 % of its zero gate bias value over a period of 10 4 sec with
only a 4 % drift. The capability to partially pinch off the device under strictly
DC conditions may provide a solution to the RF burnout problem observed in
these devices when the RF signal is removed while holding the device at high
drain bias voltage.
A t 9 .7 GHz, a 1 mm gate width device produced an output power of
1 .0 7 W with a corresponding power gain and power-added efficiency of 4 .3 dB
and 3 8 % , respectively.
The highest power-added efficiency was 4 0 % at
1 2 0
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0 .9 6 W output power and 4 .8 dB gain. These results w ere obtained using a
gate-source bias of 0 V , which corresponds to the gate-source voltage at which
the maximum transconductance occurs.
Output power stability measurements were also performed. The output
power w as stable to within 1 .2 % over 2 4 hours of continuous operation with
a corresponding drain bias current increase of less than 4 % . This was the first
report o f RF power measurements on an InGaAs MISFET with a silicon/silicon
dioxide gate insulator.
In addition, RF output power greater than 1 W was
demonstrated for the first time for an InGaAs based transistor on InP [78].
The devices displayed an RF burnout phenomenon as the input power
w as decreased with a resulting increase in the drain current.
The burnout
problem limited the dynamic range of the devices. Thus, further improvements
are expected
by optimizing the device structure.
Enhanced frequency
performance is also expected through the use of submicron gate lengths.
6 .2
Submicron Gate InGaAs MISFET
Depletion mode InGaAs MISFETs with 0 .7 pm gate lengths and 0 .2 mm
gate widths were fabricated using an epitaxial process.
The devices were
fabricated using plasma deposited silicon dioxide gate insulators. Submicron
gate lengths were achieved using standard optical photolithography. However,
prior to submicron gate definition, it was necessary to planarize the mesa areas
by e-beam evaporating silicon dioxide and using a liftoff process.
The
submicron gate InGaAs MISFETs also had source/drain contact spacings of
5 pm, 3 pm, and 2 pm in order to investigate the effect on device performance.
The MISFETs were packaged for microwave power measurements at Kband frequencies of 18 GHz, 2 0 GHz, and 23 GHz. The device layout enabled
1 2 1
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multiple MISFETs to be wire bonded in parallel to obtain total gate widths
ranging form 0 .2 mm to 1 mm.
However, due to limitations in the power
measurement system, measurements were restricted to devices with
mm
0 . 2
gate widths. The microwave signal generator was not capable of sourcing a
great enough power to obtain record output power densities for devices with
greater gate widths.
The saturation current densities of the devices varied from about 3 7 5 6 5 0 m A/m m .
The variation was attributed to the non-optimized photolitho­
graphic process used prior to recess etching. There may also have been an
increase in saturation current densities as the device source/drain spacing was
reduced.
Again, the variation was probably caused by non-uniformities
associated with the recess etch lithography.
In addition, a decrease in
saturation drain-source (knee) voltages with a decrease in device source/drain
spacing and, therefore, associated parasitic source and drain resistances, was
not observed. The knee voltages were typically less than 1.2 V.
The devices had typical drain-source breakdown voltages of
6
-
8
V.
Naturally, as the device source/drain contact spacing decreased, the breakdown
voltages decreased. Based on the RF results, upper limits for the drain-source
breakdown voltages for the 3 fjm and 2 fim devices were about 5 V and 4 .5 V,
respectively. The gate-source and gate-drain breakdown voltages were greater
than 20 V.
An extensive investigation of breakdown properties was not
performed in order to conserve devices for subsequent RF testing.
The device transconductance was about 70 - 80 mS/mm. These values
were greater than the transconductances obtained for the one micron gate
length devices. Transconductance is expected to increase with a decrease in
gate length and a decrease in gate insulator thickness.
Based on l-V data
1 2 2
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
obtained after RF packaging, the transconductance tended to increase as the
device source/drain spacing decreased. The device extrinsic transconductance
(gMe) is dependent upon the intrinsic transconductance (gM) and parasitic
source resistance (Rs) as shown in the following equation: gMe =
(1 + Rs gM) [46].
gM/
As the device source/drain spacing in decreased, the
parasitic source (and drain) resistance decreases with an expected increase in
the measured extrinsic transconductance.
The
submicron
gate
InGaAs
microwave
power transistors
with
source/drain spacings of 5 pm, 3 fjm, and 2 pm were power tested at K-band
frequencies.
At 18 GHz, a device with a source/drain spacing of 5 pm
produced an output power density of 1 .0 4 W /m m with a corresponding power
gain and power-added efficiency of 3 .7 dB and 4 0 % , respectively. The linear
gain was 8 .5 dB.
The highest power-added efficiency was 4 5 % with a
corresponding output power density of 0 .9 5 W /m m and power gain of 5 .8 dB.
At
2 0 GHz and 23
GHz,
output power densities of 0 .8 8 W /m m
0 .7 4 W /m m , respectively, were obtained.
and
The linear gains at 20 GHz and
2 3 GHz were 6.1 dB and 5.1 dB, respectively.
The highest power-added
efficiencies obtained at 20 GHz and 2 3 GHz were 3 5 % and 2 8 % , respectively.
A device with a source/drain spacing of 3 pm produced an output power
density of 1 .0 2 W /m m at 18 GHz with a corresponding power gain and poweradded efficiency of 3 .6 dB and 4 0 % , respectively. The linear gain was 8 .3 dB.
The highest power-added efficiency was 4 5 % with a corresponding output
power density of 0 .9 5 W /m m and power gain of 5 .8 dB.
At 20 GHz and
2 3 GHz, output power densities of 0 .8 9 W /m m and 0 .7 7 W /m m , respectively,
were obtained.
The linear gains at 2 0 GHz and 23 GHz were 6 .4 dB and
6.1 dB, respectively. The highest power-added efficiencies obtained at 20 GHz
123
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and 2 3 GHz were 3 7 % and 3 1 % , respectively.
A device with a source/drain spacing of 2 //m produced an output power
density o f 0 .7 8 W /m m at 18 GHz with a corresponding power gain and poweradded efficiency of 3 .5 dB and 3 8 % , respectively. The linear gain was 7 .4 dB.
The highest power-added efficiency was 4 3 % with a corresponding output
power density of 0 .7 7 W /m m and power gain of 4 .9 dB.
Output power
densities of 0 .7 6 W /m m and 0 .7 2 W /m m were obtained at 20 GHz and
23 GHz.
The linear gains at 20 GHz and 23 GHz were 6.1 dB and 5 .2 dB,
respectively. The highest power-added efficiencies obtained at 20 GHz and
23 GHz were 3 3 % and 2 6 % , respectively.
Comparing the results obtained indicates the tradeoff involved as the
device source/drain spacing is decreased.
For example, as the source/drain
spacing is decreased, the transconductance and power gain are expected to
increase. The output power density increases with an increase in power gain
and is expected to increase with an increasing maximum drain current. The
power-added efficiency tends to increase with increases in power gain and
output power density. However, the reduction in device source/drain spacing
also causes a decrease in the drain-source breakdown voltage with a
corresponding reduction in the maximum power gain and output power density.
The maximum drain-source biases used for the RF power measurements
of devices with source/drain spacings of 5 fjm, 3 //m , and 2 fjm were 7 .0 V,
5 .3 V, and 4 .8 V, respectively, when the gate-source bias was -3.5 V. The
devices with source/drain spacings of 3 fjm produced output power densities
comparable to the 5 fjm devices at 18 GHz and 20 GHz with slightly improved
results at 23 GHz. However, improved linear gains with the 3 fjm devices were
clearly evident as the frequency increased compared to the 5 fjm devices. The
124
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improved linear gains were also achieved at lower drain-source bias.
In
addition, improved power-added efficiency/output power density combinations
were obtained for the 3 pm devices as the frequency increased.
The
improvement is a result of the increased gain obtained at lower drain-source
biases for the 3 pm devices.
The RF power performance of the devices with 2 pm source/drain
spacings, however, degraded in comparison to the 5 pm and 3 pm devices. In
comparison to the 5 pm devices at 2 0 GHz and 23 GHz, the linear gains of the
2 pm devices were comparable using substantially lower drain-source biases.
However, due to the lower drain-source breakdown voltages of these devices,
the output power densities tended to saturate at lower values compared to the
5 pm and 3 pm devices.
In general, the devices displayed a good dynamic range. The devices
were typically tested over an input power range from about 10 dBm to 2 0 dBm.
Of technological significance is the fact that the drain bias current of these
devices could be decreased and maintained for extended periods with negative
gate bias at a fixed drain bias. The control of drain bias current through the use
of a negative gate bias allowed the device output power to be optimized for the
record output power densities reported here.
In addition, output power stability measurements were also performed
on the submicron gate InGaAs MISFETs. The output power was demonstrated
to be stable within 3%
over 17
hours of continuous operation.
The
Finally, scatter parameter measurements were also performed on the
submicron gate InGaAs MISFETs over the frequency range of 10 - 20 GHz. A
thru, reflect, line (TRL) calibration procedure was implemented in order to
125
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characterize the devices using a H P 83040 modular microcircuit package as the
RF test fixture. Error correction applied to a THRU standard indicated return
losses greater than 55 dB and insertion losses less than 0.1 dB. The phase
shift was less than
0
. 6 °.
Scatter parameter measurements were performed on devices with
source/drain spacings of 3 fjm and 2 fjm. An analysis of the S-parameter data
indicated that the devices were conditionally stable from 1 0 - 2 0 GHz.
A
maximum stable gain (MSG) of about 13 dB and 1 0 .5 dB at a frequency of
10 GHz and 20 GHz, respectively, was obtained for a 3 fjm device.
Slightly
greater MSG values were obtained for the 2 fjm device. The increase in gain
is attributed to the expected increase in device transconductance as the
source/drain spacing is decreased. The maximum unilateral transducer power
gain cutoff frequency (fMAX) was estimated to be about 50 GHz.
In summary, this is the first report of RF power measurements on InGaAs
MISFETs with submicrometer gate lengths. An output power density greater
than 1 W /m m has been demonstrated for the first tim e for an InGaAs based
transistor on inP at K-band. in addition, the output power densities obtained
are the highest reported for an InGaAs MISFET at K-band [79].
Scatter
parameter measurements were also performed. Maximum stable gains greater
than 1 0.5 dB were obtained over the 10 - 2 0 GHz octave band.
126
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6 .3
Publications and Presentations
This research has resulted in five refereed journal and proceedings
volume publications. In addition, this research material has been presented at
four conferences.
The publications and conference presentations are listed
below.
Publications from Refereed Journals and Proceedings Volumes
[1]
G. A. Johnson, V. J. Kapoor, D. Schmitz, and H. Jurgensen, "InGaAs
Field-Effect Transistors with Submicron Gates for K-Band Applications",
IEEE Trans. Microwave Theory Tech., vol. 4 0 , pp. 4 2 9 -4 3 3 , 199 2.
[2]
G. A. Johnson and V. J. Kapoor, "Submicron Gate Indium Gallium
Arsenide Microwave Power Transistors", 1991 IEEE MTT-S Int.
M icrowave Symp. Digest, Boston, M A, pp. 1 3 1 -1 3 4 .
(This student paper was awarded 1st prize in the symposium.)
[3]
G. A. Johnson, V. J. Kapoor, M. Shokrani, L. J. Messick, R. Nguyen, R.
A. Stall, and M. McKee, "Indium Gallium Arsenide Microwave Power
Transistors", IEEE Trans. Microwave Theory Tech., vol. 3 9 , pp. 106 91 0 7 5 , 1991.
[4]
G. A. Johnson, M. D. Biedenbender, V . J. Kapoor, L. J. Messick, R.
Nguyen, D. Schmitz, and H. Jurgensen, "InGaAs/InP Submicron Gate
M icrow ave Power Transistors for 20 GHz Applications", Proceedings of
the Third International Conference on Indium Phosphide and Related
Materials, IEEE Catalog #91C H 2950-4, pp. 4 2 3 -4 2 6 (1 991 ), Library of
Congress # 9 0 -8 5 2 4 7 .
[5]
G. A. Johnson, V. J. Kapoor, L. J. Messick, R. Nguyen, R. A. Stall, and
M . McKee, "High Frequency Transistors on M OCVD Grown InGaAs/InP",
Proceedings of the Second International Conference on Indium Phosphide
and Related Materials, IEEE Catalog # 9 0 C H 2 8 5 9 -7 , pp. 3 0 4 -3 0 7 (1990),
Library of Congress #9 0 -8 0 5 9 6 .
Conference Presentations
[6 ]
G. A. Johnson, M. D. Biedenbender, V . J. Kapoor, L. J. Messick, R.
Nguyen, D. Schmitz, and H. Jurgensen, "InGaAs/InP Submicron Gate
M icrowave Power Transistors for 20 GHz Applications", Third Int'l Conf.
on Indium Phosphide and Related Materials, Cardiff, Wales, UK, April 8 11, 1 99 1.
[7]
G. A. Johnson and V. J. Kapoor, "Microwave Power indium Gallium
Arsenide Transistors", 1931 March Meeting of the American Physical
Society, Cincinnati, Ohio, March 18-22, 19 9 1 , Bulletin of the American
Physical Society, vol. 36, no. 3, pp. 9 8 5 , 199 1.
127
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[8 ]
G. A. Johnson, V . J. Kapoor, L. J. Messick, R. Nguyen, R. A. Stall, and
M . McKee, "High Frequency Transistors on M O C VD Grown InGaAs/InP",
Second International Conference on Indium Phosphide and Related
Materials, Denver, Colorado, April 2 3 -2 5 , 1 9 9 0 .
[9]
G. A. Johnson and V. J. Kapoor, "Dielectric Films for InGaAs Power
Transistors", 176nd Meeting of the Electrochemical Society, Hollywood,
Florida, October 15-20, 198 9, J. Electrochem. Soc., vol. 136, no. 8 , pp.
385c, 1989.
Additional Publications
The following publications contain subject matters related to this
dissertation research, and are also based on results obtained at the University
of Cincinnati.
[10]
G. A. Johnson and V. J. Kapoor, "Plasma-Deposited Germanium Nitride
Gate Insulators for Indium Phosphide Metal-lnsulator-SemiconductorFieldEffect Transistors", J. Appl. Phys., vol. 69, pp. 3 6 1 6 -3 6 2 2 , 1991.
[11] V . J. Kapoor, M . D. Biedenbender, and G. A. Johnson, "Encapsulated
Rapid Thermal Annealing and Thin Gate Dielectrics for InP MISFETs", InP
Microwave/M illim eter W ave Technology Workshop, NOSC, San Diego,
California, January 2 5 -2 6 , 1989.
[12]
G. A. Johnson and V. J. Kapoor, "Plasma Deposited Germanium Nitride
on InP Compound Semiconductors", Dielectric Films on Compound
Semiconductors. Journal of the Electrochemical Society, Pennington, NJ,
8 8 - 1 5 . pp. 5 7 -7 0 (1988).
[13]
G. A. Johnson, V. J. Kapoor, and P. G. Young, "Plasma Deposited
Germanium Nitride on Indium Phosphide", 172nd Meeting of the
Electrochemical Society, Honolulu, Hawaii, October 18-23, 1987, J.
Electrochem. Soc., vol. 134, no. 8 B, pp. 4 3 0 c , 19 8 7 .
[14] G. J. Valeo, M. D. Biedenbender, G. A. Johnson, V. J. Kapoor, and W .
D. Williams, "Encapsulated Annealing of InP Substrates", Dielectric Films
on Compound Semiconductors. Proceeedings of the Electrochemical
Society, Pennington, NJ, 86-3. pp. 2 0 9 -2 1 9 (1 9 8 6 ).
128
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6 .4
Suggestions for Future Research
Possible improvements in the one micron gate ion-implanted InGaAs
MISFET power performance may be accomplished by reducing the device
saturation current densities in order to increase the drain-source breakdown
voltages. Reduced saturation current densities can be obtained by increasing
the recess etch times.
In addition, the channel implant schedules could be
altered to obtain reduced theoretical carrier concentrations in the range of about
1 0 1 7 - 3 x 1 0 1 7 cm ' 3 based on the results obtained w ith the submicron gate
epitaxial devices.
The devices could also be further characterized using
negative gate-source bias when performing the RF power measurements.
These improvements are expected to increase the dynamic range of the
devices.
Possible improvements in the fabrication of the submicron gate epitaxial
InGaAs MISFETs are described in the following. Improved yield and reduced
feature size of the submicron gates could be accomplished using x-ray or ebeam lithography. In addition, larger samples could be processed to possibly
reduce edge effects.
Ohmic contact formation could be more thoroughly investigated. W hen
wire bonding the drain pads of the devices during RF packaging, occasional
adhesion problems were encountered. The entire drain pad would lift with the
rising bonding tool. This adhesion problem with the ohmic contacts was not
encountered with the one micron gate ion-implanted devices.
Thus, it is
speculated that the problem may be associated with the substrate material.
Different substrates from two different vendors w ere used during the ionimplanted and epitaxial device fabrication.
129
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The recess etch photolithography could also be improved in order to
decrease the variation in saturation current densities for these devices. This
has recently been achieved by using a different resist (Shipley 1417 instead of
1421) and reducing the UV lamp intensity during exposure [80].
The gate and drain pad separation in the device layout could also be
increased in order to facilitate wire bonding. Different device topologies that
use air bridges and via holes could also be investigated in order to possilbly
improve device performance.
Finally, submicron gate devices with a silicon dioxide gate insulator and
a thin silicon interfacial layer could be investigated to possibly improve the
device drain current drift and output power stablity.
However, improved
control over the silicon interfacial layer thickness is needed.
The silicon
interfacial layer tends to decrease the device transconductance and, therefore,
power gain.
E-beam evaporation of a thin silicon layer prior to plasma
deposition of silicon dioxide may provide a better control over the interfacial
layer thickness.
Recent research on MBE silicon/photo-CVD silicon dioxide structures
using in-situ x-ray photoelectron spectroscopy (XPS) indicates that the silicon
prevents the oxidation of Ga sites and, therefore, provides improved drain
current drift [35]. However, in this research, it is speculated that the plasma
deposited silicon interfacial layer acts as a type of getter during the post­
deposition annealing [81].
Additional measurements that could be performed on the submicron gate
epitaxial InGaAs MISFETs include the following. Large-signal scatter parameter
or reflection coefficient measurements could be performed in order to better
characterize the devices under large-signal conditions. Load-pull measurements
130
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could also provide output power contour information as a function of device
load impedance [77], [82].
Finally, an equivalent circuit could be developed
based on scatter parameter measurements and techniques to extract device
parasitics such as bond wire inductances [83].
131
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132
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