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RF modeling of flip -chip interconnects and MEMS in microwave /mm -wave circuits

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RF M od elin g of Flip-chip Interconnects and
M EM S in M icrow ave/M M -w ave Circuits
by
Zhiping Feng
B.S.. Peking University. Beijing. P. R. China. 1987
M.S.. Bowling Green Stare University. OH. 1994
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A thesis submitted to the
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Faculty of the Graduate School of the
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University of Colorado in partial fulfillment
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of the requirements for the degree of
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Doctor of Philosophy
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Department of Electrical and Computer Engineering
2000
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
UMI Number: 9995717
Copyright 2001 by
Feng, Zhiping
All rights reserved.
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unauthorized copying under Title 17, United States Code.
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P.O. Box 1346
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
This thesis entitled:
RF Modeling of Flip-chip Interconnects and MEMS in Micro\vave/MM-\vave
Circuits
written by Zhiping Feng
has been approved for the Department of Electrical and Computer Engineering
K. C. Gupta
Y. C. Lee
^
2.QQQ
The final copy of this thesis has been examined by the signatories, and we find
that both the content and the form meet acceptable presentation standards of
scholarly work in the above mentioned discipline.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
iii
Feng. Zhiping (Ph.D.. Electrical Engineering)
RF Modeling of Flip-chip Interconnects and MEMS in Microwave/MM-wave C ir­
cuits
Thesis directed by Professor K. C. Gupta
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This thesis presents measurement and electromagnetic simulation-based mod-
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eling of (i) high-frequency flip-chip interconnects and (i i ) micro-electro-mechanicalsystem iMEMS) capacitors and switches. In the first part, the objective is to char­
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acterize flip-chip interconnects with and without underfill based on experimental
measurement and electromagnetic iE.M) simulation, and to investigate the effect
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of flip-chip joints on RF performances of copianar waveguide I CPU') circuits. In
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the second part, the objective is to design and characterize RF MEMS tunable
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capacitors and switches, and thereby develop design guidelines and methodology
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for RF MEMS devices.
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measurement, has been developed for frequencies up to 4(1 GHz. For the specific
An RF model of CPW flip-chip joints, based on EM simulation and RF
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design considered, the inductance due to the flip-chip joint is about 0.012 nH. Also,
effects of the underfill epoxy on flip-chip assemblies have been studied. Additional
loss due to underfill is 0.22 dB/'mm and additional transmission phase delay is
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13 deg/mm at 40 GHz.
This additional phase delay can be compensated by
redesigning dimensions of transmission lines in the RF circuit.
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CPW compatible high-Q series- and shunt-mounted variable capacitors us-
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ing MEMS (with thermal actuation) have been designed, characterized and measured. Lumped-element models have been developed for these MEMS capacitors.
Effects of actuators and thickness of the gold layer on the MEMS plate have been
analyzed to improve RF performances of these MEMS variable capacitors. De-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
sign guidelines for RF MEMS variable capacitors have been developed based on
characterizations of these capacitors. For the shunt-mounted capacitor design,
the measured value of the shunt resistance (R). which is series with the tunable
capacitance, is 0.15 Q. the measured capacitance is 0.272 pF. the Q-factor is ap­
proximately 390 at 10 GHz. the self-resonance frequency is beyond 40 GHz. and
the simulated maximum to minimum capacitance ratio is about 5:1. For rlip spHp^mounted capacitor design, the measured R is 4.2 Q. the measured capacitance is
0.331 pF with 0 volt bias voltage, the Q-factor is approximately 110 at 1 GHz.
the measured tuning ratio is about 2.66:1 with the actuation voltage varied from
0 to 2.5 volts, and the self-resonance frequency is 14 GHz when bias voltage is 2.5
volts. For RF MEMS multiway switches, a design method has been developed.
Lsing this method. 2-port MEMS switches have been designed and optimized.
The insertion loss is approximately 0.1 dB and the isolation is 22 dB at 14 GHz.
Initial designs of 3-port and 4-port MEMS switches have been carried out and
characterized.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D edication
To my mother. Xurong Wang, my father. Zhen Feng, my husband. Chongchan
and our son. Jason Jiasheng.
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Acknowledgements
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I would like to thank many people who helped continuously to make the
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dissertation come true. I am especially thankful for Dr. K. C. Gupta and Dr. Y. C.
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Lee. the dissertation advisors, for their endless encouragement, patient guidance
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and invaluable advice. Also. I appreciate Dr. Don DeGroot's help on measurement
and calibration. I wish to thank Wenge Zhang. Bingzhi Su and Huantong Zhang,
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for their jovful collaborations during mv graduate studies. GaAs chips, which
were used in the flip-chip research, were donated by Hughes Aircraft Company,
and I am thankful to Drs.
Tom Midford. C.P. Wen and Mike Cole of Hughes
for several interactions. Besides. I am very grateful to Dr. Melinda Picket-.May
for serving on my committee during her very busy schedule. Special thanks to
Dr. Richard C. Booton. Jr. my committee, for showing such kind attention to my
thesis, even during his hospital stay.
Finally. I want to express my gratitude from the bottom of my heart to my
husband. Dr. Chongchang Mao. for his love and encouragement. The dissertation
would not have been possible without his understanding and endurance. Also. I
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thank my mom. Xurong Wang, and my dad. Zhen Feng, for their encouragement
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and unselfish help. Specially. I will give the dissertation to my lovely son. Jason
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Jiasheng Mao. for the happiness he brings to the world, for his bright eyes and
crystal heart, and for being always patient for not having enough time to stay
w ith me.
J
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Contents
C hapter
1
Introduction
1
1.1
RF modeling and characterization of flip-chip interconnects . . . .
1
1.1.1
Flip-chip interconnects in RF packaging
...........................
1
1.1.2
Flip-chip assembly and wire b o n d in g .................................
4
MEMS in RF circuits and systems...................................................
9
1.2.1
M E M S ...................................................................................
9
1.2.2
Electromechanical a c tu a tio n ................................................
12
RF modeling and characterization of RF M E M S ...........................
20
1.3.1
MEMS tunable c a p a c ito rs ...................................................
20
1.3.2
MEMS multiway switches
...................................................
21
...............................................................
23
1.2
1.3
1.4
2
Organization of the thesis
RF Modeling of Flip-chip Interconnects
26
2.1
Experimental characterization of flip-chip interconnects...............
26
2.1.1
Test circuits and assem blies................................................
27
2.1.2
Measurement results and m o d e lin g ....................................
31
2.2
2.3
Electromagnetic simulation of flip-chip interconnects
..................
42
2.2.1
Numerical results and analysis.............................................
42
2.2.2
Effect of bump height............................................................
47
R em arks.............................................................................................
50
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3
4
Underfill Effects on Flip-chip Interconnects
3.1
Test circuits and measurement.........................................................
3.2
Measurement results and characterization.......................................
3.2.1
Measurement results of flip-chip assemblies with underfill .
3.2.2
Losses...................................................................................
3.2.3
Change in e,* of CPW line on G aA s.......................
3.2.4
Phase shift due to underfill e p o x y .......................................
3.3
Modeling based on measured results................................................
3.4
Rem arks............................................................................................
Design and Characterization of RF Series-mounted Tunable Capacitor U
ing MEMS
4.1
Design and fabrication of series-mounted tunable capacitors . . .
4.1.1 Electro-thermal actuation and mechanical design
4.1.2
.............
RF d e s ig n .............................................................................
4.1.3 F a b ric a tio n ..........................................................................
4.2
Results and analysis
.......................................................................
4.2.1 Measured results and m o d e lin g ..........................................
4.2.2 Simulation of tunable MEMS capacitors and analysis . . .
4.3
Optimization of series-mounted c a p a c ito rs ....................................
4.3.1
Gap in C P W '.......................................................................
4.3.2
Connect pad and b e a m s ......................................................
4.3.3
Q-factor and gold layer th ic k n e s s .......................................
4.3.4
Effect of actuators on RF perform ance..............................
4.3.5 Improved series-mounted MEMS tunable capacitor design
4.4
MEMS tunable bandpass filte r .........................................................
4.4.1
Bandpass filter design
..........................................................
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IX
5
4.4.2 One-pole MEMS tunable bandpass f i l t e r ............................
122
4.5 Rem arks..............................................................................................
125
Shunt-mounted MEMS Tunable Capacitor Design
127
5.1 Design of shunted-mounted capacitors.........................................
127
5.1.1 RF d e s ig n .........................................................................
127
5.1.2 Mechanical design and fabrication...................................
129
5.2 Results and RF modeling for thefirst design
................................
5.2.1 Measured results and characterization.............................
129
129
5.2.2 Simulation results and RF modeling for the first design . .
136
5.3 RF and mechanical improvements....................................................
139
5.3.1 Electro-thermal actuators and sizes of MEMS plates . . . .
139
5.3.2 Actuator effects in shunt-mounted capacitors................
5.3.3
5.4
Q-factor and thickness of gold la y e r....................................
Measured results and analysis of the seconddesign
5.5 Discussions
5.5.1
140
153
.......................
153
......................................................................................
15$
Shunt-mounted ca p a c ito rs ..............................................
15S
5.5.2 Comparison of series-mounted and shunt-mounted capacitors 15$
6
RF MEMS Multiway Switches
161
6.1 Design of MEMS s w itc h e s ...........................................................
6.1.1
161
General design considerations.........................................
161
6.1.2
Mechanical design and fabrication.......................................
163
6.1.3
RF design method and 2-port MEMS switch design . . . .
165
6.2 Design examples of multiway-MEMS s w itc h e s ..........................
6.2.1
Design and characterization of 3-port (SPDT) switches
6.2.2
RF design and characterization of 4-port sw itche s........
178
. .
179
6.3 Rem arks..............................................................................................
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178
180
7
Summary and Future Works
7.1
7.2
Summary
.........................................................
7.1.1
Flip-chip interconnects........................
7.1.2
RF M E M S .............................................
7.1.3
Design procedure and role of modeling
Suggestions for future w o rk s ..........................
7.2.1
Flip-chip interconnects........................
7.2.2
RF M E M S ............................................
Bibliography
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Tables
Table
1.1 The percent change of Z q of CPU’ on GaAs with and without met­
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allization on surface of the substrate under chip.............................
7
Comparison of microactuation m ethods..........................................
15
1.3 Comparison of tunable capacitors using different tuning methods .
20
1.2
2.1 Comparison of Zu and t Tl. of CPW’ on GaAs with and without
alumina substrate vicinity effect at 10 G H z ....................................
.'39
2.2 Loss of single flip-chip joints with different bump heights................
4S
3.1 Comparison of the measured and calculated frequencies for mini­
mum reflection in the flip-chip assemblies with the underfill epoxy
58
3.2 Values of various elements in the model of flip-chip interconnects
with and without epoxy
..................................................................
GO
4.1 Summary of selected M U M P’s process parameters...........................
68
4.2 Values of elements in lumped-element model based on simulation
results for the series-mounted MEMS capacitor with different airgaps. 83
4.3 Dimensions and number of beams in different simulation structures.
85
4.4 Resistance and Q-factor of multilayer metal with different thickness
of the gold layer..................................................................................
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95
4.5
Parameters of the improved series-mounted capacitors for different
bias voltages........................................................................................
4.6
Values of the elements for 1-section bandpass filters........................
4.7
Values of the elements in the equivalent --circuit of gap capacitors
in CPW...............................................................................................
4.8
Values of the elements in the equivalent --Hrcuir of interdigita!
capacitors in CPW .............................................................................
5.1
Values of the capacitance for the shunt-mounted MEMS capacitor
with different airgaps.........................................................................
G.l
Dimension of MEMS for 2-port switches
.......................................
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F igures
Figure
1.1 Multi-level RF packaging...................................................................
3
1.2 Wire-bonding (a) and flip-chip bonding lb) technologies................
16
1.3 Structure of the flip-chip assembly with CPW on chip and mi­
crostrip line tiix substrate. Vias are needed to connect the ground
planes...................................................................................................
17
1.4 Approximate field distributions for flip-chip assemblies using CPW
(a) and inicrostrip line (b).................................................................
IS
1.5 Anisotropic etching in bulk micromachining of crystalline silicon .
19
l.G The basic fabrication process of surface micromachining: (a) de­
posit an isolation layer: (b) deposit and pattern a sacrificial layer:
(c) deposit and pattern a structural layer : (d) selectively etch the
sacrificial layer to release the polysilicon cantilever (as an example).
19
2.1 Photo of the GaAs test chips with bumps. The smaller chip is used
in this thesis as chip No. 1 and the longer chip is called chip No. 2.
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27
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2.2
Layout of calibration set and circuits for mounting chips on alumina
substrate. Three chip-sets (1.2.3) are shown at the first line. Two
chip-sets (4.5) are shown at the right end of the second line. Only
two chip-sets (1 and 4) were used in this thesis. The calibration
set. which consists of a thru line, four longer delay lines and one
offset short, are the rest of components in this lavout.....................
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2.3
A photograph of flip-chip assemblies with chip Xo. 1 and chip Xo. 2. 30
2.4
The measured
of line 1 in the calibration set compared with
the response from the simulation by using MDS.......................
31
2.5 The measured S;! for the flip-chip assembly with chip Xo. 1 (1.10G
mm long) and the simulated response from modeling..............
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30
34
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2.0 The measured 5-ji for the flip-chip assembly with chip Xo. 1 and
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the simulated response from modeling.......................................
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2.7 Phases of S2\ for the flip-chip assembly with chip Xo. 1.................
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2.S The measured values of 5n for the flip-chip assembly with chip Xo.
34
2 (a length of 4.700 mm) and the response from modeling.....
35
30
2.9 Measured S2i values of the flip-chip assembly for chip Xo.2 (4.700
mm long] and the response from simulations...........................
30
2.10 Phases of S2 1 for the flip-chip assembly with chip Xo. 2.........
37
2.11 Lumped-element model of one single flip-chip interconnecton CPW
with three bumps on each end for signal and ground planes.
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...
37
2.12 Modeling of flip-chip assemblies on CPW. For modeling purposes.
the assembly is separated into three parts: CPW on mother board
substrate. CPW on GaAs chip with substrate effect and flip-chip
interconnects................................................................................
38
2.13 Flow chart of the modeling method for CPW flip-chip interconnects. 41
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XV
2.14 Structure of the flip-chip interconnect simulated on HFSS. (a) Top
View and (b) front view....................................................................
45
2.15 Comparison of the measured and simulated values of Sn for the
flip-chip assembly with chip Xo. 2. which length is 4.700 mm. x
marks are the simulation results from HFSS. the solid line is the
measured result....................................................
46
2.16 Comparison of the measured and simulated values of S>i for the
flip-chip assembly with chip Xo. 2. which length is 4.700 mm. x
marks are the simulation results from HFSS. the solid line is the
measured result..................................................................................
46
2.17 Structure of one single flip-chip interconnect used in HFSS simula­
tion. d is the bump height, which is equal to the air gap between
the chip and the mother board.........................................................
47
2.IS Simulated values of 5u for a single flip-chip interconnect on CPW
as a function of frequency for different bump heights. Bump height
is changed from 62 to 240 qm...........................................................
49
2.19 Simulated values of 5 ji for a single flip-chip interconnect on CPW
as a function of frequency for different bump heights. Bump height
is changed from 62 to 240 ^m ...........................................................
3.1
A photograph of flip-chip assemblies with underfill epoxy.
small box at the up left corner is chip Xo.
49
The
1. which has been
flip-chip bonded on the alumina substrate. The black region un­
derneath the chip is the epoxy material. The large long box is chip
Xo. 2. A section of CPW line, which can be seen on each side of
these chips, is the probe pads............................................................
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53
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3.2
Comparison of the measured Sn of the flip-chip assembly with and
without the underfill epoxy for chip Xo. 1.......................................
3.3
Comparison of the measured S2: of the flip-chip assembly with and
without the underfill epoxy for chip Xo. 1.......................................
3.4
54
Comparison of the measured 5 n of the flip-chip assembly with and
without the underfill epoxy for chip Xo. 2.......................................
3.5
54
55
Comparison of the measured S21 of the flip-chip assembly with and
without the underfill epoxy for chip Xo. 2.......................................
55
3.6 Comparison of losses of the flip-chip assembly (chip Xo. 1) with
and without the underfill epoxy........................................................
3.7 Comparison of losses
61
of the flip-chip assembly (chip Xo. 2) with
and without the underfill epoxy........................................................
61
3.S Multilayer structures used in HFSS to compute the effective di­
electric constants of CPW’ with and without underfill epoxy in the
flip-chip assemblies.............................................................................
3.9
62
Comparison of the measured and calculated phase shifts due to the
underfill epoxy for the flip-chip assembly with chip Xo. 1 ............
63
3.10 Comparison of the measured and calculated phase shifts due to the
underfill epoxy for the flip-chip assembly with chip Xo. 2..............
63
3.11 Comparison of the measured 5 U and the response from the model
of the flip-chip assembly for chip Xo. 1 with underfill epoxy. . . .
64
3.12 Comparison of the measured S2 1 and the response from the model
of the flip-chip assembly for chip Xo. 1 with underfill epoxy. . . .
4.1 Layer layout of surface MEMS fabricated by MCXC.......................
64
67
4.2 One design of electro-thermal actuators. The longer arm at the
center is the hot arm and the two shorter arms are the cold arms.
r
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71
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4.3
(a) Temperature distributions along the hot arm and cold arm in an
actuator, (b) Deformation of the actuator after adding the currency
through i t ............................................................................................
72
4.4
A typical MEMS design for the series-mounted capacitor...............
72
4.5
Simplified series-mounted MEMS tunable capacitor, (a) Longitu­
dinal side view, ib ) top view..............................................................
4.6
Photograph of a series-mounted capacitor assembly after removing
silicon..................................................................................................
4.7
7S
Comparison of the measured and modeling S-pararneters of the
series-mounted MEMS tunable capacitors........................................
4.9
7S
Movement of the free end of a electro-thermal actuator as a function
of applied voltage................................................................................
4.S
73
79
Lumped-element model of MEMS tunable series-mounted capaci­
tors and its relationship to Y-parameters.........................................
79
4.1U Comparison of the modeling response and the measured IinO T ) of
the series-mounted MEMS capacitor.................................................
SO
4.11 Capacitance. C. of the series-mounted capacitor as a function of
frequency.............................................................................................
SO
4.12 Comparison of the modeling results and the measured real(loi) of
the series-mounted MEMS capacitor.................................................
SI
4.13 Q-factor of the series-mounted MEMS capacitor as a function of
frequency.............................................................................................
SI
4.14 Simulation results (Sn and Sox) of the MEMS series-mounted tun­
able capacitor for different airgaps...................................................
82
4.15 Simulated S-parameters of the series-mounted MEMS capacitor
with different widths of the gap in the center strip of CPW. The
gap is changed from 40
to 100 gm. (a) Son (b) Sn ..................
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88
xviii
4.16 Series capacitances of the series-mounted MEMS capacitor for dif­
ferent widths of gap in the center strip of CPW. The gap is changed
from 40 nm to 100 /im .......................................................................
89
4.17 Structure used for simulation of beam effect in HP-momentum. (a)
Top view, (b) side view with substrate layers..................................
90
4.IS Simulation results for different number of beams. Solid line with
—
(case l i is for 21 beams (each beam 6 /mi wide), solid line
with xxxx (case 3) is for three beams (each beam 10 /an wide), and
solid line (case 2) is for five beams (each beam 10 /mi wide), which
is chosen for the new design...............................................................
91
4.19 A series-mounted capacitor without actuators, which is used for
simulating the pad size effect in HP-momentum. L is the length of
the connecting pad. It is open air under the alumina substrate.
.
92
4.20 Simulation results for the series-mounted capacitor with different
connecting pad lengths. Length of pud. L. is 200. 100 and 50 /mi
when keeping other parameters same................................................
92
4.21 Skin depth of gold as a function of frequency...................................
90
4.22 Transmission line model for the
s u rfa c e
resistance of the multilayer
metal, dg is the thickness of the gold layer, d is the thickness of
polysilicon layer, and Z is the impedance of the air. The real part
of Z m gives the surface resistance......................................................
97
4.23 Surface impedance of the multilayer metal with different thickness
of gold layer versus different frequencies. The solid line with mark
x is for 40 GHz. and the solid line with mark A is for 30 GHz. the
solid line with mark square is for 20 GHz. the solid line is for 1 GHz.
98
4.24 Structure of the series-mounted capacitors with strips for simula­
tion.......................................................................................................
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103
xLx
4.25 Simulated S-parameters of MEMS series-mounted capacitors with
actuators, which is simplified as a strip. The width of strips is 10
^m and 5 /j,m. Su of capacitor without actuators is also included
for comparison.....................................................................................
104
4.26 Comparison of capacitances for series-mounted capacitors with and
without strips......................................................................................
105
4.27 Structures of series-mounted capacitors with strips that are isolated
from ground (a) and areleft open (b).................................................
106
4.2S S-parameters of the series-mounted capacitor with strips but no
grounding (no via is added and via is isolated from the ground
plane). S-parameter of series-mounted capacitor without actuator
also is included forcomparison............................................................
107
4.29 Lumped-element model of the MEMS series-mounted capacitor in­
cluding the effect of actuators. La and Ra are the inductance and
resistance due to actuators,
iai Model with inductance La. (hi
model with inductance La and resistance Ra...................................
108
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4.30 Two series rr-circuits and the equivalent rr-circuit
........................
109
4.31 Structure of the series-mounted capacitor with strips that are par­
tially grounded....................................................................................
109
4.32 S-parameters of the series-mounted capacitor with strips that are
I
partially grounded...............................................................................
110
4.33 Comparison of S-parameters of the series-mounted capacitor with
1.5 ^m thick polysilicon strips and w ith 0.5 /rm thick gold strips.
W idth of the strip is 5 jim .................................................................
4.34 Photo of the improved series-mountedc a p a c ito r............................
Ill
113
4.35 Measured the change of the airgap as a function of voltage using
Zygo.....................................................................................................
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115
XX
4.36 Measured S-parameters of the improved series-mounted capacitor
for different bias voltages, (a) 5u- (b) S^. Solid line with x is for
0 volt bias, solid line is for 2.5 volts bias, and solid line with -r is
.
for '2.5 volts bias............................................................................. .
116
4.37 -5 2 i of the series-mounted capacitor, which calculated from mea­
sured S-parameters. (a) Imaginary parr of
(hi real narr of }\.
Solid line with x is for 0 volt bias, solid line is for 2.5 volts bias.
and solid line with — is for 2.5 volts bias..................................
117
4.38 Capacitance of the series-mounted capacitor, which calculated from
measured S-parameters. Solid line with x is for 0 volt bias, solid
line is for 2.5 volts bias, and solid line with — is for 2.5 volts
bias. 1IS
4.39 Comparison of capacitances of the series-mounted capacitor, which
calculated from measured and simulated S-parameters. The airgap
is 2.27 /mi with 0 volt bias.........................................................
119
4.40 Q-factor of the improved series-mounted capacitor for different bias
voltages. Bold solid line with x is for 0 volt bias, solid line is 2.25
volts bias, dot line is for 2.5 voits bias.......................................
119
4.41 Substrate layout of a MEMS tunable bandpass filter with biascircuit. 120
4.42 Simulation results of one-section bandpass filter. Solid line is the
result obtained from network simulator (MDS) using the design val­
ues. Dot line is the result from the EM simulation (HP-Momentum)
with the layout using the interdigital capacitors.......................
123
4.43 The interdigitai capacitor in CPW. a = 30 gm. b = 55 gm. W
= 200 gtm. and L changes from 220 ^m to 570 gm for different
capacitances.................................................................................
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124
xxi
4.44 Simulation results of the one pole bandpass filter.Center frequency
of the tunable bandpass filter changes from 10.6 to 13.6 GHz as the
airgap in the MEMS capacitor changes from 0.5 /zm. 1 /zm. 2 /zm.
3 /zm to 4 /zm (from left to r i g h t ) ..........................................
124
5.1 Simplified structure of the MEMS shunt-mounted capacitor. Lon­
gitudinal side view iupi and top view idown).........................
132
5.2 Lumped-elemenr model of the shunt-mounted capacitor and the re­
lationship between the model and Z-parameters without consider­
ing actuator effect (a), and a simplified model of the shunt-mounted
capacitor without considering the effect of actuators ib )................
132
5.3 Photograph of one shunt-mounted capacitor assembly after remov­
ing silicon for the first design............................................................
133
5.4 Measured 5 ;; and ST of the first design for the shunt-mounted
MEMS tunable capacitor with a fixed 4 /zm airgap.........................
134
5.5 Capacitance from measured S-parameters of the shunt-mounted
MEMS capacitor for the first desisn.................................................
5.6
134
R: calculated from measured S-parameters of the shunt-mounted
MEMS tunable capacitor for the first design....................................
135
5.7 Simulated S-parameters of the shunt-mounted MEMS tunable ca­
137
o\
pacitor for different airgaps (4. 2. 1. 0.5 /zm)...................................
.8 The capacitance values of the shunt-mounted MEMS tunable ca­
pacitor for different airgaps (4. 2. 1. 0.5 /zm) from simulated Sparameters...........................................................................................
138
5.9 The pattern of the gold layer on the MEMS plate for the MEMS
capacitor design with itching holes....................................................
144
5.10 The uniform gold layer layout on the MEMS plate w ith itching holes. 144
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xxii
5.11 Lumped-element model of the shunt-mounted capacitor with effect
of actuators.........................................................................................
144
5.12 Structures of the shunt-mounted capacitor with simplified actua­
tors. (a) with two strips and (b) with four strips.............................
5.13 Simulated
145
S-parameters of the shunt-mounted capacitorwith two
strips and without actuators. W idth of strips is taken as 20. 10. 5
/zm. Length of strips is 200 /zm. Airgap = 1 /zm.............................
5.14 Simulated
146
capacitance of theshunt-mounted capacitorwith two
strips and without actuators. W idth of strips is taken as 20. 10. 5
/zm. Length of strips is 200 /zm. Airgap = 1 /zm. Solid line with x
is for the capacitance of MEMS capacitor without actuators. . . .
147
5.15 S-parameters of the shunt-mounted capacitor with two strips at
higher frequencies, (a) W idth of strips is 10 /zm. ib) width of strips
is 20 /zm. Length of strips is 200 /zm. Airgap is 1 /zm....................
14S
5.16 Simulated capacitance of the shunt-mounted capacitor with two
strips at higher frequencies, ia) Width of strips is 10 /zm and ibi
width of strips is 20 /zm. Length of strips is 200 /zm. Airgap is 1
/zm........................................................................................................
5.17 Simulated
149
capacitance of the shunt-mounted capacitorwith two
strips and without actuators. Width of strips is 20 /zm. Length of
strips is taken as 200 and 0 /zm. Airgap = 1 /zm.............................
5.18 Simulated
150
capacitance of the shunt-mounted capacitorwith two
strips and four strips. W idth of strips is taken as 20 /zm for 2-strip
case and 10 /zm for 4-strip case. Length of strips is 200 /zm. Airgap
= 1 /zm................................................................................................
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150
xxiii
5.19 Structure of the shunt-mounted capacitor w ith two actuators for
HP-Momentum simulation, in which cold arms are ground and hot
arm is isolated from ground plane.....................................................
151
5.20 Comparison of simulated S-parameters of the shunt-mounted ca­
pacitor with two strips and two actuators, in which cold arms are
ground and the hot arm is isolated from ground pianos Width of
strips is taken as 20 /mi for 2-strip case and 10 ^m for the cold and
hot arm in 2-actuator case. Length of strips is 200 /mi. Airgap =
1 / m l ..................................................................................................................................
151
5.21 Layout of a complete actuator used in HP-momentum simulation,
la™ is the length of hot arm and cold arms and is chosen as 200
//m. Lf is the length of flexure and is 55 /mi. the width of the hot
arm at center is 20 /mi. and the width of cold arms is 5 /mi. . . .
152
5.22 The photo of the second version of the shunt-mounted MEMS ca­
pacitor.................................................................................................
154
5.23 Current distribution on the top MEMS plate from EM simulation. 150
5.24 Measured S-parameters of the shunt-mounted capacitor for the imi
i
proved design. Solid line with xx is Su . solid line is for S- > . . .
156
5.25 Measured capacitance of the shunt-mounted capacitor for improved
design...................................................................................................
157
5.26 Measured resistance of the shunt-mounted capacitor for improved
design...................................................................................................
157
5.27 Comparison of the capacitance values of the series- and shunt-
6.1
mounted capacitors.............................................................................
160
Layout of the initial design of MEMS for 8-port switches..............
163
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XXIV
6.2
Schematic drawing of the 2-port MEMS switch, (a) Top view, (b)
side view. Metal-to-metal contact in part 2 of the switch is assumed. 170
6.3
Schematic layout of one cantilever beam in the multiway switch. .
6.4
Microscope photo of the zip cantilever beam for different bias voltages. 171
6.5
Flow chart of the design method for multiway-.MEMS switches.
6.6
Lumped-element model of 2-port MEMS
6.7
Different substrate layouts for 2-port MEMS sw itches.................
G.S
Simulated S-parameters for the 2-port switch with different sub­
. 172
173
s w itc h e s
174
strate la y o u ts ...................................................................................
6.9
170
175
S-parametcrs for the improved 2-port MEMS switch from the lumpedelement model with Con and C . / / ..................................................
176
6.10 Photo of an example of 2-port MEMS switch assemblies with bias
177
circuits................................................................................................
6.11 Layout of the T-junction switch using 3-beams MEMS............
1S1
6.12 Layout of rhe Y-junction switch using 3-beams MEMS............
1S1
6.13 Lumped-element model of 3-port MEMS switches..........................
1S2
6.14 Simulation results of T-junction MEMS switches. Airgap is 3 pm
and the diameter of the center pad of MEMS is 370 pm. Dot lines
are insertion loss (S^i for ON state) (a) and isolation (S21 for OFF
state) (b) between port 1 and port 2. Solid lines are insertion loss
(S31 for OX state) (a) and isolation (5 3 1 for OFF state) (b) between
port 1 and port 3...............................................................................
183
6.15 Simulated S-parameters of the Y-junction MEMS switch. Airgap
is 3 pm................................................................................................
184
6.16 Layout of a 4-port MEMS switch.....................................................
184
6.17 Lumped-element model of the 4-port MEMS switch......................
185
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XXV
6.IS Insertion loss (a) and isolation (b) for off-state between port 1 and
2. and between port 1 and port 3 (dotted line) for the 4-port MEMS
switch...................................................................................................
186
7.1
Flow chart for RF part of MEMS device design..............................
191
7.2
Conceptual flow chart for design of RF MEMS................................
192
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Chapter 1
Introduction
This chapter describes roles of flip-chip interconnects and RF MEMS in
microwave electronics and brings out needs for modeling and characterization of
flip-chip interconnections and RF MEMS based on electromagnetic simulation
and/or experimental measurement.
1.1
RF m odeling and characterization of flip-chip interconnects
1.1.1
Flip-chip interconnects in RF packaging
The major trend in the RF and microwave packaging industry today is to
make products lighter, smaller, thinner, shorter and faster, while at the same rime
making them more friendly, functional, powerful, reliable and less expensive T [10]. Some of examples are cellular phones, wireless phones, pagers, etc. As the
trend toward miniature and compact products continues, one of the key technolo­
gies that are helping to make these product design goals possible is packaging
technology. Packaging focuses on assembling chips together on one substrate in
one housing efficiently and reliably. A chip needs to connect with other chips in
a circuit through an input/output (I/O ) system of interconnects. Furthermore,
the chip and its embedded circuitry are delicate, requiring a packaging to earn-,
support and protect it. Thus, major mechanical functions of a packaging [1]-[10]
are (1) support the chip and protect it from hostile environments, and (2) remove
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the heat generated by the circuits or devices (chips). RF functions of the packag­
ing and interconnections are (1) distribute the signals onto and off the chips, and
(2) provide a path for the electrical current to power the circuits on the chip. For
frequencies higher than 1 GHz. the packaging can strongly affect the RF perfor­
mance of the circuit. RF packages are parts of circuits and not just housings or
connecting wires found in low frequency electronics. The travel of elecrromagneric
waves in and out of a RF packaging is determined by its geometrical configuration.
Packaging parasitic reactance and loss parameters become increasingly important
as frequency increases. RF microwave design rules need to be developed to reduce
losses, crosstalks and resonances due to the packaging.
There are a number of levels in RF packaging isee Figure 1.1). The first
level packaging consists of attachment of the chip to a substrate in either single
chip packages or multichip modules. The secotid level packaging is mounting the
chip (on the substrate) to a printed circuit board (PCB). The third level packaging
is housing the PCB with other boards in another housing. Because of the recent
trend towards Hip bare chips on board (COB) technology, the distinction between
the first and second levels of RF packaging is blurring. Packaging configuration
is dependent upon the particular RF system and packaging technology available,
however, in all of these packaging arrangements, a connection between the chip
and substrate is necessary. The first level packaging assembly technologies include
wire bonding, tape automated bonding (TAB), and flip-chip soldering or bonding.
Wire bonding is the earliest and widely used technology today. However, current
upsurge in wireless communication applications of RF and microwave circuits has
created a need for higher circuit density and reliability in hybrid planar circuits at
these frequencies. Because of automated assembly, compact modules, minimum
interconnect length, compatibility with CPW and efficient thermal management,
flip-chip assembly technolog}- is attracting more and more attentions [12]-[19].
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I
Chip
Level 1
Substrate
i i
\1 h
Level 2
Housing
ik
Level 3
Board
Figure 1.1: Multi-level RF packaging
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4
1.1.2
Flip-chip assem bly and wire bonding
Wire bonding is a widely-used method of connecting a chip to motherboard
in the electronic or RF packaging (see Figure 1.2 (a)) [7j. A typical bonding wire
is around 300 gm in length and 25 gm in diameter. This length includes an extra
margin for (1) the height difference between the chip and the substrate. (2) chip
cuntact pads’ 'locations, and i3) an extra iength needed to avoid a mechanicai
failure during thermal cycling. The inductance of the bonding wire may degrade
the electrical performance of the chip and can be calculated using the following
formula [11’:
,
-1
3
I , = o/i/n( — i — - )
( 1. 1 )
where I is the length of the wire in inches. D is the diameter of the wire in
inches, and L, is in nanohenries. L'sing the equation, the inductance of the typical
bonding wire with a length of 300 /mi and diameter of 25 /mi is about 0.143 nH.
An interconnect with a return loss better than -10 dB requires bonding wires not
longer than 0.033A0 [14[. which is only 100 //in at 94 GHz. Furthermore, bonding
pads add significant parasitic reactances to the circuit on chip and can degrade the
overall performance of the assembly at higher frequencies. In addition, when the
circuit has more I/O ports, the conventional wire-bonding method is increasingly
difficult and time comsuming because pads for wire bonding must be near the
edge of the chip and bonding is carried out one wire at a time in the typical wirebonding technology. A large number of bond wires may cause reliability problems
[12]-[14j.
In order to eliminate the problems associated with wire bonding, a flip-chip
packaging technique has been used [15]-[18]. [22]. [26]. In this method, bonding
wires are replaced with metal bumps plated on chip(see Figure 1.2 (b)). These
metal bumps are used to attach the chip to the substrate. The bump height (30
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fim to 70 /jm) is short compared to the length of the bonding wire, the bump
diameter (40 /im to 150 /im ) is larger than that of the bonding wire, and the
bonding pad (typically 40
to 70 //ml for a flip-chip assembly can be smaller
than that in a wire-bonding assembly, (typically 100 x 100 /j.m). Therefore, a
considerable improvement of electrical interconnect properties is achieved. From
Figure 1.2. we notice that flip-chip bonding needs less space than wire bonding
because of the improved alignment of bonding pads on the substrate to those on
chip. Because connect pads in a flip-chip assembly are not needed to be close to
the edge of the chip, the substrate layout is more flexible and more I/O ports
are possible. In the bonding process, metal humps are aligned with respect to
metal (gold) pads on the substrate and all joints are made simultaneously. Fur­
thermore. chips are not needed to be thinned in the flip-chip packaging. Hence,
compared to wire bonding, the flip-chip approach provides advantages of lower
parasitic reactance, more reliability, shorter assembly time, lower cost and more
I/O ports for same size of chip 13 - 14'. 17 - IS . However, there still are three
main issues that need to be investigated in order to use flip-chip technology for
RF and microwave applications including ' l 1 the effect of the substrate on RF
performance. (2) modeling and characterization of flip-chip interconnects and (3)
the effect of underfill on RF performance.
Substrate Effect: After a chip (with RF and microwave circuits) is flipped on
a substrate, the substrate is close to the surface of the chip (a typical gap is 30 -70
fj.m) and EM fields on the chip interact with the substrate. Because the dielectric
constant of the substrate is larger than that of air. the effective dielectric constant
of transmission lines on the chip is increased and the characteristic impedance is
reduced. Also, transmission lines or circuits on the substrate affect RF perfor­
mance of the chip. These parasitic effects in a flip-chip assembly may be called
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substrate effects [21]. These effects can be reduced by carefully choosing types
of transmission lines or redesigning the dimensions of transmission lines. Impor­
tant parameters affecting the substrate effects are [21]: (1) types of transmission
lines in the chip (MMIC). (2) dimensions of transmission lines. (3) airgap (bump
height) between the surface of the chip and that of the substrate. (4) material
and thickness of the substrate and /-5) presence or absence- of tar ground plant- or
other metallization on the surface of the substrate under the chip.
Generally, microstrip line and coplanar waveguide I C'PW) are common trans­
mission lines in RF and microwave circuits. Because the ground conductor and
the signal strip line are not on the same plane in the microstrip line configuration,
vias are needed to connect the ground plane on the chip and that on the package
substrate (see Figure 1.3). In a coplanar waveguide (CPW) transmission line, two
ground planes and the signal strip are all in one plane and there is no metalliza­
tion on the backside of the chip. Thus, no via is necessary for CPW flip-chip
package. Furthermore, it is possible to design a CPW line ifor a desired char­
acteristic impedance I with narrower gaps and strip width. These narrow CPW
lines have smaller radiation at discontinuities and lower dispersion compared with
the conventional microstrip line [23]. Figure 1.4 shows the approximate electricfield distributions of a microstrip line and a CPW line in a flip-chip assembly.
At higher RF. microwave and mm-wave frequencies, the fields in CPW are well
confined within the gaps on the CPW. therefore, there is a smaller substrate ef­
fect in flip-chip assemblies with CPW lines. Moreover. CPW circuits experience
less coupling between the different lines on the same metallization layer [23]. It
has been reported [21] that when a GaAs chip is flip-chip bonded on an alumina
substrate, the percent change (decrease) in the line impedance of a microstrip line
on a GaAs chip is larger than 59c for the flipped case compared to the unflipped
case when the width of the strip is 254 fim and the airgaps are 100 gm. But the
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I
Table 1.1: The percent change of Zo of CPW on GaAs with and without metal­
lization on surface of the substrate under chip.
I
;
!
Bump height ([im) j 10 j 20
30 i 40 j
7c change of Z0 without | 2.4 j 1.3 j 0.5 | 0.2 j
lA. change of Z0 with I IS ! 7 ' 3.5 I 2 1
percent change of the impedance for CPV» uii tue GnA? chip u iih the wiulu ui
14.2 pm and gaps of 56 pm is less than 0.3 M up to 50 GHz compared to the
unflipped case for the same airgap. Therefore. CPW circuits are more compatible
with flip-chip bonding technology compared with microstrip line circuits. In this
thesis, the CPW line hits been chosen as transmission lines on chips and also on
substrates.
Metallization on the surface of the substrate under chip interacts with the
EM fields on the chip and affects RF performances of the chip circuit. Heinrich et
al .28: compared the variation of CPW transmission-line parameters as a function
of the bump height with and without metallization on the surface of the mother
board under chip. For W —2G (ground-to-ground spacing' in CPW equal to 50
pm on GaAs 'see Figure 1.4 (a!), the impedance chances are shown in Table
1.1. When a metallized substrate surface is used, a taller bump is required. Of
course, these effects can be considered in the circuit design (the circuit modified
to accommodate these effects). But this circuit redesign would require special
modeling tools. Meanwhile, if the backside of the substrate is metallized as well,
or is placed on the bottom plane of a packaging, which is metallized, a parasitic
parallel-plate mode gets excited in the substrate. This mode can couple to the
CPW mode at any discontinuity, such as. flip chip interconnects. When this hap­
pens. the RF performance of the flip-chip packaging become worse and cross-talk
between two ports in the flip-chip assembly increases [28]. Therefore, from RF
and microwave considerations, the non-metallization of the substrate under chips
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8
has clear advantages.
Characterization of Flip-chip Interconnects: RF characterization of flip-chip
interconnects offers a guideline for RF circuit and packaging designs that use these
interconnects. A lumped-element model is convenient for RF designers to include
thp narL'sti*** AfF!pr*r in nirrmir ■^irTiui 2 .tionc Sovcriii th.oorot icul studies in R.F characterization of flip-chip interconnects have been published ’12\ 424- 25 . In 1994.
Sakai et al.
1S_ reported a shunt capacitor model for flip-chip interconnects in
microstrip line based on measurement results for a very short bump height (2-3
fim). Two years later. Ghouz :25; published a "-circuit model based on simula­
tion results for cube bumps without experimental verification. In the same year,
a raised coplanar waveguide model was reported by Krems 14-. The CPW’ model
is symmetric, but the flip-chip joint is not symmetric. Therefore, an accurate
lumped-element model is necessary to describe the RF effect of a flip-chip joint.
Also a verification of the model for flip-chip assemblies with cylinder bumps is
needed.
Underfill: Generally, a flip-chip assembly requires an underfill to reduce the
stress on joints during thermal excursions, increase the fatigue life of joints and
protect the assembly from the environment [34]-[38]. However, the underfill ma­
terial affects the electrical performance of the assembly due to different values of
its dielectric constant (er ) and dissipation factor (tand) compared to those of the
air. The related study reported earlier is of the effect of Sealgard (er =2.8) and
Globtop (er =3.14) on the performance of an LXA in the frequency range from 5
to 15 GHz [39]. More studies on underfill effect are required to evaluate the use
of underfill in flip-chip assemblies for microwave and mm-wave.
One of the goals in the flip-chip part of this thesis is to develop and verify a
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lumped-element --circuit model of flip-chip interconnects by using measurements
at microwave and mm-wave frequencies. The other goal is to characterize effects of
underfill encapsulant on RF performance, based on measurement results of CPW
flip-chip assemblies with and without underfill.
1.2
1.2.1
M EM S in R F circuits and system s
MEMS
Microelectrumechanicai system (MEMS) is defined as a class of mechanical
actuators, sensors and other electro-mechanical devices that are microscopic in
scale and are typically fabricated by the techniques used in the manufacture of in­
tegrated circuits and semiconductor components S3'. These devices may either be
independent structures or be integrated into other micro electronic circuit devices.
Micro-mechanical devices and systems are inherently smaller, lighter and faster
than their macroscopic counterparts, and usually more precise. There are several
advantages of MEMS compared to their macroscopic counterparts: (1) smaller size
and lighter weight, t 2 > lower power consummation and higher isolation. t3* po­
tentially compatibility with conventional monolithic microwave integrated circuit
(MMIC) fabrication techniques and (4) increased functionality(command,.'control,
display and sensing) for a given area of the chip. Compared to semiconductor
counterparts, advantages of MEMS devices are (1) tunability. high linearity and
low intermodulation distortion (IM D). (2) lower loss/higher Q-factor. especially
at high frequencies.
Based on their fabrication processes, there are two kinds of MEMS technolo­
gies: bulk micromachining and surface micromachining. Both bulk and surface
micromachining are silicon micromachining. Bulk micromachining of silicon uses
wet and dry etching techniques in conjunction with etch masks and etch stops to
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10
sculpt micromechanical devices from the silicon substrate. The process of bulk
micromachining is based on the fact that anisotropic enchants of silicon such as
KOH (potassiumhydroxide and water) and EDP (ethylenediamine. pyrocatechol
and water), and hydrazine-water solution, etch along the (100) and (110) crystal
planes but are practically stopped along the (111) planes •S3). ( I l l ) planes are
erchpd ar a slower rare than all other crystallcgraphic planes due to the combi­
nation of highest area density of atoms, one dangling bond (as opposed to two
dangling bonds for (100) surface atoms) and geometric screening effects I threedimensional distribution of atoms in the lattice). Since the (111) planes make a
34.74 degree angle with the (100) planes, significant under-etching may occur in
convex corners or where there are curved edges at etch mask openings. In these
cases, under-etching continues until it reaches the (111) planes. Silicon dioxide,
silicon nitride and some metallic thin films such as chromium and gold, provide
good etch masks for typical anisotropic enchants. Figure 1.3 shows two simple ex­
amples of the bulk micromachining process for (100) and (110) silicon substrates.
Surface micromachining relies on releasing specific structural parts of a de­
vice embedded in layers of a sacrificial material during the fabrication process.
The sacrificial material is dissolved in a chemical enchant that does not attack
the structural parts. In polysilicon surface micromachining, which is widely used,
polycrystalline silicon is the structural material. Phosphorus-doped silicon oxide
is used for sacrificial layers . which can be etched using hydrofluoric acid. Sili­
con nitride is used as theisolation layer. The basic fabrication process for surface
MEMS is shown in Figure 1.6. Because surface micromachining is more versatile
than bulk micromachining, it can be used to fabricate diaphragms and also more
complex mechanisms such as gear-trains. turbines, linkages and micromotors [82].
Microfabrication and micromachining have their origins in efforts beginning
in the mid-1960s through early 1970s. The first micromachined sensor was fabri­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
11
cated at Stanford University [83]. In the mid-1980s, fabrication tools have been
set for a wide array of geometry and structures with silicon by the University of
California at Berkeley and the University of Wisconsin. Some commercial appli­
cations are worth mentioning here j84j. [85]. Texas Instruments’ digital mirror
devices are arrayed micrometer-scale mirrors used to produce high-definition pro1
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deployment in automobile crashes are being manufactured by Analog Devices and
Lucas Nova Sensor. Fluid transistors using mierochannel technology have been
developed by Redwood Microsystems for integrated fluidic circuitry, with func­
tionality similar to electronic circuitry devices. Honeywell has developed infrared
cameras comprising infrared sensitive detectors manufactured using MEMS tech­
nology. Lawrence Livermore National Laboratory has developed weapons-arming
accelerometers, heat dissipaters and thermopmeumatic pumps.
Recently extensive research has been carried out to explore more new areas
for MEMS applications. RF MEMS is one novel MEMS application in RF and
microwave fields. RF MEMS represents a major system impact opportunity for
RF communications and radars, which make possible highly compact, efficient,
reliable and affordable RF systems. RF devices that can be benefited by MEMS
are low-loss microswitches, tunable capacitors, microinductors, microresonarors.
miniature filters, etc 46|-[57j. MEMS is lightweight and small size, and overcomes
limitations inherent in conventional electronics approaches, enables performance
with low power consumption, enables circuit integration efficiency and reduces
assembly complexity through batch fabrication. RF MEMS devices have lower
loss/cost (high Q). high isolation and higher linearity comparing to the semicon­
ductor devices. However, there are still several special challenges in RF MEMS
device design and characterization. These include: (1) isolation of RF signals
from actuators. (2) limitations on RF design flexibility and RF performance due
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12
to MEMS structures. (3) difficulties in RF simulation because of MEMS mate­
rial characteristics and dimensions and (4) high RF loss of low resistivity silicon,
which is the substrate material for surface machined MEMS.
In this thesis, the focus is on designs and characterizations of high-Q MEMS
tunable capacitors and multiway switches which enable many important circuit
fiitirrinnc
"T'Ko orrointjJ^Io p£3r^*GT'TT1liliC? Of RF circuits fabricated in a traditional
IC technology has been impeded by the low Q-facrors of on-chip varacrors 5S\
A low-noise RF YCO requires a resonant device with a high Q-factor. since the
phase noise of an oscillator is proportional to l / Qj - where Q t is the overall Qfactor of the resonator 59;. High dynamic range filters also require a high Q-factor
resonator since the dynamic range of the filter is proportional to Q2r GOb HighQ MEMS tunable capacitors can replace low-Q varacrors to improve all of these
RF performances. MEMS switches can benefit RF phase-shifting technology in a
number of ways including use as a time-delay phase shifter. Multiway MEMS RF
switches reported in this thesis have not only all of the advantages of MEMS RF
switches bur also are very compact, requiring much less board space1.
1.2.2
Electrom echanical actuation
Actuation is a critical part of most MEMS devices. The implementation
of these MEMS devices exploit a variety of actuation mechanisms: electrostatic,
electromagnetic, magnetic, piezoelectric, shape memory alloy (SMA). electrical
thermal system, and electrochemical, etc. These actuators can move pieces of
metal or polysilicon linearly, rotationally and 2D surface scanning depending on
the mechanical structures of actuators.
Electrostatic actuators are popular in RF MEMS applications due to their
simplicity. In electrostatic actuators, generally, there is a pair of metal plates, like
a parallel plate capacitor; one is fixed and the other one is flexible and can be
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13
moved. When a voltage is applied between the two plates, an attractive electro­
static force is generated between the two plates, which causes the movable plate
to move closer to the fixed plate. An electrostatic curved electrode actuator with
a deflection of 25 ^m and an actuation voltage of 200 volts has been reported
by Legtenberg [66]. To generate a larger force but w ith reduced voltage, a larger
change of canacirance wirh disranvp i*5 required This had !pd to the development
of electrostatic comb drives. An electrostatic comb drive for vertical actuation lias
been designed 61 for a displacement of up to 2 fin\ with an actuation voltage of
10 volts. Another kind of electrostatic actuator is the wobble motor. The rotor is
a circular disk which can rotate around its axis 66 .
Magnetic actuators have been fabricated by electroplating an extra layer of
a weakly ferromagnetic material such as nickel 'S7\ A ferromagnetic microacruator wirh rorsional-polysilicon flexures has been developed. A 45" deflection out
of the surface plane of the wafer is generated when a current of 500 rnA flows
through a ten-turn coil integrated in this microactuator S7 . Problems with mag­
netic actuators are that 3D coils are very difficult to microfabricate and the choice
of magnetic materials is limited to those that can be easily micromachined, so the
material of the magnet is nor always optimum SS\
Piezoelectric effect can also be used for actuation of MEMS. A piezoelectric
actuator consists of a layer of piezoelectric material (generally ZnO is used), which
is deposited on a beam. When a voltage is applied across the beam, the strpss
generated in the piezoelectric material causes the beam to bend. A piezoelectric
cantilever microactuator has been published by DeYoe [65]. The deflection at con­
stant voltage 2 V is about 0.6 n m. Other piezoelectric materials for piezoelectric
microactuators are lead zirconate titanate (PZT) and polyvinylidene fluoride. O f
these materials. PZT has the largest piezoelectric coefficient.
A ll of the three actuators mentioned above are electromagnetic microactu­
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14
ators. The other type of actuation employs thermal effects including bimetallic,
thermopneumatic and shape memory alloy (SMA). Bimetallic microactuators uti­
lize the mismatch of coefficients of thermal expansion (CTE) between two layers
of different materials to generate force or motion. Materials with the same CTE
but different cross-sections and or at different temperatures can be used for the
thermal actuation as well. Pan has reported a clcciro-ih^nnal avtuutur using
two arms in the same material but in different lengths 62'. The deflection was
about 5 /an for 10 volts actuation voltage. In
thermopneumatic actuation, the
volume expansion of a heated fluid in a sealed cavity is used as a source of mi­
croactuation to deflect a thin silicon diaphragm. Shape memory alloys (SMAs) are
metals that have shape-recovery characteristics 63'. If these alloys are plastically
deformed at one temperature, they will completely recover their original shapes
when raised to higher temperature. In recovering their shapes, these alloys can
produce displacements or forces, or both. A particular SMA material for microac­
tuator applications is Xi-Ti. an alloy of titanium and nickel 64". In all of the
thermal actuators, the heated materials have to cool down to return actuators to
original positions. For this purpose the heat has to be dissipated into surrounding
structures, which may affect the speed of such an actuator.
Different microactuation methods can be compared by the amount of energy.
\V. available per unit volume. Other factors such as speed, power consumption,
material issue, size, integration and application, must also be considered when
comparing different microactuation methods. In general, thermal microactuators
have a slow response time (on the order of tens of milliseconds) and high power
consumption (on the order of tens of milliwatts). Electrostatic microactuators, on
the other hand, can be much faster (with a response time measured in microsecond
10-6 to 10_I second) and consume far less power [S3]. But electrostatic actua­
tors need higher actuation voltages. From the view of RF applications, these
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15
Table 1.2: Comparison of microactuation methods
Electrostatic
Piezoelectric
M agnetic
M ism atch of
A ctu atio n I or V
! D e fle c tio n ^ m )
Special process?
10-200 V
2V
500 m.A
3-10 V
!
2-25
I
0.6
| 45 degree
!
3-6
Xone
Maybe
Yes
Xone
Special m aterial?
Xone
Piezoelectric
Ferrom agnetic
Xone
therm al expansions
i
Therm o pn eum atic
SMA
32 d e c re e
Yes
20
\ [a rh p
Fluid
SMA
actuation mechanisms mentioned above are compared in Table 1.2. We notice
that electrostatic actuation and electro-thermal actuation are more suitable for
RF applications because no special materials are required. These actuators can
be integrated with MMICs as well. So far. all published RF ME.MSs have used
electrostatic actuators because of simplicity, low power consumption and higher
speed. In this thesis, the electrostatic actuation method has been chosen for the
MEMS switch design, in which the switching speed is a very important factor.
However, in electrostatic actuator, high actuation voltage is recpiired. commonly
from 30 volts to 30 volts. Thermal actuation, on the other hand, needs low DC
driving voltage (2-5 volts,;. It has great potential for RF applications at handsets
in wireless communications, which require low DC operation voltage. Chapter 4
and 5 of this thesis describe RF applications of MEMS with thermal actuators in
MEMS tunable capacitors.
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M other hoard
-----------M o th e r hoard
*hi
Figure 1.2: Wire-bonding (a) and flip-chip bonding (b) technologies
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17
CPNV on jh ip
Via to iirnumi plane
M icrostnp line or. Nub-ant:
Figure 1.3: Structure of the flip-chip assembly with CPW on chip and microstrip
line on substrate. Yias are needed to connect the ground planes.
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18
M .itS e r N i ix o \u r» « tn tr
▼
C F A .-n .m r
-- --------’
----- t - j -------------------------------^r w
t
%
^
,
L*mr
M other N ia rc »urwtfate
*
> * x
^
*
V iL -P 'M n r .in g i>r. L f . i r
C"
Figure 1.4: Approximate field distributions for flip-chip assemblies using CPW
(a) and microstrip line (b).
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Masking material
Silicon substrate
Masking matenal
_/
S ilic o n ->unstnte
tb i
Figure 1.6: Anisotropic etching in bulk rnicronuichining of crystalline silicon
Silicon nitride isiation layer]
Silicon substrate
Sacnficiai layen Silicon oxide
S tructural iay en P o ly silico n i
S acn ficiai layer e t c h e d -------
d
Figure 1.6: The basic fabrication process of surface micromachining: (a) deposit
an isolation layer: (b) deposit and pattern a sacrificial layer: (c) deposit and
pattern a structural layer : (d) selectively etch the sacrificial layer to release the
polysilicon cantilever (as an example).
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20
Table 1.3: Comparison of tunable capacitors using different tuning methods
i
i
j
Possibility of
MEMS
Possible
1
Trimmer
Difficult
i
Large
i
j
i
Semiconductor ‘
Yes
; integrate w ith M M IC
Size
Tuning
!
1.3
Loss ■Q -fa c to r
:
Small
L in e a r/m a n u a lly
. L in ea r/e lectric ally
; Low loss High Q
i Low loss High Q
Small
i
N o n lin e ar electrically
;
High loss.’Low Q
RF m odeling and characterization of RF M EM S
j
j
i|
|
I
I
1.3.1
M EM S tunable capacitors
So far. commercial available1tunable capacitors are trimming capacitors and
semiconductor devices ivaractor diodes and transistors). A typical size of trim -
i
j
ming capacitors is 0.35 x 0.31 x 0.12 cm. the Q-factor is about 500-1500 at 250
i
MHz and 130 -45 at 1 GHz. self-inducranee is about 1.2-1.5 nH. capacitance
I
range is 1.5-15 pF ''Trimmer .IS 130) 07 . Trimming capacitors generally can not
I
be tuned electrically and are difficult to integrate with MMIC. Varactor diodes
i
and transistors can be integrated with MMIC and tuned electrically. However.
S
the nonlinear C-V characteristic of the semiconductor devices causes their capac-
|
itances to be functions of RF voltages.
It leads to intermodulation distortion
(IMD) in a wireless communication system that employs them as tuning circuits.
Also, semiconductor devices have high loss (low Q)in high frequencies due to con­
tact resistors. Compared to trimming capacitors. RF MEMS tunable capacitors
are smaller and tuned electrically. It also can be integrated with MMIC. Com­
pared to varactor diodes and transistors. RF MEMS tunable capacitors have low
loss and high Q at high frequencies. RF MEMS tunable capacitors do not ex­
hibit intermodulation distortion because the MEMS actuators do not respond to
RF signals. A comparison of MEMS tunable capacitors, trim ming capacitors and
varactor diodes is summarized in Table 1.3
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21
Research on the MEMS tunable capacitors has started recently [69]. [79][81j. Larson et al. designed a MEMS tunable interdigital capacitor using elec­
trostatic actuators [69]. The capacitance can be changed linearly from 0.035 pF
to 0.1 pF with the bias voltages of 80 volts to 200 volts. Q-factor was not re­
ported. Dec et al. i79i have reported a MEMS tunable parallel plate capacitor
using electrostatic actuators. A Q-factor of 0.6 at 1 GHz for a 4 pF capacitor
has been reported. The capacitance value changed from 4.0 pF to 4.4 pF for the
bias voltages of 0 to 0.S V. Young and Boser SO] have described a MEMS tunable
capacitor with electrostatic actuators using aluminum as the structure material
and obtained a Q value of 62 at 1 GHz for a capacitance of 2.11 pF (of 4 shunt
capacitors in parallel) from the measured S-parameters up to 1.2 GHz. Goldsmith
et. al have reported an digital tunable capacitors tuned by RF switches. Its tuning
ratio is high (22:1) and the capacitance can be tuned from 1.5 pF to 33.2 pF. But
the control voltage is high (30-55 volts), self-resonant frequencies are low (below
2 GHz at 6 pF). the Q-factor was not reported. So far none of the MEMS tunable
capacitors has been reported for using at frequencies beyond id GHz iX-band).
To show the advantage of MEMS capacitors, compared to semiconductor devices,
tunable MEMS capacitors need to be characterized carefully to improve Q-factors
and self-resonance frequencies for X-band communication systems.
In this thesis, the goal of the research of the tunable MEMS capacitors is to
characterize these capacitors from the RF view and develop design rules for RF
MEMS capacitors to obtain tunable MEMS capacitors with high Q-factors and
high self-resonance frequencies for microwave and mm-wave applications.
1.3.2
MEMS m ultiw ay sw itches
Because the structure of a single-pole single-throw RF switch is simple, the
RF MEMS switch is the first application of MEMS at RF frequencies and is the
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most investigated RF MEMS device as well [55]. [68] - [73]. [75] - [76]. The elec­
trostatic switch consists of either a thin metallic cantilever or some other forms
of membranes that are pulled down to a bottom electrode to short or open a
transmission line . Micromechanical membrane switches have several advantages
compared to FET or p-i-n diode switches [55]. [70] - [73i. [75] - [76]. (1) Losses of
R.F MEMS switches are primarily do uu.ua it'd u\ cuuuuciur
losses
and not depen­
dent on contact resistors typically seen in semiconductor switches. This makes low
loss and IMD switching possible. (2) MEMS switches are amenable to low-cost
processing. MEMS switches fabricated on silicon possess only six process lay­
ers. Silicon compatible processing on material such as silicon-on-sapphire allows
fabrication of 6-inch wafers with advantageous economies of scale. (3) Microme­
chanical switches require low supply power, using DC supply current only during
the switching transient. The typical switching energy is approximately 10 nano­
joules. (4i Micromechanical switches also are integratable with other technologies.
Devices built on silicon on sapphire can be integrated with CMOS control circuits
to perform level shifting and address decoding. This allows a substantial reduction
in packaging complexity associated with routing control signals to each individual
membrane element. These switches also can be integrated with GaAs electron­
ics to achieve low loss and low IMD switching of low-noise amplifiers and filters
for receiver front ends. A main limitation of these switches is their switching
speeds. Microsecond switching precludes their uses in transmit/receive switching
applications. However, these speeds are more than sufficiently fast for electronic
beamsteering. Potential insertions include low loss switches, phase shifters and
antenna tuners for low noise receivers and phase array antennas for both m ilitary
and commercial telecommunications at microwave and mm-meter wave frequen­
cies.
The first application of MEMS in RF frequency range is a switch for low
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23
frequency signals, which has been published in 1979 [68]. This switch employed
a micromechanical cantilever beam on a silicon substrate using electrostatic force
to pull the cantilever beam down and up to switch the electrical signal. In 1991.
Larson reported a rotary switch on silicon, utilizing electrostatic actuation [691.
The insertion loss of 0.5 dB and the isolation of 35 dB at 40 GHz were reported for
this switch. The actuation voltage were in range uf 30-200 volts. Because of the
rotary structure, the switching speed was not high. A group at Texas Instruments
developed membrane switches, with the actuation voltages around 30-50 volts '70:
- :<3;. The insertion loss was 0.1-0.25 dB and the isolation was 15-25 dB at 10
GHz. In 1997. Santos published the optimization of cantilever structures r74" to
obtain the insertion loss of 0.1-0.01 dB and the isolation loss of 20-40 dB with
actuation voltages around 3U -80 volts. In 1999. Hyman 76 reported a cantilever
beam RF MEMS switch with the act nation voltage of 30 volts. The insertion
loss was 0.2 dB from DC through 40 GHz and the isolation was 50 dB below
2 GHz from EM simulation results. So far. all of these efforts focused on the
SPST switch designs. MEMS SPDT and SP3T (multiway switches need to be
developed for RF applications. In Chapter 6 of this thesis, we treat the design
of compact MEMS multiway switches using cantilever beams with electrostatic
actuation.
1.4
Organization o f the thesis
This thesis begins with a study of flip-chip interconnects in CPW configura­
tion. In Chapters 2 and 3. characterization and modeling of flip-chip interconnects
with and without underfill epoxy have been presented. CPW line sections w ith
bumps on GaAs have been chosen as test chips. These test chips were flip-chip
bonded on alumina substrates. Two assemblies with different lengths of CPW
lines on chips have been measured and modeled before adding underfill. Then
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24
one of commercial underfill epoxies has been put under the chips and the effect
of underfill has been investigated. A rr-circuit lumped-element model of flip-chip
joints has been developed based on simulation results and verified by measure­
ment results. Also, we have studied the effect of underfill epoxy on performance
on CPW flip-chip interconnects. The additional loss and phase shift (when GaAs
chip was a through line) due m underfill epoxy have been investigated.
Chapter 4 presents the study of series-mounted RF MEMS tunable capaci­
tors. Because of linear tuning characteristic and precise position control, electro­
thermal actuators are chosen to use in RF MEMS tunable capacitors. The seriesmounted RF MEMS tunable capacitors have been designed, fabricated and mea­
sured. The connecting beams and pads are optimized and the effect of actuators
on RF performance of the capacitors is discussed. Finally, the capacitor is tested
up to 40 GHz.
The measured S-parameters show that the capacitance of the
series-mounted capacitor is tuned from 0.33 pF to O.SS pF for bias voltage from 0
to 2.5 volts. A method has been developed to obtain Q-factor from S-parameters.
Effect of the thickness of the gold layer on polysilicon on the Cj-factor has been
studied. Design rules for MEMS tunable capacitor with electro-thermal actuation
are summarized. An application of MEMS tunable capacitors: in tunable bandpass
filters in CPW configuration is reported.
Chapter 5 reports investigations of shunt-mounted RF MEMS tunable ca­
pacitors. which have been designed, fabricated and measured. A T-circuit lumpedelement model has been developed for the shunt tunable capacitor. The effect of
actuators has been characterized. Design of the capacitor has been optimized
based on the model and simulation results. Measurement results are reported.
In Chapter 6. 2-port. 3-port and 4-port MEMS multiway switches have been
designed using electrostatic actuation. A 2-port switch has been characterized,
fabricated and measured. Lumped-element models have been developed for 2-
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port. 3-port and 4-port MEMS switches. The optimizations of these switches,
based on their lumped-element models, are discussed.
Finally, a summary of the thesis and suggestions for future works are pre­
sented in the last chapter.
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Chapter 2
RF M odeling of Flip-chip Interconnects
This chapter describes RF modeling of flip-chip interconnects in CPW’ cir­
cuits. based on RF measurements and electromagnetic simulations. W’e report
experimental results for flip-chip assemblies on CPW' circuits obtained by using
on-wafer probes and HP (now Agilent Technologiesi SolOB Network Analyzer
with multi-line Thru-Reflect-Line (M-TRL) calibration up to 40 GHz 30’. Also a
3-D electromagnetic simulator (High Frequency Structure Simulator (HFSS) from
Agilent Technologies) has been used for RF modeling of CPW’ flip-chip intercon­
nects .31.. A lumped-element model of CPW’ flip-chip interconnects has been
developed and verified based on measurement and simulation results. Flip-chip
interconnects with different bump heights have been simulated to investigate the
effect of bump heights on the RF performance of flip-chip interconnects.
2.1
Experim ental characterization of flip-chip interconnects
In this section, measurements of flip-chip interconnects on CPW' are reported
and a lumped-element model for the flip-chip interconnect in CPW' circuits has
been developed and verified based on experimental results.
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27
2.1.1
Test circuits and assem blies
For characterization of flip-chip interconnects, a section of 50 Cl CPW line
on alumina substrate (the most common substrate for hybrid MICs) is taken as
a test motherboard circuit. A GaAs chip with a 50 Cl CPW line, air bridges and
bonding pads is flip-chip bonded on the motherboard circuit.
In our study, two GaAs chips1 containing CPW through line sections have
been selected for this experiment 4Q:. Figure 2.1 shows the photo of these two
chips. The smaller chip is called chip Xo. 1 and the lunger chip is called chip Xo.
2 in this thesis. There is a 0.600 mm 50 Cl CPW through line on chip Xo. 1. with
dimensions of 1.106 mm x 1.3S0 mm x 0.635 mm. Chip Xo. 2 with length of 4.700
111111
has a 4.125 mm 50 Cl CPW line on it. The thickness of the GaAs substrate
Figure 2.1: Photo of the GaAs test chips with bumps. The smaller chip is used
in this thesis as chip Xo. 1 and the longer chip is called chip Xo. 2.
is 0.635 mm. The center strip and gaps of CPW line are 30 gm and 35 gun wide.
respectively. On these test chips, six silver bumps were plated at the ends of CPW
1 These chips were donated by Hughes Aircraft Company.
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28
lines and on edges of ground planes for signal and ground (shown as the black
circles in Figure 2.1). Dimensions of the bumps are To pm in height and 150 pm
in diameter before flip-chip bonding. Two CPW circuits, which are marked 1 and
4 in Figure 2.2. have been designed and fabricated on 0.635 mm thick alumina
substrate as carriers for chip Xo. 1 and 2. respectively. For minimizing the effect
I
of metal lavers on the motherboard underneath the GaAs chipl28 . an opening
in the metallization on the alumina substrate has been designed to remove metal
layers under the chip. CPW lines on alumina consist of two metallization layers,
j
0.02 pm TiW and followed 4 pm gold. The dimensions of CPW lines on alumina
!
are designed for an impedance of 50 il. The center strip (203.6 pm) is selected
j
I
I
!
wide enough for bonding bumps and the gaps are 96.7 /mi each. The length of
CPW at each end is 1.24 mm. which including the bonding pads and pads for
j
CPW probes. M-TRL calibration procedure 30' has been utilized for on-wafer
!
calibration. The M-TRL calibration standard set (taking the center plane of the
CPU’ thru line as reference plane) consists of one 1.0(1 mm thru line, four delay
;
lines which are longer than the thru line, and one -0.1 mm offset short to cover 0.5
GHz-40 GHz frequency range. These lensths of four delay lines are 24.94 mm (line
l i. 10.767 mm dine 2). 4.671 mm dine 3) and 2.22S mm dine 4). For the layout,
all of lines in the calibration set are added extra 0.09 mm at each end as pads for
CPW probes. Dimensions of CPW lines in calibration set are the same as those
used in carrier circuits. Both the calibration set and carrier circuits for mounting
chips have been fabricated on one single 25.4 mm x 25.4 mm alumina substrate
(see Figure 2.2).
The flip-chip thermosonic technology has been employed in
flip-chip bonding [41]. Parameters used for the bonding operations are: bonding
force 14.1 X. temperature 180°C. bonding time 300 ms and ultrasonic power 8.5
W. After bonding, the assemblies have been inspected under the microscope and
probe station for checking the alignment and the conductivity. The height of the
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bumps is reduced to 62 yum and the diameter is changed to 181 /im due to the
bonding force. A photograph of final assemblies is shown in Figure 2.3.
i
!
i
i
i
i
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30
Line4Short 5
Line2
4
Thru Line3
Figure 2.2: Layoui of calibration set and circuits for mounting chips on alumina
substrate. Three chip-sets (1.2.3) are shown at the first line. Two chip-sets (4.5)
are shown at the right end of the second line. Only two chip-sets (1 and 4) were
used in this thesis. The calibration set. which consists of a thru line, four longer
delay lines and one offset short, are the rest of components in this layout.
Figure 2.3: A photograph of flip-chip assemblies with chip Xo. 1 and chip Xo. 2.
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31
2.1.2
M easurem ent results and m odeling
Measurements2 have been performed on a HPS510B network analyzer with
Cascade on-wafer probes for a frequency range extending to 40 GHz. A pair of
probe heads with 250 ^m pitch are selected for a dimensional match to CPW lines
on alumina.
Measurement Results: Figure 2.4 shows the measured 5 U of line I in cal­
ibration set obtained from the calibration procedure as a function of frequency
and also shows the data from Microwave Design System (MDS) simulation (dis­
cussed later) for line 1. The agreement between two sets of results is fairly good
and wo can conclude that the calibration and measurement have been carried our
properly.
C. 05
Frequency(GHz i
4 0. 0
Figure 2.4: The measured Su of line 1 in the calibration set compared with the
response from the simulation by using MDS.
Solid curves in Figures 2.5 and 2.6 display measured magnitudes (dB) of
2 All R F measurements reported In this thesis were carried out at National Institute of
Standard Technologies' laboratories in Boulder. CO.
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32
Sn and S2i of the flip-chip test assembly with chip Xo. 1 (a length of 1.106
mm CPW). Figure 2.7 shows the measured phase of S21. The solid curves with
squares are obtained from the model developed as discussed later. Figures 2.S and
2.9 shows the similar results of the flip-chip assembly with chip Xo. 2 (4.700 mm).
The phase of S2 1 is shown in Figure 2.10 for chip Xo. 2. Reference planes for all of
nipsw nrprl rp c u lrc arP Q
rnrn fr o m
r ip e of*
probcS
P e r tllCSC
the characteristic impedance. Ztl. of TRL lines is taken as the reference impedance.
Modeling: A lumped-element model of flip-chip interconnects in CPW cir­
cuits is needed by RF and microwave circuit designers for incorporating the effect
of flip-chip interconnects in circuit designs. For deriving a lumped-element model
of the CPW flip-chip interconnects from measurement results, we start with a
simple 7r-circuit based on physical understanding of CPW flip-chip interconnects.
The Tr-circuir model for one single flip-chip interconnect on CPW is shown in Fig­
ure 2.11. In this model. L denotes the inductance of bumps and the inductances
associated with the bend between CPW line on the motherboard and connecting
bumps, and the bend between connecting bumps and the CPW line on chip. Ca­
pacitors C l and C2 represent the discontinuity capacitances at the bumps located
on alumina and GaAs substrate, respectively. The resistance R denotes the loss
in the flip-chip interconnect. Port 1 and port 2 of the flip-chip interconnect are
usually on different layers. In our case, port 1 is on the end of CPW line on
alumina and port 2 is on the end of CPW line on GaAs chip. Therefore, it is
not practical to make measurements on one single flip-chip interconnect directly.
As mentioned above, these whole flip-chip assemblies have been measured. In
order to get the model of the single flip-chip interconnect from the measurement
results of the whole flip-chip assemblies, the flip-chip assembly is divided into five
sections: two flip-chip interconnects, one section of CPW on a GaAs chip, with
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
substrate effect, and two sections of CPW on alumina substrate motherboard,
shown in the top portion of Figure 2.12.
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34
Fisiure '2.3: The measured 5n fur the flip-chip assembly with chip No. 1 11.106
Him ions’;!1and the simulated response from modeling.
-Measured-.
aaaoaa
Tioae^ir.c i
?recuer.cv(G K :i
Figure 2.6: The measured Soi for the flip-chip assembly with chip No. 1 and the
simulated response from modeling.
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35
Figure 2.7: Phases of 5-.>i for the flip-chip assembly with chip No. 1.
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36
Figure 2.S: Tlu> measured values of SyL for the flip-chip assembly with chip Xo. 2
i a length of 4.700 innr and the response from modeling.
j
z aoooo
Measured.
~ o d e l:n a
Freauencv(GHz)
Figure 2.9: Measured S2i values of the flip-chip assembly for chip Xo. 2 (4.700
mm long) and the response from simulations.
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37
O
0
0
1
To3
x
X.
• a : c" ■'•an
:acooc
-
•a
-
'
Figure 3.11): Phases of 5-_>i fur rhe flip-chip assembly with chip Xu. 2
C 2
Figure 2.11: Lumped-element model of one single flip-chip interconnect on CPW
with three bumps on each end for signal and ground planes.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3S
• \ lu ir ir . J 'L S M r a l.*
C ? W
''b
- i.u m ir u
L
P o n
’.
P o n
v
f* P ^ *m V u m iiu
CTA
——
r. Cj_ v
vntp. SurN f^tc Er^T
N J i 'C n
:
>r. •Viurr.m.i
r F - .? -v n
Intfri.-p.nec
Figure 2.12: Modeling of flip-chip assemblies on CPW’. For modeling purposes, the
assembly is separated into three parts: CPW on mother board substrate. CPW
on GaAs chip with substrate effect and flip-chip interconnects.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
39
Table 2.1: Comparison of Z q and e r e of CPW on GaAs with and without alumina
substrate vicinity effect at 10 GHz
:
t
Z q (Q)
^re !
i CPW on GaAs with alumina j 46.48 ! 7.259
! CPW on GaAs without alumina : 50.1 ! 7.1S
Put tilt- CP”
nfv-tiou on Liit- GaAs chip, alumina substrate effects on Z q and
f r, of CPW on GaAs have been evaluated by EM simulation using Agilent Tech­
nologies' High Frequency Structure Simulator (HFSS). Comparisons of Z q and e-,.
values with and without the substrate effect are shown in Table 2.1. For the CPW
line on the alumina substrate, the default model in Microwave Design System
(MDS) is used. Including the - circuit model for the flip-chip interconnects, the
schematic circuit (Figure 2.12) of the whole assembly is represented by an equiv­
alent network in MDS for optimization. Responses of the CPW circuit (obtained
from MDS) for various values of L. R. C’1 and C2 in the lumped-element model
are obtained and compared with the measured response. Optimized values are
correspond to the lowest differences between measured and modeled S-parameters
I least square). Figure 2.13 shows the How chart for RF modeling of CPW flip-chip
interconnects.
Comparisons of the measured results and the corresponding responses of the
model for the flip-chip assembly with chip No. 1 are shown in Figures 2.5. 2.6 and
2.7. Similar results for the flip-chip assembly with chip No. 2 are shown in Figures
2.8. 2.9 and 2.10. This exercise shows that the optimum values are: an inductance
of 0.02 nH. a resistance of 0.3 Q. C l and C2 of 0.025 pF and 0.091 pF. respectively.
The agreements between the measured and modeled values of the magnitudes of
S-parameters are very good, but there is a lack of agreement in the phases of S21
values. It may be because of the difference between the measured and simulated
electrical lengths of CPW lines on alumina and on GaAs with substrate effect.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
40
In the modeling, the ideal model in MDS is used for the CPW line on alumina.
In the HFSS simulation for the substrate effect, the thickness of metal layers of
the CPW lines is taken as zero. A ll of these affect the effective dielectric constant
and the calculation of electrical lengths of the CPW lines. However, the difference
does not affect the lumped-element model significantly because the length of CPW
included in the flip-chip interconnect is very short. Hence, the lumped-element
model for the flip-chip interconnect is valid. Note that the inductance value (0.02
11
H) is much smaller than the typical value of bonding wires (0.14 nH for 300 pin
length and 23 /mi diameters 11). In our case, the 0.3 P. ohmic loss includes the
loss of the CPW line on GaAs and also the loss of a part of the CPW line on
alumina. Therefore, the loss of flip-chip bumps should be lower than 0.3 P. Also,
the measurement error of loss due to the measurement errors of S-parameters
has an order of 0.1 P.. More discussions about the ohmic loss in the flip-chip
interconnects have been presented in the section of Effect of Bump Heujht. If a
two-tier TRL calibration is utilized, the effect of CPW lines can be removed ami
the loss due to the single flip-chip) joint can be found.
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41
\vi"->in<i;- -u;_
Interconnects assembly
C PW on alumina
CPN\ on GaAs
Model ot
substrate
substrate with
substrate effect
flip-chip
interconnect
S-parameters of
assembly
Model of assembly
(measured or HFSSi
Optimization using M D S
_______ I_______
Values o f elements in
flip-chip interconnect
model
Figure 2.13: Flow chart of the modeling method for CPW flip-chip interconnects.
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42
2.2
E lectrom agnetic sim ulation of flip-chip interconnects
A flip-chip interconnect is physically a three-dimensional structure. There­
fore. an accurate simulation of its performance needs a 3-D electromagnetic field
simulator. HFSS [31] from Agilent Technologies utilizes the finite element method,
which is a rigorous 3-D electromagnetic simulation method, and can compute the
complex 3-D configuration accurately. We have used HFSS to calculate frequencydependent S-parameters of the flip-chip assembly with chip No. 2. Also, single
flip-chip interconnects with different bump heights have been simulated.
2.2.1
Num erical results and analysis
Figure 2.14 shows the structure of the 3-D flip-chip assembly analyzed by
HFSS. The CPW flip-chip assembly is enclosed in a box whose walls are perfect
conductors. Dimensions of the flip-chip assembly are the same as those in the test
assembly with chip
N o.
2 (4.700 mm CPW lensrth'. Conductors are taken to be
gold and assumed to be infinitely thin. Air layers are added
b e lo w
and over the
assembly to remove the effect of the outer enclosure metal on RF performance of
the assembly. The electromagnetic wave is incident from port 1 of the CPW line
on alumina substrate and is coupled to the CPW line on the GaAs chip through
the bumps, and then, again via the bumps, coupled to the port 2 of the CPW
line on alumina. Because of the symmetry of the structure with respect to the
plane x-x. we need to consider only the half of the flip-chip assembly shown in
Figure 2.14. Furthermore, recognizing the symmetry of the structure with respect
to the y-y plane and using even and odd mode excitations, only one quarter of
the configuration is needed to set up simulations. This structure is analyzed twice
w ith electric wall and magnetic wall at the y-y plane to obtain S-parameters for
the even mode {Sue) and the odd mode (Sn0). Parameters Sn and S21 of the
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43
complete assembly are calculated from
s 11 =
Sne
- lie
+
and
S u 0 as [321:
S u o
r
(2.1)
S'Ae ~ Sun
S-n = ------ —
The x marks in Figure^ 2.1-j and 2.iu ahuw tlitr* Minuiciiiun
*2 .2 )
2qi anu
ui
the flip-chip assembly for chip Xo. 2. The solid lines are the measurement results
of this flip-chip assembly. We note that there is a little lack of agreement at high
frequencies. This may be attributed to the following: ( li In HFSS simulations,
all of the metal layers in the HFSS simulation structure have been taken as zero
thickness. But in experimental setup, the metal layer on the mother board is
4 /nn thick and the one on the chip is G /mi thick. The thickness of the metal
layers affects the calculated value of the effective dielectric constants of CPW lines.
The effective dielectric constant of the CPW lines on alumina with 0 thickness
metal layer is 2 percent higher than that of the CPW lines with 4 pm thickness
gold. The effective dielectric constant of the CPW lines on GaAs with 0 thickness
is 11 percent higher than that of the CPW lines with 6 /nil gold. Hence, the
electrical length of CPW with I) thickness metal layer is longer than that of CPW
line with 4 or 6 pm gold layer for the same physical length of CPW line. When
frequency is higher, the difference becomes larger. Note that at low frequencies
the agreement is fairly good, but at high frequency, the point with minimum
reflection in simulation results is shifted down compared with the measured results
because the calculated electrical length is longer at higher frequencies.
(2) In
measurements, assemblies are placed on a quartz substrate to isolate assemblies
from the metal plane of the holder in the probe station, but the assemblies float on
the air layer in HFSS simulation. Because the thickness of motherboard substrate
(alumina) is thick (635 pm) compared with the gaps of CPW line (96.7 pm).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the effect of the quartz substrate can be ignored. Hence the second reason is not
significant. For the first reason, if the length of the CPW line is reduced, the effect
of the thickness of the metal layer can be ignored as well. In the next section, one
single flip-chip interconnect with very short CPW lines is studied by using HFSS.
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45
CPW on chip
CPW on substrate
>—
l, *. i-*",. .'•• ?
Port 1
Pon
\
GaAi^chip^
----------------------
Bump
■Mumina substrate
i b»
Figure 2.14: Structure of the flip-chip interconnect simulated on HFSS. (aI Top
View and (b) front view.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
46
CQ .
"C r
cn
o
lO
i
0.05
FrecuezcviGHz:
40
Figure 2.13: Comparison of the measured and simulated values of S;i for the
flip-chip assembly with chip Xo. 2. which length is 4.700 mm. x marks are the
simulation result> from HFSS. the solid line is the measured result.
r<j
CO
o
•
*
_
.
.
.
.
.
...
-
_ _
— -
i -------------------------------___________________
0.05
Frequency(GHz)
40
Figure 2.16: Comparison of the measured and simulated values of S? 1 for the
flip-chip assembly with chip Xo. 2. which length is 4.700 mm. x marks are the
simulation results from HFSS. the solid line is the measured result.
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47
2.2.2
Effect of bum p height
The structure of one single flip-chip interconnect, which has been simulated
in HFSS. is shown in Figure 2.17. d is the bump height that is equal to the
airgap between the chip and the motherboard. Dimensions of the flip-chip joint
are the same as those of flip-chip joints in experimental test assemblies except
the thickness of metal layers (as before, all of the metal layers are taken to have
0 thickness in HFSS simulation j. The reference plane is placed at the center of
these bumps (see Figure 2.17). Port 1 is on the end of CPW’ on the alumina
motherboard and port 2 is on the end of CPW’ on the GaAs chip. The simulated
Reference plane
*
Bump
.
Pon:
CPW on.A lum ina suhstruiae
t
*
"
" " ;r
CPW on G aA s Chip
Figure 2.17: Structure of one single flip-chip interconnect used in HFSS simulation,
d is the bump height, which is equal to the air gap between the chip and the mother
board.
S-parameters for bump heights from 62 pm to 240 pm are shown in Figures 2.IS
and 2.19. RF performance of the flip-chip interconnect with a bump height of 240
pm is better (smaller Sn and larger S2 1 ) than others. Magnitude of S2i is 0.973
(-0.238 dB) at 22 GHz. Magnitude of Su is 0.165 (-15.7 dB) at 22 GHz. The
insertion loss is good for most applications in the microwave frequency range, but
the return loss is higher than -20 dB return loss required in typical applications).
There are two kinds of losses introduced by flip-chip interconnects. The first
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48
Table 2.2: Loss of single flip-chip joints with different bump heights.
t
o
—*
CO
i Bump height (gm)
62
120
240
■5ai
0.235
0.212
0.186
0.167
! •S'oi
! 0.958
: 0.963
| 0.96S
1 0.973
Loss(dB)
0.1259
0.1277
0.1296
0.1253
is the ohmic loss, the energy dissipated in flip-chip interconnects, the other is the
return loss, the energy reflected back due to the mismatching of dimensions around
the flip-chip joint. According to the energy conversation law. the ohmic loss can
be found from the S-parameters of the flip-chip interconnect. Expressed in dBs.
the loss is equal to iO/ot/l l ~C.C ). The ohmic losses of the flip-chip interconnect
with different bump heights (at 22 GHz ) are summarized in Table 2.2. There is
not a significant difference in these losses when the bump height changed. The
value of ohmic loss (0.13 dBl is smaller than the insertion loss (0.24 dB). Hence,
the large return loss may be mainly contributed bv the dimensional mismatching
of
CPW line around bumps. By carefully designing the layout
of
C'PW near the
bumps. RF performance of the flip-chip interconnects on CPW can be improved
further.
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49
0.3
0.25
0.2
0.15
01
0.05
0
10
1 5
20
25
Freauency (GH z)
Figure 2.IS: Simulated values of 5n for a simile flip-chip iiiremuinect on CPW as
a function of frequency for different hump heighrs. Bump height is changed front
02 to 240 /mi.
S2l 62 j m
S2’ 120jm
S21 1 8 0 - ~
0
0 jn
9 9
5 098
0.97
0.96
0.95
10
15
20
25
Frequency(GHz)
Figure 2.19: Simulated values of Soi for a single flip-chip interconnect on CPW as
a function of frequency for different bump heights. Bump height is changed from
62 to 240 fini.
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50
2.3
Remarks
Measurements of the CPW flip-chip assembles with chip No. 1 and chip
No. 2 have been carried out and provide us with accurate datas used for deriving
a lumped-element mudel of flip-chip interconnects in CPW circuits for cylinder
bumps with 62 finl height and 1S1 fiin diameter good up to 40 GHz.
HFSS
simulation of the flip-chip assembly with chip No. 2 has been obtained. The
bump height effect in flip-chip interconnects has been discussed based on HFSS
simulation results. In the next chapter, the effect of the underfill epoxy on the
RF performance of these flip-chip assemblies will be described.
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Chapter 3
U nderfill Effects on Flip-chip Interconnects
This chapter describes the effect of underfill epoxy on the RF performance
of flip-chip assemblies discussed in Chapter 2. After flip-chip bonding, some epoxy
I
materials are introduced in the gap between the chip and the motherboard subsrrare. This 'underfill' material is cured for reducing the stress of joints during
j
i
|
j
!
thermal excursions and thus increased the structural reliability of Hip-chip assemblies. In our case, the fatigue life (measured in thermal cycles before breakdown)
uf the assembly with chip No. 1 (small chip with a length of 1.1UG mini is increased
|
from 1200 to 14000 thermal cycles 99 when an underfill epoxy is used. However.
I
I
the underfill epoxy influences RF performance uf the flip-chip assemblies. In this
chapter, effects of underfill epoxies on RF performance are characterized up to
40 GHz. based on the measurement results of CPW flip-chip assemblies with and
without underfill epoxy. The lumped-element model of the CPW flip-chip inter­
connects. which was developed in the previous chapter, is modified to include the
effect of underfill epoxy.
3.1
Test circuits and m easurem ent
Two flip-chip assemblies with two GaAs chips on alumina motherboard,
which have been investigated without underfill in Chapter 2. are used to study
the effect of underfill epoxy. An epoxy (U300 from Epoxy Tech. Inc.. with er =4.1
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
oz
and tand=0.009 at 100 kHz) has been filled in the gaps between chips and the
motherboard substrate, and cured at 120° C for 25 minutes. Figure 3.1 shows a
photograph of the flip-chip assemblies w ith the underfill epoxy. In this photo, the
black regions underneath the chips are the epoxy material. Note that the underfill
epoxy does not spread significantly away from the chip location.
As earlier. RF measurements have been performed on a HP8510B network
analyzer with on-wafer probes for a frequency range 0.05 GHz to 40 GHz. MTRL calibration set. which has been described in Chapter 2. has been used for
calibration. Measurements of assemblies for chip No. 1 and chip No. 2 with the
underfill have been carried out.
3.2
3.2.1
M easurem ent results and characterization
M easurem ent results o f flip-chip assem blies w ith underfill
Figures 3.2 and 3.3 show the comparison of measured S-parameters of the
fiip-chip assembly for chip No. 1 (with a 0.600 mm CPW linei with and without
the underfill epoxy. Figure 3.4 and Figure 3.5 show the similar results of the flipchip assembly for chip No. 2 (with 4.125 mm CPW line l. Comparing the measured
results of the two fiip-chip assemblies with and without underfill, we see three kinds
of effects due to the underfill: (1) increase of the return loss and insertion loss of
flip-chip assemblies. (2) downwards shift of frequencies at minimum reflection and
(3) shift of phases of transmission coefficient. These effects are observed because
the er and tand of the underfill epoxy are larger than those of air. In the next
section, the effects of the underfill on RF performance of the flip-chip assemblies
have been characterized in detail.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
53
Figure 3.1: A photograph of flip-chip assemblies with underfill epoxy. The small
box at the up left comer is chip No. 1. which has been fiip-chip bonded on rhe
alumina substrate. The black region underneath the chip is the epoxy material.
The large long box is chip No. 2. A section of CPW line, which can be seen on
each side of these chips, is the probe pads.
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54
0
10
•20
•30
n
a
■
»
V
w ith o u t e p o x y .
•50
with ep oxy
•60
0
30
20
10
40
50
Frequency(GHz)
Figure 3.2: Comparison of the measured s \; of the fiip-chip assembly with and
without the underfill epoxy for chip Xo. 1.
m
x»
without epoxy
■4
—
with epoxy
5
0
10
20
30
40
50
Frequency(G Hz)
Figure 3.3: Comparison of the measured Soi of the flip-chip assembly with and
without the underfill epoxy for chip Xo. 1.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
55
0
10
•20
•30
without epoxy .
w ith epoxy
-60
0
10
20
40
30
50
Frequency(GHz)
Figure 3.4: Comparison of the measured 5 It of the fiip-chip assembly with and
without the underfill epoxy for chip Xo. 2.
CQ
w i t h o u t e poxy
w ith epoxy
'*
•10
0
10
20
30
40
50
Frequency(GHz)
Figure 3.5: Comparison of the measured S2 1 of the flip-chip assembly w ith and
without the underfill epoxy for chip Xo. 2.
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56
3.2.2
Losses
Losses in the CPW flip-chip assembly include the loss in the CPW line on
the alumina substrate, the loss due to the flip-chip interconnects, and the loss in
the CPW line on the GaAs chip. From measured S-parameters. the total loss in
dB of the flip-chip assembly can be evaluated as:
Figure 3.6 shows the losses of the flip-chip assembly with and without un­
derfill epoxy for chip Xu. 1. Figure 3.7 shows the similar results for chip Xo. 2.
The only difference between the two sets of data is the addition of the underfill
epoxy. So the additional loss due to underfill epoxy can be evaluated from the
difference. The additional loss at 40 GHz is less than 0.6 dB for the flip-chip
assembly with chip Xo. 1 and has a per unit CPW length value of 0.266 dB, mm.
For the flip-chip assembly with chip Xo. 2. the additional loss at 40 GHz is less
than 1 dB and has a per unit length value1 of 0.213 dB. nun. The average addi­
tional loss is 0.24 dB nun at 40 GHz due to the addition of the underfill epoxy
with er =4.1 and tand=0.009 at 100 kHz.
3.2.3
C hange in
t rr
o f C P W line on GaAs
Shifts of frequencies with the minimum reflections in Figures 3.2 and 3.4
are attributed to the difference in the values of the effective dielectric constants
of CPW lines w ith and without the underfill epoxy. The effective dielectric con­
stants of CPW on GaAs with and without underfill have been computed by EM
simulations using HFSS. Figure 3.8 shows the multilayer structures simulated in
HFSS. The airgap between GaAs and alumina is 62 /im. which is equal to the
bump height after bonding. \ alues of ere of the CPW Line on GaAs without and
with underfill epoxy are 7.259 and 8.917. respectively. The difference is about
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0 I
23 percent. The electrical length of CPW lines is a function of frequency, the
effective dielectric constant and the physical length of CPW lines [32].
le =
(3-2)
where the L and lp are the electrical and physical length of the CPW line oil
GaAs. respectively. / is the frequency, c is the velocity of light and crt. is the
effective dielectric constant of the CPW line, which is a function of frequency.
When the electrical length le of the CPW line on GaAs between the two flip-chip
interconnects is equal to [2n — 1)A - the reflection from the flip-chip assembly
will be minimum. Since the epoxy changes the t r, . the frequencies for minimum
reflection shift as following:
e
J U-or
J
:it
,
r r' .. .
I .j ^ j
f rr,l iir
where. f wot and / Trt are the frequencies of minimum reflections in the flip-chip
assemblies without and with epoxy, respectively. ert,ir and
are the effective
dielectric constants of CPW line on GaAs in flip-chip assemblies with and without
epoxy. Therefore, we can calculate the frequencies for assemblies with epoxy from
measured frequencies for assemblies without epoxy. Table 3.1 shows the measured
and calculated (using the computed values of the effective dielectric constants)
frequencies of minimum reflection for the two assemblies. The good agreement
between the measured and calculated frequencies for minimum reflection validates
the accuracy of our measurements and modeling.
3.2.4
P h ase shift due to underfill epoxy
The phase shift of the transmission coefficient S2 1 of the flip-chip assembly
before and after adding the underfill epoxy consists of three parts: the first and
major part is the phase shift in CPW line on GaAs with and without epoxy, the
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58
Table 3.1: Comparison of the measured and calculated frequencies for minimum
reflection in the flip-chip assemblies with the underfill epoxy
Xo. of chip ;
Measured Freq.
• without epoxy (GHz)
, Chip Xo.l ;
36.0050
Chip Xo. 2
34.2073
Chip Xo. 2
21.2235
Chip Xo. 2
9.43S3
i
Measured Freq. ; Calculated Freq. ;
with epoxy (GHz! | with epoxy (GHz) '
i
32.4857
!
32.2085
30.8637
31.4108
19.1490
19.6255
S.5157
S.4385
second part is the phase shift due tu the bump interconnects and the third part is
the phase shift in CPW line on alumina. The bump height after bunding is about
02 finl and the length of CPW line on alumina that got covered by epoxy is about
L50 pin.
F o r c o m p u t i n g th e phase s h ift d u e to th e b u m p i n t e r c o n n e c t , th e b u m p
in te r c o n n e c t are ta k e n as a s e c tio n o f tra n s m is s io n lin e in th e a i r a n d u n d e r f il l
m a t e r i a l , so th e p h a s e shift is t a k e n
b u m p h e ig h t, f ,
a n d ( r, . .
as k 0 (
Wl
-
va
)d.
w h e r e d is th e
a re t a k e n as th e d ie le c tr ic c o n s t a n t s o f a i r a n d th e
epoxy, respectively. For CPW on alumina mother board substrate, the phase shift
value is
.i s
- vf
ilp. where / is the physical length of CPW line on
alumina which has been covered by epoxy.
is the effective dielectric constant
of CPW on alumina covered by 150 pm thick epoxy. er tw is just the effective
dielectric constant of the CPW line on alumina. For CPW on GaAs. the phase
shift has been computed using above formula with the values of ere reported in
the previous section. Finally the total phase shift is the sum of these values.
The measured and calculated values of phase shifts for Chip Xo. 1 and Chip
Xo. 2 are shown in Figures 3.9 and 3.10. There is a fair agreement between the
measured and calculated phase shifts. Xotice that there is the better agreement
for chip Xo 2. It may be because of the fact that the approximation of three
bumps in flip-chip interconnects taken as a transmission line in air (as reported
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
59
by Krems [14]) is not sufficient. For the longer chip, however, the phase shift
due to CPW on GaAs is dominant so the agreement is better. The measured
phase shift at 40 GHz is about 22 and 13 degree/mm for chip X o.l and chip Xo.
2. respectively. The average phase shift due solely to the flip-chip interconnect
with and without underfill is about 4.3 degree (5.4° for chip Xo. 1 and 3.2° for
chip Xo. 2) when taken the flip-chip joint 300 pm long along CPW line. This is
acceptable for most RF applications. Otherwise, we can redesign CPW lines on
chips considering underfill epoxy.
3.3
M odeling based on m easured results
The lumped-clement models for the CPW flip-chip interconnects with and
without epoxy are identical. However, the values of elements are different in two
cases. Figures 3.11 and 3.12 show the comparison of the measured results and
the corresponding responses using the lumped element model for chip Xo. 1 with
the epoxy. The agreement between the measured results and the response of the
model is fairly good. These model values are shown in Table 5.2. The vaiues of the
inductance in the two cases are very close. The effect of the underfill epoxy on the
inductance is negligible because the epoxy is not a magnetic material. Vaiues of
two capacitances increase due to the underfill epoxy because the dielectric constant
of the epoxy is larger than that of air. Using the lumped-element circuit model,
we calculated the insertion loss introduced by a single CPW flip-chip interconnect
(a set of three bumps). Increase in the insertion loss because of the underfill epoxy
is 0.5 dB at 35 GHz.
3.4
Rem arks
The investigations reported in this chapter show that the U300 epoxy (from
Epoxy Tech. Inc.) with er=4.1 and tand=0.009 (measured at 100 kHz) can be
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60
Table 3.2: Values of various elements in the model of flip-chip interconnects with
and without epoxy
! Chip Xo. 1 w /o epoxy
i Chip Xo. 1 with epoxy
0.014
0.010
0.018
0.028
0.0S1 1 2 x l0 "d j
0.11 i 1.2xl0-4 |
used for flip-chip assemblies up to 40 GHz with only a small additional loss. The
effect of the change in
can be compensated by modifying the line lengths
appropriately. By choosing an underfill epoxy with lower loss and lower dielectric
constant, the effects of underfill could be reduced further. The underfill epoxy
does not change the lumped-elemenr model of the flip chip assembly, but increases
values of the resistor and the capacitors.
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61
2
witnaui eooxy . .
1.75
wi t h e p o x y
.5
1.25
0.75
0.5
0.25
0
0
1C
20
30
50
Figure 3.6: Comparison of losses of the flip-chip assembly (chip No. l i with and
without the underfill epoxy.
j
2.5
2
1.5
0.5
w ith e p o x y
w ithout e pox y
0
0
10
20
30
40
50
F re q u e n c y ( G H z )
Figure 3.7: Comparison of losses of the flip-ehip assembly (chip No. 2) with and
without the underfill epoxy.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
•Xirsap
M other roam Jiumtna s u ^ tn te
CPN^ on chip
<■iu .\'
;n:p
Underfill cpo
M other board am m iru Mib'trate
>hi
Figure 3.8: Multilayer structures used in HFSS to compute the effective dielectric
constants of CPW with and without underfill epoxy in the flip-chip assemblies.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
63
measured results
Calculated results
2C
3C
:reCu6ncviGri2l
Figure 3.9: Comparison of rhe measured and calculated pha.se shifts due to the
underfill epoxy for the flip-chip assembly with chip No. 1
* asc
* s r *ec
6C
2C
•20
10
20
30
10
50
Frequency (G H z)
Figure 3.10: Comparison of the measured and calculated phase shifts due to the
underfill epoxy for the fiip-chip assembly with chip No. 2.
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64
•20
•=■ -30
CO
-40
Meas.
Modeling
-sc
1
0
20
30
40
50
Freq uen cy (GHz)
Fisrurc 3. II: Comparison of the measured 5i> and the response from the model of
the flip-chip assembly for chip No. I with underfill epoxy.
CO
T
3
Meas.
Modeling
10
20
30
40
50
F r e q u e n c y (G H z)
Figure 3.12: Comparison of the measured Soi and the response from the model of
the flip-chip assembly for chip No. 1 with underfill epoxy.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 4
D esign and C haracterization of R F Series-m ounted Tunable Capacitor
U sing M EM S
Microelectromechanical systems (MEMSs!. which can be integrated with
MMICs. allow a precise positioning and repositioning of suspended membranes
and cantilevers, and thus offer a new approach for tuninc microwave circuits.
One of important applications of MEMS in RF circuits and antennas is in the
form of tunable capacitors. High Q-faetor tunable capacitors are needed in mi­
crowave communication systems to replace semiconductor varaetors. which have
hi ah 1<is> low O-factor and hitrli intermudularion distortion! IM D ). In MEMS. usimi [lolysilicon with a cold layer as structure materials and air instead of other
dielectric materials makes liigh-Q capacitors possible. Also, there are not con­
tact and channel resistances in MEMS capacitors, and intermodulation signals
are avoided. This chapter describes design, fabrication, measurement and RF
modeling of RF series-mounted MEMS tunable capacitors in CPW circuits using
electro-thermal actuators with a drive voltage below 5 volts.
4.1
D esign and fabrication o f series-m ounted tunable capacitors
4.1.1
Electro-therm al actuation and mechanical design
Vertical electrothermal actuators employ more than two beams, which are
in different sizes and different materials to produce thermal expansion mismatch.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
66
I f constrained to expand linearly, the differential expansions result in mechanical
forces and the vertical displacement of these beams. Compared to electrostatic
actuators, thermal actuators have several advantages: (1) no collection of static
charges on capacitor plates, which improves the repeatability of capacitance varia­
tion and avoids the sticking problem in electrostatic actuation. (2) approximately
lin a a r
••
•
•-
v t* r i u r i n n
‘V
.
.
n f f ) n o r 'ir < in e ( i
>
.
K
M
tt.il
**n c n n e f
i
V
.I
ro
I
u
^
.
c* »»-«-*>.•* !
i ‘1 \
U
liU \ '- * !
Iv
/*
*C
i L
i
V
.
tuarion voltages (typically 5 volts for thermal actuators compared to 20-70 volts
for electrostatic actuators). In this thesis, electro-thermal actuation is chosen for
RF MEMS tunable capacitor designs.
Surface MEMS technology made available by multi-user MEMS process
^MUMP)1 is employed for our electro-thermal actuator designs. This process
90 includes seven layers on the surface of silicon substrate. As shown in Figure
4.1. these are one layer of S i^.\\ as the isolation layer, three layers of polysilicons
'Poly 0. Poly 1. and Ploy 2) as structure layers separated by two layers of 5/O-j
and with one layer of gold on the top surface. The two layers of S/Oj ;irt> the
sacrificial layers, which are etched out during the releasing process. Table 4.1
summarizes selected MUMP’s process parameters.
There are several special considerations in the design of vertical electro­
thermal actuators. (1) The resistances of beams in an actuator should be different
enough to produce enough temperature difference while a current goes through
the beams.
(2) The ends of beams should be fixed or connected together to
transform forces to the vertical displacement of the beams. (3) Entire MEMS
devices should be isolated from the silicon substrate using the SiOn layer so that
the silicon substrate can be removed during the releasing process. This is the key
point in avoiding the high loss of the silicon substrate with RF MEMS tunable
1 Cronos Integrated Microsystems, a JDS Uniphase Company. 3000 Aerial Center Parkway.
Suite 110. Morrisville. X C 27560.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
capacitor designs. W ith these considerations in mind, our actuators are designed
on poly 1 and poly 2 layers, and without structures on Poly 0. Hence, a whole
layer of SiOn between poly 0 and poly 1 separates the actuator from the silicon
substrate. Figure 4.2 shows one design example of the actuators, which consists
of one hot arm and two cold arms. The hot arm on ploy 1 is the center beam and
In n c r tir
r V it in
rV > P
/-- rv lr }
-a rm
Ir^
p ro c c
~ j.lX W
U lld
t ilC
*^50
//in. Two cold arms are on the ploy 2 layer and the size of each one is 1.5 //m
x S //in x 200 //m. The hot and cold arms are rigidly connected at one end and
the zither ends are fixed on the substrate separately. In the design, the resistance
of the hot arm is 321 H. the resistance of two cold arms in parallel is 237 12.
Gold—
...I.....:.;;..... ...........
*-Polv2
S i0 2 S i0 2 -
Figure 4.1: Layer layout of surface MEMS fabricated by MC’NC.
Finite element method (FEM). ABAQUS2 . has been employed to compute the
temperature distribution in the actuator along the hot and cold arms. Figure 4.3
(a) shows the temperature distribution along the hot arm and cold arms in an
actuator while an actuation voltage of 2 volts is applied between the hot and cold
arms (2 volts voltage is applied at the end of the hot arm when the ends of the
cold arms are grounded) 193]. The bold solid line is the temperature distribution
along the cold arm. the fine solid line is the temperature distribution along the
2 A suite of general-purpose mechanical simulation programs based on finite element method
from H ibbitt. Karlsson and Sorensen. Inc. 1080 Main Street. Pawtucket. R I 02860-4S47.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
68
Table 4.1: Summary of selected MUMP’s process parameters.
| layer
Poly 1
; Poly 2
! Gold
Thickness
2.0 ij.m
1.5 //m
0.5 gm
Sheet Resistance
9 Q /sq
19 Q /sq
0.06 Q /sq
hot arm. Since the temperature of hot arm is higher than that of cold arm. the
expansion of the hot arm is larger than these of the cold arms. This allows the
free end (the joint of the hot and cold arms) of the actuator to bend up or down
(see Figure 4.3 ib)). When actuation voltage is 2 volts, the displacement of the
actuator is about 2.7 /an without any load 93'.
Two or four actuators are connected to the top plate of the variable capacitor
to move it up and down. A flexure is introduced between actuators and the top
plate for mechanical and RF considerations (see Figure 4.2 for one design of the
flexures). In mechanical design, the flexure is used to reduce the stiffness of the
joint. In RF design, the flexure is used as a high inductance or a ground path in
different specific designs.
Design for the top plate includes determining its size and choosing material
layers. The size of the top plate is decided by RF performance, mechanical perfor­
mance and also fabrication. If the size is small, the capacitance may be too small
for specific applications: if the size is large, the warpage of the plate will be large
and the yield w ill be very small due to long time releasing. Balance between RF
and mechanical performance needs to be reached. From our experimental results.
MEMS plates with sizes around 200 to 300 gra have better performance.
In our design, the top plate employs all possible layers in the MUMP's pro­
cess. which consist of 0.5 gzm gold layer. 1.5 gtm polysilicon-1. 2.5 gm polysilicon-2
and 0.75 grm S iO i layer in between the 2 polysilicon layers to reduce the warpage
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
69
of the plate [89]. The S i0 2 layer is included to make the plate stiffer and reduce
the warpage of the top MEMS plate. A typical MEMS design for a series-mounted
capacitor is shown in Figure 4.4(b). Four actuators are connected to the top plate
in the design.
4.1.2
RF design
RF considerations for a variable RF capacitor design include: frequency
of operation, self-resonance frequency, maximum-to-minimum capacitance ratio
and quality-factor. Mounting configuration (series-mounted or shunt-mounted)
can also influence the capacitor geometry. Design specifications depend on the
intended applications of variable capacitors. In this chapter, series-mounted ca­
pacitors suitable for mounting in CPW’ lines are discussed.
The motivating application of the series-mounted capacitors is a tunable
bandpass filter in X-band frequency range, which is discussed later in the appli­
cation section. The possible application of the MEMS tunable bandpass filter
is in satellite communications, which commonly operate in either the C-band
1.4-6 GHzl or Ku-band ill-1 4 GHz) 94 . For the C-band operation, the capac­
itor is designed to have a self-resonance frequency of at least 10 to 14 GHz. A
capacitance tuning range of 5:1 with minimum capacitance value of 0.1 pF is ad­
equate. A series-mounted configuration, so that the capacitor can be mounted in
a half-wavelength transmission line resonator, is desirable. Keeping these charac­
teristics in mind, a parallel-plate configuration, which has been used extensively
as lumped-element MIM capacitors in MMICs. is selected for the series-mounted
MEMS tunable capacitor (see Figure 4.5).
The basic feature of the MEMS tunable capacitor is to use a micro-actuator
to move the top MEMS plate to change the airgap for varying the capacitance
value. The bottom plate is fixed on the alumina substrate and is a section of the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
center strip in a 50 Q CPW line. The capacitance value is approximately given by
the well-known parallel-plate formula. C=er e0A /d. in which A is the area of plates
and d is the airgap between two parallel plates. The size of plates is chosen to be
200 pm x 300 pm. which provides a capacitance of 0.137 pF for an airgap of 2
pm. The center strip of CPW is 203.2 pm wide to match the width of MEMS top
nlarp In order to get the ratio of Cmax/C mtn to be 5:1. the gap d should change
from 2 /mi to 0.4 pm. In this design, the dielectric material between two plates is
air and thus the dielectric loss at high frequencies is avoided. A 0.5 pm thick film
of gold is plated on the surface of the top plate to decrease the conductor loss.
Meanwhile, compared with MEMS capacitor designs published earlier "79. SO;,
the connect pad and beams have been introduced so RF signal can go in and
out without going through parts of actuators. Hencp. a lower RF loss and higher
Q-factor are expected.
In the initial design, the layout parameters are as follows: the gap in the
central strip is 80 pm. the size of connect pad is 200 pm x 200 pm on one side
of the gap. the number of connecting beam is 22. each beam is 00 pm x G pm
x 2 pm and consists of the 0.5 pm gold layer and the poly 2 layer. A 0.59 mm
CPW line length is added at the each end of capacitor and is used as pads for RF
probes for on-wafer microwave network analyzer measurements. Port 1 is at the
end of CPW closer to via and the port 2 is at the other end of CPW line. The
CPW ground planes are located with a spacing of 96.7 pm (calculated for 50 Q.
characteristic impedance of the CPW line) on each side of the center strip (see
Figure 4.5).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
71
M o v in g plate
F lexure
Cold arms
Hot arm
Figure 4.2: One design of electro-thermal actuators. The longer arm at the center
is the hot arm and the two shorter arms are the cold arms.
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72
500 •
400 •
300 200
—
Hoc Ann
—
Cold Arm
-
0
50
too
150
200
I. I , . m l
(a)
H o t & c o ld arm n g id ly c o n n e c te d a t th is en d .
C o ld a r m o n P o lv 2
H o t a r m o n P o l\ !
A rm s fix e d to s u b s tr a te at this en d .
(b)
Figure 4.3: (a) Temperature distributions along the hot arm and cold arm in an
actuator, (b) Deformation of the actuator after adding the currency through it.
Connect Pad
Connect Beam
Actuator
Actuator
Figure 4.4: A typical MEMS design for the series-mounted capacitor.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
73
Bonding pads
Figure 4.5: Simplified series-mounted MEMS tunable capacitor, (a) Longitudinal
side view, (b) top view.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
74
4.1.3
Fabrication
The initial airgap between the top MEMS plate and the surface of alumina
substrate is chosen to be 2 /urn in the series-mounted MEMS tunable capacitor
design. To support the MEMS structure and give the 2 /.im space, the indium
bumps are deposited on the alumina substrate underneath the connect pad and
bonding pads using left-off technology (see Figure 4.51. The indium bump under
the connect pad also plays a role as electrical path for RF signals. After indium
bumps are deposited, the MEMS on silicon is flip-chip bonded on the alumina
substrate.
The MEMS is transferred to the alumina substrate using flip-chip
assembly technolog}' 41'. Then, the whole assembly is ‘released’ in 49 percent
HF acid. A ll 5/O j layers are etched out to make MEMS active and to remove the
silicon substrate 91:. After the assembly is rinsed with methanol, a CO -2 dryer
is used for removing the moisture from the space in between MEMS and alumina
substrate ;92.. A photograph of the initial series-mounted capacitor assembly after
removing the silicon substrate is shown in Figure 4.G. In the figure, the MEMS
plate (in light grayi is connected to the connect pad 'the square in light gray)
through 22 connect beams. Eight actuators have been connected to the MEMS
plate to move the plate up and down. The bonding pads, which need to support
the MEMS. are isolated from RF ground by slots (in dark gray) in ground planes
of CPW on the alumina substrate.
4.2
R esults and analysis
4.2.1
M easured results and m odeling
Network analyzer HP (now Agilent Technologies) 8510 B and Cascade probes
(ACP50) have been used for RF measurements from 0.05 GHz to 40 GHz. The
multi-line TRL calibration standard set. which has been described in chapter 2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
75
is employed to cover this frequency range. A Zygo interference microscope3 has
been utilized to detect and measure the movements of actuators and top MEMS
plates. Distance between the surface of MEMS and the surface of alumina sub­
strate can be measured by the interference microscope directly. By abstracting
the thickness of the MEMS (the top layer of the capacitor), the value of airgap is
First, in order to verify the design of actuators, one actuator in chip version
(the MEMS actuator left on the silicon chip after releasing; is tested. The move­
ment of the free end of actuator versus the applied voltage is shown in Figure 4.7.
W ithout any load, the free end of the actuator with 250 /mi long hot arm and
200 /.im long cold arms can move 1.4 /mi with 3 volts voltage, which is close to
the simulation results from finite element method. Also the displacement shows
a good linearity with voltage.
The measured S-parameters of the initial series-mounted capacitor with a
top plate 200 /mi x 300 /mi are shown in Figure 4.S. As expected, the 5T (cross
marks) is close to 1.0 at low frequencies and decreases as frequency increases. FT
values (diamond marks) are dost1 to 0 and increases as the frequency increases.
Figure 4.S also shows results obtained from the modeling of the capacitor, which
is discussed later.
Based on understanding of the physics involved, this series-mounted capac­
itor is modeled as a "-circuit as shown in Figure 4.9 (right part). The variable
capacitor. C. is series to the transmission line, which is why the capacitor is called
a series-mounted capacitor. The parasitic inductance. L. is caused by the current
flow along the length of plates, suspension beams and the via. R is the resistance
3 A general purpose, three d im e n sio n a l, im a g in g surface s tru c tu re a n a lyzer, w h ic h use w h ite
lig h t in te rfe ro m e try to im age and measure th e m ic ro s tru c tu re a n d to p o g ra p h y o f surface in th re e
dim ensions w ith 0.1 n m re s o lu tio n . Z ygo C o . L a u re l B ro o k R oad. M id d le fie ld . C o n n e c tic u t
06455
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
due to the ohraie losses in series with the MEMS capacitor.
and Cg2 denote
the capacitances between the top plate (MEMS) to ground and the bottom plate
to ground, respectively. At high frequencies, the parasitic elements. L. R. Cgl and
Cgi. have more effect on RF performance of the capacitor because the impedance
of the capacitor (l/j^ 'C ) is lower at high frequencies.
Conversion of S-parameters to ^'-parameters provides a convenient method
for deriving an equivalent --network lumped-element model for the series-mounted
capacitor. Furthermore, modeling based on Y-parameters provides a good ap­
proach to find the precise value of resistance in the lumped-element model since the
level of the resonance peak is very sensitive to the loss of the capacitor. As shown
in Figure 4.9 (left part), admittances in the rr-network are given by ) \ = - Y 2!
and Yj = Y ; — Y2!. Yj = Yw — Y j,. The series admittance Y.
= -Y
ji
is modeled
as a series combination of a variable capacitance C. an inductance L. and a resis­
tance R. If_cC > 1 _L. the capacitance value can be calculated from the imagine
part of Y = -Y j: i computed from measured S-parameters) as 1, _clnn-l A T ). The
variance of
I i i k Y j ;
: with frequency is shown in Figure 4.10 and the C ( = L Y Itn(-
1 Yj; i ! as a function of frequency is shown in Figure 4.11. At low frequencies, the
C does not vary with frequency and is about 0.102 pF. Note that 1/Y Im i-1/Y j;)
becomes negative for frequencies greater than 31 GHz. This behavior shows that
there is a series inductance that causes this resonance effect. From the resonance
frequency, the initial value of L is found and R is calculated from the real part
of 1/Yi. Then the final values of C. L and R are obtained using an optimization
subroutine (built in the HP's MDS microwave network simulator (now called ADS
from Agilent Technologies)) by matching the measured values of-Y 21 with the val­
ues of these lumped elements over the frequency range of 0.5 to 40.0 GHz. The
resulting values are L =0.262 nH. C = 0.102 pF and R=6.2 Q. The comparison
of Im(Y2i) and Real(Y2i) obtained from model and measured S-parameters are
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
shown in Figures 4.10 and 4.12.
Values of Cgi and Cgi can be obtained directly from }•> and V3. respectively.
Cgi is 0.058 pF and Cg 2 is 0.093 pF. The real parts of V2 and 5 3 (about 2.3xl0 - 4
and 1.4xl0-3) can be ignored. A comparison of S-parameters from the complete
"-circuit model and the measured S-parameters is shown in Figure 4.8.
The
agreement between the measured S-parameters and the responses from the model
is good. Based on the model derived from measurements, the Q ( = —V7 ) value
is found to be 25G at
1
GHz for 0.102 pF. Figure 4.13 shows the Q-factor as a
function of frequency. The Q-factor decreases when frequency increase because Q
is proportional to
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
78
Figure 4.6: Photograph of a series-mounted capacitor assembly after removing
silicon.
E
<
U
£
C
i.
o
1 .5
V o lta g e IV o L zs /
3 .;
Figure 4.7: Movement of the free end of a electro-thermal actuator as a function
of applied voltage.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
79
-20
-30
Z
-40
modeling Si 1
modeling S21
+ Meas. S11
o Meas. S21
•50
i
-60 J—
---------------------------------------------------------------------------------------------- _J
0
10
20
30
40
50
Frequency GHz)
Figure 4.S: Comparison of the measured and modeling S-parameters of the seriesmounted MEMS tunable capacitors.
* . 'V 'V
---------------------------—
»
;______ c
—
v:='j ii-y:;
V
i
<
~____________ n i l ____
•
»
f __________ _
,
i
4
*
i
'
Y3«Yt:*Y;i
V
c$:
v
~
Figure 4.9: Lumped-element model of MEMS tunable series-mounted capacitors
and its relationship to Y-parameters.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
80
M o d e iin c
.
0
4
0
: e - ; o
4 £ . - ; ( •
r requencv i H z ■
Figure 4.10: Comparison of the modeling response and the measured In d lC ) of
the series-mounted MEMS capacitor.
2. 2:
Frequency <GH:'
4C
Figure 4.11: Capacitance. C. of the series-mounted capacitor as a function of
frequency.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
81
0 0
•oo;
•0 Oo
•0
•<> : -
M o vi e lin
(I
L 0
•j 0
-i E
J
0
Frejucnc> ' H i '
Figure 4.12: Compari.son of the modeling results and the measured real(Fji) of
the series-mounted MEMS capacitor.
?rscusscv(GHz)
Figure 4.13: Q-factor of the series-mounted MEMS capacitor as a function of
frequency.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
82
4.2.2
Sim ulation of tunable MEMS capacitors and analysis
The variable MEMS capacitor has been simulated using HP-Momentum4
[97; for different airgaps to investigate the tuning of the MEMS capacitor. The
structure and dimensions of the MEMS capacitor used in simulation are the same
as those used in measurements except that the top plate of capacitor is taken as
just a 0.5 /mi gold layer without any polysilicon layer and actuators are removed
to simplify the RF simulations.
Simulated S-parameters of capacitors with different airgaps are shown in
Figure 4.14. As we expected, the S-parameters show that capacitance increases
while the airgap decreases. Again, the S-parameters have been transformed to
Y-parameters to drive rhe lumped-element model. The values of the elements in
the model are summarized in Table 4.2 for different airgaps.
•
S21 Q Sun
X
S 2 ia n
— S11 4un
*
0
5
10
15
2
0
2
5
X
3
6
4
321 4un
0
Frequency (Gtt)
Figure 4.14: Simulation results (Sn and So!) of the MEMS series-mounted tunable
capacitor for different airgaps
4 E M field planner simulator based on the Method of Moments from HP-EEsof (Santa Rosa.
C A ). Edition 4. March 1996. Now H P is called Agilent Technologies.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
83
Table 4.2: \ allies of elements in lumped-element model based on simulation results
for the series-mounted MEMS capacitor with different airgaps.
; Airgap(/im)
;
0.5
i
1
2
4
L(nH)
0.21
0.21
0.216
0.22
C(pF)
1.20
0.63
0.314
0.177
|
|
I
;
!
From Table 4.2.J capacitance changes from 0.177 pF to 1.2 pF when airgap
decreases from 4 to 0.5 /mi. Simulation results predict that the ratio of Cma~,'Cmtn
is about 4:1 for airgap from 4 to 0.5 /mi. The capacitance value of the capacitor
with 2 /mi airgap is larger than that obtained from measured results. This is
because the warpage in the top plate of the capacitor increases the effective airgap
and thus decreases the capacitance. The warpage of the MEMS plate is about
1 /mi. Note that the inductance of the capacitor is close to the value obtained
from measured results. The variation of the airgap does not affect L significantlv
and the inductance values are almost the same for different airgaps. W hen the
top plate moves down, the capacitance increases and the resonance frequencies
decrease. For 0.5 /mi airgap. the resonance frequency is about 20 GHz. So the
tunable capacitor can be used up to 15 GHz.
J R is not shown in the table because loss in simulation is much lower than real case.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
84
4.3
O ptim ization o f series-m ounted capacitors
Self-resonance frequencies and Q-factors of series-mounted MEMS tunable
capacitors are affected by several factors, which include gap in CPW. connecting
pads and beams, thickness of gold layer and actuators. In this section, these
factors are investigated one by one in detail to improve RF performance of the
series-mounted MEMS capacitors.
4.3.1
Gap in C P W
In the series-mounted MEMS tunable capacitor, a gap is introduced in the
center strip of C'PW’ for incorporating the series-mounted capacitor. The effect of
the gap in CPW on RF performance is characterized by using EM simulation (HPMumentum). Series-mounted capacitors with different widths of gap in CPW have
been simulated. The gap is chosen to be 30. 40. 50. 00. SO and 100 /mi. Airgap
is 1 //m. Other parameters are maintained as those used in the previous section.
Simulated S-parameters are shown in Figure 4.15. Note that all S-parameters are
similar at low frequencies and minimally different at high frequencies, which may
be because the self-resonance frequencies are different due to the different gaps.
Transforming S-parameters to Y-paraineters. the series capacitances in the MEMS
capacitors are calculated from Y-parameters for gap 30 //m to 100 //m (see Figure
4.16). A ll capacitance of the series-mounted capacitors are very close and about
0.63 pF at 3.7 GHz. But the self-resonance frequency increases when the size
of gap in CPW increases because the total length of the MEMS plate increases.
However, the change is small and increase about 6 percent when the size of gap
in CPW increases from 30 /im to 100 //m. When airgap is larger, the smaller gap
(about 30 (im) in CPW line w ill lim it the lowest value of capacitance (0.0188 pF).
Considering the alignment accuracy during the flip-chip bonding process, the 80
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
85
Table 4.3: Dimensions and number of beams in different simulation structures.
Width of beam i/rm)
i
; case 1
6
: case 2
10
! case 3
10
Length of beam (gm) j Number of beam
80
!
21
;
80
:
5
80
3
I
//m gap in the initial design is kept.
4.3.2
Connect pad and beams
In the structure of the series-mounted capacitor shown in Figure 4.5. the
connecting pad is required to let the RF signal in and out of the top plate. Beams,
which are introduced between the top of the via and the moving plate, are used
to reduce the stiffness of the upper plate. From an RF point of view, if the beam
is as wide as the top plate. RF performance will be optimal since resistance and
inductance introduced will be the minimum. Bur from a mechanical point of view,
if the beams are narrower, the connection is more flexible and the loading of the
actuators (because of the beams) will be smaller. Hence, a trade-off between RF
performance and mechanical performance has to be carried out in the optimization
process.
Beams: Figure 4.17 shows the structure used in HP-Momentum to investigate the
effect of beams' geometry on the capacitor performance. Dimensions and number
of beams used in the simulations are summarized in Table 4.3. The substrate
in all of these cases is the same and is shown in Figure 4.17 (b). Since in RF
measurements, a 5 mm quartz substrate is used to isolate CPW circuits from
the metal holder, the quartz substrate also is included in the simulation set-up.
A section of microstrip line is chosen for locating the ports at each end of the
"beams" configuration. A 1 /tm airgap between the "beam” structure and the
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86
alumina substrate is selected for simulation. Case 1 is for the initial design of
series-mounted capacitor shown in Figure 4.5.
Cases 2 and 3 are the designs
modified to improve the mechanical performance. Five beams (case 2) are shown
in Figure 4.17 (a). For case 3. two beams next to the center beam are removed.
The simulated S-parameters of the structure with different numbers of beams
are shown in Figure 4.18. As we expected, the case with 21 beams (each 6 gm
wide) has the best RF performance, the lowest insertion loss of 0.1 dB at 40 GHz.
However, the 21 beam configuration is too stiff to give enough displacement by
two thermal actuators. When the number of beams is three and five (each 10 gm
wide), insertion loss values are less than 0.5 dB at 20 GHz and return loss values
are -15 dB and -20 dB at 20 GHz for three and five beams, respectively. Since a
-20 dB return loss is required for most of the practical applications, the 5-beam
configuration is selected for the series-mounted capacitor to replace the 22 beams
to balance RF and mechanical performance.
Vertical Via Connection: Figure 4.19 shows the structure of the series-mounted
capacitor used in HP-momemum for the study of the vertical via effect.
The
quartz substrate and the metal holder are not included in this simulation because
alumina substrate, on which CPW circuits are fabricated, is thick enough (25 mil)
for CPW circuit and the effect of the quartz on RF performance of CPW circuits
can be ignored. S-parameters have been computed for the structure with different
sizes of the via connect pad. The Im ( l’i) of the structure w ith different sizes of
the pad are shown in Figure 4.20. Note that when the length of the pad reduces
from 200 fj.m to 50 fim. the resonance frequency increases from 19.43 GHz to 22.25
GHz for 2 ^m airgap. At low frequencies, these curves almost overlay together,
which means that the capacitance (0.314 pF) does not change when length of
the connecting pad changes. The inductance is calculated from the resonance
frequency and the capacitance for the capacitor ( jj = ^== ). The inductance
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value in the lumped-element model of the capacitor is reduced from 0.21 nH to
0.16 nH. Considering the alignment accuracy during the flip-chip bonding process,
the 100 /im long pad is used for the improved design.
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88
. /
J'.IT
-juancyiGK:
(b)
Figure 4.15: Simulated S-parameters of the series-mounted MEMS capacitor with
different widths of the gap in the center strip of CPW. The gap is changed from
40 /im to 100 /im. (a) 52i - (b) Su-
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89
o
r-j
!•
i'J
u
o
/>
•'.J
h
•1
J.
O
o
i
_. »
Frequency C-Hr
41.1
Figure 4.16: Series capacitances of the series-mounted MEMS capacitor for dif­
ferent widths of gap in the center strip of CPW. The gap is changed from 40 /tin
to 1 0 0 //m.
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90
Beam.-
i a)
( iolii Ijver 0 5 um ■
■
■-
—
. i
_
Air I um
Mumtna
,y.,.
|
i
.p ,
um
; ,
•
'V ,'- '—^
Quart.: * mm
Ground
Figure 4.17: Structure used for simulation of beam effect in HP-momentum. (a)
Top view, (b) side view with substrate layers.
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91
/ _
Figure 4.18: Simulation results for different number of beams. Solid line with
- r - f - r + (case 1 ) is for 2 1 beams (each beam 6 iim wide), solid line with xxxx (case
3) is for three beams (each beam 10 ^zm wide), and solid line (case 2) is for five
beams (each beam 1 0 /zm wide), which is chosen for the new design.
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92
Reference Planes
CPW' on aiimuma substrate
A irgap
M E M S plate;
Ahm unia substrate
gap ,
CPW'
Fiiiure 4.19: A series-mounted capacitor without actuators, which is used for
simulating the pad size effect in HP-momentum. L is the length of the connecting
pad. It is open air under the alumina substrate.
v.
" I
£
,
< 7 ? -
!
•
-------
f :i
.
\
.
U \ .
ii*.
\
o
*ri
r*
)
1• z
n
-------
.
I r
Frequency'.GK;,
1w..
Figure 4.20: Simulation results for the series-mounted capacitor w ith different
connecting pad lengths. Length of pad. L. is 200. 1 0 0 and 50 gm when keeping
other parameters same.
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93
4.3.3
Q-factor and gold layer thickness
The top MEMS plate in the series-mounted capacitor is made of polysilicon
1. polysilicon 2 and a gold layer on surface of polysilicon 2. The resistivity of the
polysilicon
1
and polysilicon 2 are 9 and 19 Q/square. respectively. Even though
there is a gold layer deposited on the surface of polysilicon
ause
uf
tlic Mcuida.ru
uf
2
. the thickness of
ML MF
s
process
90 .
In this section, rhe effect of the gold layer thickness on Q-factor of the capacitor
is snidied using rhe transmission line model for the surface impedance of the
multilayer metal.
The skin depth of a good conductor can he computed by rhe formula:
•)
(4.1)
where _ is the angle frequency. - is the conductivity of the conductor and // is the
permeability of free-space. Figure 4.21 shows the skin depth of gold as a function
nf frequency.
Notice that when frequency is below 20 GHz. the skin depth is
larger ii.-lo /nil. It means that EM wave , RF current'' will penetrate through the
increases due to the higher resistivity uf polysilicon.
For conductor loss calculation, the presence of imperfect conductors must be
taken into account. Surface resistance concept allows us to do this in a convenient
way. Consider a bulk good conductor, when a plane wave is normally incident
upon the conductor, most of it is reflected, and the power that is transmitted into
the conductor is dissipated as heat within a very short distance from the surface
(skin depth ds). Using Joule's law. the power can be computed [98]:
(4 .2 )
where
t] 0
is the wave impedance of free space, the
rj
is the wave impedance of the
I
I
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94
medium, which can be defined to relate the electric and magnetic fields:
n = J^ r
(4.3)
where - is the complex propagation constant. If the incident wave is a plane wave,
this impedance is the intrinsic impedance of the medium as well. If the medium
is a good conductor, the intrinsic impedance of the conductor simplifies to
n =
n- ~ J
i y ' - r
(4..4)
Since ;i C ;/0. for large conductivity, the equation 4.2 becomes:
P = X '^ ~
m). ;/-
(4.5)
/?. = —
i 4.(3)
rr.o,
where R, is the surface resistance of the conductor. For good conductors with
a great thickness much larger than skin depth), /w is small (0.014 H for copper
at 3 GHz'. However, for a conductor with a thickness less than its skin depth,
the above simpie equation is not applicable. In a mulrilaver-metal configuration,
in
which each layer is verythin, a transverse transmission
for calculation of thesurface
linemodel is needed
resistance. In this model, thesurfaceresistance of
the multilayer-metal can be found as the real part of the input impedance of rhe
several cascaded sections of transmission lines (see Figure 4.22) [95]. Using the
transmission model, the surface impedance of the MEMS plate are calculated and
shown in Figure 4.23.
Since the airgap is much smaller than the size of the capacitor, the seriesmounted capacitor can be considered to be a parallel plate capacitor. Q-factor
can be found from the surface resistance for a low-loss parallel-plate capacitor:
q
= rcZ
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(4‘ ()
95
Table 4.4: Resistance and Q-factor of multilayer metal with different thickness of
the gold layer.
0.4(/jm) : 0.5(/mi) I
R Q at 1 GHz
0.105 I 0.0S67 !
R Q at 1 0 GHz
0.105
0.0882 j
Q at 1 GHz
1514
1834
Q at 1 0 GHz ; 151.4
180.3
1 (/mi)
0.0501
0.0519
3136
306.4
where. R is the resistance due to the conductor loss and calculated from
where I is the length of the conductor and \Y is the width of the conductor. The
values of R and Q-factor for various thickness of the gold layer on polysilicon are
shown in Table 4.4 for
x 300
fin
1
pF parallel-plate capacitor, which plate sizes are
20 0
/mi
l and the airgap is 0.53 /mi. If the thickness of the gold layer on the
polysilicon plate in the capacitor increases from 0.5 /mi to
1
/an. the Q-factor of
the MEMS capacitor will increase from ISO to 306 for 1 pF at
10
GHz. However,
it may be noted that the measured R of the series-mounted capacitor is about
6.4 H and is much larger than the calculated R due to conductor loss from the
surface impedance (0.0S67 H for 0.5 /mi gold layer on polysilicon). This means
that the additional losses contributed by the vertical interconnect via and the
beams connecting the movable plates to the via are large and play a dominant
role in the total loss of the capacitor. Thus, the improvement in Q-factor by
increasing thickness of the gold layer may not be in the same proportion as shown
in Table 4.4.
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96
3
20
30
Freausru'x G H
i >
Figure 4.21: Skin depth of gold as a function of frequency.
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97
Gold
Air
!
I
Polysilicon
:
Air
i
Zin
dg
J Z
Zin
'
>
Figure 4.22: Transmission line model for the surface resistance of the multilayer
metal, dg is the thickness of the gold layer, d is the thickness of polysilicon layer,
and Z is the impedance of the air. The real part of Zm gives the surface resistance.
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98
Figure 4.23: Surface impedance of the multilayer metal with different thickness of
gold layer versus different frequencies. The solid line with mark x is for 40 GHz.
and the solid line with mark A is for 30 GHz. the solid line with mark square is
for 20 GHz. the solid line is for 1 GHz.
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99
4.3.4
Effect o f actuators on RF perform ance
Since the top plate, a part of the MEMS tunable capacitor, is connected to
actuators. RF performance of the capacitor is affected by these actuators. The
actuator can be modeled as a inductor series with a resistor.
An attempt is
made to separate resistance and inductance effects by simulating two different
actuator set-ups in HP-.Momentum simulation. This effect of the inductor can be
characterized by comparing simulation results of the MEMS capacitor with and
without actuators, which employs a 0.5 /zm gold layer. The effect of actuator with
resistance can be characterized by using simulations with actuators made of a
2
/zm polysilicon layer.
First, the actuator is taken as a 0.5 /zm thick gold strip for simplicity of
simulations to characterize the effect of the inductor. Series-mounted capacitors
with different widths of strips have been simulated (see Figure 4.24i. One end of
the strip is connected to the top plate while the other end is grounded. Width
of the strip is Id /zm and the airgap is 1 /zm. A ll other dimensions are the same
as those used in section 4.2.2. Simulated S-parameters are shown in Figure 4.25.
Note that simulation results of the series-mounted capacitor with grounded strips
are significantly different from those for the capacitor without any actuators. The
capacitances of these series-mounted capacitors with and without the actuator
strips, calculated from S-parameters. show that grounded strips decrease the ca­
pacitance of the series-mounted capacitor significantly, from 0.587 pF to 0.175 pF
for 1 /zm airgap (see Figure 4.26). This reduces tuning ratios of series-mounted
capacitors, although resonance frequencies increase. Similar results are obtained
for different widths of strips (5 /zm) and a strip with a right angle bend.
The grounded strips connected to series-mounted capacitor affect RF per­
formance by two factors: the first is a strip inductance and the other one is a
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100
ground path for current. In order to separate these two effects and find out which
is dominant, the series-mounted capacitor is simulated in two different configu­
rations: ( 1 ) with the strip connected to the via but isolated from ground by a
slot in the ground metal plane and (2 ) with a open-end strip without any via (see
Figure 4.27). Figure 4.28 shows these simulation results. Results for these two
cases are identical and similar rn that for rim capacitor without accouters. This
means that the grounding of actuators is the key point for RF performance of
the series-mounted capacitor and isolation methods do not make difference*. The
luinped-element model of the series-mounted capacitor is modified to include the
inductance of the actuators (see Figure 4.29 la)). From the model, it is very clear
to see that actuator strips work as inductance, which is connected the capacitor
to ground planes directly. Hence, isolating the actuator from ground planes is
recommended for series-mounted MEMS capacitor designs.
However, in the layout of the series-mounted tunable capacitor with MEMS.
the space between the bonding pads limits dimensions of the CPU', especially
for ground planes. In order to increase the widths of the ground planes, some
bonding pads of the actuator will need to be bonded on the ground planes directly.
Also for improved thermal management, the cold arms of the actuator should be
connected to a bigger metal plane. The structure of the series-mounted capacitor
with actuators partially grounded is shown in Figure 4.31. The actuator is made
of three strips, each of which is
10
/zm wide. The center strip is the hot arm
and isolated from the ground plane. Two other strips (cold arms) are grounded.
Hence, the total width of the two strips which are grounded is 20 /zm. Simulation
results from HP-Momentum are shown in Figure 4.32. For comparison, the Sparameters of the series-mounted capacitor with two strips, which width of each
strip is 20 /zm. also are shown in the figure. As was expected, the two sets of
S-parameters is very close. It means that only these strips which are grounded
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101
affect the RF performance of the series-mounted MEMS capacitor.
Strips in the simulation mentioned above are taken as a 0.5 pm thick gold
layer. Thus, the effect of the resistance is not included because the resistance of
the strip made of 0.5 pm thick gold layer (around 1.2 Q for 200 pm long and 10
pm wide strip) is much smaller that of strips made of 1.5 pm thick polysilicon
i around 3S0 Q for 200 pm long and
10
f/m wid.p ^trip 1 In the MEMS tunable
capacitors, the polysilicon is the structure material. Hence the lumped-element
model of the series-mounted capacitor with the actuator effect should include a
resistor ft,, (see Figure 4.29 lb)). For characterization of the effect of resistance,
the series-mounted MEMS capacitors with actuators have been simulated again
with two 1.5 pm thick polysilicon strips, which are 5 pm in width. The simulated
results are shown in Figure 4.33. S-parameters of the case without actuators and
with 0.5 //m thick goid strips (5 pm wide) also are included in the figure for
comparison. We note that the performance of the series-mounted capacitor with
the 1.5 pm thick polysilicon strips are close to these of case without actuators.
Therefore, the partial isolation can be used for the series-mounted capacitor design
when considering the high resistance of the polysilicon actuators.
From the lumped-element
m odel
with actuators, this point can
be
shown
more clearly. Based on physical understanding, the electro-thermal actuator can
be modeled as an inductor series with a resistor and is shunt connected to the
original model (see Figure 4.29). Note that the model is not a simply --circuit
but two --circuits that are series connected together (shown at the left part in
Figure 4.30).
represents the admittance of actuators and V2 is the tunable
capacitance. Since the Y-parameters from the measured S-parameters is respect
with the whole circuit, the two tr-circuit needs to be transformed to an equivalent
--circuit (see the right part in Figure 4.30) to calculate the values of these element
from Y-parameters. From the definition of the Y matrix and Kirchhoff's law. Y-
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102
parameter of the equivalent --circuits can be calculated from I j . Y2 . I 3 . I 4 and
r 3.
v ,, =
(4,9)
1 1 T
i 4 ~
1 5
v 12 = IV = - I V = A,
-1
V-v. =
*4
- '• ! - I
) 1 —
* .r)
3
(4.10)
(4.11)
24 ~
IV is the most concern parameter in our case, substitute inductance, capacitance,
and resistance into V . l j . and 1’-, (see Figure 4.29 (bl). IV. ran lje written ;ls :
~ j-C
h i = ------------------- -------------- 5 - 7 -7 1 - i7? - j ^ L )( j~ C ' -
(4.12)
where Ra and L,. due to actuators are just included in the last term of the denom­
inator. If /?,. and L,. are much lamer than R ami L. respectively,
then ft.,
. — '"V
1
can be ignored. Equation 4.12 will be reduced to:
= 1-
1
l4' 13'
where no actuator effect is shown off. This means that if resistance and induc­
tance of actuators are very large, these actuators can be taken as a RF choke
and the effect of actuators can be ignored. Hence, the variable capacitance and
resistance of the tunable capacitor can be calculated from Y-parameters just as
before without considering the effect of actuators.
!
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103
R eferen ce P lanes
C P W un ahm um a substrate
M EM S piate
A lim una substrate
C P W on alim una substrate
►
tnp
Figure 4.24: Structure of the series-mounted capacitors with strips for simulation.
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104
Figure 4.25: Simulated S-parameters of MEMS series-mounted capacitors with
actuators, which is simplified as a strip. The width of strips is 10
and 5 /urn.
5 n of capacitor without actuators is also included for comparison.
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105
-r
Figure 4.26: Comparison of capacitances for series-mounted capacitors with and
without strips.
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106
C P W on aiimuna substrate
Open hole in the ground plane
MEMS plate
fcl
c .-a —
g
Vias
i a)
I
C P W on
a iim u n a s u b s tra te
MEMS plate
lb )
Figure 4.27: Structures of series-mounted capacitors w ith strips that are isolated
from ground (a) and are left open (b).
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107
Figure 4.28: S-parameters of the series-mounted capacitor with strips but no
grounding (no via is added and via is isolated from the ground plane). S-parameter
of series-mounted capacitor without actuator also is included for comparison.
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108
(bi
Figure 4.29: Lumped-element model of the MEMS series-mounted capacitor in­
cluding the effect of actuators. La and Ra are the inductance and resistance due
to actuators, (a) Model with inductance La. (b) model with inductance La and
resistance Ra.
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109
v.
F ig u re 4 . ‘30: T w o series r - c ir c u it s a n d th e e q u iv a le n t rr -rirc u it
M E .\{S plate
SjoLin ground plane
/
CPW on alimuna substrate
Figure 4.31: Structure of the series-mounted capacitor w ith strips that are par­
tially grounded.
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110
Figure 4.32: S-parameters of the series-mounted capacitor with strips that are
partially grounded.
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Ill
v .;-
3;
.;
c
Figure 4.33: Comparison of S-parameters of the series-mounted capacitor with 1.5
thick polysilicon strips and with 0.5 /im thick gold strips. W idth of the strip
is 5 fj.m.
1
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112
4.3.5
Improved series-m ounted MEM S tunable capacitor design
Based on discussions in the previous section, a new version of the series-
mounted capacitor has been designed reflecting a trade off between RF and me­
chanical performance. Figure 4.34 shows a photograph of the new version of the
series-mounted capacitor. Compared with the old design, the connect pad area
ana via are reduced from 20(J pm x 200 pm to 100 pm x 200 pm. The number of
connecting beams is reduced from
increases from
6
21
to 5 and the width of each of these beams
to 10 pm. In order to reduce the effect of actuators further, only
two new actuators are used to drive the top MEMS plate. This becomes possible
because the stiffness of the beams reduces significantly when only five beams are
used. Meanwhile, the hot arm pad (the center one) is isolated from ground planes.
The pads of cold arms are contacted to RF ground planes to increase the width
of the ground plane for CPW and more heat can be conducted through the RF
ground to make cold arms cold. The measurement results from Zygo interference
microscope show the new capacitor design works very well. The airgap between
the top plate and the surface of the substrate changes from 2.27 //in to 0.67 pm
when bias voltage increases from
0
to 2.5 volts /see Figure 4.35i.
Figure 4.36 shows the measured S-parameters of the new series-mounted
capacitor for different bias voltages. There is a noticeable change in S-parameters
when actuation voltage changes. As before. S-parameters have been transformed
to Y-parameters to derive the "-circuit model for the series-mounted capacitors.
The capacitances of the series-mounted capacitor is calculated from Yi =-}•>; for
different bias voltages. Figure 4.37 shows the imaginary and real parts of -Yj i .
Capacitance as a function of frequency is shown in Figure 4.3S for different
bias voltages. When the voltage increases, the capacitance of the series-mounted
capacitor increases as was expected. The capacitance of the tunable capacitor
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.34: P hoto o f the im proved .series-mounted c a p a cito r
changes from 0.331 pF to 0.891 pF when the bias voltage increases from
0
to 2.5
volts. The tuning ratio is about 2.7:1. The measured capacitance with an airgap
of 2.27 pm has been compared with simulation with an airgap of 2 /mi in Figure
4.39. There is a very good agreement. Since the simulation results assume very
little loss, the resonance peak for the simulation results is much sharper.
The resonance frequency and Q-factor can be found from M value as well.
When the circuit is at the resonance frequency, the inductive part in the cir­
cuit admittance cancels the capacitive part.
At this point. imag(T1)=0 and
real(T 1 )= l/R . Hence, the frequency at the point with zero imaginary part of
i'i is the resonance frequency. Measurements show that the resonance frequency
for 2.5 volts bias is the lowest and is about 14.03 GHz. Therefore, the tunable
capacitor can be used at 10 GHz. Resistance. R. of the capacitor is 4.03 H for 2.5
volts bias. Q-factor can be calculated from resistance using formula Q — -T— or
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114
Table 4.5: Parameters of the improved series-mounted capacitors for different bias
voltages.
j
j
i
I
1
V o lta g e • V i
0 .0
i
2.25
2.5
!
:
A t r g & p ijim
2.27
1.03
0.67
!
i
!
!
Mea. C;pF> Cal. CpF ; R(H)
0.331
0.233
4.32 : 21.42
0.16
i
i
oo
0.530 ; 0.516 1 “t.-- | 19.7S | 0 . 1 2
0.8S1
0.793 ! 4.05
14.03 ! 0.14
:
; G H i i
;
|
;
(
|
L i n h
Qa: GH: !
Ill
71
44
:
can be found from the y- (= Z\) as:
q
=
„
.
I I L
^ ,
I
(4.141
0-factor of the tunable capacitor for different bias voltages are shown in Figure
4.40. Q-factor of the capacitor is approximately 10S for 0.331 pF and 44 for
0.S81 pF at
1
GHz. Using the error transform formula*1 . the error of R due to
measurement errors of S-parameters can be computed. In our measurement using
HPS510. the measurement error of S-parameter is about
0
.0 1 . then the error of R
is about 0.3 H. Hence, the minimum Q-factor is 42 for a capacitance of 0.SS1 at 1
GHz. Compared to the initial design. R. loss uf the capacitor. lias been reduced
from 6.2 H to about 4.1 H. Thus, for the same capacitance, the Q-factor increases
by 50 %. These parameters of the tunable series-mounted capacitor are listed in
Table 4.5.
6 If y is a function of x i . x 2. ■■■ and x m. y = f { x i . x 2. ■■-x m) and the maximum errors of
x i . x 2 . ■■■ and x m are A x i . Axo. - • • A x m. Then the maximum error of v is as following.
Ay = | j £ | A x l + j | 4 | A x 2 + . . - - j ^
A x m.
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115
2 5
Voliaae iVi
Figure 4.35: Measured the change of the airgap) as a function of voltage using
Zygo.
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116
1
Figure 4.36: Measured S-parameters of the improved series-mounted capacitor for
different bias voltages, (a) Sn . (b) S2 1 . Solid line with x is for 0 volt bias, solid
line is for 2.5 volts bias, and solid line with — is for 2.5 volts bias.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ill
Figure 4.37: -V^i of the series-mounted capacitor, which calculated from measured
S-parameters. (a) Imaginary part of
(b) real pan of I I . Solid line with x is
for 0 volt bias, solid line is for 2.5 volts bias, and solid line with -r is for 2.5 volts
bias.
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118
I
Figure 4.38: Capacitance of the series-mounted capacitor, which calculated from
measured S-parameters. Solid line with x is for 0 volt bias, solid line is for 2.3
volts bias, and solid line with — is for 2.5 volts bias.
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119
Figure 4.39: Comparison of capacitances of the series-mounted capacitor, which
calculated from measured and simulated S-parameters. The airgap is 2.27 /tm
with 0 volt bias.
O
r
Figure 4.40: Q-factor of the improved series-mounted capacitor for different bias
voltages. Bold solid line with x is for 0 volt bias, solid line is 2.25 volts bias, dot
line is for 2.5 volts bias.
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120
4.4
M EM S tunable bandpass filter
Generally, varactors are employed in tunable bandpass filter designs, as tun­
able capacitors to tune center frequencies or bandwidths. Since varactors are lossy
at high frequencies, the insertion losses of these tunable bandpass filters are high.
To compensate the loss due to varactors. active tunable bandpass filters using
FETs have been reported 43. 44’ 45’ . The insertion loss of the active tunable
bandpass filter can be near
0
: but. there are high intermodulation distortions
(IMD) in the active tunable filters due to FETs and varactors.
In this section, we report an application of the series-mounted MEMS tun­
able capacitors in tunable bandpass filters. The MEMS tunable capacitors, which
we describe in the previous sections, replace varactors and are integrated at the
centers of half-wavelength resonators in the bandpass filter to tune the center
frequency. The MEMS tunable bandpass filter replaces varactors with high-Q
MEMS tunable capacitors and is expected to give the lower insertion loss and
IMD.
Figure 4.41: Substrate layout of a MEMS tunable bandpass filter with bias circuit.
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121
4.4.1
Bandpass filter design
The insertion loss method [32] is used for the filter design. The ripple level
is selected to be 0.5 dB. The design values of the elements in one pole bandpass
filter are shown in Table 4.6 for 10 GHz center frequency and 5 9c bandwidth.
The simulation results using MDS for the one-section filter are shown in Figure
4.42.
For the physical layout of the bandpass filter, both gap and inrerdigital
capacitors in CPW configuration are explored for realizing capacitor Cn in the
bandpass filter design.
The gap capacitor in CPW is modeled as a --circuit.
The dimensions of CPW are kept the same as these used in the series-mounted
MEMS capacitor design: the center strip is 203 /mi wide and gaps are 96.7 /mi
each. HP-.Momentum has been used to simulate the gap capacitor with different
gaps to calculate the capacitance of the gap capacitor. The values of the elements
in the rr-circuit for the gap capacitor at S GHz are shown in Table 4.7. From
the table, we note that it is hard to get capacitance larger than 0.02 pF in gap
capacitor configurations when considering the fabrication process in our laboratory
! minimum gap can be fabricated is 35 //mi. In order to get the capacitance of
0.12 pF. the interdigital capacitance (Figure 4.43) is used for the bandpass filter
design. The dimensions of the interdigital capacitor are shown in Figure 4.43.
Again, the interdigital capacitor is integrated with 50 9. CPW with a 203.2 //m
wide center strip and 96.7 /mi gaps on alumina substrate. Table 4.8 shows values
of the capacitance. When L is 570 //m. capacitance of the interdigital capacitor
is about 0.1 pF. which is chosen for the filter design.
The pattern of one pole bandpass filter is shown in Figure 4.41. Pads and
bias circuits for the MEMS tunable capacitor also are included, which are discussed
later on. The physical layout has been simulation by using HP-Momentum. The
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122
Table 4.6: Values of the elements for 1-section bandpass filters.
!
I
n
1
2
gn : Zq Jn \ Bn (xlO
0.6986 i 0.3353 i
7.555
1.000 ! 0.3353 '
7.555
simulated insertion loss is shown in Figure
C„(pF)
3 )
1
i
0 .1 2 0 2
:
0 .1 2 0 2
6
142.9
—
1
i
.12. Compared to the results from
the lumped-element model using MDS. the bandwidth is smaller because of the
smaller coupling capacitance and the additional parasitic capacitances.
4.4.2
O ne-pole M EM S tunable bandpass filter
The MEMS is integrated to the center of the resonator to tune the center
frequency of the bandpass filter. Figure 4.41 shows the layout of bandpass with
MEMS. The bandpass filter has been simulated again with MEMS. The HPMomentum simulation results for different airgaps in the MEMS capacitor are
shown in Figure 4.44. We notice that the center frequency changes from 10.6
GHz to 13.6 GHz as airgap changes from 0.5 pm to 4 pm. Bandwidths are almost
the same. The insertion loss of filter is lower than that of filter without MEMS
due to the loss of the MEMS capacitor.
Table 4.7: Values of the elements in the equivalent tr-circuit of gap capacitors in
CPW.
gap(pm)
45
40
35
30
25
C(pF)
0.016
0.0168
0.0177
0.0188
0 .0 2 0 1
Ci and Oj (pF)
0.0026
0.0023
0.0019
0.0017
0.0013
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123
Table 4.8: Values of the elements in the equivalent "-circuit of interdigital capac­
itors in CPW.
Length(^m) 1 C’(pF) : Ci (pF) : Co (PF) :
570
; 0.0999 0.0219 : 0.0696
500
■0.0937 0.0213
0.0716
400
0.0695 0.0198
0.0537
300
0.0545 0.01C7
0.0417
300
0.0545 0.01G7
U.0417
2 2 0
0.0433 0.0139
0.033S
un
>
-
5
——
-
frequency (C-i::)
15
Figure 4.42: Simulation results of one-section bandpass filter. Solid line is the
result obtained from network simulator (MDS) using the design values. Dot line
is the result from the EM simulation (HP-Momentum) with the layout using the
interdigital capacitors.
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Figurp 4.43: The interdigital capacitor in CPW. a = 30 /mi. b = 55 /mi. W = 200
/mi. and L changes from 220 /mi to 570 /mi for different capacitances.
O
'
GO
j
frequ ency(G H : i
1:
Figure 4.44: Simulation results of the one pole bandpass filter. Center frequency
of the tunable bandpass filter changes from 10.6 to 13.6 GHz as the airgap in the
MEMS capacitor changes from 0.5 /mi. 1 //m. 2 /mi. 3 gm to 4 /mi (from left to
right)
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4.5
Remarks
A series-mounted MEMS tunable capacitor in CPW configuration has been
designed and measured up to 40 GHz. The Q-factor is
1 0
S at
1
GHz for a 0.331
pF capacitance value. The tuning ratio [Cmax/ C min) is about 2.7:1 and the res­
onance frequency is about 21 GHz to 14 GHz. when bias changed from 0 to 2.5
volts. A lumped-element model has been developed for the series-mounted MEMS
tunable capacitors. Considerations that affect RF performance of such capacitors
are discussed and some useful design guidelines have been derived. These may be
summarized as follows.
( 1 ) Gold layer thickness: In the series-mounted capacitor design, the losses due
to the connecting pad and beams are dominant. When the loss of connecting pad
and beams has been reduced, the conductor loss would lim it the Q-factor. If the
thickness of gold layer increases from 0.5 /mi to
1
/mi. Q-factor will be able to be
increase about 50/i.
(2) Vertical connect via: In our case, the vertical connect via is made of deposited
indium. It limits Q-factors in our capacitors because of its high resistance ibad
contact). Gold plated bumps will reduce the contact resistance and yield a higher
Q-factor. Meanwhile, the length of connect via (pad) along the direction of wave
propagation affects the self-resonance frequency of the capacitor. By reducing the
length of connect via from
2 0 0
gm to
100
/mi. the resonance frequency increased
from 19.43 GHz to 20.5 GHz (for a capacitance of 0.314 pF).
(3) Connect beams: Connect beams affect both of RF and mechanical perfor­
mance. When the number of connect beams is larger, the RF performance is
better, but the stiffness of connect beams is higher and thus the load on actuators
increases. For the same actuator, the displacement of the actuator w ill be smaller
and the capacitor tuning ratio w ill be lower. Therefore, the design rule is to use
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126
the fewest number of beams as possible for meeting the general requirement of RF
performance (-20 dB return loss) and. at the same time, to obtain the reasonable
mechanical load for actuators. Five 10 fim wide and 80 pm long beams work well
in our design.
(4) Actuator effect: Actuator effect in the series-mounted capacitor is significant.
Icrtlatmg actuators from ground planes is recommended. If it is not possible in
the circuit layout, partial isolation between actuators and ground planes can be
used, if the actuator is designed with higher inductance and or resistance as a RF
choke. When an actuator is not grounded, its effect can be ignored.
(5) Actuator inductance: An actual actuator can be modeled as an equivalent
strip with equal inductance.
M ultistrip can be modeled as parallel inductors.
The resistance of the actuator can be computed using DC resistance formula.
l
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Chapter 5
Shunt-m ounted M EM S Tunable C apacitor Design
The series-mounted capacitor discussed in Chapter 4 is one of the commonly
used capacitor configurations in RF and microwave circuits. The other equally
useful configuration is a capacitor mounted in shunt across a transmission line.
In this chapter, a shunt-mounted MEMS tunable capacitor in CPW configuration
is developed and investigated. It overcomes the drawbacks in the series-mounted
capacitor design and provides higher Q-factor and higher self-resonance frequency.
In this research, two shunt-mounted MEMS tunabie capacitors have been imple­
mented.
5.1
5.1.1
D esign o f shunted-m ounted capacitors
RF design
Figure 5.1 shows the conceptual design layout of the shunt-mounted MEMS
tunable capacitor. A MEMS plate bridges over CPW to distribute the EM field
while the airgap is small. Electro-thermal actuators hold the MEMS plate and
move it up and down to change the airgap and vary the capacitance. Based on
qualitative understanding of the field distribution, the shunt-mounted capacitor is
modeled as a T-circuit (see Figure 5.2 (a)). Where Cn is the capacitance between
the top MEMS plate and the center strip of CPW on alumina substrate. Ci 2
and C 1 3 are capacitances between the top MEMS plate and the ground planes of
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128
CPW at each side of the MEMS plate (Note that the MEMS plate covers a part of
ground plane at each side). When the airgap changes, the values of all these three
capacitors vary. The resulting capacitance is in shunt with the transmission line.
This is why it is called as a shunt-mounted capacitor. R denotes the resistance
because of the losses. !•> and
are the fringing inductances due to the length of
the MEMS plate along the CP1\ line anu the v^i n iransmissiuii unt* undciiieaiii.
L\\ and L v> denote the parasitic inductances due to the length of the top plate
along the direction perpendicular to the CPW transmission line.
Since these
shunt-mounted MEMS tunable capacitors have a symmetrical configuration.
w ill be equal to
£ .3 .
I;-. = L u and CM = CM
In the first design of the shunt-mounted capacitor, the dimensions of the
30 o CPW line
011
25 mil alumina substrate are the same as those for the series-
mounted capacitors. The CPW center strip is 203.2 /an wide arid the gaps are 9G.7
/tm. The size of plate is selected to be 200 /nil x GOO /mi. so the MEMS plate covers
the CPW ground planes about
100
/mi at each side isee Figure 5.1). The layout
is based on the following consideration. As discussed before, the shunt capacitor
between the MEMS plate and CPW metal layer consists of three capacitors: one
capacitor (CM) between the MEMS plate and the center strip of CPW. and two
capacitors (C^j and CM) between the MEMS plate and the ground planes at each
side of the center strip. The total shunt capacitance (C) is CM series with the
capacitors (C 12 — C i3) (see Figure 5.2 (a)).
1
C
1
1
Cu ' C l 2 -rC l 3
^
C n (C i 2 -f- Ci3)
c = or 11 - T■ Lr 1 2 T~ rc 13'
(5.1)
( o -2 )
The maximum value of C can be obtained only when keeping CM = CM + CM.
which means keeping IP =
2
HM In the first design of the shunt-mounted MEMS
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129
tunable capacitor. W is designed to be 200 ^m.
is 100 /urn. A 0.59 mm CPW
section is added to each end of the CPW line as the pads for on-wafer probes.
These additional lines are de-embedded during the calibration processes. DC bias
circuits have been isolated from RF grounds by using slots on the ground planes
(see Figure 5.1).
5.1.2
M echanical design and fabrication
Electro-thermal actuators used in the shunt-mounted capacitor are identical
to those used in the series-mounted MEMS tunable capacitors. In the first design,
eight actuators are connected to the top MEMS plate on each side to support the
plate and move it up and down.
MEMSs to the alumina substrate.
Again, flip-chip technology is used to bond
The releasing and C’O-j drying processing
are identical to those in the processes of the series-mounted capacitors.
The
photograph of a final assembly for the first shunt-mounted capacitor design (after
removing the silicon substrate) is shown in Figure 5.3.
5.2
5.2.1
R esults and RF m odeling for the first design
M easured results and characterization
Network analyzer HP 8510 B and Cascade probes (ACP50) with the multi-
line TRL calibration standards have been used in RF measurement from 0.05
GHz to 40 GHz. The measured S-parameters of the shunt-mounted capacitor for
the first design are shown in Figure 5.4. The S-parameters show the behavior of
a shunt capacitor: when frequency increases. Sn increases and S2i decreases. In
order to understand the capacitor performance better, the S-parameters have been
transformed to Z-parameters leading to the T-network model shown in Figure 5.2
(a). In the shunt-mounted capacitor design. Z2= Z 3. they can be modeled as a
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series of an inductance and a resistance, which is mainly due to the current on
the top MEMS plate. Z\ in the lumped-element model can be simplified to a
series of capacitance C. inductance L and loss R (see Figure 5.2 (b )). C denotes
the total variable capacitance between the top plate and center strip, and two
ground planes (see Equation 5.4). L is total inductance ( =
of
rh p
MEMS plate and actuators (effects of the actuators
^ because
d ie d iscu ssed in
next
section). The values of capacitance. C and resistance. R. in the simplified model
can be calculated from Z-parameters.
(5.3)
(5.4)
-
I m
a
g
\ Z
x ) '
R = Rt a l ( Z \)
When ~- L
(o.o
p. C can be simplified as:
-1
~I
The shunt capacitance i
1
Z; j
5.6)
i a> a function of frequency is shown in Figure
5.5. The capacitance is almost uniform in the low frequency ramie U.U5 to 12 GHz)
and is 0.097 pF at 10.S36 GHz. From 12 to 40 GHz. the capacitance decreased
a little (about 0.076 pF at 20.03 GHz). It may be because of the effect of the
inductance, which is contributed by actuators. Rl. which is the absolute value of
the real part of Z x. is show in Figure 5.6. As seen in Figure 5.6. the value of R:
is fluctuating considerably (between 5.5 fi and 0.137 Q) due to the measurement
error and noise. Using the digital filter in MS-Excel. j Rj is averaged to reduce
the effect of noise. The average value over the frequency range from 4 GHz to
40 GHz is 2.8 Q. The standard deviation of this value (which can be used as an
estimate of the error bound) is 2.6 Q. The Q-factor (=
is 58 at 10 GHz for a
capacitance of 0.097 pF. Error bound of the Q-factor is estimated to be 820 to 30
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131
(corresponding to resistance values ranging from 0.2 Q to 5.4 H). Because there is
no resonance observed over the measured frequency range, inductance value could
not be calculated from the resonance frequency. The optimization tool in MDS
is used to compare the measured Z x to those computed from the lumped-element
model to get the value of inductance. L is 0.03 nH and much smaller than that
in series-mounted capacitur \L=u.22 n fij. L x and L j can be computed directiy
from Z> and Z 3 . L-. = L-> = 0.017 nH. Because the self-resonance frequency of
the shunt-mounted capacitor is fairly above 40 GHz. the shunt-mounted tunable
capacitor can thus be used beyond 30 GHz at least. Compared with the seriesmounted capacitor described in last chapter, the self-resonance frequency of the
shunt-mounted MEMS capacitor has been increased significantly.
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Figure 5.1: Simplified structure of the MEMS shunt-mounted capacitor. Longi­
tudinal side view (up) and top view Mown).
Figure 5.2: Lumped-element model of the shunt-mounted capacitor and the rela­
tionship between the model and Z-parameters without considering actuator effect
(a), and a simplified model of the shunt-mounted capacitor without considering
the effect of actuators (b).
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133
Figure 5.3: Photograph of one shunt-mounted capacitor assembly after removing
silicon for the first design.
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134
Fisture 5.4: Measured 5 1; and 5'ji of the first design for the shunt-mounted MEMS
tunable capacitor with a fixed 4 pin airgap.
yr
—
-
C3 i
-
C
7
Freauer.cviGK:;
Figure 5.5: Capacitance from measured S-parameters of the shunt-mounted
MEMS capacitor for the first design.
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135
Figure 5.6: R calculated from measured S-parameters of the shunt-mounted
MEMS tunable capacitor for the first design.
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136
5.2.2
Sim ulation results and R F m odeling for the first design
The variable MEMS capacitor also has been simulated using HP-Momentum
for different airgaps to test the tuning of the capacitor. The structure and dimen­
sions of the capacitor used in simulation are similar to those used in measurements,
excppr that the top plate of the capacitor is taken as just a 0.3 (tin gold layer with­
out polysilicon. Also, thermal actuators are ignored in the RF simulations at this
time.
Simulated S-parameters of the shunt-mounted capacitor with different airgaps are shown in Figure 3.7.
Note that the change of the S-parameters for
different airgaps is significant. Capacitance ( /m~^ ,
) for different airgaps as a
function of frequency are shown in Figure 5.8. .Vote that curves of the capacitance
as a function of frequency are very flat and the value of the capacitance increases
when the airgap decreases. The simulated capacitances for the shunt-mounted
capacitor are summarized in Table 5.1. The tuning ratio of C.naj-. C„un is about
3.4:1 when the airgap is varied from 0.3 //in to 4.0 (tin. The riming ratio is smaller
than 8:1. which is calculated by using the parallel plate capacitor formula.
It
means that the fringe effect and the parasitic parameters in the shunt-mounted
MEMS variable capacitor in CPW configuration reduce the tuning ratio. Since
no resonance is observed in
1
to 40 GHz frequency range, the inductance. L. is
difficult to obtain from these results precisely. Roughly. L is smaller than 0.007
nH and is ignored. In the EM simulation, the resistances. R. is ignored as well
because of its small value.
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137
Table 5.1: Values of the capacitance for the shunt-mounted MEMS capacitor with
different airgaps.
; Airgap(/mi) i C(pF)
0.5
0.41
L
U. 2 2
•1
0.13
4
0.076
c/i
-a
e
«
•0 5 urn S ’ *
FraqueneyfHz)
Figure 5.7: Simulated S-parameters of the shunt-mounted MEMS tunable capac­
itor for different airgaps (4. 2. 1. 0.5 /mi).
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138
Figure 5.S: The capacitance values of the shunt-mounted MEMS tunable capacitor
for different airgaps (4. 2. 1 . 0.5 pm i from simulated S-parameters.
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139
5.3
R F and m echanical im provem ents
5.3.1
Electro-therm al actuators and sizes of M EM S plates
Learning from the problems in the first design, the actuators have been
improved and redesigned. The new actuator design (see Chapter 4) is used for
the second improved design of the shunt-mounted capacitor^
The top MEMS plate in the MEMS tunable capacitor designs consists of
0.5 /mi gold layer. '2.0 pm polysilicon
1
. 0.75 pin S/Cb and 1.5 pm Polysilicon 2.
Because in the first design of the shunt-mounted MEMS capacitors, the size of
the top MEMS plate is large. GOO /mi x 200 /mi. compared with 300 /mi x 200
/mi for the series-mounted capacitor, the warpage of the MEMS plate due to the
mismatching of the thermal expansions of the gold layer and the polysilicon layer is
becoming a big concern. The thermal expansion constants of gold and polysilicon
are IGxlO- " j- and 3x10 ? j-. respectively.
After the MEMS is released, its
warpage of the GOO //in x 200 //in MEMS plate is about 1.3 pm. which is close
to the airgap (2-3 //mi. Meanwhile, when the bias current is applied, the top
MEMS plate gets heated. The warpage of the plate is reduced and cancels the
displacement of the MEMS plate. Therefore, it is difficult to control airgap and
tuning of the capacitance.
In order to reduce the warpage of the MEMS plate and get good control of
the airgap. the MEMS plate is reduced to 300 pm x 200 pm and the gold layer
on the surface of the MEMS plate is patterned. Figure 5.9 shows the layout of a
patterned MEMS plate design. The layout of the uniform gold layer in the first
MEMS plate design is shown in Figure 5.10 for comparison. The warpage of the
300 pm x
2 0 0
pm MEMS plate with the patterned gold layer is reduced to less
than 0.4 pm. To match the width of the MEMS plate, the dimensions of the 50
Q CPW line are reduced, the width of the center strip is 103.1 pm and gaps are
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140
4S.3 pm. So that the MEMS plate is able to cover 50 pm ground plane at each
side.
5.3.2
A ctuator effects in shunt-m ounted capacitors
Similar to the series-mounted capacitor, the effect of actuators on RF per­
formance of the shunt-mounted capacitor has been characterized by comparing
simulation results of the shunt-mounted capacitors with and without these actu­
ators.
First, based on the physical understanding, the actuator in the shuntmounted MEMS capacitor is modeled as an inductance series with a resistance.
The lumped-element model of the shunt-mounted capacitor is modified to include
the effect of the actuator and is shown in Figure 5 . 1 1 . La and Ra denote the in­
ductance and resistance due to the actuator, respectively. In order to simulate the
shunt-mounted capacitor with actuators, the actual actuators are also simplified
to straight strips as done in the series-mounted capacitor designs. Figure 5.12 (a!
shows the top view of the shunt-mounted capacitor with 2 strips. The size of the
MEMS plate in this case is 200 /mi x 300 pm. The center strip of CPW is 103.1
pm and gaps are 4S.3 pm. In HP-Momentum simulation, all of the metal layers
are taken as gold layers and the thickness of the MEMS plate is 0.5 pm. The strip
is connected to the MEMS plate at each side and ground through a vertical via at
the other side. The capacitor with different widths of strips has been simulated
while the length of the strip is kept 200 pm and the airgap is
1
pm. The width of
the strip is taken as 20. 10 and 5 pm.
Simulated S-parameters are shown in Figure 5.13 and the result for the
shunt-mounted capacitor, without any actuators, also is included for compari­
son. Note that S-parameters of the shunt-mounted capacitors with different strip
widths are similar. At higher frequencies, there is a little difference. S-parameters
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141
for the MEMS capacitor with 5 /im strips show a resonance, corresponding to a
minimum value of jSoij around 35 GHz. The simulated S-parameters values have
been transformed to Z-parameters for deriving a T-circuit model. Capacitances
of the shunt-mounted capacitors with different wide strips (calculated from Equa­
tion 5.S) are shown in Figure 5.14 and capacitance values for the MEMS capacitor
without actuators arp also shown. From this figure we norp
that
rherp are ran
kinds of actuator effects on RF performance of the shunt-mounted MEMS tun­
able capacitor: ( 1 ) The grounded actuators increase the capacitance value of the
shunt-mounted capacitor compared with the one without actuators. (2) The ca­
pacitors with narrower strips have lower resonance frequencies. In this case, the
capacitance increases from 0.222 pF to 0.433 pF. after adding the ground strips.
This may be because after adding the strips, these strips provide a path for the
current through inductance Lu and the capacitor C" is bypassed (see Figure 5.11).
The total capacitor is not C' series with the parallel combination of C" bur just
C". Hence, the total capacitor increased.
Because a narrower strip has a higher inductance, when the width of strips
decreases, the self-resonance frequencies increase . In our simulation results, the
self-resonance frequency of the capacitor with 5 /mi wide strips is lowest and
about 34.04 GHz. When the width of strips increases from 5 to 10 and 20 /mi.
the resonance frequency increases to a value above 40 GHz. More simulations
in high frequencies have been performed to reach the self-resonance frequencies.
Simulated S-parameters at higher frequencies for the
10
and 20 /mi strips cases
are shown in Figure 5.15. Again, the capacitance values for capacitor with 10
and 20 /mi wide strips are obtained from S-parameters and are shown in Figure
5.16. Note that an additional resonance is shown in both curves. The resonance
frequencies are 41.96 GHz and 56.35 GHz for the MEMS capacitor with
10
/im
wide strips, and 55.94 GHz and 71.25 GHz for the MEMS capacitor with 20 /im
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142
wide strips. Based on the model redrawn in Figure 5 . 1 1 . the 2nd resonance should
be due to the resonance of the shunt La and C " . The inductance of the shuntmounted capacitor w ith strips can be computed based on the simulation results
(C and u-'o using „'q = ^ ~
) and is about 0.005 nH for the
5
/.im strip case.
Compared with the MEMS capacitor without actuators, the inductance increased
from 0.0024 nH to
0 OO n n H
«\f
rl>o
• l e r i i ' H - Af
There are two ways to reduce the inductance and increase the resonance
frequency:
(1)
reduce the length of the actuator.
i2l
increase the width of the
actuator. \\ hen the length of the strips is reduced to zero, the inductance of
the strips will be near zero and the resonance frequency will be close to the one
without actuators. To verify the assumption, the capacitor with zero length strips
has been simulated. Figure 5.17 shows the comparison of the capacitances for the
capacitors without actuators and with zero length strips. As we expected, the
curve is very flat for the capacitor with zero length strips, showins absence of
resonance at a higher frequency. This means that the effect of inductance due to
actuators on self-resonance frequency is dominant. However, zero lemrth actuators
are not practical for the thermal actuator desiun The lemrth of thermal actuators
is determined by the mechanical design for the optimum movement. Therefore,
increasing the width of the actuator or employing multistrip is a good way to
reduce the inductance of the actuator.
The shunt-mounted MEMS capacitor with four strips has been simulated
(see Figure 5.12 for the layout). Figure 5.18 shows the simulated capacitance
for a capacitor w ith four strips
(1 0
gm wide and
capacitor with two strips (20 /tm wide and
2 0 0
2 0 0
nm long each) and for a
gtm long each). The interesting
observation is that capacitance values in these two cases are very close. Therefore,
these grounded actuator strips at each side of the MEMS plate can be combined
together simply as parallel inductors. In the real assembly of the shunt-mounted
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143
MEMS tunable capacitor, only cold arms are grounded and hot arms are isolated
from ground for bias. The case with cold arms grounded and hot arms isolated
also has been simulated using by HP-Momentum. Figure 5.19 shows the top view
of the capacitor with two actuators. Each actuator consists of one hot arm and
two cold arms. The hot arm is at the center and while the cold arms are at each
side of the hot arm. The widths of all strips arc the same and 10 //in. Tut- gap
between the cold and hot arms is 10 /mi as well. The length of the cold arm is
'200 //m and the hot arm is 220 //in long. The simulated S-parameter is very dose
to that of the case with 20 //in strips (shown in Figure 5.20|. This means that
the effect of the noti-grounded hot arm can be ignored. Oniy grounded cold arms
affect RF performance of the MEMS capacitor and each one can be modeled as an
inductance, several arms (strips) can be summed together as parallel inductors.
In the shunt-mounted capacitor design, the actuators are floated above the
ground planes of the CPW’ line.
In order to calculate the inductance of the
actuator, the complete actuator has been simulated using HP-momentum. The
structure used in HP-momentum simulation is shown Figure 5.21. Microstrip lines
are added at each end of the actuator for RF ports needed in HP-Momentum
simulation. The width of the microstrip line is close to the width of the actuator
to reduce any discontinuity reactance. Reference planes are placed at the ends of
the actuator. The airgap (between the structure shown in Figure 5.21 and the
ground plane) is
1
/tm in this case. The inductance calculated from Y-parameters.
which were transformed from S-parameters. is about 0.026 nH. The inductance is
much larger than that value obtained from simulation results of shunt-mounted
capacitor w ith actuators. This means that the inductance of actuator can not be
characterized using this approach because the EM field distributions are different
in these two cases.
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144
Figure 5.9: The pattern of the gold layer on the MEMS plate for the MEMS
capacitor design with itching holes.
Figure 5.10: The uniform gold layer layout on the MEMS plate with itching hules.
R-
l:
u
r .'
Figure 5.11: Lumped-element model of the shunt-mounted capacitor with effect
of actuators.
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MEMS
(b)
Figure 5.12: Structures of the shunt-mounted capacitor with simplified actuators,
(a) with two strips and (b) with four strips.
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146
o
o
-j
Figure 5.13: Simulated S-parameters of the shunt-mounted capacitor with two
strips and without actuators. Width of strips is taken as 20. 1 0 . 5 nm. Length of
strips is 200 ^m. Airgap = 1 iim.
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147
Figure 5.14: Simulated capacitance of the shunt-mounted capacitor with two strips
and without actuators. W idth of strips is taken as 2 0 . 1 0 . 5 /mi. Length of strips
is 200 fim. Airgap = 1 /mi. Solid line with x is for the capacitance of MEMS
capacitor without actuators.
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148
: requency
(0
Figure 5.15: S-parameters of the shunt-mounted capacitor with two strips at
higher frequencies, (a) Width of strips is 10 pm. (b) width of strips is 20 pm.
Length of strips is 200 pm. Airgap is 1 pm.
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149
Figure 5.16: Simulated capacitance of the shunt-mounted capacitor with two strips
at higher frequencies, (a) W idth of strips is 10 /urn and (b) width of strips is 20
fim. Length of strips is 200 /jm. Airgap is 1 jim.
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Figure o.l7: Simulated capacitance of the shunt-mounted capacitor with two strips
and without actuators. W idth of strips is 20 /mi. Length of strips is taken as 200
and 0 /mi. Airgap = 1 /mi.
-' - v -»«
-; . . 4
------- .. ----------•
fi S- - ..Js
- — — ——i
v/c szrips
•
1. Q
F requencyIGHz ;
40 . C
Figure 5.18: Simulated capacitance of the shunt-mounted capacitor w ith two strips
and four strips. W idth of strips is taken as 20 /im for 2 -strip case and 10 gm for
4-strip case. Length of strips is 200 gm. Airgap = 1 gm.
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151
MEMS
Hot a m
C o ld a r m s
Figure 5.19: Structure of the shunt-mounted capacitor with two actuators for
HP-Momentum simulation, in which cold arms are ground and hot arm is isolated
from ground plane.
C
O
*3*
I
0
Figure 5.20: Comparison of simulated S-parameters of the shunt-mounted capaci­
tor with two strips and two actuators, in which cold arms are ground and the hot
arm is isolated from ground planes. W idth of strips is taken as 20 gm for 2-strip
case and 10 /zm for the cold and hot arm in 2-actuator case. Length of strips is
200 ^m. Airgap = 1 gm.
.
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152
Micro.trip line
'
F,c' urc
s—
KS -n a
C^ldcrm .
Hot -L'TTl
■
MicioMnp line
---------
Figure 5.21: Layout of a complete actuator used in HP-momentum simulation.
Larir. is the length of hot arm and told arms and is chosen as 2 0 0 /mi. Lf is the
length of flexure and is 55 /mi. the width of the hot arm at renter is 20 /mi. and
the width of cold arms is 5 /mi.
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153
5.3.3
Q-factor and thickness of gold layer
In the previous chapter, the Q-factor of a parallel plate capacitor made of
multilayer metal has been calculated using the transmission line model. Because
there are not any via and beam included in the shunt-mounted capacitor lay­
out and the dielectric layer is air as well, the conductor loss due ro the MEMS
multilayer metal plate will be dominant for the shunr-mounted capacitor. Hence,
the transmission line model can give a good estimation of Q-factor of the shuntmounted capacitor. Using the surface impedance of the multilayer metal, which
has been shown in Figure 4.23. the resistance of the top MEMS plate has been
calculated and is about 0.147 V.. Adding the resistance of the 2 /mi gold layer on
the bottom plate ia part of C'PW). the total resistances have been found 0.1G7 H
for
10
GHz for a 0.5 /mi gold layer on polysilicon. It is smaller than the measured
resistance (0.2S H) for the first design. It may lie because of
11
; resistance added
by the actuator. !2 1 gold film being less than 0.5 /mi and (3) measurement errors.
5.4
M easured results and analysis o f th e second design
The shunt-mounted capacitor has been redesigned to improve RF and me­
chanical performance according to discussions in the previous section. The size of
plate is reduced from 600x200/mi to 300x200/mi. which improved the mechanical
performance considerably and made the processes easier. Although the area of
capacitor is reduced by a factor of 2 . the capacitance is not reduced because the
top plate is grounded by cold arms. The gold layer on the top MEMS plate is not
uniform but patterned for the new design to reduce the warpage. The actuators
have been changed to the new design with the 250 /tm long hot arm and 200 gm
long cold arms. Four actuators are connected to the MEMS top plate through
flexures. Dimensions of CPW are reduced to 103.1 gm wide for the center strip
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154
and 48.3 fim for gaps. The photograph of the second design is shown in Figure
5.22. The pattern in light gray is the substrate circuit on alumina. The dark
gray area is the MEMS structure. Black areas are slots in the gold layer on the
alumina substrate. As seen in this photo, the hot arms are isolated from ground
planes and the cold arms are grounded.
!
I
!
i
Figure 5.22:
paritor.
The photo of the second version of the shunt-mounted MEMS ca-
i
j
The measured S-parameters of the second design are shown in Figure 5.2-1.
j
Capacitance of this design is shown m Fisure 5.25. Total capacitance value is
about 0.272 pF and the resonance frequency is beyond 40 GHz (not seen in this
figure). Total loss (;R,. the real part of Z\) is shown in Figure 5.2G. Note that R
is large at low frequency (below 5 GHz), but it is very small and almost uniform
above 5 GHz.
Reference to the lumped-element model of the shunt-mounted
capacitor with the effect of actuators (see Figure 5.11). at low frequencies, most
current goes through the La and Ra (actuators) because the 1/wjC is large at low
frequencies. But. when frequency increases. 1/^,’C decreases and jjL increases,
more and more RF current goes through C" and Ra is bypassed. Hence, loss is
reduced at higher frequencies. Taking the average of |R| above 5 GHz to reduce
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155
the measurement noise. jR| is about 0.151 ± 0.145 Q. The error of |R| is dependent
of measured S-parameters. In our measurement, the measured errors in the real
and imaginary parts of S-parameters are approximately
error of
|R: is close to 0.145 Q(seesection4.3.5 for the
The Q-factor calculated from the measuredresults
iO"i
/
iw *
n o —o ~ r ?
w.
i _
p !
(U
in
iU
0.01
and the measured
error transform formula).
is approximately 383 (min.
tt-
V J liz , .
The measured R (0.151 51) is very close to the calculated R (0.154 H). which
is computed by using the parallel plate capacitor model and the surface impedance
of the multilayer metal. This means that the transmission line model for surface
impedance and the parallel plate capacitor model give a good estimate on the Qfactor of the shunt-mounted capacitor. If the gold layer thickness is increased from
0.5 /mi to
1
/nn. the Q-factor of the shunt-mounted capacitor w ill be increased
from ISO to .340 at
10
GHz for 1 pF (about 50(a 1 . Comparer! with the first design,
the R in the second design is reduced from 2.S H to 0.151 H.
Computed from the real part of Zj. the value of R , and R ; is approximately
0.5 H and can not be ignored (see Figure 5.2). The large valve of /?•> and
be due
to
the current distribution on the
top
mav
MEMS plate. Figure 5.23 shows
the current distribution on the top MEMS plate at one moment. Xote that the
current does not go through the top plate along the short edge directlv but it
flows along a circle. The path of the current is much longer than the length of
short edge of the MEMS plate. Thus, the resistance due to the MEMS top plate
increases. If including R2 and R3 in the Q-factor. the Q-factor w ill be reduced a
half.
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Figure 5.23: Current distribution on the top MEMS plate from EM simulation.
C
0
3
V3
FrecuencviGHz!
Figure 5.24: Measured S-parameters of the shunt-mounted capacitor for the im­
proved design. Solid line with xx is 5 U- solid line is for S21.
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157
Figure 5.25: Measured capacitance of tiie shunt-mounted capacitor for improved
design.
£ ^
a:
v*
v
-
Frecuer.cv i GK:
Figure 5.26: Measured resistance of the shunt-mounted capacitor for improved
design.
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158
5.5
Discussions
5.5.1
Shunt-m ounted capacitors
Two shunt-mounted MEMS tunable capacitors in CPW configuration have
been designed and measured up to 40 GHz. A lumped-element model has been
developed for the shunt-mounted MEMS tunable capacitors. The effects of the
actuators have been characterized. In the shunt-mounted capacitor design, the
actuator should be grounded to increase the capacitance. Multi-strips reduce the
inductance and increase the self-resonance frequency. And several strips can be
added as the parallel inductors. High Q-factor has been obtained in the shuntmounted capacitor designs. The Q-factor is approximately 3S3 for 0.277 pF at
10
GHz. The simulated tuning ratio of tlie shunt-mounted capacitor is approximately
5.4:1 with a airgap varied from 4 to 0.5 /urn.
5.5.2
Com parison of series-m ounted and shunt-m ounted capacitors
The capacitance values of the series-mounted and shunt-mounted capacitors
from measurement results are shown in Figure 5.27. The shunt-mounted capacitor
has higher self-resonance frequency than the series-mounted version. The seriesmounted capacitor can be used below 14 GHz. but the shunt-mounted capacitor
can be used up to 40 GHz. Also, the shunt-mounted capacitor has much higher Qfactor because there are not beams, connecting pad and via in the shunt-mounted
capacitor. For the series-mounted tunable capacitor, the Q-factor is approximately
256 at
1
GHz for a
0 .1 0 2
pF capacitance value. For the shunt-mounted tunable
capacitor. Q-factor is approximately 383 at
10
GHz for a 0.272 pF. Tuning ratios
are similar for both of capacitor designs and are approximately 5:1 based on
simulation results. The measured tuning ratio of series-mounted capacitor is 2.6:1
for the airgap changed from 2.27 to 0.67 fim. Chapters 4 and 5 have described our
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159
attempts in design, fabrication, measurement and modeling of the series-mounted
and shunt-mounted MEMS variable capacitors. Results point out two possible
high Q capacitor designs, which are suitable in microwave/mm-wave circuits, de­
values can be increased further if a process for higher thickness of gold layer can
be incorporated in the fabrication process.
I
i
I
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160
&
S e n e s Mour . t ea
S" j r : M o j r t e c
:c
tc
F re q u e n c y (G H z )
Figure o.'27: Comparison of the capacitance values of the series- and shuntmounted capacitors.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 6
RF M EM S M ultiway Sw itches
A RF Switch is the component that performs high-frequency (RF/Microwave)
signal switching and routing. Semiconductor devices, such as p-i-n diodes and
GaAs FETs. are commonly used as switching devices in RF Microwave switches
because they can switch from a high impedance to a low impedance when con­
trolling biases are changed. However. RF loss in semiconductor switches is large
at high frequencies. Insertion loss of a typical GaAs-FET or p-i-n switch is ap­
proximately 1 dB at
'20
GHz SC’ . As a possible replacement of semiconductor
switches. MEMSs have been developed for RF switches o j . 71 - 76’.
So far. all of published studies on MEMS switches are simile pole simile throw
iSPST) switches in series-configuration or parallel-configurarion. In this chapter,
we develop compact SPOT and SP3T MEMS multiway switches in CPW circuits
using cantilever beams with electrostatic actuations.
6.1
6.1.1
D esign of M EM S sw itches
G eneral design considerations
RF switch design considerations include: ( 1 ) Switching speed: Turn-on
switching speed is defined as the time interval between the instants when the
envelope of the RF output rises from 109t of its peak value to 909c of its peak
value. Turn-off switching speed is defined as the time interval between the instants
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162
when the envelop of the RF output reduces from 909c of its peak value to 109c of
its peak value when the switch is off. Switching speed becomes very important
for high-speed digital circuits or modulations in modern communication systems.
It is limited by switching devices and biasing networks.
(2) RF power handling: This is a measure of how much and. in some re­
spects. how well a switch passes R.F signals. To quantify RF power handling.
dB compression point is commonly specified and is defined as the point of
1
1
dB
deviation from linearity of the output power with respect to the input power. In
semiconductor switches, e.g.. PIX diodes and MMIC switches, power handling is
a function of frequency.
(3) RF insertion loss and isolation: These are measures of RF performance
when the switch is in OX state and OFF state, respectively.
Insertion loss is
defined as the ratio of the power delivered to the load of an ideal switch in OX
state, to the actual power delivered by the practical switch in OX state. Isolation
is defined as the ratio uf the power delivered to the load of an ideal switch in OX
stare, to the actual power delivered to the load when the switch is in OFF stare.
Both of these may be calculated by considering an equivalent lumped-element
model of the switch in OX and OFF state. In terms of S-parameters. S2; of a
switch in OX state is its insertion loss, and 52i of a switch in OFF state is its
isolation.
(4) Actuation voltage/current: In addition to the above parameters, the ac­
tuation voltage/current, a bias necessary to produce switching, is also an impor­
tant switch parameter. Especially for electrostatically actuated MEMS switches,
reduction of the actuation voltage is the key mechanical design factor.
Switching speed, actuation voltage and power handling of MEMS switches
are affected more by mechanical design and properties of structure materials.
Insertion loss and isolation of the MEMS switch are determined mainly by RF
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163
design.
6.1.2
M echanical design and fabrication
Because of their simplicity, the most common and basic MEMS switching
elements are cantilever beams and doubly-supported beams (membrane) !77:. In
mir
M
-*
*,*1
1
». ti *-J >* lie u vaCJA^iiO. c u u u itv c i
I. ...
\
ucaiild liavt* U f f l l
l
*
>•
i
SVVUCiiUlg fit*-
ments. Also, electrostatic actuation is utilized because of higher switching speed
(on order of microseconds) compared to thermal actuation (on the order of tens
of milliseconds) rS3:.
The conceptual design layout of MEMS for multiway switches is shown
in Figure 6 . 1 . Again surface MEMS technology from MC'NC is used to fabricate
MEMS structures. As before. MEMS is flip-chip bonded on the alumina substrate
Center pad
V
\
\
Cantilever Beams
Figure 6 . 1 : Layout of the initial design of MEMS for 8 -port switches.
w ith indium bumps. After flip-chip bonding, the silicon substrate is removed by
the releasing process. Figure 6.2 show the top view and the cross section of a
two-port MEMS switch. The two beams are moved up and down by electrostatic
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164
forces from DC bias voltage. In a multiway configuration, the RF signal can go
through any two ports which cantilever beams are pulled down by DC bias while
the other pons with zero bias voltage keep flat. Figure 6.3 shows the schematic
layout of one cantilever beam in the multiway switch. Actuation voltage of the
cantilever switch is determined by the structure and the size of the switch beam,
and can be found from the pull-down voltage of the cantilever beam. When DC
voltage is applied between the top cantilever beam and the metallization layer on
the alumina substrate, the forces acting on the beam include the electrostatic force
and the restoring force of the beam. The pull-down voltage for the cantilever beam
can be calculated by setting up a force-balance equation between the electrostatic
force and the restoring force of the cantilever beam and is given 74 by:
\ P= t ,
■2EhI hH * K
... . ■
,
2
A = 4 A - — -----
-.3(1 - A )
ib.l;
vA
I m l — A ).
= --------------- —---- -
VA
1
-3A
. )
16 2
iG:!l
where Eb is the elastic modulus of the beam. I b is the angle momentum of the
beam. r 0 is the perm ittivity of free space.
11
), and Lb are the width and length of
the beam, respectively. ST (= H0-H) is the deflection at the tip of the beam. H0
is the initial airgap (bump height) and H is the gap between the beam and the
surface of the substrate. When the beam is bent about one third of the initial gap
between the cantilever beam and the substrate, the electrostatic force is equal to
the recovering force of the beam. After that, the electrostatic force increases as a
function of 1 /H and faster than the recovering force increasing speed, so the end
of beam is pulled down suddenly. Xote that the pull-down voltage is a function
of the size of the beam and the bump height (airgap).
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165
Table 6.1: Dimension of MEMS for 2-port switches
; Beam Length Lb I Beam width H \ { Center pad diameter Db
| Case 1
780 /mi
360 /mi
90 /im
i
! Case 2
360 //m
90 /im
360 /im
T w o
c p fc
o f
iv tt h
c i7 o c
o f t H t ? C *O r l t G T' p ^ i c i I" 1 0 .V C
using the MUMP’s processes. The parameters for these two designs are shown
in Table 6.1. MEMSs for 2-beam (2-port). 3-beam, and 4-beam versions have
been fabricated. Mechanical performance of the beam of on-chip version has been
tested by the interference microscope. Figure 6.4 shows the microscope photo of
a cantilever beam for different actuation voltages. While the actuation voltage is
2 0
volts, the free end of the cantilever is pulled down and touches the surface of
substrate.
In the electrostatically actuated switch design, electrostatic sticking is a
special problem 7S;. which causes non-operation of the switch or reduces the
switching speed. To avoid this problem, a thin layer (0 . 1 /m il of the dielectric
material (Si,?A -. for example) needs to be placed on substrate. As an alternative
to dielectric materials, dimples can be used in the MEMS beam to reduce the
sticking.
6.1.3
RF design m ethod and 2-port M EM S sw itch design
RF design method:
The following MEMS switch design description refers to the schematic draw­
ing shown in Figure 6.2. In the 2-port switch design, the center pad is kept because
our propose is to design a multiway switch using a multibeam MEMS and the cen­
ter pad is necessary to hold these beams. Notice that the MEMS switch structure
can be separated into two parts as shown in Figure 6.2. One is the center pad with
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166
bonding bumps and a part of beams, which is called Part
1
. the other part is the
overlay area between the cantilever beam and the metal layer on the substrate,
which is called Part 2. When bias voltage is on or off. the beam is bent down or
up. and the capacitance of Part 2 changes to a large or a small value.
Part 1 needs to be optimized for the better insertion loss and isolation while
*.
c •*)
—;c
A
~~~A
~
t
-------------- ^
I'-'* ^ a u J i a y i u i v iiiCL.iiaiiiL.cti
l/^j c i a n u i i .
*
ui c sig il l i i c m u ui iilcts
been developed for the MEMS multiway switch design. A flow chan of the design
method is shown in Figure 6.5. First, the basic layout of the multiway switch is
selected (for example, a 2-port switch in figure 6.2). Then, the whole switch is
separated into two parts. Part 2 is determined based on mechanical consideration,
and is analyzed and calculated by the parallel-plate capacitor formula to obtain
on and off capacitance values. Part I is simulated using EM simulation tools (HPMomentum. HP-HFSS). Then a lumped-element model for Part I is developed to
optimize the insertion loss and the isolation. After that, the physical layout of the
substrate circuits (gap between the MEMS and substrate in our case) is chosen
according to the lumped element model. Finally, the switch capacitances (Part
2) are added to the lumped-element model of Part
1
to obtain RF performance
of the whole MEMS switch using the linear network simulation in MDS. In the
next section, as an example, a 2-port MEMS switch is designed using this design
method.
Design of 2-port switches:
In RF design of a 2-port switch, the first step is to choose transmission lines
on the substrate of the motherboard (alumina used in our work). CPW has been
used for the MEMS switch design because in CPW configuration the ground planes
and the center signal strip are in one plane, the distance between the MEMS and
the ground planes of CPW is can be modified conveniently by suitably locating
the edges of the ground planes. A 50 Q CPW on alumina substrate is designed
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167
for the MEMS switch, the center strip is 203.3 /im wide and the gap is 96.7 /im
as before.
Reference to the basic structure of the 2-port switch (see Figure 6.2). an
equivalent, lumped-element circuit of the switch has been developed (see Figure
6
.6 ). L is the inductance of the beams and the center pad. Cc is the capacitance
•jUm LLii cnc c t m L i puva a n u cue ^ l u u i i u p ia u c a .
^ off d iiu
ori
Liit' c ap dL italiL
between the beams and the center strip of CPW’ for the switch in OFF and OX
state, respectively. When no DC bias voltage is applied, there is no force on the
beam, the beam is flat and airgap between the beam and the surface of the gold
layer on alumina substrate is equal to the bump height 1 2-3 /mi). The switch is in
OFF state and the switching capacitor is C ,//- Isolation of the switch is dependent
of Caff. The smaller the C„ff- the better the isolation. When a DC actuation
voltage (20-25 volts in our case) is applied, the electrostatic force pulls the beams
down and increase the switch capacitance from Cn,-f to Con. The switch is in OX
stare. Usually a 0.1 /mi Si-.iXA layer is added on the surface of the gold layer on
the alumina substrate. In the OX state, the capacitor Crm is very large because
the airgap is very small (0.1 /mi if
layer is plated). In our simulations,
metal to metal contact is assumed because the Con is large and its effect on RF
performance can be ignored. Generally Con/C 0ff is around 50 to several hundreds.
For optimization of the switch design, the gap between the MEMS and the
edge of the ground plane is the key parameter. Xote that in the lumped-element
model, two inductors (L) and one capacitor (Cc) make a T-network. When the
loss (R) of the circuit is very small, the characteristic impedance of the T-network
as a section of transmission line is calculated using equation [96;:
Ztn = ^
[2L
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(6.4)
168
The ratio 1 of ^
is able to be changed to match 50Q transmission line and to
reduces the insertion loss of switch at OX state. Several switch layouts have been
designed and characterized to find the better RF performance of the 2 -port switch
(see Figure 6.7). In the simulation set-up2 for HP-momentum. the Si^X^ layer is
not added, the beam is flat for OFF state, with a airgap of 3 /zm. For OX state.
t-Kn k n .-,™
*b
futiL.
l-ikuu
. . -t a kj
0
- va
J va
J -cta
J a
- *i me
\ to . id a
1
- ......... a—
ic a >
ueLv\eeii
me
MEMS and the center strip of CPW on the substrate. The dimensions of MEMS
are as follow: the length of beam is 360 //in. width of beam is 90 /zm. and the
diameter of the center pad in MEMS is 780 /mi. Reference planes are placed at
the ends of beams. For the OX state, the simulated S->i is the insertion loss and
the simulated 5 j: in OFF state yields isolation.
Simulated 5-jis for the different substrate layouts are shown in the Figure
6
.S. Transforming S-parameters to Z-parameters. capacitance C (Figure
6
.6 ) is
calculated from Z, i= Z ji) and L is calculated from Z j (= Z i; -Z j; i or Z:i ; =
Z j-j-Zii). In the first layout attempt Idesign
=
1
i .
the ground plane is under the
MEMS plate and thus Cr is large. The simulated isolation is good (-30 dB at
10
GHz) but the insertion loss is large i 0 dB at 13 GHz:. From the lumped-element
model and Equation 6.4. notice that reducing the capacitance in the T-network
of Part
1
can change the Zm to match 50 H and thus reduce the insertion loss.
In the next design (initial design #
2
). the gap between the MEMS plate and
ground plane is increased (300 /zm) to reduce the capacitance value. Simulation
results show an improvement of the insertion loss but the isolation is reduced (see
Figure 6 .8 ). In design # 3. the gaps between the MEMS plate and the edges of
the ground planes are selected to be about 105
/zm
to balance the capacitance.
1 In the M EM S switch C on is very large and is approximately 9 pF in our case, the reactance
of the capacitor at high frequency is very small, hence, the C on is not considered for the insertion
loss.
2 In this chapter, in all of simulation set-ups. M EM S is taken as 0.5 /zm gold plate unless
otherwise stated.
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169
Insertion loss is approximately 0.3 dB at 10 GHz and isolation is approximately
22 dB at 10 GHz. which are both better than the previous designs (see Figure
6.8
for comparison). Cc is 0.041 pF and L is 0.33 nH. The input impedance Z m (
So far. the
layer is not considered. If a Si:iX A layer is introduced
hprween the beams and the metal layer on the alumina substrate. Can and COJ-j
in the lumped-element model should include the effect of S i . layer. These can
be estimated by using the parallel plate capacitor formula because the airgap is
much smaller than the size of the overlap area between beams and the center strip
on the substrate. If a 0.1 /mi Si:iX A is deposited on the surface of substrate, and
the overlay area between the center strip of CPU’ and a MEMS beam is 130 x
90 /mi and the airgap is 3 /mi. Con and C'af f are about 8.9 pF and 0.041 pF.
respectively. The ratio of Con and C„n is approximately 217:1. Including the Con
and C0ff . RF performance of the whole MEMS switch in OX and OFF state has
been computed using the lumped-element model. The final results are shown in
Figure 6.9. For this case, the insertion loss is approximately
0.1
dB at 14 GHz
and the isolation is 23.G at 14GHz. The design == 3 has been fabricated. Figure
0 .10
shows the photo of one sample of 2 -port MEMS switch assemblies with bias
circuits.
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170
-P an !
P an Z —
—
P an: —
M EM S
Port !
Pan;
CPW
Reference plane
Sv.ucb up
M EMS
R F input
RF output
Bumps
A lu m iro substrate
Snvncn
R F input
RF output
•b*
F i g u r e G.2: S c h e m a t i c d r a w i n g o f th e 2 - p o r t M E M S s w i t c h , u u T o p v ie w , ( h i side
v ie w .
M e t a i - t o - t n e t a l c o n ta c t in p a r t 2 o f rh e s w i t c h is a s s u m e d .
Ahtfluna stbstraie
Figure 6.3: Schematic layout of one cantilever beam in the multiway switch.
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171
Figure 6.4: Microscope photo of the zip cantilever beam for different bias voltages
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
: Basic structure of multiwav switch
Design of Part 2 based on
Equivalent circuit
mechanical consideration
model for Pan 1
Optimization o f insenion loss and isolation using
O n /O ff capacitances of Pan 2
cncuit model o f Pan 1 to obtain the value of elements
Analysis o f the complete switch with
Physical layout of switches substrate
from the lumped-element value
the switch capacitors using the cricuit model
Fabncation and measurement
Comparison
i
Final desten
Figure 6.5: Flow chart of the design method for multiway-MEMS switches.
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173
Reterenccnlane
Reierepcs plane
n«air.
Figure G.6 : Lumped-element model of 2-port MEMS switches.
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174
CPW
(ai Initial desian #1
CPW
(b) Initial desian #2
.CPW
ic ) Optimized design
Figure 6.7: Different substrate layouts for 2-port MEMS switches
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175
o
i
3
3
6
a
-9
10
0 00E- 00
5 00 E- 0 9
l f l OE - 1 0
l 50E- 10
2. 00E- 10
Frequency(Hz)
( a)
10
•
-20
•
•
m
2.
|
-30 •
a
O -4G •
3 3e e
- r
1, 3
3 = 3:3^
«1
•50 --------O.OQE -00
00 E - 0 9
1 00 = - 1 0
l 50E- 10
2 00E-’ 0
Frequency(Hz)
(b)
Figure 6 .8 : Simulated S-parameters for the 2 -port switch with different substrate
layouts
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176
m
■o
In s e r t i o n lo s s
■is o la tio n
39
J S .3 5
c ;-3 i
:= -3 9
Frequency(Hz)
Figure 6.9: S-parameters for the improved 2-port MEMS .switch from the lumpedelement model with Cm) and C0/ f
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177
Figure 6.10: Photo of an example of 2 -port MEMS switch assemblies with bias
circuits.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
178
6.2
D esign exam ples of multiway-M EM S sw itches
Following the study of the 2 -port MEMS switch described in the previous
section, the 3 and 4-port MEMS switches are discussed as follow.
6.2.1
D esign and characterization of 3-port (SPD T ) sw itches
Two kinds of 3-port switches in CPW configuration have been designed and
characterized: the T-junction MEMS switch (see Figure 6 . 1 1 ) and the Y-junction
MEMS switch (see Figure 6.121. Again, for the design purpose, the 3-port MEMS
switch is separated into two parts as well: Part
1
is the part includes the MEMS
center pad and a part of the beams. Part 2 is the overlay area of the beams and
the center strip of CPW. which is taken as parallel plate capacitors. Design of
Part 2 is identical to that for 2-port switch in section 6.1. Based on physical
understanding, a lumped-clement model has been developed fur the 3-port switch
(see Figure 6.13).
For both Y-junction and T-junction MEMS switches, the substrate layout
obtained from the 2-port MEMS switch design is used for the 3-port switch. The
distance between MEMS and the edges of the ground planes is about 105 /mi.
Diameter of the center pad in MEMS is 360 //m. the length and width of beams
are 360 gm and 90 fim. Again the 50 Q CPW transmission line is used as the
ports for simulation and the probe pads for RF measurement. In the structure
for HP-Momentum simulation, the beams are flat for OFF state and via is added
for OX state while the third beam is left flat. For example, when simulating the
isolation (S2 1 for OFF state) between port
1
and port 2. beams at port 1 and 2
are kept flat, beam at port 3 is flat as well and the CPW line at port 3 is matched
in a 50 Q load. When simulating the insertion loss (S2i for OX state) between
port
1
and port 2 . the vias are added at the overlay areas at port
1
and port 2 . the
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179
beam at port 3 is still flat without via added and the CPW* at port 3 is matched
by a 50 Q load.
The simulated insertion loss and isolation of the T-junction switch with a
3 pm airgap are shown in Figure 6.14. Since this design is not symmetric, the
insertion loss between port
between port
1
1
and port
2
is a little different from the insertion loss
and port 3 at higher frequencies. Insertion loss is 0.25 dD at S
GHz. Isolation is -16 dB at 3 GHz. The Y-junction switch is symmetric. Hence,
only one case (from port
1
to port
2
. for example I is needed to be characterized.
The same lumped-elemenr model could be used for the Y-junction switch, bur
= I j = L 3. R i = R-> =
from symmetry consideration. The simulated insertion
and isolation for the Y-junction switch with a 3 pm airgap are shown in Figure
6.15. Insertion loss is -0.24 dB and isolation is approximately -15.55 dB at S GHz.
Better insertion loss and isolation could be obtained by optimizing the 3-port
switch layouts using the design method used in the previous section. Moreover,
isolation can be improved by increasing the airgap. When airgap increase from 3
pm to
20
6
pm. isolation of these 3-port switches increases by 5 dB i from 15 dB to
dB).
6.2.2
RF design and characterization o f 4-port switches
Primary layout of a 4-port MEMS switch is shown in Figure 6.16. A lumpedelement model based on the 4-port switch structure has been developed and shown
in Figure 6.17. Simulations have been carried out for the 4-port MEMS switch
design w ith dimensions similar as these used in 3-port switches (excepting one
more beam is added).
Simulated insertion losses and isolations between port
between port
1
1
and port
2
. and
and port 3 for switch are shown in Figure 6 .IS (a) and (b). Notice
that the insertion loss between the port 1 and port 3 is larger than that for the
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180
port 1 and port 2 at higher frequencies.
and are approximately
0.6
dB at
8
A t low frequencies, they are similar
GHz. Isolation values for both of them are
approximately 15 dB. A better performance can be obtained while optimization
of the 4-port switch design is done by using the design method used for the 2-port
MEMS switch design. This primary design of 4-port switch gives the direction for
the multiway MEMS switches design.
6.3
Rem arks
A design method has been developed for the multiway-MEMS switch design.
CPW has been chosen for the multiway switch layout. 2-port switches have been
designed and optimized as a design example. The insertion loss is less than 0.1
dB and isolation is better than 23 dB at 14 GHz. Two primary 3-port switches.
T- and Y-junction switches, have been designed . The insertion loss and isolation
between any two ports in both switches are approximately 0.2 dB and 16 dB at
S GHz for airgap 3 /mi without any dielectric layer between MEMS beam and
gold surface on alumina substrate. A 4-port switch has been designed as well.
Insertion loss between any ports are
0.6
dB. and isolation are 15 dB. 3-port and
4-port switches can be improved further by using the design method developed
for the multiway switches.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure (3.11: Layout o f the T -ju n c tio n sw itch using 3-beams M E M S .
T
Figure 6 . 1 2 : Layout of the Y-junction switch using 3-beams MEMS.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Part 1
C=
R'
Port 3
Figure 6.13: Lumped-element model of 3-port MEMS switches.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
183
(b)
Figure 6.14: Simulation results of T-junction MEMS switches. Airgap is 3 /tm
and the diameter of the center pad of MEMS is 370 ^m. Dot lines are insertion
loss (S2i for OX state) (a) and isolation (Soi for OFF state) (b) between port 1
and port 2 . Solid lines are insertion loss (S3 1 for OX state) (a) and isolation ( S31
for OFF state) (b) between port 1 and port 3.
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184
O
30
rrecuer.cviG r.z'
Figure 6.15: Simulared S-parameters of the Y-junction MEMS switch. Airgap is
3 fun.
Port 4
Figure 6.16: Layout of a 4-port MEMS switch.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
185
Figure G .li: Lumped-element model of the 4-port MEMS switch.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
186
o
i a
•T
tr.
isncvtC
(b)
Figure 6.18: Insertion loss (a) and isolation (b) for off-state between port 1 and
2 . and between port 1 and port 3 (dotted line) for the 4-port MEMS switch.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 7
Sum m ary and Future Works
7.1
Sum m ary
7.1.1
Flip-chip interconnects
A lumped-element model of flip-chip interconnects in CPW circuits lias been
developed based on 3-D FEM simulation results and verified by measurements.
The effect of the mother substrate in a flip-chip assembly on the RF performance
of the chip circuit has been characterized. Also, the bump height effect has been
discussed. The height of bumps in flip-chip assemblies affects the RF performance
of flip-chip assemblies by two ways: it affects values of elements in the lumpedelement model of the flip-chip interconnects, and it determines the airgap between
the substrate and motherboard, which changes the substrate effect.
Underfill epoxy has been added to reduce the stress on bump joints and in­
crease their fatigue lifes. Characterization of flip-chip interconnects with underfill
has been performed. The additional CPW line loss due to the underfill (Epoxy
U300) is less than 0.5 dB/cm at 40 GHz and the change in the phase delay due to
the underfill is a 22 degrees/cm at the same frequency. Redesigning dimensions
of CPW lines on chip can compensate for the phase delay.
7.1.2
RF M EM S
RF MEMS Tunable Capacitors:
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188
Two kinds of MEMS tunable capacitor configurations, series-mounted and
shunt-mounted, have been investigated. Lumped-element models have been de­
veloped for these two kinds of MEMS capacitors. The effect of actuators on RF
performance has been characterized for the two kinds of capacitor designs as well.
Factors affecting the self-resonance frequency have been analyzed and methods
AAACACcl^AAAJS,
-U ~
LHC
c
J C A i- l CL3C/IK111CC
... u
tA C '^ju C H L V
i
UCtVC
UCCU
j
3LU UAC U
n
rr \
I U I At l
ttta
rc
.VAJ_-.'A-J
L t ip a v *
itor designs. The surface impedance of the multilayer metal has been computed
using a transmission line model to predict Q-factors of MEMS capacitors. From
these characterizations, design rules (sections 4.3 and 5.31 for RF MEMS tun­
able capacitors have been developed. Following these design rules, series-mounted
and shunt-mounted MEMS tunable capacitors with electrothermal actuation have
been designed and tested. Excellent RF performances have been obtained from
these RF MEMS tunable capacitors. For the shunt-mounted RF capacitor with
MEMS plate 200 x 300 /mi. the measured loss (resistance R) is 0.14 Cl. the mea­
sured capacitance is 0.275 pF. and the Q-factor is approximately 380 at
10
GHz.
The self-resonant frequency is above 40 GHz. which is the upper lim it of our mea­
sured frequency range. The tuning ratio i based on simulations i is approximately
•5:1. For the series-mounted RF
capacitor with a
2 0 0
x 300//m MEMS plate,
the measured loss (resistance R) is 4.2 Cl. the measured capacitance is 0.331 pF
with 0 volts bias voltage, and Q-factor is approximately 114 at 10 GHz. The
measured tuning ratio is approximately 2 .6 6 : 1 with bias voltage varied from
0
to
2.5 volts. Self-resonance frequency is 14 GHz when bias voltage is 2.5 volts and
the capacitance is 0.S8 pF.
RF MEMS Multiway Switches:
A design concept for multiway MEMS switches has been developed. Electro­
static actuators have been used for our switch designs due to their faster switching
speed compared with electrothermal actuators. Bias voltages for electrostatic ac­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
189
tuators are 20 to 25 volts in our design. A 2-port switch has been designed and
improved by using the design method. A lumped-element model has been ob­
tained for 2-port switches and used to optimize the 2 -port MEMS switch design.
The simulated insertion loss of the 2-port MEMS switch is 0.1 dB at 14 GHz and
isolation is 22 dB at the same frequency. 3-port and 4-port MEMS switches have
been rhararrpn.zpd and lumped-element models have been developed. Optimiza­
tions of 3-port and 4-port MEMS switches need to be carried out.
7.1.3
D esign procedure and role of m odeling
A design approach has been developed for RF MEMS device design includ­
ing RF and mechanical design considerations, which is depicted in the conceptual
flow chart shown in Figure 7.1. An initial design is developed based on the physical
understanding of this device operation. Then the RF modeling and mechanical
characterization of the RF MEMS device are carried out to optimize RF and
mechanical performances. The next step is the overall evaluation of RF MEMS
performance followed by the fabrication and asM’tnblv. Next. RF and mechanical
measurements are performed and measured results are then analyzed and com­
pared with simulations. Based on the analysis. RF and mechanical designs are
improved. If the results are not satisfactory, the improvement process (Part A in
Figure 7.1) is repeated until a satisfactory result is obtained. The approach, which
includes the parallel design and characterization for RF and mechanical parts, en­
ables us to reach the design goal faster when the design is multidisciplinary and
requires a good team effort (see Chapter 4 for example).
In the RF design of RF MEMS devices, modeling is the key step in the
improvement procedure. The general RF design procedure is shown in Figure
7.2. Taking the 2-port MEMS switch design as an example (see section 6.1.4
in Chapter 6). from the initial conceptual design of the MEMS switch an initial
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
190
physical layout is developed. RF performances of different physical layouts are
compared by using 2-D or 3-D EM simulation (such as. HP-momentum or HFSS).
Also, from the physical layout a lumped-element model is developed. Values of
these elements are obtained by comparing responses of lumped-element models
with EM simulation results. Optimum values of these elements are found from
analytic or network simulation (MDS). The physical layout is optimized based on
these optimum values. Then, the design is finalized (see Figure G.7). RF modeling
not only allows us to understand MEMS devices deeply but also makes RF design
improvement simpler and faster.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
191
lr.it.ai design naiCil .ie\:ce ^peraitar. I
RF par:
j
M ecnar.:jai ? i r
*
i
S irr. a ■ai:on a: m adding
j
a :m u.Mien
a:
characterization
(Hera!, tva.uatior. o' MEMSpertorir.an*? ;
Funr:;anor. and as'cairO
j MgjPar.u'al rneusurerr.cr.:
R r : easurcrr.cn
Sansi'actorN
A <
r r ' ” >erT’ en
ly{'* R F :•'err.’
rman.r
I
•me:r.an;»j. *er.as;•• |
Mdd:;:cJ it*
Figure 7.1 : Flow chart for RF part of MEMS device design.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
lninal design
P h \ siea 1 l a y o u t
E M simulation
L um p ed -elem en t moue!
L u m p e d parame'.er values
O p t im iz a t io n using n e m o r k s im u lato r
I
Im p ro v e d phvsical lavout
T
A n a iv si
A <
Satisfactory
Final desisn
Figure 7.2 : Conceptual flow chart for design of RF MEMS.
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193
7.2
Suggestions for future works
7.2.1
Flip-chip interconnects
Characterization of flip-chip interconnects at higher frequencies (above 40
GHzi need to be carried out to explore high frequency behaviors/limitations of
flip-chip interconnects in CPW circuits. This will suggest improvements of the
flip-chip interconnect for RF performance at higher frequencies. A flip-chip single
joint is very difficult to measure directly due to its structure. So we only have
measured whole flip-chip assemblies. However, if a two-tier TRL calibration set
is developed and used, the measured results for the single flip-chip joint can be
obtained from two-tier de-embedding. which removes the effect of CPW line on
the chip 9S\
7.2.2
RF MEMS
MEMS tunable capacitors:
Series-mounted capacitors: The length and width of the MEMS plate in the
series-mounted capacitor design can be optimized to obtain a higher self-resonance
frequency. Also, using gold bumps instead of deposited indium bumps can reduce
the loss (R) of the MEMS capacitor further. The tuning ratio can be improved
further by increasing the movement of thermal actuators.
Shunt-mounted capacitors: Connecting actuators to RF ground, which in­
creases the capacitance, results in a higher loss at low frequencies. This loss can
be reduced in two ways: ( 1 ) reducing the resistance of actuators and increas­
ing the inductance: (2 ) increasing the capacitance between the MEMS plate and
ground plane (as discussed in section 5.4). However, these methods involve design
trade-offs between RF and mechanical performances. A balance among trade-offs
needs to be maintained carefully to reduce the loss at low frequencies and also
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
194
keep good mechanical performance.
Tuning ratios of series-mounted and shunt-mounted capacitors can be im­
proved further by increasing the movement of thermal actuators. Future research
also should involve modifications of these designs in MEMS tunable capacitors for
special applications such as tunable bandpass filters, voltage controlled oscillators.
*
rinsiiog phiisc shifters, etc.
MEMS Multiway Switches:
Optimizations of 3-port and 4-port switches need to be performed based on
the design method and initial designs, which have been discussed in Chapter G.
Fabrications and measurements of these switches need to be carried our. More
multiway switches. 5-porr to S-port switches can be characterized and optimized.
Research reported in this thesis can form the basis of a methodology for the
design of electrothermally and electrostatically actuated RF MEMS devices.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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