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RF /microwave integrated passives for system on package module development

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R F /M ic r o w a v e In t e g r a t e d P a s s i v e s
for
Sy stem
on
Package M o dule D evelopm ent
A Thesis Presented to
The Academic Faculty
By
Mekita F. Davis
In Partial Fulfillment
o f the Requirements for the Degree
Doctor o f Philosophy in Electrical and Computer Engineering
Georgia Institute o f Technology
July 2003
Copyright © 2003 by Mekita F. Davis
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UMI N um ber: 3095713
UMI
UMI Microform 3095713
Copyright 2003 by ProQuest Information and Learning Company.
All rights reserved. This microform edition is protected against
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R F /M i c r o w a v e In t e g r a t e d P a s s i v e s
fo r
Sy st em
on
Pa c k a g e M o d u l e D ev e l o pm e n t
Approved by:
■y May1
C—xzz. €1
g - ...
Dr. Emmanouil M. Tentzeris
Date Approved
i f D 3
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for
R F /M ic r o w a v e In t e g r a t e d P a ssiv es
S y st em o n P a c k a g e M o d u l e D e v e l o pm e n t
Mekita F. Davis
92 Pages
Directed by Dr. Joy Laskar
This thesis reports the first comprehensive design and analysis of integrated RF
passives developed for next generation, low cost and high performance materials used in
a multilayer packaging environment for System on Package (SOP) technology. Novel
hollow ground plane (HGP) inductors are introduced and demonstrate superior
performance to their on-chip counterparts and comparable performance to their expensive
multilayer technology counterparts. The first reported inductor library including the use
of a design of experiments and statistical analysis approach for multilayer passives
implemented in Liquid Crystal Polymer (LCP) Technology is presented. This approach
allows comprehensive quantification of the effects of the inductor factors, which leads to
prediction and optimization of the important electrical characteristics of the RF
structures. In addition, compact filter topologies for RF module development are
demonstrated. These building blocks demonstrate feasibility of efficiently integrating
quality passives for System on Package Technology, ultimately eliminating the need for
discrete passives. Multilayer Organic and LCP process technologies are presented as
strong candidates for future RF modules and the realization of System on Package.
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This thesis is dedicated in loving memory of my grandmother,
Lizzie L. Banyard, who I know is my angel right now looking over me.
iii
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ACKNOWLEDGEMENTS
Wow! Who would have ever thought I would have made it this far. I would like
to thank God for his many blessings and strength through my entire academic career and
life thus far. I know with Him, my future is very bright. I am sure it was a part of his
master plan to have me as a member of Dr. Joy Laskar’s group, which has truly been a
unique and unparalleled experience.
I thank Dr. Laskar, for instilling in me the
importance of excellence and great work. From being in his group, I have had the honor
of a number of publications as well as conference experiences including my last Student
Paper Competition experience. I would like to thank the rest of my committee members
Dr. Tentzeris, Dr. May, Dr. Rhodes and Dr. Kohl for being patient and stepping in when I
needed it. I would like to thank the entire Microwave Applications Group (past and
present) especially, Dani, Albert, Babak, Ade, Neeraj, Eddie, STS, Chang-ho, Rana,
Kyutae and Stephane. Special thanks to Dr. Tentzeris and extended Athena family. You
all have given me memories that I will forever cherish
For many years school and the National Society of Blacks Engineers were
synonymous to me. I appreciate NSBE for helping development my leadership skills. I
will forever be thankful for the support and great network of people. Included in this list
of greats would be Dr. Gary May who initiated my interest in graduate school through his
dedication to graduate education through the SURE program. Without Dr. May, I could
have never been Graduate Student of Year. Thanks.
I would like to thank the Lucent
Bell Labs CRFP program, including mentor On-Ching Yue. I cannot forget to thank the
GEM Consortium. NACME, Motorola, General Motors have also been supporters that I
will always remember.
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To my mom and my dad, thanks for instilling in me the values that helped me to
arrive at this point in life. It couldn’t have started here; it is all because of you dedication
and support in all that I ’ve ever done. To my grandma, granddad, godparents, and
brother, I love you. To my aunts, Patricia, Prentess, Willimina, Mira, and uncle Ardie
Jr., I love you. To my cousins Donell, Shaunte", Kia, Ardie and Alan, I love you. To my
extended family, it’s just too many of you to name, but I love you just the same. To
Penny and Cyrita, thanks for being there.
Last but not least, good friends are hard to find. I would like to thanks those who
helped me endure this experience one way or another and remained my friends even
though I couldn’t hang out most of the time: my best friend, Dr. Jennifer L. Barnes of
almost 20 years, Erica Anthony, Tiffany Leginton, Dr. Raheem Beyah (who’s
competitive spirit kept me motivated), James Pritchett, Craig M. Garrett, Larry Luv, Dr.
Pinkett, Dr. and Mrs. Robinson, Devon and the Vatanna Gaines family. I can’t forget
about my GT Lorraine peeps, Corey Turner and Mary Spio. Thanks to Third Baptist and
Destiny Metropolitan for keeping me grounded.
v
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TABLE OF CONTENTS
Chapter I:
Introduction................................................................................................1
Chapter II: System on Package (SOP) Technologies...................................................4
2.1.
MCM-C....................................... , ....................................................................5
2.2.
MCM-D............................................................................................................. 7
2.3.
MCM-L.............................................................................................................. 8
2.4.
Multilayer Organic Packaging Technology...................................................13
2.5.
Liquid Crystal Polymer Packaging Technology........................................... 14
Chapter III: Inductor Library.......................................................................................17
3.1
3.2
Multilayer Inductors........................................................................................17
3.1.1
Hollow Ground Plane (HGP) Investigation.................................... 21
3.1.2
Measurement and Modeling........................................................... 25
CPW Inductor Library.................................................................................... 29
Chapter IV: Design of Experiments and Statistical Analysis..................................... 39
4.1
Design of Experiments: HGP Inductor..........................................................39
4.2
Basic Experiment........................................................................................... 41
4.2.1
Analysis of Variance: HGP Inductor..............................................44
4.2.2
Analysis of Variance: Parasitic Elements...................................... 48
4.2.3
Summary of Effects........................................................................ 49
4.3
Statistical Model Development..................................................................... 53
4.4
Sensitivity Analysis........................................................................................ 57
Chapter V: Passives Components for Module Development....................................60
5.1
Low-pass Filter (LPF) Design....................................................................... 61
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5.2
Bandpass Filter (BPF) Design...................................................................... 63
5.2.1
Square Ring Resonator BPF............................................................. 64
5.2.2 Square Patch PBF..............................................................................67
5.3
Module Implementation.................................................................................67
5.3.1
C-band Transmitter............................................................................68
5.3.2 Intelligent Network Communicator (INC).......................................71
Chapter VI: Conclusions.................................................................................................73
Chapter VI: Future Work...............................................................................................75
Appendix A.......................................................................................................................76
Appendix B.......................................................................................................................79
Appendix C: Publications Resulting from Thesis Work............................................. 86
References.........................................................................................................................89
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LIST OF TABLES:
Table 2.1.
Summary of enabling SOP materials and their properties........................... 13
Table 3.1.
Summary of extracted circuit parameters of two-turn MLO-based
FGP and HGP inductor..................................................................................25
Table 3.2.
Effective inductance of HGP inductors with varying hollowsize.............. 29
Table 3.3.
Summary of measured Q, L, and SRF of LCP CPW inductors..................37
Table 4.1.
Variables for 26'1based experiments............................................................. 42
Table 4.2.
The 2 61 experiment....................................................................................... 43
Table 4.3.
ANOVA table for Qmax.................................................................................. 44
Table 4.4.
ANOVA Table for Inductance.......................................................................45
Table 4.5.
ANOVA table for SRF................................................................................... 45
Table 4.6.
Summary of significance effects....................................................................47
Table 4.7.
F-statistic for inductor parasitics....................................................................48
Table 4.8.
P - values of factors for model development................................................54
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LIST OF FIGURES:
Fig 2.1.
An example of an LTCC test board containing embedded passives,
antennas, and module.......................................................................................7
Fig. 2.2.
MLO test boards containing transmission lines, inductor library,
embedded passives for module development,
and an antenna.................................................................................................10
Fig.2.3.
LCP test boards containing transmission lines, embedded passives
for module development and antennas.........................................................12
Fig.2.4.
Cross-section of MLO technology for SOP integration...............................14
Fig.2.5
Fabricated CPW transmission lines............................................................... 15
Fig.2.6.
Measured S-parameters of LCP 200 mil long CPW line.............................16
Fig.3.1.
Typical inductor behavior...............................................................................19
Fig.3.2.
One-port inductor electrical model used for performance optimization.. .20
Fig.3.3
A three-dimensional view of full ground plane (top) and hollow
Ground plane (bottom) inductor topology...................................................22
Fig.3.4.
Photograph of four-turn MLO-based HGP inductor.................................... 23
Fig.3.5.
Measured Q(top) and Leff (bottom) FGP and HGP
implementation of a one-turn and six-turn inductor................................... 24
Fig.3.6.
Measured and circuit simulated Q (top) and Leff (bottom)
of a two-turn MLO-based FGP and HGP inductor..................................... 26
Fig.3.7.
Photograph of LCP-based HGP inductor library..........................................27
Fig.3.8.
Measured and circuit simulated Q and Leff of a one-turn
LCP-based HGP inductor..............................................................................28
Fig.3.9.
Measured Leff of LCP-based HGP inductors with varying
hollow area..................................................................................................... 28
Fig.3.10
Photograph of LCP-based CPW inductor library.........................................29
Fig.3.11.
Measured and circuit simulated Q and Leff LCP-based
CPW inductor.................................................................................................30
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Fig.3.12.
Maximum quality factor for conductor width = 3,4,5, and 6
versus radius.................................................................................................. 31
Fig.3.13.
Inductance (top) and SRF (bottom) for conductor width - 3,4,5, and 6
mils versus radius........................................................................................... 32
Fig.3.14.
Maximum quality factor for ground plane width = 4, 8, 16 and 20 mils
versus radius....................................................................................................33
Fig.3.15.
Inductance(top) and SRF (bottom)for ground plane width = 4, 8, 16, 20
mils versus radius........................................................................................... 34
Fig.3.16.
Maximum quality factor for ground plane spacing = 5.5, 8, 16 and 20
mils versus radius........................................................................................... 35
Fig.3.17.
Inductance and SRF for ground plane spacing = 5.5, 8, 16 and20 versus
radius............................................................................................................... 36
Fig.4.1.
Top view of HGP inductor with layout parameters.....................................41
Fig.4.2.
Layout 32 treatment combinations for 26' 1based experiments...................42
Fig.4.3.
3-D contour plot of Q ....................................................................................51
Fig.4.4.
3-D contour plot of inductance (top) and SRF (bottom)..............................52
Fig.4.5.
Pareto Chart of Q (top) and inductance (bottom)........................................ 56
Fig.4.6.
Pareto Chart of SRF........................................................................................57
Fig.4.7.
Sensitivity analysis of Q ................................................................................ 58
Fig.4.8.
Sensitivity analysis of inductance (top) and SRF (bottom)........................ 59
Fig.5.1.
T-network for lowpass filter..........................................................................62
Fig.5.2.
Photograph lumped element 750MHz LPF..................................................62
Fig.5.3.
Measured and MOM simulation of lumped element 750MHz LPF.......... 63
Fig.5.4.
Schematic of one coupling gap square ring resonator BPF........................ 64
Fig.5.5.
MOM simulation of square ring resonator 5.8 GHz BPF........................... 65
Fig.5.6.
Photograph of square ring resonator 5.8 GHz BPF.....................................66
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Fig. 5.7.
Schematic diagram of a transmitter module.................................................68
Fig. 5.8.
Magnitude of return and insertion loss of BPF for c-band
transmitter module......................................................................................... 69
Fig.5.9.
Photograph of implemented MLO-based c-band transmitter module....... 70
Fig.5.10
Photograph of implemented stripline filter for module development.......70
Fig.5.11.
Schematic of INC system architecture.......................................................... 71
Fig.5.12.
Layout of analog block for INC system........................................................ 72
Fig.5.13.
Photograph of fabricated INC board............................................................. 72
Fig. A1.
Process variation usingl5pm dielectric thickness....................................... 75
Fig. A2.
Process variation using 30pm dielectric thickness...................................... 75
Fig. A3.
Process variation using 3pm metal thickness.............................................. 76
Fig. A4.
Process variation using 12pm metal thickness............................................ 76
Fig. B 1.
Pareto Chart of Q for rectangular spirals......................................................80
Fig. B2.
Pareto Chart of inductance (top) and SRF (bottom) for rectangular
spirals.............................................................................................................. 81
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SUMMARY
This thesis reports the first comprehensive design and analysis of integrated RF
passives developed for next generation, low cost and high performance materials used in
a multilayer packaging environment for System on Package (SOP) technology. Novel
hollow ground plane (HGP) inductors are introduced and demonstrate superior
performance to their on-chip counterparts and comparable performance to their expensive
multilayer technology counterparts. The first reported inductor library including the use
of a design of experiments and statistical analysis approach for multilayer passives
implemented in Liquid Crystal Polymer (LCP) Technology is presented. This approach
allows comprehensive quantification of the effects of the inductor factors, which leads to
prediction and optimization of the important electrical characteristics of the RF
structures. In addition, compact filter topologies for RF module development are
demonstrated. These building blocks demonstrate feasibility of efficiently integrating
quality passives for System on Package Technology, ultimately eliminating the need for
discrete passives. Multilayer Organic and LCP process technologies are presented as
strong candidates for future RF modules and the realization of System on Package.
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CHAPTER I
INTRODUCTION
For emerging wireless communication systems, we see an important trend toward
more flexible and wideband applications toward higher carrier frequencies. These
applications in the RF/microwave/millimeter wave regimes require miniaturization,
portability, cost and performance as key driving forces in this evolution [1].
Designing small, low-cost RF modules to meet these needs is challenging but these
modules are required to meet these future wireless applications. Investigations on the
System-on-Package (SOP) approach for module development have become a primary
focus due to the real estate efficiency, cost-savings and performance improvement
potentially involved in this integral functionality.
The demands for wireless portable devices such as network interface cards require
compact highly integrated radio front-end systems. In most of the presently used RF
front-end architectures, complete system integration has not been achieved. Many single­
chip solutions still need external components for impedance matching, power amplifiers,
RF bandpass filters (BPFs), etc [2]. Silicon IC technology is attractive due to its lowcost.
However, it has performance limitations, especially regarding the efficient
integration of passive components. External components such as the antenna and passives
used for impedance matching, for instance, are still needed.
Another area of
concentration includes the actual design of passive components to reduce the overall
module size and weight. Passive development is extremely important in terms of
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performance, compactness and cost advantages [3], since wireless front-end systems are
using a considerable amount of passive components. In conventional microwave
integrated circuits, the passives are surface mount devices, consuming a large area and
yielding a high mounting cost [4]. Design flexibility and optimized integration can be
achieved with multilayer substrate technology in which ‘free’ vertical real-estate is taken
advantage of. In this configuration, an antenna and embedded passives, for example,
may all be integrated together on the same package allowed by the various layers of
metals and dielectrics.
The objective of this research is to develop RF passive design methodologies for
SOP applications taking advantage of superior multilayer packaging processes. In the
effort to realize complete integrated wireless communication front-end systems,
embedded passive components, including the design of compact high Q inductors, which
are required for low-power, low-noise, and high bandwidth portable [4]
RF and
microwave applications are investigated. Design of experiments is performed to
understand and optimize the layout parameters. In addition to individual passive device
implementation, complete passive RF front-end functional building blocks, such as filters
are studied.
Original contributions reported in this dissertation include:
1.) First development of compact multilayer organic-based hollow ground plane
inductors demonstrating a high Q.
2.) First development of compact liquid crystal polymer-based inductor library
demonstrating record high frequency band of operation among the available
commercial SOP technologies.
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3.) First application of a design of experiments method and statistical analysis for
RF passives in multilayer packaging environment.
4.) First demonstration of complete passive RF front-end functional building
blocks implemented in organic for SOP module development.
Chapter 2 covers some of the available SOP technologies in detail. In chapter 3, we
investigate performance of multilayer organic (MLO) and liquid crystal polymer (LCP)based inductors, including the enhanced Hollow Ground Plane implementation, by
design, fabrication and characterization. Chapter 4 focuses on design of experiments and
statistical analysis o f a hollow ground plane (HGP) inductor in terms of achieving a
scaleable electrical model. Chapter 5 highlights RF passive functional blocks developed
for integration in SOP modules including transmitter and Intelligent Network
Communicator modules. All passive structures have been simulated using a commercial
Method of Moment (MoM) simulator [5].
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CHAPTER II
SYSTEM ON PACKAGE TECHNOLOGIES
System on Package (SOP) is a single component, multi-function, multi-chip
package providing all the needed system-level functions including analog, high speed
digital, RF, and MEMs. It has become a major thrust in electronic packaging because it
offers great promise as a thin, portable, high-performance/density electronic package at
low cost [6], The major building blocks for SOP technology are ultra high-density wiring
on substrates, a reliable flip-chip technology, and embedded passives within the dielectric
layers on the substrate [7].
New systems will continue to challenge packaging
technology due to increased performance requirements, higher densities, higher
temperatures, and limited space available. This challenge mandates the use of unique
packaging techniques that must not only provide the increased circuit density but also
reliability, electrical performance, thermal management and hermeticity [8]. Using SOP
technology, these needs can be addressed, including the integration of small but
expensive MMICS into a much cheaper environment to become a multichip module [9].
The major advantages over individual packaged parties include: 1) higher packaging
efficiency due to closer placement of bare chips [10]; 2) better electrical performance,
due to shorter wiring lengths between closer placement of chips [10]; 3) greater reliability
due to the reduced number of interconnects between chip and board [10]; 4) lower cost,
resulting from the replacement of individual discrete components with embedded
passives [10,11]; 5) design flexibility with realization of high-Q embedded passives [11];
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6) reduction in module size by adopting multilayer topology [11]; 7) easy to realize
multi-functional RF modules in a single package [11].
Single chip solutions have also been studied and are difficult and even impossible
to obtain on standard silicon substrate, since electrical losses are detrimental for systemon-chip (SOC). Silicon technologies suffer from limited performance because these
losses affect the quality of interconnects and on-chip passives, especially inductors. SOC
realizations typically have lower self resonance frequencies, which is a natural
consequence of the fact that these technologies and the used materials are not optimized
for the passive devices, but for the active ones [2].
There are currently three multi-chip module (MCM) technologies that can employ
System on Package concept in order to meet the requirements of consumer products
ranging from household products to high performance electronics and mobile
communications [17]. According to the types of substrates, the MCM technologies are
divided into three basic styles: MCM-C, thick-film or co-fired ceramic technology;
MCM-D, deposited thin-film multilayers; and MCM-L, based on organic laminate
technology [10].
2.1 MCM-C
Multilayer ceramic technology has evolved from traditional thick film fabrication
to co-fired stack of ceramic green sheets on which metal wiring is printed and vias are
punched for interlayer connections. It is a thick film process, therefore having limited
wiring density. As a result, the ability to have highly integrated, high-speed chips is
limited. Unlike other technologies where sequential printing, drying, and firing of each
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layer is required; it has parallel process steps (i.e. all layers are punched, printed, and
dried in parallel), like PWB technology, so green sheets can be inspected. As a result
optimum yield and cost effectiveness are achieved, since each process is not dependent
on the previous process [4], It is considered a low to medium cost process, fired at low
and high temperatures. Ceramics are generally regarded as high performance materials
because o f their hermeticity, high reliability, low CTE, and low losses.
These
characteristics along with the ability to achieve as many as 50 to 60 ceramic tapes make
low and high temperature co-fired ceramics, LTCC and HTCC, respectively, currently
the most popular technologies to implement singe-package designs.
LTCC is a type of glass ceramic process and is gaining popularity because it can
be processed at lower temperatures than normal co-fired temperatures. Unlike high
temperature co-fired ceramic (HTCC), LTCC process allows the use of high low
resistivity [2]metals such as silver and gold since the melting point of these metal is well
above the temperature at which the LTCC stack is fired. In HTCC processes, the stacked
tape is fired at a much higher temperature, requiring the use of metallization having an
even higher melting point, and in many cases less conductivity than silver or gold used in
LTCC. One of the limitations of LTCC is shrinkage control [4], which the industry has
addressed with improved fabrication and technology. Even though the cost is higher
compared to FR4, for example, LTCC technology offers many features that are beneficial
for high reliability MCM applications. Examples of implementations on LTCC include
PA [13], RF front-end modules including receiver [14], and transmitter [15] including the
use of pBGA technology [16]. Figure 2.1 gives an example of an LTCC test board
containing baluns, filters, antennas, and PA module.
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Fig.2.1. An example of an LTCC test board.
2.2 MCM-D
MCM-D is a thin-film process where metal, typically Cu or Al, and dielectric
layers, typically polyimide or benzocyclobutene (BCB), are fabricated by sequential
deposition on a substrate base made of ceramic, silicon, or metal [17]. Promising
developments have been made because of its excellent dimension control and the use of
high quality materials [18]. Copper metallization many be combined with very low loss
dielectric materials in a thin film IC-like manufacturing process. In this way, both
resistive and dielectric losses can be kept to a minimum, making it more feasible for
higher frequency applications as well as high quality passive structures. It offers a
substantial increase in packaging density compared to thick film.
Spin coating is
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typically used to deposit the thin dielectric layers (1-20 um), which are patterned by
etching.
Electroless plating and electroplating may also be done.
Much lower
temperature is required for curing as compared with LTCC. Temperatures range from
200°C (BCB) to 400°C (polyimide)[300].
Extremely high wiring density can be
achieved with widths and spaces of the conductors ranging from lOOum down to a few,
depending on the metal thickness. The material has excellent electrical characteristics. It
is a specialized technology with only a few suppliers. The combination of superior
materials and small feature sizes potentially enables MCM-D to have future dominance in
the MCM arena as the clear leader in high density and circuit speed. However, it is the
most process intensive and expensive of the three MCM technologies. Reduction of
fabrication costs is needed for MCM-D substrates to compete against the widespread
MCM-L and PCB technologies. Detailed investigations revealed that the problem is
located in today’s use of equipment and today’s size of process panels [19] Examples of
implementation in this process include mm-wave microstrip patch and slot antennas [20],
embedded passives to V-band, and RF front end module [17].
2.3 MCM-L
MCM-L is derived from conventional printed wiring board (PWB) technology.
The laminate layers are covered with metal, which are then patterned to form the
conductors, with plated through-hole or via interconnecting the layers. It is the least
expensive to implement. The label MCM-L refers specifically to the technology used to
manufacture the wiring platform. The platform can be used to interconnect ICs, as a pure
stand-alone MCM or to build up a complex circuit board containing many different
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components, active and passive [10]. Once populated, the MCM-L uses organic coating
to protect the chips and their bonds, as well as the components and the entire board. [10]
The copper comes laminated to the core material. PWBs utilize holes drilled through the
entire board thickness to electrically connect the desired metal planes, and the patterned
conductor layers that intersect the hole. Although the MCM-L offers the lowest density
and slightly lower performance than the other three major MCM technologies, it is
widely used due to its low cost [23] Power amplifiers, VCO with printed and integrated
inductors, respectively, and 1.8GHz transceiver have been implemented [22] The density
limitations, however, are due in large part to the need of plated through-holes and
thickness o f basic laminate layers; therefore, creating a great need for an organic
substrate of MCM-Ls with high density [23]. This issue is being addressed with the use
of advanced PWBs, which are based on the development of a built up MCM-L where
thin-film multilayer signal layers are placed on either side of PWB core. This is the
natural evolution of PWB technology, which require high wiring densities due to the
elimination of thru holes except in core and MCM-D technology, which requires cost
reduction. Built-up technologies can be considered a merger of these 2 technologies.
A multilayer organic process developed at Georgia Institute of Technology is an
example of this built-up technology. Organic materials have gained widespread use in
electronics because o f their low cost, good dielectric properties, reasonable mechanical
properties, and ease of processing. The thinner films (10-50) um used in new organic
build-up technologies also offer the ability to design and implement ultra-high density
wiring required to package emerging and future high I/O chip technologies.
Organics
do present limitations due to higher loss tangent, high coefficient of thermal expansion
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(CTE), and low thermal conductivity.
Figure 2.2 shows examples of MLO test boards
containing transmission lines, inductor library, antennas, and embedded passives for
module development.
Fig.2.2. Examples of MLO test boards.
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As have been described earlier, there are various MCM technology available
based on the particular characteristics needed to meet a specific application. Among these
technologies, MCM-L has provided remarkable cost and weight savings due to the
incorporation of low-cost materials and processes [12], MCM-D provides the highest
resolution in line and spaces due to the thin film processes, however, processing lower
cost MCM-D is a major challenge to the semiconductor industry today.
MCM-C
provides an intermediate resolution and had been used for high density packages as early
as 1980s [12]. One overarching goal, however, is that manufacturers must solve a
difficult task of maximizing system performance while minimizing cost of product
development and production. Liquid Crystal Polymer (LCP) seems to be emerging as a
candidate to meet these needs.
LCP offers the same advantages as organics while also possessing better electrical
characteristics.
One advantage of LCP is that copper metallization may be combined
with low-loss dielectric material using a standard, low cost PCB-type process.
In this
way, highly conductive copper for the metal minimizes ohmic losses. Dielectric losses
may also be kept very low, allowing the realization of high Q passive structures. LCP is
highly attractive for RF packaging due to its low loss and nearly steady dielectric
constant over a wide frequency range, near hermitic plasing sealing due to superior
moisture barrier properties, flex circuits, and microvia laminates for high density
interconnection [24], Thermal characteristics include a combination of low coefficient of
thermal expansion (CTE), as low as 8 ppm/°K [25], and higher modulus, which
minimizes any issues relating to warpage and stress. LCP is very stable up to its high
melting temperature. Superior performance of integrated passives can be achieved using
11
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
this technology. LCP provides overall flexibility, performance, and low-cost. It is also a
self-sustaining technology in which the substrate can eventually be eliminated. Sample
LCP test boards containing transmission lines, inductor library, antennas, and embedded
passives for module development can be seen in Figure 2.3.
QSHHOQB
HQQQQ0
s a a n noa'g'iBW i**® is
— i i i i ■ fe flS M M H M a f
==s h q d I M i g
H
-
BOO I g g g i w a H « « : d
Esses™noon - - ---- -i
st
El
I ..............
° I n i i u i / «*>««!
I
* iniiiilt
im
ikx
n
_ _ r i a i sss
X
I SSB
-------
§ tO ils s :.
Fig.2.3. Examples of LCP test boards.
12
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Process characteristics of technologies that have been used for SOP implementation are
summarized in Table 2.1.
Table 2.1. Summary of enabling SOP materials and their properties.
Material
Dielectric
Constant
Loss
Tangent
CTE
Cost
LTCC
5.6,
5.8 GHz
0.0012
5.8ppm/°C
Low/Medium
Dynavia
3.5,
5.8 GHz
0.026
55ppm/°C
Low/Medium
BCB
2.65,
10 GHz
2.9,
20 GHz
0.0008
42ppm/°C
High
0.002
(8-17) ppm/°C
Low
LCP
2.4. MLO Packaging Technology
A fully organic multilayer packaging process developed by Georgia Institute of
Technology’s Packaging Research Center offers the potential as the next generation
technology of choice for SOP RF-wireless, high-speed digital and RF-optical applications
[11]. The current SOP configuration is shown in Figure 2.4. It incorporates low cost
materials and processes consisting of a double-sided core FR-4 substrate laminated with
two thin organic layers on each side.
13
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig.2.4. Cross-section of MLO technology for SOP integration.
The thickness of the core substrate is 40 mils while the thickness of the laminate
layers are 2.46 mils each.
The integral passive components are fabricated within the
wiring structure of the SOP module, which consists of a three metal layer structure
including two layers of high density wiring metallization and two micro via levels.
Copper metallization of 10-18 pm and 100 pm diameter micro via process are used for
this multilayer interconnection structure. The minimum metal line width and spacing is 1
mil for the top two metal layers. Using this topology, high-density hybrid transition
schemes as well as various compact passive structures, including inductors, capacitors
and filters can be designed.
14
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2.5 LCP Packaging Technology
LCP is a fairly new material that can be used as a single sheeted or laminated
dielectric or as a substrate. It has superior loss, tan 5-.002 and CTE, (8-17) ppm/°K
characteristics compared to a comparable organic process with tan 8=.026 and CTE, (1520) ppm/°K. A process developed at Microconnex uses 4-metal layers employing 9 pm
thick copper, 50pm thick dielectric layers and 75 pm microvia process.
Coplanar waveguide (CPW) transmission line test structures have been fabricated
to assess the loss performance of this technology, (Figure 2.5.)
Figure 2.6 shows the
measured S-parameters of a 200 mil CPW line. A maximum insertion loss of 1.7dB/in at
23 GHz is demonstrated. This result is not the best reported.
In this case, metal
roughness is the most probable contributor to the additional loss. The CPW exhibits a
good match demonstrated by a minimum of 15dB return loss to 30 GHz. This result is
better than a CPW fabricated on a similar organic process[26]. For all S-parameter
measurements in this paper, a HP8510C network analyzer was calibrated using the
LRRM technique up to 30GHz. Cascade Microtech coplanar ground-signal-ground
probes were used.
25
50
100 mil lines
Fig.2.5. Fabricated CPW transmission lines.
15
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o
Insertion Loss (dB)
Return Loss (dB)
-10
-20
-30
-40
-10
-50
0
5
10
15
20
Frequency (GHz)
Fig.2.6. Measured S-parameters of LCP 200 mil long CPW line.
16
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER III
INDUCTOR LIBRARY
3.1 Multilayer Inductors
In addition to material performance, another critical aspect in the design of
passive components, which occupy the highest percentage of integrated circuit and circuit
board real estate, is the effort to reduce the module size. Inductors are important in that
they are the performance limiting component in important RF circuits, such as voltagecontrolled oscillators (VCO) phase noise, low noise amplifiers(LNA) bandwidth, and
passive filter loss [27].
In most of the conventional silicon technology (RFICs),
microwave integrated circuits (MICs) or MMICS, it is difficult to integrate the passives
efficiently with required the quality [28]. By using special materials and processing
techniques the Q on Si may be increased but is still limited to 20-35 [18]. Higher quality
values are needed to improve the microwave circuits’ performance benchmarks such as
insertion loss, gain, noise figure, and PAE. These issues can be addressed with multilayer
substrate technology while achieving the necessary design flexibility and optimized
integration. In this research, MLO and LCP technology uses copper metallization and low
loss dielectric materials in a cost effective way to embed passives efficiently, including
the realization of integrated spiral inductors with Q factors close to 100 at microwave
frequencies.
17
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The three figures of merit used to evaluate the inductor performance are the Q,
the effective inductance (Left) and the self resonant frequency (SRF) [29]. In all cases
high quality factor is of prime importance. The Q factor of an inductor is a measure of the
amount of energy stored compared to the energy loss. The degree from which the
inductor deviates from an ideal device is described by the quality factor, Q, defined by:
Q =
Im[Z]
,
(2.1)
,
(2.2)
Re[Z]
and the effective inductance,
L e ff,
by:
L eff
- Im[Z]
27lf
where Z is the measured device input impedance obtained from a one-port S-parameter
measurement. Since the device operating frequency in RF and microwave circuits are
well below the self-resonance frequency, the above definition is traditionally accepted.
However, since inductors may be used as two-port devices and terminals exhibit
unsymmetrical characteristics, one-port measurement data is an approximation.
Q is a total result of energy factors including magnetic energy stored in the spiral,
substrate loss factor as a result of energy dissipated in the substrate and finally reduction
in Q due to the increase in peak electric energy with frequency. Q is proportional to the
net magnetic energy stored, which is equal to the difference between the peak magnetic
and electric energies. An inductor is at self-resonance when the peak magnetic and
18
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
electric energies are equal [30]. Therefore, Q, vanishes to zero and the behavior of the
device is no longer inductive above this point of SRF, (Figure 3.1.) The quality factor
typically has the highest value at approximately one-fourth of the SRF [31].
iax
frequency
self-resonance
O-max
Fig.3.1. Typical inductor behavior.
A commonly used circuit model that captures the key elements of this behavior is
shown in Figure 3.2. The Q and SRF of a one-port inductor can be analyzed using this
one-port lumped element circuit model, where port-2 of the inductor is connected to
ground to derive the impedance looking into port-1. The model consists of an ideal L in
series with a resistor Rs to account for the conductor and via loss. The dielectric loss, the
substrate capacitance, and coupling capacitance between turns are represented by Rp, Cs,
and Cc, respectively. Since Cs and Cc are in parallel and Cc is not significant, the two can
be combined together into a single capacitor, Ceq for future analysis.
19
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In p u t p o rt
O
Cs
Rs
Fig.3.2. One-port inductor electrical model used for performance optimization.
The analytical expression of the inductor Q is given by [30]:
Htl
Rp+ [(w L /R s)2+ 1 ]R s
1
The resulting Q factor is affected by dielectric, conductor, and radiation losses.
Several aspects contribute directly to the distributed loss mechanisms including length
(number of turns), line width, turn shape, parasitic capacitance, metallization thickness,
and conductivity as well as substrate conductivity and dielectric constant [1],
In
general, for a simple turn inductor, as the area increases with the number of turns, Rs, Cs,
and Cc increases while Rp decreases. This topology therefore decreases in Q and SRF
significantly, while increasing the number of turns to achieve a higher inductance.
Ohmic losses appear as a result of both conductor skin and proximity effects. The
20
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
minimization of these affects can be achieved by using highly conductive materials. For
this reason, technologies have moved from aluminum to copper. Series resistance, Rs
takes these losses as well as radiation losses into account. Losses associated with the
ground plane and dielectric material are a result of both the electric field, which creates
conductive current through the material and the magnetic field, which induces eddy
currents [32]. The substrate capacitance Cs, which allows current flow, not only through
the metal strip [33], but also through the dielectric material and ground, has significant
impact on performance degradation.
Hollow ground plane (HGP) implementation decreases a large part of losses
associated with eddy current effect and capacitive coupling; therefore, superior
performance can be achieved while maintaining the size of the compact inductor
footprint.
3.1.1 Hollow Ground Plane Investigation
Close proximity of the ground plane to the inductor footprint reduces the effective
inductance due to negative mutual coupling caused by the current flowing in the ground
plane in the direction opposite to the inductor current flow. A multilevel ground concept
developed for an inductor library using LTCC is used to address this issue [34], The
HGP configuration creates a ground plane opening under the footprint of the inductor,
which decreases shunt parasitic capacitance and negative mutual coupling caused by
eddy current in the ground plane, thus resulting in higher Q and Leff. Figure 3.3 shows a
full ground plane (FGP) and HGP representation of simple rectangular spiral inductor.
Figure 3.4 shows a 4-tum HGP inductor implemented in MLO.
21
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig.3.3 A three-dimensional view of full ground plane (top) and hollow ground
plane (bottom) inductor topology.
22
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig.3.4. Photograph of four-turn MLO-based HGP inductor.
Simple one to six-turn inductors are designed and measured. Figure 3.5 shows a
Qmax of 18 for a 1-turn rectangular spiral inductor with a FGP implementation.
Leff of InH and SRF 15GHz.
It has a
The HGP implementation of the same inductor
demonstrates an increase in Q to 33 with Leff= 1.9nH, SRF=14GHz. As the number of
turns increase, the HGP configuration can result in a significantly higher improvement in
Q based on the proportionally larger reduction in parasitic capacitance. For a 6-turn
inductor the Q increased from Q=11 to Q=38, showing a three times improvement, which
is significantly greater than the increase in Q for the 1-tum inductor.
23
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
40
35
30
25
20
15
10
* - - 1-turn FG P
-e— 1 -turn HGP
5
■ • - -6 - tu r n FG P
■ • - - 6-turn HG P
0
0
1
3
2
4
6
5
Fequency, GHz
60
| * mT i
1I
r ""| - ‘
I
— • » - 1-turn f;;GP
50
o
V-
1-turn HGP
- - • - - 6 - t u r n FG P
- - • « - 6-turn HGP
40
30
I
U ..,,
20
i
t
10
rrrr. r-frr~. ■ i
1*= r
2
4
6
8
10
12
14
F re q u n c y , G H z
F ig.3.5. M easured Q (top) and Leff (bottom) FGP and HGP implementation of
a one-turn and six-turn inductor.
24
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Increasing inductance by increasing the number of turns causes degradation in Q and
SRF, while increasing the area occupied by the inductor. While Leff has increased from 1
nH to 12nH going from a one-turn to a six-turn inductor in the full ground plane
configuration, considerable decrease in Q and SRF is evident. However with HGP
implementation Leff can be increased, without compromising Q.
3.1.2 Measurement and Modeling
The proposed inductor model of the full ground plane (FGP) and HGP simple 2tum inductor shows an excellent correlation to the measured results. The values of L, Rs,
Rp and Ceq for both topologies shown in Table 3.1 are optimized to match the measured Q
and Leff. This correlation, as well as the HGP improvement, can be seen in Figure 3.6,
which shows the measured, and modeled Q of a FGP and HGP simple 2-tum inductor.
As can be seen from the table, the increase in Q is as a result of a significant decrease in
the metal series resistance, Rs, whose behavior at RF is governed by the eddy current
effect resulting from any conductive media close to the inductor [30]. Also the increase in
Rp reflects reduction in substrate loss, as the eddy currents in the substrate are more
significant with lower resistivity. The size of the inductor footprint is 1 x 1 mm2.
Table 3.1. Summary of extracted circuit parameters of two-turn MLO-based FGP and
HGP inductor.
Type
FGP
HGP
L(nH)
3.3
4.5
Rs(Q)
.6
.35
Rp(kQ)
7
10
C(pF)
.08
.074
25
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-T i t—i—r-T i
r i 1 r i,m
-]
»
i
i
t
f
o
80
—
•
r
••r r - r-"i i r i
i""
Modeled FGP
-M easured FGP
Modeled HGP
M easured HGP
?/
...
60
o
0
$
...O"
/
40
/'
......
/!
'A
'
A
20
t
...J
I
I
I
I
i,. .J
I
I---- L— I— I.....I
I...
3
4
Frequency, GHz
10
X
c
•
_
•
.
0
1
2
3
4
M odeled FG P
.M e a s u re d FG P
M odeled HG P
Me a s u r e d HGP
5
6
F re q u e n c y , G H z
Fig. 3.6. Measured and circuit simulated Q (top) and Leff (bottom) of a two-turn MLObased FGP and HGP inductor.
26
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A compact 30 X 25 m i l 2 HGP inductor implemented in LCP technology, shown
in Figure 3.7, has demonstrated measured Qmax>50 at 12GHz, Leff of .8nH and SRF as
high as 29GHz, which represents the highest reported frequency of operation to date in a
multilayer topology including MCM-D [4], LTCC [34], MCM-L [22], Measured and
modeled results can be seen in Figure 3.8. Another benefit of the HGP configuration is
that the Leff can be adjusted by increasing or decreasing the shunt parasitic capacitor, Cs
and negative mutual coupling due to the ground plane, which is achieved by decreasing
or increasing the area of the hollow ground plane opening, respectively. Decreasing the
HGP opening increases Cs therefore canceling part of the inductance. Increasing the
opening reduces Cs and increases Leff, while maintaining the size of the inductor
footprint. One-turn inductors of radius 9 mil and 12 mil, respectively, both implemented
9
9
with a hollow area of 10 x 10 mil and 20 x 20 mil , are measured. Figure 3.9 shows that
as the hollow area increases, Leff increases. The larger inductor (radius=12 mil) has an
even more significant increase in inductance due to the proportionally larger reduction in
parasitic capacitance, Table 3.2.
Fig.3.7. Photograph of LCP-based HGP inductor library.
27
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
12
60
-e— M easurement
Model
50
10
3
o
Q.
"5
C
aQ)
CD
"CD
3O
CD
S'
30
CJ
a
X
20
10
0
0
2
4
6
8
10
12
14
16
Frequency (GHz)
Fig.3.8. Measured and circuit simulated Q and Leff of a one-turn LCP-based HGP
inductor.
5
4
— e — HGP
--© --H G P
o
HGP
HGP
Inductor 1-small area hollow
Inductor 1
Inductor 2-small area hollow
Inductor 2
iC
oc
U
3
U
3
CD
c
2
O-
................
---© -
-
1
--o------“°“
€h
0
5
10
15
F re q u e n c y (G H z)
Fig.3.9. Measured Leff of LCP-based HGP inductors with varying hollow area.
28
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 3.2. Effective inductance of HGP inductors with varying hollow size.
HGP Ind 1 (radius = 9mil)
HGP Ind 2 (radius =12mil)
Leff (nH)
(area = 1 0 x 1 0 mil2)
Leff (nH)
(area = 20 x 20 mil2)
.9
1.3
1.2
1.9
3.3 CPW Inductor Library
High Q at the frequency range of interest can be obtained by designing compact
CPW inductors. The CPW spiral inductor has the same advantages of HGP microstrip
inductors; in addition, it avoids via losses and has reduced dielectric losses. As a result
high Q and Leff can be achieved. Figure 3.10 shows a photograph of a partial LCP-based
CPW inductor library. Figure 3.11 shows measured and modeled results of a compact 25
X 15mil2CPW inductor. It demonstrates a Qmax >90 at 6GHz, Leff of 1.3nH and 17Ghz
SRF.
Fig.3.10 Photograph of LCP-based CPW inductor library.
29
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
100
M easurem ent
Model
80
3
O
6 0)►
3
o
0
S'
o
o
CL
CD
60
CD
3
o
40
4
I
20
0
5
10
15
Frequency (GHz)
Fig. 3.11. Measured and circuit simulated Q and Leff LCP-based CPW inductor.
Basic CPW spiral inductors were designed and measured with variations that include
spiral radius (inductor size), coil width, ground plane spacing, and ground plane width.
The spiral radius was varied at 5, 10, 15 and 20 mil. Each of them was implemented with
coil width o f 3, 4, 5 and 6; ground plane spacing of 5.5, 8, 12, 16 and 20 mil; and ground
plane width of 4, 8, 12, 16, and 20.
In d u c t o r R a d i u s
For all cases, as the radius of the CPW inductor increases from 5 to 20 mils, Q and
SRF decreases. This decrease is a result of higher resistance associated with longer coil
and larger parasitic capacitance associated with a larger inductor area. The inductance
increases as it is proportional to the coil length.
30
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C O N D U C T O R W ID TH
The variations of quality factor, Figure 3.12, and both inductance and self­
resonant frequency, Figure 3.13, as a function of conductor coil width can be seen. As
the conductor width increases from 3 mil to 6 mil, Qmax increases, while L and SRF
decreases. Qmax is highest when coil width is 6mil due to the decrease in series
resistance relating to the sheet resistance of the coil, which is inversely proportional
to the coil width [33].
SRF decreases due to the higher parasitic capacitance
associated with larger coil width.
55
Conductor Width (mils)
50
45
40
35
30
25
5
10
15
20
25
R adius (mils)
Fig.3.12. Maximum quality factor for conductor width = 3,4,5, and 6 versus radius.
31
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.5
- Conductor Widtt (mils)
2.5
I
c
8c
to
0.5
5
10
15
20
25
Radius (mils)
24
Conductor Width fmilsl
22
20
18
16
14
12
10
5
10
15
20
25
R adius (mils)
Fig.3.13. Inductance (top) and SRF (bottom) for conductor width = 3,4,5, and 6 mils
versus radius.
32
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
G r o u n d p l a n e w id t h
While keeping the same spiral footprint, ground plane width was varied at 4, 8, 16
and 20 mils. As the size of the ground plane increases, resistive losses, which are
inversely proportional to the width of the medium, decrease. This improves Q at larger
inductor radius. The increase in ground plane width has an adverse effect at smaller
inductor radius, as reduction in parasitic capacitance due to the smaller coil become
dominant, (Figure 3.14.) Inductance values increase due to the mutual coupling and SRF
decreases due to parasitics associated with the ground, (Figure 3.15.)
45
Ground Plane Wi 1th (mils)
40
CO 35
LL
O
30
25
20
5
10
15
20
25
R a d iu s (mils)
Fig.3.14. Maximum quality factor for ground plane width = 4, 8, 16 and 20 mils versus
radius.
33
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.5
Ground Plane Wic th (mils)
c5
0.5
5
10
15
20
25
Radius (mils)
iround Plane Wic th (mils)
22
20
N
X
CD
LL
X
co
5
10
15
20
25
R a d iu s (mils)
Fig.3.15. Inductance(top) and SRF (bottom)for ground plane width = 4, 8, 16, 20 mils
versus radius.
34
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
G r o u n d p l a n e sp a c in g
Figure 4 also demonstrates that as the spacing between the inductor and ground
increases from 5.5mil to 20 mil, inductance, Figure 3.17, and maximum Q in general,
Figure 3.16, increases due to the reduction in eddy current effect. An increase in SRF
decreases as a result of the parasitic resistance, (Figure 3.17.) A summary of all the CPW
library data can be seen in Table 3.3.
45
G round P la n e S p a c in g (mils)
40
ir
O
O
CO
LL
35
CO
O 30
25
20
5
10
15
20
25
R a d iu s (m ils)
Fig.3.16. Maximum quality factor for ground plane spacing = 5.5, 8, 16 and 20 mils
versus radius.
35
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.5
Ground Plane Spacing (mils)
3
2.5
2
1.5
1
0.5
5
10
15
20
25
Radius (mils)
24
Ground Plane Spacing (mils)
22
20
N
X
CD
Ll_
DC
C/3
5
10
20
15
25
Radius (mils)
Fig.3.17. Inductance (top) and SRF (bottom) for ground plane spacing = 5.5, 8, 16
and 20 versus radius.
36
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Table 3.3. Summary of measured Q, L, and SRF of LCP CPW inductors.
Radius
(mils)
5
cw
GPW
(mils) (mils)
12
3
GPS
(mils)
12
Q
L
(nH)
-
-
-
SRF
(GHz)
5
4
12
12
49
1.24
20.25
5
5
12
12
48
1.24
19
5
6
12
12
52
1
18.25
5
5
4
12
34
1.25
22.25
5
5
8
12
32
1.25
20.75
5
5
16
12
34
1.35
19
5
5
20
12
30
1.5
18
5
5
12
5.5
36.5
1.1
22
5
5
12
8
37
1.2
21
5
5
12
16
39
1.3
17.75
5
5
12
20
42
1.4
16
10
3
12
12
-
-
-
10
4
12
12
38
1.6
17.5
10
5
12
12
40
1.5
16.5
10
6
12
12
46
1.5
15.75
10
5
4
12
31
1.5
19.5
10
5
8
12
30
1.5
18
10
5
16
12
30
1.6
16
10
5
20
12
30.5
1.65
15.75
10
5
12
5.5
32
1.35
19.25
10
5
12
8
30
1.4
18
10
5
12
16
34
1.6
15.75
10
5
12
20
34.5
1.7
14.25
15
3
12
12
-
-
-
15
4
12
12
34
1.85
15.5
15
5
12
12
37
1.8
14.75
15
6
12
12
41
1.75
14
15
5
4
12
31
1.75
16.75
15
5
8
12
-
-
-
15
5
16
12
29
1.85
14.25
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
15
5
20
12
-
-
-
15
5
12
5.5
30.5
1.6
16.25
15
5
12
8
31
1.7
15.5
15
5
12
16
15
5
12
20
20
3
12
20
4
20
30.25 1.85
14
35
1.95
13
12
31
2.8
14
12
12
34
2.2
14
5
12
12
31
2.1
12.25
20
6
12
12
37
2
12
20
5
4
12
-
1.9
15
20
5
8
12
30
1.9
14
20
5
16
12
28
2
11.25
20
5
20
12
27
2.1
11.1
20
5
12
5.5
27.5
1.85
14.5
20
5
12
8
27.5
1.9
14.25
20
5
12
16
28.5
2.2
12
20
5
12
20
29.5
2.15
11.75
25
3
12
12
25
3.2
12
25
4
12
12
28
2.5
12.5
25
5
12
12
28
2.3
11.8
25
6
12
12
32
2.2
11.75
25
5
4
12
23
-
-
25
5
8
12
27
2.1
12.5
25
5
16
12
25
2.2
11.25
25
5
20
12
28
2.2
11.1
25
5
12
5.5
25
2.2
13.5
25
5
12
8
28
2.2
13
25
5
12
16
24
2.45
11.25
25
5
12
20
26
2.5
11
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER IV
DESIGN OF EXPERIMENTS AND STATISTICAL ANALYSIS
4.1 Design of Experiments: HGP Inductors
One of the most challenging components in integrated RF systems in terms of
control and prediction of parasitic effects and behavior is the integrated inductor [35].
The need to predict the inductor geometry that will provide the highest possible quality
factor for a given inductance value and frequency range is vital. Modeling RF inductors
is, therefore, imperative in understanding design insights and optimization. Most
conventional modeling is relatively inaccurate or not scaleable over a wide range of
layout dimensions and process parameters. A novel experimental approach of significant
factors for RF inductor design in a multilayer packaging environment is discussed in this
chapter. It includes the design of an experiment (DOE) [36] and statistical analysis in
terms of a geometrically scalable electrical model.
Barriers to optimizing key performance parameters for the realization of good
inductors include achieving high Q-factor in a specific operation band and accurate
inductance(L). A model is necessary to identify the relevant parasitics and their effects
including eddy current losses. Significant geometrical parameters of spiral inductors that
affect these barriers have already been identified to be: the number of number of turns,
the conductor width, the spacing between the conductors, and the radius of the spiral
[35].
The next step is to gain a general understanding of all involved factors, their
39
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relative importance, and the interaction between them. The design of experiments
approach used here allows these goals to be achieved.
The design of experiments is the set of designated experiments where the input
variables are systematically varied to extract maximum information about the effect of
input variables on the response variables [36]. Previous work shows the use of the design
of experiments in modeling of microwave/millimeter-wave integrated circuits [38,39] and
flip-chip packaging [36], For this experiment, we modeled a multilayer spiral inductor
with a hollow ground plane(HGP) implementation. Two additional parameters were
therefore taken in account for this DOE, which include HGP width and spacing from the
HGP to the inductor footprint. The important electrical characteristics of the inductor, Q;
L; and SRF , are considered the response variables or what we call the output variables.
The input variables for this experiment can be seen in Figure 4.1 and are defined as
follows:
A
Number of turns
B
Conductor width
C
Spacing between turns
D
Spacing between HGP and inductor
E
HGP width
F
Radius of inner spiral
40
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Fig.4.1. Top view of HGP inductor with layout parameters.
4.2 Basic Experiment
A 26'1partial factorial design [39] has been chosen for the 6 variables. The
experiment consists of 26"1= 32 treatment combinations. For the design of experiments,
two levels, high and low, of each of the layout parameters are used. The values are
shown in Table 4.1.
A layout of the 32 treatment combinations can be seen in Figure
4.2. Results of the 261 partial factorial design experiment is presented in Table 4.2.
41
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Table 4.1. Variables for 26'1based experiments.
Input Variable
L ow
L evel
H igh
L evel
W idth o f the Inductor line A
2 m ils
6 m ils
# O f turns B
2
3
Spacing betw een the lines C
2 m ils
4 m ils
HGP spacing D
2 m ils
8 m ils
HGP w idth E
6 m ils
2 0 m ils
Radius o f the Inductor F
4 m ils
8 m ils
Fig.4.2. Layout 32 treatment combinations for 26' 1based experiments.
42
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Table 4.2. The 2 6-1 experiment.
Spacing
(mils)
-
HGP
Spacing
-
HGP
Width
-
Radius
Qmax
Leff
(nH)
-
Number
o f turns
-
-
105.99
2.7
SRF
(GHz)
15.5
2
+
-
-
-
-
+
107.58
4.55
8
3
-
+
-
-
-
+
100.56
8.43
6.5
4
+
+
-
-
-
-
82.46
6.91
5.5
5
-
-
+
-
-
+
115.37
4.89
9.8
6
+
-
+
-
-
-
99.78
3.7
9.25
7
-
+
+
-
-
-
102.98
7
7.25
8
+
+
+
-
-
+
93.61
10
4.25
9
-
-
-
+
-
+
125.65
4.9
10.5
10
+
-
-
+
-
-
94.77
4.0
8.75
11
-
+
-
+
-
-
106.34
6.1
8.75
12
+
+
-
+
-
+
84.68
8.3
4.75
13
-
-
+
+
-
-
117.8
3.6
12.75
14
+
-
+
+
-
+
116.15
5.2
7.25
15
-
+
+
+
-
+
109.61
10.8
5.75
16
+
+
+
+
-
-
94.25
8.2
5
17
-
-
-
-
+
+
96.89
4.8
9.25
18
+
-
-
-
+
-
86.96
3.7
9
19
-
+
-
-
+
-
96.45
6.2
7.5
20
+
+
-
-
+
+
81.17
9.5
4.25
21
-
-
+
-
+
-
109.35
3.9
11
22
+
-
+
-
+
+
92.34
5.2
6.5
23
-
+
+
-
+
+
87.98
10
5
24
+
+
+
-
+
-
79.17
7.2
4.5
-
+
+
-
114.01
3.7
12
+
+
53.47
4.8
7
Run
#
1
Width
25
-
26
+
-
-
+
27
-
+
-
+
+
+
96.77
9.7
5.75
28
+
+
-
+
+
-
82.29
7.8
5
29
-
-
+
+
+
+
101.82
5.3
8.25
30
+
-
+
+
+
-
95.57
4.4
8
31
-
+
+
+
+
-
99.55
7.8
6.25
32
+
+
+
+
+
+
67.64
9.9
3.5
-
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4.2.1 Analysis of Variance: HGP Inductor
Statistical analysis has been performed to study the effect of the various layout
parameters on the inductance, SRF and, Qmax. Analysis of variance (ANOVA) is the
appropriate procedure for testing the significance of several factors. It is the most useful
technique in the field of statistical inference [39]. The statistical analysis is performed by
Minitab software [40]. The ANOVA table has been obtained for each of the inductor
performance parameters as shown in the Tables 4.3, 4.4 and 4.5.
Table 4.3. ANOVA table for Qmax.
Source
Sum of
Squares
DF
Mean
Square
F
A
2367
1
2367
151.4
B
882
1
882
42.8
C
140
1
140
6.1
D
15
1
15
0.6
E
1460
1
1460
78.2
F
41
1
41
1.8
Error
4905.3
6
44
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Table 4.4. ANOVA Table for Inductance.
Source
Sum of
Squares
DF
Mean
Square
F
A
0.36
1
0.36
0.7
B
126.99
1
126.99
96.56
C
3.53
1
3.53
6.5
D
1.11
1
1.11
2.0
E
0.75
1
0.75
1.4
F
26.18
1
26.18
56.0
Error
158.92
6
Table 4.5. ANOVA table for SRF.
Source
Sum of
Squares
DF
Mean
Square
F
A
53.17
1
53.17
86.8
B
125.02
1
125.02
334.8
C
5.91
1
5.91
7.7
D
0.44
1
0.44
0.6
E
8.77
1
8.77
11.5
F
27.66
1
27.66
39.6
Error
220.96
6
45
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The F statistics for all the six factors that influence the electrical characteristics of
the inductors are obtained and can be seen in the last column of each table. Variables
with higher F statistic have a greater significance in influencing the respective response.
The threshold value for the statistical significance has been calculated to be 3.2 for 0.95confidence coefficient [39]. Every variable with F value lower than 3.2 is considered
statistically insignificant. This implies that the particular variable having F less than 3.2
may still impact the respective inductor performance but to a lesser degree.
Results
These results are valid only for the specified interval of each variable. The
statistical analysis reveals that for quality factor, the width of the inductor line (A) is the
most significant design variable followed by HGP width (E) and the number of turns and
(B). The radius (F) and the HGP spacing (D) are statistically insignificant. The positive
effects are C and D. A, B, E, and F have a negative effect on Q, which means Q
decreases as the number of turns and width of the inductor line increases. Similarly for
the value o f Leff, the number of turns (B) is the most significant design parameter
followed by the radius (F) and spacing (C) of the inductor lines. Coil width is statistically
insignificant and has the least impact on the inductance of the inductor. The positive
effects are A, B, C, D, E, and F, which means that Leff increases with increasing A, B, C,
D, E, and F. The most significant layout variable for SRF is the number of turns (B), the
width of the conductor lines (A) and the radius of the inductor (F). The HGP spacing (D)
is statistically insignificant. The negative effects are A, B, C, D, E, and F. There are no
46
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positive effects. All of the negative and positive significance effects are summarized in
Table 4.6.
Table 4 .6 . Summ ary o f sign ifican ce effects.
T erm
Q
L
SRF
A
-17.202
0.212
-2.578
B
-10.499
3.984
-3.953
C
4.183
0.6639
-0.859
D
1.358
0.372
-0.234
E
-13.509
0.306
-1.047
F
-2.277
1.808
-1.859
A*B
0.331
-0.002
0.578
A*C
3.958
-0.173
0.359
A*D
-5.639
-0.112
-0.016
A*E
-3.324
-0.056
0.422
A*F
-0.049
-0.401
0.672
B*C
-3.367
0.289
0.047
B*D
0.736
0.083
0.234
B*E
3.076
0.029
0.297
B*F
-0.407
0.584
0.609
C*D
1.368
0.079
0.141
C*E
-1.007
-0.207
0.016
C*F
0.535
0.082
0.141
D*E
-3.757
-0.014
0.078
D*F
-3.822
-0.129
0.141
E*F
-8.382
-0.001
0.141
47
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4.2.1 Analysis of Variance: Parasitics
Statistical analysis was also performed to understand the fundamentals of inductor
parasitic effects, which ultimately impacts Q, SRF, and L. These electrical parameters
can be analyzed once the parasitic values are known. The ANOVA table has been
obtained for each of the parasitic values as shown in the Table 4.7.
Table 4.7. F-statistic for inductor parasitics.
Factor
A
B
C
D
E
F
Ceq
60.9
116.2
2.6
2.8
57.0
18.9
Rp
222.1
14.6
.8
5.4
7.3
3.0
L
41.6
525.6
6.7
5.2
1.4
5.12
Rs
167.7
182.7
1.5
8.2
26.0
4.1
The statistical analysis reveals that for Ceq, the number of turns (B) is the most
significant design parameter followed by width (A) of the inductor lines and hollow
ground plane width (E). The spacing between the lines (C) is statistically insignificant
and has the least impact. The positive effects are A, B, C, E, F, which means that
parasitic capacitance increases with increasing A, B, C, E, and F. D, however, has a
negative effect on capacitance, which means Ceq decreases as the spacing between the
inductor footprint and hollow ground plane increases. Similarly for Rp, the width of the
inductor line (A) is the most significant design variable, followed by the number of turns
48
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(B) and HGP width (E). The radius (F) and spacing between the lines (C) have
insignificant impact on Rp. The positive effects are C and D. The negative effects are A,
B, E and F. For L, the number of turns (B) is the most significant followed by radius (F)
and spacing between the lines (C). The HGP width (E) is the least significant. The
positive effects are A, B, C, D, E, and F. The most significant layout variable for Rs the
number of turns (B) followed by width (A) and hollow ground plane width (E). The
spacing between the lines (D) is least significant. The positive effects are A, B, E, and F.
The negative effects are C and D.
4.2.3 Summary of Effects
The results of the statistical analysis show that the impact of the layout parameters,
including the variations o f the hollow ground plane, varies on different electrical
properties of the multilayer inductors.
Q is impacted mainly by, Rs, and Rp. This is verified by Q’s significant factors, which
are A, B and E respectively. The most significant layout parameter relating to Q is line
width. In this case, the negative effect of increasing line width is related to magnetically
induced losses, which contributes to the coil resistance that increases with width [33]
The ideal inductance, L in the model simply demonstrates that the effective inductance
is most effected by B, F and A. The number of turns is the most significant factor for
Leff, which increases with number of turns and inner opening radius [41]. The eddy
current effect, which reduces the ideal inductance is mostly eliminated by the hollow
ground plane configuration.
49
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SRF is mostly impacted by Ceq and is very closely tied to L, which is the reason the
most significant factor are B. F is also relatively significant due to L and E due to the
effects of Ceq. The SRF is limited by the substrate capacitance [41], which is the
capacitance between inductor turns and ground plane and not so much by the inherent
existence of distributed parasitic capacitive coupling that occur among the turns of the
inductor.
The knowledge about the variations provide framework for the optimization of the
layout and enhancing the performance of inductors. For instance, to maximize the quality
factor of the inductor for a constant value of inductance, design parameters to be chosen
for variation are those that have the least impact on the inductance value but have
significant impact on the Q of the inductor. Similarly various tradeoffs can be done to
optimize the layout of a passive for a particular RF and microwave application based on
the information obtained from statistical analysis.
50
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To obtain the variation of Q, L and SRF along the entire range of layout
parameters, 3-D plots are generated from the statistical analysis. These graphs can be
used to obtain the optimal responses on the curve. We choose the two most significant
geometrical parameters with the exception of number of turns, which can not be varied
over a range. The other variables remain at their mean values. Figure 4.3 shows that over
the range of the significant variables, HGP width and conductor width, Q is at a
maximum with minimum HGP width and minimum conductor width. Inductance is at a
maximum with maximum radius and maximum spacing, (Figure 4.4.) SRF is at a
maximum with minimum conductor width and minimum radius, (Figure 4.4.)
C onductor Width
HGP Width
F ig.4.3. 3-D contour plot o f Q.
51
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6
Radius
e
Spacing
8
Conductor Width
Radius
Fig.4.4. 3-D contour plot of inductance (top) and SRF (bottom).
52
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4.3 Statistical Model Development
A regression model is used for the development of a scalable model. These models are
developed for scaling the values of the electrical characteristics with the physical
attributes of the inductor and the fabrication limitations. The need for full scalability of
the model can be satisfied by developing regression models [39] for Q, L, and SRF. The
empirical constants for polynomial regression function are obtained during the model
development process. Prior to model development the significance of the main effects
and two factor interactions are analyzed. The normal probability plot [39] of the effects
indicates that third and higher levels of interactions are not significant and hence
eliminated from the further analysis. This is done to select the optimal regression
coefficients by selecting only the significant factors and eliminating the insignificant
parameters and it ensures the simplicity of the model without losing the accuracy.
The T and P values are also statistical values that allow the significance of the
variables to be quantified. The T and P values for the regression coefficients for various
terms are shown in the Table 4.8. The level of significance (a) for the experiment is
chosen to be 0.1. The criteria for retaining the term in the regression model is that the Pvalue for that term should be less than or equal to 0.1. If the term has a P-value greater
than 0.1 then that term is not significant and discarded from the regression model.
53
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Table 4.8. P - values of factors for model development.
T erm
SR F
L
Q u a lity F a c to r
T
P
T
P
T
P
C o n sta n t
66.54
0.000
84.29
0.000
85.58
0.000
A
-5.91
0.000
1.42
0.187
-14.57
0.000
B
-3.61
0.005
26.50
0.000
-22.34
0.000
C
1.44
0.181
4.42
0.001
-4.86
0.001
D
0.47
0.651
2.48
0.033
-1.32
0.215
E
-4.64
0.001
2.04
0.069
-5.92
0.000
F
-0.78
0.452
12.03
0.000
-10.51
0.000
A *B
0.11
0.912
-0.02
0.985
3.27
0.008
A *C
1.36
0.204
-1.16
0.274
2.03
0.070
A *D
-1.94
0.081
-0.75
0.471
-0.09
0.931
A *E
-1.14
0.280
-0.38
0.715
2.38
0.038
A *F
-0.02
0.987
-2.67
0.023
3.80
0.003
B *C
-1.26
0.236
1.93
0.083
0.26
0.796
B*D
0.25
0.806
0.56
0.591
1.32
0.215
B *E
1.06
0.316
0.20
0.847
1.68
0.214
B *F
-0.14
0.892
3.89
0.003
3.44
0.006
C *D
0.47
0.648
0.53
0.608
0.79
0.445
C *E
-0.35
0.737
-1.38
0.197
0.09
0.931
C *F
0.18
0.858
0.55
0.597
0.79
0.445
D *E
-1.29
0.226
-0.09
0.927
0.44
0.668
D *F
-1.31
0.219
-0.86
0.410
0.79
0.445
E *F
-2.88
0.016
-0.01
0.991
0.79
0.445
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The regression model equations can be written as:
Q
I lld X
= 116.100 - 1.950A - 10.4995 + 0 .8 3 1 5 - 0.469 A * D - 0.299 5 * 5
L= -2.787 + 1.3605 - 0.392C + 0.062D + 0 .0 2 1 5 - 0 .0 7 8 5 - 0.050 A *5
+ 0.2895 *C + 0 .2 9 2 5 * 5
SRF= 36.6150 - 2.336A - 6.9375 - 0.789C - 0 .1 3 5 5 -1 .5 5 2 5 + 0.289
A *5 +0.089 A *C + 0.015 A *5 + 0.084 A * 5 + 0.305 5 * 5
The pareto charts, which can be seen in Figure 4.5 and 4.6, are also used to select the
significant main effects and 2-way interactions for the model development. The terms
that have the p value of less than 0.1 (a=0.1) are selected in the model. The significant
factors for Quality factor are A, E, B, E*F, and A*D, (Figure 4.5.) The significant factors
for inductance are B, F, C, B*F, A*F, D, E, and B*C, (Figure 4.5.) This implies that the
regression terms that will is used in the model has will have these terms. Similarly for
SRF the significant factors are B, A, F, E, C, A*F, B*F, A*B, A*E, A*C and B*E,
(Figure 4.6.)
55
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CO..
D—
CE­
BU..
CF—
SP­
A SAF~|
6
B
F
C
8F
AF
D
E
BC
A
CE
AC
DF
AD
BD
CFCDAE
J
DEABEF
0
10
20
Fig.4.5. Pareto Chart of Q (top) and inductance (bottom).
56
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig.4.6. Pareto Chart of SRF.
4.4 Sensitivity Analysis
In this case, sensitivity has been calculated as 10% around the mean by varying
the input parameters by 10% of their full range of deviation. Sensitivity analysis is used
to quantify the variation in the output variable for an incremental change in a particular
input parameter, which is of interest if one wants to know effects of process variation for
instance on the response variables [42].
57
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In general the sensitivity of one output value with respect to the input variable is
formed by obtaining the partial derivative of the response with respect to the input of
interest while holding the others constant [43].
(4.1)
We have done the sensitivity analysis separately for 2 turn and 3 turns, since the
number of turns couldn’t be varied over a 10% range. As you can see, sensitivity
changes for the same input variable depending on the number of turns, (Figures 4.7 and
4.8.) The sensitivity for SRF is seen to be much greater than Q and inductance because
SRF is mostly limited by parasitic capacitance and higher frequencies for multiple turn
inductors losses due to parasitic capacitance has the most significant impact on inductor
behavior.
0.00«
-0.00®
- 0.01
-0,01s
- 0.02
O c r f Twrr»ip*>;!
■I 0 <&t Turn*** 3
Fig.4.7. Sensitivity analysis of Q.
58
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©.OS
0 .0 4
f M ft o f T u rn s* 2
I m j t o f T u rn * - 3
0 .0 0
0.02
0.05
-
0.05
-CM S
- 0 ,2 5
-
0.35
Fig.4.8. Sensitivity analysis of inductance (top) and SRF (bottom).
59
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER V
PASSIVE COMPONENTS FOR MODULE DEVELOPMENT
The major drawbacks of some commercially available transceivers are their
increased size, weight, and cost [44]. On monolithic microwave integrated circuits, filter
structures require a large area, serving as an obstacle in compact module design and
resulting in high cost [45]. There is also considerable potential for the savings of
assembly time and cost by reducing MMIC real estate. Multilayer technology can be used
to realize microwave circuits such as high Q capacitors and inductors. These components
can be combined as well to form passive filter structures, which are essential for
microwave circuits. Miniaturized high performance narrowband embedded microwave
bandpass filters are also highly desirable for the next generation of satellite and mobile
communications. These integrated filters that include the interconnect as an embedded
function between individual microwave components can be realized in multilayer
technology, thus reducing the global system cost. It is, therefore, attractive to establish
design methodologies to implement high performance embedded passives such as filters
in addition to power splitters/combiners, couplers tod baluns, etc.
A microwave filter is a 2-port network used to control the frequency response at a
certain point in a microwave system by providing transmission at frequencies within the
passband of the filters and attenuation in the stopband of the filter. Perfect filters have
zero insertion loss in passband, infinite attenuation in the passband and a linear phase
response (to avoid signal distortion) in passband. The filter design depends on the type of
needed response such as, flat passband, sharp cutoff, etc. In addition, to specify the
60
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amplitude response, in some applications (such as multiplexing filters for communication
systems) it is important to have a linear phase response in the passband to avoid signal
distortion [46]. Sharp-cutoff response is generally incompatible with a good phase
response. There are different topologies that can be used for filter design. The center
frequency and process design rules are taken into account in the proposed designs.
Dual-mode microstrip filters, which take the form of ring, disk, or square patch,
have been attractive to meet some of the demands. It is felt, however, that these sizes are
still too large for the design of high performance filters, especially at lower microwave
frequency bands. Multilayer filter topologies offers alternative design solutions as well
as an alternative to on-chip active filtering, which help address these issues. LTCC has
been studied to implement embedded filters for applications including the downconverter
subsystem of a EHF SATCOM transceiver [44], as well as for front-end image rejection
in a Bluetooth wireless LAN transceiver system[47] and front-end filtering for Ku-band
satellite communications applications [48]. MLO and LCP can also serve as a potential
technology to achieve these objectives.
5.1 Low-pass Filter Design
Lumped-element filter designs tend to work well at lower frequencies, since
lumped elements are generally only available to a certain range of values. They however,
are difficult to design at higher frequencies, and at microwave frequencies the distances
between the filter components are not negligible. This makes lumped-element not
attractive for higher frequencies. Finally, as a matter of practical design procedure, it is
necessary to determine the order of the filter, which is usually dictated by a specification
61
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on the insertion loss at some frequency in the stopband of the filter. This design uses a T
form of constant-k lowpass filter. L represents the total series inductance and C, the total
shunt capacitance, (Figure 5.1.) Signals pass through the filter unattenuated at frequencies
below the cutoff frequency, toc, which can be calculated using the equations below [47]:
Z0= VT/C = k, C0c = 2/VLQ L = 2 Zo/C0c, C=2/o)c Z0
L /2
o
L /2
fYYY\ __ 0000
o
c
0 ------------ 1 -------------- O
Fig.5.1. T-network for lowpass filter
where, 0 )cis the cutoff frequency andZ0is a nominal characteristic impedance.
Figure 5.2 shows the 2nd order Bessel lumped element lowpass filter with cutoff
frequency at 750MHz. The simulated and measured return loss and insertion loss are
shown in Figure 5.3.
Fig.5.2. Photograph lumped element 750MHz LPF.
62
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-5
-5
-10
C
-15
-15
-20
-20
M easu red
S im u la te d
-25
-25
-30
0
2
4
6
8
-30
1
Frequency, G H z
Fig.5.3. Measured and MOM simulation of lumped element 750MHz LPF.
5.2.Bandpass Filter Design
The band pass filters in this research are dual mode. The dual mode concept
stems from a physical coupling of two degenerate modes in a geometrically symmetrical
resonator such as a ring or patch. The coupling of the two modes, which construct the
BPF is achieved by introducing a perturbation element along the orthogonal plane of the
resonator in view of the 2 modes. These modes are excited by asymmetrical feed lines
and by adding notches or stubs on ring or patch resonators.
63
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5.2.1 .Square Ring Resonator BPF
Bandpass filters can be implemented using coupled resonators. The microstrip
ring resonator has been heavily studied and possesses attractive features including small
size, narrow band, low cost. It is easy to design because of transmission line theory. It is
also easy to fabricate do to the lack of a large metal patch which can be a challenge with
newer non-mature processes with metallization issues.
Broadside-coupled microstrip dual-mode square ring resonator [49] configuration
is used to design the following BPFs. The ring resonator is fed by a pair of orthogonal
feed lines, which connects to approximately X/4 stub with two open ends. It is perturbed
by inserting a small metal polygon at one comer with length, d, (Figure 5.4.) The outputs
are taken symmetrically with respect to this perturbation, which causes the resonator
modes to split into two degenerate coupled modes, giving a second-order bandpass filter
response. The advantages of this design are compactness and controllability of the
bandwidth by varying the size of the perturbed polygon that causes mode splitting.
output port
input port
Fig.5.4. Schematic of one coupling gap square ring resonator BPF.
64
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No perturbation is added when d = 0, only a single mode is excited. The size of d
controls the degree of coupling, hence controlling the mode splitting.
Larger
perturbations cause more mode splitting and result in a larger bandwidth. Figure 5.5
shows the frequency characteristics of mode splitting for various values of d. Without the
patch (d=0), neither splitting of the resonance frequency nor the bandpass response takes
place. As d increases from 42 to 82 mil, resonance frequency splitting increases to
2GHz. The tradeoff however is that a greater variation results in the ripple in the
passband causing it to become less ideal.
©—
B—
*—
X—
d
d
d
d
=42
=52
=62
=82
mil
mil
mil
mil
Frequency, GHz
Fig.5.5. MOM simulation of square ring resonator 5.8 GHz BPF.
65
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The width of the coupling gap affects the insertion loss and resonant frequency.
This loop resonator first done by J. S. Hong and M. J Lancaster [49] for 1.55 GHz uses an
equivalent transmission line model for the proposed loop resonator. It can be shown that
the first resonance occurs when (a+b)/2= XIA, where a and b is the length of the outer and
inner loop respectively.
The surface area occupied by the square loop resonator may
then be estimated by Sloop = (A,/4)2 if (a-b)/2 « a . The fabricated 5.8 GHz square ring
resonator BPF can be seen in Figure 5.6.
Fig.5.6. Photograph of square ring resonator 5.8 GHz BPF.
66
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5.2.2. Square Patch BPF
The patch BPF is compact, and easy to fabricate, due to the lack of coupling gaps to
cause etching uncertainties affecting the design including resonance frequency [50].
The MLO filter is a BPF designed for C-band applications and has a size of 2.2 x 2.2
mm2. It consists of a square patch resonator with inset feed lines. This orthogonal pair of
inset feed lines perturbs the fields and excites the degenerate mode. The length of the
feed lines is determined by the input and output matching requirements. The inset gaps
act as small capacitors and cause the filter to have a pseudo-elliptic response with
transmission zeros on either side of the passband. This structure also has a tunable
bandwidth. The length of the insets and the distance between them are the main
controlling factors, effectively setting the size of the mode-splitting perturbation in the
field of the resonator. This square patch BPF has been implemented in a C-band
transmitter.
5.3. Module Implementation
To satisfy the needs of today’s communications systems, great effort has been
used to develop low-cost, compact, high performance, RF front-end modules. Many
single-chip solutions still use external components for impedance matching, RF bandpass
filters, etc.
Silicon IC technology is attractive due to its low-cost; however, it has
performance limitations, especially regarding the efficient integration of passive
components. LTCC [51] and MCM-D [17] have been used to implement a transceiver
module.
67
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5.3.1. C-band Transmitter
We present the first report of a fully integrated multilayer organic (MLO)-based
transmitter module incorporating a single MMIC for a WLAN applications C-band
transmitter. A schematic diagram of the module can be seen in Figure 5.7.
r1
MLO BPF
Up-converter MMIC
Fig. 5.7. Schematic diagram of a transmitter module.
This development of a complete module includes an upconverter MMIC and a
miniaturized integrated square patch resonator band pass filter (BPF) with inset feed lines
fabricated in MLO packaging technology. The upconverter MMIC consists of a double
balanced diode ring mixer (DBM), a wide tuning range (20%) voltage controlled
oscillator (VCO), an LO buffer amplifier, an IF amplifier, and a RF amplifier. The
upconverter MMIC integrated with a VCO exhibits a measured up-conversion gain of 14
dB and an IIP3 of 15 dBm as well as LO-to-RF rejection of 45dB and image rejection of
lldB c without any band pass filtering. In addition, a second harmonic suppression of
more than 22 dB is obtained. An integrated square patch resonator band pass filter (BPF)
with inset feed lines was developed in MLO technology and incorporated with the
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upconverter MMIC to reject the spurious signals generated by the mixer. The MLObased BPF indicates 27 dB of the return loss at 5.8 GHz, and image rejection of 35dBc at
4 GHz image frequency, 500MHz of bandwidth, as well as better than 3dB of insertion
loss, as shown in Figure 5.8. The insertion loss includes losses of the feed lines and
radiation loss due to the open patch. This realizes a compact and highly integrated
transmitter module suitable for the low cost network interface card (NIC), IEEE 802.11a
WLAN applications in 5-6 GHz frequency band, (Figure 5.9.) This transmitter module
demonstrates the feasibility of developing a miniature high performance and highly
integrated wireless SOP.
-30
-40
-50
2
3
4
5
6
7
8
9
10
Frequency (GHz)
Fig. 5.8. Magnitude of return and insertion loss of BPF for c-band transmitter module.
69
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Fig.5.9. Photograph of implemented MLO-based c-band transmitter module.
As a next step in taking advantage of multilayer topology, a stripline filter with
the top ground used for MMIC attachment or wire bonding is designed. A fabricated topview of this structure designed for C-band in shown in Figure 5.10. This filter was also
designed for a C-band transmitter module.
Fig.5.10 Photograph of implemented stripline filter for module development.
70
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4.3.2. Intelligent Network Communicator
The Intelligent Network Communicator (INC) is a universal information system
that integrates digital, optical, analog and RF functions into a series of universal and
evolving systems with increased System-on-Package (SOP) capabilities. Its design and
implementation shows the feasibility of a high performance, multiple-function co-design
system necessary for the evolution of future electronic products. INC transmits and
receives a high speed digital and a modulated RF mixed signal through an optical
channel. A schematic diagram of this system can be seen in Figure 5.11.
Intelligent N etw ork C o m m u n icato r
D ig ita l B lo c k
A n a lo g B lo c k
[
O p tic B lo c k
RF| O u t
Fig.5.11. Schematic of INC system architecture.
At the analog block, a 1Gb/s subcarrier header signal, which gets upconverted to
14GHz via subharmonic mixing with a 7GHz LO frequency, is combined with a 2.5Gb/s
base-band signal generated by the digital block. A multilayer mixed signal combiner is
designed to combine the 14Ghz wireless signal with the 2.5Gb/s base-band signal and
transmit the signal to the optical modulator. The LPF and 14GHz BPF filters the header
71
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data stream and the upconverted signal, respectively. Active components, which include
RF mixer, buffer amplifier and power amplifier are being developed using commercial
MESFET MMIC technology. Figure 5.12 shows a layout of the analog block. The entire
fabricated INC board can be seen in Figure 5.13.
Fig.5.12. Layout of analog block for INC system.
Fig.5.13. Photograph of fabricated INC board.
72
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CHAPTER VI
CONCLUSIONS
This thesis reports the first comprehensive design and analysis of integrated
passives developed for next generation, low cost and high performance materials used in
a multilayer packaging environment for System on Package (SOP) technology. It begins
with material characteristics performance comparison of available multilayer process
technologies used to achieve System on Package.
Novel hollow ground plane (HGP) inductors are introduced and demonstrate
superior performance to their on-chip counterparts. This configuration achieves high
quality factor, with operation in Ku-band demonstrating the highest self-resonant
frequency ( ~29 GHz) reported in a similar multilayer packaging environment.
The first reported inductor library including the use of a design of experiments
and statistical analysis approach for multilayer passives implemented in Liquid Crystal
Polymer Technology is presented. We applied this powerful design tool for the first time
to RF passive development in a polymer technology and it enables the efficient selection
of the most significant inductor factors for the important electrical characteristics, Q, Leff
and SRF. Just as important, the least significant factors were found, which enables the
selection of optimum layout parameters to achieve maximum Q and SRF for a particular
inductance.
73
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In addition, compact filter topologies for RF module development have been
demonstrated. A 5.8GHz square patch BPF with inset feed lines yielding insertion loss of
better than 3dB has been used to realize the first MLO-based C-band transmitter. A 750
MHz lumped element LPF and 5.8 GHz square ring resonator band pass filter have been
used to realize an Intelligent Network Communicator (INC), which demonstrated the first
implementation of a MLO-based digital, optical, and analog co-design system.
These building blocks demonstrated the feasibility of efficiently integrating highquality passives for System-on-Package Technology, ultimately eliminating the need for
discrete passives. Multilayer Organic and Liquid Crystal Polymer process technologies
have been presented as strong candidates for future RF modules and the realization of
System on Package.
74
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CHAPTER VII
FUTURE WORK
Future works include applying the experimental approach of significant factors and
design rule development to other RF embedded passives. The modeling of multilayer
components using neural network modeling, which provides extremely accurate mapping
between input and output, allows the prediction of response variables, given important
input variables. The optimization and performance prediction of components such as
filters, combiners, baluns and antennas for example are key in developing more compact
and sophisticated SOP modules in emerging new multilayer technologies.
75
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Appendix A
Process Sensitivity
MLO and LCP are fairly newer processes as opposed to the more established LTCC and
some MCM-D processes. Quality factor of an inductor is an example of a parameter that
is extremely important and very sensitive to process variations. Using a commercial
MOM simulator, we study effects of Q as a result of metal and dielectric variations.
Process
Process 1 uses a 15um dielectric thickness and the metal thickness is varied from l-5um.
Process 2 uses a 30um dielectric thickness and the metal is varied from 7-13um.
Process 3 varies dielectric thickness from 13-17um with a 3um metal thickness.
Process 4 varies dielectric thickness from 28- 32um with a 12um metal thickness.
76
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120
M etal Thiel n e s s (um)
100
o
o
CO
LL
g
ra
o
60
20
0
4
2
8
6
10
Frequency, Ghz
Fig. A l. Process variation usingl5(im dielectric thickness.
200
Mf lal Thickn :ss (um)
k
150
50
2
3
4
5
6
7
8
9
Frequency, GHz
Fig. A2. Process variation using 30|am dielectric thickness.
77
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100
C iefectric fh i fcness '(um |
80
Ll 60
40
20
3
2
4
5
7
6
8
Frequency, Ghz
Fig. A3. Process variation using 3|im metal thickness.
200
Dielectric Thickness
•28
•29
■32
150
%
CO
LL
£
D 1°0
O
50
2
3
4
5
6
7
8
Frequency, Ghz
Fig. A4. Process variation using 12|am metal thickness.
78
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Appendix B
The same design of experiments and statistical analysis in terms of obtaining a scaleable
electrical model has been applied to rectangular inductors. The high levels and low
levels were selected differently, thus yielding different results.
Table B l. Variables for 261 based experiments for rectangular spirals.
Input Variable
L ow
L evel
H igh
L evel
W idth o f the Inductor line A
2 m ils
3 m ils
# O f turns B
1
2
Spacing betw een the lines C
2 m ils
4 m ils
HGP spacing D
2 m ils
8 m ils
HGP width E
6 m ils
2 0 m ils
R adius o f the Inductor F
4 m ils
8 m ils
79
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Table B2. The 2 6-1 experiment for rectangular spirals.
Run
#
Width
Number
o f turns
Spacing
HGP
Spacing
HGP
Width
Radius
Q
Leff
(nH)
SRF
(GHz)
1
-
-
-
-
-
-
121.31
1.7
22.17
2
+
-
-
-
-
+
121.96
2.2
15
98.12
7.0
6.5
3
-
+
-
-
-
+
4
+
+
-
-
-
-
104.64
4.8
8.25
5
-
-
+
-
-
+
114.8
2.4
15.5
6
+
-
+
-
-
-
119.6
1.6
20.5
7
-
+
+
-
-
-
135.52
4.7
8.25
8
+
+
+
-
-
+
100.64
6.6
6
9
-
-
-
+
-
+
132.66
2.8
15.5
10
+
-
-
+
-
-
137.55
1.8
19.75
11
-
+
-
+
-
-
116.52
5.4
9
12
+
+
-
+
-
+
117.83
6.9
6.5
13
-
-
+
+
-
-
139.63
2.1
20.5
14
+
-
+
+
-
+
140.55
2.6
14.5
15
-
+
+
+
-
+
114.48
7.5
6.5
16
+
+
+
+
-
-
117.45
5.2
7.75
17
-
-
-
-
+
+
101.19
2.4
15.5
18
+
-
-
-
+
-
126.48
1.6
20.75
19
-
+
-
-
+
-
96.37
5.1
8.75
20
+
+
-
-
+
+
91.95
6.6
6
21
-
-
+
-
+
-
115.74
1.8
21.5
22
+
-
+
-
+
+
111.02
2.2
14.5
23
-
+
+
-
+
+
88.34
7.2
6
24
+
+
+
-
+
-
96.28
4.9
7.25
25
-
-
-
+
+
-
124.09
1.9
20.25
26
+
-
-
+
+
+
124.1
2.2
14.25
-
+
+
+
110.58
7.8
6.5
28
+
+
+
-
+
+
-
113.3
5.0
8
29
-
-
+
+
+
+
119.6
2.6
14.75
30
+
-
+
+
+
-
133.76
1.7
19
31
-
+
+
+
+
-
110.3
5.6
8
32
+
+
+
+
+
+
107.4
7.0
5.75
27
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Table
B 3.
ANOVA table
fo r Qmaxfor
rectangular spirals.
Source
Sum of
Squares
DF
Mean
Square
F
A
25
1
25
1.2
B
2233
1
2233
171.3
C
17
1
17
0.8
D
1416
1
1416
89.8
E
798
1
798
44.8
423
22.2
F
423
1
Error
4911.4
6
81
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Table B4. ANOVA Table for Inductance for rectangular spirals.
Source
Sum of
Squares
DF
Mean
Square
F
A
0.78
1
0.78
1.6
B
128.08
1
128.08
1949.7
C
0.02
1
0.02
0.00
D
0.81
1
0.81
1.7
E
0.00
1
0.00
0.00
F
13.97
1
13.97
31.3
Error
143.651
6
Table B5. ANOVA table for SRF for rectangular spirals.
Source
Sum of
Squares
DF
Mean
Square
F
A
4.5
1
4.5
1.3
B
897.82
1
897.82
1705.6
C
1.5
1
1.5
0.4
D
1.3
1
1.3
0.4
E
1.1
1
1.1
0.3
F
116.3
1
116.3
31.1
Error
1022.58
6
82
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Table B6. Summary of significance effects for rectangular spirals.
Q
L
A
1.766
-0.311
-0.750
B
-16.707
4.001
-10.594
C
1.466
0.0463
-0.438
D
13.302
0.3187
-0.406
E
-9.985
0.003
-0.375
Term
b
SRF
F
-7.270
1.321
-3.813
A*B
-3.984
-0.095
0.250
A*C
-2.855
0.0475
0.031
A*D
1.619
-0.082
0.063
A*E
2.994
-0.057
0.031
A*F
3.069
-0.117
0.219
B*C
0.796
-0.010
-0.063
B*D
-1.678
0.117
0.531
B*E
-0.975
0.120
0.062
B*F
-0.735
0.657
1.875
C*D
-1.024
0.0175
0.062
C*E
-2.169
0.032
0.031
C*F
-2.036
0.002
0.156
D*E
1.168
-0.072
-0.062
D*F
3.720
0.030
0.312
E*F
-0.498
-0.007
0.031
—
.
p -l
e .P
'.... I
F-AB~;i
OF
i
:
.......
AF-
AE
;
AC -- :
CE-
,
.
Cf
a
i
- ;.
;
bd™
AD--
:
I
C—1i
0£~ :
;
;
CD-- i
;
BC-
!
in n
0
j
~T —
1
!
2
,..„
3
4
5
r
6
Fig. B l. Pareto Chart of Q for rectangular spirals.
83
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Fig.B2. Pareto Chart of inductance (top) and SRF (bottom)
for rectangular spirals.
84
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Table B7. P - values of factors for model development fro rectangular
spirals.
Term
Constant
SRF
L
Quality Factor
T
P
T
P
T
P
82.45
0.000
220.34
0.000
260.61
0.000
0.000
-7.83
0.000
A
0.63
0.543
-8.40
B
-5.96
0.000
107.94
0.000
-110.57
0.000
C
0.52
0.613
1.25
0.241
-4.57
0.001
D
4.74
0.001
8.6
0.000
-4.24
0.002
E
-3.56
0.005
0.10
0.921
-3.91
0.003
F
-2.59
0.027
35.64
0.000
-39.79
0.000
A*B
-1.42
0.186
-2.56
0.028
2.61
0.026
A*C
-1.02
0.333
1.28
0.229
0.33
0.751
A*D
0.58
0.577
-2.23
0.050
0.65
0.529
A*E
1.07
0.311
-1.55
0.152
0.33
0.751
A*F
1.09
0.300
-3.17
0.010
2.28
0.046
B*C
0.28
0.782
-0.27
0.793
-0.65
0.529
B*D
-0.60
0.563
3.17
0.010
5.54
0.000
B*E
-0.35
0.735
3.24
0.009
0.65
0.529
B*F
-0.26
0.799
17.14
0.000
19.57
0.000
0.947
0.65
0.529
C*D
-0.36
0.723
0.47
C*E
-0.77
0.457
0.88
0.401
0.33
0.751
C*F
-0.73
0.485
0.07
0.948
1.63
0.134
D*E
0.42
0.686
-1.96
0.079
-0.65
0.529
D*F
1.33
0.214
0.81
0.437
3.26
0.009
E*F
-0.18
0.863
-0.20
0.844
0.33
0.751
The regression model equations can be written as:
Q max= 133.884- 8.745 + 2.217D - 0.113E - 1.817F - 1.992 A *5
L= - .978 + 0.082A + 1.85 - 0.006D - 0 .1 0 4 F - 0.0475 A*B
- 0.0147 A*F+ 0.039 B*D + 0.017 B*E + 0.329 B*F
SRF= 48.14 - 0.539A - 17.6045 - 0.219C - 0.49D - 0.0275 -2.6F + 0.125 A*B
+0.027 A*F + 0.177 B*D + 0.938 B*F + 0.026 D*F
85
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Appendix C
PUBLICATIONS RESULTING FROM THESIS WORK
1) M.Davis, S-W.Yoon, S.Pinel, K.Lim, and J.Laskar, “Liquid crystal polymerbased integrated passive development for RF applications,” in IEEE Int.
Microwave Symp. Dig., 2003, pp. 1155-1158, Philadelphia, PA, June 2003.
2) M.F. Davis, R.J. Pratap, S. Pinel, U. Jalan, D.-K. Kim, J. Laskar, G.S. May
“Design rule development for electrical modeling of RF multilayer packaging
inductors” presented at IEEE 2003 Proceeding 53rd Electronic Components &
Technology Conference, pp 1498-1502, New Orleans, LA, May 2003.
3) M. Davis, K. Lim, S. Pinel, E. M. Tentzeris and J. Laskar "Development of highly
integrated 3D microwave-millimeter wave radio front-end system-on-package
(SOP)” PIERS 2002, pp 495, Cambridge, Massachusetts, June 2002.
4) M.F. Davis, A. Sutono, S.-W. Yoon, S. Mandal, N. Bushyager, C.-H. Lee, K.
Lim, S. Pinel, M. Maeng; A. Obatoyinbo, S. Chakraborty, J. Laskar, E.M.
Tentzeris, T. Nonaka, R.R. Tummala, "Integrated RF architectures in fullyorganic SOP technology" IEEE Transactions on Advanced Packaging, vol. 25, no.
2 , pp. 136-142, May 2002
5) M.F. Davis, S.-W. Yoon, S. Mandal, M. Maeng, K. Lim, S. Pinel, A. Sutono, J.
Laskar, M. Tentzeris, T. Nonaka, V. Sundaram, F. Liu, and R. Tummala, “RFmicrowave multi-band design solutions for multilayer organic system on package
integrated passives,” in IEEE Int. Microwave Symp. Dig., 2002, pp. 2217-2220,
June 2002.
6) M.F. Davis, A. Sutono, A. Obatoyinbo, S. Chakraborty, K. Lim, S. Pinel, J.
Laskar, and R. Tummala, "Integrated RF architectures in fully-organic SOP
technology," presented at the 2001 IEEE EPEP Topical Meeting, pp.93-96,
Boston, MA, October, 2001.
7) M.F. Davis, A.Sutono, K.Lim, J.Laskar, V.Sundaram, J.Hobbs, G.E.White, and
R.Tummala, “RF-Microwave multi-Layer integrated passives using fully organic
system on package (SOP) technology,” IEEE MTT-S Digest, vol. 3, pp. 17311734, May 2001.
8) M.F. Davis, A. Sutono, K. Lim, J. Laskar, and R. Tummala, “Multi-layer fully
organic based system on package (SOP) technology for RF applications, IEEE
EPEP Digest, pp. 103-106, Scottsdale, Az, October 2000.
86
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9) S. Pinel, M. Davis, V. Sundaram, K. Lim, J. Laskar, G. White and R. Tummala,
“High Q passives on liquid crystal polymer substrates and pBGA technology for
3D integrated RF Front-End Module,” accepted to IEICE Transactions on
Electronics, August 2003.
10)K. Lim, M.F. Davis, M. Maeng, S. Pinel, L. Wan, J. Laskar, V. Sundataraman, G.
White, M. Swaminathan, R. Tummala “Intelligent network communicator: Highly
integrated system-on-package (SOP) testbed for RF/digital/opto applications"
Proceeding 53rd Electronic Components & Technology Conference, pp. 15941598, New Orleans, LA, May 2003.
11)S.-W. Yoon, M. Davis, K. Lim, S. Pinel, M. Maeng, C.-H. Lee, T. Nonaka, J.
Laskar, G. White, and R. Tummala, "C-band oscillator using high-Q inductors
embedded in multilayer organic packing", Presented at 2002 IEEE International
Microwave Symposium, Seattle, WA, pp. 703-706, June 2002.
12)N. Bushyager, M. Davis, E. Dalton, J. Laskar, M. Tentzeris, "Q-Factor prediction
and optimization of multilayer inductors for RF packaging microsystems using
time domain techniques," Proc. of the 52nd ECTC, pp 1718-1721, May 2002.
13)C.-H. Lee, M.F. Davis, S.-W. Yoon, S. Chakraborty, K. Lim, S Pinel, J. Laskar,
"A C-band fully organic-based transmitter module" GaAs IC Symposium, 2002.
24th Annual Technical Digest, pp. 247-250, 2002.
14)K. Lim, S. Pinel, M. Davis, A. Sutono, C.H. Lee, D. Heo, A. Obatoyinbo, J.
Laskar, E.M. Tentzeris, R. Tummala, "RF-system-on-package (SOP) for wireless
communications," IEEE Microwave Magazine, vol. 3, no. 1, pp. 88-89, March
2002 .
15) J. Laskar, S. Pinel, K. Lim, M.F. Davis M. Maeng, R. Li, M. Tentzeris, “Compact
system-on-package (SOP) architecture for low cost RF front-end module,” Invited
to GaAsIC MANTECH 2003.
16)M. Maeng, K. Lim, Y. Hur, M. F. Davis, N. Lai, S. Yoon, J. Laskar, "Novel
combiner for hybrid digital/RF Fiber-Optic application," Presented at 2002 IEEE
Radio and Wireless Conference, pp. 193-196.
17) S. Pinel, K. Lim, M. Maeng, M.F. Davis, R. Li, M. Tentzeris, and J. Laskar “RF
system-on-package (SOP) development for compact low cost wireless front-end
systems," Presented at European Microwaves Conferences 2002, Milano, Sep.
2002 .
18)J. Laskar, A. Sutono, C.H. Lee, M.F. Davis, A. Obatoyinbo, K. Lim, and M.
Tentzeris, “Development of integrated 3D radio front-end system-on-package
(SOP),” IEEE GaAs IC Symposium, pp. 215-218, Baltimore, MD, April 2001.
INVITED
87
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19)J. Laskar, E. Tentzeris, K. Lim, S. Pinel, M. Davis, A. Rhagavan, M. Maeng, SW. Yoon, R. Tummala “Advanced system-on-package RF front-ends for
emerging wireless communications” Asia-Pacific Microwave Conference, pp.
1703-1708, Kyoto, November 2002.
20)J. Laskar, A. Sutono, D. Staiculescu, C.H. Lee, M.F. Davis, K. Lim, and M.
Tentzeris, “Multi-layer 3D system-on-package (SOP) architectures for highly
integrated microwave and millimeter-wave radio front-end,” International Surface
Mount Technology Association Conference, pp. 774-777, Chicago, IL, April
2001. INVITED
21) E. Tentzeris, N. Bushyager R. Li, K. Lim, S. Pinel, M. Davis, J. Laskar, E. Zheng,
J. Papapolymerou “Analysis of MEMS and embedded components in multi-layer
packaging using FDTD/MRTD for system-on-package applications” Asia-Pacific
Microwave Conference, pp.554-557, Kyoto, November 2002.
22) V. Sundaram, F. Liu, S. Dalmia, J. Hobbs, E. Matoglu, M. Davis, T. Nonaka, J.
Laskar, M. Swaminathan, G. White, R. Tummala, “Digital and RF integration in
system-on-a-package,” Proc. of the 52nd ECTC, pp. 646-650, May 2002.
23)S. Pinel, K. Lim, G. DeJean, R. L. Li, C-H. Lee, M. Maeng, M.F. Davis, M.
Tentzeris, J. Laskar, “Advanced System-on-Package (SOP) compact and low cost
RF Wireless Systems,” accepted to European Microwaves Conference 2003.
24) J. Lee, K. Lim, S. Pinel, G. DeJean, R. Li, C.H. Lee, M.F. Davis, M. Tentzeris
and J. Laskar, “Advanced system-on-package(SOP) mulitlayer architecture for
RF/Wireless systems up to millimeter-wave frequency bands,” accepted to
APMC 2003, Seoul, November 2003.
25) S. Chakraborty, K. Lim, A. Sutono, E. Chen, S. Yoo, A. Obatoyinbo, S.W. Yoon,
M. Maeng, M.F. Davis, S. Pinel, J. Laskar, "A 2.4-GHz radio front end in RF
system-on-package technology," IEEE Microwave Magazine, vol. 3, no. 2, pp.
94-104, June 2002.
88
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