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Systematic Design of a Microwave GaN Doherty Power Amplifier

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Systematic Design of a Microwave GaN Doherty Power Amplifier
by
Kenneth Previn Samuel
A thesis submitted in conformity with the requirements
for the degree of Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
c Copyright 2017 by Kenneth Previn Samuel
ProQuest Number: 10254958
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Abstract
Systematic Design of a Microwave GaN Doherty Power Amplifier
Kenneth Previn Samuel
Master of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto
2017
Doherty PAs are the standard for efficient transmission of amplitude modulated signals. However, its
design process varies tremendously across use case, frequency range, power range, and device technology.
Due to this, the design procedure of a Doherty PA is often subjected to tuning and optimization. A
step-by-step systematic approach in designing a Doherty PA is introduced in this thesis as a consequence
of a novel method to match devices to their optimum terminations. The design methodology introduced
in this thesis can be applied to any use case irrespective of the operating conditions. To display the
functionality of this procedure, a microwave GaN Doherty PA is designed from simulations using Agilent’s
Advanced Design System (ADS). It is then fabricated and measured for performance. Good agreement
between measured and simulated data is demonstrated.
ii
This work of my hands I dedicate to my beloved parents
Previn Inbaraj Samuel & Jessie Carolyne Samuel,
whose continued support, sacrifice, and unending love has led me to great heights.
To my grandmother
Victoria Devasundaram.
And to the memory of my late grandparents
Inbaraj Samuel & Premila Inbaraj Samuel,
& Raphael Devasundaram.
Unto God,
under whose steady and mighty hand I have humbled myself and overcome all things.
I waited patiently for the lord,
and he inclined unto me and heard my cry.
He drew me up from the pit of destruction,
out of the miry bog,
and set my feet upon a rock,
making my steps secure.
He put a new song in my mouth,
a song of praise to our God.
Many will see and fear the lord
and put their trust in him.
Psalm 40:1-3
iii
Acknowledgements
It would be foolish to believe that one’s accomplishments belong to themselves alone. Without friends,
family, mentors, or companions, I would be likened to wilderness that does not bring forth any fruit,
subject only to desolation and decay. However, I’ve been blessed enough to have all four in my
possession, and their waters have turned this wilderness into a garden that bears good fruit. If it
weren’t for the likes of these people, this feat of mine would not have come to pass.
First and foremost,
Prof. George V. Eleftheriades,
for believing in me and giving me this opportunity.
My Parents.
My sister Kathleen.
Rev. David Kalison, whose support, spiritual guidance, and efforts I will not forget.
My grandmother Victoria & my late grandparents.
My extended family who have been a constant source of strength, love, and guidance.
Especially my two uncles Melvin Samuel & Joshua Alexander, whom I’ve adored.
Elders in my family that have counseled me, especially Mercy Joy,
whose sacrifice has enabled generations hence.
My confidant Naif, for his counsel, advice and brotherly love.
My friends Sorooban, Nishant, Kajani, Swakhar, Vijith, Raj, Pradeep, Shalini, Sean, Vinny, Presanna
and Jordan. For your companionship through the years.
Ben Joyner, you inspired the fire in me.
Eman Assem, for your comforting words that have enabled me to see beyond limitations.
Trevor R. Cameron, whose constant companionship and friendship during my time here has enabled
me to breakthrough critical technical challenges associated with this work.
All my friends in the research group, whom I have shared great moments with in the past few years.
May there be many of them.
Dr. Khoman Phang and Prabhu Mohan for your support in my search for admission into this program.
Venrick Azcueta for photographing the work presented in this thesis.
The teachers that have inspired within me the curiosity and have nourished it.
iv
Contents
1 Introduction
1
1.1
Motivation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Matching for Load Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.3
Known Bandwidth Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
1.4
Proposed Design Overview & Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
1.4.1
5
Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Power Amplifier Theory
2.1
2
6
Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.1.1
Ideal Non-Linear Device Current-Voltage Model . . . . . . . . . . . . . . . . . . .
6
2.1.2
Classes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.1.3
Efficiency and Conduction Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.1.4
Back-Off Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Load-pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Load Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
Doherty Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Design Considerations of a Doherty Amplifier
20
3.1
Choosing a Power Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2
Realizing a Doherty Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1
Characteristic Impedance of the Transformer . . . . . . . . . . . . . . . . . . . . . 24
3.2.2
Auxiliary Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3
Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4
Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5
Load-pull for Doherty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6
Output Impedance of the Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4 Design of a GaN Doherty Amplifier
39
4.1
Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.2
10W CREE GaN RF Power Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.3
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4
Load-pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5
Double Impedance Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.6
Transformer & Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
v
4.7
Simulation of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.8
Bandwidth Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5 Fabrication & Measurements
5.1
59
Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1.1
Broadband Wilkinson Power Divider & Input Delay . . . . . . . . . . . . . . . . . 59
5.1.2
Source Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.1.3
Output Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.2
Layout & List of Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.3
Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.4
Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6 Bandwidth of an Inverter
76
6.1
The Quarter-Wave Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2
Group Delay Contributions of Poles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3
π, T, and n-Stage Ladder Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.4
Wheatstone Bridge or Lattice Phase Equalizer . . . . . . . . . . . . . . . . . . . . . . . . 90
6.4.1
The ABCD Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.5
Lattice Network as Impedance Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.6
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
7 Conclusion
95
7.1
Recent Research Efforts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2
Key Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
7.3
Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
7.4
Closing Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Bibliography
100
vi
List of Figures
1.1
Typical matching solutions for devices used in PAs . . . . . . . . . . . . . . . . . . . . . .
3
2.1
Ideal Non-linear Device Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.2
Classification of amplifiers based on biasing. Drain current output driven by an input
signal vin shown, for varying Vgs bias points . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.3
Maximized drain current and voltage swing due to optimum load . . . . . . . . . . . . . .
9
2.4
Drain Efficiency and Output Power vs. Conduction Angle for optimum loads . . . . . . . 10
2.5
Efficiency restored in back-off operation when load resistance is increased . . . . . . . . . 11
2.6
load-pull Contour for pPmax Delivered Power . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Power delivered reduced due to sub optimum load impedance . . . . . . . . . . . . . . . . 13
2.8
Load modulation of common load R by a second source . . . . . . . . . . . . . . . . . . . 14
2.9
Load modulation with input impedance shifted by a transmission line . . . . . . . . . . . 15
2.10 Load modulation given by Eq. 2.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Load modulation required for optimum efficiency at both back-off and peak power operation 17
2.12 Doherty Amplifier Voltage, Current, Power and Efficiency relations . . . . . . . . . . . . . 18
3.1
Performance limits of power devices by technology . . . . . . . . . . . . . . . . . . . . . . 21
3.2
Traditional Doherty Amplifier topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3
0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Load inversion of Zm
3.4
Impedance modulation given in Example 3.2.1 . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5
Overshoot caused by choosing zo > zP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6
Load modulation bandwidth is reduced as a result of being pushed farther out on the
Smith chart when zo < zP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.7
Current characteristics of the main and auxiliary amplifiers . . . . . . . . . . . . . . . . . 27
3.8
Current harmonic components plotted against conduction angle α. Harmonics are normalized to Imax = 1. Note the disappearance of the 3rd harmonic when α = π. . . . . . . 29
3.9
A resonant parallel LC filter used to short out harmonic components in an ideal device.
The filter presents a short at every other frequency other than the fundamental. Zm is
the modulated load impedance seen at the fundamental frequency by the device. L∞ is
an RF choke and C∞ is a DC blocking capacitor. . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 The resonant LC tank is replaced with a short circuited shunted stub of length λ/4. This
stub shorts out the termination impedance of the device at the 2nd harmonic frequency.
At the fundamental frequency, the stub presents an open in parallel with the load Zm ,
leaving it untouched. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
vii
3.11 A λ/12 open circuited stub presents a short at the 3rd harmonic f3 , which is 3 times the
fundamental frequency f1 . At f1 , the impedance seen looking into the stub is ≈ j0.58Zo ,
where Zo is the characteristic impedance of the stub. . . . . . . . . . . . . . . . . . . . . . 31
3.12 Circuit model for a GaN HEMT proposed in [1], complete with parasitic elements. Bond
wire inductances, pad capacitances, junction to junction resistances and capacitances are
shown. Face A0 is the access point of device’s drain terminal. . . . . . . . . . . . . . . . . 32
3.13 Depiction of how load-pull contours shift when parasitics are accounted for. Drain and
source parasitics are shown, and the Smith chart depicts impedance shift going from face A
to A0 . Concentric contours on the Smith chart represent levels of degrading performance,
with optimum performance in the centre. The blue impedance is the termination the
device should see, where as the red is its conjugate which will be used in designing the
matching network. The red curves see an increase in transmission length going from
A → A0 due to the parasitics, so they shift in a clockwise fashion on the Smith chart.
Whereas, the blue curves being the conjugate of the red, shift counterclockwise. . . . . . . 33
3.14 A load-pull characterization depicting power delivered contours, blue, and PAE contours,
red. The figure highlights how the optimum impedance may differ for the two metrics. In
such a case, a design compromise between the two points is made; shown by the yellow line. 34
3.15 Example load-pull contours shown for both peak and back-off conditions. ZP and ZBO
contours shift with parasitics. ZBO is a certain VSWR away that is greater than that of
ZP , given that ZP is close to Zo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.16 The role of the matching network is shown. It matches the complex optimum impedances
to a real value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.17 The common load point is a junction of three branches, where the main, the auxiliary
and the common load are all shunted together. ZL is the impedance of the common
load presented by the output matching network of the amplifier that matches it to the
0
standard 50Ω. Zm
is the modulated impedance and Zm is its inverted version, both these
impedances are purely real. Zdev is the impedance that is to hit both optimum impedances
ZBO and ZP of the main device, it is a complex valued impedance transformed from the
purely real impedance Zm by the device matching network. Zout is the impedance seen
looking into a matched auxiliary amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.18 Output impedance Zout of the auxiliary amplifier when turned off, spans around the outer
rim of the Smith chart due to the passive lossless components of the matching network.
At the fundamental frequency f1 , it must be an open circuit. . . . . . . . . . . . . . . . . 38
4.1
K–∆ analysis of the CREE CGH40010 device under Vd = 28 V and Iq = 200 mA. Sparameter simulation from 500 MHz to 6 GHz shows K and ∆ plotted over frequency.
The device is potentially unstable for frequencies in the shaded region because K dips
below 1 in that region.
4.2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A stabilization parallel RC network is added in series with the gate with R = 15 Ω and
C = 10 pF. The resistor adds loss to the transmission path, thereby decreasing the gain
and making the device unconditionally stable. The capacitor improves high frequency
operation by providing a bypass path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
viii
4.3
The stabilization network causes the device to become unconditionally stable for most of
the usable frequency range, where K is now > 1. K and ∆ are plotted before and after
stabilization. With solid lines showing values after stabilization and dashed lines before
stabilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4
Load-pull test bench used in ADS for the CREE CGH40010 . . . . . . . . . . . . . . . . . 43
4.5
Harmonic balance one-tone load-pull of the CREE CGH40010 device model. Power is
swept and the maximum power delivered, maximum gain and gain compression is recorded
by sweeping the load across the Smith chart. ZP is chosen to be 20 + j20 Ω as a suitable
compromise between the three metrics. At about 4 dB away from ZP , ZBO is chosen
optimally to be 15 + j45 Ω. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6
2nd harmonic load-pull contours showing PAE. The fundamental load is fixed and the 2nd
harmonic load is swept to plot these contours. (a) shows that when ZBO is presented and
the amplifier is operating at back-off condition, the 2nd harmonic termination must be
close to j24 Ω for improved efficiency. (b) shows that when ZP is presented at the peak
operating condition, the termination required is much more relaxed. . . . . . . . . . . . . 46
4.7
The optimum impedances obtained from Fig. 4.5, ZBO and ZP are matched to a real
valued impedance. Matching network is first terminated with the conjugate of the opti∗
mum impedances, ZBO
and ZP∗ . The first component in the matching network is a series
∗
inductive element with reactance j0.26. This component transforms ZBO
and ZP∗ such
that they have approximately the same susceptance. Next, a shunt inductor with suscep-
tance −j0.68 moves both impedances to the real line. The final transformed real valued
0
0
∗
impedances ZBO
and ZP∗ are 107 − j4 Ω and 28 + j0.3 Ω respectively. . . . . . . . . . . . . 47
4.8
Reflection Coefficient of the matching network of the two load points . . . . . . . . . . . . 48
4.9
Complete ADS test bench of the Doherty PA . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.10 Simulated performance of the designed Doherty PA showing PAE over frequency and
output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.11 Simulation of (a) gain versus output power and (b) gain compression versus output power
of the designed Doherty PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.12 Circuit used to simulate the impedance seen by the main amplifier . . . . . . . . . . . . . 54
4.13 A load-pull contour analysis of BW 1 GHz to 1.4 GHz . . . . . . . . . . . . . . . . . . . . 56
4.14 A load-pull contour analysis of BW 1.5 GHz to 1.7 GHz . . . . . . . . . . . . . . . . . . . 57
4.15 A load-pull contour analysis of BW 1.8 GHz to 2.0 GHz . . . . . . . . . . . . . . . . . . . 58
5.1
Layout of the multistage broadband Wilkinson power divider and input delay line
. . . . 60
5.2
Layout of source matching network and stability components . . . . . . . . . . . . . . . . 61
5.3
Reflection coefficient of the source matching network . . . . . . . . . . . . . . . . . . . . . 61
5.4
Layout and schematic of the output network of the Doherty PA . . . . . . . . . . . . . . . 62
5.5
Tuning of the matching network accounting for pad delay and component dimensions . . . 64
5.6
Layout and schematic of the fabricated Doherty PA . . . . . . . . . . . . . . . . . . . . . 65
5.7
Close-up of the lumped components used . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.8
The fabricated Doherty PA photographed- showing top view
5.9
Photograph of the Doherty PA mounted onto a heat-sink . . . . . . . . . . . . . . . . . . 68
. . . . . . . . . . . . . . . . 67
5.10 The test bench setup for measuring the performance of the Doherty PA . . . . . . . . . . 69
5.11 Measured DE plotted against output power delivered . . . . . . . . . . . . . . . . . . . . . 72
ix
5.12 Comparison of back-off DE of measurement, co-simulation, and full-simulation . . . . . . 72
5.13 Measured harmonic distortion of the Doherty PA . . . . . . . . . . . . . . . . . . . . . . . 73
5.14 Co-simulated OIP3 of the Doherty PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1
Geometry of group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2
S21 poles of low pass and high pass Π networks . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3
Phase analysis of the low pass Π network . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4
Coefficients of n-stage Π network on Pascal’s triangle . . . . . . . . . . . . . . . . . . . . . 84
6.5
Poles of an n-stage Π network, shown up to 4 stages . . . . . . . . . . . . . . . . . . . . . 86
6.6
Phase and phase departure versus number of stages, showing the n-stage Π network models
a transmission line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.7
Region on the complex plane where conjugate poles contribute a phase value that is greater
6.8
Schematic of the lattice phase equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.9
Poles and zeroes of a lattice phase equalizer or Wheatstone bridge network . . . . . . . . 91
than the normalized group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.10 ABCD analysis of a lattice network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
x
Chapter 1
Introduction
The Doherty Amplifier was first introduced by William H. Doherty in 1936 as an efficient technique
used in transmitting signals with high peak-to-average power ratio (PAPR). The modulation scheme
used in these signals causes the signal to peak to high power levels occasionally, but its average power
was is lower than these peaks. Traditional fixed load amplifiers suffer from efficiency degradation when
they are not operating at peak output power. The Doherty PA introduced a technique in which the
load of the amplifier can be dynamically changed to restore efficiency at a lower power level, much
lower than the peak output power. By doing so, it improved efficiencies to up to 60-65% by means of
a load varying action of the vacuum tube impedance over the modulation cycle. It was first used in a
50 kW transmitter where the PA was operated at an efficiency of 60%, reducing the power consumption
by half when compared to a classical linear power amplifier operating at 33% efficiency [2]. By 1940,
the Doherty amplifiers were incorporated in 35 commercial radio stations worldwide, at powers of up
to 50 kW. The amplifier’s popularity and use waned with the increasing use of frequency modulated
broadcasting. It wasn’t until the emergence of digital modulation schemes, which saw a spread of carrier
signal amplitudes while broadcasting, did there come a need to re-visit the Doherty PA. In the mid
90’s, a Doherty Amplifier for microwave frequencies was introduced [3], implementing the well known
topology of a Doherty PA seen today. Since then little has changed in the topology itself, but many
variations have been proposed that allow a user to tailor design the amplifier for different use cases.
These variations in the Doherty topology will be re-visited once enough background has been developed
to discuss the topic in more detail.
In the classical topology, there exists a need for a quarter-wave transmission line or equivalently a
◦
90 phase shift between the main amplifier and load. The need for this 90◦ phase shift is warranted and
was first introduced by William H. Doherty as the impedance inverting network. It will soon be clear
why this inverting network is essential to the functioning of the Doherty PA. It is often considered that
the quarter-wave transmission line used to realize this impedance inverting network is the BW limiting
factor in an ideal Doherty PA where the transistors are modeled as current sources. While this is true,
ideal current sources do not accurately model the transistor’s behaviour with frequency. There has been
much debate over what is the BW limiting factor in a Doherty PA as seen in [4, 5, 6]. One aim of this
thesis is to shed light on this issue and how BW is inherently narrowed in the design process and why
there isn’t a universal technique to design a Doherty PA with maximal BW. In [7], there is a review of
competing Doherty PAs with claims to have increased BW. However, in this thesis, it will be clear why
1
Chapter 1. Introduction
2
two different Doherty PAs cannot be compared in BW the same way the BW of two matching networks
can be compared. This motivates the main goal of this thesis which is to construct a systematic approach
to designing a Doherty PA taking into consideration all the BW limitations and design pitfalls that one
may encounter. If designing a Doherty PA were an art form, this thesis aims to procure a detailed
list of steps a designer would take to construct a base design upon which the amplifier can be further
optimized. A specific interest is paid to developing the PA using GaN technology as it offers improved
efficiency over competing technologies, more on this topic in Chapter 2. But first, let us review the goal
of this thesis and what it aims to accomplish.
1.1
Motivation
The Doherty PA has been around for more than half a century. Yet, its design procedure is among the
least documented. This is because the procedure varies across the technology being used and across
the frequency range the amplifier is designed for. The objective in this thesis is to lay out a systematic
design procedure, which can be used by a designer to construct a Doherty PA with any RF power device
technology. Let’s first shed some light on the issues that plague the design process of Doherty PAs.
In this thesis, the focus will be on high power amplifiers, with more than 40 dBm output power. Base
stations operate at this high power regime and in this power range, the RF power devices used to realize
the amplifier are usually packaged transistors. For operating under a low power regime, the Doherty
PA can be implemented as a monolithic microwave integrated circuit [8]. But, an IC is not a suitable
platform for high power amplifiers mainly due to heat generated by the device. Due to this, a number of
challenges arise. First and foremost, the rest of the amplifier, i.e. the matching network, the impedance
inverter and other necessary components must be designed separately on a dielectric substrate. So then,
knowing that the devices being used don’t necessarily operate optimally when terminated with a 50 Ω
or 100 Ω load as in a classical Doherty PA, how does one determine the optimum loading conditions of
the device and design the output network of the Doherty PA with these loading conditions? In [3], the
impedance inverter is designed with standard characteristic of 50 Ω, but this only works if the packaged
device is matched to 50 Ω. Moreover, the Doherty amplifier has two optimum loading conditions, when it
is operating at peak output power and when it is operating at a backed-off output power. The impedance
to be presented to an ideal device is higher in back-off operation than in peak operation. This is the
premise behind the need for load modulation or inversion, and so this also applies to non-ideal devices
where the two optimum impedances are two different points on the Smith chart. Therefore, the output
network that is to be designed on a substrate, is to hit these two impedances at peak operation and
back-off operation. The traditional Doherty topology works well if these two impedances to be targeted
are purely real, because the impedance inverter modulates a purely real common load termination.
Therefore, the inverted load used at back-off power and the matched load used at peak power are both
purely real. This is a perhaps the key stumbling block in Doherty PA design.
The impedance inverter introduced by Doherty is generally realized with a quarter-wave transformer
when the amplifier is designed for microwave frequencies. The only time lumped components are used
to realize the impedance inverter is when space is at a premium, which is the case in an IC. The BW
limitations of quarter-wave transformer are well known and documented. A lumped element network
that achieves this impedance inversion, such as a Π-network, has even narrower inversion BW, see
Chapter 6. For this reason, a quarter-wave transformer is generally used to implement the impedance
3
Chapter 1. Introduction
MN
MN
ZL
(a) Typical matching procedure used in a fixed load PA
ZL
(b) Typical matching procedure used in a load modulated PA
Figure 1.1: Typical matching solutions for devices used in PAs
inverting network in a microwave Doherty PA. Another scenario when lumped components may be used
is in a lower frequency range where the wavelength might be too large to be able to implement the
inverter using a quarter-wave line, so lumped components may be used here as well. In [4], the BW
of a Doherty PA is studied, and the two major limiting factors are pointed out to be the quarter-wave
line and the output capacitance of the device being used. Now, while this is true that these do affect
the BW in a major way, it does not take into account the load-pull optimization required for achieving
high efficiency levels [9](p. 17-18). Load-pull is a widely used technique where the device is characterized
for performance by sweeping its terminating load. The device is characterized over the entire Smith
chart or over a region of the Smith chart to find optimum loading conditions. The optimum loads are
then used to design an output network for the device to get the most out of the amplifier. This type of
optimization is needed because of the large signal, non-linear operation of the device where a small signal
analysis is not sufficient to determine the optimum load. The Doherty PA’s BW has been defined by its
efficiency at back-off operation in literature and so load-pull optimization is a direct contributor to this
efficiency. This part of the design process is the least documented, especially how the device is matched
to two different optimum loads at peak operation and at back-off. In this thesis, a matching procedure
will be introduced which allows the designer to match two different complex loads to two purely real
loads. It will become apparent why this matching procedure is essential to a systematic design of the
Doherty PA. [7] introduces the idea of bringing together an understanding of device efficiency behaviour
and optimization based on load-pull contours for Doherty PA design. However, here the process of
designing a Doherty PA that is BW optimized is less apparent as most of the analysis is constructed
using a theoretical model. In practice, the impedances have to be obtained from load-pull simulations
or measurements. In this thesis, the design process will be carried out using GaN devices from CREE,
following a step-by-step method to design a Doherty PA using load-pull optimization keeping in mind
BW concerns.
1.2
Matching for Load Modulation
The standard way of wide-band matching for a simple PA, one that has a fixed load termination, is
shown in Fig. 1.1a. Here, the reactive component of the optimum load caused by the device output
capacitance and packaging are tuned out with a series inductor, and then a multi-section wide-band
matching network is used to match the real part to a load termination ZL [10]. For load modulated PAs,
the device has to be matched for two different optimum loads. So, assuming that the reactive component
of the optimum load is simply due to output capacitance of the device and also assuming that other
Chapter 1. Introduction
4
effects that contribute to the reactive component are negligible, a shunt inductor is used to resonate with
the output capacitance of the device, see Fig. 1.1b. This in theory will cause the optimum impedances to
have a purely real value, at least at the frequency of interest. However, the two optimum impedances at
back-off operation and at peak operations will not always have the same reactive component. This will
be seen later in the thesis when performing load-pull simulations on GaN devices supplied by CREE.
Simply using a shunt inductor to resonate with the output capacitance is not sufficient sometimes to
achieve purely real impedances to match. The currently used solution to overcome this is to add a
section of transmission line called an offset line. This offset-line shifts the impedance point that still has
a residual reactive component after resonant matching onto the real axis [11]. However, this method is
not well suited if the difference in reactive components of the two impedances are too great. After tuning
out the reactive component of one of the impedances, the offset-line needed to bring the other onto the
real axis will have to be of significant electrical length. Meaning, if the Q of the optimum impedance
needed to be matched using the offset-line method is too high, a significantly long piece of transmission
line will be needed to match this impedance. Using electrically long transmission lines, i.e. when the
electrical length is comparable to λ/4, causes the BW of the Doherty PA to suffer even more.
1.3
Known Bandwidth Limitations
The commonly known BW limitation of the Doherty PA is the λ/4 transmission line used as the
impedance inverter. But there are several other factors that limit the BW of a practical amplifier.
As mentioned before, [4] notes that the output capacitance of the device plays a role in limiting the
BW. In [6], the output impedance seen looking into the auxiliary amplifier is shown to be of significant concern. This impedance is to be large enough at back-off operation, such that when it is not
operating (the auxiliary amplifier), the common load is unaffected by it. This is because the auxiliary
amplifier is shunted with the common load. The device used to realize the auxiliary amplifier usually
has a sufficiently large output impedance, especially true for GaN devices, since they have small device
output capacitance [5]. However, when the matching network is introduced to match the device to their
appropriate impedance values, the impedance seen looking into the amplifier that includes the matching
network spreads much more with frequency. In order to re-establish a large impedance seen looking into
the auxiliary amplifier, an offset line is usually used. This in turn is a detriment to BW.
In this thesis, another source of BW limitation is highlighted. This limitation arises from the 2nd
harmonic termination of the device. It will be shown that the loading condition at the 2nd harmonic
frequency ultimately determines the BW of the amplifier. A simple explanation is because power consumption increases when the device delivers power to the load at harmonic frequencies, thereby lowering
the efficiency. Therefore, not only does one have to make sure the fundamental load termination of the
device is optimum for BW, the harmonic termination must be either an open or a short or a reactive load
in order to maintain high efficiency. This is obviously a very difficult, if not impossible, task because the
generally used solution to tune the harmonic loads is to use resonators [12](p.258-260). These resonators
are generally realized with stubs that short out the harmonics. However, sometimes the harmonic termination needed is not a simple short, and may be a purely complex impedance that lies on the outer edge
of the Smith chart. The reasons for this can be mainly attributed to the non-linearity of the device. This
phenomenon will be shown in this thesis and using stubs here is not an option or may not necessarily
improve performance.
Chapter 1. Introduction
1.4
5
Proposed Design Overview & Goal
This thesis will focus on using GaN devices for two main reasons. First, GaN devices often have high
reactive optimum loading conditions, and these can be hard to match to. So if a systematic design
procedure is developed for this technology, then they can be developed for others as well. Second, the
technology offers high power densities and efficiencies, which make it an attractive domain for research.
It also possesses a very large usable BW, which is desirable. However, this also makes the device more
susceptible to harmonic distortion. So, this work helps develop a plan on working with these devices.
Another avenue of interest is the BW of a Doherty PA, whose narrow BW behaviour has been well
documented. This thesis aims to shed light on where these bandwidth limitations arise and why there
has been much debate on this topic.
1.4.1
Goal
The most significant issue this thesis aims to solve is the double matching solution needed for load
modulation. In this thesis, a new method to match two arbitrary complex impedances (that are relatively
close to each other) onto two points on the real axis. This matching solution will allow the user to mitigate
the use of offset-lines, at least from a matching point of view. Using this method, the designer will be
able to maximize the BW of the match at the fundamental load. This benefit is however not directly
observed as a result of harmonic power dissipation, which degrades the efficiency of the Doherty PA.
Nonetheless, the method introduced is useful in designing the amplifier for the frequency of interest, and
its fundamental load BW competes with some of the most wide-band Doherty PAs introduced to date.
Further harmonic tuning, not discussed in this work, will allow a designer to exploit the benefit of the
method introduced in this work.
The offset-line used for the re-establishing the large output impedance of the auxiliary amplifier may
still be required, but this is less significant of an issue. With the aid of this matching solution, the design
process of the Doherty PA can be simplified, because less tuning is required. A more systematic approach
can be used to design the Doherty PA. More importantly, this method provides the best optimized BW
for the fundamental load termination, at least from a matching perspective. Harmonic termination and
sensitivity issues make it difficult to show this benefit in the fabricated amplifier. Nonetheless, the used
methodology shows the ingenuity in the optimized fundamental load match for Doherty PAs.
Chapter 2
Power Amplifier Theory
2.1
Power Amplifier
What is a PA? A PA consists of a semiconductor device that is able to deliver a desired amount of power
to an output stage, typically an antenna. The output of the PA is connected to a device that consumes
real power. Therefore it must see a real component in the impedance seen looking into the output stage.
This real part has to be matched to 50 Ω, the standard impedance to match for RF components. At
the heart of the PA is the semiconductor device. RF power transistors, aptly named, are semiconductor
devices that are tailored to operate at RF frequencies and provide ample power gain at those frequencies.
RF power transistors demonstrate the same behavior as any semiconductor device would, meaning their
current-voltage curves remain identical to those of transistors not tailored for RF. This brings us to the
first topic, the current-voltage relationships of transistors and their non-linearity.
2.1.1
Ideal Non-Linear Device Current-Voltage Model
It is essential that the non-linear behavior of the device is accounted for, because PAs operate in the
non-linear regions of the device curves. Therefore, a linear small signal model alone will not be sufficient
to study the PA. The first curve to investigate is that of the gate voltage to drain current relationship. As
Fig. 2.1a depicts, the device would turn on at a given threshold voltage Vt , conducting increasing current
with increasing gate voltage, until the device eventually leaves saturation and enters triode operation
for Vgs > Vds + Vt . The middle region, or the saturation region, is where the device acts as an amplifier.
The slope of the saturation region is the device transconductance Gm . One of the assumptions of this
model is the constant slope of the saturation region, meaning constant Gm . In practice however, there
will exists some curvature in the slope leading to weakly non-linear effects that cause distortion[13].
The other set of curves is the drain current to drain voltage relationship as depicted in Fig. 2.1b.
They portray the device operating as a current source. The drain source voltage Vds needs to overcome
the gate source voltage Vgs in order for the device to go into saturation. So there is a lower threshold for
Vds under which the device may go into triode operation. The device needs to operate above this lower
threshold known as the knee voltage, Vknee . All devices have a drain breakdown voltage, Vbreak , due
to the increasing electric field intensity in the channel as Vds increases. Vbreak will be specified by the
manufacturer in the data sheet. Also, channel length modulation is not included in this model. It will
add a finite slope in the region where the device acts as a current source. This idealization will suffice
6
7
Chapter 2. Power Amplifier Theory
Id
Id
Increasing Vgs
Vknee
Vt
Vgs
Vds
(b) Drain Current versus Drain Voltage
(a) Drain Current versus Gate Voltage
Figure 2.1: Ideal Non-linear Device Relationships
for the purpose of demonstrating the ideas discussed in this thesis.
2.1.2
Classes of Operation
There are two DC bias voltages to vary given the curves of Fig. 2.1. For the moment, let us ignore the
effects of varying Vds and assume that the transistor has been set to operate as a current source. Now,
given a time varying RF input signal vin (t) that is superimposed on to the DC bias voltage of Vgs , what
happens to Id as Vgs is varied to various bias points?
The output current waveform is shown in Fig. 2.2. When the device is biased at A, the output current
swings for both positive and negative excursions of vin . There is a DC component of Id when biased at
this point, and the signal remains undistorted at the output. Bias point B demonstrates what happens
when the device is biased at the threshold voltage Vt . Only the positive excursions of vin make it to
the output. In this case, the output waveform is heavily distorted. However, the DC component of Id
is greatly reduced when it is biased at B. When the half wave rectified waveform is decomposed into
its frequency components, it can be shown that there is a finite DC component to the waveform when
biased at B. This DC current takes away from the efficiency of the amplifier. The efficiency of the
amplifier is a measure of how much power is delivered to the output compared to the power consumed
by the amplifier. Amplifiers can now be classified based on their bias points; this gives us insight as to
how efficiently it operates. Class A amplifiers are ones that are biased at point A and Class B at point
B. Class B amplifiers are more efficient than class A ones, and one can note the trend that as bias of the
device is pushed deeper into cutoff, the more efficient the amplifier is. Class AB amplifiers are ones that
are biased between Class A and B, hence the name. Class C amplifiers are those that are biased below
threshold Vt . Notice how in Fig. 2.2 the amplitude of the output when biased at B is much lower than A;
the input swing has to be doubled in the case of B in order for it to deliver the same amount of power as
A. Therefore the gain is reduced when the amplifiers are biased more efficiently. This is the first tradeoff
for achieving higher efficiency. The other is that the output becomes distorted as only part of the cycle
8
Chapter 2. Power Amplifier Theory
Id
Id
A
C
B
Vt
t
Vgs
Figure 2.2: Shown on the left is the drain current-gate voltage relationship of a device along with the
various bias points and regions. Class A is the device biased such that the entire cycle of the input signal
is amplifier to the output. In class B, the device is biased at the threshold voltage, so only half the cycle
appears at the output. Note that the input swing has doubled so as to restore the maximum swing of
the output current. Therefore, the gain has reduced by biasing the device at a lower bias point. Class
C amplifiers comprise of devices biased below the threshold voltage. For devices biased between class
A and B, the amplifier is classified as class AB. Shown on the right is the corresponding drain current
waveform.
is amplified. This manifests itself as non-linearity in the system because now the output spectrum will
contain other frequency components that are not present in the input. To summarize, amplifiers can be
classified based on their efficiency namely Class A, AB, B, and C with increasing efficiency respectively.
The names refer to the bias point of the transistor. As amplifiers become more efficient, the gain is
reduced and the output suffers from harmonic distortion.
2.1.3
Efficiency and Conduction Angle
Although the idea of efficiency is the ratio of power delivered to power consumed, it is still loosely
defined. There are two specific definitions of efficiency in literature, namely the Drain Efficiency, η, and
the Power-Added Efficiency, P AE. η is simply the ratio of the output power of the fundamental tone
or frequency of interest to the DC power consumption of the transistor. P AE adds one more degree of
detail to η by accounting for the input power consumed in operating the device. If Pfund is the power
level of the fundamental tone in the spectrum then,
η=
Pout,fund
PDC
(2.1)
9
Chapter 2. Power Amplifier Theory
P AE =
Pout,fund − Pin,fund
PDC
(2.2)
So far, the amplifiers were classified discretely into their classes based on efficiency. However, it is
a continuous spectrum rather than a discrete one. So in order to paint the complete picture, let us
introduce the conduction angle approach [13] (p.47-49). The conduction angle α, is simply the part of
the cycle for which the transistor is turned on. For example, if the transistor is biased at cutoff, only
the positive excursions of the input waveform cycle will be amplified to the output. Since half of the
cycle is being amplified, this is equivalent to saying α is equal to π. Then for a Class A amplifier, since
it amplifies the complete cycle, the conduction angle is 2π. The amplitude of the nth component of the
current can be found by integrating the inner product between the output waveform and nth frequency
tone over the entire cycle. The equation is given in [1](p.48) where Imax is the maximum value of the
output current,
1
In =
π
Z
α/2
Imax
α
) cos nθ dθ.
α (cos θ − cos
1
−
cos
2
−α/2
2
(2.3)
The DC component and the fundamental tone, where n = 0 and n = 1 respectively, are the ones of
interest because they are needed to compute efficiency. For the two cases, equation 2.3 simplifies to:
IDC =
Imax 2 sin α2 − α cos α2
2π
1 − cos α2
(2.4)
Imax α − sin α
2π 1 − cos α2
(2.5)
Ifund =
The voltage at the drain terminal is trivial to compute. The DC component of it is simply the drain
bias voltage, which is set to the supply voltage VDC . Given that optimum load is presented to the drain
of the transistor, the maximized output swing of the voltage at the fundamental tone, Vfund , will have
an amplitude of VDC . This can be seen in Fig. 2.3, where the voltage reaches a maximum of 2VDC when
id = 0, i.e. assuming that the knee voltage, Vknee , is negligible (≈ 0). The quiescent current, Iq , is simply
the DC bias current flowing through the transistor when no input is applied. Drain voltage follows the
current on the dotted line as the output swings. This line is solely defined by the impedance of the load
Id
Iq , VDC
Vknee
Vds
Figure 2.3: Maximized drain current and voltage swing due to optimum load
10
Chapter 2. Power Amplifier Theory
1
2 VDC Ifund
Output Power Pout
Drain Efficiency η
1
0.5
η
Pout
π
0
Class
C
B
α
AB
A
Figure 2.4: Drain Efficiency and Output Power vs. Conduction Angle for optimum loads
presented to the drain terminal. In order for maximum power to be delivered to the load, the swinging
of the voltage and current must be maximized by presenting an optimum load.
Now, all the necessary elements to form an expression for efficiency are at hand. Drain efficiency for
the specific case of maximized output swing can be modeled as
η=
VDC Ifund
Pout,fund
α − sin α
Ifund
1
2
=
=
=
PDC
VDC IDC
2IDC
4 sin α2 − α2 cos α2
(2.6)
Although the amplifier becomes extremely efficient as it is biased deeper into class C, it is important to
note that the power delivered to the load also approaches 0. It is also important to keep in mind that
the efficiency curve in Fig. 2.4 only holds when the optimum load is presented. This is an issue when
the amplitude of the input signal varies with time. One can no longer present a single optimum load to
the device to maximize the output swing for all input drive conditions. The next section examines what
happens when the transistor is driven with a reduced input signal or equivalently what happens when
the output is backed-off from its optimum operating condition.
2.1.4
Back-Off Operation
If the amplitude of the signal that drives the input is reduced, the output will also be reduced. Let’s say
the output is reduced by a factor ζ. Now the peak current value will be ζImax . So then from (2.4) and
(2.5), it can be said that both IDC and Ifund will also be reduced by ζ. Fig. 2.5a shows how the output
swing is lowered from its maximum operating condition. It is also clear that the fundamental tone of the
drain voltage will also be lowered by the same factor ζ from its maximum condition. However, the DC
component of the drain voltage will be unaffected by this lowered swing and will remain at the supply
voltage VDC . So let’s compute what the efficiency will be
ζV
η=
ζI
DC
fund
ζIfund
ζ
α − sin α
Pout,fund
2
=
=
=
PDC
VDC ζIDC
2IDC
4 sin α2 − α2 cos α2
(2.7)
11
Chapter 2. Power Amplifier Theory
vds (t)
vds (t)
Id
Id
Iq , VDC
Vknee
Iq , VDC
id (t)
Vds
Vknee
(a) Reduced output swing
id (t)
Vds
(b) Voltage swing is restored
Figure 2.5: Efficiency restored in back-off operation when load resistance is increased
It is clear now that the efficiency will also drop by the same factor ζ when the swing is reduced. This
often leads to poor efficiency performance of PAs when the driving signal is not of constant amplitude,
which is the case in many modulated schemes. One can always design an amplifier to yield maximized
swing if the input signal has a constant amplitude that is known. However, this is not the case for
modulated signals. For such signals, the waveform has an average amplitude and peaks occasionally.
If the PA is designed to be optimized for the average amplitude, then the peaks in the signal may be
lost due to clipping. Likewise, if it is designed to be optimized for peak amplitude operation, then
the amplifier suffers from efficiency degradation because the driving signal spends most of the time at
a reduced drive level. From Fig. 2.5a it is obvious that the drain voltage swing can be restored to
its original amplitude by simply using a shallower slope. This is demonstrated in Fig. 2.5b where the
voltage swing is restored to its maximum by increasing the load resistance by the same factor ζ. Now
the amplitude of the fundamental tone of the voltage will be restored to its maximized value of VDC .
This in turn will restore the efficiency of the amplifier to (2.6). The answer may seem simple as to what
the terminating load impedance must be for optimum performance and one may come to the conclusion
that it is the slope of the line that subtends the maximum swing of voltage for a given current (2.8).
Ropt =
VDC Ifund
ζ
(2.8)
This method of estimating the optimum impedance is known as the load-line theory or the Cripps
method. There has been some debate about whether the output waveform actually follows the DC
curves of the device drain current-voltage curves. Nevertheless, it is a good starting point to understand
optimum loads. A more rigorous method known as load-pull is used in practice to determine the optimum
loads of any device under known operating conditions. This is done by sweeping the load presented to the
device over regions of the Smith chart and extracting performance metrics such as gain, power delivered,
efficiency and gain compression. But it is a good sanity check to ensure the optimum loads evolve in
correspondence with load-line theory.
12
Chapter 2. Power Amplifier Theory
p
pRopt + jXm = Ropt φm = [ Ropt
+ jBm ]−1
Y =
Z = pRopt + jX
pRopt
Ropt
p
Ropt
+ jB
Ropt /p
Z = pRopt − jX
Y =
p
Ropt
− jB
p
pRopt − jXm = Ropt −φm = [ Ropt
− jBm ]−1
Figure 2.6: load-pull Contour for pPmax Delivered Power
2.2
Load-pull
If, say the optimum load through the load-line method is found to be Ropt . Then if Ropt is decreased
by a factor of p, it will cause the voltage swing to drop for maximized current swing. On the contrary,
if Ropt increased by the same factor p, then the voltage will saturate to its maximum swing well before
the current reaches its maximum and so the current swing is compromised. In either case, the total
power delivered to the load will decrease by a factor of p. In the first case the voltage is reduced and in
the second case the current is reduced. Note that in both these scenarios the current and voltage are in
phase with each other, this is because the load impedance is purely real. The drop in power is simply
due to the sub optimum swing of the voltage or current waveform. The loads are shown on the Smith
chart in Fig. 2.6, where the impedance moves to the left of Ropt when it is decreased and to right when
it is increased. At these two terminal points the power delivered is a factor p less than the maximum
operating power Pmax which occurs at Ropt .
Let’s first examine the case when the impedance is less than Ropt , this is the point marked as pRopt
in Fig. 2.6. In this case, the voltage will never reach the full swing although the current is maximized,
see Fig. 2.7a. It is apt to say that the swing is voltage limited. If a reactive component jX is added to
this impedance pRopt , the impedance will move up on the circle of constant resistance as depicted by the
green curve in Fig. 2.6. The impedance pRopt + jX will have increasing magnitude as jX is increased.
However, the current and voltage will now acquire a phase difference due to the imaginary part of the
impedance. As jX is increased, the magnitude of the complex impedance will eventually equal Ropt .
The voltage swing will now be restored to its maximum. However, due to the difference in phase φm
between the voltage and current, the power delivered will still be a factor of p lower than Pmax . This
13
Chapter 2. Power Amplifier Theory
vds (t)
Id
Id
pRopt
Ropt
Ropt
Vds
Vds
(a) Voltage limited output swing
id (t)
Ropt /p
(b) Current limited output swing
Figure 2.7: Power delivered reduced due to sub optimum load impedance
restored point is depicted in Fig. 2.6 as the northern most tip of the contour. The same can be said
if the reactive component is −jX, only now the impedance moves downward from pRopt on the same
constant resistance circle, marked by the red curve in Fig. 2.6. In the end, the magnitude of the complex
impedance will once again reach Ropt . But the phase between the current and voltage will now be −φm ,
because this impedance is simply the conjugate of the case mentioned earlier.
The blue and purple curves of Fig. 2.6 are simply the dual of the voltage limited case. Only now the
swing is current limited as in Fig. 2.7b and adding a shunt susceptance ±jB will gradually restore the
current swing. Once again the voltage and current will inquire a ±φm phase shift as the current swing
is restored when magnitude is Ropt .
The four segments traced form an enclosed contour on the Smith chart. The points along this
contour simply specify the impedances for which the PA will deliver a factor of p less power than its
max output. As p → 1 the contour becomes smaller and smaller till it becomes the point at Ropt . As
p → 0, the contour becomes larger and larger. It can be thought of as a tolerance for power delivered.
The smaller the tolerance, the smaller the target region on the Smith chart. In practice, the device is
characterized nearly over the entire Smith chart. Its DC power consumption, gain, gain compression and
power delivered are recorded for each impedance point on the Smith chart. It will be shown later in the
thesis how these contours are obtained and also how the optimum contours don’t necessarily coincide
with each other. So, not only can power contours be produced, but also contours for efficiency and gain.
With the help of these contours, performance can be tailored for various requirements.
It is important not to confuse load-pull contours with back-off efficiency restoration as in 2.1.4. Loadpull contours simply give insight as to how the performance degrades from the optimum load. Back-off
operation arises from reduced drive strength of the output current. This means there is a limited amount
of current swing available. So, as the available current swing decreases, the optimum load point on the
Smith chart moves to the right (increases) to maximize the voltage swing for the given current swing.
The contours that enclose this optimum load also move in conjunction with it. If the load is not in
its optimum point, there will be a decrease in efficiency because the PA is not delivering the maximum
14
Chapter 2. Power Amplifier Theory
amount of power it is capable of delivering for a given bias point. Since the optimum load moves with
drive strength, a method to modulate the load under varying drive strengths in required. This is known
as load modulation.
2.3
Load Modulation
A simple circuit with two current sources I1 and I2 delivering current to a common load R, will be the
premise behind how load can be dynamically modulated. In the circuit in Fig. 2.8, the impedance seen
by the first source I1 is simply
Zin,1 =
1+
I2
R;
I1
(2.9)
As the second source I2 delivers current to the common load, the load seen by the first source, Zin,1 ,
increases. If the second source is turned off, then Zin,1 simply equals R. Note that the ratio of the
amplitude of the two currents are what controls Zin,1 . Therefore, if the first source is to see twice the
common resistance, then I2 must deliver the same current as I1 .
Now, a transmission line is introduced between the first source and the common load as in Fig. 2.9.
Before explaining the significance of this transmission line, let us come up with an expression for the
input impedance seen by the first source Zin,1 . Let’s express the transmission line as ABCD matrix first.
Then the equations to solve are:
VL = R I10 + I2
(2.10)
V1 = AVL + BI10
(2.11)
DI10
(2.12)
I1 = CVL +
Substitute 2.10 into 2.11 and 2.12
V1 = AR I10 + I2 + BI10
= AR + B)I10 + ARI2
I10 =
V1 − ARI2
AR + B
(2.13)
Zin,1
I1
R
I2
Figure 2.8: Load modulation of common load R by a second source
15
Chapter 2. Power Amplifier Theory
θ · Zo
+
I10
+
Zin,1
I1
V1
IL
VL
−
I2 ∠θ
R
−
Figure 2.9: Load modulation with input impedance shifted by a transmission line
I1 = CR I10 + I2 + DI10
= CR + D)I10 + CRI2
I10 =
I1 − CRI2
CR + D
(2.14)
Substitute 2.13 into 2.14
I1 − CRI2
V1 − ARI2
=
AR + B
CR + D
AD − BC
AR + B
I1 + R
I2
V1 =
CR + D
CR + D
V1
AD − BC I2
AR + B
Zin,1 =
+R
=
I1
CR + D
CR + D I1
The ABCD matrix of a transmission line with characteristic impedance Zo =
(2.15)
1
Yo
and electrical length θ
is given in [14]:
"
Substitute 2.16 into 2.15
Zin,1 =
cos θ
jZo sin θ
jYo sin θ
cos θ
#
R cos θ + jZo sin θ
R
I2
+ R
j ZRo sin θ + cos θ
j Zo sin θ + cos θ I1
(2.16)
(2.17)
Now, the second current I2 is in phase with I1 , but leads I10 by θ due to the delay added by the transmission line. The currents have to be in phase at the common load point in order for the power supplied
by each source to add up. Therefore, a phase delay of θ is added to the second source. The phase delay
can be written as e−jθ or equivalently cos θ − j sin θ. (2.17) becomes
Zin,1
R cos θ + jZo sin θ R cos θ − j sin θ I2
=
+ R
j ZRo sin θ + cos θ
j Zo sin θ + cos θ I1
(2.18)
16
Chapter 2. Power Amplifier Theory
θ = 45◦
θ = 45◦
θ
θ = 22.5◦
θ
θ = 0◦
θ = 22.5◦
θ = 67.5◦
0.25
0.5
0.8
1.25
2
4
r
θ = 90◦
θ = 0◦
θ = 67.5◦
0.25
0.5
2
4
θ = 90◦
I2
I1
(a) Zin,1 when I2 = 0, sweeping r and θ
(b) Zin,1 when I2 /I1 is increased
Figure 2.10: Load modulation given by Eq. 2.18
First, let us examine the case when the second source is not supplying any current. The circuit
in Fig. 2.9 simply becomes a transmission line terminated with a load. The output impedance of the
second current source is infinity as it is a perfect current source. (2.18) simplifies and only the first term
remains, the second vanishes because I2 = 0. Assume a normalized characteristic impedance, zo = 1,
and plot zin,1 on a Smith chart while sweeping θ and r. Fig. 2.10a depicts what happens to zin,1 when
this happens. As r starts at 1 and gets smaller, the impedance goes from the centre of the Smith chart
and moves left. If θ is then increased, the impedance gets translated clockwise. When θ = 90◦ , the load
is inverted zin,1 = 1/r. If the impedance at the common load is decreased, zin,1 will see an increase and
vice versa. This is because the radius of the arc that is swept will change as the common load impedance
is changed.
Now, let’s examine the second part of (2.18), the component which depends on the presence of I2 .
As I2 is increased, the impedance moves towards the centre Smith chart as depicted in Fig. 2.10b. The
orange curves show how a common load of r = 0.5 is modulated as the ratio of the currents I2 /I1 is
increased. The magenta curves are the modulation for r = 0.25. In either case, the impedance can be
swept within the circle set by the common load by controlling the second source.
What happens at the impedance seen looking into the load just after the transmission line, i.e. the
impedance zin,1 translated to the right by the length of the line? When the second source starts supplying
current, the impedance increases as given by Eq. 2.9. When I2 = I1 , the common load impedance would
have doubled. When I2 = 2I1 , it would have tripled. When I2 = 3I1 , it would have quadrupled and so
forth. Therefore, looking at Fig. 2.10b, in order to bring the common load of r = 0.5 to 1, i.e. to double
the impedance, the ratio of the currents must be 1. For the case when r = 0.25, the impedance has to
be quadrupled in order for r = 1. Therefore I2 must equal 3I1 to bring the impedance to the centre of
the Smith chart. The greater the mismatch between the common load and the characteristic impedance,
the greater the current ratio needed to achieve the complete modulation range.
Of all the swept values of θ, the most interesting one is of θ = 90◦ . The input impedance zin,1 is the
mirror of what happens at the common load point. As the common load impedance moves from 0.5 → 1,
zin,1 moves from 2 → 1. This inverting property is key because now the impedance actually decreases
17
Chapter 2. Power Amplifier Theory
θ = 45◦
θ
θ = 22.5◦
θ = 0◦
PP
OBO
θ = 67.5◦
θ = 90◦
I2
I1
Figure 2.11: Load modulation required for optimum efficiency at both back-off and peak power operation
as the second source starts to become active. Section 2.1.4 shed light on how the load impedance must
increase when the drive strength is backed-off; voltage swing will increase with increasing impedance
as current is lowered. It will be later discussed how the scenario when the second source I2 is turned
off is analogous to back-off operation. Subsequently, when I2 is delivering maximum current, it is the
equivalent of peak power operation where the available current swing is at a maximum and therefore the
load impedance required is smaller than that of back-off operation. This property of the inverted load
when θ = 90◦ is at the heart of the Doherty Power Amplifier.
2.4
Doherty Power Amplifier
The Doherty Amplifier was first introduced by William H. Doherty in 1936 [15]. It aimed to solve the
issue of amplifier efficiency during back-off operation. Much was discussed about how the efficiency
suffers under lowered input drive conditions for a simple power amplifier. Load modulation discussed
in the last section allows for a way to change the load by using a second source. If the impedance is
tailored such that it can be adjusted when the current swing drops under reduced drive conditions, i.e.
the impedance remains high, and when the current swing is at a maximum, the impedance is restored to
its smaller optimum value, as in Fig. 2.5, optimum efficiency performance can be achieved during back off
operation. Load modulation allows for a way to achieve that. The question now is how to introduce the
second source into the amplifier and turn it on and off appropriately to modulate the load as required?
Let us answer this by first stating what is required:
• Under maximum input drive, the impedance is smaller and the second source is supplying current
• Under reduced input drive, the impedance is greater and the second source is turned off
The solution presents itself from these two requirements. In Fig. 2.10b, the impedance evolution requirement is fulfilled when θ = 90◦ . Now, the other part of the requirement is that I2 be turned off when
the input is backed off and only I1 be functional. If these current sources were transistor amplifiers,
from section 2.1.2, I2 can be realized using a class C amplifier. That way it will only function above a
certain threshold of input power. During back-off operation, i.e. when input strength is reduced below
18
Chapter 2. Power Amplifier Theory
1
|id |
1
(a) Current versus Input Voltage swing
ert
y
π
4
Do
h
I2
I1
Drain Efficiency η (%)
Imax
sB
as
Cl
Pmax -6 dB
Output Power Pout (dBm)
|vin |
Pmax
(b) Drain Efficiency versus Output Power for a Doherty power
amplifiers
Figure 2.12: Doherty Amplifier Voltage, Current, Power and Efficiency relations
a certain threshold, I2 remains inactive. This threshold can be set by adjusting the gate bias of the
transistor. The input drive condition that pushes the second source to the brink of turning on is called
the input back-off point. The corresponding output that is a result of this drive condition is the output
back-off power, OBO. Likewise, the input drive condition that causes the the second source to deliver
the maximum intended amount of current such that the impedance moves to the centre of the Smith
chart as in Fig. 2.10b is the peak input point. Its corresponding output power point is the peak output
power, PP. These two operating points are shown in Fig. 2.11. When the first source or device sees this
type of load evolution, its efficiency performance will be optimum.
The ability to pull the load from a higher impedance value to the centre of the Smith chart depends
on how much current the second source is capable of supplying. Ideally, the current to input voltage
magnitude relationships should resemble Fig. 2.12a for a common load R = 0.5. Here, only the first
source supplies current until the input voltage swing is half of its peak value which is normalized to 1.
The second source only becomes active once the input voltage swing’s amplitude crosses this halfway
point. This can be controlled by selecting an appropriate gate bias for the device used to realize the
second source. Notice how I2 has a steeper rise with current amplitude than I1 . This has to hold in
order to achieve the complete modulation range within a given input voltage swing. Because of the way
I2 is biased, half the amplitude of the input swing will be chopped off. So I2 has to catch up to the same
amount of current supplied as I1 in the remaining half input swing. If this does not happen, then the
impedance is not modulated all the way to the centre of the Smith chart as in Fig. 2.11.
If such an amplifier was constructed, and I1 is realized using a class B amplifier, then according to
Section 2.1.2 and Fig. 2.4, the constructed Doherty amplifier will have to operate at η = π/4 efficiency at
OBO and PP. The resulting efficiency versus output power relationship will resemble that of Fig. 2.12b.
Here, the OBO is at a quarter of the peak power or equivalently 6 dB back-off point from PP. This 6 dB
back-off is because I1 delivers half the maximum current and I2 delivers 0 at OBO. Then at PP both I1
and I2 supply max current, which yields a total current that is 4 times that of OBO operation. Notice
how the Doherty power amplifier does not suffer from efficiency degradation at back off operation when
compared to a classical class B amplifier. In the range where the load is being modulated, between
Chapter 2. Power Amplifier Theory
19
OBO and PP, there will be a slight dip in efficiency based on how well the load modulation tracks the
optimum impedance.
Chapter 3
Design Considerations of a Doherty
Amplifier
Now that the working principle behind a Doherty Amplifier has been introduced, let us delve into what
it takes to design one.
3.1
Choosing a Power Device
The first step in building any PA is to pick the type of power device. This choice greatly affects what
comes after. To start, there is a number of semiconductor materials and device structures to choose from.
Large scale production for RF and microwave power devices for commercial purposes are mainly silicon
(Si) and gallium arsenide (GaAs) based technology. Whereas, research interests are widely devoted to
using wide-band-gap materials such as gallium nitride (GaN) and silicon carbide (SiC) for their innate
property of high power density.
Devices are also characterized by their structures. Bipolar-Junction Transistors (BJT) and FieldEffect Transistors (FET) are two main classifications of structures. Under these two main classes are
different and improved structures which include the Heterojunction Bipolar Transistors (HBT), Metal
Oxide Semiconductor FET (MOSFET), and Metal Semiconductor FET (MESFET). An even further
subclass of the MOSFET is the Laterally Diffused MOSFET (LDMOSFET or LDMOS), and of the
MESFET is the High Electron Mobility Transistor (HEMT). GaN devices are typically fabricated as
HEMT structures as they have improved electron mobility over the MESFET due to the availability of
heterojuction technology. They can also be developed as MESFETs but typically are not since HEMTs
are superior[16].
Energy band-gap is the energy required moving an electron from the valence band into the conduction
band. Having a large band-gap implies it is capable of supporting higher internal electric fields before
breakdown and so devices with higher power densities can be constructed. Achieving high power densities
is a priority as it not only reduces size, it also increases the optimum terminating impedance of the device
which is necessary for easier matching. The ideal impedance range to match is in the tens of ohms. SiC
MESFETs and GaN HEMTs are of particular interest in this regard. RF output power densities are on
the order of 4-7 W/mm and 10-12 W/mm respectively [17]. The electron mobility of SiC MESFETs is
significantly lower than that of GaN due to the lack of heterojunction technology. The substrates for SiC
20
21
Chapter 3. Design Considerations of a Doherty Amplifier
70
GaAs
GaN
Si
60
40
Pout(dBm)
50
Efficiency(%)
GaAs
GaN
Si
50
40
30
20
30
20
10
10
0
0
0
5
10
15
20
Frequency(GHz)
25
30
35
(a) Efficiency vs. Frequency
0
5
10
15
20
25
Frequency(GHz)
30
35
40
(b) Output Power vs. Frequency
Figure 3.1: Performance limits of power devices by technology
are also costly, have limited wafer diameter, and are prone to micro defects affecting manufacture and
yield. If these issues are not addressed, SiC MESFETs will not be able to compete in the base station
power amplifier market [16]. GaN HEMTs on the other hand are an attractive option for frequency
bands anywhere from a few GHz to up to the 10 GHz range.
What is probably the most enticing trait of GaN technology is the higher efficiency it offers on top
of the high output powers compared to its competitors as shown in Fig. 3.1a. Of course, some GaAs and
Si devices allow for operation past 30 GHz, which is less common in GaN. However, for a few GHz to
tens of GHz, GaN is a viable option. This range of frequencies is of interest for base station PA design.
GaN also offers more output power than other competing technologies due to its high power density
capabilities. Its comparison relative to other popular semiconductor materials are shown in Fig. 3.1b.
Since the main concern with building a Doherty PA is efficiency, the choice in terms of what device to
use is obvious. Unmatched GaN devices also possess an extremely wide, potentially usable BW. They
are typically rated from DC to 10 GHz. Matching it however will greatly reduce the BW because PAs
are typically optimized for a certain range. As will be shown later while performing load-pull, it is hard
if not impossible to match discrete devices such as these over decades of bands.
3.2
Realizing a Doherty Amplifier
Much has been discussed about how a Doherty amplifier works and the conditions required for load
modulation in Section 2.4. But what components comprise the Doherty PA? In Section 2.3, it was shown
that a 90◦ phase shift is needed between the main amplifier and the common load to achieve load
inversion. This phase shift is achieved by introducing a TX line as in Fig. 2.9. I1 is replaced by a class
AB amplifier called the main amplifier, and I2 is replaced by a class C amplifier called the auxiliary
amplifier. To compensate for the phase difference between the two amplifier branches so that the current
arrives at the same phase at the common load point, another transmission line of 90◦ phase is introduced
at the input of the auxiliary amplifier. In a typical scenario, the common load impedance required will
not be 50 Ω, so a matching network is needed to match the required load to the terminating impedance
which is in most cases 50 Ω. This traditional topology is depicted in Fig. 3.2. Here, notable impedance
points on the circuit are labeled and will be referred to later in the text. Zm is the impedance seen
0
by the main amplifier, this is the inverted modulated impedance. Zm
is the non-inverted modulated
22
Chapter 3. Design Considerations of a Doherty Amplifier
M
Zm
90◦ · Zo
OMN
Zm0
ZL
50 Ω
90◦ · Zo
A
Zout
Figure 3.2: Traditional Doherty Amplifier topology
impedance. ZL is the common load impedance, it was denoted as R in Section 2.3. Za is the impedance
seen by the auxiliary amplifier and is of less significance. Zout is the output impedance of the auxiliary
amplifier. Ideally, Zout would be an open when the auxiliary is turned off. There is also the characteristic
impedance of Zo of the quarter wave transformer. A power splitter is used to divide the input signal into
the separate branches. The function of the input feed is really to split the incoming signal and compensate
for the phase difference so that the currents appear in phase at the common load. A quadrature coupler
could also achieve this functionality. Note that the input power is depicted as being split evenly here.
However, the ratio of the split is subject to the desired drive strength of the two branches. As it will
become clear later, there isn’t a clear choice in the split in power ratio, but rather it is a design choice
that needs to be made based on the relative amplifying strength of the two branches.
How does one determine the impedance ZL ? Or the characteristic impedance Zo ? From Section 2.4,
0
has to be inverted, i.e. mirrored across the centre of the Smith
it was clear that the modulated load Zm
0
and Zm are simply the mirrored
chart so that the impedance decreases with increasing drive strength. Zm
0
is purely real. At back-off, Zm = ZBO
locus across the y-axis of the Smith chart, assuming that Zm
0
= ZL , then ZL is simply the mirrored point of ZBO as depicted by Fig. 3.3. When the auxiliary
and Zm
0
starts to see an increase from ZL , denoted by the arrow in Fig. 3.3. At peak
starts to deliver current, Zm
0
sees is directly linked to the current ratio between the main
power output, the maximum increase Zm
and auxiliary. In order to modulate the impedance, the auxiliary amplifier has to drive more and more
current into the common load ZL . The amount of current the auxiliary amplifier supplies relative to the
0
main amplifier under peak conditions directly affects the modulation range. For example, if Zm
has to
move from ZL → 2ZL , then the auxiliary has to supply equal amount of current as the main. If it has
to move to 3ZL , then it has to supply 2 times the current as the main. How to determine much current
ratio is required? Looking at the inverted impedance Zm in Fig. 3.3, at peak operating condition, Zm
should reach ZP and at back-off it must remain at ZBO . So the current ratio is determined from the
modulation range M .
Zm : ZBO → ZP
M=
ZBO
ZP
0
Zm
then has to swing from ZL → M ZL . So, the current ratio is given by
(3.1)
Chapter 3. Design Considerations of a Doherty Amplifier
23
ZBO
M
ZBO
ZP
ZL
Z0m
Zm
M ZL
0
Figure 3.3: Load inversion of Zm
Iaux : Imain = {M − 1} : 1
(3.2)
However, this is not the only condition to be able to hit both points ZP and ZBO . Zo and ZL values
play a role in achieving target impedances. In most cases Zo ≈ ZP . More on that later, let’s first look
at an example.
Example 3.2.1. The back-off impedance ZBO and the peak impedance ZP is found from load-pull to
be 60 Ω and 20 Ω respectively. Given a 20 Ω quarter wave transformer, find the modulation range M ,
current ratios Iaux : Imain , and the common load ZL .
M=
60
ZBO
=3
=
ZP
20
Iaux : Imain = M − 1 : 1 = 2 : 1
(3.3)
Zo = 20 Ω
ZL =
202
Zo2
=
= 6.67 Ω
ZBO
60
0
The modulation locus of the impedances Zm and Zm
are given in Fig. 3.4. An auxiliary amplifier
that supplies twice as much current as the main amplifier at peak operation is required to achieve this
modulation range.
20 Ω
6.67 Ω
60 Ω
Z0m
Zm
Figure 3.4: Impedance modulation given in Example 3.2.1
Chapter 3. Design Considerations of a Doherty Amplifier
3.2.1
24
Characteristic Impedance of the Transformer
In Example 3.2.1, Zo was given and it was purposely chosen to be the same as ZP . Let’s see what
happens when Zo is increased from the nominal value of ZP . The problem in Example 3.2.1 is plotted
on a normalized Smith chart in Fig. 3.5. zo is slowly increased, moving from zP → zBO as shown in the
subsequent Smith charts. First, notice that zL increases with increasing zo in order to mirror to zBO at
back-off.
ZL =
Zo2
ZBO
(3.4)
Eq. 2.18 can then be rewritten for θ = 90◦ , Zin,1 = Zm , and R = ZL from Eq. 3.4 as
Zm = ZBO − Zo
I2
I1
(3.5)
When zo is increased, i.e. brought closer to zBO , the mismatch between these two points is lowered.
This means the mismatch with common load zL is also lowered, thereby seeing an increase in zL as
0
depicted by Fig. 3.5, where zL goes from 0.33 → 0.39 → 0.47. The point M zL of zm
, where M = 3, now
begins to cross the centre of the Smith chart. This crossing is also apparent in Eq. 3.5, where the second
modulated term of zo II12 = 2zo is greater than the first term zBO at peak operation. When the crossing
is projected on to zm , it overshoots the target zP . The solution then is to lower the modulation range M
so that it does not overshoot zP . However, this has consequences. It will lower the current supplied by
the auxiliary, thereby lowering the peak delivered power. This in turn means a lowered back-off point.
Therefore, it is not advisable to choose zo > zP .
How about choosing a zo < zP ? The opposite starts to happen where Fig. 3.6 depicts this scenario.
At peak operation of the auxiliary, i.e. I2 = 2I1 , the impedance zm comes short of meeting the peak
impedance zP . The only way to restore the impedance modulation is to increase the modulation range
M by increasing the max current supplied by the auxiliary. This also has the effect of increasing the
0
are pushed further out into the
peak delivered power contrary to the previous scenario. Also, zm and zm
Smith chart as zo increases. Since the points farther out transform more aggressively with frequency,
the bandwidth of the load modulation scheme is inherently lower as a result of this. So therefore the
most optimum point is in fact zo = zP . Of course, this is only possible is zP is purely real. If so,
the characteristic impedance of the transmission line can be be easily determined using this method.
However, most zP values will have some reactive component to them. This is where a matching procedure
is used to transform the complex impedance into a purely real value, which will be covered later on in
the thesis.
This discussion assumed that the modulation range M can be set by adjusting the strength of the
auxiliary amplifier. But in practicality, the size and strength of the auxiliary amplifier is not a flexible
design parameter. Therefore, it may be necessary to adjust the characteristic impedance so that the
load modulation scheme is able to hit both the zBO and zP impedance points with a fixed M . That is,
if M falls below the required value, zo > zP should be used and vice-versa.
25
Chapter 3. Design Considerations of a Doherty Amplifier
zP = 1
zL = 0.33
zm
zBO = 3
z0m
zP = 0.85
zL = 0.39
zm
zBO = 2.55
z0m
zP = 0.7
zL = 0.47
zm
zBO = 2.1
z0m
Figure 3.5: Overshoot caused by choosing zo > zP .
26
Chapter 3. Design Considerations of a Doherty Amplifier
zP = 1.1
zL = 0.303
zBO = 3.3
z0m
zm
zP = 1.5
zL = 0.22
zBO = 4.5
z0m
zm
zP = 2
zL = 0.17
zBO = 6
z0m
zm
Figure 3.6: Load modulation bandwidth is reduced as a result of being pushed farther out on the Smith
chart when zo < zP .
27
Chapter 3. Design Considerations of a Doherty Amplifier
Id
(M − 1)Imain,pk
Iau
x
Imain,pk
ai
n
Im
0
0.5
Vin,BO
Vin
1
Active Auxiliary
Figure 3.7: Current characteristics of the main and auxiliary amplifiers .
3.2.2
Auxiliary Amplifier
The modulation range M is a parameter that is solely defined by the current supplied by the auxiliary
amplifier at peak operation. By supplying M − 1 times the current of I1 , it modulates the common
0
load impedance Zm
from ZL → M ZL . As mentioned earlier, M is not a very flexible design parameter,
because it is difficult to find transistors that possesses the needed properties. For one, the auxiliary
amplifier is turned off until the back-off point, and it has to catch up to supplying the required current
of (M − 1)I1 with a shortened input drive. Depicted in Fig. 3.7, the range for which the auxiliary
amplifier is active is a smaller window of the input voltage drive than that of the main amplifier. Due
to this, the auxiliary amplifier must have a transconductance Gm,aux greater than the main amplifier
by a factor β given by (3.6). Bear in mind that transconductance Gm primarily applies to small signal
models, whereas this is a large signal amplification. Nonetheless, the transconductance referred to here
merely allows this text to discuss and compare the drain current-gate voltage relationship of the two
amplifier branches.
Gm,aux
(M − 1)Imain,pk Vin,P
β=
=
(3.6)
Gm,main
Vin,P − Vin,BO Imain,pk
The input back-off voltage Vin,BO can be written as a factor of Vin,P , where τBO is the proportion of the
input voltage swing for which the auxiliary remains below threshold.
Vin,BO = τBO Vin,P
(3.7)
Chapter 3. Design Considerations of a Doherty Amplifier
28
Using (3.7), (3.6) can be written as:
β=
M −1
1 − τBO
(3.8)
A typical scenario is M = 2 and τBO = 0.5 for 6 dB OBO, which yields β = 2. β required only increases
with greater back-off operation. This means the device used for the auxiliary amplifier should in theory
have twice as much gain as the main amplifier. This is obviously not achievable if the device used for
the main and auxiliary amplifiers are the same. There are a few approaches to mitigate this issue. The
first option is to sacrifice operation on either back-off operation or peak operation, meaning only one
of the twin peaks in efficiency as depicted in Fig. 2.12b will be prominent. This is done by using the
same device for the auxiliary as the main, biased at a lower voltage. Current supplied by the auxiliary
will not be enough to pull the load all the way from ZBO to ZP , however, one can find a compromise
between the operating points. This approach is called the Doherty Lite[18]. The approach of using the
same device for both main and auxiliary amplifiers is called a symmetrical DA.
Another method used to improve the gain of the auxiliary amplifier is to increase the gate bias voltage
dynamically when the amplifiers enters modulated operation. This is known as adaptive biasing. At a
system level, the transmitter is aware of the signal it wants to send to the PA. Therefore, it is not out of
the realm of possibility to have a processor that is able to generate a voltage signal that is proportional
to the RF envelope amplitude. Such a signal could be used to drive the bias voltage of the auxiliary to
momentarily improve the gain under modulated operation, i.e. when the auxiliary is active[18].
If however, an auxiliary device that has a suitable greater gain than the main device is available, then
utilizing such a device makes it an asymmetrical DA. Aptly named since the auxiliary and main do not
possess the same current carrying capabilities or transconductance parameters. The auxiliary device is
would be far stronger so that greater load modulation ranges than M = 2 can be achieved. Asymmetry
of DA, Ψ, can be described in a similar fashion to (3.3) with a small modification
Ψ=M :1
(3.9)
Here, a Ψ = 2 : 1 would describe a symmetrical DA utilizing an auxiliary with similar current supplying
capabilities as the main. Of course, a 2 : 1 ratio means β = 2, meaning the auxiliary needs twice as
much transconductance. But Ψ is a measure of current balance much like (3.3), where at peak operation
both devices supply equal current, hence the symmetry. Designing an asymmetrical DA comes with its
own set of challenges. The matching network used to match to the device’s optimum impedance will
be different across the main and auxiliary. Also, the phase delay acquired from input to output across
the two amplifiers will be significantly different. Phase compensation of sorts will then be required to
restore the balance. A symmetrical DA that has uneven power splitting at the input can also be used
to improve the gain along the auxiliary branch. By splitting the input signal unevenly and in favor of
the auxiliary amplifier, the auxiliary branch is driven harder in comparison to the main. This manifests
itself as increasing the slope of Iaux in Fig. 3.7. However, it will also decrease the input back-off voltage
Vin,BO , so this method requires some optimization.
29
Chapter 3. Design Considerations of a Doherty Amplifier
0.5
In
2nd Harmonic
3rd Harmonic
4th Harmonic
0.25
0
-0.25
0
0.5π
1π
1.5π
α
2π
Figure 3.8: Current harmonic components plotted against conduction angle α. Harmonics are normalized
to Imax = 1. Note the disappearance of the 3rd harmonic when α = π.
3.3
Harmonics
The non-linear device model introduced in section 2.1.1 contains regions of non-linearity in its characteristic curves. When the amplifier operates in these non-linear regions, how does non linearity manifest
itself in the output? The first and most obvious problem is when the device operates with a conduction
angle α < 2π. The portion of the conduction cycle for which the device remains below cutoff will be
clipped at the output. Clipped sinusoid waveforms contain harmonic distortion. A clipped waveform
can be deconstructed into its Fourier components, given by (2.3). For n ≥ 2, (2.3) evaluates the nth
harmonic of the output current:
In = 2
Imax sin n α2 cos α2 − n sin α2 cos n α2
π
n(n2 − 1) 1 − cos α2
(3.10)
The corresponding voltage waveform Vn is given by:
Vn = Zn In
(3.11)
By tuning the load impedance Zn at the nth harmonic frequency, one can control the power dissipated by
the device[19]. Known as harmonic tuning, this approach is almost always used in power amplifier design
so as to boost the efficiency by at least 5-10 %. At microwave frequencies, the higher order harmonics rise
in frequency rather drastically at which point they are nearing the device cutoff frequency. For example,
a microwave PA designed for 1.5 GHz will have a 2nd , 3rd , and 4th harmonic at 3 GHz, 4.5 GHz, and
6 GHz respectively. A GaN power device typically operates in the 10 GHz range, beyond which it may not
be able to produce sufficient gain. Moreover, beyond the 3rd harmonic, the components start to become
insignificant judging from Fig. 3.8. So essentially, the harmonic components that need to be addressed
are the 2nd and 3rd . And if the amplifier is operating in class B (α = π) or close to it, then according to
Fig. 3.8, the 3rd harmonic component will be 0 or very small. This makes suppressing the 2nd harmonic
of paramount importance. The main amplifier, which is realized using a class B or class AB amplifier
30
Chapter 3. Design Considerations of a Doherty Amplifier
Vd
L∞
C∞
Pin
L
Zm
C
Figure 3.9: A resonant parallel LC filter used to short out harmonic components in an ideal device.
The filter presents a short at every other frequency other than the fundamental. Zm is the modulated
load impedance seen at the fundamental frequency by the device. L∞ is an RF choke and C∞ is a DC
blocking capacitor.
Vd
L∞
C∞
λ/
4
Pin
Zm
Figure 3.10: The resonant LC tank is replaced with a short circuited shunted stub of length λ/4.
This stub shorts out the termination impedance of the device at the 2nd harmonic frequency. At the
fundamental frequency, the stub presents an open in parallel with the load Zm , leaving it untouched.
will not have much of a 3rd harmonic component, but the auxiliary amplifier will have this harmonic
component. But, since a significant amount of the total power is delivered by the main amplifier, the
3rd harmonic distortion of the complete amplifier should be relatively small. If the harmonic impedance
Z2 in (3.11) can be controlled, i.e. made short or open, then no power will be delivered to the load at
the 2nd . So, if there is no power delivered at this harmonic, then the DC power consumption as a result
of producing these harmonics will reduce. This directly causes a rise in efficiency of the amplifier.
Presenting Z2 to be a short or open doesn’t allow the device to transfer any power, real or reactive,
to the load. If Z2 was made to be to be purely imaginary, the reactive power transferred to the load
will return to the drain of the transistor where it will be dissipated due to losses in the device. So, the
most optimum way of suppressing power consumption due to harmonics is to have shorts or opens at
harmonic frequencies, particularly the 2nd . A short is more robust than an open because as soon as any
finite impedance appears in shunt with an open, it vanishes. Since all terminations are presented as a
shunt to the device, it is clear that only a short will be realizable. In an ideal scenario, a parallel resonant
LC tank can be used to short out harmonics as depicted in Fig. 3.9. However, also due to the resonant
31
Chapter 3. Design Considerations of a Doherty Amplifier
f1
j0.58Zo
λ/12
f3
Z
Figure 3.11: A λ/12 open circuited stub presents a short at the 3rd harmonic f3 , which is 3 times the
fundamental frequency f1 . At f1 , the impedance seen looking into the stub is ≈ j0.58Zo , where Zo is
the characteristic impedance of the stub.
filtering of the LC tank, the amplifier will not function outside the design frequency. When dealing at
lower frequency ranges as in a couple of MHz, it is easy to realize such a resonant LC tank. However,
at microwave frequencies, the component values become quickly unrealizable[13]. L and C values for a
resonant filter are given by:
L=
Q
1
and C =
Qωo
ωo
(3.12)
Here, ωo is the centre frequency and Q is a measure of the resonance of the filter. High Q implies a
highly resonant filter. The stop band has to lie at the 2nd harmonic, which is 2 times the fundamental
frequency that lies in the pass-band. Higher order filters typically roll off over a decade and do not have
pass bands and stop bands at such close proximity. A commonly used method to realize this filter is to
replace the resonant LC tank with a shunted stub. A short circuited shunted stub, SCSS, of physical
length λ/4 replaces the LC tank as in Fig. 3.10. The SCSS at the fundamental frequency presents an
open in parallel with the load termination Zm . Whereas at the 2nd harmonic frequency, it remains a
short now that the electrical length of the stub has doubled from 90◦ to 180◦ .
A similar method can be used to short out the 3rd harmonic. Here an open circuited shunted stub,
OCSS, of physical length λ/12 would do the task of presenting a short at the 3rd harmonic frequency
because at this frequency the stub’s electrical length is 90◦ . So, it transforms the OC to a SC at the 3rd
harmonic. However, at the fundamental frequency, it does not present a perfect open. It will present an
imaginary impedance ≈ j0.58Zo as shown in Fig. 3.11. When this impedance is presented in shunt with
the load termination Zm , it will de-tune the termination. So, some post tuning and or optimization will
be required to achieve optimum performance.
This approach of presenting a short at the drain works well when device parasitics and other nonlinear effects are insignificant. So, it works well when the operating frequencies are relatively low where
parasitics and other effects don’t affect the device performance too much. Things change however, at
microwave frequencies. Optimum impedances shift and skew, and the much needed shorts or opens at
harmonic frequencies will be de-tuned to a different value. Only load-pull will help find these de-tuned
impedances.
32
Chapter 3. Design Considerations of a Doherty Amplifier
C31
R31
Lg
Lg B
Rg
Rd
Ld B
Ld
G
D
+
R11
Vgs0
Cgs
−
C11
Cgd
∗
ZA
A
0
Ids (Vgs0 ,Vds
)
Ri
∗
ZA 0
ZA
0
ZA
+
R21
A0
0
Vds
Cds
−
C21
Rs
Ls
S
Figure 3.12: Circuit model for a GaN HEMT proposed in [1], complete with parasitic elements. Bond
wire inductances, pad capacitances, junction to junction resistances and capacitances are shown. Face
A0 is the access point of device’s drain terminal.
3.4
Parasitics
A typical device possesses parasitic components as depicted by Fig. 3.12, which is a small signal model
of a GaN HEMT. Methods to determine the parasitic element values in Fig. 3.12 are described in [20]. A
combination of load-pull measurements and device IV characterization are used to develop large signal
models as described by [21, 22]. So far along this text, optimum impedances and terminations were
discussed with the assumption that the device is an ideal non-linear device without any parasitics. Only
the dependent current source in Fig. 3.12 characterized by a look-up table is needed to describe such an
ideal model. Judging by schematic, it is obvious that the presence of these components will introduce
a skew in the optimum impedances and harmonic terminations. Characterizing the skew associated
with each parasitic element is beyond the scope of this thesis. However, it is beneficial to understand
approximately how the parasitics may skew the optimum impedances on a macro scale.
In Section 2.1.4 it was shown that ideal non-linear device impedances can be extracted based on drain
currents and voltages, and happen to be purely real based on load-line theory. This is because parasitic
behavior and other non-linear effects are not taken into account in such an analysis, but simply the DC
characteristics are studied to predict the behavior of device. It is obvious that the optimum impedance
will no longer be purely real impedance. The parasitic elements add an imaginary component to the
purely real optimum impedance at the drain pin. The effect of the output capacitance of the device on
its load line is shown in [9], p. 4, where it was shown that by accounting for parasitics, the trajectory
of the optimum load is no longer a straight lined slope on the drain current-voltage curves, but rather
follows an elliptical trajectory due to the added complex component by the parasitics. This can also
be understood with a simple thought experiment. At the interface A in Fig. 3.12, ZA is the optimum
∗
impedance and so ZA
is the impedance to match to for the network that follows. If no parasitics exist,
33
Chapter 3. Design Considerations of a Doherty Amplifier
Rd
Ld B
Ld
D
∗
ZA
ZA
A
R21
A
0
0
Vds
Cds
G
ZA0 ,opt
∗
ZA0
ZA
0
+
A0
←
A
−
ZA,opt
C21
Rs
0
A
Ls
←
A
∗
ZA
0 ,opt
Figure 3.13: Depiction of how load-pull contours shift when parasitics are accounted for. Drain and
source parasitics are shown, and the Smith chart depicts impedance shift going from face A to A0 .
Concentric contours on the Smith chart represent levels of degrading performance, with optimum performance in the centre. The blue impedance is the termination the device should see, where as the red
is its conjugate which will be used in designing the matching network. The red curves see an increase in
transmission length going from A → A0 due to the parasitics, so they shift in a clockwise fashion on the
Smith chart. Whereas, the blue curves being the conjugate of the red, shift counterclockwise.
∗
then at A, ZA would be purely real based on load-line theory and ZA = ZA
. However, when parasitics
are accounted for, the interface where terminating impedances will be presented to device will have
∗
∗
traversed to A0 . ZA
, now ZA
0 , has acquired an imaginary component due to the parasitic elements.
Consequently, so has ZA0 . ZA0 is found through load-pull done at A0 . Then a device matching network
will be used to match the device to a real impedance.
Let’s try to predict how the impedance ZA shifts with parasitics to ZA0 . In Fig. 3.13, the shift of the
optimum impedance contours are depicted. Let’s ignore the feedback parasitic elements for a moment,
i.e. the ones connecting the gate to the drain. So then, the remaining elements form a parasitic network
that sits between the drain output pad marked as A0 and the drain of the device A. Since the parasitic
network that sits between is a foster network, the conjugate impedance that is marked red, shifts in a
clockwise direction on the Smith chart. Note that the clockwise shift is merely a qualitative measure and
the curves do not shift in a perfect circle around the centre of the Smith chart. But, instead it will follow
a trajectory based on the parasitics of the device as a whole. Nonetheless, the conjugate impedance will
always move in a clockwise fashion. Therefore, the optimum termination impedances, marked blue in
Fig. 3.13, will move counterclockwise since it is its conjugate.
Why is this important? Because now, the optimum impedance is no longer a real valued impedance,
but it is a complex one. Therefore, there is a need to match the complex impedance to a real value
so that the methods described in Example 3.2.1 can be used to design the Doherty output network.
Also, while discussing bandwidth of PAs. The impedance presented by any passive foster matching
network will always deviate in a clockwise fashion with increasing frequency. Conversely, the optimum
impedances of the device, i.e. the termination that has to be presented to the device, shifts counterclockwise with increasing frequency. This is due to the increasing electrical length of the parasitic network
with increasing frequency, making the matching bandwidth worse.
34
Chapter 3. Design Considerations of a Doherty Amplifier
Zopt,PAE
PAE Contours
Zopt,Pdel
Power Delivered Contours
Figure 3.14: A load-pull characterization depicting power delivered contours, blue, and PAE contours,
red. The figure highlights how the optimum impedance may differ for the two metrics. In such a case,
a design compromise between the two points is made; shown by the yellow line.
3.5
Load-pull for Doherty
ZP and ZBO of the device have to be found through load-pull characterization. Now, load-pull can
be done both in the lab, or through harmonic balance simulations as described in [23]. Large signal
models of the device are generally provided by the vendor and encompass both large signal behaviour
and parasitics from Fig. 3.12. These models can be used with both Keysight’s Advanced Design System
(ADS) and National Instruments’ Microwave Office. Performing load-pull characterizations through
simulations is a much cheaper option. It also requires no test bench setup or calibration. However,
they may be slight discrepancies between the actual device and the model. Nonetheless, the accuracy of
simulations is sufficient for this study.
Finding the the device optimum impedances begins with presenting a load that is swept at the drain
terminal as described in Section 2.2. The result is contours of degrading optimum performance on the
Smith chart. In essence, the performance of the device is measured for every point on the Smith chart
and plotted on it. This gives the user an idea about where the optimum impedances lie under various
conditions. There are two conditions of interest.
• When the device delivers the maximum output power that the device is capable of producing; the
optimum impedance found here is ZP .
• The back-off condition where the device is X dB backed-off from the maximum output power, and
the optimum impedance found here is ZBO .
PBO,dBm = PP,dBm − X dB
(3.13)
When the sweep is performed, it is not a single optimum impedance point that is sought, but rather a
compromise to gain the best possible impedance to satisfy all the performance metrics. For example,
say the device can offer a maximum output power of 30 dBm. Now, to hit that power level, it may be
the case that efficiency will have to be sacrificed because the best efficiency and most power delivered
35
Chapter 3. Design Considerations of a Doherty Amplifier
ZBO contours
ZP contours
Ideal Device
Zo
Figure 3.15: Example load-pull contours shown for both peak and back-off conditions. ZP and ZBO
contours shift with parasitics. ZBO is a certain VSWR away that is greater than that of ZP , given that
ZP is close to Zo .
impedances slightly vary from each other as in Fig. 3.14. The reason for this slight difference can be
attributed to the device channel series resistance and the soft turn-on characteristic of any real device
[24]. Here, an impedance that lies on the yellow line may be chosen as a compromise between efficiency
and power delivered. This would be the optimum impedance to target while designing the amplifier.
Now, efficiency and power delivered are only two metrics shown here. There are two other performance
metrics, gain and gain compression, that can be swept for at the fundamental tone. With so many
metrics to optimize for, there isn’t a systematic approach but rather a criteria driven method to find the
optimum impedance. For example, say the gain required is 10 dB, then only the points that lie within
the 10 dB contour should be considered. The idea here is that the optimum point to be chosen is not a
single unique impedance, but is rather a choice based on the designer’s criteria.
Another load-pull is performed at the 2nd harmonic, to determine the load to optimize efficiency
of the amplifier. Because, from Section 3.3 and 3.4, it is known that the much needed 2nd harmonic
short is no longer a short due to parasitics, but rather a impedance to be sought. This is known as the
2nd harmonic load-pull. Sometimes, depending on the amplifier class, a 3rd harmonic load-pull may be
required. A class B amplifier or something close will only add marginal performance to a 3rd harmonic
optimization because the 3rd harmonic disappears for class B operation, refer to Fig. 3.8.
Now, these load-pull optimizations are performed at both peak power and back-off conditions. ZP
and ZBO will be sought after within the power delivered contours PP,dBm and PBO,dBm . For an ideal
device without parasitics, it is known that the two impedances are purely real and ZBO > ZP from
Section 2.1.4. So, choosing a Zo as close to ZP while performing load-pull, the VSWR of ZBO will be
greater than that of ZP . This is also true for a device with parasitics. Note that the Zo talked about in
this section is the characteristic impedance of the load-pull sweep. As long as a Zo is chosen reasonably
close to ZP , then the point ZBO will be a certain VSWR away from the centre of the Smith chart and
its VSWR will be greater than that of ZP . Ideally, ZP would have a VSWR of 1 : 1, i.e. ZP would lie
at the centre of the Smith chart. But since it is not known initially what ZP is and also it may be a
36
Chapter 3. Design Considerations of a Doherty Amplifier
Z
de
v
ZBO
ZP
Zm
0
ZBO
0
ZP
λ/4
MN
Zdev
G
Zm
Main
0
Figure 3.16: Matching the device optimum impedances ZBO and ZP to a real value ZBO
and ZP0 . The
main device, its matching network and the quarter wave transformer from the Doherty topology are
shown here. Modulated impedance Zm is transformed by the matching network to Zdev which hits
target optimum imepdances ZBO and ZP obtained from load-pull. Note that the black curved lines
simply represent mapping and do not represent the path taken to match the device.
complex impedance, load-pull is done a second time with ZP of the sweep brought as close to Zo as
possible without choosing a complex Zo .
Once the optimum impedances are found, it is time to match them to a real impedance. This has to
happen because the load modulation scheme described in earlier chapters modulates real impedances.
The impedance Zm from Fig. 3.2 only sees real quantities. So, the device matching network must match
0
ZBO and ZP to two new real impedances ZBO
and ZP0 so that Zm can be designed to hit these targets;
refer to Fig. 3.16. Here, the impedance seen by the device Zdev has to hit the optimum impedances
obtained from load-pull characterization. This is done through the use of a device matching network
0
that matches ZBO , a complex value, to ZBO
, a real value. It does the same with ZP and ZP0 . This type of
matching where a complex impedance is matched to a real value is widely known and well documented.
0
However, the difference here is that this has to be done for two impedance points ZBO → ZBO
and
ZP → ZP0 . The systematic approach of designing such a double matching network is a major highlight
of this thesis and is covered in the following chapters.
3.6
Output Impedance of the Amplifier
A big assumption was made when the Doherty topology was presented, and it was that the impedance
seen looking into the output of the auxiliary is an open circuit when it is turned off. Fig. 3.17 shows the
junction where the main amplifier branch, the auxiliary branch and the load branch appear in shunt.
37
Chapter 3. Design Considerations of a Doherty Amplifier
N
OM
50 Ω
λ/4
ZL
MN
Zdev
Main
Zm
0
Zm
Zout
MN
Aux
Figure 3.17: The common load point is a junction of three branches, where the main, the auxiliary and
the common load are all shunted together. ZL is the impedance of the common load presented by the
0
output matching network of the amplifier that matches it to the standard 50Ω. Zm
is the modulated
impedance and Zm is its inverted version, both these impedances are purely real. Zdev is the impedance
that is to hit both optimum impedances ZBO and ZP of the main device, it is a complex valued impedance
transformed from the purely real impedance Zm by the device matching network. Zout is the impedance
seen looking into a matched auxiliary amplifier.
0
0
The main branch impedance Zm
sees ZL in parallel with Zout at this junction. If Zm
has to see only
ZL under back-off operation where the auxiliary is turned off, then Zout should be an open or much
larger than ZL . If the auxiliary device wasn’t matched, then this would not be a problem up to a few
GHz. Unmatched devices possess an output impedance seen looking into the drain of the transistor
that mimics the behaviour of a capacitor, due to the drain to source capacitance of the device. This
capacitance is small and ranges between 1 to 5 pF. For frequencies up to 2 GHz, this parasitic capacitance
that appears in shunt with the drain of the transistor can be ignored and the impedance seen looking in
to the drain can be considered sufficiently large or open. However, since the device requires matching, a
matching network appears at the drain of the device. The device combined with the matching network is
now an amplifier, and the impedance seen looking into the output of the amplifier is governed primarily
by the passive elements that comprise the matching network. Since the matching network is comprised
of capacitors and inductors, which are passive and lossless, Zout as indicated in Fig. 3.17 will be purely
imaginary and will spread along the outer rim of the Smith chart as in Fig. 3.18. It spreads rather
rapidly around the Smith chart compared to when there was no matching network, because now there
are more passive elements connected to the drain of the device. If this impedance Zout appears in shunt
with the load ZL to the main branch, it is as if there is a stub that is shunted with the load. This
0
will de-tune the load impedance ZL that appears to Zm
during back-off operation, especially if |Zout |
is less than or comparable to ZL . In order to prevent this, at the fundamental frequency, Zout must
fall on open circuit as indicated by Fig. 3.18. This is done with the aid of a piece of transmission line
with characteristic impedance Zo = ZL that offsets the impedance seen at the fundamental frequency
Chapter 3. Design Considerations of a Doherty Amplifier
38
f1
Figure 3.18: Output impedance Zout of the auxiliary amplifier when turned off, spans around the
outer rim of the Smith chart due to the passive lossless components of the matching network. At the
fundamental frequency f1 , it must be an open circuit.
to an open. Because Zo = ZL for this line, the matching is unaffected and the line is therefore benign
in nature. All it accomplishes is that it adjusts the phase of ΓZout so that Zout is an open circuit at
the fundamental frequency. This is called an offset-line [11]. It is certainly not optimum to have an
offset-line in the Doherty because it causes Zout to spread even more with frequency, thereby narrowing
the bandwidth over which all the impedances are tuned to perfection. Nonetheless, it is required if the
device and matching network combination used for the auxiliary amplifier does not sport a large |Zout |.
Because this adds electrical length to the auxiliary branch, the current I2 supplied by the auxiliary will
no longer be in phase with the current from the main branch I1 at the common load. It will lag the I1
by the electrical length of the offset line, δ. Therefore, the lag must be compensated by delaying the
current I1 . This is accomplished by inserting a line of electrical length δ before the main device, i.e. at
its gate, so that the signal driving the main device is delayed by δ.
Chapter 4
Design of a GaN Doherty Amplifier
4.1
Design Overview
In this chapter, a Doherty Amplifier using GaN devices from CREE is designed with complete simulation
results. The topology is a simple symmetrical Doherty amplifier utilizing the methodology introduced
in Chapter 3. Simulations are run using the Agilent ADS software. The choice of using GaN RF power
device is a result of the conclusions drawn from section 3.1, namely the higher power density and higher
efficiency capabilities of GaN devices. The amplifier is designed for 1.5 GHz operating frequency, with
proper harmonic terminations, bias schemes, stabilizing networks, and realizable matching networks.
Harmonic balance method is used in ADS to simulate the device model, provided by CREE. Detailed
test bench setup of sweeps is outlined in this chapter.
4.2
10W CREE GaN RF Power Device
The device used to realize the main and auxiliary amplifiers is the CREE CGH40010F, whose package
is a flange type, useful for mounting purposes. Table 4.1 lists some of the capabilities of the device. Its
intended use is for class AB operation, used as the operating point of the main amplifier in the design.
The devices need not necessarily be used in the suggested bias class, but it is recommended in order to
achieve optimum performance out of the device. The peak output power of the device is rated for 10 W
or equivalently 40 dBm, which will be the peak operating power of the main. The total peak output
power of the Doherty will be slightly higher due to the contributions of the auxiliary amplifier. When
Peak Output Power
Supply Voltage
Frequency
Package Type
Small Signal Gain
Efficiency
Quiescent Current Iq
Typical Quiescent Gate Voltage
Source Impedance @ 1.5 GHz
10 W
28 V
DC to 6 GHz
Flange
16 dB @ 2 GHz, 14 dB @ 4 GHz
65% @ Saturated Power
200 mA
−2.5 V
7.37 Ω
Table 4.1: CREE CGH40010F 10W GaN HEMT notable operating parameters taken from data sheet
39
40
Chapter 4. Design of a GaN Doherty Amplifier
2
1.5
|∆|
K
1
0.5
0
0.5
1
1.5
2
2.5 3 3.5 4 4.5
Frequency (GHz)
5
5.5
6
Figure 4.1: K–∆ analysis of the CREE CGH40010 device under Vd = 28 V and Iq = 200 mA. Sparameter simulation from 500 MHz to 6 GHz shows K and ∆ plotted over frequency. The device is
potentially unstable for frequencies in the shaded region because K dips below 1 in that region.
the ideal non linear device model was first introduced, there was no limit on its drain supply voltage.
Meaning, if the supply voltage can be increased indefinitely, output power will also rise indefinitely. For
any realistic device, the drain supply voltage should have limits beyond which the device will breakdown.
Moreover, the vendor provides a rated supply voltage for the device that is recommended to prevent
such breakdowns. In this case, the supply voltage for the device is rated to be 28 V. The quiescent
current, Iq , is the bias current drawn under no input excitation, and this device is rated at 200 mA.
All S-parameter models provided by the vendor, which are used in stability analysis and differ from the
large signal model, are specified at rated Iq values. If the device is to be used with a different Iq , then
its S-parameters need to be measured at that Iq . So, for this design the main amplifier will operate at
rated Iq . The gate quiescent voltage is the voltage required at the gate terminal to draw the required
Iq at the drain, and this voltage varies with temperature and devices. Typically, this voltage should be
somewhere around -2.5 V, but is subject to variation. So therefore, the current being drawn at the drain
should be measured and the gate voltage should be adjusted so that Iq = 200 mA. Lastly, the source
impedance given is the impedance that the gate of the transistor should see in order to optimize input
power transfer. An input matching network is required to match the 50 Ω standard impedance from the
source to the termination specified in the data sheet, which happens to be approximately 7 Ω at 1.5 GHz.
4.3
Stability
The stability of the device is of concern, especially due to the wide operating range of the device, DC to
6 GHz. The way to ensure that the device is stable is to perform the stability analysis entailed in [14].
Here, the K–∆ test will help determine if the device is unconditionally stable. If not, then the device
has to be forced to be unconditionally stable. Otherwise, the device could oscillate if the termination
lies in a potentially unstable region of the Smith chart. The K–∆ test is given in [14], where the device
is unconditionally stable if it satisfies both conditions:
41
Chapter 4. Design of a GaN Doherty Amplifier
S-Parameter Model
10 pF
2
Iq =200 mA
1
Vd =28 V
Term 1
5Ω
Term 2
50 Ω
15 Ω
500 MHz – 6 GHz
Figure 4.2: A stabilization parallel RC network is added in series with the gate with R = 15 Ω and
C = 10 pF. The resistor adds loss to the transmission path, thereby decreasing the gain and making the
device unconditionally stable. The capacitor improves high frequency operation by providing a bypass
path.
K=
1 − |S11 |2 − |S22 |2 + |∆|2
>1
2|S12 S21 |
|∆| = |S11 S22 − S12 S21 | < 1
(4.1)
(4.2)
The S-parameters are those of the device characterized at its pins, port 1 being the gate and port 2
being the drain. The S-parameters are also bias point specific. Meaning they have to be characterized
for different bias conditions. The design in this chapter will use a main amplifier with device quiescent
bias current Iq of 200 mA and drain supply voltage Vd of 28 V. The small signal S-parameter model for
Iq = 200 mA and Vd = 28 V is provided by Cree. The model is split into two separate files, one for
frequencies from 0 → 500 MHz, and the other that covers 500 MHz+. The later model is simulated first
to ensure stability in the 500 MHz to 6 GHz frequency range. Since the optimum source termination is
known to be 7.37 Ω, a close approximation of 5 Ω is used as the terminal 1 impedance for the S-parameter
simulation in ADS. This terminal is connected to the gate pin or port 1 of the model file. The load
terminal or terminal 2 is of impedance 50 Ω, and is connected to the drain pin or port 2 of the model
file. K and ∆ are computed from the resulting simulation and plotted in Fig. 4.1. K dips below 1 in
the shaded region and the device is potentially unstable under this termination. A simple approach to
make the device unconditionally stable is to add loss in the transmission path. If the signal arriving at
the gate is attenuated, it will reduce the gain of the entire network. This is accomplished by introducing
a resistor in series with the transmission path just before the gate terminal. This resistor also kills the
gain for frequencies which are already unconditionally stable. So therefore, a bypass capacitor is added
in parallel with the resistor so as to improve the gain at higher frequencies. In this design, the concern
is primarily in the 0.5 to 2 GHz range, so it is not too important to include this bypass capacitor. It
does not affect the performance of the amplifier, because the design is not intended to be used in the
already unconditionally stable frequency range. Nonetheless, the capacitor is included for completeness
as in Fig. 4.2.
The result of adding the stabilization network is shown in Fig. 4.3. Where now K > 1 and ∆ < 1 for
most of the usable frequency range, deeming the device unconditionally stable over this range. It dips
42
Chapter 4. Design of a GaN Doherty Amplifier
|∆| after stabilization
K after stabilization
|∆|
K
2
1.5
1
0.5
0
0.5
1
1.5
2
2.5 3 3.5 4 4.5
Frequency (GHz)
5
5.5
6
Figure 4.3: The stabilization network causes the device to become unconditionally stable for most of the
usable frequency range, where K is now > 1. K and ∆ are plotted before and after stabilization. With
solid lines showing values after stabilization and dashed lines before stabilization.
slightly near the 0.5 GHz range, but further conditional stability analysis described in [14] is performed
to ensure that this potential instability is harmless. It was found that the potentially unstable regions
of the load at 0.5 GHz or below lies at the upper left rim of the Smith chart, far away from the load
termination presented at these frequencies. The load presented at these low frequencies is close to an
open due to the blocking capacitor. The open appears on the opposite end of the Smith chart to where
the potential instability lies.
4.4
Load-pull
Simulation test benches for performing load-pull characterizations are readily available through the ADS
software. The test bench of interest is the harmonic balance one-tone load-pull with power available
power sweep. One tone means there is a single excitation frequency by the source. This particular
setup sweeps the available power that excites the device model and performs a load-pull for each power
level. The desired output power can then be specified, and performance metrics extracted for those
levels. Output power at peak condition, PP,dBm , would be the maximum achievable by the device, which
happens to be 40 dBm. For back-off operation of 6 dB, the desired power PBO,dBm should normally be
taken at 3 dB less than the peak, or half the power. The reason for this is because the auxiliary amplifier
will ideally add to the output power by supplying 3 dB more, totaling an increase of 6 dB from the
back-off point. However, since we have a symmetrical device and the auxiliary is not going to be able to
match the main amplifier by supplying 40 dBm at peak operation, it will not add 3 dB increase to the
total output power. So therefore, the desired power at back-off, PBO,dBm , should be taken at 4 to 5 dB
less than the peak.
The CGH40010 large signal device model is provided by CREE for harmonic balance simulations.
Using the ADS test bench for HB load-pull, namely the one-tone load-pull with power sweep, the device’s
performance over the Smith chart can be studied. This particular test bench has a power sweep option
43
Chapter 4. Design of a GaN Doherty Amplifier
A
Vd =28 V
Vg =-2.7 V
A
L∞
Load Pull Tuner
C∞
10 pF
L∞
CGH40010
5Ω
C∞
15 Ω
Figure 4.4: The load-pull test bench used as used in ADS to obtain load-pull contours for the CREE
CGH40010. The device is stabilized, biased and terminated appropriately.
in its standard load-pull setup which is needed for designing the Doherty. The test bench sweeps the
input power of the device and is able to display the saturated power or maximum delivered power for
every point on the Smith chart, i.e. the maximum power that can be delivered to any load on the Smith
chart. it differs from a simple load-pull where the power delivered is shown for a single given input
power level. This is also true for gain and efficiency, in that the load-pull with power sweep gives the
maximum achievable quantity for every possible load. The device along with the stabilization network
is configured as in Fig. 4.4 for the load-pull simulation. The power available is swept from 0 dBm to
25 dBm at the source and the fundamental frequency of the harmonic balance simulation is 1.5 GHz.
The source impedance is given by the data sheet to be 7.37 Ω; a close approximation of 5 Ω is used as
the source impedance. This approximation is used because the given source impedance by the data
sheet is at a single frequency of 1.5 GHz, since the design is made for a wider frequency range it makes
little difference to be off slightly. The only factor affected by an improper source impedance match
is gain. A current probe that measures all the harmonic currents and a voltage probe that measures
all the harmonic voltages are inserted at the gate and drain supplies to measure the harmonic power
dissipated by the device. These measurements are used to compute the various metrics of the load-pull
analysis. The results of the load-pull simulation are given by Fig. 4.5. The contours of maximum power
delivered, maximum PAE, and gain compression at each point on the Smith chart are shown. It is
self explanatory what PAE and power delivered contours are, but gain compression on the other hand
is little more complex. The gain compression contours are of relevance and is only applicable to this
44
Chapter 4. Design of a GaN Doherty Amplifier
particular load-pull test bench with power sweep, because without sweeping power, the amount the gain
has compressed from its initial value cannot be computed. They present how far into compression the
device is operating, because each data point is a maximum performance characteristic, it is important
to know this. From this plot, the optimum impedances ZP and ZBO are chosen. The performance at
each impedance point is given in Table 4.2.
Impedance (Ω)
PAE (%)
Power Delivered (dBm)
Gain (dB)
Gain Compression (dB)
Bias Current (mA)
ZP = 20 + j20
57
39.7
14.6
3.3
581
ZBO = 15 + j45
59
35.7
10.7
5.7
217
Table 4.2: Performance metrics of the device at the two optimum impedances ZP and ZBO .
Now, the second harmonic termination must also be considered. By optimally terminating the second
harmonic, efficiency can be improved as mentioned in Section 3.3. The same test bench is used, except
now instead of sweeping the fundamental load, the load at the 2nd harmonic is swept while keeping the
fundamental load fixed at ZBO and ZP . The optimum second harmonic termination is highly sensitive to
drive strength, i.e. the optimum point moves with how much output power is obtained from the device
and also with frequency. So it is advisable to study the efficiency contours under both ZBO and ZP
fundamental termination as in Fig. 4.6. These contours show that the harmonic termination is more
sensitive for the back-off ZBO case in Fig. 4.6a than the peak ZP case in Fig. 4.6b. In the case of ZP ,
the efficiency only drops to about 50% anywhere on the Smith chart. Whereas for ZBO , the efficiency
drops below 40%, which is not desirable. So, when designing the matching network and the Doherty
amplifier, it is important to make sure the modulated impedance Zm falls in the optimum regions at the
fundamental and 2nd harmonic. It was shown that a SC is the harmonic termination to be presented
to an ideal device, but actual devices have optimal harmonic terminations that are shifted along the
outer rim of the Smith chart. These impedances are purely imaginary and so do not consume power
at the 2nd harmonic. The load-pull in Fig. 4.6 aids in determining the optimum imaginary impedance.
The termination does not necessarily have to be purely imaginary and lie on the outer rim of the Smith
chart, however, this would yield the most optimum performance. For example, during back-off, if the
2nd harmonic impedance is ZBO,2nd = j24 Ω as obtained from Fig. 4.6a, then PAE will see the most
improvement. But, a termination of 0.1 + j24 Ω will also yield good improvement as indicated by the
contours. So, it might be sufficient that the termination lies close to its optimum value.
In this text, the fundamental load-pull data was extracted by fixing the 2nd harmonic termination
to its optimum value of j24 Ω. Usually, the 2nd harmonic termination is only known after the optimum
fundamental load is fixed and a load-pull of the 2nd harmonic is performed. The process of finding the
two optimal terminations of the fundamental load and 2nd harmonic termination is dependent on each
other to a certain degree. However, a fundamental load-pull can be performed with an arbitrary 2nd
harmonic termination and the resultant plot can be studied to see where the optimum contours lie. The
location of these optimum contours don’t change much when the 2nd harmonic termination is updated,
only their values improve.
45
Chapter 4. Design of a GaN Doherty Amplifier
Zo : 50
Gain compression (dB)
1.
8
2
5
0.
ZBO
0.
4
5
0.
3
3
4.5
20 + j20
4
60
-0.1
10
5
4
3
2
1.8
1.6
1.4
3.5
37
36
2
-5
4.5
35
.3
-0
-4
-0.
38
1.2
39
0.8
0.7
45
40
0.6
0.5
0.4
0.3
0.2
0.1
50
1
0.1
4
55
0.9
ZP
5
0 .2
20
15 + j45
PAE (%)
1.6
6
0.
1.4
1.2
0.7
0.8
0.9
1
Power Delivered (dBm)
-3
.4
-0
-2
.8
-1
.6
-1
4
-1.
-1.2
-1
-0.9
-0 . 8
7
-0.
-0
.6
-0
.5
4
Figure 4.5: Harmonic balance one-tone load-pull of the CREE CGH40010 device model. Power is swept
and the maximum power delivered, maximum gain and gain compression is recorded by sweeping the
load across the Smith chart. ZP is chosen to be 20 + j20 Ω as a suitable compromise between the three
metrics. At about 4 dB away from ZP , ZBO is chosen optimally to be 15 + j45 Ω.
46
Chapter 4. Design of a GaN Doherty Amplifier
Zo : 50
2
1.
8
1.6
1.4
1.2
0.9
1
0.8
0.7
6
0.
5
0.
j24 Ω
60
55
0.
4
3
0.
3
50
4
0.2
45
5
20
10
4
5
3
1.6
1.8
2
1.4
1.2
0.9
1
0.8
40
0.7
0.6
0.4
0.5
0.3
0.2
0.1
0.1
-0.1
-0 .
2
-5
.3
-0
-4
-3
-2
.8
-1
.6
-1
4
-1.
-1.2
-1
-0.9
-0.8
-0.
7
-0
.6
-0
.5
.4
-0
(a) 2nd harmonic load-pull with Zfund = ZBO
Zo : 50
2
1.
8
1.6
1.4
1.2
0.9
1
0.8
0.7
6
0.
5
0.
0.
4
0.
3
3
60
4
0.2
5
50
20
10
5
4
3
1.8
2
1.6
1.4
1.2
0.9
1
0.8
0.7
0.6
0.5
0.3
0.4
55
0.2
0.1
0.1
-0.1
-0 .
2
-5
.3
-0
-4
-3
-2
.8
-1
.6
-1
4
-1.
-1.2
-1
-0.9
-0.8
7
-0.
-0
.
6
-0
.5
.4
-0
(b) 2nd harmonic load-pull with Zfund = ZP
Figure 4.6: 2nd harmonic load-pull contours showing PAE. The fundamental load is fixed and the 2nd
harmonic load is swept to plot these contours. (a) shows that when ZBO is presented and the amplifier
is operating at back-off condition, the 2nd harmonic termination must be close to j24 Ω for improved
efficiency. (b) shows that when ZP is presented at the peak operating condition, the termination required
is much more relaxed.
47
Chapter 4. Design of a GaN Doherty Amplifier
1.6
0.9
0.8
1.4
1.
8
0.7
1.2
-0
.6
.6
-1
.8
-1
6
0.
4
10
-0.
7
-1.
-0.8
-0.9
-1.2
-1
1
Zo : 30
28 + j0.3 Ω
(0.9 + j0.01)30
5
0.
-0
.
5
-2
2
5
.4
2.
4
-2
.4
-0
0.
4
2
-3
107 + j4 Ω
(3.6 − j0.14)30
3
.3
-0
0.
3
-4
4
1
-5
5
-0.
0 .2
2
0.5
-0.1
0.1
20
4
3
5
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.4
1.6
1.8
2
2.4
3
4
5
10
20
∗
ZBO
10
0
2.4
2
1.8
1.6
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
1.4
0.2
0
ZP∗
0.2
0.1
-0.1
0.5
ZP∗
2
0.2
-5
-0.
5
1
4
-4
0.
3
.3
-0
∗
ZBO
-3
3
2
0.
4
.8
-1
2
-2
-0
5
0.
.5
-2
2.
4
.4
.4
-0
4
-1.
-1.2
-1
-0.9
-0.8
-0.
.6
-1
-0
.6
7
1
0.9
1.2
0.8
1.4
0.7
1.6
10
6
0.
1.
8
5
15 − j45 Ω
(0.5 − j1.5)30
20 − j20 Ω
(0.67 − j0.67)30
[j0.26]jX
0
ZP∗
0
∗
ZBO
[−j0.68]jB
ZP∗
∗
ZBO
Figure 4.7: The optimum impedances obtained from Fig. 4.5, ZBO and ZP are matched to a real valued
∗
impedance. Matching network is first terminated with the conjugate of the optimum impedances, ZBO
and ZP∗ . The first component in the matching network is a series inductive element with reactance j0.26.
∗
and ZP∗ such that they have approximately the same susceptance. Next,
This component transforms ZBO
a shunt inductor with susceptance −j0.68 moves both impedances to the real line. The final transformed
0
∗0
real valued impedances ZBO
and ZP∗ are 107 − j4 Ω and 28 + j0.3 Ω respectively.
48
Chapter 4. Design of a GaN Doherty Amplifier
0
-10
0.82 nH
|Γ| (dB)
-20
28 Ω
107 Ω
-30
|ΓP |
|ΓBO |
4.6 nH
20 − j20 Ω
15 − j45 Ω
-40
|ΓP |
|ΓBO |
-50
-60
1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9
Frequency (GHz)
2
Figure 4.8: Reflection coefficient versus frequency of the matching network, which matches the two
∗
conjugate optimum loads ZBO
= 15−j5 Ω and ZP∗ = 20−j20 Ω to real values 107 Ω and 28 Ω respectively.
4.5
Double Impedance Matching Network
The device matching network can now be designed since ZBO and ZP are known. The goal of the
matching procedure is to bring both impedances onto the real axis. After which, the Doherty topology
can be designed. In order to see optimum impedances looking into the input port of the matching
network, given that the load port is terminated with appropriate real impedances, the matching network
∗
must be matched to the conjugate of the optimum impedances ZBO
and ZP∗ at the input port. So, the
first step in the design of the network is to terminate the input port with conjugate optimum impedances
as in Fig. 4.8. This input port can be thought of as the load port just for the matching part of the design,
this is where the device’s drain will connect. When matching, the impedance is transformed onto the
real axis as shown on the Smith chart in Fig. 4.8.
The procedure of transforming the two impedances to real values are as follows. It is known that
impedances that lie on the left side of the Smith chart translate aggressively by adding reactance, and
the ones that lie on the right side of the Smith chart translate more aggressively by adding susceptance.
This property will be leveraged. First, note the location of the impedances with relation to each other.
Then, the first element that is to be added will either change the reactance of the two impedances
such that their susceptances are equal, or it will change the susceptance of the two impedances such
that their reactances are equal. The second component will then cancel out the residual reactance or
susceptance. In Fig. 4.7 the first component is a inductive reactance of j0.26 Ω and the second is an
inductive susceptance of −j0.68 f that accomplishes this. These values at 1.5 GHz equate to component
values of 0.82 nH for the series inductor, and 4.6 nH for the shunt inductor. Note that when the matching
is done, the impedance or admittance always crosses down the lines of constant Q, meaning the imaginary
part relative to the real part is always decreasing. Thereby preserving the original Bode-Fano limit of
the impedance prior to matching.
If more stages were used in the matching, it would be possible to achieve a smaller distance between
0
0
∗
the two points ZBO
and ZP∗ on the real axis. However, when this matching network is fabricated, the
lumped components occupy physical length on the final board. It is desirable to reduce this for better
performance as it begins to manifest itself as transmission length, causing the impedance locus to spread
Chapter 4. Design of a GaN Doherty Amplifier
49
and shift from its desired value. A two stage L-matching network as designed here is optimum.
4.6
Transformer & Load
Now that the device is matched and stabilized, it is time to design the quarter wave transformer and load
impedance termination of the Doherty PA. (3.5) can be used to determine the characteristic impedance of
the transformer. This is a symmetrical Doherty PA without adaptive biasing, so the current I2 supplied
by the auxiliary will be approximately 0.5Imain at peak operation and 0 at back-off.
ZBO = 107 Ω
ZP = 28 Ω
Using (3.5), the characteristic impedance required can be computed:
Iaux
Imain
0
Zm,BO = 107 − Zo ·
= 107 Ω
Imain
0.5I1
Zm,P = 28 = 107 − Zo ·
Imain
107 − 28
= 158 Ω
⇒ Zo =
0.5
Zm = ZBO − Zo
These numbers seem a little odd since it reveals a Zo > ZBO . But this is the characteristic impedance
needed to completely cover the range if the auxiliary amplifier can only supply 0.5Imain at peak operation.
If suppose, it is assumed that the auxiliary amplifier is capable of supplying the needed amount of current
Iaux at peak operation, which is is given by (3.2) and (3.1):
M=
ZBO
107
≈ 3.8
=
ZP
28
Iaux = (M − 1)Imain = 2.8Imain
If Iaux can equal 2.8Imain , then the Zo required is equal to ZP . Of course, the auxiliary amplifier that
is being used is not capable of supplying such current, since it is of the same size and biased at a lower
voltage [25], but this choice simplifies design parameters. By choosing Zo = ZP , the design is limited to
either optimally designing for back-off operation, meaning hitting the impedance ZBO , or designing it for
peak operation and hitting ZP . Moreover it is difficult to achieve high impedance value of Zo = 158 Ω
on the board that will be later used to design the amplifier. The board is simply too thin and its
dielectric constant is too small to be able to achieve 150 Ω, and it will be clear as to why the design has
to fabricated on this board in Chapter 5. There is also one other motivating factor to make this design
choice. If Zo = ZP , the standing wave ratio will be 1 for ZP and 3.54 for ZBO . Whereas, choosing
Zo = 158 Ω the standing wave ratio is 5.67 for ZP and 1.4 for ZBO . It is desirable to have as little of
a mismatching as possible between the loads and Zo . So therefore, the Zo chosen here is 30 Ω which is
≈ ZP .
The load termination ZL determines which of the two operating conditions the amplifier is optimized
for. The choice of Zo has limited the design to only optimally design the amplifier for one of the two
50
Chapter 4. Design of a GaN Doherty Amplifier
A
Vd = 28 V
Vg = −2.7 V
A
L∞
C∞
0.82 nH
30 Ω · λ/4 · 1.5 GHz
10 pF
L∞
Power Splitter
← 10 Ω Taper 50 Ω →
4.6 nH
50 Ω
Main
CGH40010
C∞
15 Ω
A
Vd = 28 V
Vg = −4.2 V
L∞
A
5Ω
C∞
0.82 nH
10 pF
L∞
4.6 nH
5 Ω · λ/4 · 1.5 GHz
Auxiliary
CGH40010
C∞
15 Ω
Figure 4.9: Test bench used to simulate the Doherty amplifier is depicted. Matching networks, quarter
wave transformers, bias voltages, probe components, and the output taper are included.
conditions. Since it is harder to achieve back-off efficiency and it would be in the interest of this thesis
to show how the Doherty is designed for back-off efficiency, the amplifier designed here is chosen to be
optimized for back-off efficiency. Common load impedance is determined by (3.4):
ZL =
Zo2
302
= 8.4 Ω ≈ 10 Ω
=
ZBO
107
An approximation of 10 Ω is used because its load will have to be matched to 50 Ω in the output stage
using a tapered line or multi-section transformer as depicted in Fig. 4.9. Therefore, it is desirable not to
have too low of an impedance since the trace widths begin to become too large on the board.
51
Chapter 4. Design of a GaN Doherty Amplifier
Class AB @ 1.5 GHz, ZBO optimized
Class AB @ 1.5 GHz, ZP optimized
1.00 GHz
70
1.10 GHz
60
1.20 GHz
PAE (%)
50
1.30 GHz
1.40 GHz
40
1.50 GHz
30
1.60 GHz
1.70 GHz
20
1.80 GHz
10
1.90 GHz
0
2.00 GHz
10
15
20
25
30
35
Output Power (dBm)
40
45
(a) ADS simulation of PAE versus output power is shown. The different traces show the frequency degradation of efficiency
over the span of 1-2 GHz. The amplifier performs perfectly as a Doherty PA at 1.6 GHz. The solid and dashed black curves
show the efficiency performance of a class AB amplifier designed with the same device (CREE CGH40010), optimized for
peak power and back-off power respectively.
70
36 dBm
37 dBm
60
38 dBm
PAE (%)
50
39 dBm
40 dBm
40
41 dBm
30
42 dBm
20
10
0
1.00
1.20
1.40
1.60
Frequency (GHz)
1.80
2.00
(b) ADS simulation of PAE versus frequency. The traces show the various power levels. 36 dBm is the back-off power level
and 42 dBm is the peak power level. Around 1.6 GHz, both the back-off power level and the peak power level have over
50 % PAE.
Figure 4.10: Simulated performance of the designed Doherty PA showing PAE over frequency and output
power.
52
Chapter 4. Design of a GaN Doherty Amplifier
15
1.00 GHz
1.10 GHz
14
1.20 GHz
Gain (dB)
13
1.30 GHz
1.40 GHz
12
1.50 GHz
11
1.60 GHz
1.70 GHz
10
1.80 GHz
9
1.90 GHz
8
2.00 GHz
10
15
20
25
30
Output Power (dBm)
35
40
45
(a) ADS simulation of gain versus output power is plotted. The traces represent frequency sweeps. Note that the more
efficient operating power levels, i.e. 36 dBm and beyond, the gain compresses. This is because the device is most efficient
under gain compression.
4
1.00 GHz
1.10 GHz
Gain Compression (dB)
1.20 GHz
3
1.30 GHz
1.40 GHz
2
1.50 GHz
1.60 GHz
1.70 GHz
1
1.80 GHz
1.90 GHz
0
2.00 GHz
10
15
20
25
30
Output Power (dBm)
35
40
45
(b) ADS simulation of gain compression versus output power.
Figure 4.11: Simulation of (a) gain versus output power and (b) gain compression versus output power
of the designed Doherty PA
Chapter 4. Design of a GaN Doherty Amplifier
4.7
53
Simulation of the Design
The Doherty PA simulated in ADS and its performance metrics are extracted. PAE of the device is
plotted against output power in Fig. 4.10a, and then against frequency in Fig. 4.10b. Fig. 4.10a shows the
Doherty PA’s efficiency enhancement compared to a class AB amplifier designed with the same device.
The Doherty PA is able to not only achieve enhanced efficiency at peak output power, but also at the
back-off power. This is something that a typical class AB amplifier cannot achieve as evident by the
solid and dashed black efficiency curves, which are representative of the amplifier being optimized for
one of the two operating powers, but not both. Fig. 4.10b shows how the Doherty PA behaves with
frequency, as it displays the Doherty behaviour around 1.5 GHz to 1.8 GHz. In this range, the back-off
output power, 36 dBm, is delivered at a higher efficiency > 40 %. In the range 1.3 GHz to 1.5 GHz,
this efficiency drops below 40 %. This is quite strange since it was designed at a central frequency of
1.5 GHz. The reason for this sub par performance is described shortly after. The peak power output of
the amplifier should be 43 dBm, since the maximum achievable power output of the main device alone
is 40 dBm. However, from load-pull, it is known that the max output power at a load of ZP is 39.7 dBm
from Table 4.2. Add on top the fact that the auxiliary is incapable of supplying the same amount of
power, 39.7 dBm, at peak operation. The total power at peak operation does not increase by 3 dBm, but
somewhere between 1.5 to 2.5 dBm. Therefore the max output power caps off before 43 dBm, around
42 dBm. However, this can be overcome by driving the PA with a greater input drive strength. A preamp
stage might be required to achieve this. A preamp that is capable of supplying a maximum of 30 dBm
is used in the experimental setup in Chapter 5. Therefore, the plots in the following figures sweep the
available source power to a maximum of 30 dBm. Gain and gain compression plots are plotted against
output power in Fig. 4.11a and Fig. 4.11b respectively. The figures show that the gain compresses in the
power range where the amplifier is most efficient, i.e. 36 to 42 dBm. A pre-distortion stage can be used
to linearize the gain through the amplifier.
4.8
Bandwidth Analysis
In the context of this thesis, BW of a Doherty PA was defined as the fractional bandwidth for which
the back-off efficiency remains above a certain level. Now, if the minimum acceptable efficiency is 40 %
at back-off or 36 dBm, then the BW can be computed using the data from Fig. 4.10b. The method to
compute bandwidth is to find the two frequencies at which the back-off efficiency drops below 40 % and
divide it by the average of the two frequencies, i.e. the centre frequency:
f2,40% − f1,40%
f2,40% + f1,40%
1.79 − 1.51
=2
= 0.17 = 17 %
1.79 + 1.51
BWη:40% = 2
This design has a fractional BW of 17 %. But the question now is, why is this the case? What
causes such narrow bandwidth. It is believed that the quarter wave transformer is the most narrowband component in the architecture. A study of both the fundamental load-pull contours at the swept
fundamental frequencies and its corresponding harmonic contours reveals more about this efficiency
degradation. The impedance presented to the main amplifier is solely responsible for the efficiency
54
Chapter 4. Design of a GaN Doherty Amplifier
0.82 nH
30 Ω · λ/4 · 1.5 GHz
4.6 nH
Zm
← 10 Ω Taper 50 Ω →
50 Ω
0.82 nH
1.5 pF
4.6 nH
Figure 4.12: The impedance seen by the main amplifier at back-off is simulated by terminating the
auxiliary branch with an equivalent capacitor that models the drain source parasitic capacitance, Cds =
1.5 pF.
performance. This impedance can be simulated using the schematic in Fig. 4.12, where a 1.5 pF capacitor
models the drain source capacitance of the auxiliary amplifier when it is turned off. The back-off
operation scenario is modeled in this case. So, by knowing the impedance seen by the main amplifier
and imposing it on the load-pull contours, the efficiency BW behaviour can be understood.
The impedance Zm of Fig. 4.12 seen at the fundamental frequencies of 1-2 GHz and at their corresponding 2nd harmonic frequencies is plotted on the Smith charts of Fig. 4.13, Fig. 4.14, and Fig. 4.15.
There are two factors that determine the efficiency. First, where the fundamental load impedance falls
on the fundamental PAE contours determines the maximum achievable efficiency. Then, the point where
2nd harmonic load falls on the harmonic PAE contours determines the degradation from the maximum
achievable efficiency determined from the fundamental analysis. It was noted earlier that the back-off
efficiency degrades unexpectedly in the 1.3-1.5 GHz range although the amplifier was designed for a central frequency of 1.5 GHz. This can be explained. In Fig. 4.13, the fundamental impedance falls outside
the 30 % efficiency contours in the 1.0-1.2 GHz range, thereby rendering the maximum achievable efficiency less than 30 % in this range. At 1.3 GHz the fundamental impedance falls near the 50 % efficiency
contour, however, the harmonic impedance falls near the 35 % efficiency contour. This is the cause of
efficiency degradation at this frequency, i.e. sub-optimum 2nd harmonic termination. In fact, this is the
case up until 1.5 GHz where the harmonic termination enters the 40 %+ efficiency contours as seen in
Fig. 4.14. From 1.5 GHz up to 1.8 GHz, both the fundamental impedance and the harmonic termination
are in a reasonably optimum region on the efficiency contours. This is observed as the back-off efficiency
BW in Fig. 4.10a. Beyond 1.8 GHz, the harmonic termination enters the sub 40 % contours and eventually the fundamental load does as well, rendering the Doherty inefficient at back-off. Note that the
efficiencies plotted in Fig. 4.10 are 5-10 % less than marked values on the load-pull contours because the
load-pull contours only take into account the power consumed by the main amplifier, whereas the PAE
plots consider the power consumed by the whole Doherty PA which includes the auxiliary as well.
From this analysis, it can be concluded that the BW of a Doherty PA is subjective to the device being
used, the back-off efficiency required, and how much the 2nd harmonic termination matters. If suppose,
the 2nd harmonic optimization is ignored, the Doherty architecture can be judged solely based on the
Chapter 4. Design of a GaN Doherty Amplifier
55
fundamental load and contours. The goal of this thesis is to maximize the potential BW of a Doherty
PA before optimization. Because the 2nd harmonic optimization is subject to the type of device being
used, the matching network, and other parasitics that manifests itself as a result of high frequencies,
it is very difficult if not impossible to propose a universal efficiency enhancement scheme. Moreover, if
the main PA was biased more closely to class A, then a 3rd harmonic termination would be necessary.
Therefore, the design approach outlined in this chapter allows one to design a Doherty PA with maximal
BW benefits prior to harmonic termination optimization as evident by the fundamental termination in
the load-pull BW analysis. If the fundamental termination alone is taken into account, the impedance
stays within the 40 % efficiency contours approximately between 1.25 GHz and 2 GHz. This yields a
back-off fractional 40 % BW of
BWη:40% = 2
2 − 1.25
= 0.46 = 46 %
2 + 1.25
A whopping 46 % of fractional BW at 40 % back-off efficiency is potentially achievable. Of course this
number is a little optimistic and is subject to degradation when the power consumption of the auxiliary
is added. Also, there are potential differences between simulated load-pull contours and experimental
load-pull contours that may or may not affect this number. Nonetheless, the analysis and methods used
to design remain the same whether the load-pull is acquired from simulated data or experimental data.
Current research shows much more precise and tedious design approaches to yield the same potential
fractional BW as the simple approach shown in this thesis.
56
Chapter 4. Design of a GaN Doherty Amplifier
1.4
1.2
1.
8
2
5
2.
4
2.
4
50
f1 =1.1 GHz
3
50
20
4
25
45
0.2
0.2
35
-0.1
20
10
5
3
35
4
1.8
2
2.4
1.4
1.6
1.2
1
0.7
0.8
0.6
0.5
0.4
0.3
0.2
0.1
20
10
4
5
3
2.4
2
1.6
1.4
40
40
1.8
1.2
1
0.8
0.7
0.6
0.5
0.1
0.4
5
45
0.1
0.9
f2 =2.0 GHz
0.9
0.
4
0.
3
4
5
0.3
3
0.
3
f1 =1.0 GHz
0.
4
15
0.2
6.2+j27.7 Ω
0.
5
0.
2
5.0+j24.5 Ω
20
0.1
1
0.9
1.6
0.7
6
0.
1.6
1.
8
6
0.
0.8
1.2
Zo : 50
1.4
0.9
0.8
0.7
1
Zo : 50
f2 =2.2 GHz
-0.1
30
30
-0.2
-0.2
-5
30
-4
.3
-0
-3
.6
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0
-2
1.4
1.2
1
0.9
1.6
0.7
1.
8
2
2
1.
8
6
0.
1.6
6
0.
f1 =1.3 GHz
2.
4
2.
4
5
0.
f1 =1.2 GHz
5
0.
0.8
1.2
Zo : 50
1.4
0.9
0.8
0.7
1
Zo : 50
.8
-1
-0
.
-2
.8
-1
-0.7
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
25
.6
-1
.6
-0
.5
5
.4
-2
.4
-0
.4
-2
.4
-3
0.
4
7.8+j31.1 Ω
3
0.
3
4
25
50
4
5
5
45
0.2
0.2
40
35
-0.1
20
10
4
3
30
-0.2
50
-5
.4
.4
-0
-3
-2
.8
-1
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
.6
-0
-2
.8
-1
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
.6
-0
.5
.5
-2
-4
.4
-2
.3
-0
-3
.4
-4
40
-0
2.4
45
30
-0.2
.3
2
1.8
1.6
1.4
35
35
f2 =2.4 GHz
1.2
0.9
f2 =2.6 GHz 40
1
0.8
0.7
0.5
0.6
0.4
0.3
0.2
0.1
20
10
4
5
3
2.4
2
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
40
-5
0.1
0.1
0.1
30
-0.1
45
35
30
-0
10.0+j35.0 Ω
3
0.
3
0.
4
50
5
-0
-4
3
-5
.
-0
Figure 4.13: First of a three part figure depicting frequency degradation of amplifier efficiency using a
load-pull approach from 1 GHz to 1.4 GHz. Fundamental tone PAE contours are shown in white and
2nd harmonic PAE optimization contours are shown in red. The impedance seen by the main device at
the fundamental frequencies is shown by the blue trace. The corresponding 2nd harmonic impedance
is marked and the sweep is indicated by the green trace. The point where the fundamental impedance
falls on the fundamental PAE contours indicate the maximum achievable PAE for that specific operating
frequency. The point where the harmonic impedance falls on the harmonic PAE contours determines
the achieved PAE of the main device at that frequency.
57
Chapter 4. Design of a GaN Doherty Amplifier
1.2
1
0.9
1.6
1.
8
2.
4
5
0.
2.
4
55
13.2+j39.2 Ω
f1 =1.5 GHz
0.
3
0.2
0.2
40
60
0.1
35
20
10
4
5
3
2.4
2
1.2
1
0.9
0.7
0.8
0.6
0.5
0.4
0.3
0.2
0.1
20
10
5
4
2.4
1.6
55
3
2
1.6
1.8
1.4
1.2
1
0.9
0.8
0.7
0.6
0.4
0.5
5
f2 =3.0 GHz
0.1
40
0.3
4
45
1.4
0.
3
50
60
50
5
40
45
f2 =2.8 GHz
3
55
4
45
60
1.8
0.
4
3
0.2
17.9+j43.8 Ω
2
65
2
5
0.
60
0.
4
f1 =1.4 GHz
50
0.1
1.4
0.7
6
0.
1.6
1.
8
6
0.
0.8
1.2
Zo : 50
1.4
0.9
0.8
0.7
1
Zo : 50
45
55
-0.1
30
40
-0.1
50
-0.2
-0.2
-5
-5
-4
.3
-0
-3
-3
0.
4
-0.1
-2
.
-1
.6
-1.2
-1.4
-1
4
20
10
4
5
3
2.4
2
1.6
1.4
1.8
1.2
40
1
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
20
10
4
5
3
2.4
2
1.8
1.6
1.4
1.2
1
0.9
0.8
0.1
0.7
0.1
0.6
55
5
50
0.8
0.
3
0.2
0.5
60
0.2
0.4
1.2
1.6
0.
3
0.3
35.4+j51.2 Ω
3
f1 =1.7 GHz
50
45
45
40
0.2
1.4
65
f2 =3.4 GHz
5
55
0.1
1
0.9
0.8
2
2.
4
0.
4
4
50
70
55
3
f1 =1.6 GHz
55
f2 =3.2 GHz
24.9+j48.2 Ω
60
2.
4
65
70
5
0.
5
0.
2
60
1.
8
1.
8
6
0.
1.6
0.7
1.4
1.2
1
0.9
0.8
Zo : 50
6
0.
0.7
Zo : 50
-1
-0.9
-0.8
-0.7
-0
.6
8
-0
.5
-2
.8
-1
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
.6
-0
.5
-2
.4
-2
.4
-0
.4
.4
-0
-4
.3
-0
-0.1
50
45
-0.2
-5
-0
.5
.4
-2
-2
8
.
-1
.6
-1
-1.4
-1.2
-1
.8
-1
-0
.6
-0.9
.4
-1.4
-1.2
-1
-0.9
-0.8
-0.7
.6
-1
.6
-0
-2
.5
-0
45
-0.8
-3
-2
.4
-0
-0.7
-4
.4
-0
.3
-0
-3
.3
-0
-4
40
-5
-0.2
Figure 4.14: Second of a three part figure depicting frequency degradation of amplifier efficiency using a
load-pull approach from 1.5 GHz to 1.7 GHz. Fundamental tone PAE contours are shown in white and
2nd harmonic PAE optimization contours are shown in red. The impedance seen by the main device at
the fundamental frequencies is shown by the blue trace. The corresponding 2nd harmonic impedance
is marked and the sweep is indicated by the green trace. The point where the fundamental impedance
falls on the fundamental PAE contours indicate the maximum achievable PAE for that specific operating
frequency. The point where the harmonic impedance falls on the harmonic PAE contours determines
the achieved PAE of the main device at that frequency.
58
Chapter 4. Design of a GaN Doherty Amplifier
1.2
1
0.9
1.6
1.4
0.7
6
0.
2.
4
2.
4
5
0.
2
2
f2 =3.8 GHz
1.
8
1.6
1.
8
6
0.
f2 =3.6 GHz
45
70
60
49.8+j49.6 Ω
3
65
3
4
50
4
50
5
f1 =1.8 GHz
5
0.2
0.
4
0.
3
35
64.8+j38.6 Ω
0.
3
55
40
0.
4
5
0.
0.8
1.2
1.4
0.9
0.8
0.7
Zo : 50
1
Zo : 50
0.2
45
20
10
5
4
3
2.4
2
1.8
1.6
1.4
0.9
1
0.8
0.7
0.5
0.4
0.3
0.2
0.1
10
20
5
4
3
2
2.4
1.8
1.6
1.4
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.6
35
30
-0.1
1.2
0.1
0.1
45
f1 =1.9 GHz
40
40
-0.1
-0.2
-0.2
-5
-5
.3
-4
-3
-2
.
-1
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
.6
-0
.6
8
-0
.5
-2
.8
-1
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
.6
-0
.5
-2
.4
-2
.4
-0
.4
.4
-0
-3
-0
-4
.3
-0
1.4
2.
4
5
0.
2
1.
8
1.6
1.2
1
0.9
0.8
f2 =4.0 GHz
6
0.
0.7
Zo : 50
0.
4
3
0.
55
70.9+j18.4 Ω
4
3
50
5
0.2
45
0.1
40
20
10
5
4
3
2.4
2
1.8
1.6
1.4
1.2
35
1
0.9
0.8
f1 =2.0 GHz
0.7
0.6
0.5
0.4
0.3
0.2
0.1
35
-0.1
-0.2
-5
-4
.3
-0
-3
-2
-1
.6
-1
-1.4
-1.2
-1
-0.9
-0.8
-0.7
-0
.6
.8
-0
.5
.4
-2
.4
-0
Figure 4.15: Third of a three part figure depicting frequency degradation of amplifier efficiency using a
load-pull approach from 1.8 GHz to 2.0 GHz. Fundamental tone PAE contours are shown in white and
2nd harmonic PAE optimization contours are shown in red. The impedance seen by the main device at
the fundamental frequencies is shown by the blue trace. The corresponding 2nd harmonic impedance
is marked and the sweep is indicated by the green trace. The point where the fundamental impedance
falls on the fundamental PAE contours indicate the maximum achievable PAE for that specific operating
frequency. The point where the harmonic impedance falls on the harmonic PAE contours determines
the achieved PAE of the main device at that frequency.
Chapter 5
Fabrication & Measurements
In this chapter, the design introduced in Chapter 4 is fabricated and the performance of the amplifier
is characterized. How the various functional blocks within the amplifier are realized is highlighted.
Comparisons between simulated data and measured data are also made. The amplifier is tuned due to
practical considerations that need to be taken into account, thereby slightly modifying the matching
network introduced in 4.5. A complete layout of the final amplifier with component listing is given.
The choice of substrate is the ROGERS 3003, which is low loss with a loss tangent of 0.001 and a
dielectric constant of 3. This was chosen because it is desirable to have a lower dielectric constant. Since
transmission lines with small characteristic impedance have large trace widths, it is necessary to have
even longer lengths so that the widths of the traces aren’t comparable to their lengths. Having a lower
dielectric constant as the substrate helps maximize the required lengths of the traces.
5.1
Components
The amplifier schematic introduced in Fig. 4.9 is to be realized. In the schematic, little consideration
was given to the source and feed of the two devices. One, the source impedance seen by the devices is
approximately 5 Ω at 1.5 GHz, given by the data sheet. Two, the source signal must be split into the
main and auxiliary branch using a Wilkinson power divider. And three, the auxiliary feed branch must
be delayed by a quarter-wave transmission line. In Fig. 4.9, the impedance of the signal source was set to
be 5 Ω, so there was no need to change the impedance. However, actual signal sources have a standard
50 Ω impedance. There are two ways around this. One, the signal is split using a 50 Ω Wilkinson power
divider, auxiliary branch is delayed with a 50 Ω quarter-wave line and then matched to 5 Ω. Or two,
the impedance is matched to 5 Ω first, then the power divider and the quarter-wave line are in the 5 Ω
regime. The former of the two solutions is implemented because the transmission lines of characteristic
impedance 5 Ω have large trace widths. It would be desirable to minimize the use of these 5 Ω lines.
5.1.1
Broadband Wilkinson Power Divider & Input Delay
The amplifier is to be characterized over a frequency span of 1-2 GHz. This means an equal power
split has to be achieved over this range. For this purpose, a multistage Wilkinson power divider is
implemented as introduced in [26]. The divider has two stages, and has all three ports are matched to
50 Ω. The first stage has a characteristic impedance of 84 Ω and the second stage 59.4 Ω. The layout
59
60
Chapter 5. Fabrication & Measurements
DC blocking capacitor gap
50 Ω
Isolation resistor gaps
50 Ω
DC blocking capacitor gap
50 Ω
Figure 5.1: The layout of the multistage broadband Wilkinson power divider and the auxiliary branch’s
input delay line. The power splitter was adopted from the implementation introduced in [26]. The stages
are meandered so as to conserve space.
of the component is shown in Fig. 5.1. The component also includes the quarter-wave input delay line.
This achieves the phase shift required between the two ports. The input delay line must be realized with
a transmission line so as to mimic the phase shift produced by the quarter-wave line at the output end.
The two phases have to spread in unison with frequency, i.e. the phase of the input delay line and the
phase of the transformer in the output Doherty network, so as to maintain current phase balance at the
load. It is of paramount importance that the power splitter has good isolation between the two ports.
Since the gate of the device does not consume any substantial power, the signal will be reflected back.
If there were no isolation resistors placed, the reflected signal with one port will interfere with the input
signal going to the other port. This will lead to poor performance of the amplifier.
5.1.2
Source Matching Network
Now that the power is split into the two branches and a quarter-wave phasing is achieved between them,
it is time to match to the needed 5 Ω source impedance. Here, this is realized using a multi-section
binomial transformer, whose design methodology is well documented. It could also be done with a
Chebyshev or tapered transformer, just something that provides reasonable BW. The input match is
done in two sections. Using the binomial transformer design method, the characteristic impedance of
61
Chapter 5. Fabrication & Measurements
31.2 mm
29.8 mm
Stability Network Gap
Device Gate Pad
16.6 mm
Z2 = 28 Ω
4.2 mm
Z1 = 9 Ω
50 Ω
Figure 5.2: Layout of the source matching network that matches 50 Ω to 5 Ω using a two stage binomial
transformer. A pad is used to make contact with the gate of the device. This pad is separated from the
5 Ω end so as to allow the stability network components to be soldered in.
the two stages are determined by Table 5.1 in [14].
Zo = 50 Ω
ZL = 5 Ω
Z1 = 1.7783ZL ≈ 9 Ω
Z2 = 5.6233ZL ≈ 28 Ω
These impedances were then used to determine the trace widths using the Line Calc tool in ADS. Yielding
a 9 Ω line trace width of 16.6 mm and a 28 Ω line trace width of 4.2 mm. The layout of the input feed of
the device, which includes the source match and gaps for the stabilizing components are shown in Fig.
5.2. The reflection at the 50 Ω port is shown in Fig. 5.3. It was simulated using momentum in ADS.
5.1.3
Output Network
The output network of the Doherty PA comprises everything beyond the drain of the device. This
includes the matching network, the quarter-wave line, and the output taper. The layout of the output
network is shown in Fig. 5.4a. The matching network used here is slightly different from the one used in
-5
-10
|Γ| (dB)
-15
-20
-25
-30
1
1.1
1.2
1.3
1.4
1.5
1.6
Frequency (GHz)
1.7
1.8
1.9
2
Figure 5.3: The reflection seen at the 50 Ω port of the source matching network. The reflection remains
below 10 dB for nearly the entire fundamental frequency range.
62
Chapter 5. Fabrication & Measurements
50 Ω
Series Component Gap
Main Drain Pad
Choke Inductor Gaps
Vias to Ground
Ground
Supply Voltage Pad
Shunt Component Gap
Aux Drain Pad
(a) Layout of the output network of the Doherty PA. The main and auxiliary device’s drain pads are shown with neighboring
pads and gaps. The drain pads are followed by pads allocated for the matching network. Between the two lies the quarterwave transformer with characteristic impedance 30 Ω. The common load point is where the meandered output taper
connects with the quarter-wave transformer and the matched auxiliary device. The output taper tapers from a width of
11.9 mm to a final width of 1.9 mm. This matches 10 Ω to 50 Ω.
4.8 pF
30 Ω · λ/4 · 1.5 GHz
← 10 Ω Taper 50 Ω →
6 nH
Main
50 Ω
4.8 pF
Aux
6 nH
(b) Schematic of the proposed Doherty output network. The matching network shown here are designed here are a result
of tuning as outlined in the subsequent work. The series capacitor also functions as a DC block, it is placed in the series
component gap of layout in (a). Likewise, the shunt inductor is placed in the allocated shunt component gap.
Figure 5.4: (a) Layout, and (b) schematic of the output network of the Doherty PA.
63
Chapter 5. Fabrication & Measurements
Component
L1
L2
C1
C2
C3
R0
R1
R2
Function
RF Choke Ind
Matching Network
Ind
DC Blocking Cap
Stability Network
Cap
Matching Network
Cap
Short/Jumper
Power Divider
Isolation Res
Stability Network
Res
Value/Rating
130 nH
Manufacturer
Murata
Part #
LQW2BANR13G00L
6 nH
CoilCraft
0603HP-6N0X-LU
39 pF, 50 V
Murata
GRM1885C1H390JA01D
10 pF, 100 V
AVX
06031A100JAT2A
0 Ω, 0.1 W
Johanson
Tech.
Yageo
200 Ω, 0.1 W
Yageo
RC0603JR-07200RL
15 Ω, 0.5 W
Vishay Dale
RCL061215R0FKEA
2.4 pF, 200 V
201R07S2R4BV4T
RC0603JR-070RL
Table 5.1: List of lumped component parts used in the Doherty PA of Fig. 5.6a.
the simulated design in Chapter 4. This is due to the tuning that is required when fabricating. The drain
pads and matching network occupy physical length on the board, whereas in simulation this is not the
case. To characterize this length or delay, a replica of the output network was fabricated. An arbitrary
matching network was inserted in the signal path and the three port output network was characterized
using a VNA. The three ports being the drain pad, the auxiliary pad and the 50 Ω termination end.
The S-parameters of this network were then compared to the S-parameters of an equivalent simulated
network, where the components of the matching network and the drain pads do not possess physical
length. VNAs possess a port extension utility that allows the user to extend a port by a fixed electrical
length. This was used to sweep the electrical length extension at the main device’s drain port till the
S-parameters acquired from measurement lined up with those from simulation. The amount of port
extension needed to have simulation line up with measurements is the delay caused by the pads and the
dimensions of the components. In the case of this output network, the delay was characterized to be 30◦
at 1.5 GHz on a 50 Ω Smith chart. So therefore, the optimum impedances have to be translated by 30◦
and then matched. This is depicted in Fig. 5.5. The resulting matching network is different from the
one used in 4.5. However, the resulting final impedances are similar for both cases. Note that the series
capacitor in the new network also functions as a DC blocking capacitor for biasing, thereby serving a
dual purpose. The series capacitor and shunt inductor values can then be computed:
1
= 4.8 pF
0.44 · 2π · 1.5 · 50 · 109
50
L=
= 3.8 nH
1.4 · 2π · 1.5 · 109
C=
In Section 4.8 it was found that the PAE performance is not solely affected by the fundamental
termination impedance alone, but also the second harmonic impedance. Through iterative process,
taking into account the BW degradation shown in 4.8, the matching network designed here was further
tuned to optimize the second harmonic termination at 1.5 GHz. The final matching network has a
slightly higher shunt inductance of 6 nH, while the series capacitor remains at the same value of 4.8 pF.
64
Chapter 5. Fabrication & Measurements
1.6
0.9
0.8
1.4
1.
8
0.7
1.2
-0
.6
.6
-1
.8
-1
6
0.
10
-0.7
-1.4
-0.8
-0.9
-1.2
-1
1
Zo : 50
36.2 − j1.7 Ω
(0.72 − j0.036)50
5
0.
-0
.
5
-2
2
5
4
2.
4
.
-2
.4
-0
0.
4
2
-3
142 + j2 Ω
(2.84 − j0.04)50
3
.3
-0
0.
3
-4
4
1
-5
5
-0.2
0.2
0.5
-0.1
0.1
20
10
5
4
3
2.4
∗
ZBO
2
1.8
1.6
1.2
1.4
0
1
0.8
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.4
1.6
1.8
2
2.4
3
5
4
10
20
ZP∗
0.2
0.1
-0.1
0.5
0.2
-5
ZP∗
-0.2
1
5
4
-4
0.
3
.3
-0
3
-3
2
.4
-0
0.
4
-2
.4
15 − j45 Ω
(0.3 − j0.9)50
-1.4
-1.2
-0.8
-0.9
-1
1
0.9
1.2
0.8
1.4
10
.6
-1
0.7
1.6
-0.7
-0
.6
1.
8
5
6
0.
.8
-1
2
-2
-0
5
0.
.5
2.
4
∗
ZBO
20 − j20 Ω
(0.4 − j0.4)50
[−j0.44]jX
0
ZP∗
[−j1.4]jB
0
∗
ZBO
λ/6 · 1.5 GHz
ZP∗
∗
ZBO
Figure 5.5: Tuning of the matching network accounting for pad delay and component dimensions. The
delay was characterized to be 30◦ at 1.5 GHz, which equates to a λ/6 section of a transmission line.
The characterization was done at 50 Ω, so the line used to model this delay has the same characteristic
impedance. This shifts the optimum impedance termination and the matching network used to match
the resultant impedance is depicted. This differs from the matching network introduced in 4.5, indicated
by the dashed lines.
5.2
Layout & List of Parts
The layout of the Doherty PA along with the components in place is shown in Fig. 5.6a. A close up of
the lumped components is depicted in Fig. 5.7. The list of lumped components parts used is shown in
Table 5.1. The RF choke and DC block are realized using inductors and capacitors operating at their
self-resonant frequencies (SRF) respectively. The parasitic capacitance associated with the inductor
makes it a parallel resonator at the resonant frequency, thereby causing the impedance to shoot to high
value over that frequency range. This frequency range is the SRF. The inductor can be used as a choke
to block of RF power from leaking into the power supply. In the design, L1 is a 130 nH used for this
purpose. Its component value is not high enough to be used as a choke, but since its SRF is in the 1 GHz
range, it functions as a choke. Similarly, the parasitic pad inductance associated with a capacitor makes
it a series resonator at the resonant frequency, essentially making it a short over that frequency range. A
capacitor can be used as a DC block if the RF frequency happens in the SRF range. The 39 pF capacitor
65
Chapter 5. Fabrication & Measurements
C2
C3
C3
R2
C1
L2
L1 L1
L1 L1
R0
L1
R1 R1
R1
L1
R0
L1 L1
L1 L1
C2
L2
C3
C1
C3
R2
(a) Layout of the complete Doherty PA drawn to scale.
A
Vd = 28 V
Vg = −2.7 V
A
L∞
4.8 pF
30 Ω · λ/4 · 1.5 GHz
10 pF
Power Splitter
L∞
C∞
← 50 Ω
Binomial
6 nH
← 10 Ω Taper 50 Ω →
50 Ω
Main
CGH40010
5Ω →
15 Ω
A
Vd = 28 V
Vg = −4.2 V
L∞
A
50 Ω
4.8 pF
10 pF
C∞
L∞
5 Ω · λ/4 · 1.5 GHz
← 50 Ω
Binomial
6 nH
Auxiliary
5Ω →
CGH40010
15 Ω
(b) Schematic of the designed Doherty PA, whose layout is shown in (a).
Figure 5.6: The layout (a) of the complete fabricated Doherty PA along with all the components and
its corresponding schematic (b).
66
Chapter 5. Fabrication & Measurements
C2
C3
C3
R2
L2
L1 L1
L1 L1
R0
L1
L1 L1
L1
C2
L2
C1
C3
R2
R1 R1
C3
R0
L1 L1
R1
Figure 5.7: Close-up of the lumped components used in the Doherty PA
Chapter 5. Fabrication & Measurements
67
Figure 5.8: A photograph showing the top view of the fabricated Doherty PA. Power supply capacitors
are also soldered into the supply bank so as to filter out any parasitic signal that may originate from the
DC source.
Chapter 5. Fabrication & Measurements
68
Figure 5.9: Photograph showing the Doherty PA mounted onto a heat-sink. The devices are clamped
down with another heat-sink to ensure the ground flange makes contact with the ground plane. The
board is held down using clamps.
69
Chapter 5. Fabrication & Measurements
GPIB controller
RF Power Meter
-10dB
Signal Generator
Pre-Amp
Isolator
Coupler
Multimeter
IDC
Power Supply
IDC
DUT
Attenuator
Spectrum Analyzer
Figure 5.10: The Automated test bench setup for measuring the performance of the Doherty PA across
frequency and power.
C1 is used as a DC block in the design. The power supply pads are also placed in close proximity to a
ground. This is done to allow for the placement of power supply capacitors so current does not rush into
the components when the supply is turned on or off. It also shorts any interference or stray signal that
may originate from the supplies. The list of capacitors used to achieve this is not included in the parts
list here, they can be found in the CREE CGH40010 data sheet under the demo board parts listing.
Only the elements crucial to the function of the Doherty PA are mentioned in this thesis. The isolation
resistors needed according to [26] are 100 Ω for the first stage, and 184 Ω for the second stage. A close
200 Ω resistor was used for the second stage in this design. This first stage is realized using two 200 Ω
resistors in parallel.
5.3
Measurement Setup
Due to restrictions in budget, experimental load-pull was not performed on the device. The costs
associated with experimental load-pull involve equipment and training expenses. The only experiment
performed was to characterize the PA for gain, efficiency, and harmonic distortion over frequency and
power and this was done with a single experimental setup that is discussed below. One of the primary
interests of this work is to study the BW of a Doherty PA, so other experiments such as IP3 and ACPR
(Adjacent Channel Power Ratio) were not performed in this work. Another reason for abandoning these
experiments was again due to the costs associated with the experimental setup.
The Doherty PA is to be characterized over a span of 1 GHz and over 30 dBm of power sweep for
each every frequency step. If the frequency were incremented by 100 MHz and the power was swept from
0-30 dBm in 1 dBm increments, the data matrix would have 300 entries. To get an even finer resolution
on the sweep, the number grows even more. Also, that is for a single metric, i.e. output power or current
consumption. Multiply the number of entries by the number of metrics needed and the task is tedious
to be performed by hand. Therefore, there is a need to automate the measurements. The measurements
performed here were automated using a GPIB controller that sequenced the test equipment. The test
equipment used are as follows:
• Signal Generator (Agilent E8257D)- Provides the signal source to be used as input. Sweeps fre-
Chapter 5. Fabrication & Measurements
70
quency from 1-2 GHz. Required to sweep power over required pre-amp input power levels. GPIB
controllable.
• Pre-amplifier (Minicircuits 15542)- Maximum output power of 30 dBm. Necessary stage to amplify
signal coming from the signal generator in order to push the DUT into saturation.
• Multimeter (HP 3478A)- Used as an ammeter to probe the current being supplied to the Doherty
PA. This probes the supply current to the drain of both the main and auxiliary amplifier. Since
the two drains have the same supply voltage of 28 V, the same supply can be used to power both
devices in parallel. This will help characterize the power consumed by the DUT.
• RF Power Meter (Agilent E4418B)- This meter is used to probe the power out of the pre-amp,
which is the available source power to the DUT. This information is useful in measuring the gain
of the DUT.
• Spectrum Analyzer (HP 8563E)- The spectrum analyzer is used to characterize the output of
the DUT. It measures the power delivered at the fundamental frequency, the second and third
harmonic.
• 10 dB Coupler (Narda 4226-10)- Used to tap into the output power of the pre-amp. The RF power
meter is connected to the coupled port to measure this power.
• 40 dB Attenuator 50 W (Fairview Microwave SA18SFSF)- Attenuates the output of the amplifier
by a fixed 40 dB before feeding it to the Spectrum Analyzer. This is needed to prevent damage to
the Spectrum Analyzer which does not handle power levels over 30 dBm.
• Isolator 1-2 GHz 10 W (Fairview Microwave SFI1020)- Connects to the output of the pre-amp
before the coupler. The preamp does not tolerate loads greater than a certain VSWR. If the load
it sees is not within this VSWR, it may damage the pre-amp. The isolator is used to isolate the
termination of the preamp from the impedance seen at input of the DUT.
There are five quantities to be measured in this setup, namely the DC current consumption, the
output power at the fundamental, second and third harmonic, and finally the available source power.
Using this information, one can compute gain, PAE, harmonic distortion and gain compression across
frequency and power level. The procedure to measure the five quantities is as follows:
• Before performing measurement, sweep the pre-amp alone across power and frequency without the
DUT in the schematic. Record the necessary signal generator power level to achieve 30 dBm out
of the pre-amp. This was measured to be 0 dBm of power from the signal generator.
• Bias the devices properly, and ensure the DUT is functioning.
• Set signal generator output frequency to 1 GHz and output power to sweep from -30 dBm to 0 dBm
in increments of 1 dBm.
• Record the reading from the RF Power meter. This reading is 10 dB less than the available source
power going into the DUT or equivalently the power coming from the pre-amp.
• Record the DC current reading on the multimeter. This is the current consumed by the DUT. The
power supply is set to 28 V. Therefore, the DC power consumed can be computed.
Chapter 5. Fabrication & Measurements
71
• Record the power of the fundamental tone at the spectrum analyzer. Repeat for the second and
third harmonic. This reading should be 40 dB less than the actual output of the DUT due to the
attenuator.
• Increment the signal generator power by 1 dBm and repeat the measurements. Once the signal generator has reached 0 dBm, reset the power level to -30 dBm, increment the frequency by 0.01 GHz,
and repeat all measurements.
5.4
Measurement Results
Data acquired from the experiment is then used to compute the performance of the Doherty PA. The
extracted parameters from the characterization are DC current consumption Idc , fundamental P1 , second
P2 and third P3 harmonic power delivered, and available source power Pavs . Gain G and drain efficiency
η can be computed:
G = P1,dBm − Pavs,dBm
η=
P1,W
VDC IDC
Note that the gain computed here is the gain through the entire PA and not just the gain through the
transducer. The transducer gain does not account for the fraction of available source power that does
not make it through to the input due to reflections. Therefore, the transducer gain will always be greater
than the entire PA gain. Similarly, computing PAE requires the power that makes it to the input of the
device. Since only the available source power is obtained from the measurement, if PAE was computed
using Pavs , it would yield a slightly lower PAE than if it were computed using the actual input power. For
this reason, the drain efficiency η is computed since it does not require input power in its calculation. η
computed from measurements is depicted in Fig. 5.11, where it is plotted against output power delivered.
The back-off efficiency point, 36 dBm, is plotted against frequency in Fig. 5.12 and compared to simulated
data. The back-off point is considered to be 36 dBm because at best the main amplifier is able to output
39 dBm of power according to Fig. 4.5, so technically the +3 dB power added by the auxiliary amplifier
must be equal to a peak power of 42 dBm. Something to make note of is that the auxiliary amplifier isn’t
capable of supplying this +3 dB due to it being a symmetrical amplifier, for the reasons explained in
Section 3.2.2. Therefore the back-off will suffer in this amplifier, or more so the peak power will not be as
high as 42 dBm, unless the amplifier is operated well into gain compression. The back-off point and peak
power are subject to the strength of the auxiliary amplifier as explained in Chapter 3. The scope of this
work is to show the systematic implementation of the Doherty concept, so the same device was used for
both the main and auxiliary amplifiers so as to simplify the design process with a symmetrical Doherty
PA. In Fig. 5.12, the co-simulation data and full-simulation data correlate quite well. Co-simulation is
where the output network with the lumped components, the quarter wave transformer and the taper
are characterized using a VNA and the resulting S-Parameters are used in simulation with the device
model to extract performance. Whereas in full simulation, there is no physical device or measurement
and everything is simulated using ADS and MoM solvers. The experimental measurements show inferior
BW performance to that of either co-simulation or full simulation. This degradation can be attributed to
its sensitivity to the pad delay. To show how sensitive the amplifier is to the pad delay, the transmission
72
Chapter 5. Fabrication & Measurements
60
1.30 GHz
Drain Efficiency η (%)
50
1.35 GHz
40
1.40 GHz
30
1.45 GHz
20
1.50 GHz
1.55 GHz
10
1.60 GHz
0
−5
0
5
10
15
20
25
30
35
40
45
Output Power (dBm)
Figure 5.11: Measured DE of the DUT plotted against power delivered. The various traces represent
frequency sweeps. At 36 dBm or back-off, efficiency is elevated around 1.4 GHz demonstrating Doherty
behaviour. DE is computed from the multimeter readings of DC current consumption and from the
spectrum analyzer readings of power delivered at the fundamental tone.
50
Measured
Co-simulation
Full-simulation
De-tuned simulation
Drain Efficiency η (%)
40
30
20
10
0
1.3
1.4
1.5
Frequency (GHz)
1.6
1.7
Figure 5.12: The back-off drain efficiency at 36 dBm of the Doherty PA is plotted against frequency to
show the back-off efficiency BW. Measured data acquired from the test setup is shown. Co-simulation
data, is a combination of simulation and measurements. Here the S-parameters of the output network
are characterized using a VNA, then the device model is simulated using the characterized data. Fullsimulation data is obtained purely through ADS simulations. The output taper and quarter wave
transformer here were extracted for S-parameter using a MoM solver and then simulated with the rest
of the PA. De-tuned simulation data is obtained by adjusting the parasitic pad delay which was modeled
by a transmission line from 30◦ to 10◦ . The De-tuned simulation data and Measured data have similar
efficiency performance with a slight shift in frequency which may be attributed to the distributed nature
of the actual pad delay compared to the simulated pad delay. This was done to show how sensitive the
performance is to the pad delay.
73
Chapter 5. Fabrication & Measurements
45
35
Fundamental
25
15
5
Output Power (dBm)
-5
-15
-25
-35
2nd Harmonic
3rd Harmonic
-45
-55
-65
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
-75
GHz
GHz
GHz
GHz
GHz
GHz
GHz
GHz
GHz
-85
5
10
15
20
25
Available Source Power (dBm)
30
35
Figure 5.13: Measured 2nd and 3rd harmonics are shown along with the fundamental output power
delivered over a frequency span of 1.3 GHz to 1.7 GHz. The harmonics are about 30 dB less than the
fundamental tone.
74
Chapter 5. Fabrication & Measurements
52
OIP3 (dBm)
51
50
49
48
1.4
1.45
1.5
Frequency (GHz)
1.55
1.6
Figure 5.14: Output-referred third order intercept point (OIP3) was determined using a two-tone simulation in ADS and is plotted against frequency. The inter-modulation was simulated over frequency
and power, and the mean of the power data points is plotted here versus frequency. The spacing used
between the two tones is 100 KHz. Ths simulation was a co-simulation where the output network used to
terminate the devices was fabricated separately and its S-parameters were characterized using a VNA.
line modeling the pad delay was adjusted from the expected 30◦ to 10◦ . The result of this simulation
is shown in Fig. 5.12 as the de-tuned simulation data. The efficiency BW performance of the De-tuned
simulation data now coincides with the measured data with a slight shift in frequency. This means that
the parasitic delay of pad and component physical length was overcompensated in the design. One more
iteration of the design process by remodeling the parasitic delay with a 10◦ will help achieve a closer
match between the prototype and simulation. Post-tuning such as this is often required in PA design to
achieve better performance.
There are potentially other less significant reasons lead to such degraded BW performance. One, the
device model slightly differs from the actual device. Two, the way the device makes contact with the
pads was not optimized. These pads can be more precisely designed such that it allows the device to
see the output termination properly. When the output network alone was characterized using the VNA,
it was fabricated with 50 Ω launching traces. The effects of these traces were then removed using port
extension. Such a technique cannot be used to launch the output from the drain of the device. The drain
pad must be optimized and precisely designed. Finally, equipment and test setup used is not tailored
to perform high power PA characterizations. The setup used here was put together to approximately
measure the performance of the Doherty PA and to show evidence for the design methodology entailed in
this thesis. More specifically, the output of the PA can be measured more precisely by power calibrating
the spectrum analyzer and also minimizing the stages needed between the output of the PA and the
spectrum analyzer. Moreover, just the overall mounting of the device can be improved by screwing it
down to the ground and heat sink. This was not done in the setup, instead the device was fastened
down using a clip. The isolation of the power divider also plays a role in the performance. Using an off
the shelf power divider with good isolation would help. If all these details are covered, a more closer
match between measurements and simulation can be expected. Harmonic distortion is depicted in Fig.
5.13. The measurements show that they are about 35 dB less than the fundamental output power,
or equivalently -35 dBc. To provide a basis for comparison, a similar PA with output power of 10 W
Chapter 5. Fabrication & Measurements
75
and operating in the 1-2 GHz range sold by EMPOWER RF SYSTEMS (Part #: BBM4A5AAJ), has a
harmonic distortion of -20 dBc. The two-tone co-simulation of output-referred third order intercept point
(OIP3) was obtained using ADS and is also shown to display the inter-modulation distortion. There is
good correlation between the measured third harmonic and the OIP3. The co-simulated OIP3 is about
50 dBm, comparable to the PA offered by EMPOWER at 53 dBm. For reasons due to budget and time,
the two-tone simulation was only performed in co-simulation. In the co-simulation, the output network
of the Doherty PA was fabricated alone and characterized using a VNA. This characterized S-parameter
block was then used to simulate the Doherty PA in ADS to obtain the OIP3 data.
Chapter 6
Bandwidth of an Inverter
Load inversion happens when the phase between the driving point impedance and the load impedance
happens to be 90◦ . The network that exists between these points is responsible for such an inversion.
It was clear that such an inversion is necessary for the operation of a Doherty PA. A quarter-wave
transmission line achieves this at a particular central frequency, i.e. quarter the wavelength of the wave
excited by the central frequencies. Now if the frequency of interest changes, the length is no longer
quarter wave length and therefore the load inversion degrades as well. Is there a network that can
maintain 90◦ of phase between the driving point impedance and the load impedance over all frequency.
If not, what is slowest degradation from 90◦ that is achievable? To shed some light on this question, the
S21 transfer function of an inverter needs to be examined. First, let’s examine the S21 transfer function
of a quarter-wave line and then draw comparisons.
6.1
The Quarter-Wave Transmission Line
The ABCD matrix of transmission line is given as:
"
cos θ
jZo sin θ
jYo sin θ
cos θ
#
The S21 transfer function can be extracted from this given by:
2
A+
+ CZo + D
2
=
= e−jθ
cos θ + j sin θ + j sin θ + cos θ
S21 =
B
Zo
∠S21 = −θ
(6.1)
(6.2)
The transfer function S21 of a transmission line is an all pass transfer function, meaning its magnitude
is 1 over all frequency. Its phase, θ adds electrical delay between the driving point and the load. So
therefore, there are two conditions that need to be satisfied, i.e. the magnitude of S21 has to be 1 and its
phase must be 90◦ at the central frequency for load inversion. Ideally, both the magnitude and phase
76
77
Chapter 6. Bandwidth of an Inverter
will remain at 1 and 90◦ respectively over all frequency for infinite inversion BW, but this is not possible
and it will soon be apparent why. First let’s take a look at the derivative with respect to frequency of
the phase of S21 . This gives a measure of the departure of the phase from its value at that frequency.
d∠S21
dθ
d
=−
=−
dω
dω
dω
dθ
lo
θ
→
=
=
dω
co
ω
ωlo
co
=−
lo
co
(6.3)
Here, co is the speed of light in that medium, a fixed quantity, and so is lo , the length of the line.
Therefore, the phase of any transmission line always degrades at a constant rate since its derivative is a
constant. It can also be written differently from lo /co , so this constant value is more apparent.
θ = βlo
(6.4)
Here, lo is the length of the line given by a desired fixed phase θo at a desired fixed spatial frequency βo
and consequently fixed wavelength λo .
θo
θo λo
=
βo
2π
(6.5)
2π θo λo
λo
θo λ o
=
= θo
2π
λ 2π
λ
(6.6)
f
fo
(6.7)
lo =
Substituting (6.5) → (6.4),
θ=β
Since λ = c/f , (6.6) can be written as
θ = θo
From (6.3),
dθ
θ
θo f
θo
= =
=
dω
ω
ωfo
ωo
(6.8)
That is, the group delay of a transmission line is fully described by the desired electrical length of the line
at the desired central frequency. If the central frequency is normalized, i.e. ωo = 1, then the derivative
of the phase of a transmission line is equal to its central frequency’s phase value, θo . From this point
in the text, the central frequency will be normalized to 1, in order to make it easier to compare the
derivative of the phase of various networks at the central frequency. Therefore, the group delay of a
simple quarter-wave transmission line is simply π/2.
6.2
Group Delay Contributions of Poles
Since the aim of the whole discussion is to compute the measure of departure of the phase from its value
at central frequency, the question is whether this can be computed given the location of poles. The
answer is yes. Measure of departure of phase with frequency, also known as group delay has a direct
impact on the BW of an inverter. The larger the frequency range over which an inverter is able to
maintain 90◦ of phase, the larger the inversion BW. Therefore, the ideal scenario would be that this 90◦
of phase is maintained over all frequencies. And in this case, the group delay would be 0 because the
phase never changes with frequency. This is obviously not possible and therefore the next best option
is to have the smallest possible group delay at the frequency of interest. To study the group delay of
78
Chapter 6. Bandwidth of an Inverter
jω
h sin dθ
dω
h0
dθ
ω
h
θ
={p} = yp
σ
<{p} = xp
Figure 6.1: The figure aims to establish the geometry involved when the frequency changes by dω from
ω. The corresponding change in phase is dθ from θ. The length of the hypotenuse subtended changes
from h to h0 .
an arbitrary two-port network, the most generic method of analysis would be to quantify how a single
pole affects the group delay. That is, how the placement of a single pole contributes to group delay. An
expression for a measure of the group delay can be computed using the location of poles. Fig. 6.1 depicts
the geometry of the analysis, where the group delay due to a single pole is shown.
From the small right triangle in the figure,
h sin dθ
= cos (θ + dθ)
dω
Using the small angle approximation, sin dθ ≈ dθ
hdθ
= cos (θ + dθ)
dω
dθ
cos (θ + dθ)
=
dω
h
cos (θ + dθ) =
xp
h0
(6.9)
(6.10)
Substituting (6.10) into (6.9):
dθ
xp
xp
= 0 =q
dω
hh
(ω + dω − yp )2 + x2p · (ω − yp )2 + x2p
(6.11)
In the limit that dω → 0, (6.11) simplifies to
dθ
xp
=
dω
(ω − yp )2 + x2p
(6.12)
Yielding an expression for the group delay given by the real and imaginary parts, xp and yp , of the pole
79
Chapter 6. Bandwidth of an Inverter
p. The total group delay is simply a summation of the contributions of every pole of S21 . Note that
the group delay will always be negative for a system of poles restricted to the left half plane. As ω
grows, the total phase subtended becomes more negative. This is because the angle subtended by each
pole appears in the denominator of S21 and grows bigger. This also makes intuitive sense because a
simple passive network, one with poles on the left half plane, becomes electrically longer with increasing
frequency. The expression for total group delay is then:
N
X
d
<{pn }
∠S21 =
dω
(ω − ={pn })2 + <{pn }2
n=0
6.3
(6.13)
π, T, and n-Stage Ladder Networks
A transmission line can be modeled by ladder network of infinitesimal series inductors and shunt capacitors. The purpose of this section is to see the evolution of pole placement as the number of stages
is increased, starting with a simple π network. As the number of stages are increased, the group delay
should converge to the group delay of transmission line (6.8). So, let’s take a look at a simple π or T
network that achieves a π/2 phase in its S21 . The design equations for such a network are given below,
they are similar to (3.12), where Q = 1/Zo :
1
Zo
, C=
ωo
Z o ωo
L=
(6.14)
These component values in a π or T network will achieve a ±π/2 phase shift with |S21 | = 1 at a frequency
of ωo . It will be matched to a characteristic impedance of Zo .
The ABCD of a series element is given with Z being the impedance of the component:
Mz =
"
1
Z
0
1
#
(6.15)
And a shunt component with Y being the admittance of the component:
My =
"
1
0
Y
1
#
(6.16)
So then, a the ABCD of a Π network can be computed by cascading the components in shunt-series-shunt
order:
My Mz My =
"
#"
1
1
0
Y
1
0
Z
1
#"
1
0
Y
1
#
=
"
#"
1 + ZY
1
0
Y
1
Y
Z
1
#
=
"
1 + ZY
Z
2Y + ZY 2
1 + ZY
#
(6.17)
Now, the denominator of S21 is A + B/Zo + CZo + D given by (6.1). By solving for the poles of S21 ,
the phase and phase derivative can be computed as it will be shown later. The poles can be solved by
finding the roots of the denominator. By inspection, the denominator of S21 is simply the summation of
all the elements of the ABCD matrix of any network with a slight modification. The modification being
that B is divided by Zo and C is multiplied by Zo . Let’s perform this transform directly on the ABCD
matrix so the terms of the denominator can be taken directly from the modified matrix. Let’s denote
80
Chapter 6. Bandwidth of an Inverter
jω
j
1
σ
−j
√
Figure 6.2: The poles of S21 of the low pass Π network are shown in blue, located at −1 and −0.5 ± j 27 .
√
The poles of S21 of the high pass Π network are shown in red, located at −1 and −0.25 ± j 47 . Note
that the high pass network also has three zeroes at the origin not shown here.
this transform with the symbol Ψ{}:
Ψ
("
A
B
C
D
#)
=
"
A
B
Zo
CZo
D
#
(6.18)
So then if the Ψ transform is applied to (6.17):
Ψ
("
1 + ZY
Z
2Y + ZY 2
1 + ZY
#)
=
"
1 + ZY
Z
Zo
2Y Zo + Zo ZY 2
1 + ZY
#
(6.19)
Now Z is allowed to either be an inductor, sL or a capacitor, 1/sC. Likewise Y is either sC or 1/sL.
√
In either case, the central frequency of the Π network is given to be ωo = 1/ LC, and the impedance
p
to match at that frequency to be Zo = L/C. Note that when the series branch is an inductor, the
shunt branch is a capacitor and vice-versa. If this was not true, then there is no longer a π/2 phase shift
at ωo . So ZY is either s2 LC for the low pass configuration (series L, shunt C) or 1/s2 LC for the high
pass configuration (series C, shunt L). Let’s first look at the low pass configuration and then extend the
p
analysis to the high pass configuration. Substituting Zo = L/C, Z = sL and Y = sC into (6.19):

1 + s2 LC

q
q
L
L 3
2sC C
+ C
s LC 2

"
√
1 + (s LC)2
=
√
√
2s LC + (s LC)3
1 + s2 LC
√sL
L/C
#
√
s LC
√
1 + (s LC)2
(6.20)
81
Chapter 6. Bandwidth of an Inverter
jω
-32.85◦
j
45◦
1
σ
77.85◦ −j
Figure 6.3: Phase contributions of each pole in the low pass Π network is shown. The angle subtended
between a horizontal line and the line that connects the pole with the point s = j is the phase contribution
of that pole. These are indicated by the dashed lines. The sum of all subtended angles equate to 90◦ .
Because these are poles, and happen to occur in the denominator of S21 , the total phase contribution is
actually negative, i.e. -90◦ .
For the high pass configuration, it can be easily proven that the powers of (6.20) are simply negative:
"
√
1 + (s LC)−2
√
√
2(s LC)−1 + (s LC)−3
#
√
(s LC)−1
√
1 + (s LC)−2
(6.21)
√
√
Let’s normalize the central frequency to 1, i.e. ωo = 1/ LC = 1 or equivalently LC = 1. S21 can then
be easily constructed from (6.1), by summing up all the elements of (6.20) and (6.21):
2
2
= 3
2(1 + s2 ) + 3s + s3
s + 2s2 + 3s + 2
2s3
2s3
=
= 3
3
2
2(s + s) + 3s + 1
2s + 3s2 + 2s + 1
S21,LP =
S21,HP
(6.22)
(6.23)
The poles of the two configurations are depicted in Fig. 6.2. Point j on the imaginary axis is the central
frequency of the network, i.e. s = jωo = j. The angle subtended between the real axis and the line that
connects a pole to this point j is the phase contribution of that pole at the central frequency. To make
this clear, Fig. 6.3 depicts this. Here, the negative of all the angles subtended are summed to compute
the phase of S21 at the central frequency. Negative because the phase contributions of the poles are in
the denominator of S21 . This can also be expressed mathematically, where pn is the nth pole of S21 , zm
82
Chapter 6. Bandwidth of an Inverter
is the mth zero, N and M are the total number of poles and zeroes respectively:
∠S21 =
M
X
ω − ={zm }
<{zm }
−1
tan
m=0
!
−
N
X
ω − ={pn }
<{pn }
−1
tan
n=0
!
(6.24)
The same analysis or expression can be used to compute the phase of S21 at ω = ωo = 1 for the high
pass network. Doing so reveals that the zeroes of the high pass network contribute 270◦ , and the poles
contribute -180◦ , resulting in a total phase of 90◦ at the central frequency. Note that |S21 | = 1 at ω = 1.
It is trivial to compute the magnitude contributions of the poles and zeroes of the transfer function.
Graphically, it is simply the product of the length of the lines connecting the singularities to the point
ω = 1 or s = j:
M
Q
|S21 | = 2 m=0
N
Q
n=0
|jω − zm |
(6.25)
|jω − pn |
Using (6.13), the group delay of the Π networks can be computed. The group delay of the low pass and
high pass configurations at ω = 1 are:
−1
d
∠S21,LP −
=
2 + 12
dω
(1
−
0)
(1 +
ω=1
d
−1
∠S21,HP =
−
dω
(1 − 0)2 + 12
(1 +
ω=1
√
0.5
7 2
2 )
√
+
0.52
−
0.25
7 2
4 )
+ 0.252
0.5
(1 −
−
√
7 2
2 )
(1 −
√
+ 0.52
= −2
0.25
7 2
4 )
+ 0.252
= −2
It is greater than that of a simple quarter-wave transmission line whose group delay is -π/2. This is
expected, the next question is whether a ladder network can achieve a smaller group delay. A ladder
network with equally distributed components achieving a certain phase delay going from port 1 to 2
can be thought of as a model for a transmission line. Therefore, as the number of stages in the ladder
increases, one can expect the behaviour of the resulting network to approach that of the transmission
line. That is, its group delay will be the same as that of a transmission line whose phase delay is
equivalent to that of the network in question.
Let’s put this to the test by computing the poles of a multistage Π network. It will be seen that as
the number of stages increases the resulting orientation of poles form a network who’s S21 behaviour
approaches that of a transmission line. Let’s first begin with a 2 stage Π network. This means we have
an additional stage of My Mz matrices multiplied to the single stage Π network ABCD matrix:
My Mz My Mz My =
=
=
"
"
"
1
0
Y
1
#"
1
0
1
Z
Y
1 + ZY
Z
#"
1 + ZY
Z
1 2Y + ZY 2
#"
1 + ZY
2Y + ZY 2
1 + ZY
#
Z
#
1 + ZY
1 + 3ZY + (ZY )2
2Z + Z 2 Y
3Y + 4ZY 2 + Z 2 Y 3
1 + 3ZY + (ZY )2
#
Let’s apply the Ψ transform. It can be noted that this transform has the effect of bumping down the
powers of Z by 0.5 and increasing the powers of Y by 0.5 in the B element, and vice-versa in the C
83
Chapter 6. Bandwidth of an Inverter
element:
Ψ
("

1 + 3ZY + (ZY )2
2Z + Z 2 Y
3Y + 4ZY 2 + Z 2 Y 3
1 + 3ZY + (ZY )2
= q
√
√
1 + 3(s LC)2 + (s LC)4
L
C (3sC
+ 4s3 LC 2 + s5 L2 C 3 )
"
√
√
1 + 3(s LC)2 + (s LC)4
√
√
√
=
3s LC + 4(s LC)3 + (s LC)5
=
"
#)

+ s3 L2 C)

√
√
1 + 3(s LC)2 + (s LC)4
q
C
L (2sL
#
√
√
2s LC + (s LC)3
√
√
1 + 3(s LC)2 + (s LC)4
√
√
√
1 ( ZY )0 + 3 ( ZY )2 + 1 ( ZY )4
√
√
√
3 ZY + 4 ( ZY )3 + 1 ( ZY )5
#
√
√
2 ZY + 1 ( ZY )3
√
√
√
1 ( ZY )0 + 3 ( ZY )2 + 1 ( ZY )4
This is for a low pass 2 stage Π network. The significance of highlighting the coefficients will be apparent
soon. The same algebra can be repeated for a 3 stage Π network by multiplying another stage of My Mz
to the 2 stage ABCD matrix. The in between steps are not shown below.
(
Ψ My Mz
("
=Ψ
Let
√
"
1 + 3ZY + (ZY )2
2Z + Z 2 Y
3Y + 4ZY 2 + Z 2 Y 3
1 + 3ZY + (ZY )2
1
Z
Y
1 + ZY
#"
#)
1 + 3ZY + (ZY )2
2Z + Z 2 Y
3Y + 4ZY 2 + Z 2 Y 3
1 + 3ZY + (ZY )2
#)
ZY = a, then:
=
"
1 a0 + 6 a2 + 5 a4 + 1 a6
3 a + 4 a3 + 1 a5
4 a + 10 a3 + 6 a5 + 1 a7
1 a0 + 6 a2 + 5 a4 + 1 a6
#
Similarly, for a 4 stage Π network:
"
1 a0 + 10 a2 + 15 a4 + 7 a6 + 1 a8
4 a + 10 a3 + 6 a5 + 1 a7
5 a + 20 a3 + 21 a5 + 8 a7 + 1 a9
1 a0 + 10 a2 + 15 a4 + 7 a6 + 1 a8
#
The highlighted coefficients appear on the shallow diagonals of Pascal’s triangle as shown in Fig. 6.4,
where the coefficients in the Ψ-transformed ABCD matrix of a 1, 2, 3 and 4-stage Π networks appear. This pattern can be used to predict the Ψ-transformed matrices for higher number of stages, and
consequently its S21 transfer function.
84
Chapter 6. Bandwidth of an Inverter
1
1
1
1
1
1
1
1
2
3
1
1
3
1
1
1
1
2
3
4
5
1
3
6
10
1
4
10
1
5
1
1
1
1
1
1
1
1
1
3
5
7
2
4
6
1
3
6
10
15
21
1
1
4
10
20
35
1
5
15
35
1
6
21
1
7
1
1
1
1
1
1
1
1
1
1
1
8
9
10
35
1
5
15
35
70
126
1
4
20
56
84
3
10
21
1
6
15
28
36
3
5
7
2
4
6
1
6
21
56
126
1
1
7
28
84
1
8
36
1
9
1
Figure 6.4: Coefficients of 1, 2, 3 and 4-stage Π networks appear on the shallow diagonals of Pascal’s
triangle. The yellow coefficients belong to the A and D elements of the Ψ-transformed ABCD matrix.
The orange coefficients belong to the B element. And finally, the green coefficients belong to the C
element. The denominator of S21 is simply obtained by summing the ABCD elements. The coefficients
then add up according to their respective orders. Since A and D have the same set of coefficients
repeated, the corresponding coefficient is simply multiplied by 2. B and C have different coefficients, so
the coefficients of corresponding order have to be summed, marked by the dashed lines.
85
Chapter 6. Bandwidth of an Inverter
The transfer function of an n-stage Π network is given by:
S21 =

n
P 2
k=0  2
√
2(n−k)
2n−k
ZY
k
√
2(n−k)
2n−k
ZY
k
+
+
2
√
2(n−k)+1 2n+1−k
+ 2n−k
ZY
k
k−1
√
2(n−k)+1 2n+1−k
ZY
k
(6.26)
if k > 0
if k = 0
n∈ [1, 2, 3, 4, ..., N ]
There is but one more detail that is missing. That is, if the number of stages is increased, then the
component values Z and Y have to be scaled by a factor, let’s call it φ. To make this argument clear,
starting with a 1-stage Π network, let’s say the series and shunt component values Z and Y produce an
electrical delay of 90◦ at the central frequency. Now, if another shunt and series of Y and Z stage is
added to that 1-stage Π network, now making it a 2-stage Π network, the electrical delay at the central
frequency becomes greater than 90◦ . Therefore, the components Z and Y have to be scaled in order
to re-establish 90◦ at the central frequency. Through numerical iteration, it was found that this scaling
factor φ is given by
φ=1+
(n − 1)
θo
(6.27)
where θo is the desired phase in radians at the central frequency. So then Z and Y in (6.26) scale to the
value Z/φ and Y /φ. That is, component values L and C scale by either φ or 1/φ depending on whether
the configuration is low pass or high pass. (6.26) then becomes:
S21 =

n
P 2
k=0  2
2n−k
√
ZY 2(n−k)
k
φ
√ZY
2n−k
k
φ
2(n−k)
+
+
2
2n+1−k
√ZY
+ 2n−k
k
k−1
φ
√ZY 2(n−k)+1 2n+1−k
k
φ
2(n−k)+1 (6.28)
if k > 0
if k = 0
n∈ [1, 2, 3, 4, ..., N ]
The resulting S21 transfer function can be solved for zeroes and poles. The low pass configuration
will have no zeroes. The poles of up to 4 stages are shown in Fig. 6.5, for both the low pass and high pass
configurations. These placements of poles produce -90◦ delay at the the central frequency, normalized
to be 1, for the low pass configuration. The corresponding high pass configuration produces a lead of
86
Chapter 6. Bandwidth of an Inverter
jω
j5
j4
j3
jω
j2
j
j
1
σ
1
σ
−j
−j2
−j3
−j4
−j5
Figure 6.5: The poles of a n-stage Π network, up to to 4 stages, is shown. Shown on the left is the low
pass configuration and on the right is the high pass configuration. An n-stage Π network has 2n + 1
poles. The high pass configuration also has 2n + 1 zeroes at the origin.
87
Chapter 6. Bandwidth of an Inverter
-88.6◦
-0.45π
Group Delay
Phase
-0.5π
-89.2◦
-0.55π
θ
ω=ωo
!
Group Delay
dθ dω Phase
ω=ωo
!
-88.8◦
-89.6◦
-0.6π
-90◦
-0.65π
0
5
10
15
number of stages n
20
25
30
Figure 6.6: The phase and group delay at a normalized central frequency of ωo = 1 is plotted for n
stages. Here, the network is designed for a desired phase, θo , of 90◦ at ωo . It can be seen that group
delay starts to settle at the value θo /ωo as the number of stages is increased, approximating (6.8), and
modeling the behaviour of a transmission line of electrical length θo = 90◦ at central frequency.
90◦ in combination with zeroes at the origin.
As the number of stages is increased the phase and group delay computed for S21 ω=ωo =1 start
approaching that of its equivalent transmission line counterpart. That is, if this n-stage network was
designed for a desired phase of θo at a central frequency of ω = ωo = 1, then its phase will start
approaching the desired phase value of θo as the number of stages is increased, and its group delay value
at the central frequency will start approaching θo /ωo = 1, i.e. (6.8). This occurrence is shown in Fig.
6.6 where the network designed for a desired electrical length of 90◦ , approximates the phase and group
delay behaviour of a transmission line as the number of stages is increased.
To summarize, the group delay of a transmission line was first introduced. It was found that it was
limited to θo /ωo , where θo is the desired electrical length of the line at ωo , the desired central frequency.
Then, equations to compute group delay at ωo using the location of poles of a S21 transfer function
was introduced. This was followed by a mathematical model of predicting the placement of poles for
an n-stage π-network that achieved a desired phase of θo and |S21 | = 1 at ωo . Using the model and
group delay computation methodology, the group delay was determined for an n-stage π-network. It was
found that as the number of stages increased, the group delay started to approach the transmission-line
group delay value of θo /ωo . Given the four necessary conditions, let’s call them the Single Signal Path
Passivity and Phase (SSPPP) conditions:
• |S21 | ≤ 1 ∀ ω - Since it is a passive network the transfer function cannot have a magnitude greater
than 1.
• |S21 |ω=ωo = 1 - Since at the frequency of interest, no reflections and or losses are expected of the
inverting network.
88
Chapter 6. Bandwidth of an Inverter
• ∠S21 = θo - Is the required phase delay.
ω=ωo
• No zeroes in the LHP or RHP - Since zeroes in the RHP and LHP are usually characteristics of an
all-pass network. All-pass networks’ zeroes are a result of multiple signal path cancellation from
one port to the other.
It seems as though there is a limit governing the minimum achievable group delay, and that limit
being θo /ωo . If it can be proven that the placement of poles of an n-stage is unique to achieving the
conditions listed above, then this limit is in fact true. Because, if the 2n + 1 poles of an n-stage ladder
network have a unique placement to achieve the conditions listed, and cannot be placed in any other
configuration, then they will always yield a group delay that is greater than or equal to that of an
equivalent transmission line. The limit being
dθ θo ≥
dω ωo ω=ωo
(6.29)
Let’s introduce a method of comparing group delay to its phase value. It is clear that a for network
that produces a phase of θo at ωo , the limit of minimum achievable group delay
dθ
dω
according to (6.29)
can be obtained by a normalizing factor ωo . That is, the group delay of any two port network can be
compared to its central phase value θω=ωo = θo by re-arranging (6.29), and normalizing the group delay:
dθ ωo dω
ω=ωo
≥ θω=ωo
(6.30)
So the idea is to figure out the regions on the complex plane where a conjugate pair of poles on the LHP
has a smaller normalized group delay than phase. This region is found by equating 6.13 and (6.24) for
a conjugate pair of poles whose real part is xp and imaginary part is yp :
xp
ωo + yp xp
ωo − yp
−1
−1
+
+ tan
≥ ωo tan
(wo + yp )2 + x2p
xp
xp
(wo − yp )2 + x2p (6.31)
This yields the shaded region shown in Fig. 6.7, where if any conjugate set of poles or a single pole on
the real axis lies within this region, its group delay contribution at the central frequency is less than its
phase contribution at the central frequency. A rigorous proof is not shown here, but it can be seen that
all but one of the poles of an n-stage Π network lie outside this region. This one pole that lies within
this region is the only contributor to a normalized group delay value that happens to be smaller than
the phase it contributes. Hence, the sum of all the contributions of all poles ends up with a group delay
that is greater than or equal to θo /ωo for an n-stage Π network. But the question still remains. Can
there be a possible combination of poles inside and outside this region that helps break this limit? This
study aims to show that it is very hard, if not impossible, to come up with a configuration of poles that
allows a two port network to meet the four criteria and break the transmission line group delay limit of
(6.29). Moreover, the analysis shown in this section is to provide a basis for the hypothesis that there
exists a unique placement of poles for an n-stage Π network that satisfies the SSPPP conditions. If this
hypothesis were true, it would mean that there is no allowable placement of poles that would break this
limit because there is only one unique solution for the fulfillment of SSPPP conditions and that unique
solution does not break the limit. The purpose of this study is then to motivate further reasearch into
proving that only a unique solution exists for a given number of poles that satisfy the SSPPP conditions.
89
Chapter 6. Bandwidth of an Inverter
jω
j5
j4
j3
j2
j
1
σ
−j
−j2
−j3
−j4
−j5
Figure 6.7: The shaded region on the complex plane indicates where conjugate poles when placed in
that region contribute a phase value that is greater than the normalized group delay. Up to 4 stages are
shown in an n-stage ladder network. Note that there is only one pole in this region and most poles lie
outside the region.
90
Chapter 6. Bandwidth of an Inverter
+
0
Z
Z
+
Z
Z
0
−
−
Figure 6.8: Circuit showing the schematic of the Wheatstone Bridge or lattice phase equalizer. This
network is excited differentially at both ports. There are four branches of components, typically realized
by a single capacitor and inductor for Z and Z 0 or vice-versa, depending on whether the phase needed
is ±90.
Also, it is useful to know the group delay of a n-stage ladder network because sometimes a quarterwave transmission line cannot be used to implement the impedance inverter due to size restrictions. In
these cases, lumped components may be used to implement the inverter and finding a tradeoff between
number of stages and group delay might be useful.
Another way of understanding what is happening
is to imagine the situation in terms of a Bode plot. Specifically the phase behaviour of a Bode plot due
to poles located at certain frequencies. When a pole is placed at ωo , the phase has dropped by 45◦ at
that frequency. Graphically, this pole would be placed at −ωo in the complex plane or equivalently -1
in a normalized complex plane. If the phase contribution of such a pole has to be lowered, it can be
placed at a higher frequency > ωo . Graphically, its placement would be at an xp > ωo , so that the drop
in phase is not 45◦ , but much less. This is what happens when more stages are added, there are more
poles being added at frequencies greater than ωo . It can be seen in Fig. 6.7, where the singular real axis
poles move left as more stages are added. The conjugate poles are placed at a higher frequency than ωo ,
this effective frequency can be computed by calculating the phase they contribute and then using that
information and (6.24) to find the x placement of an equivalent single pole that contributes the same
phase at ωo . This x placement of the equivalent single pole is then simply the effective pole frequency
ωeq . The expression for the effective pole frequency by a conjugate set of poles is given by
ωeq =
x2p + yp2 − 1
2x
(6.32)
where −xp and ±jyp are the real and imaginary parts of the poles. Once again, these poles have to be
placed at a ω > ωo , thereby smoothing out their phase contribution at ωo and eventually leading to a
two port that satisfies (6.29) at best.
6.4
Wheatstone Bridge or Lattice Phase Equalizer
There is one known network however that seems to yield a smaller group delay than a transmission line,
specifically only for a phase of θ > 90◦ . This happens to be the lattice phase equalizer or the Wheatstone
bridge network. It achieves this by violating the fourth condition in the criteria that no zeroes can exist
in the RHP. An ABCD analysis of this network reveals two poles and two zeroes for this network. The
two poles both being placed at -ωo on the real axis on the LHP as shown in Fig. 6.9. And the zeroes,
91
Chapter 6. Bandwidth of an Inverter
jω
jω
j
j
−1
1
σ
−1
⇒
−j
1
σ
−j
Figure 6.9: Poles and zeroes of a lattice phase equalizer or Wheatstone bridge network are shown. There
are two poles at -1, a zero at -1 and a zero at 1, shown on the left. A pole zero cancellation happens at
-1, simplifying the placement to one pole at -1 and a zero at 1, shown on the right. A 180◦ phase shift
exists between the Z = jωL and Z 0 = 1/jωC configuration and vice-versa. i.e. a ±90◦ can be achieved
at central frequency if the places of the inductors and capacitors are switched around.
√
one being at -ωo on the LHP and the other at ωo on the RHP, where ωo = 1/ LC. The inductors
and capacitors must be placed on the bridge such that Z = jωL and Z 0 = 1/jωC or vice-versa in the
network shown in Fig. 6.8. This network is strictly a differential network, and therefore it should not be
excited by unbalanced feeds like a micro-strip line. Such a network when designed to have a 90◦ phase
at ωo yields a group delay of
1
dθ =
dω ω=ωo
ωo
which is less than group delay of a quarter-wave line:
6.4.1
θo
ωo
=
(6.33)
π
2ωo
The ABCD Matrix
A schematic of the network is shown in Fig. 6.8. To find the ABDC matrix of this two port, the standard
approach of using short-open is used. This is explained below.
V1 = AV2 + BI2
I1 = CV2 + DI2
V1 = AV2 if I2 = 0. This happens when the output terminal is opened. Then, the input port is excited
with a voltage V1 and computing V1 /V2 yields an expression for A. Similarly, to find B, the output
terminal is shorted, V1 is applied to the input port, and an expression for V1 /I1 is determined. To find
C and D, the same procedure is repeated, except now the input port is excited with a current I1 . These
configurations are shown in Fig. 6.10. Using such an analysis, the transfer characteristics reveal A, B,
C and D of the lattice network.
92
Chapter 6. Bandwidth of an Inverter
Z
Z
Z
− V2 +
I2
I1
Z
Z
Z
Z
0
0
−
+
V1
0
0
Z
− V2 +
I2
Figure 6.10: On the left, exciting the input port with V1 and opening the output port to obtain the
reciprocal of the transfer function V1 /V2 yields A. Shorting the output port to obtain the reciprocal of
the transfer function V 1/I1 yields B. Similarly, on the right the input port is excited with I1 and the
reciprocal transfer function of I1 /V2 and I1 /I2 yields C and D respectively.
V1
V2
V1
I2
I1
V2
I1
I2
So then if Z = sL and Z 0 = 1/sC, then Zo =
can be applied:
Ψ
n
=
S21 =
"
"
Z 0 +Z
Z 0 −Z
2
Z 0 −Z
Z 0 +Z
0
Z
√ −Z
2 ZZ 0
Z 0 −Z
Z 0 +Z
Z 0 −Z
Z0 + Z
Z0 − Z
2ZZ 0
=B= 0
Z −Z
2
=C= 0
Z −Z
Z0 + Z
=D= 0
Z −Z
=A=
p
L/C =
√
(6.34)
(6.35)
(6.36)
(6.37)
ZZ 0 . Now, the Ψ transformation of the matrix
#
2ZZ 0 o
Z 0 −Z
Z 0 +Z
Z 0 −Z
#
√
2 ZZ 0
Z 0 −Z
Z 0 +Z
Z 0 −Z
√
2 ZZ 0
Z 0 −Z
2
√
2 ZZ 0
Z 0 −Z
0
Z +Z
+Z
0 −Z
√
√
0
02
2(Z − Z)
Z − Z2
√
√
=
= √
2(Z 0 + Z + 2 ZZ 0 )
( Z 0 + Z)2
√
√
√
√
√
√
( Z 0 + Z)( Z 0 − Z)
Z0 − Z
√
√
√
=
=√
( Z 0 + Z)2
Z0 + Z
1
√1
s − √LC
−s
LC
=
or
1
1
s + √LC
s + √LC
+
+
(6.38)
Chapter 6. Bandwidth of an Inverter
93
depending on whether Z = sL and Z 0 = 1/sC or vice-versa. This S21 results in the pole-zero placement
as given in Fig. 6.9, which in turn yields a group delay given by (6.33).
6.5
Lattice Network as Impedance Inverter
Theoretically, the lattice network can be used as an impedance inverter in the Doherty PA. However,
this requires a differential Doherty PA or a push-pull Doherty PA [27]. This way, the two ports of the
lattice network can be excited differentially. However, the benefit that the lattice network offers in terms
of BW improvement is quickly diminished by the compounded effects of second harmonic termination.
It is no easy feat to tune out the harmonics by terminating with appropriated impedances, and it is only
that much harder to do so in a push-pull configuration. In [27], the 2nd harmonic is shorted, and as it
was seen in the case of design in this thesis, this cannot always be done. A unique purely imaginary
impedance is sometimes needed to tune out the harmonics and this is very difficult to achieve in a pushpull configuration. In theory however, a differential Doherty PA with ideal devices that uses the lattice
network for impedance inversion does have better BW performance than a quarter-wave transmissionline based Doherty PA. It is because when the devices are ideal, the only BW limiting factor is the
impedance inverter.
6.6
Summary
It is known that inverting of the load is necessary to achieve Doherty functionality, therefore there was
a need for a network that achieved a phase of 90◦ and a magnitude of 1 for its transmission. Later,
the quarter-wave transmission line was used to realize this network. However, the problem was that
a quarter-wave line scales with frequency and therefore loses its inverting property as frequency drifts.
In this chapter, the bandwidth of such an inverter was attributed to how much the phase drifts with
frequency around that central point. This led to the group delay analysis of inverters and it was clear
that a smaller group delay meant more inversion bandwidth. So the question was, is there a network
that has a smaller group delay at 90◦ phase than a transmission line? It was found that the lattice
network has a group delay of 1/ωo , which turned out to be smaller than the group delay of a quarterwave transmission line of π/2ωo . And the other question, what is the smallest group delay achievable for
a two port network? Now, this chapter may have answered one of those questions with the lattice phase
equalizer having the smaller group delay. The lattice network being the Wheatstone bridge network
with capacitors and inductors in adjacent branches. These capacitor and inductor values can be tuned
to achieve 90◦ of phase and a magnitude of 1 at a desired frequency ωo . However, it was understood that
this network possesses such sub-transmission-line group delay because it has zeroes on the RHP of its
S21 transfer function. The second question was not answered directly, but analysis of poles and zeroes
of a ladder network was shown to study the behaviour of group delay and pole placement. And this
study hoped to shed some light on the understanding of why it is very difficult to create a two port that
has a smaller group delay than a transmission line. The placement of poles for an n-stage Π network
yielded a limit for the smallest achievable group delay as the number of stages was increased, and this
limit was that of a transmission line group delay, which could not be exceeded by such a ladder network.
Further analysis of pole placement highlighted a region on the complex plane in which the majority of
the poles have to be placed in order to beat this transmission-line group delay limit. It was not proven
Chapter 6. Bandwidth of an Inverter
94
in this thesis whether a solution for the placement of poles exist that helps beat this limit, but if it can
be proven that the placement of poles for an n-stage ladder network given by 6.28 is unique, then this
limit is in fact true given the four SSPPP conditions. First and second being the magnitude and phase
have to be 1 and 90◦ respectively. The third being |S21 | < 1 for all ω. And finally, there aren’t any
zeroes in the RHP, i.e. it is a minimum phase network.
Chapter 7
Conclusion
A simple Doherty PA was designed and fabricated from scratch using GaN devices for enhanced efficiency
in the 1.5 GHz range. This work hopes to shed light on the design process of a Doherty PA and some
of its pitfalls. The design procedure outlined is specifically targeted towards GaN devices but can also
be extended to use with other devices. A big emphasis was placed on harmonic optimization and it was
shown that without harmonic optimization, the designed amplifier will not achieve enhanced efficiency
performance. Design procedures of the various components involved in designing a Doherty PA were
demonstrated. At the heart of this discussion was the design of the double impedance device matching
network and its tuning. The matching network allows the output network of the Doherty topology to
present optimum impedances at both the back-off operating point and the peak operating point of the
main device. This is necessary to achieve enhanced efficiency at the back-off condition, which is desired
in amplitude modulated signals.
Many design trade-offs and pitfalls were explained in Chapter 3 of this text. With this knowledge in
mind, Chapter 4 focused on the simulated design procedure where the amplifier was designed using the
aid of load-pull characterization. This step in the design process is crucial as it allows the user to study
the performance of the devices used to construct the amplifier. The flexibility of simulated design also
enables the designer to make design trade-offs and comparisons. This step is where design specifications
need to be addressed. In this thesis, a classical symmetrical Doherty PA was designed with identical
devices for both the main and auxiliary branches. However, the procedure can be extended to other
variations keeping in mind the principles of load modulation. In essence, this text aims to highlight the
core formulaic procedure needed to design the foundations of a Doherty PA.
Some thought was also given to the BW and specifically the BW of the PA under back-off operation
since the Doherty PA’s main function is higher efficiency at back-off. From Section 4.8, it was understood
that the efficiency at back-off can be studied by the load termination at the fundamental and 2nd
harmonic load. It was this analysis that led to the conclusion that there is no universal, formulaic
method to optimize efficiency BW at back-off, but tuning the 2nd harmonic termination to optimum
regions was necessary. However, outside of the second harmonic tuning, the rest of the design is in
fact systematic. The design of the fundamental termination, matching network, and other components
followed a step by step approach that resulted in the design, simulation, fabrication and measurement
of a 10 W symmetrical GaN Doherty PA.
The fabrication of the PA is the last step in the design. In this step, the output network needs
95
Chapter 7. Conclusion
96
special attention. The output network alone, which includes the output taper, the matching networks
of the devices and the quarter-wave transformer, all need to be fabricated and characterized first before
fabricating the rest of the Doherty PA. This step helps the designer to compare the terminations the
device sees on a fabricated output network versus a simulated one. In this thesis, it was noted that the
physical length of the lumped components used for the matching network and the launching pad used
to make contact with the drain of the transistor add insertion delay. This delay causes distortion of
the terminating impedance as if there were a transmission line of fixed length due to the dimensions
of the pad and components. Fabricating the output network alone allows the designer to characterize
this delay and then redesign the matching network to account for it. However, there may still be a
difference in the pad delay between the simulated and fabricated design as was the case in this thesis
where the pad delay was first characterized to be 30◦ , but then a de-tuned simulation of the original
design which adjusted the delay to be 10◦ showed correspondence with the in-lab measurements. This
is because every time an output network is fabricated and its delay characterized, the re-iterated design
compensating for the characterized delay will have a different matching network and this will ever so
slightly change the previously characterized delay. This is also much more significant if the matching
network has a discrepancy in the number of stages between iterations because now the physical length of
the matching network composed of lumped components has changed. Therefore, this part of the design
process may need a few iterations to converge on a final design. That is, if the design presented here
were to be re-iterated, the next iteration of the design would model the pad delay with a transmission
line of electrical length 10◦ instead of 30◦ as in Fig. 5.5. This step can be referred to as post-fabrication
tuning of the PA. The shortcoming of this work is simply the thorough post-fabrication tuning of the
design. Nonetheless, this delay can be removed through an iterative design, however tedious it may be.
The design methodology of the various components of the amplifier remain the same however, proving
this systematic design procedure to be repeatable and robust. Using this method, a designer can develop
a Doherty PA as long as the components used are rated for the scenario.
7.1
Recent Research Efforts
By going through the design process from start to finish, it is easy to see why the BW of an actual
fabricated amplifier is not a trivial metric to accurately predict and control. It is affected by many
factors from harmonic termination to the design of the matching network to device pad delay. Moreover,
the principal contributor to optimum efficiency and consequent BW is the load-pull contours of the
device being used. These contours are device dependent and the operating metrics such as gain and
efficiency may vary across power devices due to size, structure, and type of technology. Efficiency is a
result of how close the designed impedance network meets these contours both at back-off and at peak
power levels. When analyzing BW using load-pull contours it was found that efficiency is affected by
not only the fundamental impedance, but also the second harmonic impedance. In [25], a Doherty PA is
designed over a reasonably large BW 2.3-2.9 GHz because the second harmonic contours do not shift too
much in that frequency range, which in turn allows the designer to focus on tuning the fundamental load
termination. In this paper, the fundamental termination is optimized for back-off and peak power levels
using a method called the real frequency technique first introduced by Herbert J. Carlin in 1979[28].
This procedure simply allows a designer to develop an optimized two port matching network given the
Γ of the load as a function of frequency. This small signal optimum load characteristic is not readily
Chapter 7. Conclusion
97
available since it has to be obtained from load-pull contours, which can be a tedious and convoluted
task. Hence, the method introduced in [25] is not so straight forward since extracting S-parameter
characterization of an optimum load obtained from load-pull contours is no easy feat. Moreover, this
sort of optimization often calls for distributed matching or a number of stages of lumped components.
In Chapter 5, it was shown how stacking a series of lumped components in the signal path can introduce
a transmission length to the matching network and how this is detrimental to the overall design of the
Doherty PA. Having a large number of lumped components also introduces losses. So it is desirable to
have a simple L-network to perform the double matching of ZBO and ZP to the real axis as described in
this thesis.
Sometimes a design criteria may require the need for an asymmetrical Doherty PA if greater back-off
levels need to be achieved. This means the auxiliary amplifier will be realized with a device that differs
from the main amplifier. In this case, the matching network used to match the devices will also differ.
Therefore, the transmission phase across the main and auxiliary amplifier will differ. In order to fix this
difference, an offset line may be used to re-align the phase of the two signals [11]. In some cases, if the
output impedance seen looking into the auxiliary amplifier isn’t sufficiently large enough in magnitude,
i.e. it is a small reactive value, offset lines can be used to shift this small reactive impedance to a large
value. Introducing offset lines only causes the impedance characteristic of the Doherty’s output network
to be more sensitive to frequency. As a matter of fact, the sensitivity to pad delay that was seen in the
design shown in this thesis is because the pad can be seed as an offset line, and the phase of such an
offset line becomes crucial. Ideally, it would be in the best interest to avoid the use of offset lines as
this complicates the design process. But nonetheless, it is sometimes required and cannot be mitigated.
In such cases, careful design, characterization, and tuning of the offset line is required. Moreover, it is
inaccurate to assume that offset lines are always detrimental to BW. It may be the case that an offset
line attached to the auxiliary amplifier may act as a stub, modifying the impedance seen by the main
amplifier at the second harmonic for improved performance at a certain frequency. The only way to
definitively tell is to perform a BW analysis using load-pull contours as in Section 4.8.
In [4], the method of lumping the device parasitics along with a section of transmission line was
introduced to implement the inverter. This is a form of offset-line matching and the BW suffers when the
Q of the impedances to match to are high, e.g. 15+j45 where Q = 3. In these cases, the auxiliary amplifier
cannot be matched in the same fashion, and will require a longer offset line or input compensation line
to align the phases of the currents again. Typical wide-band matching of PA’s are implemented using a
shunt inductor to resonate with the output capacitance of the device. This cancels out the reactive part
of the optimum impedance [4]. However, since the Doherty PA requires load modulation, this will not
work since a shunt inductor alone is not capable of tuning out the reactive part for both ZP and ZBO .
This is where the double impedance matching procedure introduced in this thesis differs from matching
networks of the past and allows the designer to match nearly any two impedances with arbitrary reactive
values to two new points on the real impedance axis.
7.2
Key Contributions
Doherty PA’s have been around for over half a century and there have been many renditions of the
amplifier. The highlighting contribution of this thesis is the systematic approach to design a Doherty
PA from packaged devices, specifically GaN ones. These devices tend to have optimum impedance values
Chapter 7. Conclusion
98
that of high Q as depicted in Fig. 4.5. In such cases, the matching of devices becomes a task in of itself.
Most design procedures glance over this topic and design a matching network for the device optimized
for one of the two optimum impedances, ZBO or ZP , and not both [29]. While others lump together the
matching network used for the main device along with a short section of a transmission line to achieve
the 90◦ phase shift or load inversion between the main device and the common load [30], but no mention
of how devices such as GaN which often have high Q optimum impedances can be matched at both peak
and back-off conditions. In many cases, short offset lines are used to bring both ZBO and ZP onto the
real axis [31], but this may not always be possible to do with short sections if the optimum impedance is
of high Q. If the lengths of offset lines are comparable to λ/4, the matching becomes very narrow-band
because of electrical length scaling of transmission lines. This is why lumped component matching as
implemented in this thesis becomes beneficial to the designer for BW purposes. Moreover, this double
matching technique can be used to match any device, not just GaN with high Q optimum impedances,
for a Doherty PA application. Ignoring the efficiency BW lost due to second harmonic tuning and post
fabrication tuning, this double matching technique can achieve a 46% fractional BW of at 40% drain
PAE. This is comparable to some of the highest recorded BW from Doherty PA designs in the past at
56%[5]. It was reported here that a matching network that uses a series of micro-strip lines and shunt
inductors were used to match the device optimum impedance to 50 Ω. From the analysis presented in
this thesis, it is clear that it is not just one impedance that needs to be matched, but two. The methods
to achieve this double matching is not clearly portrayed in this paper or any others for that matter.
It is this issue that this work aims to outline, i.e. the systematic procedure of Doherty PA design and
significance of double impedance matching to do so. Also, it aims to shed light on the fact that two
Doherty PAs with different devices will require drastically different 2nd harmonic tuning to boost the
efficiency, and consequently the BW limit related to efficiency is subjected to the device and how well
the tuning can be optimized over frequency.
7.3
Future Work
The systematic design procedure presented in this thesis could be extended to the many variations of
the Doherty PA, i.e. the asymmetrical Doherty PA, or the N-way Doherty PA, which involves multiple auxiliary amplifiers for hitting multiple back-off power levels. A more detailed study of efficiency
degradation due to the 2nd harmonic across various power device technologies would also help to shed
some light on this issue. As it was noted, 2nd harmonic degradation was the key factor in the decreased
BW in the simulated design in this thesis. Adopting this design methodology for a Doherty PA with
another technology where the harmonic terminations are not so crucial may help highlight the benefit
of this design procedure. Properly accounting for the pad delay and tuning would also improve this
design dramatically. Therefore, a procedure to de-embed the pad delay and design the amplifier would
be beneficial for the design methodology presented.
7.4
Closing Remarks
The work presented in this thesis aimed to demystify the design procedure of a Doherty PA, and how to
realize it using GaN devices. The typical design methodologies documented about have been a subject
to optimization and tuning more so than a step-by-step design procedure. So, in this work, the discussed
Chapter 7. Conclusion
99
key design elements aimed to maximize the efficiency and BW using a systematic procedure. Albeit this
optimization was not fully demonstrated in the design due to imperfect fabrication and 2nd harmonic
termination, the reasons as to how this procedure is still valid was noted. Presenting the workings of a
Doherty PA, a simulated design, a fabricated design and its measurements, this work has accomplished
its initial purpose.
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