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Development of microwave and millimeter -wave pin grid array and ball grid array packages

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Development of Microwave and Millimeter-Wave Pin Grid
Array and Ball Grid Array Packages
A Thesis Presented to
The Academic Faculty
By
Hongwei Liang
In Partial Fulfillment o f the Requirement
for the Degree Doctor o f Philosophy in the
School o f Electrical and Computer Engineering
Georgia Institute o f Technology
Atlanta, GA 30332
November, 2001
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UMI Number 3032458
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Copyright 2002 by ProQuest Information and Learning Company.
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Development of Microwave and Millimeter-Wave
Pin Grid Array and Ball Grid Array Packages
Approved:
iirman
CStevenson Kenney
Date Approved
lljz/jd I
ii
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D edicated to my fam ily
iii
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Ackowledgements
First and foremost, I would like to thank God for blessing me and giving me the
chance to pursue the Ph.D degree in Georgia Tech.
I’m extremely grateful for the guidance, encouragement, and support that I
received from Dr. Joy Laskar. He has always nourished me with fresh ideas to overcome
the barriers in front of me. Without his help and enthusiasm, it is impossible for me to
obtain many opportunities to build my professional career and complete this thesis. I
gratefully acknowledge Dr. Robert Feeney, Dr. Steve Kenney, Dr. Manos Tentzeris, and
Dr. Jianmin Qu to serve in my PhD. exam committee.
I have benefited a lot from the collaboration and support from industries,
especially from Agilent Technologies and Micro Substrates Corporation. I would like to
give my deepest appreciation to Dr. Don Estreich and Ms. Heidi Bames in Agilent, and
Mr. Mike Hyslop in Micro Substrates for their ideas, cooperation, and providing me of
summer jobs. I would thank the NSF Microsystems Packaging Research Center in
Georgia Tech for the opportunities to work on so many exciting projects.
Special thanks go to all members of the legendary Microwave Applications Group
under the leadership of Dr. Laskar: Carl Chun, Anh-Vu Pham, Josh Bergman, Edward
Gebara, Daniela Staiculescu, Emery Chen, David Cresci, Mekita Davis, Mike Hamai,
iv
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Kyutae Lim, Chang-ho Lee, Ramana Murty, Sebastien Nuttinck, Ade Obatoyinbo,
Arvind Raghavan, Youngsuk Suh, Gio Cafaro, Albert Sutono, Stephane Pinel, Stephanie
Horveno, Neeraj Lai, Jishnu Bhattachaijee, Moonkyun Maeng, and Debanjan Mukherjee.
I also thank Dr. Tentzeris and his group members for a lot of discussion in the projects.
I would thank many friends in Tech and Atlanta for their friendship, help, and
many exciting parties. I would give my heartiest thank to Yao Lin whom I have shared a
lot of time with and received tremendous encouragement from.
Last but most importantly, I would like to express my gratitude to my
grandparent, Jinwen Liang and Baoying Wang, my parents, Xiuzhi Liang and Jinru
Wang, and my brothers, Qianbing and Jin, for their endless love.
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Table of Contents
Dedication ............................................................................................................ iii
Acknowledgement................................................................................................. iv
List of Figures..........................................................................................................x
List of Tables.........................................................................................................xv
Summary
...........................................................................................................xvi
Chapter 1. Introduction........................................................................................ 1
Chapter 2. Background......................................................................................... 7
2.1 Peripheral and Area Array Packages.............................................................................. 7
2.1.1 Peripheral Array Packages..............................................................................7
2.1.2 Area Array Packages....................................................................................... 9
2.2 Advantages of Area Array Packages Over Peripheral Array Packages....................... 12
2.2.1 Higher I/O Interconnect Count and Density................................................. 13
2.2.2 Smaller Parasitic Parameters....................................................................... 16
2.2.3 Better RF Performances.................................................................................18
2.3 Numerical Methodsfor Electromagnetics....................................................................20
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Chapter 3: Microwave Package Measurement and De-Embedding.................27
3.1 Introduction o f Microwave Measurement........................................................................27
3.1.1 Error Sources and Twelve-Term Error Model...............................................................29
3.1.2 Vector Error Correction Methods..................................................................................34
3.2 Review o f De-Embedding Techniques..............................................................................37
3.3 Analytical De-embedding Technique — Thru-Line-Line De-Embedding
Technique...............................................................................................................................40
Chapter 4: Microwave and Millimeter-wave PGA Packages............................44
4.1 Introduction..................................................................................................................... 44
4.2 Microwave PGA Package Architecture............................................................................48
4.3 First Generation Interconnection for 10-GHz Application............................................. 53
4.4 Second Generation Interconnection for 26.5-GHz Application...................................... 59
4.4.1 D esign.............................................................................................................................59
4.4.2 Optimization o f the Performance to 32 GHz.................................................................. 64
4.4.2.1 Comprehensive Analysis Method................................................................64
4.4.2.2 TDR from S-parameters..............................................................................66
4.4.2.3 Result........................................................................................................... 68
4.5. Conclusions.....................................................................................................................71
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Chapter 5 Millimeter-Wave BGA Packages..................................................... 72
5.1 Introduction......................................................................................................................72
5.2 BGA Package Structure................................................................................................... 74
5.3 Measurement and De-Embedding o f the BGA Test Structure.........................................77
5.3.1 Design and Measurement TLL Components.................................................................. 78
5.3.2 Obtaining the S-Parameters o f the Launch....................................................................86
5.3.3 De-Embedding the Launch............................................................................................. 90
5.4 Equivalent Circuit Modelfor the BGA Transition.......................................................... 93
5.5 Application o f the Package.............................................................................................. 98
5.6 FEM Analysis o f the BGA Package............................................................................... 100
5.6.1 Modeling Strategy......................................................................................................... 100
5.6.2 Modeling Result............................................................................................................ 104
5.6.3 EM Analysis o f the BGA Package................................................................................108
5.6.3.1 Field Leakage Phenomena....................................................................... 108
5.6.3.2 Radiation Phenomena...............................................................................112
5.7 Conclusions.....................................................................................................................115
Appendix A: Matlab Code for Thru-Line-Line De-embedding
Algorithm .......................................................................................................... 117
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Appendix B: Matlab Code for the Frequency-Domain to Time-Domain
Conversion..........................................................................................................126
References ..........................................................................................................134
Publications Resulting from Thesis Work........................................................ 142
VITA.....................................................................................................................145
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List of Figures:
Figure 2.1. Examples of area array packages.
7
Figure 2.2. Illustration of a peripheral package structure
8
Figure 2.3. Illustration of an area array package structure.
9
Figure 2.4. Examples of area array packages
10
Figure 2.5. Illustration of interconnect dimensions of an area array package (left) and a
peripheral array package (right)
11
Figure 2.6. Relation between the side length o f an area array package and the pincount N
and pitch pa.
12
Figure 2.7. Illustration for calculating the maximum area pitch p„ of an area array
package. The package is assumed to occupy the same area as the die with the
peripheral wirebonds.
13
Figure 2.8. The maximum attainable area pitch pa vs. the pin count N and peripheralpitch
d for a square die.
13
Figure 2.9. A tetrahedron in HFSS simulation
19
Figure 3.1. HP 8510 test set
24
Figure 3 2. Twelve-term error model for an automatic network analyzer.
26
Figure 3.3: Eight-term TRL error model
30
Figure 3.4. Illustration of a typical de-embedding application
32
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Figure 3.5. Equivalent circuit model of the parasitic series impedances and shunt
admittances of the contact pads and interconnections on Si wafer
33
Figure 3.6. Construction of the three TLL components
35
Figure 3.7. The S-parameters of the TLL components and the original test structure
36
Figure 4.1. A traditional deep cavity metal package
39
Figure 4.2. (a) A microcircuit packaged in PGA package, (b) A complete PGA Package
with the lid.
41
Figure 4.3. The exploded view of the PGA package
42
Figure 4.4. Prototype PGA with first generation soldered pin interconnection.
43
Figure 4.5. RF pin goes through the microstrip substrate and the baseplate
44
Figure 4.6. Measured and modeled performance of the first generation PGA package with
soldered pin interconnection
46
Figure 4.7.3-D model of the first generation interconnection
47
Figure 4.8. E-field distribution at the view plane 1
48
Figure 4.9. E-field distribution at the view plane 2
48
Figure 4.10. The relation between the return loss of the first generation PGA
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interconnection and the baseplate through hole diameter and the backside ground
i
i
relief diameter.
49
Figure 4.11. Measured and modeled TDR response of the optimized PGA soldered pin
interconnection matches very well
50
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Figure 4.12. Test structure of the second generation PGA interconnection with ribbon
bond
51
Figure 4.13. (a) 3-D EM model for the second generation PGA interconnection, (b) The
pin is placed eccentrically in the substrate hole.
52
Figure 4.14. Measured and modeled return loss and insertion loss of the second
generation PGA interconnection
54
Figure 4.15. Full-wave analysis of the second generation PGA interconnection
55
Figure 4.16. The design routine using the comprehensive analysis method
57
Figure 4.17. The reflection wave in time domain is the convolution of incident wave and
s„(t)
58
Figure 4.18. TDR responses from measurement and model of the second generation PGA
interconnection match very well
60
Figure 4.19. Optimization result shows that the interconnection can achieve a better than
25 dB return loss over DC to 26.5 GHz.
62
Figure 4.20. A second generation PGA interconnection has a good electrical performance
to 32 GHz.
62
Figure 5.1. Photograph of the millimeter-wave BGA package
66
Figure 5.2. The PCB motherboard used to mount the BGA package.
67
Figure 5.3. A BGA test structure with a 50 £2 microstrip with double wire bond
interconnection to the package
68
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Figure 5.4: TLL components for de-embedding the coplanar adapters in BGA
measurements
70
Figure 5.5. Measured S-parameter of the THRU
72
Figure 5.6. Measured S-parameters of Line 1
74
Figure 5.7. Measured S-parameter of Line2
75
Figure 5.8. The launch whose S-parameters are solved using TLL algorithm
76
Figure 5.9. S-parameters of the CPW launch.
79
Figure 5.10. Comparison between the S-parameters of the orginal measurement data and
the de-embedded data
81
Figure 5.11. The hybrid circuit model for the BGA transitions
83
Figure 5.12. Very good correlation between the modeled S-parameters and de-embedded
measurement S-parameters
86
Figure 5.13. The performance of a single transition
86
Figure 5.14. Test structure is built with a pHEMT MMIC amplifier packaged in the BGA
87
Figure 5.15. The gain of the amplifier is comparable to that of the bare MMIC chip
88
Figure 5.16. The BGA test structure for EM modeling
89
Figure 5.17. The 3-D model of the BGA structure for EM analysis
90
Figure 5.18. The circuit used to obtain the S-parameters of the whole structure
90
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Figure 5.19. Part of the 3-D model showing the signal ball (half cylinder) and three
grounding balls
91
Figure 5.20. Transparent view showing the signal via (in the circle) and the grounding
via slot
91
Figure 5.21. The wirebond model is created using 3-D bended solid line segments
92
Figure 5.22. Simulated S-parameters of the BGA model in Fig. 5.17.
93
Figure 5.23. The S-parameters from the EM model and the S-parameters from
measurement.
95
Figure 5.24. The EM model with the coordination.
96
Figure 5.25. E field pattern at view plane 1 (y=4 mil).
98
Figure 5.26. E field pattern at view plane 2 (z=17 mil).
98
Figure 5.27. E field patterns at two different planes
99
Figure 5.28. Part of the CPW wave on the PCB is coupled into the leakage region
100
Figure 5.29. Radiation phenomena of the BGA package around 40 GHz
101
Figure 5.30. Electrical field distribution and field line pattern of the radiation wave
across the plane z=-20 mil
102
Figure 5.31. Leakage phenomena at 40.4 GHz
103
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List of Tables:
Table 2.1. Comparison of electrical performance between area array packages with solder
bump interconnects and peripheral packages with wirebonds and leads
interconnects.
15
Table 2.2. Microwave frequency performances of solder bump interconnects and
wirebond interconnects.
17
Table 3.1. Error sources in the measurement setup when using network analyzer
28
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Summary
Microwave packaging provides both a support structure and a protective
enclosure for the monolithic microwave integrated circuits (MMICs) and microcircuits,
furnishes electrical and thermal pathways between the chip sets and the system. The
design requirements for the microwave and millimeter-wave packaging are more
demanding than those typically encountered for digital or low frequency analog
applications, it has to meet many new performance requirements and challenges coming
from the wave nature of RF signals, high I/O interconnection density, and mixed signal
handling capability, etc.
This thesis explores the usage of area array package designs for microwave and
millimeter-wave frequency applications. The core of the research is on the pin grid array
(PGA) and ball grid array (BGA) packaging technologies. The PGA packaging design
has been successfully developed for 32 GHz microwave modules and subsystems
packaging the first time; and the BGA packaging design has been developed and
characterized for millimeter-wave single chip packaging. To achieve these goals, new
methodologies have been developed including an analytical de-embedding technique for
accurate package measurement and characterization, as well as an a comprehensive
method combining both time-domain analysis and frequency domain electromagnetic
analysis.
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Chapter 1
Introduction
The past decade has seen tremendous development in the RF/microwave
communications technologies, such as the cellular telephony, ubiquitous device
connectivity, portable Internet access and broadband communication. People’s
communication styles are improved to the level unimaginable before. However, the
demand for more advanced communication technologies from voice to video and data
transmission has never stopped. Increasingly higher rates of data transmission are
urgently needed. This requirement has pushed the development of the communication
technology into higher and higher frequencies, where bandwidth capacity is more readily
available [1]. For example, some new applications are taking off very quickly such as
28~40GHz local multi-point distribution systems (LMDS), 12-60 GHz wireless local
area networks (LAN) [2]-[3], broad band Ka-band satellite communication systems [4][6], 77 GHz vehicle collision control systems [7], and 40 Gigabit per second (Gbps)
fiber-optic communication [8]. These applications have provided the impetus for research
and development of advanced microwave and millimeter-wave packaging technologies to
satisfy the demands for higher performance requirements.
Microwave packaging provides both a support structure and a protective
enclosure for the monolithic microwave integrated circuits (MMICs) and microcircuits,
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furnishes electrical and thermal pathways between the chip sets and the system. The
objective of microwave packaging is to transfer microwave signals through several levels
of integration while preserving the bandwidth [1]. The design requirements for the
microwave and millimeter-wave packaging are more demanding than those typically
encountered for digital or low frequency analog applications, it has to meet many new
performance requirements and challenges coming from the wave nature of RF signals,
high I/O interconnection density, and mixed signal handling capability, etc. Beside the
electrical performance issue, the microwave packaging design must evolve concurrently
with the solutions to others system requirements such as power and signal distribution,
thermal management, structural design and reliability, assembly and test processes. The
effects of materials, processes, and enclosure characteristics on microwave signal
transmission are also very important factors for designing [9]-[17].
Packaging also remains a major cost driver for microwave systems. A cost
effective packaging approach that meets system requirements is urgently needed in the
highly competitive electronic market. The packaging materials must be compatible with
automated assembly and test processes in manufacturing in order to realize the low-cost
goal of batch-processed MMIC chips.
As a summary, every microwave package must perform six distinct functions [9][17]:
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•
Provide an efficient means for RF signal transmission and power distribution
to and from the IC within the package
•
Provide an efficient means for signal transmission and power distribution
between the packaged device and other components of the system
•
Enable the device to be attached to the next level of packaging through a
suitable interconnect scheme, such as surface mount technology (SMT)
•
Allow for effective dissipation of heat generated by the packaged device
during its operation
•
Provide adequate protection of the device from external forces of mechanical
or environmental nature, which may damage the device. These external forces
may include vibrations, physical handling, moisture penetration, and chemical
corrosion, among others
•
Act as space transformer between the fine pitch grid of IC and the PWB pitch
grid that is typically much larger than the IC grid
The objective of this research is to explore efficient area array package designs
for microwave and millimeter-wave frequency applications. Area array packages are
believed to have a good balance between those conflicting requirements mentioned above
and be most suitable for the next generation applications [1][16][18]. The core of the
research is on the pin grid array (PGA) and ball grid array (BGA) packaging
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technologies. The developed PGA technology has an aim for microwave modules and
subsystems packaging; and the BGA technology is designed for millimeter-wave single
chip packaging. To achieve these goals, some methodology have been developed
including a comprehensive analysis method for package design and an analytical-based
de-embedding technique for accurate package measurement and characterization.
The original contributions of this thesis include:
-
Development of a novel DC-to-50 GHz Through-Line-Line de-embedding technique
for millimeter-wave packages measurement and characterization. It enables accurate
de-embedding for microwave devices with over quarter wavelength measurement
launches.
-
Optimization of a soldered pin PGA interconnection to 20 dB return loss at 10 GHz
for a PGA package which greatly reduces the packaging costs of microcircuits and
multi-chip modules.
-
First demonstration of a new PGA package with wirebonded pin interconnection to
32 GHz microwave application.
-
Development of a comprehensive package analysis method to efficiently analyze and
optimize package interconnect design.
-
Development of a 36 GHz ceramic BGA package
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Development of a simple and accurate hybrid element equivalent circuit model for the
BGA transition from DC to 40 GHz.
-
Discover the electromagnetic field radiation and leakage phenomena associated with
the BGA package.
This thesis is organized in the following order. Chapter 2 provides a quick review
of current microwave packaging technologies including peripheral array and area array
packaging technologies. The advantages of area array packaging technologies over
peripheral packaging technologies are demonstrated in terms of I/O number and density,
parasitic parameters, and RF performance. Then three kinds of numerical electromagnetic
methods commonly used in microwave circuits design are discussed. Chapter 3 gives an
introduction on microwave measurement theory and then focuses on a novel thru-lineline (TLL) de-embedding technique developed for millimeter-wave package
measurement. It first reviews the twelve-term error models for microwave measurement
using automatic network analyzers, followed by two popular calibration methods: shortopen-load-thru (SOLT) and thru-reflect-line (TRL) methods. Then it summarizes some
commonly used de-embedding techniques. After that, it presents the TLL de-embedding
technique in detail, including the algorithm and implementation method for the TLL
components. Chapter 4 presents the development of the first 32 GHz PGA package for
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microwave module and multichip assembly. The two generations of interconnection
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designs using solder and wirebonds are presented. The time-domain analysis and EM full
wave analysis to the package are performed and they are combined to optimize the
package. Chapter 5 presents the development of the 36 GHz BGA packages. The package
structure and the manufacturing process are explained first. Then the characterization of
the package is presented, it includes the S-parameter measurements of the BGA test
structure, TLL de-embedding of the coplanar launches, and development of a broad band
equivalent circuit model from DC-to 40 GHz. Finally, electromagnetic (EM) model for
the BGA test structure is constructed and two important phenomena are discovered from
full wave analysis.
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Chapter 2
Background
Area array and peripheral array packaging technology are the two major types of
packaging technologies commonly used in microwave electronics. This chapter gives a
review and quantitative comparison of these two technologies. The I/O density and the
electrical performance issues are emphasized due to their significance on modem
microwave and millimeter-wave applications. Since the electromagnetic (EM) numerical
methods are an indispensable tool in developing the microwave packages, some popular
numerical methods are discussed including finite element method (FEM) that is used in
the thesis.
2.1 Peripheral and Area Array Packages
2.1.1 Peripheral Array Packages
The earliest peripheral package is dual in line package (DIP) invented in 1960s
[1]. The most widely used peripheral packages for low GHz range microwave
applications are the small outline integrated circuit package (SOIC) and its extended
version, quad flat pack (QFP) package. Their I/O leads are on the two opposing sides of
the package (in SOIC) or all four sides of the package (in QFP). Fig. 2.1 shows pictures
of a 20 leads SOIC package and a 100 leads QFP package.
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A 20 leads SOIC package.
A 100 leads QFP package
Figure 2.1. Examples of peripheral array packages.
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The backbone in the SOIC and QFP packages is the metal lead frame which
supports the IC and provides electrical interconnects between the IC and the board. The
IC is attached on the central pad of the lead frame. Wirebonds are used to connect the
pads on the die and the lead frame. Molded compound is then used to protect the IC,
8
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wirebond and the lead frame. A peripheral array package structure is illustrated in Fig.
2 .2 .
Wirebond
Mold compound
Die
Lead frame
Figure 2.2. Illustration of a peripheral package structure.
2.1.2 Area Array Packages
As the I/O leads go beyond 300, it is very difficult for peripheral array packages
to handle that large pin count [19]. The requirement for an ultra fine pitch size in order to
accommodate so many pins in a package will make the manufacturing process too costly,
also the very close pins are more prone to noise and cross talk issue. Area array packages
provide a solution to this problem by utilizing the bottom surface of the package rather
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than just the sides of the package for the I/O areas. The IC is mounted on the package
substrate and connected to it using wirebonds or flip chip bumps. The package is then
attached to the mother board with the solder balls. The major difference from the
peripheral array package is the way the electrical transitions from the IC to the mother
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board are formed. In the area array packages, vertical interconnects including the balls
and vias are part of the transition. Because they are significantly shorter than the leads in
the peripheral array packages, area array packages can achieve satisfactory electrical
performance at millimeter-wave frequencies easier than the peripheral array packages.
An area array package using wirebond interconnection is illustrated in Fig. 2.3.
Mold compound or encapsulant
Die
Wirebond
Substrate
Via
Solder balls
Figure 2.3. Illustration of an area array package structure.
Area array packages have been widely adopted in digital systems since 1980s.
Commonly used area array packages includes PGA, BGA, and flip chip. Fig. 2.4 shows
the pictures of these three packaging architectures.
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PGA package
BGA package
r ’.raflR■war1
flip chip
Figure 2.4. Examples of area array packages.
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2.2 Advantages of Area Array Packages Over Peripheral Array Packages
The demand for more functional, compact, portable electronic products has never
stopped. Higher functionality requires a more complex IC design with more I/O counts.
Compactness and portability requires the package to have a smaller real estate area and
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higher density of interconnections. Connecting the greater numbers of 1/Os on today’s
smaller circuits, particularly digital devices, has become a packaging challenge. These
requirements need a higher accuracy in wirebonding and more precise placement
machines for the traditional peripheral packages. Thus the cost of peripheral array
packaging will increase dramatically [20]. Many of these difficulties are avoided, or at
least delayed, by the use of area array packages. Benefits of area array packages also
come from the fact that the materials and processes can be transferred from the surface
mount technology. Higher assembly yields, and thus lower delivered system costs, can be
achieved from a low instance of electrical defects afforded by pretesting the area array
components [20]. A comprehensive package performance comparison between PGA,
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BGA, and QFP packages is presented in [20]-[21], which includes electrical performance,
thermal performance, reliability, and manufacturability. This section compares the area
!
array package and peripheral package in three aspects: interconnection count and density,
|
parasitic inductance, microwave frequency performance.
!
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2.2.1 Higher I/O Interconnect Count and Density
Some simple calculations have been performed to demonstrate the benefit of the
area array packages in terms of I/O interconnect number and density. Fig. 2.5 shows an
illustration of interconnect footprint layout and dimensions for an area array package and
a peripheral array package. For convenience all calculations were based on square dice
and square grid arrays.
VV
vv
Pa
Pp
Figure 2.5. Illustration of interconnect dimensions of an area of area array package (left)
and a peripheral array package (right).
First, for the area array package, the edge dimension of the array la has been
calculated depending on pin count N and I/O pitch pa. The result is shown in Fig. 2.6.
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E
35
E
>
a»
30
fc
3
25
3
fi
3
o
e
.o
*cn
eo
E
•5
uso
20
15
10
5
0
10
100
1000
10000
Number of pin count N
Figure 2.6. Relation between the edge dimension of an area array package and the pin
count N and pitch pa.
From Fig. 2.6, if the dimension of a square die is limited between 15 and 20 mm,
an area pitch pa of about 0.5 mm can be realized for a pin count of approximately 1000.
Hence the resulting pitch is larger than for an ultra fine pitch QFP for which the smallest
pitch is between 0.3 mm (in 1995). A QFP of 20 mm size with 0.3 mm pitch provides
2701/Os in ideal case. The same 20 mm area array package, however, provides 400 I/Os
at 1 mm pitch and 1600 I/Os at 0.5 mm pitch in ideal case. Larger pitches allow larger
clearances and less work in alignment, thus lower cost.
j
Next let’s calculate the minimum pitch pa for a given die. In calculation it is
assumed that the package occupies the same area as the die plus the peripheral
14
i
j
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wirebonds. The are occupied by the die and the peripheral wirebonds is determined by
the pin number N and the pitch d of the die, as illustrated in Fig. 2.7. The package re­
routes the peripheral wirebonds to the area array solder bumps on the package substrate.
The calculated relation between p„ and N are shown in Fig. 2.8. After re-routing, the pitch
of the area array bumps is much bigger than the pitch on the die. For example, an area
pitch pa of 0.8 mm can be realized for N=1000 and d=L00 pm. This means that when the
package is assembled on the board, a lower precision placement machinery can be used,
thus leading to a lower cost.
d: pitch of the I/O pad on the die
Substrate of the area array
package
Figure 2.7. Illustration for calculating the maximum area pitch pa of an area array
package.
15
i
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I
I
Die area: (pp*N/4)2 Package area: ( p ^Wn)2
1.4
0.8
0.6
a.
0.4
0
200
400
600
800
1000
1200
number of ptn count of the die (N)
Figure 2.8. The minimum attainable area pitch pa vs. the pin count N and peripheral pitch
d for a square die.
2.2.2 Smaller Parasitic Parameters
Area array packages such as BGA and flip chip use solder bumps, instead of the
metal leads and gold wirebonds, to make level one or level 2 interconnections. Because
these vertical solder bumps provides a shorter electrical path, and their diameters is also
generally bigger than that of metallic leads and wirebonds, their parasitic parameters such
as inductance and capacitance are generally much better than that of the solder bump
interconnections in the peripheral packages.
First, the self-inductance and the mutual inductance of the solder bump
interconnects are much smaller than that of wirebonds and leads. Reference [22] reported
the parasitic inductance of a solder bump with approximate diameter of 600 nm to have a
16
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parasitic inductance of about 0.3 nH, while the 33 pm diameter gold wirebonds used in
the same research have an inductance range of 2 to 5 nH for a wire length from 1 mm to
2.5 mm.
Second, solder bump interconnects have a smaller power supply inductance than
lead and wirebond interconnects. The QFP packages usually have a power supply
inductance in the 10-50 nH range, which is beyond the approximately 10 pH requirement
of today’s new electronic products. In reference [23], BGA packages are applied to
achieve a 5-fold reduction in system (both board and package) power distribution
inductance. Reduced power supply inductance causes a smaller power supply inductance
related noise. For example, in reference [24], small signal noise models show noise
reductions of 50-80% for models of BGA optimized power and ground routings.
Third, the crosstalk in the area array package is smaller than in the peripheral
packages. In reference [25], it is demonstrated that the crosstalk and noise performance of
BGA packages with lead counts of 50-320 has a consistent advantage over the
j
peripherally leaded counterparts.
Fourth, solder bump interconnections has speed advantage over the wirebonds or
leads due to the shorter length. In reference [26], a 10-20 % speed gain is reported when
j
BGA were used as drop in replacements for pin-in-hole packages without optimized
designs.
j
i
17
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The benefits in the electrical performance of using solder bump interconnects are
summarized in Table 2.1.
Area array package with
Peripheral packages
solder bump interconnects
with wirebonds and
leads interconnects
Parasitic inductance
-1 nH
2-5 nH
Power supply
-10 nH
10-50 nH
Noise and crosstalk
Small
Big
Speed
Fast
Slow
inductance
Table 2.1. Comparison of electrical performance between area array packages with solder
bump interconnects and peripheral packages with wirebonds and leads interconnects.
2.2.3 Better RF Performance
In microwave and millimeter-wave systems, the quality of these interconnects has
a large impact on the performance of the entire module or system. Some results of studies
18
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on the electrical performance of bond wire interconnections have indicated a drastic
increase of the loss as the frequency or interconnection length is increased [27]-[30].
Solder bump interconnects
Wirebond
interconnects
Better than 15 dB @ 120
Better than 15 dB @
GHz
15 GHz
Insertion loss (dB)
< I dB @ 120 GHz
<1 dB @30 GHz
Characteristic
109
170
Return loss (dB)
impedance (£2)
Table 2.2. Microwave frequency performances of solder bump interconnects and
wirebond interconnects. The solder bump is 40 mil in diameter, 80 mil in height, with a
pitch of 90 mil. (Note: data is from simulation.) The wirebonds are 17 mil long, 0.7 mil in
i
diameter, and they are built in ground-signal-ground configuration to interconnect CPW
lines, (from reference [31]).
j
j
At microwave and millimeter-wave frequencies, return loss and insertion loss are
used to measure the performances of many microwave devices including packaging
19
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interconnects. From these parameters, the reflection, dispersion, propagation delay,
attenuation of the interconnects can be extracted. The impedance matching for the
interconnects with the adjacent components is another important issue at microwave
frequencies. In microwave systems, usually the impedance is set to be 50 £2. In reference
[31], the above mentioned figure of merit of solder bump interconnects for area array
packages and regular wirebond interconnects have been compared using two particular
examples, as shown in Table 2.2. Obviously, solder bump interconnects give better
microwave performance than the wirebond interconnects.
2J Numerical Methods for Electromagnetics
In microwave and millimeter-wave package development, numerical EM methods
are very widely used at initial design and test structure analysis phases. The numerical
methods solve Maxwell’s equations using various mathematical algorithms in computers.
In package and interconnects, transitions between two or more different transmission line
configurations are usually unavoidable and are the places with the most parasitics. There
are no analytical formula available for designers, and some transitions are very difficult
or even impossible to measure. Further more, physical information including current
distribution, electromagnetic field patterns, modes, radiation, are only available from the
numerical methods computation. These information are especially important for coupling
and crosstalk issues. Since a lot of EM analysis will be used in our PGA and BGA
20
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packages, we will discuss three most popular and commercially available numerical EM
methods: finite-element method (FEM), method of moment (MoM), and finite difference
in time domain (FDTD).
Finite-element method fFEM)
The principle of the method is to subdivide an entire continuous domain into a
number of subdomains or elements. For a 3-D problem, the basis functions or elements
can be represented as tetrahedrons, triangular prisms, or rectangular bricks. In an
electromagnetic problem, the unknown electric and magnetic fields of the Maxwell’s
equations are then expressed as a linear combination of basic elements. This system of
linear equations can be solved by Glaerkin’s method to obtain the solutions of the electric
and magnetic fields [32].
High frequency structure simulator (HFSS) is a full-wave electromagnetic solver
for 3-D structures of any arbitrary shapes [33]. It uses the two “curl-curl” form of the
vector Helmholtz equations which are directly derived from Maxwell’s equations to solve
the 3-D field solutions.
, where h r = (O'fJioSo.
21
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The wave umber ka is known as the wavenumber of the free space. fj.r is the
complex relative permeability of the medium, and er is the complex permitivity of the
medium. £(.t,y,z)is a complex vector phasor representing anoscillating electrical field
E (x,y,z,t).
The
relation
betw een
the
phasor and
the
actual
field
is
E(x,y,z,t) = 9*[£(jr. y, z) em ]
In HFSS, the geometric model is divided into a large number of tetrahedrons,
where a single tetrahedron is a four-sided pyramid,
in Fig. 2.9. The collectionof
tetrahedrons is referred to as the finite element mesh.
Figure 2.9. A tetrahedron in HFSS simulation.
The value of a vector field quantity (such as the E or H-field) at points inside each
tetrahedron is interpolated from the vertices of the tetrahedron. At each vertex, HFSS
solves the components of the field that are tangential to the three edges of the tetrahedron.
22
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In addition, the component of the vector field at the midpoint of the selected edges is
tangential to a face and normal to the edge, as illustrated in Fig. 2.9. The field inside each
tetrahedron is interpolated from these nodal values. By representing field quantities in
this way, the Maxwell’s equations are transformed into matrix equations that can be
solved using traditional numerical methods.
HFSS creates an initial mesh that fills the geometric structure and defines the
points that contribute to the solution. The finite-element mesh is then automatically
refined until the differences of the adaptive solutions reach a stopping criteria specified
by the user. For a wide-band simulation, the mesh is created at an adaptive frequency
point and this mesh is used to analyze the structure over the entire bandwidth. The
complexity of a simulation can be significantly reduced if planes of symmetry are used to
reduce the size of the structure; for circular symmetry in a coaxial line, it allows a thin pie
shaped wedge to be used as the structure for analysis in HFSS.
Method of Moments
In Method of Moments (MoM) method, the original electromagnetic problem,
specified by the Maxwell's equations and the boundary conditions, are transformed into
integral equations in small domains where discretization is performed by expanding the
unknowns as a series of basis functions [32].
23
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The basic concept of MoM is to reduce a functional equation to a system of linear
equations that can be solved by matrix inversion techniques. To transform a functional
equation, the unknown function is first expanded in a series of basis functions with
unknown coefficients. The inner product of the functional equation and testing functions
reduces the equation into a matrix form. In Galerkin’s method, the testing function is
chosen to be same as the basis function.
Sonnet™ is a full-wave electromagnetic tool using the MoM to analyze planar
structures contained in a rectangular conducting box [34]. The analysis proceeds
automatically subdividing the circuit metallization into small rectangular subsections.
However, the basis building blocks of these subsections are set by the users. The fields
due to current in an individual subsection are represented by a sum of homogeneous
rectangular waveguide modes. Sonnet utilizes the rooftop distribution or basis functions
to solve for the current in the form of surface integral equations [34]. The distribution has
a triangle function dependence on the direction of the current flow and a rectangle
function dependence on the lateral direction. Using Galerkin’s method, a system of linear
equations relating to the tangential electric fields and surface currents are derived. The
magnitude of the current in all subsections is adjusted so that the weighted residual of the
total tangential electric field goes to zero on all metalization. All surface currents are
determined and the problem is solved. Though MoM has been proven to be a very robust
24
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i
technique, for computation of large geometries, it requires a very large computation time
and resources.
Finite-Difference Time-Domain (FDTD)
The FDTD method [35]-[36] has found many applications in modeling active and
passive microwave devices. The FDTD technique is a direct solution method for
Maxwell's time dependent curl equations. It is based upon volumetric sampling of the
unknown near-Held distribution within and around the structure of interest over a period
of time. Typically more than 10 samples per wavelength are required.
The FDTD method uses grid that is composed of rectangular boxes to divide the
structure. Each box edge is an electric field location, and the material for each mesh edge
can be specified independently of other edges. This regular grid is chosen because
making calculations for each grid element is extremely fast. This allows an
approximation to the actual physical geometry. The FDTD mesh size is 1/10 to 1/30 of a
wavelength, sometimes smaller. The time-step has to satisfy the stability condition. For
IJ
simulations of open geometries, absorbing boundary conditions are employed at the outer
grid truncation planes in order to reduce spurious numerical reflection from the grid
j
i
termination.
The FDTD method can provide a broad-band frequency information in a singlei
pass simulation using transient pulse excitation and FFT. However, the results directly
i
25
j
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produced by an FDTD run are time-domain data. They contain multiple frequency and
mode contents, so the extraction of desired frequency parameters from these data is an
important issue.
26
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Chapter 3
Microwave Package Measurement and De-Embedding
In microwave package development, measurement is an important step since it
provides the most useful data of the package performance. Measurement result is closely
related to the reference planes chosen. De-embedding is a technique referred to removing
the unwanted effect of measurement launches, contact pads, and/or connectors from the
measurement data. The performance of the DUT is most accurately obtained after the
measurement data is de-embedded to the reference planes same to the DUT edges. This
chapter discusses the fundamental concepts in microwave measurement and de­
embedding. In section 3.3, an original wide band de-embedding technique called ThruLine-Line (TLL) de-embedding is presented.
3.1 Introduction of Microwave Measurement
Vector network analyzers such as HP 8510 are used to measure the S-parameters
of the components and circuits at microwave frequencies. A S-parameter test set as part
of an HP8510 network analyzer system incorporates both transmission and reflection
measurements as shown in Fig. 3.1 [37]. If we begin with forward testing of a DUT, the
input switch connects the RF via the splitter to reference channel at and via a step
27
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attenuator in the incident channel to the device under test (DUT). A bias T, also inserted
in the incident and transmission channel, is to allow DC biasing on active DUTs. A
bridge circuit, similar to a directional coupler, but providing 6 dB or more isolation
between any two forward ports, separates the reflected signal into test channel b,. The
transmitted signal is separated from the main channel by a second bridge and directed to
test channel b2. In reverse, signal flow is in the opposite direction through the device,
with channel a2 as reference and b2 and b , as reflection and transmission outputs,
respectively [37].
ref.
test
test
ref.
6dB
Step attcn.
—
Bias T
VCO
attenuator.
bridge
R F j i
input p
tune
DUT
Figure 3.1. HP 8510 test set (from [37]).
28
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3.1.1 Error Sources and Twelve-Term Error Model
In the real test situations, imperfections exist in every network analyzer and can
cause measurement errors. Some factors that contribute to the measurement errors are
repeatable and predictable over time and temperature and can be removed, while other
errors are random and cannot be removed. Microwave measurement with network
analyzers are affected by three types of measurement errors: systematic, random and drift
[37]-[40],
1
i
Reflected
„ «> 11
►
o—
jt« »
Incident
0
*
bn
|°
j
e»
/
* oi
/
^
—►
I
►
‘1
*
[
2*
V
SS A ‘ 1
' h r*
? "
e
■Sri*
DUT
0
Transmitted
I
port forward error network
(a) six error terms in forward measurement (measuring su and s21)
DUT
Transmitted
o—«—<?
*—
►
en
4eot I
* I/A
t 'j l
*214
—
*114
Reflected
*12
►4
—
» O
‘
i
—4— o
Incident
■«--------------e ’ns
2-port reverse error network
(b) six error terms in reverse measurement (measuring sl2 and s^).
Figure 3 2. Twelve-term error model for an automatic network analyzer.
29
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Systematic errors are caused by imperfections in the test equipment and test setup.
If these errors do not vary over time, they can be characterized through calibration and
removed mathematically during the measurement process. Systematic errors encountered
in network measurements can be grouped in terms of signal leakage, signal reflections or
frequency response. There are two error terms in each group for a total of six error terms.
•
Signal leakage during transmission measurements is called crosstalk and is a
result of finite isolation between the test ports. Finite isolation of directional
couplers or bridges within the network analyzer results in a leakage term during
reflection measurements called directivity.
•
Signal reflections are due to imperfect source and load matches of the test ports.
Unless the DUT has perfect port matches, reflections occurring between the DUT
and test ports cause ripple in uncorrected transmission and reflection
measurements.
•
Frequency-response errors are associated with both transmission and reflection
measurements. Since S-parameter measurements are always ratioed
measurements, these errors are called tracking errors because they indicate how
well the various receivers in the network analyzer track one another across a
frequency sweep.
30
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When the network analyzer reverses, the source and load ports are exchanged, a
new set of six error terms applies for the swapped measurement direction. Therefore, the
full two-port error model includes six terms for the forward direction and six terms (with
different data) for the reverse direction for a total of 12 error terms. This situation is why
two-port calibration is often referred to as 12-term error correction [40]. Fig. 3.2 shows
the signal flow graph of the 12-tterm error model as well as the DUT.
In some cases, crosstalk, which is signal leakage between test ports whether or not
a device is present, can be a problem when testing high isolation devices such as a switch
in the open position, or high dynamic range devices such as filters with a high level of
rejection [40]. In such cases, a crosstalk calibration can add noise to the error model
because measurements are made near the analyzer’s noise floor. Fortunately, in many
two-port calibration situations, the crosstalk or isolation calibration often can be omitted.
If isolation calibration is deemed necessary, the best way to do is to place the devices that
will be measured on each test port of the network analyzer with terminations on the other
two device ports. Using this technique, the network analyzer views the same impedance
vs. frequency during the isolation calibration as it will during subsequent measurements
of the DUT. For high-Q devices such as filters, it should be performed with a narrow IF
bandwidth and trace averaging to ensure that the test system’s crosstalk is not obscured
by noise.
31
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Random errors are inherently unpredictable so they cannot be removed by
calibration. The main contributors to random errors are instrument noise, switch
repeatability and connector repeatability. When using network analyzers, the noise errors
often can be reduced by increasing source power, narrowing the IF bandwidth or using
trace averaging over multiple sweeps. Proper care and handling of the RF connectors in
the measurement system can minimize connector repeatability errors.
Drift errors occur when a test system’s performance changes after a calibration
has been performed. These errors are caused primarily by temperature variation and can
be removed by additional calibration. The rate of drift determines how frequently
additional calibrations are needed. Establishing a test environment with stable ambient
temperature usually minimizes drift errors.
These various error sources are summarized in Table 3.1.
32
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E rror
Details
Source of Errors
calibration ?
type
Systematic
error
Removable by
Equipment imperfections
Signal leakage e rro rs including
and setup imperfections
crosstalk and directivity errors
yes
Signal reflection e rro rs including
source match and load match errors
Frequency response erro rs including
reflection tracking and transmission
tracking errors
Random
error
Instrument noise, switch
The sampler noise and IF noise floor
repeatability, connector
can be reduced by increasing source
repeatability
power, narrowing the IF bandwidth or
no
using averaging. Caution is needed
when using connectors.
Drift error
. Can be removed
Temperature variation
by additional
calibration at new
temperatures
Table 3.1. Error sources in the measurement setup when using network analyzer.
33
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3.1.2 Vector Error Correction Methods
Vector error correction requires a network analyzer capable of measuring phase as
well as magnitude, and a set of calibration standards with known, precise electrical
characteristics. The process of vector error correction is based on the measurement of
known electrical standards, such as thru, line, open circuit, short circuit and precision­
load impedance. Measurement of these standards provide knowledge about systematic
errors in the test system. Once these errors are characterized, they can be removed
mathematically from subsequent measurements.
Two-port error correction accounts for all six forward and all six reverse sources
of systematic error, thus yields the most accurate results. Two-port calibration is most
commonly performed using open-short-load-thru (OSLT) standards, especially in coaxial
measurement environment. The other very popular method is thru-reflect-Iine (TRL)
calibraton, which is used primarily in non-coaxial environments using on-wafer probes,
waveguide, and test fixtures.
(a) SOLT Calibration
SOLT calibration solves all the 12 error terms by measuring the four standards
and an additional isolation measurement. The four standards includes one thru standard
and three reflection standards: short, open, and load. By measuring the reflection
responses at two ports with the reflection standards connected once at a time, six
34
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equations can be obtained. The measurement of the thru standard provide four data
including the forward reflection, forward transmission, reverse reflection, and reverse
transmission; and four equations can be obtained from them. Finally, the isolation
measurement in which the two ports are terminated with the system characteristic
impedance provides the last two error terms: forward isolation and reverse isolation. The
details of the SOLT calibration can be found in [37] and [38].
(b) TRL Calibration
TRL calibration measures the error terms with a different calibration standards
and a different error mode from OSLT. In the TRL calibration technique, an 8-term error
model is used, as shown in Fig. 3.3. This model, though looks very different from the 12term error model, it is actually a simplification of the previous model. There are some
variants of TRL, such as line-reflect-thru (LRM) and thru-reflect-match (TRM).
£ 10
i
%
U
I
!
*22
S [2
i
,
Sj2
K
fa
%
DUT
Figure 3.3: Eight-term TRL error model.
35
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Ten of the twelve error terms in the 12-term error model can be expressed directly
in terms of the error coefficients in Fig. 3.3 above. The relations are shown in Table 3.2
[38]. The other two error terms in the 12-term error model, forward and reverse isolation,
are not included in the 8-term error model, they are measured separately.
e 0I= £ 10e 0I
oo
f i , J2= e 23e 33
e>33= ^33
en f
®22» ® *22= ®22
e J2= e i0E 32
f i , 0/= e 0 ie 23
Table 3.2. Relations of the 8-term TRL error model coefficients and the 12-term error
model coefficients.
In the HP 8510 system, the eight error terms are obtained by measuring the TRL
standards, then those eight terms are converted to the twelve terms in the twelve-term
error model and used inside the network analyzer.
TRL calibration offers two methods to determine the reference planes. The
Reflect standard can be used to set the reference plane. In this situation, its parasitic
capacitance or inductance is required to be input in the network analyzer. The Through or
the Line standard can also be used to set the reference plane. In this situation, there is a
36
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requirement for the phase response of the Reflect standard that it must be within ±90°
from its nominal open or short value [38].
3.2 Review of De-Embedding Techniques
After calibration, the measurement reference plane is usually set to be at the end
of the coaxial connector or at the probe tips in on-wafer measurement setup. However, To
accurately characterize the microwave devices, the reference plane is most desirable if it
can be located at the device port. Thus some de-embedding procedures is needed to
remove the effects from the part between these two reference planes. Fig. 3.4 illustrate a
measuring setup where the desired reference plane is different from the measurement
reference plane. The effects of the two launches need to be de-embedded.
I
Launch
DUT
Launch
ABr desired reference plane
A’B’: measurement referent plane
The effects o f the two launches need to be de-embedded
Figure 3.4. Dlustration of a typical de-embedding application. The measurement
reference planes are at plane A’ and B’. After de-embedding, the performance of the
DUT (between reference plane A and B) is obtained.
37
]
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There are three major types o f de-embedding techniques:
Adapter-removal calibration
Adapter-removal calibration [41] removes the adapter effect at the calibration
stage, and it provides the most complete and accurate procedure for non-insertable
devices. This method uses a thru adapter that has the same connectors as the noninsertable DUT. However, for non-coaxial measurement environment, it is sometimes
difficult to build and use the thru adapter. In addition, the electrical length of the adapter
must be specified within one-quarter wavelength at each calibration frequency [41].
Model-Based De-Embedding Techniques
In the model-based de-embedding techniques, the effect of the adapters or fixtures
are represented by equivalent circuit models. Lumped-element networks or hybrid
element networks maybe used. The topology of the equivalent circuit models is
dependent on the physical configuration of the adapters or fixtures.
There are a lot of applications of this method. In reference [42], it is used to deembed the launch pad effect to get accurate measurement of the lumped-element inductor
and capacitor in 20-layer low temperature cofired ceramic (LTCC) materials in GHz
range. In references [43]-[44], a three step de-embedding method has been reported to
remove the influence of pad parasitics in silicon on-wafer BJT and MOSFET
38
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measurements. The lumped-element equivalent circuit model for the pads connecdng the
on-wafer probes and the transistors is shown in Fig. 3.5.
Z,
G3
Z,
DUT
I
G,
Figure 3.5. Equivalent circuit model of the parasitic series impedances and shunt
admittances of the contact pads and interconnections on Si wafer in [44].
The key problem in model-based de-embedding techniques is to find an accurate
equivalent circuit topology. The selection of the values for the components is another
difficulty although the optimization features in many CAD tools can provide useful
guidance.
Time-Domain De-Embedding Technique
The de-embedding can not only be performed in frequency domain, it can also be
performed in time domain. The time-domain de-embedding technique uses time-domain
39
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windowing to separates the DUT from the environment by selecting only the desired
reflections and eliminating the fixture and adapters effects. The conversion of frequency
domain reflection data to the time domain allows observation of each reflection on a time
base. The time-domain window has a greatest accuracy when broad-band measurements
are employed and windows of time are selected to include at least half wavelength
distance for the highest frequency involved [45]. The disadvantage of time-domain de­
embedding is that it provides inferior accuracy than frequency-domain de-embedding
techniques.
3.3 Analytical De-embedding Technique — Thru-Line-Line De-Embedding
Technique
The TLL method obtains the effect of the launches or the adapters by analytically
computing their S-parameters. It utilizes three de-embedding components: one Through
and two Lines (Linel and Line2). There is no reflect components used in TLL technique.
The construction method of the three components can be illustrated using the test
structure in Fig. 3.4. The thru and the two lines are built based on the launches, as shown
in Fig. 3.6. The Through consists of two launches or adapters back to back; the Linel has
a uniform 50 Q transmission line between the two launches, and in Line2 the length of
the uniform transmission line is twice of that in Linel.
40
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!
Launch
Launch
Through
r-
r*
|(L lr5 0 f t ) i
i Launch
Launch
Linel
r'
Launch
>
(2L„ 50 Q )
i
Launch
Line2
Figure 3.6. Construction of the three TLL components.
The algorithm of the TLL de-embedding utilizes the signal flow graphs of the
three components, which are shown in Fig. 3.7. To obtain the error model of the left side
launch ([A]), the TLL components are measured and their S-parameter are denoted as [a],
[P], and [x], for the thru, linel, and line2, respectively. The uniform transmission lines in
the middle of the two lines have a propagation constant y(jo)). Because the middle line is
designed to have an impedance of 50 £2. also because it has no discontinuity with the
launch, its reflection coefficients are assumed to be very small and neglected.
41
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(a) Signal flow graph of the Through
a.
1rs„
e*--- ► 5*
k
’r5= 5„ -i
(b) Signal flow graph of the Linel
8,2
<)
>— * ------<)
► ■
i r8»i
<'5 a
8„< k.
5a- k
>i\
4
^i j. - ■ 1
>— 4 ■
o
o
e—
d,
0
-0
a^
(c) Signal flow graph of the Line2
at
b,
51,
I
1S.. TA1SJ
• 5r_ 1
Launch
S|2
DUT
- I
k rs_
I
Sl2
h
s..‘
a2
Launch
(d) Signal flow graph of the original test structure
Figure 3.7. The S-parameters of the TLL components and the original test structure.
From the signal flow graph in Fig. 3.7, a set of equations to solve for [A]
obtained, as shown below:
au = S
n
SicSn
+
(1)
L—022*
§2l~
<*21=-
T— T (2 )
1 — 022 “
42
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<5,, is obtained as a solution of the equation
A&2: + fl&2 + A = 0 (5)
where A = a2 i(j3 u -au ): ,and fl = 2aiiT /Jn-aiO H /hi-au)iU u - a ii) - a :i2(;'n -a u )
And then 8 ,„ 5,, are obtained as
<5u = ctu—Sziccn (6)
Szi1 = 0 f2 l(L —& 2 !) (7)
8 12
= 821 (8)
After the S-parameters of the launch is calculated from equations (5)~(8), it can
be de-embedded from the original measured S-parameters. This procedure usually can be
done in many microwave EDA tools such as references [46]-[47].
I
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Chapter 4
Microwave and Millimeter-Wave PGA Packages
In this thesis, two kinds of area array packaging technologies (PGA and BGA) are
developed for microwave and millimeter-wave applications, and they are presented in
Chapter 4 and Chapter 5 respectively. In this chapter, the electrical analysis and
optimization of the PGA package and two designs of the vertical pin interconnection are
described in detail. The two pin interconnection designs are developed for low frequency
(10 GHz) applications and high frequency (up to 32 GHz) applications. The development
result is the first demonstration on applying the low cost digital PGA package technology
to the millimeter-wave frequency range.
4.1 Introduction
The cost and performance of microcircuits and microwave subsystems packaging
are crucial to a successful microwave product in the highly competitive electronics
market. Traditionally, deep cavity metal packages, such as the one shown in Fig. 4.1 are
used for high performance microcircuits packaging. These traditional packages are
usually expensive and bulky. Their manufacturing process typically starts with a
machined metal package with DC feed-throughs and RF glass-to-metal seals. Narrow
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channels are machined into the package, and they have a waveguide mode cut-off
frequency well above the normal operating frequencies so that good isolation can be
provided from one circuit to another. Numerous thin film circuits are attached to the floor
of the package using conductive epoxy. Various ICs are then attached in gaps between
the thin film circuits. Expensive RF connectors are attached to the sides of the package
which form edge launch transitions. Both the placement of the thin-film circuits and the
bonding for their connection have to be done manually, which add cost and reduce the
repeatability of the product [48]. Although this kind of packages can provide excellent
performance, it has the problem of high manufacturing cost and low I/O counts.
Figure 4.1. A traditional deep cavity metal package (from reference [48]). The lid is not
shown.
45
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Area array packaging provides a solution to address the need for high density UOs
of the microcircuits and microwave modules. The pin grid array (PGA) package is one
kind of area array packaging technology typically used in very large scale integration
(VLSI) systems with a lead count greater than 100 [19]. The PGA package can be
insertion-mounted to the sockets of the printed wiring board (PWB) using low cost
process control. This mature packaging technology is a potentially cost-effective solution
for RF modules to be mounted on multilayer substrates such as FR-4 and Getek. Several
groups have carded out the PGA characterization at low microwave frequencies.
Williams et. al. developed first order models for a digital PGA package up to I GHz by
using on-wafer probing techniques [49]. Goodman et. al. characterized of a high speed
PGA package using time and frequency domain techniques and reported a maximum 3dB bandwidth of 2.2 GHz for a signal line in the multi-layered PGA substrate [50].
However, there are very few reports on extending PGA technology to higher frequency
applications. Dove, Guth and Nicholson have pioneered the research on the development
and modeling of a PGA package for microwave microcircuits for test and measurement
instrumentation [48]. They reported a pin interconnect with better than 40 dB return loss
at 3 GHz and 15 dB return loss at 10 GHz. But for frequencies above 10 GHz, the
complex electromagnetic (EM) issues are severe, thus degrade the performance
dramatically.
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This thesis demonstrates that PGA technology can be designed to be a low cost
packaging solution for K-band (18-26.5 GHz) and even millimeter-wave frequencies. The
emphasis of the research in the PGA package is to design and optimize two different RF
vertical pin interconnection for 10 GHz and 32 GHz operations. The package architecture
is introduced in section 4.2. In section 4.3, EM analysis and optimization are performed
on the 10 GHz pin interconnect initially presented in [48]. A new interconnection
configuration is presented in section 4.4 that is demonstrated to have a better than 20 dB
return loss to 20 GHz. By combining full-wave analysis and time-domain reflectometry
(TDR) analysis, the 20 GHz interconnection is successfully optimized to be usable in 32
GHz applications.
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4.2 Microwave PGA Package Architecture
The PGA package is called the multichip integral-substrate PGA package solution
(MIPPS) [48]. A sample microcircuit in the package is shown in Fig. 4.2. The package
mainly consists of a metal baseplate, a single piece of ceramic substrate and a metal lid.
An exploded view of the package assembly is shown in Fig. 4.3.
(b)
Figure 4.2. (a) A microcircuit packaged in PGA package, (b) A complete PGA Package
with the lid.
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Baseplate
Epoxy Preform
Baseplate
Figure 4.3. The exploded view of the PGA package.
The baseplate is 0.095 inch long and made from 416 stainless steel to minimize
the thermal coefficient of expansion (TCE) mismatch with the ceramic substrate. It has a
slight recess on top to serve as the housing for the substrate. A 0.006 inch conductive
silver-filled epoxy preform is required between the baseplate and the substrate to insure
mechanical stability from -55°C to 150°C. Gold plated kovar pins of 0.020-inch-diameter
are vertically connected to the microstrip to form the RF transitions for the microcircuits.
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Figure 4.4. Prototype PGA with first generation soldered pin interconnection. In the
second generation interconnection, the solder is replaced with double wirebonds.
To test the performance, some prototypes with 50 Q microstrip substrates in the
PGA package are built, as shown in Fig. 4.4. On the backside of the substrate, a circular
area of the grounding metal around the pin is pulled back to serve as a ground relief
clearance between the pin and the ground. The vertical pins then go through the
machined holes in the metal baseplate where a short airline coax section is formed, as
shown in Fig. 4.5. In the first generation PGA interconnection, both the DC and the RF
pins are connected to the microstrip using a hemisphere of solder. The pins are all located
on a 0.10 inch grid for convenient assembly on PWB or testing in widely available PGA
testers. A 0.025 inch-thick alumina substrate is used in the prototype PGA structures. ICs
can be attached directly to the thick film or mounted on pedestals that come up from the
machined baseplate through laser-drilled cavities in the thick film. All bonded
interconnections are easily automated on this flat single substrate surface. The RF pin can
be plugged directly into the printed wiring board (PWB) if a low-RF-Ioss PWB is being
50
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used, or to a SMA connector (either barrel or flange mount) if the RF signal is to be sent
or received through a coaxial cable.
Ground relief clearance between the pin
and the ground plane on the back o f the
substrate.
Diameter o f the
baseplate through hole
(b)
Figure 4.5. RF pin goes through the microstrip substrate and the baseplate. Two
parameters affecting the electrical performance are also pointed out.
To obtain good isolation between the circuits on the ceramic substrate, hundreds
of conductive filled vias that connect the bottom ground plane of the circuit with the
ground metalization on the top are placed surrounding the RF signal lines, as shown in
Fig. 4.4. A lid with cavities below cut-off frequency for isolation is then epoxied directly
to the substrate using the conductive epoxy preform. When plugging the PGA into
sockets on a PWB, a metal waffle gasket is inserted between the PGA and the PWB to
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improve the isolation between the DC feed-throughs and the RF transitions. In addition,
the DC pins can be kept uncoupled from the stray RF energy using low-cost surface
mount components in the module and plugged into single-contact sockets on the PWB
[48]. This high degree of isolation is critical for the performance of some products such
as the 130 dB solid state step attenuator module manufactured with the PGA packaging
technology and used for a 4 GHz signal generator. Another example of PGA products is
an electronic calibration module that operates from 30 KHz to 9 GHz [48].
The PGA packaging architecture is more cost effective and more reliable than a
traditional deep cavity metal package. First, it uses much fewer expensive RF connectors
than traditional packages. Second, it applies low cost thick film processes and low cost
pin interconnections to microcircuit design. The PGA modules have all the microcircuits
fabricated on a single piece of substrate which provides significant cost advantages when
compared with the numerous thin film circuits used in traditional microcircuit modules.
A thick-film circuit that has both conductors and resistors printed on it generally costs
only 10% to 25% as much as a similar thin film circuit [48]. Lastly, the PGA package
takes advantage of automated assembly techniques for improved reliability over the
manual placement and line-up of thin film circuits in traditional packages.
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4.3 First Generation Interconnection for 10-GHz Application
In the first generation of the pin interconnect, the top of the pin is soldered to the
50 £2 microstrip lines by a 0.052 inch circular solder pad, which can provide sufficient
mechanical robustness, as shown in Fig. 4.4. For measurement purpose, the bottom of the
pin is inserted into a high performance SMA connector.
The HP85IOC Network Analyzer is used to obtain the S-parameters of the
prototype. A finite-element method (FEM) tool suitable for simulating arbitrary 3-D
geometry objects is used to perform EM modeling and analysis [33]. Fig. 4.6 shows the
measured and modeled performance of the interconnection. This soldered pin transition
exhibits a return loss better than 20 dB below 8 GHz. The return loss at 10 GHz is 15 dB
which is acceptable for many commercial applications. However, the return loss degrades
quickly above 12 GHz.
An EM analysis has been carefully performed on the interconnection by virtue of
the field displaying capability of the EM tool. It reveals some electromagnetic
phenomena which explains why the interconnection is not efficient for signal propagation
at high frequency. Since the vertical pin makes the field transition from the microstrip to
the coax line, two EM field view planes across the pin are chosen: one is inside the
alumina substrate and located 10 mil below the microstrip signal line, the other is across
the middle of the baseplate through hole, as shown in Fig. 4.7. The snapshots of the Efield at view plane 1 at 10 GHz and 26 GHz are shown in Fig. 4.8 (a) and (b),
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respectively. At 10 GHz, the E-field is much stronger at the pin side opposing the
microstrip, and it becomes more significant at 26 GHz. Furthermore, the E-field energy
tends to dissipate into the whole substrate at higher frequencies. Similar analysis is done
on view plane 2, for which the field distribution at 10 GHz and 26 GHz is shown in Fig.
4.9 (a) and (b) respectively. At both frequencies the E-field does not have a radially
symmetrical TEM wave pattern as it is supposed to support, and the asymmetry becomes
more severe at 26 GHz than that at 10 GHz. A TDR measurement has shown a capacitive
region near the solder ball which indicates that the solder ball is a major factor in limiting
the performance of the interconnect at higher frequencies.
-10
/-v
oa -20
■o
N—'
model
measure
-40
-50
0
5
10
15
20
25
30
Frequency (GHz)
Figure 4.6. Measured and modeled performance of the first generation PGA package with
soldered pin interconnection.
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view plane 1
view plane 2
9
Figure 4.7. 3-D model of the first generation interconnection for full wave EM analysis.
Two planes are chosen to perform full wave EM analysis. E-field is snapshot at two
different frequencies.
(a)
strong field at a
rino reoinn
(b)
strong field at a
nm» rp.tnon
Figure 4.8. E-field distribution at the view plane 1. The Full wave analysis shows that the
EM energy tends to propagate away from the interconnect at high frequency, (a) At 10
GHz. (b) At 26 GHz.
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Figure 4.9. E-field distribution at the view plane 2. (a) At 10 GHz. (b) At 26 GHz. (c)
Scale of the E-fteld.
From several experiments it is found that the performance of the interconnection
is sensitive to the geometrical parameters including the baseplate through hole diameter
and the circular relief in the ground plane of the alumina, as shown in Fig. 4.5. The 3-D
EM tool [33] helps to determine the optimal values for these two parameters. The
capacitance of the solder ball can be offset with some inductance by changing the two
parameters. Fig. 4.10 shows the dependence between the return loss and those two
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parameters at 10 GHz. The optimized diameter of the ground clearance is between 140
mil and 200 mil, and the diameter for the hole in the metal baseplate is 90 mil.
return loss in dB
-o
-IS
- 20.
Base plate thru hole diameter (mil)
(a)
return loss (dB) |
-to
3 .15
O -20
-25
backside ground clearance diameter (mil)
(b)
Figure 4.10. The relation between the return loss of the first generation PGA
interconnection and the baseplate through hole diameter and the backside ground relief
diameter. Optimization result shows that the return loss can be improved to 22 dB at 10
GHz.
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The optimization shows that the return loss of the transition can be improved to
22 dB at 10 GHz. A prototype transition with a 143 mil-diameter ground clearance is
fabricated according to this optimized data and its measurement data confirms the
optimization result. TDR from the measurement and simulation data also shows good
agreement, as shown in Fig. 4.11.
0.08
0.06
|
|
I
- - simulation
HP8510
0.04
0.02
0
| -0.02
fg
-0.04
-0.06
-0.08
■0.4 -0.3 -0.2 -0.1 0.0
0.1
0.2
0.3
0.4
0.5
Time (ns)
Figure 4.11. Measured and modeled TDR response of the optimized PGA soldered pin
interconnection matches very well.
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4.4 Second Generation Interconnection for 26.5-GHz Application
4.4.1 Design
A second generation pin interconnection has been developed to make the PGA
package usable for more applications that successfully improves the operating frequency
to 32 GHz. In the new interconnection, the solder ball is replaced with a short ribbon
bond as the electrical path from the microstrip to the pin, thereby the parasitic
capacitance of the solder is removed. The hole in the thick film alumina substrate is made
significantly larger than the pin to reduce capacitance, and the pin is placed eccentrically
in the hole to minimize the length of the ribbon bonds, as shown in Fig. 4.12. The cross
section view at the symmetrical plane of the interconnection is shown in Fig. 4.13.
Figure 4.12. Test structure of the second generation PGA interconnection with ribbon
bond.
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view plane 1
bonding wire
view plane 2
(a) 3-D EM model of the second generation PGA interconnection
(b)
Figure 4.13. (a) 3-D EM model for the second generation PGA interconnection, (b) The
pin is placed eccentrically in the substrate hole.
The metal baseplate is machined with a hole which is different from that in the
first generation interconnection. The top 19 mil of the hole is drilled to have a 46 mil
radius. This hole, together with the pin, forms a coax line with a characteristic impedance
of 50 Q. The hole is then made larger to accommodate a 50 Q hermetic seal which
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provides mechanical support for the pin as well as higher electrical performance. In the
prototype, the edge-to-edge distance from the pin to the ceramic is 10 mil, as shown in
Fig. 4.13.
-10
-20
CQ
■a
-30
model
CO
measure
-40
-50
0
5
10
15
20
25
30
Frequency (GHz)
Insertion loss
0
5
10
15
20
25
30
Frequency (GHz)
Figure 4.14. Measured and modeled return loss and insertion loss of the second
generation PGA interconnection.
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The HP 85 IOC Network Analyzer is used to obtain the performance of a
prototype interconnection. The 3-D EM model predicts the performance quite accurately.
Fig. 4.14 shows the return loss and the insertion loss. The measured return loss is better
than 20 dB from DC to 20 GHz, and the insertion loss is well below 1 dB to 26.5 GHz.
EM analysis is also performed on this second generation interconnection. Similar to that
in section 4.3, two view planes are chosen, one is 10 mils below the microstrip line in the
substrate, the other is across the 50 Q hermetic seal, as in Fig. 4.13 (a). The E-field
distribution is observed at 10 GHz and at 26 GHz. Fig. 4.15 (a) shows the E-field across
the substrate. Compared with that in the first generation interconnection in Fig. 4.8, the
interconnection seems to guides most of the field energy to propagate from the pin to the
microstrip. In the baseplate hole, the TEM wave pattern shown in Fig. 4.15 (b) is
dominating at both 10 GHz and at 26 GHz.
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(a) The E-field distribution across the view plane L (top) f=10 GHz, (bottom) f=26 GHz
(b) E-field distribution across the view plane 2. (top) f=10 GHz (bottom) f=26 GHz
Figure 4.15. Full-wave analysis of the second generation PGA interconnection (a) Efield distribution across the view plane 1. (b) E-field distribution across the view plane 2.
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4.4.2 Optimization of the Performance to 32 GHz
4.4.2.1 Comprehensive Analysis Method
The 3-D EM tool not only provides S-parameters for the package, it also serves as
a platform to optimize the microwave passive structures. The EM tool vividly presents
electrical and magnetic field distribution as well as current flow at any particular
frequency point, which gives insight to the physical mechanism of the package. TDR
analysis represents transient wave phenomena in a clear, natural and qualitative way and
allows the physics of propagation to be easily grasped and understood. TDR discloses the
impedance and parasitic inductance/capacitance at any point along the signal
transmission path. TDR is also very intuitive for equivalent circuit model development
for the package interconnects.
This thesis proposes a comprehensive analysis method which combines the EM
full wave analysis and time domain analysis. It is used to optimize the second generation
PGA interconnection. The comprehensive analysis method is shown in Fig. 4.16. In this
method, the package is first simulated using the 3-D EM tool, and the su of the [S] matrix
are converted to TDR data using the algorithm described below. After the most sensitive
region is determined from the time-domain data, the full-wave EM behaviors are
observed to understand the physical basis behind the electrical performance. As a result,
this region can be modified or redesigned and simulated by the EM tool. The optimized
geometry is recorded and used to build test structures. The comprehensive optimization
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method avoids the long “guess” period spent for recognizing the most important parts and
geometrical parameters in the structure, thus improving the design efficiency.
3-D model
FEM simulation
Full-wave analysis
41
—>
S-Darameters
\
Freauencv domain analysis
Optimized
solution
Fourier transformation
¥
Waveform analysis
TDR data
(a) In the simulation period.
3-D model
¥
Test structure
Z T 3
Frequency-domain
TDR Time-domain
measurement
measurement
\Z Does model match measurement ?
yes
r
.1 “
Done
Go back to
analysis procedure
(b) In the testing and measurement period.
Figure 4.16. The design routine using the comprehensive analysis method.
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4A.2.2 TDR from S-parameters
In this thesis, both TDR measurement and simulation are performed on the PGA
interconnects. The HP85LO Network Analyzer is applied for TDR measurement. The
simulated TDR data is obtained from the S-parameters of the EM model. The advantages
of transforming frequency-domain data (S-parameters) to the time domain include better
signal-to-noise ratio due to narrow-band measurements, the possibility of performing
error correction by measuring known standards, and freedom from time jitter and zerolevel drift [51]. In this section, the mathematical algorithm for generating the TDR from
the S-parameters will be explained.
Detlefson showed that the inverse Fourier transform of the scattering coefficient
s„(jQ)) equals to the s„ (t) that is the response to a pulse input [52]. As a result, when the
incident wave is a ,(t), the reflected wave b,(t) is the convolution of the input signal and
the s n(j(o) :
bx{t) = r l[su(jo)) * a l (ja )j\ = 5n (f) * ^ ( 0
(4.1)
As illustrated in Fig. 4.17.
The FFT algorithm requires that the frequency-domain data are given for both
positive and negative frequencies, i.e. s u(j(0 ) and s n(-jo)). In the convolution computation
the negative frequency response are the complex conjugate of the positive frequency
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data, i.e., sn(-ja)) = su'(+ja)), this is because the time-domain data are real values, and the
DFT of a real data series results in a complex conjugative series in frequency-domain.1
2
_ ...^_
^
*
i
a,(t)
—
S2t
i f su
S22 ^
m
&,(f) =
(/<»)]
Figure 4.17. The reflection wave in time domain is the convolution of incident wave and
stAt).
If there are N measured S-parameters in frequency domain with the maximum
frequency f max, then considering the N negative frequency points, after convolution there
will be 2N real values in time domain with the sampling time
In TDR analysis, the incident wave is usually a step function wave u(t), its DFT is
{l/j( 0 „ l/jOj
VjMx. -I/fas’ —rl/jaiy -7//<y,y. The TDR response to this step input has
a DFT series
{ s M /ja y ,, Sufojjj/joh, ....
Su u(Q)i)/(-j(0 t) } -
(4.2)
1 In Discrete Fourier Transform (DFT). if a series x(n) is real, then DFT[(x(n)] have the property o f X(-
jo ^ X 'C X ) [53].
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The inverse DFT of this series gives the TDR response. The implementation of this
algorithm is shown in the MATLAB code in Appendix B. In the code, a zero-padding
technique is applied to improve the accuracy of the TDR signal [53].
4.4.2.3 Result
The simulated su data of the second generation PGA interconnect is converted to
TDR response, as shown in Fig. 4.18. It has a very good correlation with the TDR data
from measurement and indicates good reliability of the successive analysis and
optimization. Fig. 4.18 also unveils an inductive region in the signal transmission path,
which is due to the ribbon bond interconnection.
Optimization of the interconnection can be done in two ways, either by reducing
the parasitic inductance of the ribbon bond or by providing a compensating capacitance.
To reduce the parasitic inductance, the ribbon bond can be made shorter, down to the
bonding process limitation of 20 mil. A 3-D model with this bond length still exhibits
great inductance. To compensate it by adding parasitic capacitance, the source of
compensating capacitance can be found from full-wave analysis. From Fig. 4.15 (a), the
E-field energy is highly concentrated near the shortest gap between the pin and the hole
edge, which demonstrates a possible capacitive region. By moving the pin closer to the
hole edge, the capacitance is increased. EM simulation shows that when the shortest gap
distance is as small as 4 mil, the inductive peak in TDR response is greatly suppressed
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and the return loss is better than 20 dB up to 26.5 GHz, as shown in Fig. 4.19 (a) and (b).
As the gap distance decreases further to 2 mil, the parasitic capacitance will be large
enough to completely compensate the inductance of the bond wire, and the return loss is
improved to be better than 20 dB from DC to 30 GHz, as shown in Fig. 4.20.
0.05
0.04
|
I
002
g
0.01
=
model
measure
0.03
0
I
-0.01
|
-0.02
(2 -0.03
-0.04
-0.05
-0.4
-03
-03
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Time (nS)
Figure 4.18. TDR responses from measurement and model of the second generation PGA
interconnection match very well. It provides a clear image that the dominant parasitic in
the interconnection is inductive.
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-♦ -4 mil gap
2 mil gap
-10
-20
CQ
-a
ij-
-30
Vi
-40
-SO
0
5
10
15
25
20
30
Frequency (GHz)
(a) Performance dependence on the distance between the pin and the edge of the hole in
the alumina substrate.
0.05
0.04
u
8u
c
_o
ou
c<u
cc
4 mil gap
2 mil gap
0.03
c
0.02
0.01
-
0.01
-
0.02
-0.03
-0.04
-0.05
-0.4 -03
-02 -0.1
0.0
0.1
02
03
0.4
03
Time (nS)
(b) TDR response shows that the inductance of the ribbon bond is suppressed when the
pin is moved closer to the edge of the hole.
Figure 4.19. Optimization result shows that the interconnection can achieve a better than
25 dB return loss over DC to 26.5 GHz.
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0
/■“N
-10
-0.4
-20
-
0.8
CQ
00
•o
'w '
-30
-
1.2
-40
-
1.6
-50
-2
-a
CN
Vi
0
5
10
15
20
25
Frequency (GHz)
30
35
Figure 4.20. A second generation PGA interconnection has a good electrical performance
to 32 GHz.
4.5 Conclusions
In this chapter, a novel millimeter-wave PGA package design for microcircuits
and microwave subsystems packaging are presented. Compared with the traditional deep
cavity metal packaging technologies, this packaging solution can reduce costs by more
than 50% and yet maintain the high performance required at RF and microwave
frequencies. Experimental and simulation results for the RF package interconnects have
shown a return loss better than 20 dB at 20 GHz, and additional optimization has
successfully extended it to 30 GHz. This is the first time that the PGA technology is
successfully applied for frequencies in K-band and above.
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Chapter 5
Millimeter-Wave BGA Packages
5.1 Introduction
BGA technology is attractive due to its near chip-scale packaging size, excellent
high frequency performance, and great capability to handle mixed signal. After its
successful application in digital systems since 1990s, BGA technology is expected to
play a bigger role for higher frequencies in microwave and millimeter-wave frequency
bands. At microwave frequencies, the BGA packages have found increasing applications
below 20GHz [54]-[57]. With the emerging wireless and optoelectronic communication
systems operating at millimeter wave frequencies, such as the local multi-point
distribution services (LMDS), there is an urgent need for low cost millimeter wave IC
packaging and printed circuit board (PCB) assembly technologies. Since BGA shares the
similar vertical interconnect scheme with flip chip, which has been reported to have
excellent performance to 120GHz [58], BGA should also be a viable packaging and
assembly technology for applications above 30GHz with a proper transition design. In
reference [59], a 31.5GHz ceramic BGA is reported with a IdB insertion loss in the two
port transitions.
72
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In this chapter, the development, electrical characterization, and EM analysis of a
36 GHz ball grid array package are presented. The TLL de-embedding technique
introduced in Chapter 3 is applied to remove the adapter effects and obtain accurate Sparameter measurement. A wide band circuit model for the BGA transitions is developed
from DC to 40 GHz with a hybrid circuit topology. Its accuracy in the whole frequency
range has been verified with experimental data. A 3-D model is constructed for the BGA
package, and the full wave EM analysis is applied to disclose limiting factors of the
package from physical aspect. Two significant EM phenomena are identified, including a
field leakage phenomenon and a radiation phenomenon. A pHEMT MMIC amplifier test
structure is built on the BGA, the measurement data has confirmed the validity of the
BGA package for up to 36 GHz application. This is the highest frequency that has been
reported for BGA package development.
73
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5.2 BGA Package Structure
The BGA package is constructed on a piece of 99.6% alumina substrate using
Via/Plane™ technology [59]. The package has two RF ports and six DC bias and control
ports, three on each side, as shown in Fig. 5.1. The package has a 6.35mm2 or 250 x 250
mil2 overall size, allowing a chip area of 3mm2. The design uses ungrounded coplanar
waveguide topology for the transmission lines on both the top and bottom sides of the
package substrate. Vias and slots are drilled in the substrate and filled with tungsten and
copper to make interconnection for CPWs on the two sides. The substrate thickness is
0.28 mm (11 mils) with a ball height of 0.28 mm. Thin film nickel and gold metal is
deposited to the top and bottom surfaces and then photo-pattemed and etched to form the
circuitry. Copper-silver ball preforms are brazed to the bottom surface and have a
hemisphere shape before attached to PCB. The center-to-center distance between the
signal and the grounding ball is 30 mil.
In most practical applications, BGA packages are mounted on PCB boards with
CPW transmission lines for RF I/O. To emulate the actual applications, the BGA package
in this thesis is mounted on a 15 mil thick alumina PCB with tapered CPW launches to
support the ground-signal-ground (GSG) on-wafer probes, as illustrated in Fig. 5.2. After
attachment to the board, the balls form a cylindrical shape with 11 mil height. A 50 £2
microstrip is mounted on the BGA and connected with the package through double
wirebonds, as shown in Fig. 5.3. The tapered CPW launch is 90 mil long, and is designed
74
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to have approximately 50 0 characteristic impedance along any cross section. In the RF
signal propagation path, the signal will go through ball interconnection, via
interconnection, wirebond interconnection, and several short planar transmission lines.
(a) Top view of the BGA package.
(b)
Bottom view of the BGA package.
Figure 5.1. Photograph of the millimeter-wave BGA package.
75
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A 'T o o tprint o f ball mterconnecfoir;
.^ ■
qgaggeasB!
Desired reference plane
reference plane for measurement
Figure 5.2. The PCB motherboard used to mount the BGA package. The reference planes
at the measurement and after de-embedding are illustrated.
desired reference plane
Figure 5.3. A BGA test structure with a 50 Q microstrip with double wire bond
interconnection to the package. The 90 mil adapters is an electrically long line and must
be de-embedded.
76
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5.3 Measurement and De-Embedding of the BGA Test Structure
At frequencies above 30 GHz, both the measurement and characterization for
BGA become more difficult than at low frequencies. First, at millimeter-wave
frequencies, the distributed-element effects associated with the big parts such as the balls,
the vias, and the short printed lines on the substrate, are significant, which requires a
more accurate modeling topology. Second, the measurement launches used to adapt the
on-wafer probes to the BGA can introduce complex parasitics to the measurement data at
millimeter-wave frequencies because it is a long and non-uniform transmission line.
When the electrical length of the launch is comparable to the wavelength, its transmission
line effects to the measurement data can not be removed using a model-based de­
embedding technique. In thepublished research literatures, modeling and characterization
of BGA packages are primarily performed below 20 GHz [54,56,57].
The CPW adapters in Fig. 5.3 have an electrical length of about A/4 at 15 GHz.
To de-embed them, the TLL technique in Chapter 3 has been applied to BGA application.
The design of TLL components is presented in section 5.3.1. The S-parameter of the
launch is calculated from the TLL components measurement data, which is shown in
section 5.3.2. The original measured S-parameter and the de-embedded S-parameters of
the BGA test structure are obtained from DC to 50 GHz, and presented in section 5.3.3.
77
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5.3.1 Design and Measurement TLL Components
The first step is construction and measurement of three TLL components. From
the BGA package test structure in Fig. 5.3, The CPW launches on the PCB designed to
adapt ground-signal-ground (GSG) probes are 90 mil long. Following the design
guidelines of the TLL technique, the three de-embedding components for the BGA
package are designed, as shown in Fig. 5.4.
The THRU consists of two back-to-back connected CPW adapters. The two
LINEs are constructed by adding a segment of a uniform CPW transmission line in the
middle of the THRU. The length of the CPW in LINE2 is twice of that in LINE1.
The TLL components are measured with HP8510 Network Analyzer and Cascade
Microtech’s 150pm pitch GSG probes after an OSLT calibration on the Cascade L01-190
ISS. The S-parameter matrices of the THRU, LINE1, and LINE2 are denoted as [x], PP],
and [Q, respectively, and are shown in Fig. 5.5 - Fig. 5.7.
l
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Figure 5.4: TLL components for de-embedding the coplanar adapters in BGA
measurements.
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0
CQ
S11 measurement
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S11 measuremen
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Frequency (GHz)
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u
-3
T3
3
.3
-4
00
S3
s
-5
c
S21 measurement
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Frequency (GHz)
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50
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120
u
60
0
S21
m easurem ent
-180
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Frequency (GHz)
40
50
Figure 5.5. Measured S-parameter of the THRU.
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0
S11 measurement
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u
•o
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S11 measurement
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a.
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0
I
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S21 measurement
4
5
10
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S
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Frequency (GHz)
40
50
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S21
m easurem ent
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40
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Figure 5.6. Measured S-parameters of Linel.
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0
S11 m easurem ent
10
<w -20
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S11 m easu rem en t
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i/i
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0
I
2
3
S21 m easurem ent
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Frequency (GHz)
180
120
eo
<u
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m easu rem en t
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Frequency (GHz)
Figure 5.7. Measured S-pararaeter of Line2.
85
j
i
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5.3.2 Obtaining the S-Parameters of the Launch
Using the TLL algorithm, the S-parameters of the CPW launch has been
computed from DC to 50 GHz from the measured S-parameters of the TLL components.
Shown in Fig. 5.8, port I of the launch is the narrower CPW end, and port 2 is the wider
CPW end. The magnitudes and phases of the s,„ s22, and s21 of the launch are shown in
Fig. 5.9. The launch does not show a linear insertion loss. Because the launch is a nonsymmetrical device, the su is not equal to the s22. Thus, the effect of the launch is
completely represented by the S-parameters. The result shows that the launch have an
insertion loss more than 1 dB at 38 GHz.
CPW launch
Figure 5.8. The launch whose S-parameters are solved using TLL algorithm.
86
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0
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■a -40
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00
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phase(S 11)
£ -120
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Frequency (GHz)
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0
S22
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phase(S 22)
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O
•u
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Frequency (GHz)
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0
10
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Frequency (GHz)
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u
2
00
o
■o
120
p h a se (S 2 1 )
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0
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20
30
Frequency (GHz)
40
50
Figure 5.9. S-parameters of the CPW launch. Note that this is an asymmetric structure, so
sll^s22.
i
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5.3.3 De-Embedding the Launch
Since the CPW launch effect is obtained in S-parameter format, it is then de­
embedded from the original S-parameter measurement data which is measured using the
HP 8510 Network Analyzer from 45 MHz to 50 GHz. Fig. 5.10 shows the comparison of
these two groups of S-parameters. The de-embedded S-parameters have different
reference planes from those in the measurement, so the groups of data have different
magnitudes and phases at all frequency points.
The benefits of de-embedding can be easily seen from the comparison in Fig.
5.10:
•
In the de-embedded S-parameters, the insertion loss due to the CPW launches
is corrected. This is shown in comparison of dB(s2l) plot in which the
magnitude of the de-embedded s21 is smaller at all frequency points.
•
The phase shift in both sn and s21 due to the CPW launches are significant, as
in Fig. 5.9. In the de-embedded data, both of them are corrected.
•
Correct amplitude of the return loss is obtained. It is interesting to see that the
CPW launches does not always make the return loss of the DUT worse at all
frequencies.
•
The resonance frequencies of the de-embedded su are shifted somewhat due
to the shift of the reference planes.
90
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The de-embedded S-parameter provides an accurate reference for equivalent
circuit development and 3-D FEM modeling. In section 5.4, the de-embedded Sparameters have been accurately modeled using a hybrid circuit model; in section 5.5, it
is compared with the 3-D FEM modeling S-parameters.
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m e asu re m e n t
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40
50
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s/a
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-90
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JO .
— measurement
— de-embedded
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0
m
T3
2
u)
O
O
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-4
u -
m e asu re m e n t
3
de-em bedded
'E
00
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22
00
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-o
90
m easurem ent
de-em bedded
0
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3
-90
-180
0
10
20
30
Frequency (GHz)
40
50
Figure 5.10. Comparison between the S-parameters of the orginal measurement data and
the de-embedded data. It can be seen that in the de-embedded data, the additional loss
and phase shift due to the launches are removed.
92
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5.4 Equivalent Circuit Model for the BGA Transition
The de-embedded S-parameters represent the combined effects from the BGA ball
interconnects, via interconnects, the microstrip, the double wirebond, and some short
CPW lines. An equivalent circuit model is successfully developed to model these
components and transitions using hybrid components in the frequency range from DC to
40 GHz, as shown in Fig. 5.11.
The transmission line segments, and the double-wire bond, are modeled using
corresponding transmission line models in the CAD tool [46]. For the ball and the via/slot
interconnection inside the BGA, a combination of lumped element LC circuits and
transmission line model is used to model them. The lumped element circuits are used to
represent the self and mutual inductance and capacitance associated with the vertical
interconnects, and the transmission line is to account for the distributed element effect of
the balls and vias at high frequencies. By combining these two circuit models together, a
wide band equivalent circuit model can be obtained for the complete BGA structures with
an easy topology.
93
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L->,*
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(a) Equivalent model in MDS circuit from the PCB to the microstrip. The parameters of
the CPW1 are: signal width=23 mil, space=6.8 mil, length=41 mil,; the parameters of the
wirebonds are: Iength=L2 mil, diameter=0.7 mil; the parameters of the microstrip line
are: length=l34 mil, width=10 mil, substrate st=9.6, tan 8=0.0002, substrate height=10
mil.
50 Q transmission line, length=ll mil
Lt: 7 pH
0-
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(b) Hybrid Tt-network and transmission line model for the balls.
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n r v Y \
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T
(c) Hybrid L-network and transmission line for the via and slot transitions.
Figure 5.11. The hybrid circuit model for the BGA transitions.
94
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For the ball interconnects, since BGA and flip chip have similarities in the
interconnection configuration, a IT-network is applied in ball modeling as it is often
adopted for flip chip interconnections [60]-[61]. In addition, in order to account for the
distributed-element effects of the balls, a segment of 50 SI transmission line with the
length equal to the ball height is combined with the n-network, as shown in Fig.5.11 (b).
For the via and slot transition, an L-network is used; similarly to ball modeling, another
segment of 50 Q transmission line with the length equal to the via height (11 mils) is
added to the L-network to represent the distributed element effect of the via/slots, as
shown in Fib. 11(c). In the LC circuits, the capacitance represents the effect from the
overlapping area of metalization on the layers, while the inductance accounts for the self
and mutual inductance of the balls and vias.
The improved hybrid circuit model predicts the test structure performance very
accurately from DC up to 40 GHz. The de-embedded measurement S-parameters in Fig.
5.12 shows the highly correlated su magnitude and phase response and s2i phase between
the modeling data and the de-embedded measurement result. The discrepency in s2I
magnitude is due to the fact that the wirebond model and the microstrip model have a
much lower loss than in the actual implementation, thus the model leads to a lower
magnitude in s^ than the de-embedded measurement result.
95
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The TLL de-embedding technique is a critical development for modeling this
BGA test structure. This is because the launch is not a uniform transmission line and its
phase response is difficult to be accurately modeled.
0
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30
35
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C
3
0
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model
de-embedded
-90
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5
25
10
30
35
40
Frequency (GHz)
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T<3u
3
’£00
s
model
- - - de-embedded
mi
5
10
15 20 25
Frequency (GHz)
30
35
40
180
model
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a.
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35
40
Frequency (GHz)
Figure 5.12. Very good correlation between the modeled S-parameters and de-embedded
measurement S-parameters.
From the hybrid model, it is found that a single transition, including one ball
transition, one via/slot transition, and related CPW lines on the PCB and the package, has
97
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a low insertion loss within 0.3dB over the whole frequency range to 40 GHz, as shown in
Fig. 5.13. In the original package, the insertion loss of ldB for two transitions at 3 1.5GHz
is presented [59]. The new package thus shows a great improvement in performance.
-10
-20
CQ
-o
A d B (S ll)
• dB(S2l)
Vi
-40
-50
0
10
20
30
Figure 5.13. The performance of a single transition shows that it has a low insertion loss
within 0.3dB to 36GHz and a reasonable return loss.
5.5 Application of the Package
A 20-40GHz wide band pHEMT MMIC amplifier is mounted on a BGA package
similar to the one described above using conductive epoxy, with the photo shown in Fig.
5.14. The mesh-bond serves as the RF interconnection between the package and the
MMIC. The measurement for the assembly is performed using a HP8510 Network
Analyzer and the result is shown in Fig. 5.15 where the gain of the bare chip is also
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shown. The comparison has confirmed that the BGA is a low loss package and it is
applicable for millimeter wave frequencies.
Figure 5.14. Test structure is built with a pHEMT MMIC amplifier packaged in the BGA.
20
16
%
12
8
— packaged
■ unpackaged
4
0
20
25
30
Frequency (GHz)
35
40
Figure 5.15. The gain of the amplifier is comparable to that of the bare MMIC chip. The
degradation includes the effect of the mesh bond.
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5.6 FEM Analysis of the BGA Package
In this section, the finite-element method modeling and analysis are applied to the
BGA test structure to study its EM behavior. The 3-D modeling result of the BGA
constructed using the FEM tool [33] shows a very good correlation with the de-embedded
measured S-parameter data. Electrical field distribution patterns are obtained from full
wave analysis at several critical frequencies for further optimization and redesign.
5.6.1 Modeling Strategy
The BGA test structure in Fig. 5.16 have symmetry along the xx’ axis and yy’
axis, which reduces the complexity of the 3-D model. A symmetrical H plane [33] is
applied to the cross section at xx’ so that only half the structure is needed in the model.
That half structure is further split into two halves because of the symmetrical plane at the
yy’ axis. The final model only has one quarter of the BGA test structure, as shown in Fig.
5.17.
y
f
Figure 5.16. The BGA test structure for EM modeling.
100
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Port2:
Microstrip
port
Figure 5.17. The 3-D model of the BGA structure for EM analysis. Only one quarter of
the real structure is necessary to put in the model due to the symmetry of the BGA.
The S-parameters from the above model is from the PCB port to microstrip port.
To obtain the S-parameters of the whole structure, two S-parameters of the quarter
101
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structure are cascaded with their microstrip ports connected, as shown in the circuit
below.
Figure 5.18. The circuit used to obtain the S-parameters of the whole structure. [A] is the
S-parameter of the quarter model, [A’] is the [A] with port number exchanged.
In order to get an accurate simulation result, the model in Fig. 5.17 has included
almost all the details related to the RF transition, and it is drawn very carefully according
to the real design. In the 3-D model, all three grounding balls, the additional grounding
vias and via slots are included in the model, as shown in Fig. 5.19 and Fig. 5.20. The
wirebond connecting the microstrip to the BGA package is represented with a 3-D
bended line segment to mimic the wirebonds in the real structure, as shown in Fig. 21.
102
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Figure 5.19. Part of the 3-D model showing the signal ball (half cylinder) and three
grounding balls.
Figure 5.20. Transparent view showing the signal via (in the circle) and the grounding
via slot. The three additional grounding vias and the thermal via slot are also included in
the model.
103
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Figure 5.21. The wirebond model is created using 3-D bended solid line segments.
5.6.2 Modeling Result
The 3-D BGA model in Fig. 5.17 has been simulated from 1GHz to 45 GHz with
1 GHz increment. The simulated half BGA structure is shown in Fig. 5.22.
The S-parameters of the complete BGA structure are obtained by using the
method illustrated in Fig. 5.18. Because the port 1 of simulated S-parameters are deembedded to the BGA edge, the reference plane at port 1 is the same as in the deembedded measurement S-parameters. The simulated S-parameters from the 3-D model
predict the BGA performance very well, as seen from the good match between the
modeled S-parameters and the de-embedded S-parameters, both in magnitude and phase,
as shown in Fig. 5.23. The modeled insertion loss is slightly lower because some planar
104
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components such as the CPW lines and microstirp lines are modeled using pure 2-D ideal
metal which causes no metalization loss.
180
-to
120
60
s, -20
so
■uo 0
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-60
S11
3
a
.c -120
a. •180
*5 -40
co
I -50
sn
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Frequency (GHz)
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40
45
0
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IS 20 25 30
Frequency (GHz)
35
40
45
35
40
45
35
40
45
180
120
■o
S21
so
13
u
*»
-60
S21
J -120
S -to
ft. -|80
0
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10
15 20 25 30
Frequency (GHz)
35
40
45
0
5
10
15 20 25 30
Frequency (GHz)
180
-10
3 -20
120
-S22
1 -30
S 22
o
cb -40
es
2
-60
cs *120
JS
-180
-50
0
5
10
15 20 25 30
Frequency (GHz)
35
40
45
0
5
10
15 20 25 30
Frequency (GHz)
Figure 5.22. Simulated S-parameters of the BGA model in Fig. 5.17. The port 1 is the
CPW on the PCB, and the port 2 is the microstrip.
105
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0
CO
-10
■a
co
43j
'S
ao
a
-20
-30
-40
EM model
de-embedded measure
-50
15
20
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Frequency (GHz)
35
40
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180
u
120
800
u
■o
CO
u91
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15
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Frequency (GHz)
25
30
35
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- - - EM model
■i
de-em bedded measure
106
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0
2
CQ
•a
M
u
•a
3
'c00
(3
4
CO
EM model
6
de-embedded measure
8
-10
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Frequency (GHz)
35
40
45
180
120
ri
CO
.e
a.
-60
-120
-180
0
5
10
15
20
Frequency (GHz)
25
30
35
40
45
- - - EM model
■de-embedded measure
Figure 5.23. The S-parameters from the EM model and the S-parameters from
measurement. The very good correlation in the ragne from 45MHz to 45 GHz shows the
validity of the model.
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5.6.3 EM Analysis of the BGA Package
The high accuracy of the simulated S-parameters have confirmed the validity of
the model. Based on the model, more EM analysis have been performed on the package
to understand the electrical behavior from the physical point of view. In this section, two
EM phenomena in the BGA package at high frequencies are discovered, one is the field
leakage phenomena, the other is radiation phenomena.
5.6.3.1 Field Leakage Phenomena
The coordination system of the EM model is shown in Fig. 5.24. Two view planes
are selected. The view plane 1 is at y=4 mil that is parallel to the ZX plane and across the
wirebond; the view plane 2 is at z=17 mil that is across the middle of the BGA substrate,
which is shown as the dotted lines.
The field leakage can be shown from the E field pattern at view plane 1. Fig. 5.25
shows the E field pattern at 32.8 GHz and 45 GHz. Compare the field patterns in Fig.
5.25(a) and (b), it can be seen that there is field leakage at the comer of the BGA ball
interconnects.
The field leakage can be seen more clearly at view plane 2. This plane is at the
middle of the BGA substrate, crossing the vias and via slots. As shown in Fig. 5.26, the E
field at 45 GHz has two strong stray field regions outside of the three grounding vias.
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Z
View plane 2
Figure 5.24. The EM model with the coordination. The (0,0,0) point is at the one of the
comers of the substrate (the big dot in the figure). The view plane 1 is at y=4 mil and the
view plane 2 is at z=17 mil.
(a) E field at view plane 1 at 32.8 GHz.
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Ball
interconnect
(b) E field at view plane I at 45 GHz.
Figure 5.25. E field pattern at view plane 1 (y=4 mil). It can be seen that there is some
field leakage near to the ball interconnection
V
Field leakage out of transmission path
(a) E field at view plane 2 at 32.8 GHz.
(b) E field at view plane 2 at 45 GHz.
Figure 5.26. E field pattern at view plane 2 (z=17 mil). It can be seen in (b) that at high
frequency some field energy is leaking out of the transmission path into the BGA
substrate.
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To find the reason of the leakage, EM analysis is performed at more view planes
at 45 GHz. Fig. 5.27 (a) shows the E field pattern at a plane which is beneath view plane
2 and across the balls, no leakage comes from the balls. Similarly, Fig. 5.27 (b) shows the
E field at a plane above the view plane 2 on the surface of the BGA substrate. The field is
propagating along the planar CPW line, and there is no leakage present.
(a) E field on a plane z=5 mil which is beneath the view plane 2 at 45 GHz.
(b) E field on a plane z=22 mil which is above the view plane 2 at 45 GHz.
Figure 5.27. E field patterns at two different planes. Both of them do not show the
leakage phenomena.
From these figures, the leakage wave seems to have no connection with the ball
and via interconnections. From Fig. 5.26 (b), the leakage wave is likely to be coupled
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from the part of the CPW modes on the PCB launches to inside the BGA substrate, as
shown in Fig. 5.28.
Field leakage
Figure 5.28. Part of the CPW wave on the PCB is coupled into the leakage region. This E
field pattern is at view plane 2 at 45 GHz, same as Fig. 5.26 (b).
5.6.3.2 Radiation Phenomena
The BGA package has a bad insertion loss around 40 GHz, as shown from both
the EM simulation and measurement in Fig. 5.23. The EM analysis has been used to And
out the reason behind it. The EM analysis is performed at 40.4 GHz, which is selected
from the simulated S-parameter.
A strong radiation from the bottom of the PCB board to the space, as shown in
Fig. 5.29. The PCB on which the BGA package is mounted is a 15 mil thick alumina
board with no ground plane on the back. The space below the PCB is filled with air. The
E field in Fig. 5.29 is snapshot at the symmetry plane of the BGA package (y=0 plane).
Fig. 5.29 (a) shows that the radiated field is even much stronger than that of the
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transmitted wave, as indicated from the color. Fig. 5.29 (b) shows the electrical field line
pattern of the radiated field.
Radiation field
(a) E field magnitude pattern across the BGA symmetry plane (y=0 plane). The radiated
field is very strong.
(b) The E field line pattern of the radiation field.
Figure 5.29. Radiation phenomena of the BGA package around 40 GHz.
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This radiation field does not exist at other simulated frequency points including
9.5 GHz, 13.5 GHz, 19.4 GHz, 25 GHz, 28.2 GHz, 32.8 GHz, and 45 GHz. To study
more about the radiation field at 40.4 GHz, a view plane 5 mils below the PCB board is
selected, its position is z=-20. The E field pattern is shown in Fig. 5.30 (a), and the E
field line is shown in Fig. 5.30 (b). From the pictures, the radiation field is propagating in
a radially symmetrical pattern into the air space. The center is right below the signal ball.
(a) E field pattern at view plane in the air space (z=-20) below the PCB.
(b) E field line pattern of the radiation field in (a).
Figure 5.30. Electrical field distribution and field line pattern of the radiation wave
across the plane z=-20 mil.
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As shown in Fig. 5.31, the leakage phenomena also exists at 40.4 GHz. The
picture is snapshot across the middle of the BGA substrate or z=l7 mil. The combined
effects of the radiation and leakage have made the electrical performance around 40 GHz
much worse than in other frequency regions.
Leakage
field
Figure 5.31. Leakage phenomena at 40.4 GHz.
From Fig. 5.29 and 5.30, it is seen that the center of the radiation field is right
below the signal ball. Perhaps the way the balls are distributed and mounted on the board,
and the geometry of the ball and the PCB, have caused the radiation. More study about
the radiation field is needed to eliminate it. After the leakage and radiation are removed,
the package is expected to have a much better electrical performance to 45 GHz.
5.7 Conclusions
In this chapter the modeling and characterization results of a 36 GHz BGA
package are presented. A novel Through-Line-Line (TLL) de-embedding technique has
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been developed for error correction of electrically large (over quarter-wavelength)
adapters. It applies an algorithm that analytically computes the S-parameters of the
measurement launches. The TLL technique has been successfully applied to obtain the
accurate S-parameter measurement of the BGA. A hybrid equivalent circuit model of the
BGA transitions has been improved to include the distributed-element effects of the
vertical interconnects in the BGA. The model is verified with the de-embedded
measurement data of the test structure in the wide frequency range from DC to 40 GHz.
Finally, the package is analyzed using the electromagnetic tool, two important
phenomena are identified: leakage and radiation, which are believed to hinder
performance at high frequencies.
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Appendix A: Matlab Code for the Thru-Line-Line De-Embedding
Technique
% The source data should be in Touchstone format
% # GHz S RI R50
%
% thru.txt, linel.txt, line2.txt contains
% no"# GHz S RI R 50". Only S-parameters
clear;
fsa=fopen ('thru.txt', V);
fsb=fopen ('linel.txt', V);
fsc=fopen (1ine2.txt', 'r');
fsd=fopen ('resl', 'at');
fse=fopen ('res2', 'at');
% in res2, portl, 2 are exchanged from that in resl.
sa=zeros(9,l);
sb=zeros(9,l);
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sc=zeros(9,l);
% N: number of freq points.
N=201;
% si la_vec contains si l(or s22) of the thru
% s2la_vec: s21 o rs l2 of the thru
% sllb , s21b: sll/s22 and s21/sl2 of the linel
% s llc , s2lc: sll/s22 and s21/sl2 of the Iine2
si la_vec=zeros(N,l);
s21a_vec=zeros (N, 1);
si lb_vec=zeros(N,l);
s21b_vec=zeros(N, 1);
s 1lc_vec=zeros(N, 1);
s21c_vec=zeros(N, 1);
f=zeros(N,l);
dll=zeros(N,i);
d22=zeros(N,l);
d21=zeros(N,l);
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d22_l=zeros(N,l);
i
d22_2=zeros(N,l);
% d ll, d22, d2l: [s] of the launch.
% because there are 2 solutions for d22, they are stored in
% d22_l, d22_2
templ=zeros(N,l);
% e_gammaLl/2: store the solution forexp(+ gamma*L)
e_gammaLl=zeros(N, 1);
e_gammaL2=zeros(N, 1);
e_to_minus_2gammaL=zeros(N, 1);
for k=l: N
tsa=fscanf(fsa, ’%lg %lg %lg %lg %lg %lg %lg %lg %lg', 9);
tsb=fscanf(fsb, ’%lg %lg %lg %lg %lg %lg %lg %lg %lg’, 9);
tsc=fscanf(fsc, '%lg %lg %lg %lg %lg %lg %lg %lg %lg’, 9);
f(k)=tsa(l);
% in Touchstone file, the data is in order of s ll , s21, s!2, s22.
% a l l can be s l l or s22 of the device.
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%al l=tsa(2)+i*tsa(3);
al l=tsa(8)+i*tsa(9);
a21=tsa(4)+i*tsa(5);
%bl l=tsb(2)+i*tsb(3);
bll=tsb(8)+i*tsb(9);
b2l=tsb(4)+i*tsb(5);
%cl l=tsc(2)+i*tsc(3);
cll=tsc(8)+i*tsc(9);
c2 l=tsc(4)+i*tsc(5);
slla_vec(k)=all;
s21a_vec(k)=a21;
% see equations
a=a21;
b = b ll-all;
c=c11-all;
A=a*b*b;
B=2*a*a*b+b*b*c-a*a*c;
%%% solve for d22
temp=roots( [A, B, A ]);
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d22_l(k)= temp(l);
d22_2(k)=terap(2);
sllb_vec(k)=bll;
sllc_vec(k)=cli;
% solve for exp(+ gamma * L ); see equation
temp=roots( [1, -(b21/c21+b21/a21), 1]);
e_gammaLl(k)= temp(l);
e_gammaL2(k)= temp(2);
% some phase are negative value, I force it to be positive.
% egammal is what I need, since abs(egammal) > 0
% found that the e_gammaLl is the right one because
% it’s absO > 0
if imag(e_gammaLl(k))<0
e_gammaLl(k)=conj(e_gammaLl(k));
end
% solve forexp(-2*gamma *L)
e_to_minus_2gammaL(k)=(a*temp(2)+b)/(a+b*temp(2))/temp(2);
%plot(f,20*logl0(abs(d22_l)));
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%title('d22_r);
%pause;
%plot(f, 180*(angle(d22_l)/pi));
%pause;
plot(f, 20*log 10(abs(d22_2)));
titie ('d22_2');
pause;
plot(f, 180*(angle(d22_2)/pi));
pause;
d22=d22_2;
% The plot shows that d22_l is not usable,
% and that d22_2 is the one that we need!
%%% solve for d ll
d l l=s 1la_vec-s2 la_vec.*d22;
plot(f, 20*logl0(abs(dl 1)));
titleCdll');
pause;
plot(f, 180*(angle(dll)/pi));
pause;
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%%% solve for (121
temp l=s2 la_vec.*( l-d22.*d22);
ang=unwrap(angle(temp 1));
% need to unwrap the phase because of the sqrt() function,
for k=l:N
d21(k)=sqrt(abs(temp l(k)))*(cos(ang(k)/2)+i*sin(ang(k)/2));
end
plot(f,20*logl0(abs(d21)));
title('d21’);
pause;
p!ot(f, 180*(angle(d21)/pi));
pause;
%%% solve for exp(-2gamma*L)
plot(f, abs(e_to_minus_2gammaL), ’gr);
titIe('exp(-2GammaL)');
pause;
pIot(f, angIe(e_to_minus_2gammaL)* 180/pi, 'gO;
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pause;
%%% solve for exp(+gamma*L)
plot(f, abs(e_gaxnmaL 1) ,V);
title('magnitude of e_to_plus_gammaLr);
grid;
pause;
plot(f, angle(e_gammaLl)* 180/pi, 'r ');
tide('phase of e_to_plus_gammaLr);
grid;
pause;
%%% save the [S] for the launch
fork=l:N
fprintf (fsd, '%g %g % gf(k),real(dll(k)),im ag(dll(k)));
fprintf (fsd, '%g % g ', real(d21(k)),imag(d21(k)));
fprintf (fsd, '%g %g real(d21(k)),imag(d21(k)));
fprintf (fsd, ’%g % g ', real(d22(k)),imag(d22(k)));
fprintf (fsd, W);
fprintf (fse, ’%g %g % g ', f(k),real(d22(k)),imag(d22(k)));
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fprintf (fse, ’%g % greal(d21(k)),imag(d21(k)));
fprintf (fse, '%g %greal(d21(k)),imag(d21(k)));
fprintf (fse, '%g % g', real(dl l(k)),imag(dl l(k )));
fprintf (fse, V );
end
fclose (fsa);
fclose (fsb);
fclose (fse);
fclose (fsd);
fclose (fse);
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Appendix B: Matlab Code for Obtaining TDR Response from Su
%clear;
file_sll=fopen ('sll.cit', 'r1);
file_s 1l_fft=fopen ('sll_fft.dat’, 'at1);
file_freq=fopen('freq.cit', V);
fmax=40e9; %highest frequency
FreqPoints=800;
%in original S-paramters
a=zeros(2,l);
si l=zeros(FreqPoints,l);
f=zeros(FreqPoints,l);
s 1l_tdr=zeros(2*FreqPoints, 1);
for k=l: FreqPoints
a=fscanf(file_s 11, '%lg,%Ig', 2);
b=fscanf(file_freq, '%lg', 1);
f(k)=b;
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sll(k)=a(l)+i*a(2);
j
i
end
jomega=f*i*2*pi;
s 1l_tdr( 1:FreqPoints)=s 11 Tjomega;
for k=FreqPoints+l: 2*FreqPoints
s i l_tdr(k)=conj(sl l_tdr(2*FreqPoints+l-k));
end
si l_tdr_norm=sl l_tdr*2*fmax;
s 1 l_fft=ifft(s 1l_tdr_norm);
%s 1l_fft=ifft(s 11); % this leads to a delta- response, not the step
% input response.
i
% (Since the response of the step function (TDR) is a real function,
% the FFT of the response should be conjugatively symmetry
i
for k=l:2*FreqPoints
fprintf (Sle_sl l_fft, ’%g,%g ’, abs(s 1l_fft(k)),angle(s 1l_fft(k))* 180/pi);
fprintf (file_sll_fft, W );
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end
fclose (file_sl I);
fclose (File_sl L_fft);
fclose (file_freq);
plot(20*log 10(abs(s 11)));
grid;
pause;
plot(abs(sl l_fft));
grid;
pause;
plot(angle(sl l_fft)* 180/pi);
grid;
pause;
p!ot(reaI(sl l_fft));
grid;
pause;
plot(real(s 1l_fft( 1:50)));
grid;
pause;
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plot(imag(s 1l_fft( 1:50)));
grid;
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pause;
.!
N=4; % O-padding in Frequency domain. 4x times of points.
% N=2,3,4,5, any integers.
|
ExpandN=N*2*FreqPoints;
si l_tdr_normN=zeros(ExpandN,l);
for k=0: FreqPoints
s 1l_tdr_normN(k+1)=s 1l_tdr_norm(k+1);
end
for k=FreqPoints+2:2*FreqPoints
s 1l_tdr_normN(ExpandN-2*FreqPoints+k)=s 1l_tdr_norm(k);
end
%windowing
i
L=FreqPoints*1.9; % L is the window resolution
% 1.9 seems to be pretty close to "8510" in MDS.
win_ham=hamming(L); % hamming window, help hamming
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window=zeros(2*N*FreqPoints, 1);
window( 1:L/2)=win_ham(L/2+1: L);
window(2*N*FreqPoints-L/2+1:2*N*FreqPoints)=win_ham( 1:L/2);
plot(abs(sll_tdr_normN), 'o-');
grid;
pause;
pIot(real(sl l_tdr_normN),'o-');
grid;
pause;
plot(imag(sl l_tdr_normN),'o-');
grid;
pause;
plot(reaI(ifft(s 1l_tdr_normN)),’o-');
grid;
pause;
plot(imag(ifft(sl l_tdr_nonnN)),'o-');
grid;
% after windowing
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plot(abs(s 1l_tdr_normN.*window));
grid;
pause;
plot(real(sl 1jdr_normN.*window));
grid;
pause;
plot(imag(sl l_tdr_normN.*window));
grid;
pause;
plot(real(ifft(s 1l_tdr_normN.*window)));
grid;
pause;
plot(imag(ifft(s 1 l_tdr_normN.*window)));
grid;
s 1l_fft_N=N*ifft(s 1l_tdr_normN.*window);
%s I l_fft_N=N*ifft(s 1l_tdr_normN);
%time scale. T is the sampling time in ps.
T=lel2/2/fmax/N;
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time=zeros(2*N*FreqPoints, 1);
for k=l: 2*N*FreqPoints
time(k)=k*T;
end
plot(time(l:100), real(s Ll_fft_N( 1:100)), ’-o');
grid;
pause;
%now, plot the TDR in a shifted order.
time2=time-N*FreqPoints*T;
sll_fft2_N=sll_fft_N;
s 1l_fft2_N( 1:N*FreqPoints)=s 1l_fft_N(N*FreqPoints+l: 2*N*FreqPoints);
s 1l_fft2_N(N*FreqPoints+l: 2*N*FreqPoints)=s 1l_fft_N( 1: N*FreqPoints);
span=I00;
x=time2(N*FreqPoints-span/2: N*FreqPoints+span);
y_real=real(sl I_fft2_N(N*FreqPoints-span/2: N*FreqPoints+span));
y_imag=imag(sl l_fft2_N(N*FreqPoints-span/2; N*FreqPoints+span));
plot(x, yjm ag, Tco-');
grid;
pause;
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plot(x, y_real, '-o’);
grid;
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References
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Publications Resulting from Thesis Work
1. Hongwei Liang. Joy Laskar, Manos Tentzeris, and Mike Hysiop, "Electrical
Modeling and Characterization of a Ball Grid Array Package to 40 GHz Using a
Novel Through-Line-Line De-Embedding Technique”, submitted to the IEEE
Microwave and Wireless Components Letters, July 2000.
2. Hongwei Liang. Joy Laskar, and Mike Hysiop, "A DC-to-50 GHz Wide Band DeEmbedding Technique for BGA Measurements”, 10th IEEE Topical Meeting on
Electrical Performance of Electronic Packaging Digest, Boston, MA, October 2000.
3. Hongwei Liang. Joy Laskar, Heidi Barnes, and Don Estreich, “Design and
Optimization for Coaxial-to-Microstrip Transition on Multilayer Substrates”, IEEE
MTT-S IntT Microwave Symposium, Phoenix, AZ, May 2001.
4. Hongwei Liang. Heidi Barnes, Joy Laskar, and Don Estreich, "Application of Digital
PGA Technology to K-band Microcircuits and Microwave Subsystem Packaging",
IEEE Trans. Microwave Theory and Techniques, Vol. MTT-48, no. 12, pp. 26442651, Dec. 2000.
142
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5. Joy Laskar, Manos Tentzeris, Albert Sutono, Hongwei Liang. Nathan Bushyager and
Kutae Lim, “Next Generation Packaging Architectures for Highly Integrated Wireless
Systems”, European Microwave Conference, Paris, France, October 2000.
6. Hongwei Liang. Joy Laskar, Heidi Barnes, and Don Estreich, "Application of Digital
PGA Technology to 20GHz Microwave Packages", IEEE International Microwave
Symposium Digest, Boston, MA, vol. 2, pp. 1051-1054, June 2000.
7. Hongwei Liang. Joy Laskar, Mike Hysiop, and Ram Panicker, "Development of a
36GHz Millimeter-Wave BGA Package", IEEE International Microwave Symposium
Digest, Boston, MA, vol. I, pp. 65-68, June 2000.
8. Hongwei Liang. Joy Laskar, Mike Hysiop, and Ram Panicker, "A Novel De­
embedding Technique for Millimeter-wave Package Characterization", 54thAutomatic
RF Technique Group (ARFTG) Digest, Atlanta, GA, pp. 137-144, Dec. 1999.
9. Hongwei Liang. Albert Sutono, Joy Laskar, and W.R. Smith, "Material Parameter
Characterization of Multilayer LTCC and Implementation of High Q Resonator",
IEEE International Microwave Symposium Digest, Anaheim, CA, pp. 1901-1904,
June 1999.
143
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10.Daniela Staiculescu, Hongwei Liang. Joy Laskar, and John Mather, "Full Wave
Analysis and Development of Circuit Models for Flip-Chip Interconnects”, IEEE ?h
Topical Meeting on Electrical Performance o f Electronic Packaging, West Point,
NY, pp. 243-246, October 1998.
11. Hongwei Liang. Carl Shun Ping Chun, Joy Laskar, and Don Estreich, "Development
of Vertical Interconnect Surface Mount Packages”, IEEE International Microwave
Symposium Digest, Baltimore, MD, pp. 1819-1822, June 1998.
12.J. Laskar, N. Jokerst, M. Brooke, M. Harris, C. Chun, A. Pham, H. Liang. D.
Staiculescu, A. Sutono - “Review of packaging research at Georgia Tech’s PRC”,
presented at the 1998 IEEE International Symposium and Exhibition on Advanced
Packaging Materials Processes, Properties and Interfaces, Braselton, GA, pp. 139150, March, 1998.
144
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VITA
Hongwei Liang was bom on December 12, 1973 in Jiangsu Province, China. He
received the B.S. degree in electrical engineering from Nanjing University, Nanjing,
China in 1993, and the M.S. degree in electrical engineering from Institute of
Automation, the Chinese Academy of Sciences, Beijing, China in 1996. He joined the
School of Electrical and Computer Engineering in Georgia Tech in January 1997. He
worked as a graduate research assistant toward the Ph.D degree in Dr. Joy Laskar’s
Microwave Applications Group and the NSF Microsystems Packaging Research Center
where he has authored and co-authored 12 journal and conference papers. He joined the
Multilink Technology Corporation, Somerset, New Jersey in August 2001. His research
interests include design o f microwave and millimeter-wave packages and
interconnections, development of highly integrated optoelectronic modules, and new high
frequency measurement and de-embedding techniques.
145
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