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Low -loss on -chip interconnects for silicon integrated radio-frequency and microwave systems

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LOW-LOSS ON-CHIP INTERCONNECTS FOR
SILICON INTEGRATED RADIO-FREQUENCY
AND MICROWAVE SYSTEMS
By
LEUNG Lap Wai, Lydia
A Thesis Submitted to
The Hong Kong University o f Science and Technology
in Partial Fulfillment o f the Requirements for
the Degree o f Doctor o f Philosophy
in the Department of Electrical and Electronic Engineering
Jan 2005, Hong Kong
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UMI Number: 3164834
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Authorization
I hereby declare that I am the sole author o f the thesis.
I authorize the Hong Kong University of Science and Technology to lend this
thesis to other institutions or individuals for the purpose o f scholarly research.
I further authorize the Hong Kong University o f Science and Technology to
reproduce the thesis by photocopying or by other m eans, in total or in part, at the
request of other institutions or individuals for the purpose o f scholarly research.
LEUNG, Lap-Wai, Lydia
u
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Low-loss On-chip Interconnects for Silicon Integrated
Radio-Frequency and Microwave Systems
By
LEUNG, Lap Wai, Lydia
This is to certify that I have examined the above PhD thesis
and have found that it is complete and satisfactory in all respects,
and that any and all revisions required by
the thesis examination committee have been made.
A pproved by:
Prof. Kevin J. Chen, Thesis Supervisor
Prof. Kei-May
Prof. Edm und Y. M. Chiang, Chairman
, Thesis Examiner
Prof. M an Wong, Thesis E? aminer
Prof. Yi-Kfuen Lee, Thesis Examiner
Prof. Khaled Ben Letaief, Head of Department
Department o f Electrical and Electronic Engineering
6 January 2005
in
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Dedicated to
M y Dad and Mum
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Acknowledgments
I w ould like to take this opportunity to express m y heartfelt gratitude to all the
people who have provided unlim ited support for me throughout m y studies in the
HKUST.
First, I am indebted to m y supervisor, Prof. K evin J. Chen, for his guidance,
unlim ited support and insight. Also, I w ould like to thank him for sharing his
invaluable experience in analytical thinking and conducting research with me.
In addition, I would like to thank all the staff in W ireless Communication
Laboratory, M icroelectronics Fabrication Laboratory and EPA CK Laboratory for
their important assistance in fabrication. Special thanks to S. F. Luk and K. W. Chan
for their assistance in using the CAD tools and setting up the measurement
equipment. I would like to thank X. Huo, W. C. Hon and Jinw en Zhang for their help
and discussion in the CAD tools and fabrication as well.
I w ould like to thank all my friends and colleagues in the Department of
Electrical and Electronic Engineering, especially Kenneth Chan, Daniel So, Peter
Chan for providing an enjoyable research environm ent for me throughout m y PhD
study.
I also want to thank Prof. K. M. Lau, Prof. Y. K. Lee, Prof. M an Wong, Prof.
K. L. W u for being m y thesis examiners and Prof. R. M urch for being my thesis
proposal committee and providing advices and suggestions for me.
Finally, m y deepest thanks go to my family for their unfailing love, devoted
nourishment, unlimited support and encouragement throughout my undergraduate
and postgraduate studies.
iv
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Table of Contents
Title Page
i
Authorization
ii
Signature
iii
Acknowledgements
iv
Table of Contents
v
List o f Figures
ix
List o f Tables
xv
Abstract
xvii
Chapter 1
1
Introduction
1
1.1.
Background
1
1.2.
Motivations
3
1.3.
Thesis Contributions
5
1.4.
Thesis Organization
7
1.5.
List of Publications
9
1.5.1. Journal Publications
9
1.5.2. Conference Publications
10
Chapter 2
11
Preliminaries
11
2.1.
2.2.
2.3.
Different types of on-chip interconnects
11
2.1.1 .Microstrip line
11
2.1.2.Coplanar Waveguides
14
High Frequency Effects
17
2.2.1.Proximity Effect
17
2.2.2.Skin Effect
18
Microwave Network Analysis
20
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2.3.1. Network Parameters
20
2.3.2.Reflection Coefficients
21
2.3.3.S-Parameters
21
2.4.
S-parameter-based Interconnect Transmission Line Characterization
23
2.5.
Conclusion
26
Chapter 3
Low-loss
3.1.
3.2.
3.3.
3.4.
27
Passives on Low-resistivity silicon with Low-k BCB Dielectric
Properties of Benzocyclobutene (BCB)
27
29
3.1.1. Electrical and Thermal properties
29
3.1.2. Coating Process
29
Thin-film Passive Components
32
3.2.1 .Filter Design
33
3.2.2.Fabrication Process
34
3.2.3.Results Analysis
37
Coplanar Waveguides
39
3.3.1. Fabrication Process
39
3.3.2.Results Analysis
42
Conclusion
52
Chapter 4
53
Edge-Suspended Coplanar Waveguides
53
4.1.
Working Principles
54
4.2.
Fabrication
56
4.3.
4.4.
4.2.1.Process design
56
4.2.2.Layout
59
4.2.3.Process Flow
61
Results Analysis
63
4.3.1 .Undercut Characteristic
63
4.3.2.Characteristics of the edge-suspended CPW
65
4.3.3.Extracted impedance and effective dielectric constant
67
Crosstalk between Finite Ground ESCPWs
4.4.1. Layout and measurement set-up
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79
79
4.4.2.Measurement Results Analysis
4.5.
79
Conclusion
82
Chapter 5
83
Computer-Aided Design (CAD) Equivalent Circuit M odeling o f Edge-Suspended
Coplanar Waveguides
83
5.1.
Propagation Modes in CPWs on Semi-conducting Substrate
84
5.2.
Modeling of the Edge-Suspended CPW (ESCPW)
86
5.2.1.Determination of the model parameters
91
5.3.
5.4.
Model Verification
93
5.3.1.RLGC Line Parameters
93
5.3.2.Insertion Loss
94
Results Analysis
96
5.4.1 .Effect of Lateral Undercut
96
5.4.2.Effect of vertical trenches by ICP-DRIE
98
5.5.
Modeling of the Crosstalk between Finite Ground ESCPWs
5.6.
Conclusion
98
101
Chapter 6
102
Through-wafer Interconnect Vias
102
6.1.
High-aspect ratio through-wafer via-holes
104
6 .1.1. Inductively Coupled Plasma Deep Reactive Ion Etching (ICP-DRIE) 104
6 . 1 .2 .Sidewall notch formation
106
6 .1.3.Fabrication
106
6.2.
Copper-filled high-aspect ratio through-wafer vias
110
6.3.
Fabrication of the Testing Structures
114
6.4.
Vias Characterization
116
6.4.1 .TWI vias impedance
116
6.4.2.Effect o f vias arrangement
120
6.5.
TWI vias modeling
124
6 .6 .
Conclusion
128
Chapter 7
129
Conclusions and Future Works
129
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References
134
Appendix
142
1. Process flow of passive components on BCB
142
2. Process flow of Edge-Suspended Coplanar Waveguides
150
3. Process flow of through-wafer interconnects vias
159
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List o f Figures
Figure 2.1: Geometry of microstrip line.
12
Figure 2.2: E-field distribution within a microstrip line.
12
Figure 2.3: Cross-sectional schematic of a CPW.
15
Figure 2.4: E-field distribution of a CPW.
15
Figure 2.5: Proximity effect due to current flow in nearby conductors: (a) even-mode
and (b) odd-mode.
18
Figure 2.6: Compact ladder model illustrating skin effect in a conductor.
19
Figure 2.7: A two-port network.
20
Figure 2.8: Two-port network showing the forward and backward traveling waves.
22
Figure 2.9: Uniform transmission line: (a) of unit length, I and (b) lumped-element
model.
24
Figure 3.1: Curing profiles for BCB in an inert ambient.
31
Figure 3.2: Process Description for Cyclotene.
32
Figure 3.3: Cross-section schematic of the thin-film microstrip line (TFMS).
33
Figure 3.4: Cross-sectional schematic of a 10 GHz low-pass filter.
33
Figure 3.5: Lumped-element low-pass filter prototype.
34
Figure 3.6: Layout of the third order equal-ripple low-pass filter.
34
Figure 3.7: Insertion loss of the TFMS.
37
Figure 3.8: Comparison of the simulation and measurement results o f the 10 GHz lowpass filter.
38
Figure 3.9: Cross-sectional view of the CPW on BCB dielectric.
39
Figure 3.10: Measured effective dielectric constant of different dimensions CPWs on 6
pm BCB.
43
Figure 3.11: Comparison of the insertion loss of the coplanar waveguide on (a) 6 jl u
BCB and (b) 14 pm BCB.
ti
44
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Figure 3.12: Comparison of the E-field distribution on 20 pm BCB with a) S = 8 jum, W
— 30 jutn and b) S = 20 jum; W = 7 0 jum. [Dashed line is added to outline the
boundary of the CPW and BCB for clarity]
45
Figure 3.13: Characteristic impedance of the CPWs listed in Table 3.7 on different BCB
thickness. [Line: EM simulation; symbol: measurement]
46
Figure 3.14: E-field strength along the interface between the lossy silicon substrate and
interfacing dielectric.
48
Figure 3.15: Performance of the coplanar waveguide on 14 pm BCB at low frequency.
49
Figure 3.16: Insertion loss of the narrow CPW (S = 8 pm, W = 30 pm ) on different
thickness of BCB.
49
Figure 3.17: Attenuation per wavelength of the narrowest CPW (CPW1) on different
thickness of BCB.
50
Figure 3.18: Comparison of the E-field distribution of narrow CPW (S = 8 jum, W = 30
/mi) with different BCB thickness (a) 6 jum and (b) 20 jum. [Dashed line is
added to outline the boundary of the CPW and BCB for clarity]
51
Figure 4.1: Cross sectional schematic of the edge-suspended CPW (ESCPW).
55
Figure 4.2: Simulated current distribution in a CPW operating at 10 GHz.
56
Figure 4.3: Cross-sectional view showing the current distribution and the edgesuspended CPW with reduced substrate coupling.
Figure 4.4: Crystal orientation of the wafer and the etching faces.
56
57
Figure 4.5: Schematic (a) top view and (b) cross sectional view showing the influence of
the edges’ orientation on the etching profile.
61
Figure 4.6: SEM images of the edge-suspended CPW aligned at 45° with the major cut
of the (100) silicon wafer with 8 -pm undercut viewing at: (a) 90° and (b) 80°.
64
Figure 4.7: SEM image of the edge-suspended CPW aligned at 0° with the major cut of
the (100) silicon wafer after TMAH etching.
65
Figure 4.8: Cross-sectional view of the edge-suspended CPW with trenches of different
depth and undercut.
66
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Figure 4.9: Measured impedance and effective dielectric constant.
68
Figure 4.10: Extracted shunt capacitance versus frequency of the 1-mm CPW1 with
different degree of undercut.
69
Figure 4.11: Extracted shunt conductance versus frequency of the 1-mm CPW1 with
different degree of undercut.
70
Figure 4.12: Extracted series resistance versus frequency of the 1-mm CPWs with
different dimensions and 15-pm undercut.
71
Figure 4.13: Extracted shunt conductance versus frequency of the 1-mm CPWs with
different dimensions and 15-pm undercut.
71
Figure 4.14: Extracted shunt capacitance versus frequency of the 1-mm CPWs with
different dimensions and 15-pm undercut
72
Figure 4.15: Comparison of the performance of the narrowest CPW (CPW1) with
different degree of DRIE and undercut.
73
Figure 4.16: E-field distribution of an edge-suspended CPW using FDTD method.
[Dashed line is added to outline the boundary of the CPW for clarity].
74
Figure 4.17: Extracted substrate capacitance and conductance versus frequency of the 1mm CPW1 with different degree of undercut and ICP-DRIE.
74
Figure 4.18: Comparison of the insertion loss in C P W l’s with different undercut length
(UC).
75
Figure 4.19: Comparison of the performance of the CPW with different dimensions with
15-jum undercut.
77
Figure 4.20: Measured attenuation-per-wavelength (dB/Ag) o f the ESCPWs with
different lateral undercut (UC).
77
Figure 4.21: Insertion loss of the narrowest ESCPWs with different lateral undercut and
characteristic impedance at 40 Hz.
78
Figure 4.22: Measured dielectric constant of the ESCPWs with different lateral undercut
(UC).
78
Figure 4.23: (a) Cross-section schematic and (b) top view of the ESCPWs.
79
Figure 4.24: Measured cross coupling between (a) narrow and (b) wide ESCPWs with
different amount o f lateral undercut.
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81
Figure 5.1: Different propagation mode of interconnects on different substrate
conductivity at different frequencies.
86
Figure 5.2: Cross-section of the edge-suspended coplanar waveguide.
87
Figure 5.3: RLGC equivalent circuit schematic o f CPW interconnects.
88
Figure 5.4: Compact ladder model for the skin effect.
89
Figure 5.5: Equivalent circuit model used in each unit cell representing 1-mm-long
ESCPW.
90
Figure 5.6: Comparison of the simulation results obtained by the proposed model and
the measurement results (a) resistance and conductance; (b) capacitance and
conductance. [Line: model; symbol: measured]
94
Figure 5.7: Comparison of the measured and modeled insertion loss o f the CPWs with
different amount of undercut. [Line: model; symbol: measured]
95
Figure 5.8: Comparison of the measured and modeled insertion loss o f the CPWs with
different amount of lateral undercut, UC and trench depth, DT. [Line: model;
symbol: measured]
95
Figure 5.9: Relationship between (a) substrate resistance, R SUb', (b) coupling capacitance:
Csi/air (diamond) and Csub (square) and the amount of lateral undercut.
97
Figure 5.10: Mutual coupling inductance added to the external inductors and inductors in
the ladder model used in each ESCPW unit cell.
99
Figure 5.11: Measured and modeled cross-coupling, S31, between adjacent (a) narrow
(CPW1) and (b) wide (CPW5) ESCPW. [Line: model; symbol: measured]
100
Figure 6.1: DRIE Bosch Process: alternating between etching and deposition.
104
Figure 6.2: ASE mechanism, showing alternating passivation and etching process: (a)
fluorocarbon polymer covers all surfaces; (b) During the initial etching cycle,
polymer is removed from the base of the trench by the fluorine radicals; (c)
The exposed silicon is etched anisotropically.
105
Figure 6.3: Charges are built up on the oxide layer which leads to the occurrence of the
notches at the Si/SiC>2 interface.
106
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Figure 6.4: SEM images of the via holes with different diameters: (a) 30 pm ; (b) 50 jam.
108
Figure 6.5: Notches formed at the Si/SiC>2 interface of the 50 jam via-holes.
109
Figure 6 .6 : Set-up for the bottom-up electroplating process.
Ill
Figure 6.7: Bottom of the via-holes being blocked after 3-hour of electroplating: (a)
topview and (b) sideview.
112
Figure 6 .8 : SEM image of the 70pm via array over-filled with copper after 3-hour
electroplating: (a) top-view and (b) side-view.
113
Figure 6.9: Testing structures built for vias characterization: (a) simple short and (b) Tresonator.
114
Figure 6.10: Via arrangement under test: (a) single via; (b) double vias; (c) quadruple
vias (diagonally) and (d) quadruple vias (straightly).
117
Figure 6.11: Measured inductance of the one-port test structure with (a) 1 via and (b) 4
vias arranged horizontally fabricated on the 400 pm HRS with different
diameter size.
118
Figure 6.12: Measured resistance of the one-port test structure with (a) 1 via and (b) 4
vias arranged horizontally fabricated on the 400pm HRS with different
diameter size.
119
Figure 6.13: Simulated charge density in the vias at resonant frequency of the Tresonator: (a) single via; (b) double vias; (c) quadruple vias (diagonally) and
(d) quadruple vias (straightly).
120
Figure 6.14: Measured (a) inductance and (b) resistance o f the 70-pm vias with different
arrangement.
122
Figure 6.15: Simulated current distribution along the shorting edge of the T-resonator at
resonant frequency: (a) single via; (b) double vias; (c) quadruple vias
(diagonally) and (d) quadruple vias (straightly) [Dashed circle in (c) and (d)
are added to outline the boundaries of the via-holes for clarity].
123
Figure 6.16: Return loss of the 10 GHz T-resonator with different via arrangement as a
function of frequency.
124
Figure 6.17: Equivalent circuit model for the TWI via.
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126
Figure 6.18: A comparison between the (a) real part and (b) imaginary part of the 70-pm
TWI vias deduced from the measurement and the equivalent circuit model.
127
Figure 7.1: Micro-channels for placing the biomaterials under testing.
133
Figure 7.2: Topview and sideview of the electromagnetic bandgap structure, which is
composed of periodic LC network.
xiv
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133
List of Tables
Table 3.1: Electrical and thermal properties of BCB and polyimide.
29
Table 3.2: Typical CYCLOTENE thickness after soft bake and hard bake.
30
Table 3.3: Pre-exposure hot plate soft bake temperature.
30
Table 3.4: Exposure dose for different CYCLOTENE.
31
Table 3.5: Characteristics and dimensions of the 10 GHz low-pass filter.
34
Table 3.6: Fabrication process flow of the passive components on thin film.
36
Table 3.7: Dimensions of the fabricated CPWs.
39
Table 3.8: Fabrication process flow of the CPW on multi-layer BCB.
42
Table 4.1: Fabrication flow of the edge-suspended CPW (ESCPW ).
63
Table 4.2: Physical dimensions of various CPW designs.
66
Table 4.3: Summary of the dimensions of the trenches and undercut created after 15-pm
ICP-DRIE and different amount of TMAH anisotropic wet etching.
66
Table 5.1: Physical dimensions of various CPW designs.
87
Table 5.2: Summary of the dimensions of the trenches and undercut created after 15-pm
ICP-DRIE and different amount of TMAH anisotropic wet etching.
87
Table 5.3: Parameters used in the ladder compact model o f the narrowest CPW with 15pm lateral undercut.
91
Table 5.4: Parameters used in each unit cell of the equivalent rr-model of the ESCPWs
with 15-pm ICP-DRIE and different amount o f undercut.
92
Table 5.5: Parameters used in the equivalent Tt-model o f the ESCPWs with different
vertical trench depth created by ICP-DRIE only.
92
Table 5.6: Parameters used in the equivalent rc-model o f the ESCPWs with different
dimensions and undercut of 15 pm.
93
Table 6 .1: Etch rate of the ICP-DRIE process throughout the fabrication process.
107
Table 6.2: Comparison of the etch rate of the via-holes with different diameters.
108
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Table 6.3: Fabrication flow of the high-aspect ratio through-wafer via-holes.
110
Table 6.4: Fabrication flow of filling the high-aspect ratio via-holes with Cu.
113
Table 6.5: Fabrication flow of the testing structures.
115
Table 6 .6 : Summary of the measured inductance and resistance of the vias with different
diameters at 2 GHz.
117
Table 6.7: Extracted lumped element for the TW I vias.
xvi
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126
Low-loss On-chip Interconnects for Silicon Integrated
Radio-Frequency and Microwave Systems
By
LEUNG, Lap Wai, Lydia
Department o f Electrical and Electronic Engineering
The Hong Kong University of Science and Technology
Abstract
With the rapid development in wireless and portable communication, there is an
increasing demand for low-cost and miniaturized radio-frequency (RF) and microwave
monolithic integrated circuits. While the active transistors have experienced steady
enhancement in device performance as a result of the advancing CMOS technology, it is
still challenging to realize low-loss high-frequency interconnects on standard CMOSgrade silicon substrates, which normally have low-resistivity in the range of 1 - 20 Qcm.
In this thesis, we study the lossy mechanisms, which are dominated by substrate
loss and metallic loss, of interconnects on standard CMOS-grade silicon substrates. Our
goals are to design, fabricate, characterize and model high-performance interconnects on
lossy substrates. Three different kinds of processing technologies are proposed:
interconnects employing high-conductive copper on low-loss low-k dielectric material -
xvii
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BCB, micromachined edge-suspended coplanar waveguides and high-aspect ratio
through-wafer interconnects vias.
Thick copper-electroplated thin-film passive components including microstrip line,
low-pass filter and coplanar waveguides were designed and fabricated on standard
CMOS-grade silicon employing a thick low-loss low-k dielectric interfacing layer to
reduce both the substrate loss and the metallic loss. We also propose the use of the
micromachining process to remove the substrate along the edge of the interconnects,
where the coupling is the strongest to achieve the edge-suspended structures, which
reduce signal coupling to the lossy silicon substrate at radio frequency and provide
support mechanical support simultaneously. Measurement and EM simulation results
reveal the working mechanisms and performance o f the proposed processing
technologies. The technologies can be generally applied to achieve low-cost and highperformance on-chip passive components on standard CMOS substrate. Moreover, the
fabricated edge-suspended coplanar waveguides have been characterized and a compact
equivalent circuit model has been derived over a broad frequency range. The circuit is
further extend to the modeling of crosstalk between the finite ground suspended CPWs.
For the realization of high-density, reliable, low-parasitic and low-cost packaging
and novel three-dimensional electromagnetic structures on silicon substrate, high-aspect
ratio through-wafer vias are needed. With the use of the state-of-the-art micromachining
technology and the bottom-up electroplating approach, high-aspect ratio through-wafer
vias on thick silicon substrate with dimensions ranging from 50 pm to 70 pm have been
achieved, characterized and modeled.
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Chapter 1 - Introduction
Chapter 1
Introduction
1.1. Background
With the increasing demand for high-density, low-cost and compact radio
frequency front ends for high data rate and wireless communication systems, a lot of
research has been conducted to develop high-performance microwave circuits on silicon
substrate. While the active transistors have experienced steady enhancement in device
performance as a result of the advancing CMOS technology, it is still challenging to
realize low-loss microwave passive components such as microstrip line and coplanar
waveguides (CPWs) on standard CMOS-grade silicon substrates, which normally have
low resistivity in the range of 1-20 Q-cm. Significant loss can be generated at
microwave frequencies as a result of the signal coupling into the low-resistivity silicon
substrate. In order to overcome this dominant loss factor in silicon-based microwave
passive components, various approaches have been investigated. Firstly, high resistivity
silicon (HRS) [l]-[2] (p > 2500 Q-cm) can be used to reduce the substrate loss. Proton
implantation can also be used to convert low resistivity silicon to high resistivity silicon
[1]. However, RF and microwave integrated circuits are usually fabricated on low-cost
low-resistivity silicon using standard CMOS production process. Secondly, the substrate
coupling can also be effectively reduced by inserting a low-loss low-k dielectric layer
[4]-[8] between the CPW and the lossy silicon substrate. Another widely investigated
approach is to apply micromachining techniques to remove the silicon substrate
1
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Chapter 1 - Introduction
underneath (or around) the signal line to reduce the substrate loss [9]-[13]. However, the
CPWs fabricated on the suspended membrane require sophisticated backside processing
and their mechanical strength is also questionable, especially for long CPWs. The
micromachined overlay CPW structure by Kim et al. [14] also requires the airbridge
technique and it remains to be seen whether it can be compatible with the standard
CMOS process. Herrick et al. [15] implemented CPWs with etched V-grooves around the
signal line in CPW to reduce the line capacitance, and the approach is CMOS compatible.
The depth and the lateral undercut of the grooves, however, are limited by the choices of
the wet etching solution, the layout orientation and the signal-to-ground separation.
Through-wafer interconnect (TWI) vias have attracted a great deal of interests
recently owing to its high density and versatile applications. Small-size TW I vias, which
can be closely packed, are needed for high density, reliable packaging and testing of
current and future systems including RF MEMS [16]. From the high frequency circuit
point of view, the TWI vias can be used to replace bond wires that add parasitics to the
overall circuitry operating at radio frequency. The wire bonding process is not a batch
process and counts for significant portion of the back-end production cost. In addition,
TW I vias are indispensable elements in integrating metamaterials, artificial materials
with specific electromagnetic properties that are not found in nature [17], into silicon.
These left-handed materials with both negative permittivity and permeability have “stop­
band” at certain frequency range. Physical realization of these novel materials have been
achieved in PBC boards in one-dimensional (1-D) [18] and two-dimensional (2-D) [19]
structures. They are applied in designing novel microwave devices such as couplers [20],
[21], resonators [22] and antennas [23], [24],
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Chapter 1 - Introduction
The development of the TWI technology has picked up speed lately with the
advancement of the deep dry etching techniques for silicon substrates [25]. Via-holes
with aspect ratio as high as 50 have been demonstrated on silicon substrates. The most
challenging task in TWI fabrication is to fill up the high aspect ratio via-holes with voidfree highly conductive materials. Recent reports on through-wafer interconnect via-holes
include attempt to fill the via-holes partially by a metal coating layer [26] or fill the viaholes by polysilicon [27], [28], both of which deliver moderate electrical conductivity.
Another recent work attempted to fill the via-holes with Au-Sn solder using molten
metal suction method [29]. By thinning down the silicon substrate, before or after the
etching of the high aspect ratio via-holes, the difficulty in metal filling o f the vias can be
eased [30]-[32] and vias filled with copper with an aspect ratio o f 14 has been achieved
on 100-pim thick wafer [31]. Moreover, sacrificial wafers have to be used to facilitate the
electroplating process [30], [33].
1.2. Motivations
This research works on the on-chip low-loss low-cost CMOS-compatible
interconnects on silicon substrate operating at microwave frequency. The employment of
the low-k dielectric as the interfacing layer to isolate the passive components from the
lossy substrate is a potential solution. Ponchak et al. uses polyimide as the low-k
dielectric layer and demonstrates high-performance CPWs using gold as the metal.
However, the polyimide prohibits the use of Cu, the metal with the highest conductivity,
because copper can drift readily into polyimide [35]-[36]. Hence, we propose the use of
a photosensitive low-k dielectric, benzocyclobutene (BCB), which has a low dielectric
loss (loss tangent, tan S = 5 x 10'4) and low dielectric constant (er = 2.65), as the
3
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Chapter 1 - Introduction
interfacing layer on the silicon substrate. In addition, a thick high-conductivity copper
layer is electroplated on the spin-on BCB layer to form the CPW to reduce the metal
conductive loss. The spin-on low-k dielectric also offers larger thickness (several tens of
micrometer), which favors the coupling reduction.
Significant improvement can be achieved by building passive components on
suspended membrane created by micromachining. Nonetheless, mechanical strength and
reliability of the packaging of the structure are still questionable. We propose the edgesuspended structure that can be achieved by removing the substrate along the edges
making use of the state-of-the-art micromachining technology whereas the substrate
supporting the center of the metal lines is left untorched.
With the increase in the demand of low-cost interconnect and packaging solutions,
low parasitic high aspect-ratio three-dimensional interconnects are needed for high
density, reliable packaging and testing o f current and future systems at radio frequency
including radio frequency MEMS, which are usually built on standard thick CMOS
substrate. TW I vias are crucial elements for realizing advanced microwave structures
like photonic bandgap structure and composite right/left-handed metamaterials on
standard
silicon
substrate.
Firstly, thicker substrate
favors
certain
microwave
components, e.g., patch antennas for wider bandwidth and microstrip lines for wider line
width that produces lower resistance. The vias here are used to provide signal feeding or
shorting paths. Second, wafer thinning is normally the final step before wafer dicing and
the thinned wafers are normally too fragile to be allowed back to the standard fabrication
line. Thicker wafer allows additional processes after the via-hole formation. Furthermore,
via-holes may be blocked by the particles generated during the thinning process and
hence, the overall yield of the process will be lowered.
4
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Chapter 1 - Introduction
1.3. Thesis Contributions
In this thesis, we study the working principles and technologies of integrating lowloss interconnect on CMOS-grade silicon substrate at radio frequency (RF) extensively.
In particular, we focus our work on the lossy mechanism of interconnects on lowresistivity silicon. The objectives are to design and realize different CMOS-compatible
techniques or post-IC processes for integrating the low-loss interconnect on silicon
substrate.
In this first part of the thesis, we make use of a photosensitive benzocyclobutene
(BCB), a low-k dielectric material as the interfacing layer on the silicon substrate to
isolate the passive components from the lossy substrate. Detailed analysis on the electric
field distribution along the interfacing layer and the lossy silicon substrate was
conducted to investigate the effect of the interconnect dimensions on its performance. In
addition, as there is no interaction between copper and BCB, high-conductivity copper
can be employed as metal layer to reduce metallic loss. A self-aligned electroplating
process was designed to achieve thick copper layer. Furthermore, the approach of
incorporating low-k isolation layer has the benefit of accommodating active circuits
underneath the passive components and interconnects, making three-dimensional
integration of active circuits and passive components feasible.
W ith the use of the interfacing layer to isolate the passives from the lossy substrate,
significant improvement can be achieved. Nonetheless, the passives are integrated as a
post-IC process and via-holes are needed to connect the passives with the active circuit
underneath. These drawbacks motivate us to our second contribution. A novel low-loss
CMOS-compatible
edge-suspended
interconnects
employing
micromachining
5
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on
Chapter 1 - Introduction
CMOS-grade silicon substrate is proposed. It is revealed that, at radio or microwave
frequencies, the current is highly concentrated along the edges of the signal line. Since
the coupling to the low resistivity silicon substrate is dominated by the current carrying
part, the substrate coupling and loss can be effectively suppressed by removing the
silicon along and underneath the edges of the signal lines. The edge-suspended structure
has been implemented with a combination o f deep reactive ion etching and anisotropic
wet etching. The major advantage of the edge-suspended is the strong mechanical
support provided by the silicon underneath the center o f the interconnects. As the edgesuspended structures are created by combining the state-of-the-art micromachining
technology and anisotropic wet etching, its physical dimensions can be controlled easily
by the etching time. Hence, the edge-suspended interconnects can be closely packed to
meet the continued scaling of semiconductor processes. The crosstalk between the
closely packed interconnects is also investigated.
Since on-chip interconnects have significant impact on the performance of both
high-speed digital and RF integrated circuits, the frequency-dependent series impedance
and shunt admittance must be taken into consideration during sub-circuit design. The
fabricated edge-suspended coplanar waveguides were characterized over a board
bandwidth and a compact equivalent circuit model that can be easily incorporated into
circuit simulators has been derived. The equivalent circuit is further extended to model
the measured cross-coupling between the adjacent edge-suspended coplanar waveguides.
In addition to planar structure, we propose the fabrication and characterization of
the high-aspect ratio copper-filled via-holes in standard silicon substrate for CMOS
technology (400 pm) for 3-D integration in compact RF systems and novel
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Chapter 1 - Introduction
electromagnetic structures such as frequency-selective surfaces and metamaterials. The
complete fabrication process can be integrated as the post-IC process.
1.4. Thesis Organization
This thesis is organized as follows. In Chapter 2, we provide the fundamental
theories of interconnects operating at millimeter-wave frequency. First, the interaction
between the interconnect signal and the substrate at radio frequency is presented. Next,
basic radio frequency characterization, extraction and measurement skills are briefly
described. The purpose of this chapter is to provide the basic knowledge in this research
area.
In this thesis, we propose three different technologies to achieve low-loss
interconnects on silicon substrate operating at radio frequency. The first technique which
employs a photosensitive low-k interfacing layer between the passive component and the
lossy substrate is discussed in Chapter 3. The CMOS-compatible low-temperature
fabrication process is also presented. Improvement achieved is proven by both
simulation and measurement results of different commonly used passive components,
including microstrip line, coplanar waveguide and low-pass filter.
The second technique that makes use of the combination o f micromachining and
anisotropic wet etching techniques to achieve an edge-suspended interconnects are
illustrated in Chapter 4. Detailed fabrication process is elaborated. In addition, the
working mechanism of the novel structure is depicted by high-frequency measurement
of the fabricated structure and full-wave electromagnetic simulation. Performance
enhancement is demonstrated by the measured insertion loss of the interconnects.
Broadband characterization of the proposed suspended structure is also performed. The
7
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Chapter 1 - Introduction
RLGC line parameters are extracted and analyzed. Moreover, the crosstalk between the
finite ground edge-suspended coplanar waveguides is investigated.
Based on the extracted line parameters in Chapter 4, a compact equivalent circuit
model which describes the quasi-TEM propagation properties of the edge-suspended
coplanar waveguides is derived in Chapter 5. The relationship between the dimensions
of the suspended structures and the model is also investigated. The equivalent circuit is
further extended to model the measured cross-coupling between the closely packed
edge-suspended coplanar waveguides.
In Chapter 6, we study the three-dimensional through-wafer interconnects that
allow low-parasitic reliable high-density packaging and testing at millimeter-wave
frequency. Fabrication processes including the state-of-the-art deep reactive ion etching
are described. The fabricated vias are characterized using different resonant structures
and the effect of the physical arrangement and distribution in multiple-via configurations
on the resulting parasitic are investigated by both electromagnetic simulation and
measurement results. Equivalent circuit models that provide good agreement with the
measurement results are also presented.
Finally, conclusions are drawn and future works are discussed in Chapter 7.
8
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Chapter 1 - Introduction
1.5. List of Publications
1.5.1. Journal Publications
1. Lydia L. W. Leung, Kevin J. Chen, X. Huo and Philip C. H. Chan, “Low-loss
Microwave Filters on CMOS-grade Standard Silicon Substrate with Low-k BCB
Dielectric,” Microwave and Optical Technology Letters, vol. 40, no. 1, pp. 9-11, Jan.
2004.
2. Lydia L. W. Leung, W. C. Hon and Kevin J. Chen, “Low-loss Coplanar Waveguides
Interconnects on Low-resistivity Silicon Substrate,” IEEE Trans, on Components
and Packaging Technologies, vol. 27, no. 3, Sept. 2004, pp. 507 - 512.
3. Lydia Lap Wai Leung and Kevin J. Chen, “Microwave Characterization and
Modeling of High Aspect Ratio Through-Wafer Interconnect Vias in Silicon
Substrates,” IEEE Trans, on Microwave Technology and Techniques, under review,
May 2004.
4. Lydia L .W. Leung, W. C. Hon, Jinwen Zhang, and Kevin J. Chen, “Characterization
and Attenuation Mechanism of CMOS-Compatible Micromachined Edge-Suspended
Coplanar Waveguides on Low-Resistivity Silicon Substrate,” IEEE Trans, on
Advanced Packaging, submitted, Sept. 2004.
5. Lydia L. W. Leung, Jinwen Zhang ,W. C. Hon and Kevin J. Chen, “CAD Equivalent
Circuit Modeling of the Edge-Suspended Coplanar Waveguide on Lossy Silicon
Substrate,” IEEE Trans, on Components and Packaging Technologies, submitted,
Oct. 2004.
9
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Chapter 1 - Introduction
1.5.2. Conference Publications
1. Lydia L. W. Leung, K. J. Chen, X. Huo, and P. C. H. Chan, “On-Chip Microwave
Filters on Standard Silicon Substrates Incorporating a low-k BCB Dielectric Layer,”
European Microwave Conference, Milan, Italy, Sept. 2002.
2. Lydia L. W. Leung, T. W. Chen, S. W. Wong, M. H. Chan, and K. J. Chen, “A 2
GHz Single-chip Lumped-element Impedance Matching Network for RF Power
Amplifiers
on
Standard
Silicon
Substrate,”
Proc.
Asia-Pacific
Microwave
Conference, Seoul, Korea, Nov. 2003, pp. 1836-1839.
3. Lydia L. W. Leung, W. C. Hon, and K. J. Chen, “Low-loss CPW Interconnects on
Low-resistivity Silicon Substrate,” Proc. Asia-Pacific Microwave Conference, Seoul,
Korea, Nov. 2003, pp. 1875-1878.
4. Lydia L. W. Leung and K. J. Chen, “Microwave Characterization of High Aspect
Ratio Through-Wafer Interconnect Vias in Silicon substrates,” IEEE MTT-S Int.
Microwave Symp. Dig., Texas, USA, June 2004, pp. 1197-1200.
5. Lydia L. W. Leung, W. C. Hon, J. Zhang, and K. J. Chen, “High-Performance
CMOS-Compatible Micromachined Edge-Suspended Coplanar Waveguides on
Low-Resistivity Silicon Substrate,” European Microwave Conference, Amsterdam,
Netherlands, Oct. 2004, pp. 1341 - 1344.
10
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Chapter 2 - Preliminaries
Chapter 2
Prelim inaries
The growing market in wireless communication leads to an increasing demand for
low-cost and miniaturized wireless devices operating at microwave frequency. To
achieve miniaturized devices, it is desirable to integrate microwave analog and digital
circuits which are operating in GHz range. For the realization o f single-chip solution, onchip interconnects that are faster, denser and more reliable become indispensable. In this
thesis, we study the lossy mechanisms of on-chip interconnects and propose different
methods for achieving low-loss on-chip interconnects. In this Chapter, we present the
fundamental knowledge and characterization methods for on-chip interconnects
operating at radio-frequency as a preliminary to this thesis.
2.1. Different types of on-chip interconnects
2.1.1. Microstrip line
Microstrip line is one of the most popular types o f planar transmission lines as it
can be easily fabricated and integrated with other passive and active microwave devices.
The general geometry of microstrip is shown in Figure 2.1, where t is the metal
thickness, W is the width of the microstrip line and h is the substrate thickness. Most of
the field lines are confined between the conductor and the dielectric region and some
exists in the air region above the substrate as shown in Figure 2.2. Hence, microstrip
lines have a relatively lower loss. On the other hand, as the field is confined within the
dielectric, the range of the characteristic impedance of is limited. Also, vias are needed.
11
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Chapter 2 - Preliminaries
Top conducting
plane
W,
Ground plane
Figure 2.1: Geometry of microstrip line.
Signal
*-
11\
O round
Si substrate
Figure 2.2: E-field distribution within a microstrip line.
2 .I.I.I.
Design Formulas
The effective dielectric constant depends on the distribution of the electric field.
The effective dielectric constant of a microstrip line is approximately given by [36],
er +l er - l
1
*ff =— O +- 2 J l +12 h/W
The characteristic impedance is calculated as
12
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(2.1)
Chapter 2 - Preliminaries
60 , ( 8 h W
-i= -ln — + —
for W/h < 1
4h
1207T
Z0 =
for W/h > 1
( 2 .2 )
W
'eff W /h + 1.393 + 0.667 In — + 1.444
vh
For a given characteristic impedance, Z0 and dielectric constant, £>, the W /h can
be designed using the following equations:
for w /d < 2
8e
e
W_
h
-2
B - 1 - ln(2fi - 1)+-S— i J ln(fi - 1 )+ 0.39 -
for W/h> 2
(2.3)
where
Z0 l £r +1 , £r +1 0.23 + 0.11
60 V 2
fr - l
B=
'i l l n
2-^0yf^r
2.1.1.2.
Effect of substrate thickness on operating frequency limitations
As the operating frequency increase, two spurious effects due to the interaction
between the quasi-TEM mode and the lowest-order TM mode and lowest-order
transverse microstrip resonance occur.
2 .I.I.I.
TM M ode limitation
Venedelin [37] indicated that there is a strong coupling between the quasi-TEM
mode and the TM mode when the associated two phase velocities are close. The
phenomenon occurs at the following frequency:
13
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Chapter 2 - Preliminaries
ctan 1(er)
/ r “
(2.4)
'‘
For narrow microstrip line on substrate with high dielectric constant, (2.4) tends to
c
T E M ,l
24 2 h yjer - l
(2.5)
Hence, to avoid coupling between the TEM and the TM modes within the operating
frequency, the maximum restriction on the substrate thickness can be easily obtained as:
(2 .6 )
It is recommended that substrates should be as thin as possible so that the operating
frequencies as stated in (2.14) of the microstrip line can be higher.
2 .I.I.2 .
L ow est-order T ransverse M icrostrip Resonance
For a sufficiently wide microstrip, a transverse-resonant mode that couple strongly
with the quasi-TEM mode occurs when (w+2d) equals to half-wavelength of that mode,
where d accounts for the microstrip side-fringing capacitance: d = 2 h :
EL = w + 2d = w + OAh
2
(2.7)
Hence,
(2 .8)
H ow ever,/cr is usually much higher than f tem.i •
2.1.2. Coplanar Waveguides
Coplanar waveguide (CPW) is another type of planar transmission line. A crosssectional schematic of a CPW is shown in Figure 2.3, where t is the metal thickness, h is
14
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Chapter 2 - Preliminaries
the substrate thickness, W is the separation between the signal line and the ground and S
is the width of the signal line.
W
Figure 2.3: Cross-sectional schematic o f a CPW.
Ground
Signal
Ground
Dielectric
Figure 2.4: E-field distribution of a CPW.
CPW is used alternate to microstrip line due to its appealing properties:
1. Ground plane is just adjacent to the signal line and no vias is needed. Hence, it
facilitates easy shunt and series connections and surface mounting of both active
and passive components e.g. the source grounding of the transistors can be
achieved without vias, which add significant parasitics at millimeter-wave
frequencies and degrade circuit performance.
15
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Chapter 2 - Preliminaries
2. Simpler fabrication.
3. Ground is adjacent to the signal line as shown in Figure 2.4. Radiation loss and
dispersion can be reduced. Therefore, it is very suitable for wideband circuits and
components.
4. As impedance is determined by the S/W ratio and the adjacent ground reduces
the coupling, compact design in the expense of higher conductor loss can be
obtained.
5. Photolithography defined structures with accurate lateral dimensions and hence
accurate characteristic impedance.
CPWs are commonly used in amplifier circuits [38]-[41], mixer circuits [42]-[44] and
switches [45]-[46] as on-chip interconnects and inductive elements. Nevertheless, for
on-chip CPW, as E-field is not isolate from the lossy silicon substrate as in microstrip
line, the spreading of E-field into the Si substrate results in high substrate loss.
2.I.2.I.
Design Formulas
The characteristic impedance of CPW is found by Wen [47] as:
30n K'(k)
(2.9)
Originally, K'(k) and K(k) have to be determined using tables of elliptic integrals. Closed
expressions have been derived by Hilberg [49],
K(k) =_ —
1 In
J ^2 l + VT)
“L i - v f J
for 0 < k < 0.707
(2.10)
for 0 > k > 0.707
(2.11)
16
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Chapter 2 - Preliminaries
where k = s/(s+2w) . Also, the effective dielectric constant is determined given by,
Eeff
= 0.5(er + l)[tanh[l .785 log(/i/ s) +1.75] + (&.s//j)[0.04 - 0.7 k + 0.0 l(l - 0. lerXo.25 + A:)]}
(2.12)
The expression is accurate within approximately 1.5% such that h/w> 1. Hence, wide
gaps should be avoided. All the expressions discussed above can only be used in the
analysis of a CPW with dimensions and dielectric constant provided.
During the synthesis of a CPW, given the characteristic impedance and dielectric
constant, we have to determine the dimensions of the CPW, S and W with the following
expressions:
(2.13)
where x = 2 1+ ^ L . Also, the initial value of the effective dielectric constant is assumed
l-4 k
to be £eff ~ (£r + 1)/2 .
2.2. High Frequency Effects
As frequency increases, the current distribution inside the conductor changes.
These changes are called skin and proximity effects, which lead to frequency-dependent
resistance and inductance.
2.2.1. Proximity Effect
At high frequency, current flowing in conductor concentrates along the side facing
an adjacent current return path so as to reduce the effective area of the current loop and
thus the loop inductance. This phenomenon is known as the proximity effect. The
proximity effect is also known as the current re-distribution due to magnetic fields
17
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Chapter 2 - Preliminaries
generated by the neighboring lines which are not orthogonal to each other. For even­
mode coupling, when the current flows in two neighboring conductors in the same
direction, the current crowding occurs at the far edge of the conductors. For odd-mode
coupling, when the current flows in opposite direction, the current density is higher
along the near edge. The current re-distribution due to even-mode and odd-mode
coupling are shown in Figure 2.5(a) and (b) respectively. The resistance increase in the
conductors in the odd-mode coupling is much larger than that in the even-mode coupling
due to the closer interaction of the generated magnetic fields and hence the higher
current density at the near edge. The current crowding along the edges of some coplanar
structures such as coplanar waveguides is a result of proximity effect.
Figure 2.5: Proximity effect due to current flow in nearby conductors: (a) even-mode
and (b) odd-mode. [Dark: high current density]
2.2.2. Skin Effect
Skin effect results in an exponential increase in the current density near the
conductor surface as frequency increases. The total magnetic flux generated by the timevarying current can be partitioned into the portion lying outside and inside the conductor.
The energy stored in the internal flux leads to internal inductance and that stored in the
external flux is represented by external inductance [48]. At high frequency, current
flows near the conductor surface, so the internal inductance decreases. As a result, the
total inductance decreases and resistance increases with frequency. A compact ladder
model [76] illustrating the skin effect is shown in Figure 2.6. The circular conductor is
18
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Chapter 2 - Preliminaries
divided into concentric rings. Each ring is represented by one ladder section. At low
frequency, the total inductance is equal to the sum of L/ to L 4 and the total resistance is
equal to Rj, R 2 , R 3 and R 4 in parallel. At high frequency, current flows near concentric
ring 1 and the total inductance decrease to L/ and the total resistance increases to Rj.
The skin depth,
8,
is defined [55] as the depth at which the amplitude of the
signals in the conductor decay by He (36.8%). The skin depth is a function of magnetic
permeability, fx and conductivity, cr, of the conductor and frequency,/. It is expressed as,
(2.14)
At 1 GHz, the skin depths of aluminum and copper are 2.58 pm and 2.09 pm
respectively. At 10 GHz, they become 0.81 pm and 0.66 pm respectively. The resistance
and inductance of the conductor will be affected by skin effect only if the thickness and
width of the conductor are larger than 28.
Current flo w s near the
conductor surface as
frequency increases
•o
Figure 2.6: Compact ladder model illustrating skin effect in a conductor.
19
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Chapter 2 - Preliminaries
2.3. Microwave Network Analysis
Characterization and design at radio and millimeter-wave frequencies, a
significant set of parameters known as “scattering parameters” (S-parameters) that
measures the reflected and transmitted power of any network is used.
2.3.1. Network Parameters
A two-port network is shown in Figure 2.7. Four different network parameters are
commonly used in the characterization and analysis of RF network.
Impedance parameters (z-parameters):
(2.15)
Admittance parameters (y-parameters):
(2.16)
Hybrid parameters (/i-parameters):
v; = * ,,/,+ a« v2
f 2
(2.17)
^ 2 1 f 1 “^ ^ 2 2 ^ 2
Chain parameters (ABCD-parameters):
(2.18)
2-port
■a
N etw ork
o
-1
o
+
V2
-
Figure 2.7: A two-port network.
20
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Chapter 2 - Preliminaries
All parameters are interrelated and can be interchanged between each other [55].
2.3.2. Reflection Coefficients
It is well known that the reflection coefficient ( / ) o f a one-port network can be
measured easily. This quantity is simply related to the impedance of the one-port
network as
r=f tr f L
(2-19)
where Zo is the characteristic impedance of the connecting transmission line. For a twoport network as shown in Figure 2.7, input (/]„) and output
(rout) reflection coefficients
are used.
2.3.3. S-Parameters
S-parameters measure the traveling voltages and currents and are used in
characterizing interconnects as they related signals entering a line at one end and
appearing at the other.
Power is another quantity which can be measured at microwave frequencies. Sparameters are based upon the incident and reflected proportions of power around the
network.
Figure 2.8 shows the wave traveling forward and backward on the reference
transmission line with impedance, Zo. Vj+ and V2+ are the incident voltage at port 1 and
port 2 respectively. V f and V i are the reflected voltage at port 1 and port 2 respectively.
As each reflected wave must be a linear combination of both a port 1 incident term and a
port 2 incident term, we have
Ki =xuK+xi2^2
21
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(2 .20 )
Chapter 2 - Preliminaries
(2 .21 )
where xnm are arbitrary coefficients.
The incident power of the wave towards port 1 is given by
(2 .22 )
The square root of the power is simply given by
h \ =^
= Vn/y fz^
(2.23)
By similar argument, b, =vr[/Jz~a , a2=vi2/Jz^ and b2 = vr2/J z ^ . Dividing (2.45) and (2.46)
by yfz^ , Vi„ and Vrn can be replaced by an and
b„
and the arbitrary coefficients are called
the scattering parameters. The expression can then be written as:
&1
SnOl + Sl2^2
b2 —‘S'21^1
Zs
(2.24)
(2.25)
^ 22^2
U ........
Of
U
P ort
j
_
*0
2 -p o rt
N e tw o rk
P ort
2
0
O
yr1
r \V1
v
y;
Figure 2.8: Two-port network showing the forward and backward traveling waves.
If the output line is matched, i.e. ZL = Zo, the load do not reflect power,
&2
= 0 and
(2.49) yields
= -H
22
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(2.26)
Chapter 2 - Preliminaries
By alternately matching the input and output ports, the three remaining parameters can
be extracted.
S22:
S 2
o2
-
(2.27)
—
a,
aj =0
S21:
—
(2.28)
02=0
S 12:
b,
S12
(2.29)
ai =0
Hence, the physical meanings of S-parameters are as follows:
Sn is the input reflection coefficient ( / / / ) when the output is matched.
S22 is the input reflection coefficient ( /I /) when the input is matched.
S 12 is the forward transfer coefficient when the output is matched.
S21 is the reverse transfer coefficient when the input is matched.
To measure the S-parameters, it is necessary to use terminations that absorb all of the
power delivered to them i.e. ai = 0 and
112
= 0.
2.4. S-parameter-based Interconnect Transmission
Line Characterization
Interconnect signal transmission is based on the solution of the classical
Telegrapher’s transmission line. All uniform transmission lines regardless of their
structures can be modeled by four distributed transmission line parameters, R, L, G, and
C as shown in Figure 2.9. R, L, G and C are referred as the series resistance, series
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Chapter 2 - Preliminaries
inductance, shunt conductance and shunt capacitance per unit length, I and are functions
of frequency.
---- I------ -
c
(a)
(b)
Figure 2.9: Uniform transmission line: (a) of unit length, I and (b) lumped-element
model.
The S-parameter responses measured from a lossy unmatched transmission line
with propagation constant, y and impedance, Z in a Zo impedance system are
[5] =
( z 2 - Z02)sinh yl
Dq
2ZZ0
2ZZn
( z 2 —Z 2)sinh y_
(2.30)
where Ds = 2ZZ0 cosh yl + {z2+ Z 02)sinh yl . The S-parameter matrix is converted to
ABCD parameters [55] which incorporate the interconnect propagation constant, y(co),
and the impedance Z( co) and is given as
[a b c d ] =
cosh yl
Z sinh yl
Z sinh yl
cosh yl
(2.31)
The conversion between the S-parameters and the ABCD matrix is [55]
A = (1+ Sn - S 22 - A S ) / 2 S 2l
B = (l + Su + S 22 + A.S')Z0/2 S 21
C = ( 1 - S u - S 22+A S)/(2S21Z 0)
D = ( 1 - S u + S 22-A S )/(2 S 21)
where AS —S n S 22 - S 21S t
24
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(2.32)
Chapter 2 - Preliminaries
Combining equations (2.31) and (2.32) to yield [58]:
-1
(2.33)
where
K =
{s^-si+i}2- {2sny Y2
(2.34)
(2 S2I)2
(2.35)
where Z q is the impedance of the measurement system. During the extraction of the
complex parameters y and Z from
and Z2, the cyclically mapped phase output of the
S-parameter network analyzer (-180° to +180°) is converted to the true radian
measurement phase. This may result in some extracted parameters which are not
physically real, such as negative attenuation constant or values that cannot physically
satisfy the Telegraph’s equation for propagation in positive direction.
From the relationship between the propagation constant and the parameters in the
Telegrapher equation:
y
=
y/(R + jccL)(G + jcoC) = a + j f i
(2.36)
(2.37)
where a is the attenuation constant and
is propagation constant. The telegrapher’s
equation parameters can be determined from the extracted complex parameters, y and Z:
R —Re{jZ0}
25
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(2.38)
Chapter 2 - Preliminaries
Imh z A
L =—
(2. 39)
CO
G = Rel z J
(2’40)
c =-- VCO—±L.
(2.41)
2.5. Conclusion
In this Chapter, the basic concepts and high-frequency behaviors of on-chip
interconnects including microstrip line and CPW are discussed. On-chip interconnect
measurement and characterization skills are also presented.
26
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
Chapter 3
Low-loss Passives on Low-resistivity silicon
with Low-k BCB Dielectric
While the active transistors have experienced steady enhancement in device
performance as a result of the advancing CMOS technology, it is still challenging to
realize low-loss high-frequency interconnects such as microstrip lines and coplanar
waveguides on CMOS grade silicon substrate. Significant loss can be generated as a
result of the signal coupling into the low-resistivity silicon substrate. Polyimide has been
used recently as the low-k dielectric layer and demonstrated high-performance CPWs
using gold as the metal. The polyimide, however, prohibits the use of Cu, the metal with
relatively higher conductivity, because copper can drift readily into polyimide. Although
Tantalum Nitride (TaN) or Titanium Nitride (TiN) can be used as the barrier layer
between the copper and polyimide to block the copper diffusion, the lower conductivity
of the barrier layer will cause a significant detrimental effect on signal propagation at
microwave frequencies.
In this Chapter, we study the use of a low-k benzocyclobutene (BCB) dielectric
that does not have interaction with copper as the interfacing layer on the low-resistivity
silicon substrate to insulate the metal layer of the passive components from the substrate
to reduce substrate loss. Also, thick electroplated copper [60] is employed as the metal
layer to reduce metal loss. Different passive components and structures have been built:
microstrip line, low-pass filter and coplanar waveguide.
27
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Chapter 3 —Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
This Chapter is organized as follows. Section 3.1 describes the properties of the
low-k dielectric BCB. The design, simulation, fabrication and characterization of thinfilm passive components and coplanar waveguides are depicted in Section 3.2 and 3.3
respectively.
28
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.1. Properties of Benzocyclobutene (BCB)
3.1.1. Electrical and Thermal properties
Benzocyclobutene (BCB) is a photosensitive material that has been developed as
dielectric in thin film microelectronic applications thanks to its low dielectric constant,
dissipation factor and conductivity. The electrical and thermal properties of BCB and
polyimide are compared in Table 3.1 [61]. The curing temperature of BCB is also much
lower than that of polyimide. Also, BCB has a low moisture pick-up: <0.25% at 85%
relative humidity [62]. Hence, it is more suitable to be used in post-IC process. Another
important property of BCB is that there is no interaction between BCB and copper.
Accordingly, high-conductivity copper can be employed as the metal layer on BCB.
BCB
2.65
8 x 10-4
3 x 106
1 x 1019
250
P ro p erty
Dielectric Constant (1 kHz -- 20 GHz)
Dissipation Factor (1 kHz —1 MHz)
Breakdown Voltage (V/cm)
Volume Resistivity (Q-cm)
Curing Temperature (°C)
Polyimide
3.3
1.8 x 10'3
3 x 106
1.5 x 1017
400
Table 3.1: Electrical and thermal properties of BCB and polyimide.
3.1.2. Coating Process
3.1.2.1.Surface processing
The surface to be coated with BCB must be free o f all organic impurities and other
contaminations. Hence, the wafer must be cleaned using oxygen plasm a for 10 minutes
before processing. Then, an adhesion promoter, AP3000, is used to enhance the
adhesion between the silicon oxide surface and the BCB. The adhesion promoter is spun
coated on the wafer surface at 4000 rpm for 30 seconds.
29
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.1.2.2.BCB Coating
After the adhesion promoter is spun dry, photosensitive BCB is spun onto the
substrate surface. Firstly, the substrate is spun at 500 rpm to spread the BCB out from
the center of the substrate. Then, the substrate is spun at a speed that the desired
thickness to be achieved for 30 seconds. The final thickness of the BCB is also
determined by the series of the CYCLOTENE used. The typical thickness of
CYCLOTENE before and after baking is summarized in Table 3.2. Next, the film should
be heated on a hot plate for 30 seconds to drive out residual solvent. Temperature of the
hot plate is set according to the BCB thickness and the data listed in Table 3.3.
Spin Speed (rpm)
1500
2000
2500
3000
3500
4000
5000
CYCLOTENE 4022
after soft bake final thickness
5.2
6.9
5.8
4.3
3.8
5.2
3.4
4.7
4.4
3.1
2.9
4.1
2.6
3.7
CYCLOTENE 4024
after soft bake final thickness
10.2
7.2
8.4
5.9
7.4
5.2
6.7
4.8
6.2
4.4
5.8
4.1
5.2
3.7
Table 3.2: Typical CYCLOTENE thickness after soft bake and hard bake.
CYCLOTENE pre-exposure thickness (pm)
< 4 .5
4.6 - 6.6
6.7 - 8.7
8.8 - 10.0
10.1 - 11.4
1 1 .5 -1 5 .6
> 15.7
H ot Plate Temp (°C)
70
75
80
85
90
95
100
Table 3.3: Pre-exposure hot plate soft bake temperature.
3.1.2.3.BCB D evelopm ent
BCB is a negative photoresist (exposed regions are crosslinked and will remain
behind after development). After a soft bake, the substrate has to be cooled down to
30
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__________________ Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
room temperature before photolithography. The exposure dose is determined by the
thickness of the pre-exposed film as shown in Table 3.4. After the exposure, the film is
heated at 10°C below the pre-exposure temperature shown in Table 3.4 for 30 seconds to
stabilize the development endpoint time. The exposed film is developed using DS2100
developer for 2 minutes and spun dry at 4000 rpm for 30 seconds. The post-develop
bake is conducted at 60 - 90°C for 60 seconds.
CYCLOTENE
4022
4024
Exposure Dose (m j/cm 2 per pm)
20
25
Table 3.4: Exposure dose for different CYCLOTENE.
3.1.2.4.BCB hard cure and descum
With the completion of the photolithography and development process, the film
has to be cured. As BCB will be oxidized in an oxygen-containing ambient at
temperature above 150°C, the film is cured under an inert ambient with a ramping
profile shown in Figure 3.1.
Ramping profile
40'
210°C---------- 210°C
150°C
150°C
room temp.
Figure 3.1: Curing profiles for BCB in an inert ambient.
A thin layer of polymer of less than 1000A is left behind after the develop process.
Therefore, a descum process that can remove 1000A - 2000A of polymer is sufficient.
As there is silicon inside BCB, the descum process cannot be done in a pure oxygen
31
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
environment. Typically, the descum process is carried out in an O 2/SF 6 ambient. The
complete processing procedures of BCB are shown in Figure 3.2.
c
Oxygen plasm a
surface cleaning
UV exposure
Pre-devclop soft
bake
Adhesion Prom oter,
,
A 1*3000
>
D
Developer, DS2100
Spin Dry
\f
Post-develop soft
bake
Spin C oat BCB
C
I lo t plate soft bake
H a rd C ure
c
J
Descum
J
Figure 3.2: Process Description for Cyclotene.
3.2. Thin-film Passive Components
A low-loss 50-Q thin-film microstrip line and a 10-GHz low-pass filter as shown
in Figure 3.3 and Figure 3.4 were designed and fabricated on 6-pm BCB dielectric on a
low-resistivity silicon, where W is the metal width, t is the metal thickness and h is the
BCB thickness.
32
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
Oxide
Si
Figure 3.3: Cross-section schematic of the thin-film microstrip line (TFMS).
TiW/Cu ■
BCB
Oxide
Figure 3.4: Cross-sectional schematic of a 10 GHz low-pass filter.
3.2.1. Filter Design
The 10 GHz low-pass filter was designed using microstrip lines. For a third order
3-dB equal-ripple low-pass filter, the normalized low-pass prototype element values [55],
[63], [64] are gj =1.5963 , g2 = 1.0967 g3 = 1.5963 and g 4 = 1.0000, which is shown in
Figure 3.5. Richard’s transformation was used to convert series inductors to series stub
and shunt capacitors to shunt stubs. All stubs are -V8 long at resonant frequency, a>c . As
series stub is difficult to be implemented, Kuroda identities are used to convert the series
stubs to shunt stubs as shown in Figure 3.6 and the dimensions and characteristics
impedance of each individual section are summarized in Table 3.5.
33
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Chapter 3 —Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
g4
Figure 3.5: Lumped-element low-pass filter prototype.
1270pm
2720.5jj.rn
2720.5pm
1270pm
15.2 pm
2.57 pm
2547pm
2652pm
2652pm
17.83 pm
6.06 pm
6.06 pm
Figure 3.6: Layout of the third order equal-ripple low-pass filter.
Width (pm)
Impedance, Z0 (Q)
£eff
45.6
17.83
2.16
50
15.2
2.13
6.06
81.3
1.98
117
2.57
1.87
Table 3.5: Characteristics and dimensions of the 10 GHz low-pass filter.
3.2.2. Fabrication Process
A 0.5-pm aluminum (AO metal layer (sandwiched by 0.5-pm oxide layers (both
below and above) was first fabricated (by sputtering) on the silicon substrate to simulate
a CMOS wafer after the conventional A/-based IC process. The A l layer is used as the
ground plate for both the microstrip lines and filters. A 6 -pm thick photosensitive BCB
layer was spin-coated on the silicon wafer, at 1500rpm. The BCB was patterned using
UV light, developed using DC2000 and cured at 150°C and 250°C for 30 minutes and
40 minutes respectively. Via holes (15 pm) were opened for connection between the
copper (C m) and the A l ground. Next, a thin TiW (thickness 80 nm) and Cu seed layer
34
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
(thickness 350 nm) was sputtered on the silicon wafer. A thick layer o f photoresist (6 10 pm) was coated on the wafer surface and the filter patterns were defined using
photolithography. Copper was deposited using electroplating and its thickness is
determined by the plating time and photoresist thickness. Finally, the photoresist and
TiW/Copper seed layers were removed by chemical stripping and etching. The complete
process flow is summarized in Table 3.6.
Fabrication Process Flow
1. Thermal oxidation
a. Low-temperature oxide (LTO) thickness = 0.5
pm
Cross-section schematic
0.5-pm LTO
Si
2. Aluminum sputtering
a. Aluminum (Al) thickness = 0.5 pm
b. A l layer is used as the interconnect of the
inductor and the metal plate of a capacitor
0.5-pm sputtered Al
:
3. Thermal oxidation
a. LTO thickness = 0.5 pm
Si
4. Via patterning
j
UV exposure
Testing:
Conductivity test is conducted on the Al plate to
ensure the complete opening of the via holes.
Si
5. BCB coating
a. BCB layer was spin-coated on the silicon wafer
at 1500 rpm
Si
35
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j
Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
6. BCB patterning and development
a. Hard cure at 150°C and 250°C for 30 minutes
and 40 minutes respectively
b. BCB thickness after hard cure = 6 pm
c. Via holes were opened for the connection
between the Cu and the Al layer for the inductor and
the upper plate of the capacitor
7. TiW/Cu seed sputtering
a. TiW thickness = 800A
b. Cu thickness = 3 5 0 0 A
|
UV exposure
j
Si
TiW/Cu seed sputtering
Si
8. Thick PR coating for self-aligned
electroplating
12-pm PR coating
9. Self-aligned Cu electroplating
a. Electroplated Cu thickness = 6 pm
Cu electroplating
10. PR and Cu seed removal
a. PR was removed using Acetone
b. TiW /Cu seed was removed using Ronetch
solution and hydrogen peroxide
PR and Cu removal
Table 3.6: Fabrication process flow of the passive components on thin film.
36
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.2.3. Results Analysis
3.2.3.1.Microstrip Line
The measurement result of the 50-Q thin-film microstrip line is shown in Figure
3.7. The transmission loss of the microstrip line is about 0.8 dB/cm at 10GHz, which is
much lower than that of the conventional transmission line on silicon substrate, which is
about 40 dB/cm on a silicon substrate with resistivity of 40 Q-cm [65]. The much
improved loss characteristic is owing to the low-k BCB dielectric layer between the
microstrip lines and ground, with the absence of the lossy silicon substrate.
0.14
0 . 12 >
"£
0.1
E
3
S 0.08
i/i
Hi
o
g 0.06
rQ>
to
£ 0.04
0.02
0
0
5
10
15
20
Frequency (GHz)
Figure 3.7: Insertion loss of the TFMS.
3.2.3.2.Low-pass Filter
The simulation and measurement results of the 10 GHz low-pass filter are
compared in Figure 3.8. The results agree well with each other. Below 10 GHz, the loss
is only 1.1 dB thanks to the isolation of the metal layer from the lossy substrate whereas
37
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
at 11 GHz (stopband), the loss is 4.5 dB. The return loss o f the filter is 18.1 at 10 GHz
and below 10 dB within the operating range (100 MHz to 10 GHz).
-10
-
C
Q
T3
C
Si
20 '
S^-sim
-30
-40
t
}
-60
-70
-80
-90
10
15
20
F re q u en cy [in GHz]
Figure 3.8: Comparison of the simulation and measurement results o f the 10 GHz lowpass filter.
38
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__________________ Chapter 3 —Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.3. Coplanar Waveguides
Coplanar waveguides with cross-section as shown in Figure 3.9 and dimensions
listed in Table 3.7 were designed and fabricated on BCB with different thickness.
w s
w
Figure 3.9: Cross-sectional view of the CPW on BCB dielectric.
CPW
1
2
3
4
5
S
30
40
50
70
70
W
8
10
11
18
20
Table 3.7: Dimensions of the fabricated CPWs.
3.3.1.
Fabrication Process
The CPW was fabricated on a standard CMOS-grade silicon substrate with a
resistivity of p = 20 Q-cm. A 0.5 pm oxide layer was first deposited on the silicon
substrate. A photosensitive BCB layer was then spin-coated on the silicon wafer at 1500
rpm and hard cured at 150°C and 250°C for 30 minutes and 40 minutes respectively.
The thickness of the BCB layer is 7 pm after hard cure. In order to achieve a larger BCB
thickness (e.g. 20 pm) to further reduce the substrate coupling, successive multiple
coating-curing approach was used. A new layer of BCB can be spin-coated on top of the
hard-cured BCB layer, with the assistance of an adhesion promoter to enhance the
39
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__________________ Chapter 3 —Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
adhesion between spin. The second curing was then carried out with the same curing
procedure. After three successive coating-curing steps, a 20-pm BCB layer was obtained.
No cracks were observed on the multiple BCB layers, indicating acceptable stress
strength between the BCB layers and the silicon substrate. After the BCB layer with
desired thickness has been achieved, a thin TiW (80 nm) and copper seed layer (350 nm)
was sputtered on the silicon wafer for electroplating. A thick layer (12 pm) of
photoresist was coated on the wafer surface. CPWs were then patterned on the
photoresist with deep opening trenches formed in the regions for signal and ground line.
6 p m copper was deposited in a self-aligned style on the openings in the thick
photoresist layer using electroplating technique. The thickness and smoothness of the
copper layer are controlled by adjusting the electroplating current and time. Finally, the
photoresist and Ti-W/Cu seed layers were removed by chemical stripping (using normal
organic stripping) and metal etching (Cu is removed using Shipley Ronetch PS mixed
with H 2SO 4 and H 2O and TiW is removed using H 2O 2 at 40° C). The removed thickness
in the electroplated copper layer by metal etching is negligible compared to its total
thickness. The process flow is summarized in Table 3.8.
Fabrication Process Flow
1. Thermal oxidation
a. Low-temperature oxide (LTO) thickness = 0.5
pm
2. 1st layer of BCB coating
a. BCB layer was spin-coated on the silicon wafer
at 1500 rpm
Cross-section schematic
0.5-pm LTO
Si
Si
3. 2nd layer of BCB coating
a. A new layer of BCB can be spin-coated on top of
40
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
the hard-cured BCB layer, with the assistance of
an adhesion promoter to enhance the adhesion
between spin.
b. The 2nd curing was then carried out with the
same curing procedure.
4. 3rd layer of BCB coating
a. Same procedure as in step 5.
b. Final BCB thickness = 20 pm
5. TiW /Cu seed sputtering
a. TiW thickness = 8 0 0 A
b. Cu thickness = 3 5 0 0 A
TiW/Cu seed sputtering
Thick PR coating for self-aligned
electroplating
PR coating
7. Self-aligned Cu electroplating
a. Electroplated Cu thickness = 6 pm
Cu electroplating
41
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
8. PR and Cu seed removal
a. PR was removed using Acetone
b. TiW/Cu seed was removed using Ronetch
solution and hydrogen peroxide
PR and TiW/Cu seed removal
Si
Table 3.8: Fabrication process flow of the CPW on multi-layer BCB.
3.3.2.
Results Analysis
3.3.2.I.
Effect o f CPW dimensions: line width (W) and spacing (S) on E-field
spreading in the dielectric
The propagation constant, y, of the CPWs is extracted using (2.59) from the
measured S-parameter and the effective dielectric constant can be estimated from
27Z 2^ .\ l £
imaginary part of the extracted propagation constant, y =a + jp and /? = — = —
c
=
Figure 3.10 compares the slowing factor,
.
of the CPWs with dimensions
listed in Table 3.7on 6-pm BCB. The effective dielectric constant increases with the
dimensions of the CPWs due to the wider spread of the E-field across the dielectric.
Also, for the narrow CPW, when most of the E-field is confined within the dielectric, the
effective dielectric constant is 2.56 approaching the optimum value, ^
= (er +l)/2 = 1.8.
Figure 3.11 (a) and (b) compare the performance o f the CPW with dimensions
listed in Table 3.7 with 6-pm and 14-pm BCB as interfacing layer respectively. It is
clear that the insertion loss of the CPW decreases with W, the width of the signal line,
which is contrary to the performance of a CPW on an insulating substrate. The reason is
revealed by the three-dimensional FDTD EM simulation using Zealand’s Fidelity. The
42
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
E-field distribution of the narrow CPW (S=8 jum, W=30 fum) and wide CPW (S=20 jum,
W=70 jum) with a 20-pm thick low-k BCB dielectric and the silicon substrate is shown
in Figure 3.12 (a) and (b), respectively. It is obvious that for wide CPW, there is more Efield spreading into the substrate, resulting in higher insertion loss. For narrow CPW, Efield is more confined in the low-loss BCB layer and lower loss can be achieved.
7
6
5
o
o
& 4
v
>
CO
3
3 3
o
</>
CPW5
CPW4
!W2
2
CPW1
1
0
0
5
15
10
20
25
30
F req u en cy (GHz)
Figure 3.10: Measured effective dielectric constant of different dimensions CPWs on 6
pm BCB.
43
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Chapter 3 —Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
0.9
CPW5
0.8
0.7
CPW4
0.6
TJ
CPW3
€PW2
0.5
c 0.4
CPW1
0.3
0.2
0.1
0.0
0
5
15
10
20
25
30
Frequency (GHz)
(a)
0.6
0.5
CPW5
0.4
CPW4
CPW3
CPW2
0.3
CPW1
0.2
0.1
0.0
0
5
10
15
20
Frequency (GHz)
25
30
(b)
Figure 3.11: Comparison of the insertion loss of the coplanar waveguide on (a) 6 jjtm
BCB and (b) 14 /Mn BCB.
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
N o. 8500 Tim e S te p
OdB » 3527.25 (V/mJ
(a)
No. 8500 Time S te p
OdB * 1835.83 [Vim]
(b)
Figure 3.12: Comparison of the E-field distribution on 20 p m BCB with a) S = 8 jum, W
= 30 jum and b) S = 20 /Mn; W = 70 jum. [Dashed line is added to outline the boundary of
the CPW and BCB for clarity]
The different degrees of E-field spreading into the substrate are also further proven
by comparing the measured characteristic impedance o f the CPWs with different
physical dimensions on different thickness of BCB shown in Figure 3.13. As the
45
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
physical dimensions (both the width and spacing) of the CPWs on thin (6 pm) BCB
increases, the characteristic impedance of the CPWs decreases. On the other hand, for
the CPWs on thick BCB (14 pm), the characteristic impedance increases slightly with
the dimensions. This can be explained by the fact that when the spacing, S, is much
larger than the BCB thickness, substrate coupling is significant. The resulting effective
dielectric constant of the wide CPWs is higher than that of the narrow ones. Hence, the
characteristic impedance, which is inversely proportional to the effective dielectric
constant, of the CPWs decreases with the physical dimensions. On the other hand, with
thick BCB, as most of the E-field is confined within the dielectric, the characteristic
impedance of the CPWs is less susceptible to the physical dimensions. The measurement
results are also validated by the results obtained from the 3-D EM simulator, Zealand’s
Fidelity (solid line) as shown in Figure 3.13.
14 nm
a
cCti
4>
6 \im
40
73
Q .
E
u
4»
-f
a>
(0
ts
a
CPW1
CPW2
CPW3
CPW4
CPW5
Figure 3.13: Characteristic impedance of the CPWs listed in Table 3.7 on different BCB
thickness. [Line: EM simulation; symbol: measurement]
46
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.3.2.2.
Effect o f CPW dimensions: line width (W) and spacing (S) on E-field
distribution
Similar results can be observed from Figure 3.14, which shows the magnitude of
the E-field at the interface between the BCB layer and the Si substrate. The electric field
of the wide CPW decreases less significantly than that o f the narrow CPW as the
distance moves away from the center of the signal line. Hence, the electric field is
widely spread along the dielectric-silicon interface. The higher the electric field and the
larger the spread of the electric field at the interface, the higher the power loss through
the low resistivity Si substrate, which explains the high-loss o f the wide CPW. This can
be further proved by comparing the insertion loss of CPW1 (S = 8 jum, W = 30 jum) and
CPW2 (S = 10 jum, W = 40 fJm) on a 14-pm BCB layer as shown in Figure 3.11(b).
When the BCB is thick enough, most of the electric field is confined in the BCB layer
where the dielectric loss is small. The insertion loss of the CPW is less dependent on the
dimensions, S and W.
In addition, when the interfacing layer is thin, e.g. 6 jum, the electric field at M,
midpoint between the signal line and the ground is exceptionally high. Hence,
significant improvement can be achieved by etching the polymer or silicon in-between
the signal line and the ground, which reduces the dielectric loss.
47
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
-40
o
-20
a
Distance from centre o f CPW (UN9
S » 8 pm, W = 30 pm
$ * 20 pm ,
W«
70 pm
Figure 3.14: E-field strength along the interface between the lossy silicon substrate and
interfacing dielectric.
3.3.2.3.
Effect of CPW dimensions: line width (W) and spacing (5) on attenuation
at low frequency
By observing the insertion loss of the CPW at low frequency shown in Figure 3.15,
we can see that the wide CPW has a better performance than the narrow one at low
frequency and vice versa at high frequency. This is because at low frequency, the overall
loss is dominant by conductive loss, which is smaller in wider signal line. Nevertheless,
at high frequency, substrate loss through the low resistivity silicon dominants the loss
mechanism and the insertion loss of the CPW highly depends on the amount of electric
field spreading into the lossy Si substrate. As a result, at 0.8 GHz, the insertion loss of
the widest CPW increases more rapidly than the other CPWs.
48
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
0.06
£
£
aii)
0.04
CPW1
CPW5
in
in
o
c
0
'€01
ein
CPW3
0.02
0.5
1.5
F req u en cy (GHz)
Figure 3.15: Performance of the coplanar waveguide on 14 pm BCB at low frequency.
0.6
0.5
6 grn
0.4
(0
(0 0.3
14 [im
O
'€
<0u 0.2
<
0.1
0.0
0
5
10
15
20
25
30
Frequency (GHz)
Figure 3.16: Insertion loss of the narrow CPW (S = 8 pm, W = 30 pm) on different
thickness of BCB.
49
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.3.2.4.
E ffect o f BCB thickness
Figure 3.16 compares the performance of the narrow CPW (S = 8 pan, W = 30 pan)
fabricated on different thickness of BCB interfacing layer: 6 pan, 14 fan and 20 pan. It is
shown that the performance of the CPW is improved by increasing the thickness of the
BCB interfacing layer. The loss per wavelength is also investigated in Figure 3.17. From
Figure 3.18, it is clear that as the BCB thickness increases from 6 pan to 20 pan, the
electric field at the interface between the dielectric and the silicon substrate decreases
drastically. Accordingly, with the use of the 20 pan BCB interfacing layer, the insertion
loss of the CPW is just 0.3 dB/mm and 2 dB/A.g at 30 GHz.
30
-«—6 um
■m— 14 um
-*—20 um
o>
20
15
10
0
5
15
10
20
25
30
Frequency (GHz)
Figure 3.17: Attenuation per wavelength of the narrowest CPW (CPW1) on different
thickness of BCB.
50
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
Si
rs
(a)
Figure 3.18: Comparison of the E-field distribution of narrow CPW (S = 8 \im, W = 30
\xm) with different BCB thickness (a) 6 \i,m and (b) 20 \xm. [Dashed line is added to
outline the boundary of the CPW and BCB for clarity]
51
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Chapter 3 - Low-loss Passives on Low-resistivitv Silicon with Low-k BCB Dielectric
3.4. Conclusion
The Chapter demonstrates the use of the low-k BCB dielectric interfacing layer to
isolate the passive components from the lossy silicon substrate. High-performance
passive components including thin-film microstrip lines, thin-film low-pass filter, and
coplanar waveguides were designed, fabricated and characterized. The insertion loss of
the microstrip line on 6 /Jm BCB at 20 GHz and coplanar waveguide on 20 jJm BCB at
30 GHz is reduced to 0.12 dB/mm and 0.3 dB/mm respectively.
52
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Chapter 4 —Edge-Suspended Coplanar Waveguides
Chapter 4
Edge-Suspended Coplanar Waveguides
The growing market of wireless and portable communications leads an increase in
the demand for low-cost, light-weight and compact radio-frequency (RF) and microwave
monolithic solution. It is desirable to integrate the active and passive circuits on a silicon
wafer due to both its maturity and low-cost. While the active transistors have
experienced steady enhancement in device performance as a result of the advancing
CMOS technology, it is still challenging to realize high-performance passive
components including coplanar waveguides (CPWs) operating at radio frequency on
standard CMOS-grade lossy silicon substrates, which normally have low substrate
resistivity in the range of 1 - 20 12-cm. Significant loss can be generated at microwave
frequencies as a result of the signal coupling into the low-resistivity silicon substrate. In
order to overcome this dominant loss factor in silicon-based microwave passive
components, various approaches have been investigated as discussed in previous
Chapter. Herrick et al. [15] implemented CPWs with etched V-grooves around the signal
line in CPW to reduce the line capacitance, and the approach is CMOS compatible. The
depth and the lateral undercut of the grooves, however, are limited by the choices of the
wet etching solution, the layout orientation and the signal-to-ground separation. Using
our novel approach, the trenches are created by the state-of-the-art deep reactive ion
etching and lateral undercut is created by anisotropic wet etch. Hence, the initial depth
of the trenches and the amount o f lateral undercut can be chosen freely by controlling
the time of ICP-DRIE and anisotropic etching. CPW designs with narrower line width
53
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Chapter 4 - Edge-Suspended Coplanar Waveguides
and line
spacing can be implemented for high-density high-performance RF
interconnects.
Strohm et al [10] also proposed the removal of the substrate materials in the gap
between signal and ground metal of the CPWs on HRS substrate. However, as substrate
coupling is not a dominating factor in CPWs on HRS, the improvement in loss-perlength is limited. At the same time, due to the removal o f the substrate, the effective
dielectric constant decreases and the wavelength increases. Accordingly, the loss-perwavelength remains unchanged.
In this Chapter, we demonstrate an edge-suspended CPW (ESCPW) structure with
reduced attenuation using CMOS compatible micromachining techniques on lowresistivity silicon. This Chapter will be organized as follows. The working principles of
ESCPW are discussed in Section 4.1 with EM simulation. Section 4.2 depicts the
detailed fabrication process. Measurement results are analyzed and RLGC parameters
are extracted in Section 4.3. The cross coupling between adjacent finite ground ESCPWs
is investigated in Section 4.4.
4.1. Working Principles
The edge-suspended CPW structure shown in Figure 4.1 features the removal of
silicon substrate around and underneath the edges of the signal (and ground) lines. At
DC and low frequencies, the current is uniformly distributed. As frequency increases,
with the skin effect and proximity effect becoming significant, the AC current is pushed
towards the edges of signal line, resulting in an uneven current distribution. The current
distribution of a conventional CPW operating at 10 GHz is simulated with the EM
simulator, IE3D based on finite-difference-time-domain (FDTD) method and is shown in
54
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Chapter 4 - Edge-Suspended Coplanar Waveguides
Figure 4.2. M ost of the current is concentrated at the two edges o f the signal line. The
current carrying portion of the line dominates the signal-to-ground coupling which is
through the air above the CPW plane and the substrate below the CPW plane as shown
in Figure 4.3. The substrate coupling represented by, Ccp, if not suppressed, can lead to
significant amount of loss in the low resistivity silicon substrate, degrading the
performance of silicon-based CPWs. By removing the silicon not only in the region
between the signal and ground, but also the silicon under the edges of the signal and
ground lines, substrate coupling, Ccp, is expected to be suppressed significantly, leading
to greater reduction of loss in the edge-suspended CPW.
SiO
ICP +
a n is o tr o p ic
etch
Figure 4.1: Cross sectional schematic of the edge-suspended CPW (ESCPW).
55
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Chapter 4 - Edge-Suspended Coplanar Waveguides
OdB
-2 #
-IdB
■M
-6<8
G
12#
um
2(1 tiB
-22 dB
•21*
-2 6 #
•2 8 #
-30#
Figure 4.2: Simulated current distribution in a CPW operating at 10 GHz.
cu rre n t
crow ding
SiO
m
■
^sub
tu b
$
4
C...,
Figure 4.3: Cross-sectional view showing the current distribution and the edgesuspended CPW with reduced substrate coupling.
4.2. Fabrication
4.2.1. Process design
To fabricate the edge-suspended structure, the silicon etching process needs to be
designed such that controllable etching can be obtained in both the lateral direction and
the vertical direction, as shown in Figure 4.3. Considering that the lateral undercut is
usually limited by the wire width, a vertical etching process needs to be first carried out
to obtain deep trenches next to the wires. Inductively coupled plasma deep reactive ion
56
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Chapter 4 - Edge-Suspended Coplanar Waveguides
etching (ICP-DRIE) is suitable because of its capability of creating high aspect ratio
trenches with vertical sidewalls. Subsequently, it is necessary to remove silicon laterally
and create the undercut beneath the edges of the wires. There are two choices for this
etching process. One is vapor-phase isotropic dry etching using xenon difluoride (XeF 2)
and the other is wet-etching (isotropic or anisotropic). Vapor-phase isotropic etching
equipment is quite specialized and not commonly available. The wet-etching process has
the advantages of low process cost, simple equipment, better surface smoothness and
lower environmental pollution. To achieve the undercut in the edge-suspended structures,
it is desirable to at least maintain and even extend the vertical walls generated by the
ICP-DRIE during the wet etching, a feature that comes naturally for anisotropic wet
etching. The anisotropic wet etching must fulfill the following criteria: 1) CMOS
compatible; and 2) highly selective for the metallization layer (A1 here) and oxide layer.
< 100>
<!!()>
< 100>
m ajor cut of
the wafer
Figure 4.4: Crystal orientation of the wafer and the etching faces.
57
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Chapter 4 - Edge-Suspended Coplanar Waveguides
Wet-etching techniques for MEMS process are usually anisotropic because of their
good controllability over the etching profile. For silicon substrates used in CMOS
process, (100) is the crystalline orientation of choice because it offers the best carrier
transport properties. Many etching solutions, including potassium hydroxide (KOH),
ethylenediamine-pyrocatechol (EDP), and tetramethyl ammonium hydroxide (TMAH),
have been used for anisotropic etching. EDP is toxic and ages fast. Hence, it should be
avoided. KOH is easy to use and provides excellent etching profiles. However, it has
poor selectivity between Si and Si02, and more importantly, it induces plenty of K+ ions
that would contaminate CMOS devices seriously. TM AH is emerging as a favorable
choice in MEMS technology because of its high compatibility with CMOS process as it
has no K+ ions contamination. It also offers benefits including easiness of handling,
smooth surface finish and low toxicity. Since the A1 pads (for probing and bonding) are
exposed during the etching process, it is necessary that the wet etching does not attack
Al. It is observed that a 5 wt% TMAH solution has an A1 etch rate of 0.75 pm/min [66],
not acceptable for MOS compatible process when Al pads are exposed. TMAH with
appropriate Si mixing can drastically reduce the Al etching rate. The etch rate as low as
0.01 pm/min has been demonstrated [67]-[68]. It is believed that the aluminum surface
is protected from the etchant by the alumino-silicate passivation layer formed during the
etching process [69]. Recently, several groups have demonstrated that adding strong
oxidants such as ammonium persulfate (NHO 2S2O 8, ammonium carbonate (NFL^COs or
ammonium hydrogen phosphate (NFLj^HPOa can help to reduce TM AH’s etching rate
of aluminum to negligible levels, and at the same time, avoid the formation of hillock
and reduce the roughness on the silicon surface [70],
58
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________________________________ Chapter 4 - Edge-Suspended Coplanar Waveguides
In this work, we prepare an etching solution of 5 wt% TMAH mixed with 0.5 wt%
(NH4)2S20 8 and 1.6 wt% dissolved silicon to realize the lateral undercut along the (100)
direction.
4.2.2. Layout
TMAH is a class of chemicals referred to as quaternary ammonium hydroxides.
It is an anisotropic etchant that exhibits different etch rate on different crystal orientation
plane, i.e., commonly {110}> {100} > {111}. The etch rates o f the {100} and {110}
planes can vary with the etchant conditions, such as the PH-value, temperature and
doping concentration of the silicon substrates. Although the {111} planes’ etch rate has
the same variability, it is always the minimum compared to that of the other orientation
planes and the {111} planes have been accepted to be the non-etching planes. As the
{111} planes provide the etching stops, it is necessary not to expose them to TMAH
during the wet etching so that the amount of undercut can be simply controlled by the
etching time and the sidewalls remain vertical. Which orientation plane is introduced
initially depends on the geometry and the orientation of the mask features. Focusing on
CMOS-compatible process, only (100) wafers with <110> primary orientation flat as
shown in Figure 4.4 will be discussed here. Provided a square mask opening is
accurately aligned with the primary orientation flat, i.e., the < 1 10> direction, only {111}
planes will be introduced as sidewalls from the very beginning o f the etching which is
54.7° to {100} as shown in Figure 4.4(a). In this case, the cross-section o f the etching pit
is a V-shaped groove with <110> edges and {111} sidewalls and almost no lateral
undercut is created beneath the masks because of the non-etching {111} plane. In order
to obtain vertical sidewalls instead of 54.7° {111} sidewalls which is illustrated in
59
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________________________________ Chapter 4 - Edee-Susnended Coplanar Waveguides
Figure 4.4 (b) [70], a special layout orientation is proposed. The {100} planes must be
exposed at the initial etching stage. It can be seen in this figure that there are {100}
planes perpendicular to the wafer surface and that their intersections with the wafer
surface are in <100> directions. These <100> directions have 45° angle with the wafer
primary orientation flat, i.e., the <110> direction. Consequently, aligning the square
mask opening with these <100> directions, {100} facets are initially introduced as
sidewalls. As the bottom and sidewall planes all belong to the same {100} group, the
lateral undercut equals the vertical etch-depth and rectangular grooves are obtained. The
grooves are bounded by the slower-etching {100} planes. Although the {110} planes
commonly are etched faster than the {100} planes, whether the {110} planes will appear
at the comers between the bottom and sidewall planes depends on the etching rate ratio
of {110} and {100} planes, as illustrated in section 4.2.1.
In this work, p-type (100) silicon wafer with <110> primary orientation flat and
resistivity 15-20 O-cm are selected as the substrate in our design. To avoid the etching
stop on (111) plane and obtain the same undercut around the conducting wires, they are
not aligned to be parallel or perpendicular to the < 1 10> flat, but 45° to it and along the
<100> direction as shown in Figure 4.5 (b). In order to accurately align the structures
with the <100> direction, the layout is turned 45° on the masks and a special alignment
mark for locating the primary <110> flat is also designed.
60
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Chapter 4 - Edge-Suspended Coplanar Waveguides
Top view
Top view
Layout
(Jrn-niiilton
< 110 >
< 110>
Side view
Side view
(100)
(100)
Figure 4.5: Schematic (a) top view and (b) cross sectional view showing the influence of
the edges’ orientation on the etching profile.
4.2.3. Process Flow
We started with the (100) silicon wafer covered by 1 /on thermal oxide layer.
Aluminum metallization layer of 1 pm thick was sputtered on the wafer. CPWs were
patterned using photolithography and etched by RIE. The wafer was then passivated by
1 jum PECVD silicon oxide layer and resembled a wafer coming out of CMOS IC
process. The post-IC micromachining process started with opening etching windows
around the wires. The width of the etching windows varies from 8 /on to 20 /on. ICPDRIE was used to create deep trenches with a depth of about 15 /on. Then, the oxide
was removed from the Al pads by RIE. At last, the undercut beneath the edges of the
aluminum wires was created using TMAH-based solution at 85 °C without stirring.
61
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Chapter 4 - Edge-Suspended Coplanar Waveguides
The TMAH-based solution with dissolved silicon was prepared first. The starting
solution is 25 wt% TMAH from Moses Lake Industries, Inc., USA. This solution was
diluted with DI water to 5 wt%. Certain amount of silicon was added into this TMAH
solution and heated to 85°C until all the silicon dissolved into it. Before carrying out the
etching, ammonium persulphate (N H ^S iO g was added in the solution. The final etching
solution is 5 wt% TMAH with 1.6 wt% Si and 0.5 wt% (NH4)2S20g.
Fabrication Process Flow________
1. PECVD oxidation
a. PECVD oxide thickness = 1 pm
Cross-section schematic
1 pm oxide
2. Aluminum sputtering
a. Aluminum (Al) thickness = 1 pm
3. Aluminum patterning
UV exposure
4. Oxide mask
62
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Chapter 4 - Edge-Suspended Coplanar Waveguides
5. Oxide mask patterning using RIE
Oxide patterning
■■■■ m
6. ICP-DRIE trench formation
a. Depth of trenches = 1 5 pm
ICP-DRIE
1
7. TM AH Anisotropic wet etching
a. Temperature = 85°C
1
TMAH anisotropic etching
an isotropic etch
—
H
H-
Table 4.1: Fabrication flow of the edge-suspended CPW (ESCPW).
4.3. Results Analysis
4.3.1. Undercut Characteristic
Figure 4.6(a) and (b) are typical SEM (scanning electron microscopy) crosssectional views of the micromachined edge-suspended structure with an undercut of 8
pm at 80° and 90° observing angles respectively. It was found that if the lines are
aligned or perpendicular to the major cut of the wafer, minimum lateral undercut is
63
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Chapter 4 - Edge-Suspended Coplanar Waveguides
created since the {111} crystal plane is exposed quickly during the TM AH etching and
the etching stops at the {111} plane, creating the diamond-shape grooves as shown in
Figure 4.7.
(b)
Figure 4.6: SEM images of the edge-suspended CPW aligned at 45° with the major cut
of the (100) silicon wafer with 8-p.m undercut viewing at: (a) 90° and (b) 80°.
64
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Chapter 4 - Edge-Suspended Coplanar Waveguides
, I ' r *f<t
”J|J
■
I,* •»•
i'tt -in
E- 4, <,
. n*;>*
S
-:r
J > *
id :,
Figure 4.7: SEM image of the edge-suspended CPW aligned at 0° with the major cut of
the (100) silicon wafer after TMAH etching.
4.3.2. Characteristics of the edge-suspended CPW
CPWs with a nominal characteristics impedance of 50 Q with different line width
(W) and spacing (S) have been designed using equations (2.9) - (2.11), with design
parameters given in Table 4.2. The initial vertical etching trenches were created by ICPDRIE to either 15 pm or 30 pm in our experiments. Then, CPWs with different lateral
undercut (C/C) were created by controlling the time o f TM AH anisotropic etching. The
depth of the trenches around the metal is equal to that created by ICP-DRIE and
anisotropic etching as shown in Figure 4.8. In addition, as the metal is protected by 1 pm
of silicon oxide, the undercut underneath the metal is l-jum less than that created by the
anisotropic etching. Undercuts of 0, 5, 8, 11, 14 jum were obtained and Table 4.3
summarizes the dimensions of the trenches and undercuts created.
65
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Chapter 4 - Edge-Suspended Coplanar Waveguides
CPW 1
CPW 2
CPW 3
CPW 4
CPW 5
S (in pm )
8
10
11
18
20
W (in pm )
30
40
50
70
70
Table 4.2: Physical dimensions of various CPW designs.
UCO
UC5
UC8
UC11
UC14
A nisotropic etching (pm)
0
6
9
12
15
D epth o f trenches (pm)
15
21
24
27
30
U ndercut, UC (pm)
0
5
8
11
14
Table 4.3: Summary of the dimensions of the trenches and undercut created after 15-pm
ICP-DRIE and different amount of TMAH anisotropic wet etching.
s
}
'
w
s
t
J
ICP-DRIE
//' ' //'/ /
UC + 1 ^
/ /////
. anisodopic
'/Z '
etching
"//'tv''/ 'ZfZZZZZZZkZkZkZkZ^kZZZkJZZkZ^ ZZ/ sZZZZ\
Figure 4.8: Cross-sectional view of the edge-suspended CPW with trenches of different
depth and undercut.
On-wafer S-parameter was measured using Agilent 8722E network analyzer and
Cascade microwave ground-signal-ground (GSG) probes from 0.1 to 39 GHz. Before the
S-parameter measurement, a short-open-load-thru (SOLT) calibration was carried out
using Cascade calibration substrate. The pads-only characteristics were measured on the
“open” pad patterns to extract the pads’ parasitics. The pads’ parasitics were then de-
66
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Chapter 4 - Edee-Susnended Coplanar Waveguides
embedded from the overall CPW characteristics by subtracting the Y-parameter of the
“open” pads from the Y-parameter of the overall CPW.
4.3.3. Extracted impedance and effective dielectric constant
The characteristic impedance and effective dielectric constant of the CPWs were
extracted from the S-parameter measured from a lossy unmatched transmission line [58]
using Equations (2.33) - (2.35)
The extracted characteristic impedance and effective dielectric constant of the
narrowest CPW (CPW1) and the widest CPW (CPW5) with different degree of undercut
are compared in Figure 4.9. The extraction was carried out at 20 GHz. The impedance of
the CPWs increases as the degree of undercut increases. As the undercut gets deeper,
more high dielectric constant silicon (er = 11.4) is removed and replaced by air with
lower dielectric constant (£r = 1). Consequently, the effective dielectric constant gets
lower and characteristic impedance gets higher. Also, the narrowest CPW (CPW1) is
more sensitive to the degree of undercut since the removed silicon represents a larger
portion of the surrounding dielectric media.
67
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Chapter 4 - Edge-Suspended Coplanar Waveguides
8
C3
©
o
c
©
T3
©
70
7
CPW1
60
6
50
5
CPW 5
CL
40
4^ 5=
©
T3
30
3
E
©
3
(0
©
©
CO
20
2
CPW1
1
10
0
LRS
0
5
8
11
U ndercut (in jxm)
Figure 4.9: Measured impedance and effective dielectric constant.
4.3.3.I.
Extracted RLGC line parameters
Once y and Z are determined, the RLGC line parameters of the 1-mm CPWs can
be determined The line parameters: R, L, G, and C of the narrowest CPW (CPW1) with
different degree of undercut from 100 MHz to 25 GHz were extracted using equations
(2.38) -
(2.41). The series resistance and inductance of the CPWs are mostly
independent on the degree of undercut. The resistance of the metal depends mainly on
the conductivity of the metal while the inductance depends on the permeability, which is
unity for both air and the silicon substrate. From Figure 4.10, we can see that the shunt
capacitance decreases with increasing frequency, a result o f current and field crowding
toward the edges of the signal line. At a fixed frequency, the shunt capacitance decreases
as the undercut gets deeper, a result from the additional removal of the high dielectric
constant silicon. The shunt conductance increases as a function of the frequency, as
68
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Chapter 4 - Edge-Suspended Coplanar Waveguides
shown in Figure 4.11. This is also a result of the current and field crowding toward the
signal lines’ edges, which are located closest to the ground lines. Larger undercut favors
the reduction of shunt conductance because the current path between the signal and
ground lines through the silicon substrate has been made longer with the creation of the
undercut.
0.8
UCO
0 .7 E
£
E
UC5
0. 6 -
0 .5 UC8
UC11
UC14
0. 1 -
0 .0 10
25
F re q u e n c y (GHz)
Figure 4.10: Extracted shunt capacitance versus frequency o f the 1-mm CPW1 with
different degree of undercut.
69
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Chapter 4 - Edge-Suspended Coplanar Waveguides
3.0
UCO
2 .5 UC5
E
I 2.0E,
o>
I
£
1 .5 -
UC8
UC11
o
■§
1.0 -
UC14
o
O
0 .5 -
0.0
10
25
F re q u e n c y (GHz)
Figure 4.11: Extracted shunt conductance versus frequency o f the 1-mm CPW1 with
different degree of undercut.
The extracted resistance, conductance and capacitance of the various CPWs with
14 pm undercut but different dimensions listed in Table 4.2 are plotted from 0.1 GHz to
25 GHz in Figure 4.12 - Figure 4.14 respectively. It can be observed that as the
dimensions of the CPWs increase (CPW1 — narrowest; CPW5 - widest), the series
resistance of the CPWs decreases. The shunt conductance increases as CPWs become
wider. This can be explained by the fact that when the line spacing increases, the deeper
is the field spreading into the substrate and the higher is the resultant conductance. For
the shunt capacitance, different CPWs exhibit significant difference below 1 GHz, when
the shunt capacitance is directly proportional to the line width. As frequency increases,
majority of the current and field are concentrated near the edges of the signal line. As a
result, the shunt capacitance is less dependent on the line width and converges.
Moreover, as the difference between CPW4 and CPW5 is just the separation between
70
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Chapter 4 - Edge-Suspended Coplanar Waveguides
the signal line and the ground, the resistance, conductance and capacitance show little
difference.
3.0
2.5£
2. 0 -
§ 1.5CPW1
©
1. 0 -
CPW2
CPW3
0.5
CPW4 & CPWS
0.0
0
1
Frequency (GHz)
10
25
Figure 4.12: Extracted series resistance versus frequency of the 1-mm CPWs with
different dimensions and 15-pm undercut.
3.0
CPW5
CPW4
2.5-
|
2.0 2
i
1 5 i.
CPW3
in
CPW2
3
2 1.0 8
CPW1
0.50.0
0
1
Frequency (GHz)
10
25
Figure 4.13: Extracted shunt conductance versus frequency of the 1-mm CPWs with
different dimensions and 15-pm undercut.
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Chapter 4 - Edge-Suspended Coplanar Waveguides
1.2
CPW4
1.0CPW5
| 0.8u.
Q.
S
c
s
I
o
CPW3
0 .6 -
CPW2
°-4 CPW1
0. 2 -
0.0
0
1
10
25
F requency (GHz)
Figure 4.14: Extracted shunt capacitance versus frequency o f the 1-mm CPWs with
different dimensions and 15-pm undercut
4.3.3.2.
Insertion Loss
The performance of the CPWs with different degree o f DRIE and undercut is
compared in Figure 4.15. A CPW fabricated on the silicon substrate without any DRIE
and undercut was also measured for comparison. When a vertical trench of 15 pm is
created yet no undercut is formed (UC=0), the insertion loss of the CPWs is greatly
reduced from 2.4 dB/mm to 1.05 dB/mm at 39 GHz since the substrate coupling in the
region between signal and ground is suppressed by removing the silicon. Shunt
conductance is also significantly reduced as a result of the silicon removal. As the depth
of the trench increases, the insertion loss continues to decrease. Nevertheless, the effect
becomes less prominent as the depth increases beyond 30 pm since the E-field spreading
into the substrate is limited, as shown in Figure 4.16. A comparison is given in Figure
4.17 for the capacitance and conductance of the CPWs with three different combinations
72
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Chapter 4 - Edge-Suspended Coplanar Waveguides
of vertical trench (by ICP-DRIE) and lateral undercut (UC). It can be observed that an
increase from 15 pm to 30 [Am in DRIE does not dramatically reduce the shunt
conductance and capacitance. A lateral undercut of 14 pm, however, reduces the shunt
conductance and capacitance significantly. Significant reduction in the capacitance and
conductance can be achieved by removing the silicon substrate under the edges of the
metal lines. Figure 4.18 plots the insertion loss of CPW1 with different degree of
undercut. With an undercut of 14 pm, the insertion loss can be reduced to 0.5 dB/mm at
39 GHz, which is only 0.1 dB/mm higher than a suspended coplanar waveguides on
CMOS-grade substrate reported in [10]
2.5
2.0-
DRIE=0um, UC=0um
i L5:
m
JS
:
I 1 .0 -
E=1 Sum, UC=Gum
DRIE=30um, UC=0um
0.5-
DR IE =15umJUG=14urr
0.0
30
40
Figure 4.15: Comparison of the performance of the narrowest CPW (CPW1) with
different degree of DREE and undercut.
73
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Chapter 4 - Edge-Suspended Coplanar Waveguides
GdS«3000|V*!n>
G
-4
I
•6
II
s 1'
■!-22:
•24
-2&
^_
-28
-30-32:
-34
Si
-38-40
Figure 4.16: E-field distribution of an edge-suspended CPW using FDTD method.
[Dashed line is added to outline the boundary of the CPW for clarity].
0.8
DRIE=14um, UC=0um
DRIE=14um, UC=0um
0.7-
0.6DRIE=30um,
DRlE=30um, UC=0um
0.5-
-
2.0
n
o
o
ST
-1.5
S 0.4-
3
o
(D
*3
m
0.3-
1.0
3
3
0.2-0.5
0.1DRIE=15um, UC=15um
0.0
0.0
0
1
Frequency (GHz)
10
25
Figure 4.17: Extracted substrate capacitance and conductance versus frequency o f the 1mm CPW1 with different degree o f undercut and ICP-DRIE.
74
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Chapter 4 - Edge-Suspended Coplanar Waveguides
2 .5 -
LRS
2.0
E
E
m
TD
(f)
W
o
c
O
'■c
(1)
cCO
UC=0um
UC=5
0 .5
1*7-111IT"—
a — — — —"
suspended
0.0
0
5
10
20
15
25
30
35
40
Frequency (GHz)
Figure 4.18: Comparison of the insertion loss in C P W l’s with different undercut
length (UC).
With a fixed 14-p.m undercut, the insertion losses of CPWs with different physical
parameters listed in Table 4.2 are compared in Figure 4.19. The insertion loss increases
with larger physical dimensions. This trend is opposite to what is observed in CPWs on
insulating material or suspended structure [9]-[10]. As shown in Figure 4.10 and Figure
4.11, the major factor resulting in higher insertion loss for larger CPWs is the higher
shunt conductance. The current path between the signal and ground line consists of two
parts of silicon in series: 1) supporting silicon underneath the center of the signal line;
and 2) silicon substrate. For wider lines, the supporting silicon ridge is wider and
75
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Chapter 4 —Edge-Suspended Coplanar Waveguides
provides higher conductance. In order to further reduce the loss, wider CPWs with more
undercut should be used.
For the use of the CPWs for phase changing components, such as the A/4 lines, it
is important to characterize the improvement in attenuation per wavelength (dB/Ag) as
shown in Figure 4.20. With the removal of the substrate, the effective dielectric constant
is reduced. The measured effective dielectric constant with different amount of lateral
undercut is shown in Figure 4.22. It is obvious that the larger is the lateral undercut, the
lower is the effective dielectric constant and hence, the longer is the wavelength. To
improve the attenuation per wavelength, the reduction in attenuation must be larger than
the increase in wavelength. As shown in Figure 4.17, as frequency increases, substrate
loss dominates the overall loss of the CPWs on the low-resistivity substrate and the
attenuation improvement that can be achieved by the suspended structure increases.
Accordingly, the attenuation-per-wavelength of the edge-suspended CPWs decreases
much faster with frequency than the CPWs fabricated on the LRS directly. The
attenuation-per-wavelength of the edge-suspended CPW with 11-pm lateral undercut is
lower than that of the CPWs on LRS after 3 GHz and is 68% lower than that of the
CPWs on the LRS at 39 GHz. Moreover, as the effective dielectric constant depends on
the amount of lateral undercut created, the characteristic impedance of the ESCPWs with
different lateral undercut is different. The relationship between the measured insertion
loss at 40 GHz and characteristic impedance of the narrowest ESCPWs (CPW1) with
different amount of lateral undercut is plotted in Figure 4.21.
76
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Chapter 4 - Edge-Suspended Coplanar Waveguides
CPWS
CPW 4
0
5
10
15
20
25
30
35
40
Frequency (GHz)
Figure 4.19: Comparison of the performance of the CPW with different dimensions with
15-pm undercut.
35
30-
c
1
§S 150Q>.
a»
UC5
C
o
3 10£
<
CO
C
LRS
UC8
UC0
5-
0
UC11
5
10
15
20
25
Frequency (GHz)
30
35
40
Figure 4.20: Measured attenuation-per-wavelength (dB/4g) of the ESCPWs with
different lateral undercut (UC).
77
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Chapter 4 - Edge-Suspended Coplanar Waveguides
♦ LRS
UC11
50
55
60
65
70
75
Characteristic im pedance (O)
Figure 4.21: Insertion loss of the narrowest ESCPWs with different lateral undercut and
characteristic impedance at 40 Hz.
20
15
£
co
10 -
LRS
5-
UCO
JJC5
5j
UC11
0
5
10
15
20
25
30
UC8
35
40
F req u en cy (GHz)
Figure 4.22: Measured dielectric constant of the ESCPWs with different lateral undercut
(UC).
78
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Chapter 4 - Edge-Suspended Coplanar Waveguides
4.4. Crosstalk between Finite Ground ESCPWs
With the increasing demand for high-density and compact RF front ends for high
data rate wireless communication, it is important not only to have low-loss on-chip
passives but to achieve high-isolation between the integrated passives and the active
circuitry. In this section, the measured cross-coupling between the finite-ground edgesuspended coplanar waveguides is investigated.
4.4.1. Layout and measurement set-up
In hopes of achieving compact design, the finite ground planes are shared by
adjacent ESCPW as shown in Figure 4.23. The width of the common ground plane is
200 jtm. The forward coupling is defined as 20logSn•
Ctmmtm
Signal
Ground
C
o m itw n
G w und
S tg rm /
Common
Ground
Part4
Port 3
2 0 9 to n
IC
'IM
M
M
t
i*r+/
m w rv 4.i«4tMl li\
u iiKoiriipk
UOMlua
Port 2
P & rtl
(a)
m
Figure 4.23: (a) Cross-section schematic and (b) top view of the ESCPWs.
4.4.2. Measurement Results Analysis
The forward coupling between the narrow (CPW1) and wide (CPW5) adjacent
ESCPWs with different amount of lateral undercut is shown in Figure 4.24(a) and (b)
respectively. From the measurement results, it is obvious that at low frequency, the
crosstalk between the adjacent ESCPWs without lateral undercut (UC = 0 jum) is higher
79
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Chapter 4 - Edge-Suspended Coplanar Waveguides
than those with lateral undercut and the results reverse at high frequency. This can be
explained by the difference in coupling mechanisms at low and high frequencies. At low
frequency, the coupling is mainly through the substrate, which is stronger in the
ESCPWs without lateral undercut. As frequency increases, the coupling is through the
air to the adjacent ESCPWs. The more is the amount of lateral undercut, the wider the Efield is spread. Hence, the crosstalk between adjacent ESCPWs increases with the
amount of lateral undercut as frequency increases. The results are further proven by
comparing the forward coupling between the adjacent o f narrow and wide ESCPWs as
shown in Figure 4.24(a) and (b). It can be observed that the crosstalk between narrow
ESCPWs is higher than that between wide ESCPWs at low frequency and the trend
reverses at high frequency. At low frequency, coupling through the substrate is stronger
for closely-packed narrow ESCPWs. Nonetheless, at high frequency, coupling is through
the air. Since E-field is more confined for narrow ESCPWs, the coupling through the air
is less and the cross-coupling between adjacent narrow ESCPWs at high frequency is
lower. The maximum cross-coupling of the 6-mm long narrow ESCPW with 12-pm
lateral undercut at 25 GHz is -23 dB, which is comparable to CPWs on thick polyimide
[59] with common ground.
80
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Chapter 4 - Edge-Suspended Coplanar Waveguides
-20
-25
m
■u
n
in
d> -30
c
Q.
3
I
-3 s
i
o
■ uco
L i.
UC6
—• — UC12
45
0
5
10
15
20
25
F req u en cy (GHz)
(a)
-20
S ' -30
■p
n
<n
d)
o. -40
3
8
i
£ -50
—■—UCO
— UC6
• UC12
-60
0
5
10
15
20
25
Frequency (GHz)
(b)
Figure 4.24: Measured cross coupling between (a) narrow and (b) wide ESCPWs with
different amount o f lateral undercut.
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Chapter 4 - Edge-Suspended Coplanar Waveguides
4.5. Conclusion
In this Chapter, a novel edge-suspended CPW structure is demonstrated using
CMOS-compatible fabrication process. Detailed layout design and fabrication process
are presented. Edge-suspended CPWs using CMOS-standard aluminum metal can
achieve an insertion loss as low as 0.5 dB/mm at 39 GHz on low-resistivity silicon
substrate. Moreover, the attenuation-per-wavelength is reduced significantly by 68% (3
dB/Ag at 39 GHz) comparing with the CPW fabricated on the CMOS substrate directly.
With deeper vertical trench and implementation of high conductivity metal (such as
copper), the edge-suspended CPWs are expected to provide even smaller insertion loss.
An important advantage of the edge-suspended CPWs is that the ESCPWs possess
strong mechanical support and reliability. The line parameters of the CPWs with
different ICP-DRIE and anisotropic etching were extracted from the measured Sparameter. The extracted parameters and the EM simulation further explain the working
principles of removing the silicon along the edge of the CPW using ICP-DRIE and
anisotropic etching. The crosstalk between adjacent ESCPWs with different amount of
lateral undercut is also investigated.
82
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
Chapter 5
Computer-Aided Design (CAD) Equivalent
Circuit M odeling o f Edge-Suspended
Coplanar W aveguides
In previous Chapter, a CMOS-compatible micromachined edge-suspended
coplanar waveguide is proposed to compromise mechanical support and performance.
W ith the partial removal of the silicon using inductively-coupled plasma deep reactive
ion etching (ICP-DRIE) and anisotropic etching, an edge-suspended coplanar waveguide
with an insertion loss of 0.5 dB/mm and 3 dB/Ag at 40 GHz has been achieved. As
substrate effect dominates the overall loss in interconnects on lossy substrate, the RLGC
line
parameters
become frequency-dependent.
Nonetheless,
frequency-dependent
parameters are not currently supported in most of the transient circuit simulators. It is
important to derive compact equivalent circuit which models the frequency-dependent
effects that must be taken into consideration during the design process. In this Chapter, a
compact frequency-independent equivalent circuit model that captures the frequencydependent extracted RLGC line parameters and can be incorporated in transient circuit
simulators is proposed. In addition, the effect of lateral undercut and vertical trenches on
substrate coupling and resistance is analyzed. Moreover, the cross-coupling is modeled
by adding mutual inductance between adjacent ESCPWs model.
83
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_________________________ Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
This Chapter is organized as follows. Different propagation modes exit in CPWs
on semi-conducting substrates such as silicon are discussed in Section 5.1. Section 5.2
introduces the circuits modeling the interconnects on lossy Si substrate including
conductor and substrate skin effect. Section 5.3 shows the model parameter extraction
and Section 5.4 verifies the accuracy o f the model by comparing the simulation and
measurement results. Finally, a circuit model depicting the crosstalk between the finiteground ESCPWs is shown in Section 5.5.
5.1. Propagation Modes in CPWs on Semi-conducting
Substrate
Different propagation modes depending on the conductivity of the substrate, the
operating frequency and the CPW dimensions exist in interconnects on semi-conducting
substrate [72], The modes of propagation including slow-wave mode, dielectric quasiTEM mode and skin-effect mode are governed by two critical frequencies. Firstly, it is
the relaxation frequency,/;, which is given by,
2 7TB0£ s
(5.i)
where crs is the substrate conductivity, es is the dielectric constant o f silicon and £o is the
permittivity of free space.
The second one depends on not only the operating frequency and substrate
resistivity but also the CPWs dimensions. The quasi-TEM analysis assumes a field
penetration depth smaller than the semi-conductor skin-depth, which is given by
s,=
, 1 ,
84
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(5-2)
Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
where jUois the permeability constant. From Davis et al [73], it can be estimated that the
quasi-TEM field penetration is (S/2+W). Hence, to ensure that the field is propagating in
quasi-TEM mode in the CPWs, the operating frequency must be smaller than
at
which the skin depth equals to (S/2+W):
f 2=
A
vT
7rasJu0(S/2 + w)
(5.3)
Accordingly, the quasi-TEM analysis is valid within frequency range: / «
f «
f x and
f 2 . The three operating modes can be defined from the two critical frequencies.
For / j < / < f 2 , transverse electric and magnetic fields freely penetrate the semi­
conductor substrate and propagation mode is in quasi-TEM mode. For f 2 < f < / , , the
propagation mode is in skin-effect mode, in which neither electric field nor magnetic
field freely penetrates into the substrate. Finally, for / «
f l and f « f 2 , the
propagation mode is in slow-wave mode and only the magnetic field penetrates the
semi-conductor but not the electric field. With the CMOS-grade silicon substrate
(p s i= 2 0 Q-crri) that we used in the fabrication, the frequency boundaries of the narrowest
and widest CPW are plotted in Figure 5.1. It is obvious that with psi = 20 £2-cm, the
propagation mode changes from slow-wave mode to quasi-TEM mode from 0.1 GHz to
40 GHz.
85
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Chapter 5 - CAD Equivalent Circuit M odeling of ESCPWs
100
Skin-Effect Mode_
Narrow CPW
Wide CPW
f=f2 :
10
E
V
a
'N , (
Slow-Wave Mode
s
,>
o
TC3J
o
o
0.1
Dielectric
Quasi-TEM' Mode
psi = 20 Q-crn
0.01
1
10
100
1000
Frequency (GHz)
Figure 5.1: Different propagation mode of interconnects on different substrate
conductivity at different frequencies.
5.2. Modeling of the Edge-Suspended CPW (ESCPW)
As discussed in Chapter 4, CPWs with a nominal characteristics impedance of 50
Q with different line width (W) and spacing (S) have been designed as shown in Figure
5.2, with design parameters given in Table 5.1. The initial vertical etching trenches were
created by ICP-DRIE to either 15 pm or 30 pm. Then, CPWs with different lateral
undercut (UC) were created by controlling the time of TM AH anisotropic etching. The
depth of the trenches (DT) around the metal is equal to that created by ICP-DRIE and
anisotropic etching. Undercuts of 0, 5, 8, 11, 14 pm were obtained and Table 5.2
summarizes the dimensions of the trenches and undercuts created.
86
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
W
5
—
► -
ICP-URIE
DUE -
created b\
a n isotropic
clciiiiii;
•upporting Si s
Figure 5.2: Cross-section of the edge-suspended coplanar waveguide.
CPW 1
CPW 2
CPW 3
CPW 4
CPW 5
S (in pm )
8
10
11
18
20
W (in pm )
30
40
50
70
70
Table 5.1: Physical dimensions of various CPW designs.
uco
UC5
UC8
UC11
UC14
A nisotropic etching
(pm)
0
6
9
12
15
D epth of trenches, D T
(pm)
15
21
24
27
30
U ndercut, UC
(pm)
0
5
8
11
14
Table 5.2: Summary of the dimensions of the trenches and undercut created after 15-pm
ICP-DRIE and different amount of TMAH anisotropic wet etching.
A typical equivalent circuit of interconnects operating in slow-wave or quasi-TEM
mode is shown in Figure 5.3. The series impedance of the CPW is modeled by series
resistance and inductance. To analyze the CPW on lossy substrate, several modifications
need to be made to achieve high accuracy in modeling [74], [75].
87
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Chapter 5 - CAD Equivalent Circuit M odeling of ESCPWs
o — n r>rv'i—
■o
v w
L
R
G
_ET
Figure 5.3: RLGC equivalent circuit schematic of CPW interconnects.
First, as 2-pm A1 was used in the fabrication of the CPWs in this work, skin effect
has to be taken into consideration at high frequency. Hence, a compact ladder model
[76] as shown in Figure 5.4 is used to model the effect. In our model, the cross-section
of the conductor is divided into three layers. Each layer is represented by one ladder
section. The resistance value chosen at each layer is related by
r, / rm
= rr
(5.1)
where RR is a constant to be determined and i = 1,... ,3. First, the dc resistance of the
conductor, Roc is determined and the resistance used in the first layer o f the ladder is
(5.2)
and Or is chosen by
(5.3)
where S,
---- is the skin depth at the maximum frequency of interest,
V<°™Mo<T
J
For
a three section ladder, RR is determined by
(RR)2 +R R + ( l - a r fi) = 0
(5.4)
The inductance used in each layer is also related by
L, / Ll+l = LL
88
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(5.5)
Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
where LL is a constant to be determined, i —1,2 and the inductance used in the first
layer is given by
h = LDc/a L
(5-6)
where LDC is the inductance of the conductor at low frequency and a L = 0.315 or*. The
constant, LL, is determined by,
Compact
ladder
model
Figure 5.4: Compact ladder model for the skin effect.
In addition, a series external inductor, Lext, is used to model the inductance of the CPWs
at high frequency.
Second, the substrate coupling is modeled by the coupling capacitor from the
CPW to the silicon substrate, Cssu which consists o f C ox and C air/si■ C ox models the
capacitance of the oxide layer and C ai,/si models the coupling from the CPW to the
silicon substrate through air and the supporting substrate. The value of Ca,r/s; depends on
the amount of lateral undercut of the edge-suspended CPW. The substrate resistor, R SUb
models the current flows from the signal lines to the ground through the low-resistivity
substrate.
89
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
As the 6 -mm-long edge-suspended CPW is electrically “long” with respect to the
signal wavelength at high frequency, a six-segment lumped-element circuit model [77]
was used to model the 6 -mm edge-suspended CPW. Each segment is represented by the
equivalent circuit model shown in Figure 5.5.
Compact
ladder
model
L2
Si Substrate
C om pact
la d d er
m o d el
A /W
R sub
Figure 5.5: Equivalent circuit model used in each unit cell representing 1-mm-long
ESCPW.
90
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
5.2.1. Determination of the model parameters
All the parameters used in the model discussed in the above section can be
extracted from the measurement results. First, the values of the resistors and inductors
used in the compact ladder model were determined using the method as discussed in
previous section. The resistance and inductance extracted from the measured Sparameter of the narrowest CPW at 100MHz are used as Roc and LDc in (5.2) and (5.6)
respectively. The maximum frequency of interest, f nax is chosen to be 25 GHz and the
thickness of the A l metal used is 2 pm. Using (5.3), (Xr is calculated as 2.54. The values
used in the ladder model of the narrowest CPW (CPW1) with 15-pm lateral undercut are
calculated using (5.1) to (5.7) and are summarized in Table 5.3. As resistance and
inductance depends on the ESCPW s’ physical dimensions as listed in Table 5.1 and the
amount of undercut, Rdc and Ldc used in the model o f the ESCPWs with different
dimensions were fine-tuned by factors, lr and If respectively. The dc resistance and
inductance used in different ESCPWs are Roc-lr and Ldc i f respectively and Rj, R 2, R 3 ,
Li and L 2 used in the ladder model are scaled accordingly. The external inductance, Lext
was estimated from the extracted inductance, L(f) at 10 GHz.
Parameters
Ri (Q/mm)
R 2 (Q/mm)
R 3 (Q/mm)
Li (nH/mm)
L 2 (nH/mm)
Value used
1.10
2.03
3.73
0.74
3.1
Table 5.3: Parameters used in the ladder compact model o f the narrowest CPW with 15pm lateral undercut.
From the equivalent Tt-mode shown in Figure 5.5, it can be realized that at low
frequency, signal is coupled through, Cox, Cair/si and RSUb to ground. As a result, the
91
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Chapter 5 - CAD Equivalent Circuit M odeline of ESCPWs
extracted shunt capacitance, C(f), at low frequency is equal to C ox and C air/si. As C ox only
depends on the oxide thickness which is a process parameter, it can be calculated easily.
Hence, the value of C air/si can be estimated from C(f) at low frequency after C„x is found.
At high frequency, signal is coupled through C ox, C atr/si and C sub to ground. Since C ox,
C sub, C(f) —> C ,ub at high frequency.
Cair/si and C SUb are in series and C ox, C air/si »
Therefore, C sub is equal to C(f) at high frequency. All values extracted are summarized
in Table 5.4 —Table 5.6.
LRS
UCO
UC5
UC8
UC11
UC14
Lext
(nH/m m )
0.45
0.4
0.35
0.36
0.35
0.35
C0x
(pF/m m )
0.375
0.375
0.375
0.375
0.375
0.375
Csi/air
(pF/m m )
-
3.75
0.45
0.3
0.165
Rsub
(Q /m m )
320
500
650
820
1050
1100
Csub
(fF/mm )
117
67.5
57
48
42
57
If
1.5
1.45
1.1
1.1
1.1
1
Table 5.4: Parameters used in each unit cell of the equivalent Tt-model of the ESCPWs
with 15-pm ICP-DRIE and different amount of undercut.
Cox
(pF/m m )
Csi/air
(pF/m m )
Rsub
(Q/mm )
Csub
(fF/mm)
If
(nH/m m )
0 .4 5
0 .3 7 5
-
320
117
1.5
0 .4
0 .3 7 5
-
500
67.5
1.1
0 .3 4
0 .3 7 5
-
700
57
1
L ext
DRIE0
DRIE15
DR1E30
Table 5.5: Parameters used in the equivalent Tt-model of the ESCPWs with different
vertical trench depth created by ICP-DRIE only.
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
C PW
1
2
3
4
5
Lext
(nH /m m )
0.35
0.35
0.34
0.35
0.35
Cox
(pF/m m )
0.375
0.5
0.625
0.875
0.875
Csi/air
(pF/m m )
0.15
0.45
0.9
Rsub
(Q/m m )
1100
1025
750
620
600
2.1
1.8
Csub
(fF/mm)
57
51
57
57
60
If
1
0.95
0.85
0.85
0.85
Table 5.6: Parameters used in the equivalent 7i-model of the ESCPWs with different
dimensions and undercut of 15 pm.
5.3. Model Verification
5.3.1. RLGC Line Parameters
In order to verify the model proposed in previous section, the circuit shown in
Figure 5.5 is simulated in the frequency-domain using Agilent ADS and the Sparameters are calculated. The line parameters: R, L, C and G are extracted from the
simulated and the measured S-parameters. The results are compared in Figure 5.6. The
RLGC line parameters are best fitted up to 25 GHz.
50
30
40
E
o
25
♦ ♦
♦ ♦
E
20
30
o
15 o
c
sc
$(/> 20
1
3E
*
10 ■3o
C
o
10
5 o
0
0
0
5
15
10
20
25
F re q u e n c y (GHz)
(a)
93
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
6
5
4
u.
Q.
3
2
T3
1
0
0
5
15
10
20
25
Frequency (GHz)
(b)
Figure 5.6: Comparison of the simulation results obtained by the proposed model and
the measurement results (a) resistance and conductance; (b) capacitance and
conductance. [Line: model; symbol: measured]
5.3.2. Insertion Loss
The measured and modeled insertion loss of the ESCPW with different amount of
lateral undercut, UC and depth of trenches, D T are compared in Figure 5.7 - Figure 5.8.
The model exhibits excellent agreement with the measured insertion loss of the CPWs
with different amount of undercut up to 25 GHz. It is obvious that the more the amount
of substrate removed, the better the measured result is fitted. When there is no undercut,
substrate coupling becomes significant and the loss is higher.
94
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
1.2
UCO
E
UC5
0.8
■■
<
/>
(A
UC8
o 0.6
-I
c
o
UC11
t<u 0.4
w
c
UC14
0.2
0.1
5.1
10.1
15.1
25.1
20.1
Frequency (GHz)
Figure 5.7: Comparison of the measured and modeled insertion loss o f the CPWs with
different amount of undercut. [Line: model; symbol: measured]
1.2
UC = 0 pm, DT = 15 pm
E
mJLB.
E 0.8
C
;oQ
w
-
5
UC = 0 jim, DT = 30 pm
0.6
c
o
■a>
■5 0.4
UC = 14 pm, DT = 30 pm
m
c
mM *"
■ 1""1
0.2
0.1
5.1
10.1
15.1
20.1
25.1
Frequency (GHz)
Figure 5.8: Comparison of the measured and modeled insertion loss of the CPWs with
different amount of lateral undercut, UC and trench depth, DT. [Line: model; symbol:
measured]
95
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
5.4. Results Analysis
5.4.1. Effect of Lateral Undercut
The series resistance used in the model is listed in Table 5.1 is independent of the
amount of undercut. Table 5.4 summarizes the parameters used in the equivalent Ttmodel of the ESCPWs with different amount of undercut. As the amount of undercut
increases, the series inductance decreases slightly. In addition, the supporting substrate
underneath the signal line becomes thinner and is farther away from the substrate
supporting the ground lines. Hence, the substrate resistance, RSUb increases linearly with
the amount of undercut until the CPW is almost completely suspended from the
substrate as shown in Figure 5.9(a). The coupling capacitors, Csmr and CSUb decrease
with the amount of lateral undercut as shown in Figure 5.9(b). The coupling capacitance
from the metal through the air and supporting substrate, Csmr is much larger than the
substrate capacitance CSUb- Thus, it is the dominating factor controlling the coupling
from the metal lines to the substrate. Moreover, Csmr is highly sensitive to the amount
of undercut as silicon (er = 11.8) is replaced by air (er = 1). Hence, creating the lateral
undercut is the most efficient way in reducing coupling o f the signal from the metal lines
to the lossy substrate.
96
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
1200 n
^
3
1000
-
■Q
J
800
«o
t;
600 -
V)
a>
0)
<*■*
«b .
400 -
0)
-Q
200
-
LRS
0
5
11
8
14
U ndercut (pm)
(a)
4
E
E
S
- -
0.12
- -
0.1
3
- 0.08
c 2
3
«CO
Q.
CO
O
o>
0.06
- 0.04
1
Q.
3
O
o
- -
0.02
Substrate Capacitance Csub (pF/mm)
r 0.14
0 4—
LRS
0
5
8
11
14
U ndercut (|im)
(b)
Figure 5.9: Relationship between (a) substrate resistance, R SUb', (b) coupling capacitance:
Csi/air (diamond) and CSUb (square) and the amount of lateral undercut.
97
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
5.4.2. Effect of vertical trenches by ICP-DRIE
From Table 5.6, it is obvious that by simply increasing the depth of the trench by
ICP-DRIE, substrate resistance, RSUb is increased and the substrate coupling capacitance,
CSub is reduced, which leads to the reduction in insertion loss. Nonetheless, no reduction
in the coupling from the metal lines through the air/substrate to the substrate is achieved.
Also, as the depth of the trenches increases, its effect on the reduction of the coupling
capacitance decreases.
It is important to note that when lateral undercut is created, the change in substrate
resistance is more significant than that in substrate capacitance. The increase in the
substrate resistance leads to a reduction in the insertion loss from 0.7 dB/mm to 0.4
dB/mm at 25 GHz as shown in Figure 4.18. Accordingly, creating lateral undercut is an
efficient way to reduce the loss of the CPWs on lossy substrate.
5.5. Modeling of the Crosstalk between Finite Ground
ESCPWs
The model derived in Section 5.2 can be used to investigate cross coupling between
the edge-suspended CPWs by simply adding constant mutual inductance: Mext, M j and
M 2 between the inductors in each unit cell of the adjacent ESCPWs as shown in Figure
5.10. Mext models the cross coupling between Lext of the adjacent ESCPWs. The
crosstalk between the adjacent ESCPWs due to the presence of the eddy current in the
low-resistivity substrate are modeled by M i and M 2 and their values are set to be
negative in order to match the higher crosstalk at low frequency of the narrow ESCPWs.
98
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
The measured and modeled cross coupling, S31 between narrow and wide ESCPWs with
11-pim lateral undercut are shown in Figure 5.11(a) and (b) respectively.
m
m
A/VV-----
o-
-o
JI
Ah
U
r? l T ^ i
i!
M,
ext
Figure 5.10: Mutual coupling inductance added to the external inductors and inductors in
the ladder model used in each ESCPW unit cell.
99
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
-10
m
■p
”
Vi
-20
u
d)
c
■5. -30
3
o
0
1
o
u_
-40
-50
-60
0
5
10
15
20
25
20
25
F re q u e n c y (GHz)
(a)
-10
-20
CO
C />
CL
|
-40
■S
io
-50
u.
-60
-70
0
5
10
15
F re q u e n c y (GHz)
(b)
Figure 5.11: Measured and modeled cross-coupling, S 31, between adjacent (a) narrow
(CPW1) and (b) wide (CPW5) ESCPW. [Line: model; symbol: measured]
100
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Chapter 5 - CAD Equivalent Circuit Modeling of ESCPWs
5.6. Conclusion
In this Chapter, a compact frequency-independent equivalent circuit model has
been derived for a new category of CMOS-compatible low loss (0.5 dB/mm at 40 GHz)
edge-suspended coplanar waveguides on CMOS-grade substrate. Frequency-dependent
line resistance, inductance, conductance, capacitance and insertion loss extracted from
the measured and simulated S-parameters show excellent agreement up to 25 GHz. It is
recognized that creating the lateral undercut can not only reduce the coupling from the
metal to the lossy substrate significantly, but also raise the substrate resistance that leads
to significant reduction in the overall loss of the CPWs on the CMOS-grade substrate.
The model can also be used to investigate crosstalk between adjacent ESCPWs.
101
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Chapter 6 - Through-wafer Interconnect Vias
Chapter 6
Through-wafer Interconnect Vias
In previous chapters, novel high-performance planar interconnects on CMOSgrade substrate have been proposed. In order achieve compact and miniaturized
microwave devices, high-density input/output, small footprint and small-size packaging
are needed. Hence, there is a trend for vertical integration such as Multichip Module
(MCM) which can enhance the space efficiency. In addition to applications in highdensity electronic packaging and reliable testing systems in RF MEMS [25], throughwafer interconnects (TWI) have aroused a great deal o f interest due to its versatile
applications and low parasitics. They can be used to replace bondwires that add
parasitics to the overall circuitry operating at radio frequency and count for significant
portion of the back-end production cost. Moreover, TWI vias are indispensable elements
in achieving three-dimensional structures like 3D-coil inductors and some novel
electromagnetic frequency-selective surfaces such as 3D electromagnetic bandgap
structures.
Fabrication of TW I vias involves two major processes: formation of the highaspect ration through-wafer via-holes and filling them with high-conductivity metal.
Thanks to the advent of the deep dry etching technology, via-holes with aspect ratio of
50 have been achieved on thin silicon substrates. Also, recent reports demonstrated that
via-holes can be filled partially by metal coating [26] or filled with polysilicon [27], [28].
Both of them deliver moderate electrical conductivity. Another work attempted to fill the
via-holes with Au-Sn solder using molten metal suction method [29]. By thinning down
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Chapter 6 - Through-wafer Interconnect Vias
the silicon substrate, before or after the etching of the high aspect ratio via-holes, the
difficulty in metal filling of the vias can be eased [30]-[32] and vias filled with copper
with an aspect ratio of 14 has been achieved on 100pm thick wafer [33]. Furthermore,
sacrificial wafers have to be used to facilitate the electroplating process [30], [33].
In this thesis, we report the first successful demonstration of copper-filled viaholes in 400 pm (standard for CMOS technology) thick silicon substrate using bottomup electroplating. Our motivations of fabricating TWI via-holes in thick silicon substrate
are two-fold. First, thicker substrate favors certain microwave components, e.g., patch
antennas for wider bandwidth and microstrip lines for wider line width that produces
lower resistance. The vias here are used to provide signal feeding or shorting paths.
Second, wafer thinning is normally the final step before wafer dicing and the thinned
wafers are normally too fragile to be allowed back to the standard fabrication line.
Thicker wafer allows additional processes after the via-hole formation. Furthermore,
via-holes may be blocked by the particles generated during the thinning process and
hence, the overall yield of the process will be lowered.
This Chapter is organized as follows. Section 6.1 and 6.2 describe the fabrication
technologies to achieve high-aspect ratio TWI via-holes with diameter ranging from 40
pm to 70 pm and to fill the high-aspect ratio via-holes with copper. Different resonant
structures designed for characterizing the resistance and inductance o f the vias at
microwave frequencies and the effect of the physical arrangement and distribution of
multiple vias on the shorting efficiency are discussed in Section 6.3. Finally, an
equivalent circuit model which can be simply incorporated into circuit simulation is
presented for the TWI vias in Section 6.4.
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Chapter 6 - Through-wafer Interconnect Vias
6.1. H ig h -a sp ect ratio th rou gh -w afer v ia-h oles
6.1.1. Inductively Coupled Plasma Deep Reactive Ion Etching (ICPDRIE)
In order to achieve small-size TW I via-hole on thick silicon substrate (400 - 500
pm), high-aspect ratio via-holes are needed. Inductively Coupled Plasma Deep Reactive
Ion Etching (ICP-DRIE) is used thanks to its high etching rate and high anisotropicity.
The advanced silicon etching (ASE) process consists of a sequence of alternating
etching and passivation cycles as shown in Figure 6.1 and Figure 6.2. The etching and
passivation gases are SF 6 and C4F 8 respectively. During the passivation phase, a
fluorocarbon polymer is formed over all the surfaces of the wafer, including the trenches
and vias. At the beginning of each etching cycle, the passivation layer is removed from
the bottom of the trenches or vias by the free radicals. Hence, the trenches and vias are
exposed to the free radicals and the silicon surface is exposed for isotropic etching. As
the vertical etch rate is faster than the lateral one, highly anisotropic profiles can be
achieved. In addition, as alternating process is used instead of simultaneous passivation
and etching used in conventional RIE, higher etch rate is obtained.
Flow rate
Passivation
Overlap
Etch Overlap
SF6
r 4 p8
Tim e
Figure 6.1: DRIE Bosch Process: alternating between etching and deposition.
104
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Chapter 6 —Through-wafer Interconnect Vias
CFx molecules
liv a lio n
F i n
e r
(a)
Fluorine free radicals
(c)
Figure 6.2: ASE mechanism, showing alternating passivation and etching process: (a)
fluorocarbon polymer covers all surfaces; (b) During the initial etching cycle, polymer is
removed from the base of the trench by the fluorine radicals; (c) The exposed silicon is
etched anisotropically.
105
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Chapter 6 —Through-wafer Interconnect Vias
6.1.2. Sidewall notch formation
As oxide has a good selectivity to silicon (1:300) in ICP-DRIE process, it is
usually used at the bottom of the silicon wafer during the etch-through process to avoid
the chunk of the ICP machine from being damaged. However, charges are built up at the
surface of the oxide layer as shown in Figure 6.3. Further incoming ions are repelled and
deflected onto the sidewalls, which leads to the formation of the notches. Accordingly,
the longer the over-etching time is, the larger the notch size is.
Notch
J
OXIDE
Figure 6.3: Charges are built up on the oxide layer which leads to the occurrence of the
notches at the Si/Si02 interface.
6.1.3. Fabrication
Via holes ranging from 20 pm to 70 pm were fabricated on 400 pm silicon
substrate. Thanks to the high selectivity of oxide to silicon (1:300) in the ICP-DRIE
process, a 3-pm thermal oxide is thick enough to be the etching mask for the etchthrough process of the 400-pm silicon substrate.
Each ICP-DRIE cycle lasts for 20 minutes and the process was repeated until all
40-pm via holes were etched through. To avoid the chunk from being damaged during
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Chapter 6 - Throueh-wafer Interconnect Vias
the etch-through process, a sacrificial wafer was placed underneath the target wafer
when the via-holes are 100 pm from being etched through. As the target wafer is closer
to the source after the insertion of the sacrificial wafer, the etch rate of both the silicon
and the oxide mask become faster. The etch rate was monitored throughout the process
and the etch rate of silicon and oxide before and after the sacrificial wafer was inserted
is compared in Table 6.1. The selectivity of the oxide mask to silicon decreases by half
after the insertion of the sacrificial wafer. Accordingly, the sacrificial wafer should be
avoided at the beginning of the process.
Table 6.2 compares the etch rate of the via-holes with different diameter. The
larger is the exposed area, the faster is the etch rate. SEM images of the via-hole array
with diameters of 30 pm and 50 pm are shown in Figure 6.4. It can be observed that
when the 50-pm via-holes were etched through, the 30-pm via-holes were still 50 pm
from being etched through. As via-holes with different diameters were fabricated on the
same wafer, via-holes with larger diameters were over-etched and notches were formed
at the Si/SiC>2 interface. To minimize the size o f the notches formed at the bottom of the
70 p m via holes, the earliest one that were etched through, the etching process was
stopped after all the 40 pm via-holes were etched through. The complete fabrication
process of the high-aspect ratio through-wafer via holes is summarized in Table 6.3.
Etch rate (pm/min)
Silicon
Oxide
Before the sacrificial wafer was
inserted
After the sacrificial wafer was
inserted
Relative
Selectivity
1.6
0.006
267
2.0
0.016
125
Table 6.1: Etch rate of the ICP-DRIE process throughout the fabrication process.
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Chapter 6 - Through-wafer Interconnect Vias
v ia diam eters fpm ) E tching
30
40
50
60
70
ra te (pm /hr)
73
84
90
93
96
Table 6.2: Comparison of the etch rate of the via-holes with different diameters.
(b)
Figure 6.4: SEM images of the via holes with different diameters: (a) 30 pm; (b) 50 pm.
108
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Chapter 6 - Through-wafer Interconnect Vias
Figure 6.5: Notches formed at the Si/SiC>2 interface o f the 50 jum via-holes.
Fabrication Process Flow
Cross-section schematic
1. Thermal oxidation
a. Low-temperature oxide (LTO) thickness = 3
pm
3-pm LTO
Si
2. Via-holes patterning
UV exposure
|
j
PR
Si
3. ICP-DRIE
i
W SF,
100
Dummy wafer
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\
Chapter 6 - Through-wafer Interconnect Vias
Oxide m ask removal
4. O xide m ask rem oval
a. Oxide mask was removed using BOE
etching.
PI
P|
Table 6.3: Fabrication flow of the high-aspect ratio through-wafer via-holes.
6.2. Copper-filled high-aspect ratio through-wafer vias
For the purpose of achieving low-parasitic through-wafer interconnects, the highaspect ratio via-holes were filled with high-conductivity copper. To ensure that the highaspect ratio via-holes are filled uniformly and completely, a bottom-up electroplating
process was used. The process flow is summarized in Table 6.4.
Firstly, the backside of the wafer was sputtered with a thin layer of TiW (300 A)
and copper (3000 A) seed. Then, the electroplating process was conducted in a copper
sulphate (CUSO4) solution using the set-up as shown in Figure 6 .6 . In view of the high
surface tension of the solution, a sucking force was applied on the wafer surface before
the start of the electroplating process to ensure that the C u S 0 4 solution flow into the
high-aspect ratio via-holes. Thus, Cu2+ ions can be replenished into the via holes during
the electroplating process. Agitation is also needed to ensure uniform plating. A dc
current density of 20 mA/cm 2 was used throughout the process.
During the early stage of the electroplating process, the copper electroplating
started from the backside of the wafer. The bottom of the via-holes was blocked by the
electroplated copper after which the holes got filled up from the bottom to the top. The
side-view and top-view of the half-filled 50 pm via-holes array are shown in Figure
6.7(a) and (b) respectively. After 3-hour electroplating, the 70 pm via-holes were
110
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Chapter 6 - Through-wafer Interconnect Vias
completely filled. Figure 6.8 (a) and (b) show the topview and sideview of the SEM
image of the completely-filled 70 pm via-holes. The image clearly shows that there is no
void inside the via-holes and the copper inside the via-holes was uniformly formed.
+ve electrode
-ve electrode
Plastic holder
li ’afer
C u S ( ) 4 s o lu tio n
Figure 6.6: Set-up for the bottom-up electroplating process.
(a)
111
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Chapter 6 - Through-wafer Interconnect Vias
(b)
Figure 6.7: Bottom of the via-holes being blocked after 3-hour of electroplating: (a)
top view and (b) sideview.
(a)
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Chapter 6 - Through-wafer Interconnect Vias
(b)
Figure 6.8: SEM image of the 70pm via array over-filled with copper after 3-hour
electroplating: (a) top-view and (b) side-view.
Cross-section schematic
Fabrication Process Flow
1. PECVD nitridation
a.
PECVD silicon nitride was deposited to isolate
the copper seed layer from the silicon
substrate.
2.
a.
b.
TiW/Cu seed sputtering
TiW seed = 300A
Cu seed = 3000 A
Nitridation
Cu seed sputtering
HiiiiiiHliNMl
3. Electroplating - vias being blocked at the
bottom
4. Electroplating - via-holes overfilled
Bottom-up approach
Vias overfilled
Table 6.4: Fabrication flow of filling the high-aspect ratio via-holes with Cu.
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Chapter 6 - Through-wafer Interconnect Vias
6.3. Fabrication of the Testing Structures
To characterize the impedance of the vias at microwave frequencies, testing
structures incorporating transmission lines and the vias shown in Figure 6.9 were
designed and fabricated. The microstrip transmission lines using thick copper were built
on the front side of the wafer. A planarization step must be done on the front side of the
wafer to remove any metal overfills of the via-holes, which adversely affect the
photolithography patterning. TiW/Cu seed layer with the same thickness as that
sputtered on the backside was deposited on the front side and was patterned using thick
photoresist (12 pm). Deep slots with the shape of the microstrip lines were formed on
the thick photoresist. In these slots [71], 4 pm copper was deposited in a self-aligned
fashion using electroplating and its thickness can be controlled by the electroplating time
and the PR thickness. Finally, the photoresist and the TiW/Cu seed layers were removed
by chemical stripping and etching. The process flow is summarized in Table 6.5. The
complete fabrication flow of the TW I vias is described in Appendix - 3.
Via patterns
under test
(a)
(b)
Figure 6.9: Testing structures built for vias characterization: (a) simple short and (b) Tresonator.
114
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Chapter 6 - Through-wafer Interconnect Vias
Fabrication Process Flow
Cross-section schematic
1. Planarization
a. A planarization step must be done on the front
side of the wafer to remove any metal overfills of the
via-holes.
2. Frontside TiW/Cu seed sputtering
Planarization
TiW/Cu seed sputtering
3. Thick PR coating and patterning
a. PR thickness = 12 pm
PR coating and patterning
4. Backside PR coating
a. The backside of the Cu was coated with PR to
avoid further thickening of the backside copper.
5. Frontside electroplating
Backside PR coating
Cu electroplating
6. PR and TiW/Cu seed removal
Table 6.5: Fabrication flow of the testing structures.
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Chapter 6 - Through-wafer Interconnect Vias
6.4. Vias Characterization
Microstrip lines with line width of 343 pm were fabricated. On-wafer Sparameters were measured from 100 MHz to 20 GHz using HP8722ES network analyzer
and Cascade microwave ground-signal-ground (GSG) probes.
6.4.1. TWI vias impedance
The vias impedance was characterized [74] using the simple shorts and half
wavelength T-resonator structures, as shown in Figure 6.9(a) and (b) respectively. In the
simple short configuration, the real part and imaginary part o f Z n are taken as the
resistance and reactance of the vias respectively after de-embedding. The configuration
shown in Figure 6.9 (b) occupies larger chip area but delivers higher accuracy, and is
used to investigate the effect of via arrangement as shown in Figure 6.10. Single via and
closely coupled multiple (double and quadruple) vias were fabricated and tested. The
measured resistance and inductance o f the single via and quadruple vias at 2 GHz are
summarized in Table 6.6. The frequency dependences of the inductance and resistance
from 0.5 to 20 GHz are shown in Figure 6.11 and Figure 6.12 respectively. As the
diameter becomes larger, both the inductance and resistance are reduced. Furthermore,
the inductance and resistance of the large vias are less dependent on the frequency as the
parasitic effect is relatively smaller. The inductance and resistance of the quadruple vias
are reduced compared to the single via, but not as much as 4 times smaller. This is a
direct result of mutual coupling and the proximity effect, which is further proven by
examining the charge density at the vias at the resonant frequency of the T-resonator.
116
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Chapter 6 - Through-wafer Interconnect Vias
(a)
•
• •
#
(b)
(c)
(d)
Figure 6.10: Via arrangement under test: (a) single via; (b) double vias; (c) quadruple
vias (diagonally) and (d) quadruple vias (straightly).
Via
diameter
(pm)
50
60
70
Inductance, Lc (pH)
Quadruple
Single via
vias
462.8
359.4
416.7
330.5
313.4
408.9
Resistance, Rc (£2)
Quadruple
Single via
vias
0.177
0.113
0.174
0.074
0.154
0.070
Table 6.6: Summary o f the measured inductance and resistance of the vias with different
diameters at 2 GHz.
500
5pum
450400-
60um
70um
350—
S
300-
1
250-
I
200-
S 150100
-
50-
Frequency (GHz)
(a)
117
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Chapter 6 - Through-wafer Interconnect Vias
500
450
400
50um
£> 350
s
300
I
250
70um
M 200
H 150
100
50
10
Frequency ^GHz|
(b)
Figure 6.11: Measured inductance of the one-port test structure with (a) 1 via and (b) 4
vias arranged horizontally fabricated on the 400 pm HRS with different diameter size.
iOunr
50um
70um
1
10
Frequency (GHz)
(a)
118
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20
Chapter 6 - Through-wafer Interconnect Vias
a
S
1
60u
4-
,K
50um
2
-
70um
Frequency {GHz}
10
20
(b)
Figure 6.12: Measured resistance of the one-port test structure with (a) 1 via and (b) 4
vias arranged horizontally fabricated on the 400pm HRS with different diameter size.
The charge distribution in the vias with different configurations was calculated
using the full-wave simulation tool Sonnet based on the method of moment (MoM) and
is plotted in Figure 6.13. It can be clearly observed that at the coupling sides of the vias,
the charge density is the minimum as a result of the proximity effect. In addition, at high
frequencies, the current is concentrated along the sidewalls o f the vias due to skin effect.
Hence, the resistance of the vias increases with frequency up to 20 GHz, after which the
resistance starts decreasing as the substrate coupling effect starts to offer additional
current paths.
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Chapter 6 - Through-wafer Interconnect Vias
Couioab/'sq m
7.52e-5 »
4 .5ie-S
o
□
O
7.52e-6
0 .0 0 0 0 0
(a)
(b)
CO
n
n
CO
t)
Coulonb/sqft
u
(c)
(d)
Figure 6.13: Simulated charge density in the vias at resonant frequency of the Tresonator: (a) single via; (b) double vias; (c) quadruple vias (diagonally) and (d)
quadruple vias (straightly).
6.4.2. Effect of vias arrangement
Normally, multiple parallel vias are required to provide low resistance
interconnects. However, different from DC and low frequency case, where the total
resistance is simply scaled by the number of vias, the microwave frequency
characteristics of multiple parallel vias strongly depend on the physical distribution or
arrangement of these vias [79].
The measured inductance and resistance of the 70 p m vias with arrangement, as
shown in Figure 6.9 are compared in Figure 6.14(a) and (b) respectively. It is obvious
that as the number of vias increases, the resultant inductance and resistance decrease.
Also, the inductance of the straightly-aligned quadruple vias is smaller than that o f the
120
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Chapter 6 - Through-wafer Interconnect Vias
diagonally-aligned quadruple vias. This is due to the non-uniform current distribution in
the microstrip-via transition. The current is concentrated near the leading edge of the
vias. As a result, the two leading vias in the diagonally-aligned quadruple configuration
contribute
most
to
the
current
conduction.
The
straightly-aligned
quadruple
configuration favors the efficient usage of the four vias and exhibits the smallest
resistance and inductance.
450
1 via
400
3501
I
300_
250-
2 vias
4 vias (sauarel
4 vias (horizontal)
.©
f
200-
I
150100
-
5010
Frequency (GHz}
(a)
121
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20
Chapter 6 - Through-wafer Interconnect Vias
1 via
2 vias
4-
8
4 vias (square)
1
4*
JB
»o
DC
4 vias (horizontal)
10
1
20
Frequency (GHz)
(b)
Figure 6.14: Measured (a) inductance and (b) resistance of the 70-pm vias with different
arrangement.
Full-wave simulation tool, Sonnet is used to evaluate the current distribution in
different vias. It can be recognized from Figure 6.15 that the more the number of vias
along the edge, the smaller the amount of current flows along the shorting edge, which is
a good indicator of the shorting efficiency. Also, the current density at the shorting
edges of the straightly-aligned quadruple vias is the minimum among the four
configurations shown in Figure 6.15. It can be concluded that arranging the vias in a
straight line perpendicular to the current flow is the most effective way of shorting
RF/microwave signals to the ground, which coincides the results that we observed in the
resonant frequency of the T-resonator. Moreover, the two leading vias in the diagonallyaligned quadruple configuration contribute most to the current conduction.
122
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Chapter 6 - Through-wafer Interconnect Vias
i
39.2
39.2
19.6
19.6
0.00
(b)
19.6
(c)
(d)
Figure 6.15: Simulated current distribution along the shorting edge of the T-resonator at
resonant frequency: (a) single via; (b) double vias; (c) quadruple vias (diagonally) and
(d) quadruple vias (straightly) [Dashed circle in (c) and (d) are added to outline the
boundaries of the via-holes for clarity].
The T-resonator structure shown in Figure 6.9(b) was used to provide accurate
characterization on the distribution effect of the vias. In this structure, both ends of the
half wavelength transmission lines are connected to the ground through TWI vias. A
short-circuited resonator resonates when the electrical length of each microstrip arm is
Pig/2. The resonant frequency is the frequency at which the magnitude of the reflection
coefficient, S n , is minimized. If vias are used to short the resonator, the via inductance,
Lyia, will lengthen the apparent length of the resonator by 2 A/, where Lyia =AZ* Z0 /Vp,
Zo is the characteristics impedance of the line, 50 Q and Vp is the propagation velocity.
The vertical microstrip shown in Figure 6.9(b) serves as the signal feeding line and
signal is coupled to the resonator arms through the capacitive gap at the midpoint of the
123
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Chapter 6 - Through-wafer Interconnect Vias
horizontal microstrip. The resonant frequency of a perfectly shorted T-resonator is 10
GHz. The return loss of the T-resonator with different via shorting arrangement are
shown Figure 6.16. In the presence of the inductance of the vias, the resonant frequency
of the structure is lowered. It can be observed that the straightly-aligned quadruple
configuration exhibits the lowest inductance and introduces the smallest shift in resonant
frequency, whereas the single via provides the highest inductance and largest frequency
shift.
-3
GO
•O
vias(h)
_j
3
CSC
Frequency
Figure 6.16: Return loss of the 10 GHz T-resonator with different via arrangement as a
function of frequency.
6.5. TWI vias modeling
As frequency increases, the parasitic effect introduced by the TW I vias becomes
more prominent and the effect must be taken into consideration during the design
process. An equivalent circuit model, which can be simply incorporated into circuit
simulation as shown in Figure 6.17, is derived for the TW I vias. The TW I via is modeled
124
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Chapter 6 - Through-wafer Interconnect Vias
by the frequency-dependent inductance, Lc(f) and the frequency-dependent resistance,
Rc(f) (representing the finite conductivity of the metal) and RSUb(f) (representing the
magnetic coupling).
Due to skin effect, the current penetration into the conductors varies with
frequency. When the frequency is high enough such that the skin depth is smaller than
the radius of the circular via-holes, the current starts to distribute un-evenly and becomes
crowded at the surface of the conductor. Hence, the resistance increases with frequency
and is approximated as [80]:
500x10'
(6.4)
where Rco is the resistance of the via(s) at 500 MHz.
The inductance decreases with frequency [81]-[82] as a result of skin effect and is
approximated as
(6.5)
where Lco is the inductance at 500 MHz and fio and ki are obtained by fitting the
measured 3m { Z }.
As frequency increases, the current induced in the substrate increases with
frequency and is modeled by Rsl,b, which in turn decreases with frequency and is
modeled as
(6.6)
where f so is obtained by fitting the measured 9te{Z}. All extracted parameters are
summarized in Table 6.7. A good agreement between both the real part and the
125
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Chapter 6 - Through-wafer Interconnect Vias
imaginary part deduced from the measurement results and the equivalent circuit model is
shown in Figure 6.18.
Figure 6.17: Equivalent circuit model for the TW I via.
Lc(f)
Leo
fio
(pH) (GHz)
ki
Rsub(f)
R-subO
fsO
(GHz)
0.5
0.5
470
414
35
28
1.2
1.7
550
580
2
2
0.6
0.56
0.5
0.5
364
328
25
30
1.5
1.8
1250
900
2
2
1
0.75
Rc(f)
Via diameter (|im)
Rc0
o
o
1
0
(Q)
1 via:
50pm
0.070
70pm
0.065
4 vias (straightly-aligned):
50pm
0.045
fcO
(GHz)
Table 6.7: Extracted lumped element for the TW I vias.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
ksub
Chapter 6 - Through-wafer Interconnect Vias
10
sim
mea
1 via
sim.
mea
4 v ias (in line)
o-
(a)
35
sim
30 -
1 via
lea
sim
20-
152
10-
4 vias (in line)
Frequency (GHz)
(b)
Figure 6.18: A comparison between the (a) real part and (b) imaginary part of the 70-pm
TWI vias deduced from the measurement and the equivalent circuit model.
127
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Chapter 6 - Through-wafer Interconnect Vias
6.6. Conclusion
In this Chapter, we demonstrate the use of ICP etching and copper electroplating
technology to achieve high-aspect ratio through-wafer interconnect vias on silicon wafer
with standard CMOS substrate thickness. Detailed fabrication techniques including the
ICP-DRIE and bottom-up via-holes filling are discussed. Also, the effect of via
arrangement has been investigated. Low-parasitic shorting can be obtained by placing
multiple vias along the edge of the microstrip. In consideration o f the parasitic effect of
the TW I vias at higher frequency, an equivalent circuit model, which can be simply
incorporated into common circuit simulation, has been presented.
128
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Chapter 7 - Conclusions and Future Works
Chapter 7
Conclusions and Future Works
In this thesis, we study the lossy mechanisms of interconnects on semi-conducting
substrates and technologies of integrating low-loss interconnects on CMOS-grade silicon
substrate for radio-frequency systems. Several methods that are either CMOScompatible or can be incorporated as post-IC process have been proposed. Various
approaches have been utilized to reduce substrate coupling and metallic loss which are
the two major sources of the interconnect loss. Among different interconnects, coplanar
waveguides (CPWs) that are widely used for microwave and millimeter circuits thanks
to their low dispersion, ease of integration and fabrication and wide impedance range are
studied extensively. Through-wafer vias which can be used for high-density packaging
for MEMS device testing and RF applications are studied as well. All proposed
structures are verified by simulation and measurement results.
With our contributions in the thesis, high-performance on-chip interconnects and
passive components for Si-integrated microwave systems have been achieved. In
addition, through-wafer interconnects for three-dimensional integration and the
realization of novel electromagnetic structures have been demonstrated, characterized
and modeled.
The first contribution is the study of the use of a low-k photosensitive dielectric as
the interfacing layer to isolate the interconnects from the lossy substrate and to reduce
the signal coupling. CPWs with different physical dimensions have been fabricated on
standard CMOS-grade substrate (20 12-cm) incorporating a low-k BCB interfacing layer.
129
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Chapter 7 - Conclusions and Future Works
Thick copper is employed as the metal layer by self-aligned electroplating. With the use
of a 20-pm BCB interfacing layer and a 6-fxm copper layer, a 50-Q CPW with insertion
loss of 0.3 dB/mm at 30 GHz has been achieved. In addition, the relationship between
the CPW dimensions and the BCB thickness is evaluated with the use of the FDTDbased EM simulator. As the whole fabrication process can be completed below 250°C,
the CPW can be integrated into other RE devices for M M ICs’ implementation as a postCMOS add-on process.
Seeing that the insertion of the interfacing layer is an add-on process, we are
motivated to our second contribution. We propose a CMOS-compatible edge-suspended
structure created by inductively-coupled plasma deep reactive ion etching (ICP-DRIE)
and TMAH anisotropic etching. As lossy substrate is removed along and underneath the
edges of the CPW, where the current and electric field is crowded, signals coupling to
the low-resistivity substrate can be suppressed. Using the edge-suspended structure, a
CPW with CMOS-standard aluminum metal exhibit significant reduction in insertion
loss from 2.5 dB/mm to 0.5 dB/mm at 39 GHz on low-resistivity silicon substrate. In
addition, since the trenches and lateral undercut are created by micromachining followed
by anisotropic wet etching, the depth of the trenches and line spacing are independent
from each other and CPW designs with narrow line width and line spacing can be
implemented for high-density high-performance RF interconnects. As the suspended
structure is partially supported by the silicon substrate underneath the metal centre, the
edge-suspended CPWs possess strong mechanical support and reliability. The cross­
coupling between adjacent edge-suspended CPWs is also investigated.
130
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Chapter 7 —Conclusions and Future Works
Our third contribution is the derivation of a compact CAD-oriented equivalent
circuit model, taking skin effect, proximity effect and substrate effect into consideration,
for the edge-suspended CPW. At microwave frequency, the lossy substrate has a
significant effect on the loss and dispersion properties of the on-chip interconnects.
Compact equivalent frequency-independent circuit model is needed to account for the
frequency-dependent RLGC parameters and facilitate the circuit-level analysis and
design of RF and mixed-signal circuits. A general quasi-TEM model is derived based on
the physical parameters of the fabrication process. It shows good agreement with both
the measured insertion loss and the extracted RLGC line parameters up to 25 GHz. With
the model, the relationship between the trench depth and lateral undercut created by
micromachining and anisotropic wet etching respectively and the line parameters is also
investigated. The circuit is further extended to model the crosstalk between the
suspended structures.
In the final part of our thesis, we study the fabrication of the through-wafer
interconnects for compact 3-D RF integration, MEMS testing and realization of novel
electromagnetic structures such as frequency-selective surfaces and metamaterials on
silicon. High-aspect ratio copper-filled through-wafer vias have been achieved in
standard 400-pm silicon substrate utilizing the state-of-the-art deep reactive ion etching
and bottom-up electroplating. The parasitics introduced by the TW I vias are
characterized using different testing structures and the coupling between adjacent vias is
investigated. A simple equivalent circuit model that can be incorporated into circuit
simulation has also been derived.
131
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_____________________________________Chapter 7 - Conclusions and Future Works
On-chip interconnects for silicon integrated microwave system has aroused the
interests of a lot of researchers in recent years. They are not only used in for routing and
connection but also integrated as a part of active circuits such as CPWs as the inductive
elements of traveling-wave amplifiers. In this thesis, different technologies achieving
low-loss on-chip interconnects have been studied. There are some areas for these works
to be extended to.
1. Integration of the proposed fabrication techniques with active circuits: the
proposed fabrication techniques: insertion of low-k dielectric and suspended
structures can not only achieve low-loss interconnects but also high-performance
passives such as inductors and filters. As the techniques are either CMOScompatible or can be integrated as post-IC process, low-loss passives can be
integrated with active circuits whose performance is always limited by the low-Q
on-chip passives such as inductors of LNA and CPWs of traveling amplifier to
achieve high-performance single-chip solution.
2. Application of the edge-suspended structures: micro-channels are created
along the edge-suspended structures. Different biomolecules such as blood and
protein can be placed inside the micro-cavities for the testing of the
biomolecules’ response to millimeter wave excitation as shown in Figure 7.1.
Also, as the complete fabrication process is CMOS-compatible, detection circuits
can be integrated with the testing structures at low cost.
132
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Chapter 7 —Conclusions and Future Works
M icro-cavity for p la cin g
b io m a ferials
Figure 7.1: Micro-channels for placing the biomaterials under testing.
3. Application of the through-wafer interconnects vias: with the measured and
modeled RF characteristics of the through-wafer interconnect vias, 3-D compact
electromagnetic bandgap structures that is composed of periodic LC networks as
shown in Figure 7.2 can be designed and realized on silicon substrate.
Capacitance is provided by the coupling between the top patch and the adjacent
patches and inductance is provided by the TWI vias connected to the ground
plane at the bottom of the substrate as shown in the inset of Figure 7.2.
Topvm w
Periodic LC
networks
Silicon oxide
Silicon nitride
Through-wafer vias
SID EVIEW
Figure 7.2: Topview and sideview of the electromagnetic bandgap structure, which is
composed of periodic LC network.
133
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References
R eferences
[1] J. F. Luy, K. M. Strohm, H. E. Sasse, A. Schuppen, J. Buechler, M. Wollitzer, A.
Gruhle, F. Schaffler, U. Guettich and A. Klaaben, “Si/ SiGe M M IC’s,” IEEE Trans,
on Microwave Theory Technology, vol. 43, no. 4, pp. 705-714, Apr. 1995.
[2] J. S. Rieh, L. H. Lu, L. P. B. Katehi, P. Bhattacharya, E. T. Croke, G. E. Ponchak
and S. A. Alterovitz, “X- and Ku-band amplifiers based on Si/SiGe HBT’s and
micromachined lumped components,” IEEE Trans, on Microwave Theory
Technology, vol. 46, no. 5, pp. 685-694, May 1998.
[3] K. T. Chan, C. Y. Chen, A. Chin, J. C. Hsieh, J. Liu, T. S. Duh, and W. J. Lin, “40GHz coplanar waveguide bandpass filters on silicon substrate,” IEEE Microwave
and Wireless Components Letter, vol. 12, no. 11, pp. 429-431, Nov. 2002.
[4] G. E. Ponchak, A. N. Downey and L. P. B. Katehi, “High Frequency Interconnects
on Silicon Substrates,” IEEE Radio Frequency Integrated Circuits Symp., Denver,
USA, June 1997, pp. 101-104.
[5] G. E. Ponchak and A. N. Downey, “Characteristics o f thin film microstrip lines on
polyimide,” IEEE Trans, on Components, Packaging and Manufacturing Technology,
vol. 21, no. 2, pp. 171-176, May 1998.
[6] X. Huo, Kevin J. Chen and Philip C. H. Chan, “High-Q copper inductors on low
resistivity silicon substrate with a low-k BCB interface layer,” IEEE Electron Device
Letter, vol. 23, no. 9, pp. 520-522, Sept. 2002.
[7] G. J. Carchon, W. DeRaedt and E. Beyne, “ Wafer-Level Packaging Technology for
High-Q On-Chip Inductors and Transmission Lines,” IEEE Trans, on Microwave
Theory and Techniques, vol. 52, no. 4, pp. 1244-1251, Apr. 2004.
[8] L. L. W. Leung, W. C. Hon and K. J. Chen, “Low-loss Coplanar Waveguides
Interconnects on Low-resistivity Silicon Substrate,” IEEE Trans, on Components,
Packaging and Manufacturing Technology, vol. 27, no. 3, Sept. 2004, pp. 507-512.
[9] T. M. Weller, L. P. Katehi, and G. M. Rebeiz, “High performance microshield line
components,” IEEE Trans. Microwave Theory and Techniques, vol. 43, no. 3, pp.
534-543, Mar. 1995.
[10]
V. Milanovic, M. Gaitan, E. D. Bowen, and M. E. Zaghloul, “Micromachined
Microwave Transmission Lines in CMOS Technology,” IE E E Trans, on Microwave
Theory and Techniques, vol. 45, no. 5, pp. 630 —635, May 1997.
134
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[11]
K. M. Strohm, Franz Josef Schmuckle, Bemd Schauwecker, Wolfgang Heintich
and Johann-Friedrich Luy, “Silicon Micromachined CPW Transmission Lines,”
European Microwave Conference, Milan, Italy, Sept. 2002.
[12]
K. Elgaid, D. L. Edgar, D. A. McCloy, I. G. Thayne, “CPW Interconnects for
MMIC Applications on Low resistivity CMOS Grade Silicon Using Micromachined
SU8 Negative Resist,” European Microwave Conference, Milan, Italy, Sept. 2002.
[13] S. J. Yoon, S. H. Jeong, J. G. Yook, Y. J. Kim, S. G. Lee, O. K. Seo, K. S. Iim ,
and D. S. Kim, “A novel CPW structure for high-speed interconnects,” IEEE MTT-S
Int. Microwave Symp. Dig., Philadelphia, USA, June 2002, pp. 771-774.
[14] Y. Kwon, H. K. Kim, J. H Park, and Y. K Kim, “Low-loss micromachined
inverted overlay CPW lines with wide impedance ranges and inherent airbridge
connection capability,” IEEE Microwave and Wireless Communication Letters, vol.
11, no. 2, pp. 59-61, Feb. 2001.
[15]
K. J. Herrick, T. A. Schwarz, and L. P. B. Katehi, “Si-micromachined coplanar
waveguides for use in high-frequency circuits,” IEEE Trans, on Microwave Theory
and Techniques, vol. 46, no. 6, pp. 762-768, June 1998.
[16]
R. Ramesham and R. Ghaffarian, “Challenges in Interconnect and Packaging of
Microelectromechanical Systems (MEMS),” IEEE Electronic Components and
Technology Conference, Piscataway/NJ, 2000, pp. 666 - 675.
[17] A. Lai, C. Caloz, and T. Itoh, “Composite Right/Left-Handed Transmission Line
Metamaterials,” IEEE Microwave Magazine, vol. 5, no. 3, Sept. 2004, pp. 34—50.
[18] C. Caloz and T. Itoh, “Electromagnetic Metamaterials: Transmission Line
Theory and Microwave Applications,” New York: Wiley, 2004.
[19] A. Sanada, C. Caloz, and T. Itoh, “Planar distribution structures with negative
refractive properties,” IEEE Trans. Microwave Theory and. Tech., vol. 47, Nov. 1999,
pp. 2509 - 2074.
[20] I. Lin, C. Caloz, and T. Itoh, “A branch-line coupler with two arbitrary operating
frequencies using left-handed transmission line,” IEEE M T T Int. Microwave Symp.
Dig., Philadelphia, PA, 2003, pp. 325-327.
[21] I. Lin, M. Devincentis, C. Caloz, and T. Itoh, “Arbitrary dual-band components
using composite right/left-handed transmission lines,” IEEE Trans. Microwave
Theory Tech., vol. 52, pp. 1142—1149.
[22] A. Sanada, C. caloz, and T. Itoh, “Zeroth order resonance in composite right/left­
handed transmission line resonators,” Proc. Asia-Pacific Microwave C onf, Seoul,
Korea, 2003, pp. 1588-1592.
135
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[23]
A. Sanada, M. Kimura, I. Awai, H. Kubo, C. Caloz, and T. Itoh, “A planar zeroth
order resonator antenna using left-handed transmission line,” European Microwave
Conference, Amsterdam, Netherlands, 2004, pp. 1341-13 44.
[24]
L. Liu, C. Caloz, and T. Itoh, “Dominant mode (DM) leaky-wave antenna with
backfire-to-endfire scanning capability,” Electron. Lett., vol. 38, no. 23, 2000, pp.
1414-1416.
[25]
S. J. Ok, C. Kim, and Daniel Baldwin, “High density, high aspect-ratio throughwafer electrical interconnects vias for MEMS packaging,” IEEE Trans, on
Components, Packaging and Manufacturing Technology, Part B: Advanced
Packaging, vol. 26, issue 3, pp. 302 - 309, Aug. 2003.
[26]
K. M. Strohm, P. Nuechter, C. N. Rheinfelder, and R. Guehl, “Via-hole
technology for Microstrip transmission lines and Passive elements on high resistivity
silicon,” IEEE MTT-S Int. Microwave Symp. Dig., Boston, Massachusetts, 1999, pp.
581-584.
[27]
C. H. Cheng, A. S. Ergun and B. T. Khuri-Yakub, “Electrical Through-Wafer
Interconnects with Sub-PicoFarad Parasitic Capapcitance,” International Conference
on Microelectromechanical Systems, Interlaken, Switzerland, 2001, pp. 18-21.
[28]
E. M. Chow, V. C. Chandrasekaran, A. Partridge, T. Nishida, M. Sheplak, C. F.
Quate and T. W. Kenny, “Process Compatible Polysilicon-based Electrical Throughwafer Interconnects in Silicon Substrate,” Journal o f Microelectromechanical
Systems, vol. 11, no. 6, pp. 631 - 640, Dec., 2002.
[29]
S. Yamamoto, K. Itoi, T. Suemasu and T. Takizawa, “Si Through-Hole
Interconnections Filled with Au-Sn Solder by Molten Metal Suction Method,” IEEE
International Conference on Micro Electro Mechanical Systems, Kyoto, Japan, Jan.,
2003, pp. 642 - 645.
[30]
N. T. Nguyen, E. Boellaard, N. P. Pham, V. G. Kutchokov, G. Craciun and P. M.
Sarro, ‘Through-w afer copper electroplating for three-dimensional interconnects,”
Journal o f Micromechanics and Microengineering, vol. 12, pp. 395 — 399, June,
2002 .
[31]
Joyce H. Wu, Jesus A. del Alamo, and Keith A. Jenkins, “A High Aspect-Ratio
Silicon Substrate-Via Technology and Applications: Through-W afer Interconnects
for Power and Ground and Faraday Cages for SOC Isolation,” International
Electronic Devices Meeting, San Francisco, CA, Dec., 2000, pp. 477 - 480.
[32]
L. Wang, A. Nichelatti, H. Schellevis, C.de Boer, C. Visser, T. N. Nguyen and P.
M. Sarro, “High aspect ratio through-wafer interconnections for 3-D microstystems,”
IEEE International Conference on Micro Electro Mechanical Systems, Kyoto, Japan,
Jan., 2003, pp. 634 - 637.
136
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[33]
J. H. Wu, J. A. del Alamo and K. A. Jenkins, “A High Aspect-Ratio Silicon
Substrate-Via Technology and Applications: Through-W afer Interconnects for
Power and Ground and Faraday Cages for SOC Isolation,” International Electronic
Devices Meeting, San Francisco, CA, Dec., 2000, pp. 477 - 480.
[34]
L. S. Loke, J. T. Wetzel, C. Ryu, Won-Jun Lee and S. S. Wong, “Copper drift in
low-k polymer dielectrics for ULSI metallization”, Symposium on VLSI Technology
Digest o f Technical Papers, pp.26-27, 1998.
[35]
G. M. Adema, L. T. Hwang, A. Rinne and I. Turlik, “Passivation Schemes for
Copper/Polymer Thin-Film Interconnections Used in Multichip Modules”, IEEE
Trans, on Components, Hybrids, and Manufacturing Technology, vol. 16, no. 1, pp.
53-59, Feb. 1993.
[36]
T. C. Edwards and M. B. Steer, “Foundations o f Interconnect and Microstrip
Design,” 3rd ed. New York, USA, John Wiley & Sons Ltd, 2000.
[37]
G. D. Venedelin, “Limitations on stripline Q,” Microwave Journal, May 1970,
pp. 63-69.
[38]
G. S. Dow, T. N. Ton and K. Nakano, “Q-Band Coplanar Waveguide
Amplifier,” IEEE MTT-S Int. Microwave Symp. Dig., vol. 2, pp. 809-812, Long
Beach, California, June 13-15, 1989.
[39]
K. M. Strohm, J. F. Luy, F. Schmuckle and W. Heinrich, “Coplanar Ka-Band
SiGe-MMIC Amplifier,” Electron. Lett., vol. 31, no. 16, pp. 1353—1354, Aug. 1995.
[40]
M. Riaziat, S. Bandy, and G. Zdasiuk, “Coplanar Waveguides for MMICs,”
Microwave J., vol. 30, no. 6, pp. 125—131, June 1987.
[41]
R. Majidi-Ahy, M. Riaziat, C. Nishimoto, M. Glenn, S. Silverman, S. Weng, Y.
C. Pao, G. Zdasiuk, S. Bandy, and Z. Tan, “94 GHz InP MMIC Five-Section
Distributed Amplifier,” Electron. Lett., vol. 26, no. 2, pp. 91—92, Jan. 1990.
[42]
J. Eisenberg, J. Panelli, and W. Ou, “A New Planar Double-Double Balanced
MMIC Mixer Structure,” 1991 IEEE Microwave Millimeter-Wave Monolithic
Circuits Symp. Dig., pp. 69 —72, Boston, Massachusetts, June 10-11, 1991.
[43]
J. A. Eisenberg, J. S. Panelli, and W. Ou, “Slotline and Coplanar Waveguide
Team to Realize a Novel MMIC Double Balanced M ixer,” Microwave J., vol. 35, no.
9, pp. 123-131, Sept. 1992.
[44]
D. Neuf and S. Spohrer, “Double Balanced, Coplanar, Image Rejection Mixer
Uses Monolithic MESFET Quad,” 1991 IEEE MTT-S Int. Microwave Symp. Dig.,
vol. 2, pp. 843 - 846, Boston, Massachusetts, June 10-14, 1991.
137
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[45]
R. W. Waugh and R. M. Waugh, “SPDT Switch Serves PCN Applications,”
Microwave RF, vol. 33, no. 1, pp. 111-118, Jan. 1994.
[46]
G. E. Ponchak and R. N. Simons, “Channelized Coplanar W aveguide PIN-Diode
Switches,” 19th European Microwave Conf. Proc., pp. 489 - 494, London, England,
Sept. 4 -7 , 1989.
[47]
C. P. Wen, “Coplanar waveguide: a surface strip transmission line suitable for
nonreciprocal gyromagnetic device applications,” IEEE Trans, on Microwave
Theory and Techn., vol. 17, Dec. 1969, pp. 1087 - 1090.
[48]
U. S. Inan and A S. Inan, “Engineering Electromagnetics,” Menlo Park, CA,
Addison-Wesley, 1999.
[49]
W. Hilberg, “Quasi-TEM Description of MMIC Coplanar Lines including
conductor-loss effects,” IEEE Trans, on Microwave Theory and Tech., vol. 41, Jan.
1993, pp. 45-52.
[50]
E. O. Hammerstad and F. Bekkadal, “A microstrip handbook,” ELAB Report,
STF44, A74169, University of Trondheim, Norway, Feb. 1975.
[51]
J. R. James and A. Henderson, “High-frequency behaviour of microstrip opencircuit terminations,” IEE Journal on Microwave, Optics and Acoustics, vol. 3, no. 5,
Sept. 1979, pp. 205-218.
[52]
R. P. Owens, “Predicted frequency dependence of microstrip characteristic
impedance using the planar waveguide model,” Electron. Lett., vol. 12, 1976, pp.
269-270.
[53]
K. C. Gupta, R. Garg, I. Bahl, and P. Bhartia, “Microstrip Lines and Slotlines,”
Boston, MA, Artech House, 1996.
[54]
Schollhom, W. Zhao, M. Morschbach, and E. Kasper, “Attenuation Mechanisms
of Aluminum Millimeter-Wave Coplanar Waveguides on Silicon,” IEEE Trans, on
Electron Devices, vol. 50, no. 3, pp. 740-746, Mar., 2003.
[55]
D. M. Pozar, “Microwave Engineering”, 2nd ed., New York, USA, John Wiley &
Sons, Inc, 1998.
[56]
W. R. Eisenstadt and Y. Eo, “S-Parameter-Based IC Interconnect Transmission
Line Characterization,” IEEE Trans, on Components, Hybrids and Manufacturing
Technology, vol. 15, no. 4, pp. 483 - 490.
[57]
J. Hanseler, H. Schinagel and H. Zapf, ‘T est Structures and Measurement
Techniques for the Characterization of the Dynamic Behavior of CMOS Transistors
on W afer in the GHz Range,” IEEE Int. Conf. on Microelectronic Test Structures,
vol. 5, 1992, pp. 90-93.
138
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[58]
Y. Eo and W. Eisenstadt, “High-Speed VLSI Interconnect M odeling Based on Sparameter Measurements,” IEEE Trans, on Components, Hybrids, and
Manufacturing Technology, vol. 16, no. 6, 1993, pp. 555—562.
[59]
J. Papapolymerou, G. E. Ponchak, E. Dalton, A. Bacon and M. M. Tentzeris,
“Crosstalk between Finite Ground Coplanar Waveguides Over Polyimide Layers for
3-D MMICs on Si Substrates,” IEEE Trans, on Microwave Theory and Tech., vol.
52, no. 4, Apr. 2004.
[60]
J. N. Burghartz, D. C. Edelstein, K. A. Jenkins and Y. H. Kwark, “Spiral
Inductors and Transmission Lines in Silicon Technology Using Copper-Damascene
Interconnects and Low-Loss Substrates”, IEEE Trans, on Microwave theory and
Techniques, Vol. 45, No. 10, Oct. 1997, pp. 1961-1968.
[61]
“Cyclotene™ 4000 Series Advanced Electronic Resins (Photo BCB)”, The Dow
Chemical Company, 2000.
[62]
A. J. G. Strandjord, W. B. Rogers, Y. Ida, R. R. DeVellis, S. Shiau, E. S. Moyer,
D. M. Scheck, and P. E. Garrou, “Photosensitive benzocyclobutene for stress-buffer
and passivation applications (one mask manufacturing process)”, Proc. o f Electronic
Components and Technology Conference, San Jose, CA, USA, May 1997, pp. 12601268
[63]
G. Matthaei, L. Young, E. M. T. Jones, “Microwave filters, impedance-matching
networks, and coupling structures”, Artech House, Inc., 1980.
[64]
M. Makimoto and S. Yamashita, “Microwave Resonator and Filters for Wireless
Communication”, Springer-Verleg Berlin Heidelberg, 2001.
[65]
T. Itoh, G. Haddad and J. Harvey, “RF Technologies Wireless Communications”,
John Wiley & Son, Inc.
[66]
G. Yan, P. C. H. Chan, I. M. Hsing, R. K. Sharma and J. K. O. Sin, “An
improved TMAH Si-etching solution without attacking exposed aluminum,” IEEE
Int. Conf. on MEMS (MEMS2000), pp. 562-567.
[67]
Tabata, R. Asahi, H. Funabashi, K. Shimaoka and S. Sugiyama, “Anisotropic
etching of silicon in TMAH solution,” International Conference on Solid-State
Sensors and Actuators, June 1992, pp. 51-57.
[68]
Tabata, “PH-controlled TMAH etchants for silicon micromachining,”
International Conference on Solid-State Sensors and Actuators and Eurosensors IX,
Stockholm, Sweden, June 1995, pp. 83-86.
[69]
M. Asano, T. Cho and H. Muraoka, “Applications of choline in semiconductor
techonology,” Electrochem. Soc. Ext. Abstr., 1976, pp.911-913.
139
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[70]
M. Madou, “Fundamentals of Microfabrication: The Science of Miniaturization”
2nd ed., CRC Press, 2002.
[71]
Lydia L. W. Leung, W. C. Hon and Kevin J. Chen, “Low-loss Coplanar
Waveguides Interconnects on Low-resistivity Silicon Substrate,” IEEE Trans, on
Components, Packaging and Manufacturing Technology, vol. 27, no. 3, Sept. 2004,
pp. 2 0 7 -2 1 2 .
[72]
R. K. Young, V. M. Hietala, and K. S. Champlin, “Quasi-TEM Analysis of
“Slow-Wave” Mode propagation on Coplanar Microstructure MIS Transmission
Lines,” IEEE Trans, on Microwave Theory and Tech., vol. 35, no. 6, June 1987, pp.
545-551.
[73]
M. E. Davis, E. W. Williams, and A. C. Celestini, “Finite-boundary corrections
to the coplanar waveguide analysis,” IEEE Trans, on Microwave Theory and Tech.,
vol. MTT-21, Sept. 1973, pp. 594-596.
[74]
V. Milanovic, M. Ozgur, D. C. DeGroot, J. A. Jargon, M .Gaitan and M. E.
Zaghloul, “Characterization of Broad-Band Transmission for Coplanar Waveguides
on CMOS Silicon Substrates,” IEEE Trans, on Microwave Theory and Tech., vol. 46,
no. 5, pp. 632 - 640, May 1998.
[75]
B. Kleveland, T. H. Lee and S. S. Wong, “50-GHz Interconnect Design in
Standard Silicon Technology,” IEEE MTT-S Int. Microwave Symp. Dig, 1998, pp.
1 9 1 3 -1 9 1 6 .
[76]
S. Kim and D. P. Neikirk, “Compact Equivalent Circuit model for the skin
effect”, IEEE MTT-S Int. Microwave Symp. Digest, 1996, pp. 1 8 1 5 -1 8 1 8 .
[77]
J. Zheng, Y. C. Hahm, V. K. Tripathi and A. Weisshaar, “CAD-Oriented
Equivalent-Circuit Modeling of On-chip Interconnects on Lossy Silicon Substrate,”
IEEE Trans, on Microwave Theory and Tech., vol. 48, no. 9, pp. 1443 —1451, Sept.
2000 .
[78]
S. Premachandran, R. Nagarajan, C. Yu, Z. Xiolin and C. S. Choong, “A Novel
Electrically Conductive W afer Through Hole Filled Vias Interconnect for 3D MEMS
packaging,” IEEE Electronic Components and Technology Conference, New
Orleans; LA; USA, 2003, pp. 627 -630.
[79]
G. Swanson, W. J. R. Hoefer, “Microwave Circuit Modeling Using
Electromagnetic Field Simulation,” 1st ed., Boston, USA, Artech House, 2003.
[80]
M. E. Goldfarb and R. A. Pucel, “Modeling Via-hole Grounds in Microstrip,”
IEEE Microwave and Guided Wave Letters, vol. 1, no. 6, pp. 135 —137, June, 1991.
140
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
References
[81]
R. Djordjevic, T. K. Sarkar, and S. M. Rao, “Analysis o f Finite Conductivity
Cylindrical Conductors Excited by Asially-Independent TM Electromagnetic Field,”
IEEE Trans, on Microwave Theory and Tech., vol. 33, no. 10, pp. 960 —966, Oct.,
1985.
[82]
I. Costache, M. W. Nemes, and E. M. Petriu, “Finite Element Method Analysis
of the Influence of the Skin Effect, Proximity, and Eddy Currents on the Internal
Magnetic Field and Impedance of a Cylindrical Conductor of Arbitrary CrossSection,” IEEE Canadian Conference on Electrical and Computer Engineering,
Quebec., Canada, Sept., 1995, pp. 253 - 256.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix
A ppendix
1. Process flow of passive components on BCB
Ground plate (Al) Patterning
1.1
Starting substrates
Comments: 6 wafers.
1) Number of wafers = 6
2) Type:
Orientation = (100)
Size (mm) = 100
Thickness (pm) = 520
Dopant type = Boron
Resistivity (£2-cm) = 1 5- 25
3) Preparation:
Label: 1 , 6
Double-side polished = No
Epitaxial = No
Remarks:
1.2
a) Labels are scribed near the major flats of the wafers using a diamond scriber.
Wafers used: All wafers
Comments: Initial clean. Remove scribe dust particles.
Sulfuric Acid Clean
1) DI spray rinse
Cycles = 4
2) H2S04:H20 2:
Composition = 10:1
Temperature (°C) =120
Time (minutes) = 10
3) DI spray rinse:
Cycles = 4
Remarks:
1.3
a) Wafers with metal cannot be cleaned with this procedure.
b) If more than 30 minutes has elapsed after the last user, then add 0.3 litre of H20 2to
the H2S0 4 :H20 2 bath.
Wafersused:All
wafers
Comments: None
Wet oxidation
1) Furnace tube = ASM D3: Wet oxidation
2) Thickness (nm) = 500
3) Process:
Temperature (°C) = 1000
142
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Appendix
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Wet cycle time (minutes) = 75
H2 flow rate (L/m) = 5.6
0 2 flow rate (L/m) = 4
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Post oxidation anneal time (minutes) = 20
N2 flow rate (L/m) = 8
1.4
______Wafers used: All wafers
Comments: Measure oxide thickness
Nanospec
Film = Thick oxide on silicon
Program = 1
1.5____ ______Wafers used: All wafers
Comments: None
A1 Sputter Deposition
1) Equipment = Varian 3180
Film = Al:1.5%:Si
2) Process:
Thickness (pm) = 1
Time =
Base pressure (Torr) = less than 10"6
Process pressure (mTorr) = 3.5
% of full RF power of 12kW = 70
1.6
______Wafers used: All wafers
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
Temperature (°C) = 105
Time (second) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = HPR-204 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 4000
Spin time (seconds) = 30
Resist thickness (pm) =1.3
4) Rinse and edge bead removal
Backside rinse RPM = 800
Backside rinse time (seconds) = 10
Frontside edge rinse RPM =1500
Frontside edge rinse time (seconds) = 15
5) Spin dry
143
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Appendix
Spin RPM = 3000
Spin time (seconds) =10
6) Pre-bake
Temperature (°C) =110
Time (seconds) = 60
1.7___________Wafers used: All wafers
Comments: None
Photoresist Exposure
1) Aligner = Canon PLA-510FA
2) Exposure side = Front
3) Process:
Mask = Metal 1 (CMF)
Align = Contact
Contact mode = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2)
1.8____ ______Wafers used: All wafers
Comments: None
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
1.9____ ______Wafers used: All wafers
Comments: None
Aluminum wet etch
1) A1 etchant
Thickness to be etched (pm) = 1
Etch rate (A/min) = 2823
Total etching time including over-etch (minutes) = 4
2) DI spray rinse:
Cycles = 4
1.10___ ______Wafers used: All wafers
Comments: Aluminum etch end point detection: conductivity test on test pattern
144
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Appendix
1.11
Wafers used: All wafers
Comments: Rotate wafer for better ash uniformity.
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) = 100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) =
Remarks:
a) Ashing may cause plasma damage in thin oxide layers.
1.12
Wafersused: All wafers
Comments: None
Photoresist Removal Inspect
1) Set microscope to darkfield.
2) Scan over the wafer along two orthogonal diameters.
3) Note if irregular shape residues remain on the surface.
4) Photoresist removal is complete if none is found
5) Otherwise try stripping again
BCB coating and patterning
2.1
Wafersused: All wafers
Comments: None
Manual Photoresist Coat
1) Coat surface = Front
2) AP3000 (Adhesion Promoter)
Dynamic spin RPM = 500
Spin time (seconds) = 20
Spin RPM = 4000
Spin time (seconds) = 30
3) Coat
Resist Type = BCB
Dynamic spin RPM = 500
Spin time (seconds) = 20
Spin R P M = 1500
Spin time (seconds) = 30
4) Pre-bake
Temperature
80
Time (second) = 30
( ° C )
=
145
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Appendix
2.2
Wafers used: All wafers
Comments: None
Photoresist Exposure
1) Aligner = AB-M#2(UV)
2) Exposure side = Front
3) Process:
Mask = via (CVA)
Align = Metal 2
Contact mode = Soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
4) Pre-develop bake
Temperature (°C) = 70
Time (second) = 30
Remarks: a) Exposure of BCB = 25mJ/cm2/p.m; BCB thickness before hard cure = 10 pm. Hence, the
exposure dose is 250mJ/cm2.
2.3
Wafers used: All wafers
Comments: None
BCB Develop
1) Develop surface = Front
2) Develop
Developer type = DC2000
Soak time (seconds) = 120
3) Spin rinse and dry
Rinse RPM = 500
Rinse time (seconds) = 20
Spin RPM = 4000
Rinse time (seconds) = 30
4) Post-bake
Temperature (°C) = 90
Time (seconds) = 60
Inspection:
2.4
a) Check if the resist pattern is a faithful reproduction of the mask pattern and if the
alignment is adequate, if not, strip the resist and repeat the photolithography step again,
b) BCB thickness measurement using stepper.
Wafers used: All device
Comments: None
Hard Cure
1) Oven = Blue M
2)
P rocess:
Ambient = N2
Pre-heat time (minutes) = 30
Pre-heat temperature (°C) = 150
Process time (minutes) = 40
Process temperature (°C) = 250
146
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Appendix
Ramp down time (minutes) = 60
2.5
Wafers used: All device
Comments: None
BCB Descum
1) Etcher = Brason/EPC4000
2) Film parameters:
Thickness to be etched (nm) = 800
3) Descum
Temperature (°C) = 70
RF incident power (W) = 800
RF reflected power (W) =
Pressure (mTorr) = 55
0 2 flow rate (seem) 45
Process time (minutes) = 0.7
Procedures 2.1 - 2.5 are repeated once and twice for 14pm and 20pm BCB respectively.
Passive components (Cu) Patterning
3.1____ _____Wafers used: All device
Comments: None
Copper seed sputtering
1) Equipment: ARC-12M
2) Sputter surface = frontside
3) Process:
Sputter etch time (minutes) = 5
TiW thickness (nm) = 80
Cu thickness (nm) = 350
3.2
_____Wafers used: All devices
Comments: Metal level lithography.
Manual Photoresist Coater
1) Coat surface = Front
2) HMDS prime
Temperature (°C) = 105
Time (seconds) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = AZ-4620 (Positive)
Dynamic dispense RPM = 500
Spin RPM = 1000
Spin time (seconds) = 30
Resist thickness (pm) = 6
4) Pre-bake
Temperature (°C) = 90
Time (seconds) = 60
147
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Appendix
3.3
Wafersused:Alldevice
Comments: None
Photoresist Exposure
1) Aligner = AB-M#2
2) Exposure side = Front
3) Process:
Mask = Metal 2 (Dark-field mask)
Align = Contact
Contact mode = soft
Contact Pressure (Torr) = 526
Exposure dose (mJ/cm2) = 75 seconds
3.4
Wafersused:Allwafers
Comments: None
Photoresist Develop
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (minutes) = 5
3) DI spray rinse:
Cycles = 4
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
Inspection:
3.5
a) Check if the resist pattern is faithful reproduction of the mask pattern and if not, strip
the resist and repeat the photolithography step again.
______ W afers used: All wafers
Comments: None
Photoresist Hard Bake
1) Oven = Hot plate
2) Time (minutes) = 10
3) Temperature (°C) = 120
3.6
______Wafers used: All wafers
Comments: Process to be done after Cu electroplating in Phase I.
Photoresist Strip
1) MS2001:
Temperature (°C) = 75
Time (minutes) = 10
2) DI spray rinse:
Cycles = 4
148
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Appendix
3.7
Wafersused: All wafers
Comments: None
Photoresist Removal Inspect
1) Set microscope to darkfield.
2) Scan over the wafer along two orthogonal diameters.
3) Note if irregular shape residues remain on the surface.
4) Photoresist removal is complete if none is found
5) Otherwise try stripping again
3.8
Wafersused: All wafers
Comments: To be done in Phase I
Cu seed removal
1) Ronetch solution :
Thickness (nm) = 350
Temperature (°C) = room temperature
Time (minutes) = 2 - 3
2) DI spray rinse :
Cycles = 4
Remarks: Observe color change: from golden (Cu) to silvery (TiW)
3.9
Wafersused: All wafers
Comments: None
TiW seed removal
1) H20 2:
Temperature (°C) = 70
Time (minutes) = 2
2) DI spray rinse:
Cycles = 4
Remarks: Observe color change: from silvery to green (BCB). Inspect the wafer under microscope to
ensure that the TiW seed is removed completely. Otherwise try stripping again.
149
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Appendix
2. Process flow of Edge-Suspended Coplanar W aveguides
Coplanar waveguides (Al) Patterning
1.1
Startingsubstrates
Comments: 6 wafers.
1) Number of wafers = 6
2) Type:
Orientation = (100)
Size (mm) = 100
Thickness (pm) = 520
Dopant type = Phosphorus
Resistivity (Q-cm) = 1 5 - 2 0
3) Preparation:
Label: 1 , 6
Double-side polished = No
Epitaxial = No
Remarks:
1.2
a) Labels are scribed near the major flats of the wafers using a diamond scriber
Wafers used: All wafers
Comments: Initial clean. Remove scribe dust particles.
Sulfuric Acid Clean
1) DI spray rinse
Cycles = 4
2) H2S04:H20 2:
Composition = 10:1
Temperature (°C) = 120
Time (minutes) = 10
3) DI spray rinse:
Cycles = 4
Remarks:
2.1
a) Wafers with metal cannot be cleaned with this procedure.
b) If more than 30 minutes has elapsed after the last user, then add 0.3 litre of H20 2 to
the H2S0 4 :H20 2 bath.
Wafers used: All wafers
Comments: None
Wet oxidation
1) Furnace tube = ASM D3: Wet oxidation
2) Thickness (pm) = 1
3) Process:
Temperature (°C) = 1000
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Wet cycle time (minutes) = 75
H2 flow rate (L/m) = 5.6
150
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Appendix
0 2 flow rate (L/m) = 4
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Post oxidation anneal time (minutes) = 20
N2 flow rate (L/m) = 8
2.2
______Wafers used: All wafers
Comments: Measure oxide thickness
Nanospec
Film = Thick oxide on silicon
Program = 1
2.3
______Wafers used: All wafers
Comments: None
A1 Sputter Deposition
1) Equipment = Varian 3180
Film = Al:1.5%:Si
2) Process:
Thickness (pm) = 1
Time =
Base pressure (Torr) = less than 10 6
Process pressure (mTorr) = 3.5
% of full RF power of 12kW = 70
2.4
______Wafers used: All wafers
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
Temperature (°C) = 105
Time (second) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = HPR-204 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 4000
Spin time (seconds) = 30
Resist thickness (pm) =1.3
4) Rinse and edge bead removal
Backside rinse RPM = 800
Backside rinse time (seconds) = 10
Frontside edge rinse RPM = 1500
Frontside edge rinse time (seconds) = 15
5) Spin dry
Spin RPM = 3000
Spin time (seconds) = 10
6) Pre-bake
Temperature (°C) =110
151
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Appendix
Time (seconds) = 60
2.5
Wafers used: All wafers
Comments: None
Photoresist Exposure
1) Aligner = Canon PLA-51OFA
2) Exposure side = Front
3) Process:
Mask = Metal 1
Align = Contact
Contact mode = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
2.6
Wafers used: All wafers
Comments: None
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
2.7
Wafers used: All wafers
Comments: None
Aluminum wet etch
1) A1 etchant
Thickness to be etched (pm) = 1
Etch rate (A/min) = 2823
Total etching time including over-etch (minutes) = 4
2) DI spray rinse:
Cycles = 4
2.8
Wafers used: All wafers
C om m ents: A lu m in u m etch end point detection: con d u ctivity test on test pattern
2.9
Wafers used: All wafers
Comments: Rotate wafer for better ash uniformity.
152
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Appendix
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) =100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) =
Remarks:
a) Ashing may cause plasma damage in thin oxide layers.
2.10
Wafersused:Allwafers
Comments: None
Photoresist Removal Inspect
1) Set microscope to darkfield.
2) Scan over the wafer along two orthogonal diameters.
3) Note if irregular shape residues remain on the surface.
4) Photoresist removal is complete if none is found
5) Otherwise try stripping again
2.11
Wafersused:Allwafers
Comments: None
Wet oxidation
1) Furnace tube = ASM D3: Wet oxidation
2) Thickness (pm) = 1
3) Process:
Temperature (°C) = 1000
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Wet cycle time (minutes) = 75
H2 flow rate (L/m) = 5.6
0 2 flow rate (L/m) = 4
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Post oxidation anneal time (minutes) = 20
N2 flow rate (L/m) = 8
Trench creating
3.1
Wafers used: All wafers
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
153
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Appendix
3)
4)
5)
6)
Temperature (°C) =105
Time (second) = 30
Cooling time (seconds) = 70
Coat
Resist Type = HPR-204 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 4000
Spin time (seconds) = 30
Resist thickness (pm) =1.3
Rinse and edge bead removal
Backside rinse RPM = 800
Backside rinse time (seconds) = 10
Frontside edge rinse RPM = 1500
Frontside edge rinse time (seconds) =15
Spin dry
Spin RPM = 3000
Spin time (seconds) =10
Pre-bake
Temperature (°C) =110
Time (seconds) = 60
3.2
Wafersused:Allwafers
Comments: None
Photoresist Exposure
1) Aligner = Suss MA6
2) Exposure side = Front
3) Process:
Mask = Trench (Dark field mask)
Align = Contact
Contact mode = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
3.3
Wafers used: All wafers
Comments: None
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
154
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Appendix
3.4
_____Wafers used: All device
Comments: None
Silicon Oxide Plasma Etch
1) Etcher = AME8110
2) Film parameters:
Thickness (pm) = 1
3) Descum:
Temperature (°C) = 70
RE incident power (W) = 800
RF reflected power (W) =
Pressure (mTorr) = 55
0 2 flow rate (seem) = 45
Process time (minutes) = 0.7
4) Etch:
Temperature (°C) = 25
RF incident power (W) = 1200
RF reflected power (W) =
Pressure (mTorr) = 50
0 2 flow rate (seem) = 6
CHF3 flow rate (seem) = 74
Percentage over-etch time (%) = 10
Total etch time including over-etch (minutes) = 55
Remarks:
3.5
a) Resist etch rate during descum - 1 .9nm/s.
b) Etch rate - 40nm/min, uniformity ~ 10%
c) Selectivity - :silicon - 8:1, mitride - 2:1, :photoresist -6.5:1
_____Wafers used: All device
Comments: None
Silicon deep reactive ion etch
1) Etcher = ICP silicon etcher
2) Film parameters:
Thickness (pm) = 15
Remarks:
3.6
a) Resist etch rate during descum ~nm/s.
b) Etch rate —nm/min, uniformity - 10%
c) Selectivity - :silicon - 8:1, mitride - 2:1, :photoresist - 6.5:1
______Wafers used: All wafers
Comments: Rotate wafer for better ash uniformity.
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) = 100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
155
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Appendix
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) = 10
Remarks:
a) Ashing may cause plasma damage in thin oxide layers.
Contact opening
4.1
______Wafers used: All wafers
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
Temperature (°C) =105
Time (second) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = HPR-204 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 4000
Spin time (seconds) = 30
Resist thickness (pm) =1.3
4) Rinse and edge bead removal
Backside rinse RPM = 800
Backside rinse time (seconds) = 10
Frontside edge rinse RPM = 1500
Frontside edge rinse time (seconds) = 15
5) Spin dry
Spin RPM = 3000
Spin time (seconds) = 10
6) Pre-bake
Temperature (°C) =110
Time (seconds) = 60
4.2
______Wafers used: All wafers
Comments: None
Photoresist Exposure
1) Aligner = Canon
2) Exposure side = Front
3) Process:
Mask = Contact (Dark field mask)
Align = Contact
C ontact m od e = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
4.3
______Wafers used: All wafers
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Appendix
Comments: None
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
4.4
Wafers used: All wafers
Comments: None
777 Etch
1) Thickness to be etched (pm) = 1
2) 777:
Temperature = Room temperature
Percentage over-etch (%) = 100
Total etch time including over-etch (minutes) = 25
3) DI spray rinse:
Cycles = 4
Remarks:
4.5
a) If complete removal is desired, end-point can be detected by hydrophobicity on silicon
surface.
Wafers used: All wafers
Comments: Rotate wafer for better ash uniformity.
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) =100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) = 10
Remarks: a) Ashing may cause plasma damage in thin oxide layers.
157
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Appendix
Creating Lateral undercut
5.1
Wafers used: All wafers
Comments: None
TMAH etch
1) Thickness to be etched (pm) = depends on the amount of lateral undercut to be created.
2) TMAH:(NH4)2S20 8:Si:
Composition = 5:0.5:1.6
Temperature (°C) = 80
Percentage over-etch time (%) = 0
Etching rate (pm/minutes) = 0.8
3) DI spray rinse:
Cycles = 4
Remarks:
a) The lateral undercut created is measured by the testing structures.
158
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Appendix
3. Process flow of through-wafer interconnects vias
Via-holes patterning
1.1
Startingsubstrates
Comments: 3 wafers.
1) Number of wafers = 6
2) Type:
Orientation = (100)
Size (mm) = 100
Thickness (pm) = 400
Dopant type = Phosphorus
Resistivity (Q-cm) = 2500
4) Preparation:
Label: 1 , 6
Double-side polished = No
Epitaxial = No
Remarks:
1.2
a) Labels are scribed near the major flats of the wafers using a diamond scriber
Wafersused:Allwafers
Comments: Initial clean. Remove scribe dust particles.
Sulfuric Acid Clean
1) DI spray rinse
Cycles = 4
2) H2S04:H20 2:
Composition =10:1
Temperature (°C) = 120
Time (minutes) = 10
3) DI spray rinse:
Cycles = 4
Remarks:
1.3
a) Wafers with metal cannot be cleaned with this procedure.
b) If more than 30 minutes has elapsed after the last user, then add 0.3 litre of H20 2 to
the H2S0 4 :H20 2 bath.
Wafersused:Allwafers
Comments: None
Wet oxidation
1) Furnace tube = ASM D3: Wet oxidation
2) Thickness (pm) = 3
3) Process:
Temperature (°C) = 1000
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Wet cycle time (minutes) = 75
H2 flow rate (L/m) = 5.6
159
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Appendix
0 2 flow rate (L/m) = 4
Dry cycle time (minutes) = 5
0 2 flow rate (L/m) = 8
Post oxidation anneal time (minutes) = 20
N2 flow rate (L/m) = 8
1.4
Wafersused:All
wafers
Comments: Measure oxide thickness
Nanospec
Film = Thick oxide on silicon
Program = 1
1.5
Wafersused:All
wafers
Comments: Pre-photolithography clean
Sulfuric Acid Clean
1) DI spray rinse
Cycles = 4
2) H2S04:H20 2:
Composition =10:1
Temperature (°C) =120
Time (minutes) = 10
3) DI spray rinse:
Cycles = 4
Remarks:
2.1
a) Wafers with metal cannot be cleaned with this procedure.
b) If more than 30 minutes has elapsed after the last user, then add 0.3 litre of H20 2 to
the H2S04:H20 2 bath
Wafersused:All
wafers
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
Temperature (°C) =105
Time (second) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = HPR-204 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 4000
Spin time (seconds) = 30
Resist thickness (pm) =1.3
4) Rinse and edge bead removal
Backside rinse RPM = 800
Backside rinse time (seconds) = 10
Frontside edge rinse RPM = 1500
Frontside edge rinse time (seconds) = 15
5) Spin dry
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Appendix
Spin RPM = 3000
Spin time (seconds) =10
6) Pre-bake
Temperature (°C) =110
Time (seconds) = 60
2.2
Wafersused:All
wafers
Comments: None
Photoresist Exposure
1) Aligner = Karl Suss MA6
2) Exposure side = Front
3) Process:
Mask = Via (Dark field mask)
Align = Contact
Contact mode = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
2.3
Wafersused:All
wafers
Comments: No
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) =15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
2.4
Wafersused:All
device
Comments: None
Silicon Oxide Plasma Etch
1) Etcher = AME8110
2) Film parameters:
Thickness (pm) = 3
3) Descum:
Temperature (°C) = 70
RF incident power (W) = 800
RF reflected power (W) =
Pressure (mTorr) = 55
0 2 flow rate (seem) = 45
Process time (minutes) = 0.7
4) Etch:
161
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Appendix
Temperature (°C) = 25
RF incident power (W) = 1200
RF reflected power (W) =
Pressure (mTorr) - 50
0 2 flow rate (seem) = 6
CHF3 flow rate (seem) = 74
Percentage over-etch time (%) =10
Total etch time including over-etch (minutes) = 75
Remarks:
2.5
a) Resist etch rate during descum ~1.9nm/s.
b) Etch rate ~ 40nm/min, uniformity ~ 10%
c) Selectivity - :silicon —8:1, :nitride —2:1, :photoresist —6.5:1
Wafers used: All wafers
Comments: Rotate wafer for better ash uniformity.
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) =100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) = 10
Remarks:
a) Ashing may cause plasma damage in thin oxide layers.
Ring mask for wafer-edge protection
3.1
Wafersused:All
device
Comments: None
SVG Photoresist Coat Track
1) Coat surface = Front
2) HMDS prime
Temperature (°C) = 105
Time (second) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = AZ-4620 (Positive)
Dynamic dispense RPM = 1000
Spin RPM = 2300
Spin time (seconds) = 30
Resist thickness (|xm) =1.3
4) Pre-bake
Temperature (°C) = 110
Time (seconds) = 60
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Appendix
3.2
Wafers used: All device
Comments: None
Photoresist Exposure
1) Aligner = Karl Suss MA6
2) Exposure side = Front
3) Process:
Mask = Ring
Align = Contact
Contact mode = soft
Contact pressure (Torr) = 526
Exposure dose (mJ/cm2) =
3.3
Wafers used: All device
Comments: No
SVG Photoresist Develop Track
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 120
Time (seconds) = 60
Through-wafer via-holes creation
4.1
Wafersused:Alldevice
Comments: None
Silicon deep reactive ion etch
1) Etcher = ICP silicon etcher
2) Film parameters:
Thickness (pm) = 30
Remarks:
a) Oxide etch rate during descum -6 nm/min.
b) Selectivity - :silicon ~ 300:1.
Step 4.1 is repeated until all the through-wafer via-holes in the wafer are opened.
Remarks:
4.2
a) A dummy wafer should be put underneath the target wafer when the via-holes are
100-pm from being etched through to avoid the chunk from being damaged,
b) The wafer surface is inspected to detect complete opening.
Wafers used: All wafers
163
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Appendix
Comments: Rotate wafer for better ash uniformity.
Photoresist Ash
1) Asher = Brason
2) Process:
Ramp ambient N2 flow rate (seem) = 450
Temperature at the end of ramp (°C) = 100
Microwave power during ramp (W) = 500
N2 pressure (Torr) =1.3
Process 0 2 flow rate (seem) = 450
Temperature at the end of ash (°C) =
Microwave power during ash (W) = 400
0 2 pressure (Torr) =1.3
Ash time (minutes) =
Remarks:
a) Ashing may cause plasma damage in thin oxide layers.
4.3
Wafersused:Allwafers
Comments: Remove the oxide mask.
BOE Etch
1) Thickness to be etched (pm) = 1
2) BOE:H20:
Composition = 1:6
Temperature (°C) = 25
Percentage over-etch time ( % ) =
Total etch time including over-etch (minutes) = 10
3) DI spray rinse:
Cycles = 4
Remarks: a) The backside oxide of the wafer must be removed completely to ensure the complete
opening of the via-holes.
Via-holes filling
5.1 _____ Wafers used: All device
Comments: None
PECVD nitridation
1) Equipment = PECVD deposition
2) Thickness (nm) = 500
5.2 _____ Wafers used: All device
Comments: None
Cu seed sputtering
1) Equipment = ARC-12M
2) Sputter surface = back
3) Process:
Sputter Etch Time (minutes) = 5
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Appendix
TiW thickness (nm) = 80
Cu thickness (nm) = 350
5.3
_____ Wafers used: All device
Comments: This process is done in Phase I.
Copper oxide removal
1) Ronetch solution rinse:
Cycle = 1
2) DI spray rinse:
Cycles = 4
5.4
_____ Wafers used: All device
Comments: This process is done in Phase I.
Copper electroplating
1) Copper sulphate solution
Thickness (pm) = 6
Temperature = room temperature
Current density (mA/cm2) = 20
Time (minutes) = 20
2) DI spray rinse:
Cycles = 4
Passive components (Cu) Patterning on frontside of the wafer
6.1
_____ Wafers used: All device
Comments: None
Copper seed sputtering
1) Equipment: ARC-12M
2) Sputter surface = frontside
3) Process:
Sputter etch time (minutes) = 5
TiW thickness (nm) = 80
Cu thickness (nm) = 350
6.2
_____ Wafers used: All devices
Comments: Metal level lithography.
Manual Photoresist Coater
1) Coat surface = Front
2) HMDS prime
Temperature (°C) = 105
Time (seconds) = 30
Cooling time (seconds) = 70
3) Coat
Resist Type = AZ4620 (Positive)
Dynamic dispense RPM = 500
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Appendix
Spin RPM = 1000
Spin time (seconds) = 30
Resist thickness (pm) = 6
4) Pre-bake
Temperature (°C) =110
Time (seconds) = 60
6.3
Wafers used: All device
Comments: None
Photoresist Exposure
1) Aligner = AB-M#2
2) Exposure side = Front
3) Process:
Mask = Metal 3 (Dark-field mask)
Align = Contact
Contact mode = soft
Contact Pressure (Torr) = 526
Exposure dose (mJ/cm2) = 75 seconds
6.4
Wafers used: All wafers
Comments: None
Photoresist Develop
1) Develop surface = Front
2) Develop
Developer type = FHD-5 (Positive)
Soak time (seconds) = 60
3) Spin rinse and dry
Rinse RPM = 1500
Rinse time (seconds) = 20
Dry RPM = 4000
Spin time (seconds) = 15
4) Post bake
Temperature (°C) = 90
Time (seconds) = 60
Inspection:
6.5
a) Check if the resist pattern is faithful reproduction of the mask pattern and if not, strip
the resist and repeat the photolithography step again.
Wafers used: All wafers
Comments: None
Photoresist Hard Bake
1) Oven = Hot plate
2) Time (minutes) =10
3) Temperature (°C) = 120
6.6
Wafers used: All wafers
Comments: Process to be done after Cu electroplating in Phase I.
166
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Appendix
Photoresist Strip
1) M S2001:
Temperature (°C) = 75
Tim e (minutes) = 10
2) D I spray rinse:
C ycles = 4
6.7
W afers used: A ll wafers
Comments: N one
Photoresist Rem oval Inspect
1) Set m icroscope to darkfield.
2) Scan over the wafer along two orthogonal diameters.
3) N ote if irregular shape residues remain on the surface.
4) Photoresist rem oval is com plete if none is found
5) Otherwise try stripping again
6.8
_______ Wafers used: A ll wafers
Comments: To be done in Phase I
Cu seed removal
1) Ronetch solution :
Thickness (nm) = 350
Temperature (°C) = room temperature
Tim e (minutes) = 2 - 3
2) DI spray rinse :
C ycles = 4
Remarks: Observe color change: from golden (Cu) to silvery (TiW )
6.9
_______W afers used: A ll wafers
Comments: N one
TiW seed removal
1)
H20 2:
Temperature (°C) = 70
Tim e (minutes) = 2
2) DI spray rinse:
C ycles = 4
Remarks: Observe color change: from silvery dark color (Si wafer surface). Inspect the wafer under
m icroscope to ensure that the TiW seed is rem oved com pletely. Otherwise try stripping again.
167
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Appendix
Photoresist Strip
1) M S2001:
Temperature (°C) = 75
Tim e (minutes) = 10
2) D I spray rinse:
C ycles = 4
6.7
W afers used: A ll wafers
Comments: N one
Photoresist Rem oval Inspect
1) Set m icroscope to darkfield.
2) Scan over the wafer along tw o orthogonal diameters.
3) N ote if irregular shape residues remain on the surface.
4) Photoresist removal is com plete if none is found
5) Otherwise try stripping again
6.8
_______ Wafers used: All wafers
Comments: To be done in Phase I
Cu seed removal
1) Ronetch so lu tio n :
Thickness (nm) = 350
Temperature (°C) = room temperature
Tim e (minutes) = 2 - 3
2) DI spray rinse :
C ycles = 4
Remarks: Observe color change: from golden (Cu) to silvery (TiW )
6.9
_______W afers used: All wafers
Comments: N one
TiW seed removal
1)
2)
H20 2:
Temperature (°C) = 70
Tim e (minutes) = 2
D I spray rinse:
C ycles = 4
Remarks: Observe color change: from silvery dark color (Si wafer surface). Inspect the wafer under
m icroscope to ensure that the TiW seed is removed com pletely. Otherwise try stripping again.
167
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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