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Microwave rectifying circuits and antennas for radio frequency identification and wireless power transmission applications

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MICROWAVE RECTIFYING CIRCUITS AND ANTENNAS
FOR RADIO FREQUENCY IDENTIFICATION AND WIRELESS POWER
TRANSMISSION APPLICATIONS
A Dissertation
by
BERND HERBERT STRASSNER II
Submitted to the Office of Graduate Studies o f
Texas A&M University
in partial fulfillment o f the requirements for the degree o f
DOCTOR OF PHILOSOPHY
August 2002
Major Subject: Electrical Engineering
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UMI Number 3060900
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P.O. Box 1346
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MICROWAVE RECTIFYING CIRCUITS AND ANTENNAS
FOR RADIO FREQUENCY IDENTIFICATION AND WIRELESS POWER
TRANSMISSION APPLICATIONS
A Dissertation
by
BERND HERBERT STRASSNERII
Submitted to the Office o f Graduate Studies o f
Texas A&M University
in partial fulfillment o f the requirements for the degree o f
DOCTOR OF PHILOSOPHY
Approved as to style and content by:
Kai Chang
(Chair o f Committee)
Robert Nevels
(Member)
Chin Su
(Member)
Guy Battle HI
(Member)
Chan an Singh
(Head o f Department)
August 2002
Major Subject: Electrical Engineering
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ABSTRACT
Microwave Rectifying Circuits and Antennas for Radio Frequency Identification and
Wireless Power Transmission Applications. (August 2002)
Bemd Herbert Strassner
n, B.S., Rose-Hulman Institute o f Technology;
M.S., Texas A&M University
Chair o f Advisory Committee: Dr. Kai Chang
This dissertation covers a variety o f topics. The two main areas o f study are
terrestrial circularly polarized (CP) rectenna arrays and radio frequency identification
(RFID) tags. Some focus has also been given to the development o f dual-frequency
diplexers, and various microstrip, stripline, and coplanar stripline filters.
The CP high gain, high-efficiency rectifying antenna (rectenna) array is designed
in a coplanar stripline circuit. The single element rectenna achieves 81 % RF-to-DC
coversion efficency at 5.71 GHz and uses a coplanar stripline (CPS) band-reject filter
(BRF) to suppress the re-radiated harmonics by more than 19 dB. At 5.61 GHz, using an
array loading o f 150 Q, a 3 x 3 rectenna array produces 0.86 W o f DC output power with
an RF-to-DC conversion efficiency o f 78 % and an axial ratio o f 0.25 dB for an incident
circularly polarized power density o f 7.6 mW/cm2.
The passive 5.8 GHz Radio Frequency Identification (RFID) backscatter tag
proposed for monitoring oil drill pipe is to be inserted into the tool joint o f the drill pipe
in order to predict the pipe’s lifetime and to provide inventory control. The tag requires
a minimal incident power density o f 13.5 mW/cm2 to establish a link and transmit 64-bit
coded information to the interrogating reader. The tag’s physical size has to be small so
that it can be imbedded into the pipe without weakening the structure.
A three-port microstrip multi-frequency diplexer is designed to take 10, 12, 19,
and 21 GHz into port one and to separate 10 and 19 GHz to port two and 12 and 21 GHz
to port three with minimal dispersion. The insertion loss for each frequency varies from
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0.4 dB to 3.4 dB, and the return loss is better than 10 dB.
The isolation between
channels at the four frequencies is greater than 50 dB.
A new low-loss dc-blocking parallel-cascaded bandpass filter is also presented.
The filter is much easier to use and fabricate, more compact, and simpler to design than
the conventional end-coupled or parallel-coupled line filters.
The filter has a wide
passband with a 2:1 VSWR bandwidth o f around 10 % and an insertion loss o f 0.5 dB at
10 GHz.
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V
To my wife Selwa.
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ACKNOWLEDGEMENTS
I would like to express my sincere gratitude to my advisor Dr. Kai Chang for his
guidance and support with regards to my graduate studies and research. My appreciation
goes out to Dr. Robert Nevels, Dr. Chin Su. Dr. Guy Battle, and Dr. Leslie Feigenbaum
for serving as committee members for my dissertation. I would also like to thank Mr. Li
and Mr. Wang at Texas A&M University for their helpful support in the development of
the projects described in this dissertation. I would like to express thanks to Dr. James
McSpadden at Boeing, Dr. Richard M. Dickinson at the Jet Propulsion Laboratory
(NASA), Joe Howell and Gary Johnson at the Marshall Space Flight Center (NASA),
and Dr. Frank Little at Texas A&M University’s Center for Space Power for their helpful
advise and criticism concerning the space solar power project. For advising my efforts
on the oil drill pipe Radio Frequency Identification (RFID) project, I would like to thank
George Savage and Paul Koomey. I would also like to express my gratitude to Mr. Ben
Weber o f Weber Energy. Inc. for funding the patent on this RFID technology and both
Page Heller and Darrell Kuhn o f the Texas A&M Technology Licensing Office for
protecting my rights in this endeavor. Lastly, I would like give thanks to my parents
whose encouragement and financial contributions have made all o f this possible.
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TABLE OF CONTENTS
Page
ABSTRACT.............................................................................................................................. iii
DED ICATION ........................................................................................................................... v
ACKNOW LEDGEMENTS.................................................................................................... vi
TABLE OF CO N TEN TS....................................................................................................... vii
LIST OF FIGURES....................................................................................................................x
CHAPTER
I.
INTRODUCTION....................................................................................................1
Q.
CIRCULAR POLARIZED RECTIFYING ANTENNA....................................7
A. Rectenna Operation Theory............................................................................ 7
B. Simulated and Measured Data for Rectenna Components....................... 19
1) Coplanar Stripline (CPS) Characteristic Impedance........................... 20
2) Circular Polarized (CP) Dual Rhombic Loop Antenna (DRLA)
21
3) Coplanar Stripline Band-Reject Filter (CPS B R F)............................. 23
4) Microstrip to Coplanar Stripline (CPS) B aiuns...................................26
5) Antenna + CPS BRF + Baiun Linear Polarized (LP) Measured
Results........................................................................................................28
6) DC-Pass Filter...........................................................................................37
7) Diode Efficiency Direct-Measurement................................................. 38
8) Rectenna Axial Ratio and Efficiency M easurement........................... 39
IB.
CIRCULARLY POLARIZED RECTIFYING ANTENNA ARRAY
43
A. Array Operation Theory.................................................................................43
B. Array Measurements...................................................................................... 51
C. C onclusions.................................................................................................... 57
IV.
RADIO FREQUENCY IDENTIFICATION FOR DRILL P IP E ................... 58
A. Operational Theory and Component D esign.............................................58
I). Tag System Components........................................................................59
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CHAPTER
Page
2). Tag/Reader Link.......................................................................................62
3) Data Rate....................................................................................................63
B. Digital Subsection........................................................................................... 65
1) Digital Com ponents................................................................................. 65
2) Microcontroller Programming................................................................67
3) Hardware Implementation....................................................................... 70
4) Digital ID C ode......................................................................................... 71
C. Measured Data for RF Subsection................................................................ 73
1) Circular Patch Antenna............................................................................73
2) PIN Diode Modulation Circuit Performance........................................77
3) Tag Free-Space Performance.................................................................. 78
D. Conclusions..................................................................................................... 82
V.
MICROSTRIP DIPLEXERS................................................................................. 83
A. What is a D iplexer?........................................................................................83
B. Two Channel / Two Frequency Band stop D iplexer................................84
C. Two Channel / Four Frequency Parallel-Coupled Band Pass Diplexer.. 86
D. Two Channel / Four Frequency Cymbal Band Pass/LPF D iplexer........88
E. Two Channel / Four Frequency Periodic Structure Diplexers................91
VI.
CONCLUSIONS................................................................................................... 102
REFERENCES........................................................................................................................ 103
APPENDIX 1........................................................................................................................... 108
APPENDIX 0 .......................................................................................................................... 115
APPENDIX IB......................................................................................................................... 122
APPENDIX IV ........................................................................................................................133
APPENDIX V ......................................................................................................................... 135
APPENDIX V I........................................................................................................................ 137
APPENDIX V n .......................................................................................................................142
REFERENCES........................................................................................................................147
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ix
V IT A ........................................................................................................................................ 148
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X
LIST OF FIGURES
FIGURE
Page
1.
Rectenna block diagram and spatial orientation.......................................................7
2.
Half-wave rectifier circuit and waveforms...............................................................8
3.
Half-wave rectifier with capacitor circuit and waveforms.....................................9
4.
Diode IV curves with the incident fundamental and diode junction voltage
waveforms..................................................................................................................... 11
5.
Equivalent model for the rectifying circuit...............................................................12
6.
Calculated diode impedance versus load resistance forVD = 3.5 V...................... 18
7.
Calculated diode impedance versus diode voltage for R l = 250 Q .....................19
8.
Coplanar stripline (CPS) structure (2-D)..................................................................20
9.
IE3D simulated input impedance o f the DRLA located 11 mm above a
reflecting plane.............................................................................................................22
10.
CPS BRF layout and dimensions (in mm)............................................................... 24
11.
IE3D simulated CPS BRF S-parameters.................................................................. 25
12.
Measured back-to-back 50 £2 microstrip to 172 Q CPS balun Sparameters....................................................................................................................27
13.
Rectenna pattern and gain measurement circuit layout. (All dimensions in
m m )............................................................................................................................. 28
14.
Measured and IE3D simulated return loss o f the pattern and gain
measurement circuit................................................................................................... 29
15.
Horn rotation with respect to the rectenna (not to scale)....................................... 30
16.
Linearly polarized rectenna gains: (a) d = 8mm, (b) d = 9 mm, (c) </ = 10
mm, (d) d = 11 mm, (e )d = 12 mm, (f) d = 13 mm.............................................. 31
17.
Measured rectenna axial ratio for different reflecting plane spacings (d)............34
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xi
FIGURE
18.
Page
Measured rectenna linear polarized gains at 5.71 GHz for 0°, 45°, 90°,
135°, 180°, 225°, 270°, and 315° horn orientations............................................... 35
19.
Measured balun-capacitor-balun S-parameters........................................................37
20.
Direct-measured diode conversion efficiency and output voltage versus
power delivered to the diode for various load resistances......................................38
21.
Rectenna element or array measurement setup. Both 5.61 GHz path
losses are measured using a network analyzer.........................................................39
22.
S-parameters between the points 1, 2 and 3 shown in Fig. 21............................... 40
23.
Measured single element rectenna efficiency curves at 5.71 GHz and d =
10 mm for 50 Cl incremental loading. Calculated curves are shown for
the 50 and 200 Cl loading........................................................................................... 42
24.
(a) Array using a honeycomb lattice. The array is etched on 10 mil
substrate with a dielectric constant o f 2.33. (b) Array layout showing
both rectenna and array effective areas along with all relevant spacings.
The innermost 9 elements with the dotted unit cell areas represent the 3 x
3 array that rectifies the incident microwave energy. The remaining
elements are present in order to account for the mutual coupling between
adjacent rectenna elements. This allows the performance o f the 3 x 3
array to predict the performance o f larger arrays.................................................... 43
25.
Fundamental and 2nd harmonic circularly polarized rectenna patterns for d
= 8 mm. A microstrip to coplanar stripline balun is used to acquire the
patterns.......................................................................................................................... 45
26.
S-parameters o f the DRLA + CPS BRF + Balun for various capacitor to
diode spacings. The circles correspond to 5.61 GHz impedances...................... 46
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FIGURE
27.
Page
The left chart represents the Narda 642 standard gain hom 5.61 GHz Eplane and H-plane patterns and their 2nd order polynomial approximation
G</0). Gg(0) has better than 0.2 % accuracy over the interval -10 £ 0<*
10 degrees. The right contour plot shows the array illumination when the
array is positioned 180 cm from the hom antenna. The 9 dotted regions in
the array layout represent the effective area o f the 3 x 3 array (147.8 cm2)
with an average gain o f 15.077 dB............................................................................48
28.
Array axial ratio versus frequency when d = 8 mm. The curve is based on
free-space measurement data taken at 10 MHz increments...................................52
29.
Array output voltage versus circularly polarized power density at 5.61
GHz for various RA values..........................................................................................53
30.
Array output power versus circularly polarized power density at 5.61 GHz
for various array load resistances (RA)...................................................................... 54
31.
Array RF-to-DC conversion efficiency versus circularly polarized power
density at 5.61 GHz for various array loading (RA)................................................ 55
32.
Array RF-to-DC conversion efficiency versus circularly polarized power
density (with and without Zener diodes) at 5.61 GHz for RA = 150 Q ...............56
33.
RFID Tag circuit block diagram. RF and DC represent the microwave
and digital portions, repectively. The voltage VH is the rectified voltage
from the Schottky diode..............................................................................................58
34.
Tag recess and 3-D structure view.............................................................................. 59
35.
3-D spatial orientation o f the tag with respect to the reader’s hom
antenna. The hom antenna is fixed at the point (.*_>,0,0) and the tag rotates
about and moves vertically along the z axis. The vector ux is normal to
the tag’s surface and represents the tag’s broadside orientation...........................61
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Page
FIGURE
36.
Main blocks o f the digital subsection: DC-to-DC converter, clock and the
microcontroller............................................................................................................. 65
37.
DC-to-DC converter schematic.................................................................................. 66
3 8.
Flowchart depicting the basic microcontroller instructions................................... 69
39.
(a) Hardware connections for the DC-to-DC converter, CLK and MCU.
(b) Etched PCB with components. Circles represent vias.....................................70
40.
(a) Microcontroller output for biasing the PIN diode, (b) Microcontroller
output for the three 3 ps oscillations, (c) Microcontroller output when the
0.9V < V„< IV ............................................................................................................ 72
41.
Circular patch dimensions and S-parameters with no recess or Teflon
cover. The circular patch is etched on Duroid 5870 with & = 2.33 and a
thickness o f 1.524 mm................................................................................................ 74
42.
Tag resonant frequency versus Teflon thickness t....................................................75
43.
The left chart shows the E- and H-plane patterns for the standard gain
hom antenna with polynomial approximation 'f/l(0t) in dB. This
approximation is good for -3O°<0,<3O°. The right chart shows the E- and
H-plane patterns for the tag's circular patch antenna with polynomial
approximation
in dB. This approximation is good for -90°< q
<90°. All angles are measured o ff broadside.......................................................... 75
44.
Measured PIN diode modulation for both on- and off-states o f the diode.
For the on-state, V[D- VG = 3 V. Similarly, the off-state occurs when V[D
- VG = 0 V. The RF circuit is etched on Duroid 6010.8 with Sr = 10.8 and
a thickness o f 0.635 mm............................................................................................. 77
45.
RFID measurement setup. When the tag is oriented to receive energy
from the hom in the H-plane, the receive hom should be E-plane oriented
and vise-versa............................................................................................................... 78
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xiv
FIGURE
46.
Page
Demodulated received signal. Vertical scale: 100 mV/div. Horizontal
scale: 200 ps/div.......................................................................................................... 79
47.
Measured rectified voltage VH versus frequency for different linearly
polarized power densities incident upon the tag’s Teflon surface. The
Teflon thickness t = 5 mm which corresponds to a new drill pipe. The
shaded area reveals the voltage region (VH > IV) for when the tag’s
electronics are producing the 64-bit identification code. These curves are
generated for broadside interrogation, i.e. 9r = 0°, fa = 0° and £ = 0° ................. 80
48.
Contour plot showing the transmit power needed to provide the 170 mW
o f 5.8 GHz energy to the Schottky rectifying diode for.r? = 1.0 ft = 30.5
cm. The angle fa varies from -45° to 45°, and the angle 9r ranges from 15° to 15°...................................................................................................................... 81
49.
Diplexer Schematic......................................................................................................83
50.
Rejection stub diplexer for 5.8 and 11.6 GHz..........................................................84
51.
Measured rejection stub diplexer return loss at port 1............................................ 85
52.
Measured rejection stub diplexer insertion loss.......................................................85
53.
Parallel coupled line bandpass filter dual frequency diplexer for 9.4, 11.5,
18, and 21.7 GHz.........................................................................................................86
54.
Parallel-coupled line band pass filter dual frequency diplexer return loss...........87
55.
Parallel-coupled line band pass filter dual frequency diplexer insertion
loss................................................................................................................................. 87
56.
Low pass filter / cymbal band pass filter dual frequency diplexer for 9.5,
11.9, 18, and 20.4 GHz............................................................................................... 89
57.
Low pass filter / cymbal band pass filter dual frequency diplexer return
loss................................................................................................................................. 89
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XV
FIGURE
58.
Page
Low pass filter / cymbal band pass filter dual frequency diplexer insertion
loss................................................................................................................................. 90
59.
(a) Diplexer layout (top-view). (b) Equivalent circuit model................................ 91
60.
Insertion loss for 10, 19 GHz filter............................................................................ 94
61.
Return loss for 10, 19 GHz filter................................................................................95
62.
Insertion loss for 12, 21 GHz filter............................................................................ 96
63.
Return loss for 12, 21 GHz filter............................................................................... 96
64.
S21 and Si2 Insertion loss o f the diplexer...................................................................98
65.
S31 and S n Insertion loss o f the diplexer...................................................................98
66.
Si 1 return loss o f the diplexer..................................................................................... 99
67.
Time delay for both diplexer channels....................................................................... 101
A 1.
Matlab output charts..................................................................................................... 113
A2.
Tag structure for heat transfer analysis. The tag size is a cylinder with a
I" diameter and a 1" height........................................................................................ 115
A3.
Internal temperature versus time when no outer insulation is used....................... 118
A4.
Internal temperature versus time for I mm thick outer insulation.........................119
A5.
Internal temperature versus time for 2 mm thick outer insulation.........................120
A6.
Plane wave power density versus frequency with FCC MPE limits......................134
A7.
Power density P j versus distance s away from 15.3 dB radiating source
for various transmit power levels Ps..........................................................................135
A8.
Bandpass filter schematic and its test fixture............................................................ 136
A9.
IE3D simulated resonant frequency versus L for various W when er = 10.8
and H = 0.635 mm....................................................................................................... 137
A 10. IE3D simulated S-parameters for different substrate thickness H. IP= 11.6
mm, L = 1.83 mm, G = 0.37 mm, and sr = 10.8......................................................138
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xvi
FIGURE
All.
Page
IE3D simulated S-parameters for different substrate dielectric constants
when H = 25 mil. When er = 8, W = 13.5 mm, L = 2.12 mm, and G =
0.42 mm. When er = 10, W = 12.1 mm, L = 1.9 mm, and G = 0.38 mm.
When £r = 12, W - 11 mm, L = 1.73 mm, and G = 0.35 m m ................................ 139
A 12. Measured and simulated S-parameter curves for W = 11.6 mm, L = 1.83
mm, G = 0.37 mm, H = 0.635 mm, and eT = 10.8. A curve representing
the measured insertion loss o f a chip capacitor is also shown...............................140
A13. (a) Planar top-view o f the metallization and its dimensions, (b) Equivalent
circuit model with open-ended stubs represented by series RLC
resonators, (c) 3-D view o f the stripline filter and its aluminum housing..........142
A 14. Simulated and measured performance o f the stripline filter. The passband
is 18.8 to 21.2 GHz, and the rejection band is 27 to 31 GHz................................ 144
A15. Measured time delay...................................................................................................... 145
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xvii
LIST OF TABLES
TABLE
Page
1.
CPS Line Characteristics.............................................................................................21
2.
50 Q to 172 Q Balun Performance.............................................................................27
3.
Linear Polarized Gains for Antenna + CPS BRF + B alun.....................................36
4.
Capacitor Performance................................................................................................ 37
5.
3 x 3 Array Average Gain and Effective A rea......................................................... 51
6.
3 x 3 Array Results for Best Operating Conditions..................................................56
7.
DC-to-DC Converter Output.......................................................................................66
8.
Cost Breakdown o f Tag’s Electronics........................................................................71
9.
Rejection-Stub Diplexer Performance........................................................................86
10.
Parallel-Coupled Line Dual-Frequency DiplexerPerform ance..............................88
11.
LPF/Cymbal Diplexer Performance...........................................................................90
12.
Simulated and Measured Results for Filter 1 ............................................................95
13.
Simulated and Measured Results for Filter 2 ............................................................97
14.
Simulated and Measured Results for the Diplexer...................................................99
A1.
Maximum Temperature Ratings for the Tag’s Digital Electronics..................... 114
A2.
Insulating Foam Thermal Conductivities and Costs per T a g ............................... 115
A3.
Cycle Time for Triple Oscillation Delay................................................................. 127
A4.
Cycle Time for Data Rate D elay.............................................................................. 128
A5.
Numbers in Relevant Bases.......................................................................................132
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1
CHAPTER I
INTRODUCTION
This dissertation is divided into four main chapters. The topics covered in the
chapters are 1) the single element rectenna, 2) rectenna arrays, 3) RFID tags and 4)
microstrip diplexers. Appendixes are added to elaborate on these areas o f research.
The concept o f wireless power transmission (WPT) began over 100 years ago
when Tesla successfully lighted two light bulbs from uncollimated radiated energy
formed from oscillators operating up to 100 MV at 150 kHz [1].
In the 1920’s and
1930’s, Japanese [2] and U.S. researchers [3] conducted feasibility studies into WPT.
With the development o f high-power, high efficiency microwave tubes by Raytheon
Company, Waltham, MA in the 1950’s [4], the concept o f WPT became reality.
In the 1960’s, Raytheon developed a rectifying antenna or rectenna which
converted RF-to-DC power at 2.45 GHz. The rectenna consisted o f a half-wave dipole
antenna with a singie diode placed above a reflecting plane. The rectenna conversion
efficiency also referred to as the percentage o f power converted from RF-to-DC
increased throughout the I960’s and I970’s. The highest conversion efficiency ever
recorded was achieved by Brown in 1977 [5]. Brown used a GaAs-Pt Shottky barrier
diode and aluminum bar dipole and transmission lines to achieve 90.6 % conversion
efficiency at an input microwave power level o f 8 W.
Later, Brown and Triner
developed a printed thin-film version at 2.45 GHz with 85 % conversion efficiency [6].
In 1991 a rectenna element was developed with 72 % conversion efficiency at 35
GHz [7], This frequency shift from the traditional 2.45 GHz to 35 GHz resulted in much
smaller aperture areas, however the components necessary for generating high power at
35 GHz are inefficient and expensive.
The journal model for this dissertation is IEEE Transactions on Microwave Theory and Techniques.
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Due to the disadvantages noted at 35 GHz, a new operating frequency or 5.8 GHz
was investigated. 5.8 GHz has smaller component sizes and greater transmission ranges
than 2.45 GHz. In 1992, the first C-band rectenna yielded 80 % conversion efficiency
[8]. These efficiencies were measured in a waveguide simulator with an input power
level o f approximately 700 mW per element. This rectenna used a printed dipole which
fed a Si Shottky diode quad bridge. In 1998, McSpadden et. ai. used a printed dipole
rectenna to achieve the highest conversion efficiency for 5.8 GHz at 82 % [9], The
rectenna used a single MA40150-119 diode for rectification on a coplanar stripline
(CPS) layout.
In order to rectify large amounts o f power, many rectennas must be combined
into an array.
In 1975. the Jet Propulsion Laboratory and Raytheon transferred DC
power from one location to another with 54 % efficiency. This included a 68.9 % DC to
microwave conversion at 2.45 GHz, 95 % effective area capture and 82.4 % diode
conversion [10].
Then in 1998 a group in Japan achieved 64 % array RF-to-DC
conversion at 2.45 GHz. This array consisted o f 2,294 dipoles each having 16 diodes for
high power rectification [11]. Another group at JPL was able to operate a dual-polarized
rectenna array with a conversion efficiency around 52 % at 8.51 GHz for 50 V output
[ 12].
In the last few years, researchers have looked into the designing o f circularly
polarized rectennas. Circular polarization (CP) enables the recieve or transmit antennas
to be rotated without changing the output voltage. Suh et. al. achieved 60 % RF-to-DC
conversion efficiency for a single CP rectenna element at 5.8 GHz [13] using a truncated
patch and microstrip circuit. Hagerty and Popovic used spiral rectennas for broadband
rectification [14].
However these spirals have relatively low gain resulting in lower
efficiencies compared with that o f dipole antennas.
The rectenna array design discussed in this dissertation combines high efficiency
RF-to-DC diode conversion with a wideband, high-gain, circularly polarized array to
produce DC power regardless o f the array’s orientation [15]. The new array is fabricated
on a single thin layer using coplanar stripline transmission lines for fabrication simplicity
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3
and size reduction. This array design is being done as part o f a feasibility study for a
NASA project on space solar power. Large space solar power satellites (SSPs) are to be
put in space to collect the sun’s energy with the use o f solar cells. The solar cell’s
outputted DC power is then converted to microwave energy using magnetrons located on
antennas in a phased array. The phased array beams the collected microwave energy to
fixed locations on the earth. Since the orientation o f the SSPs is non-uniform and the
transmitted energy may or may not be CP, the rectenna array must be CP in order to
provide a continuous and constant DC power at its output.
The harmful second
harmonic frequency generated by the array’s diodes is prohibited from re-radiation with
the use of a filter located behind the antenna.
Traditionally, rectennas have used dipoles or patch antennas with low gains.
Here a dual rhombic loop antenna is used with a CP gain o f 11 dB. The use o f a high
gain antenna has the advantage o f reducing the number o f rectenna elements (diodes,
capacitors, etc.) necessary to cover the same receiving area. The effective area o f an
antenna is proportional to its gain.
The higher antenna gain corresponds to a larger
effective area.
RFID systems are used for identifying and tracking objects as in the case o f
automobile tolling [16], collision avoidance [17], and security systems [18].
Other
applications include baggage tracking in airports [19], [20], land mine detection [21] and
even identifying sea mammals [22], but its benefit to the oil industry has not been fully
explored [23]. Most RFID systems consist o f a reader and a tag. The reader transmits
power to the tag which then sends a coded signal back to the reader [24], [25]. For oil
drill pipe monitoring, this coded signal contains information about the drill pipe being
used including the drill pipe identification, size and previous usage. The RFID tag will
provide automatic tracking o f both the up and down and rotational movement o f the drill
pipe.
With this information, someone monitoring the drill pipe can determine its
cumulative use and when it needs to be replaced. Drilling holes for tapping oil reserves
is a costly and complex undertaking. When a drill pipe is overused and breaks in the
ground, the hole leading to the oil supply, which is now blocked by the broken drill pipe,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4
must be abandoned. This is a very costly problem, especially for offshore operations,
because a new hole must be dug which can reach depths o f more than 20,000 ft. To
avoid these pipe failures, drill pipe is presently being replaced after about 25 % o f its
lifetime has elapsed. Better inventory and usage control will enable the pipes to be used
for longer periods o f time, i.e. 75 % o f their lifetimes, resulting in huge cost savings for
oil drilling companies.
The idea o f placing a radio frequency identification tag on the drill pipe for
monitoring purposes has been around for over a decade now [26]. The tags presently
used operate in the kHz range and have read ranges on the order o f an inch. These short
read ranges are due to the low gain loop antennas that serve to receive and transmit the
energy. The reader must also pass the tag at a slow velocity due to the slow data rate
which is directly dependent upon the frequency o f operation. Due to the short read range
and the slow data rate, the drilling is shutdown in order to accurately read the tag. The
cost o f shutting down operations for reading the tag and then to restart the drilling
process is around S30,000. These costs can quickly escalate justifying the need for a way
to efficiently monitor the drill pipe's history as it is operating.
The reader interrogates the tag whenever the tag leaves the “down hole”
environment and rises above the earth’s surface. The “down hole” environment that the
tag invades is extremely harsh. Temperature can reach 245°C and the outside pressures
normal to the tag's surface can exceed 20,000 pounds per square inch (psi). Most RFID
systems use batteries to drive their “on-board” electronics.
storage temperatures batteries often fail.
However, at these high
An alternative for powering the tag’s
electronics is to use rectifying circuits that convert microwave energy into DC energy.
Rectifying circuits are instrumental in rectifying antennas [15] and “passive” RFID
applications [27].
This rectification is achieved when microwave energy is incident
upon a Schottky detector diode. The Schottky diode, through a mixing process, converts
a large percentage o f the microwave energy into DC power. The rectified or DC portion
o f the energy is then used to power the electronics that create the tag’s unique
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5
identification.
Since no battery is present, the tag is referred to as a “passive” or
backscatter RFID tag.
While most existing microwave RFID technologies are designed at 2.45 GHz
[28], [29], [30], the system being proposed is a passive system operating at 5.8 GHz.
This frequency is chosen because it is an ISM band, but mainly because o f size
restrictions on the tag. The tag must fit in a cylinder V* in. tall and 1 in. in diameter.
This size restriction is due to the rotational stresses on the oil drill pipe. If too large a tag
is used, the structural integrity o f the pipe’s high-grade steel is compromised which
could lead to the pipe twisting into multiple pieces.
The smaller tag also has the
advantage o f having less pressure normal to its surface. The tag’s structure must be
designed to isolate the outside 20.000 psi pressure from reaching the sensitive
electronics.
The last obstacle to designing the tag for drill pipe monitoring is the presence of
drill mud on the pipe’s surface during interrogation. This mud functions as a drill bit
lubricant and transport of rock and materials from the drilling location to the earth’s
surface. The reader interrogates the tag when the pipe surfaces. At this time a thin film
o f drill mud may be present on the pipe’s surface. The reader/tag link must be able to
penetrate this thin wet mud layer. Many ideas o f how to reduce the mud on the tag such
as water and air jets are being looked at. The design presented will address some of
these problem issues associated with real-time drill pipe monitoring.
Diplexers are three terminal devices that take two or more frequencies into one
input port and separate them to two output ports. They are commonly used behind wide­
band or multi-frequency antennas in transciever applications. Diplexers became widely
studied in the early 60’s by Matthaei et. al. [31], [32] and Wendel [33]. They studied
microstrip diplexers that used band-pass/band-stop configurations as well as waveguide
diplexers.
In the late 1960’s waveguides became widely used due to their very low
insertion loss and high isolation.
However, waveguides generally entail much more
manufacturing complexity than planar etched microstrip diplexers.
For this reason,
microstrip diplexers have remained an active area o f research. In the I990’s, microstrip
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6
diplexers such as low-pass/band-bass [34] and ring diplexers [35] have gained notice
[36].
The diplexer presented in this dissertation uses balanced open-circuited periodic
stubs as band-stop networks to provide both low loss and high isolation between the
channels. The periodic stub geometry requires no gaps making the etching very reliable
and accurate. The design provides the advantages o f low loss, high isolation between
channels and wideband channel performance without the etching uncertainty found in
gap- coupled filters. In 1996, Sheta et. al. [37] used spurious harmonic modes for pass
bands in order to reduce the number o f filters. The diplexer in this paper utilizes pass
bands formed between adjacent harmonic stop bands for size reduction and matching
simplicity.
In the following, Chapter II describes the new CP rectenna using a dual rhombic
loop antenna. Chapter III discusses its array implementation and results. Chapter IV
presents a tag for oil drill pipe, and Chapter V discusses various microstrip diplexers.
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7
CHAPTER Q
CIRCULAR POLARIZED RECTIFYING ANTENNA
.L Rectenna Operation Theory
Fig. 1 diagrams the main components necessary for efficient rectenna operation.
Tuning Stubs
Termination Gap (Left-Hand CP)
Dual Rhombic Loop Antenna
Detector Diode
Resistive
Load
(R ,)
172 a
a .y tf = 0
<p'= 0° p o sitio n j
Fig. 1. Rectenna block diagram and spatial orientation.
The high-gain antenna couples power into the coplanar stripline (CPS) circuit. A bandreject filter located behind the antenna allows the incoming power at 5.8 GHz to pass to
the detector diode where a large portion o f the RF power is converted to DC power. The
remaining RF portion is bounced between the band-reject filter and the DC-pass filter
where it remixes at the diode and forms more DC. The resistive load (R l) is isolated
from any RF signals because o f the DC pass filter. /?/. must be chosen such that the DC-
• c 2001 IEEE.
Pans o f this chapter are reprinted, with permission, from B. Strassner and K. Chang, "5.8 GHz
Circular Polanzed Rectifying Antenna for Microwave Power Transmission.” IEEE \IT T -S Int. Microwave Syrnp Dig..
Phoenix. AZ. May 2001. pp. IS59-IS62.
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8
converted portion o f the RF power is maximized. Proper placement o f the diode and
filters is also crucial to maximizing the DC power.
Before examining specific diode performance, it is important to understand how
both a half-wave rectifier (diode) and, in the case o f the rectenna, a half-wave rectifier
with shunted capacitor work. The half-wave rectifier and its corresponding waveforms
are shown in Fig. 2.
v s(t) = Vp COS (o t ©
Diode ON
\
Diode OFF
Z y 0
/D io d e ON
Fis. 2. Half-wave rectifier circuit and waveforms.
The 5.8 GHz energy that is incident upon the diode is denoted by l»s(/). The positive
cycles o f this energy are then rectified by the diode to form the diode current
The
average DC diode current Id is found from /l(0 by
I w,
f— cos cotdt + f — cos coidt
J) nRL
P
irJr"L
(I)
where T is the period and the frequency (o— 2idT. Solving this integral gives an average
DC current o f Vp!(RL 7t). By applying Ohm’s law the average diode DC voltage is Vpln.
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9
This “rms" voltage is used to compute conversion efficiency. It is the effective voltage
or the voltage that effectively heats the load resistor R l.
The rectenna circuit o f Fig. 3 implements the half-wave rectifier circuit with the
addition o f the DC-pass filter capacitor where the capacitor is in shunt with the diode.
os(t) = VpCOSa) f (Q
A vD =p C
max'
mm
OFF
ON
'on '
OFF
'on
Fig. 3. Half-wave rectifier with capacitor circuit and waveforms.
The voltage across the load as a function o f time is
t
t
oL{ t ) ^ { V P- Q ) e " ^
(2)
where R lC is the time constant, V'P is the initial value and 0 is the final voltage if the
capacitor completely discharges.
The time t is measured from the peak where the
voltage is equal to VP. Since the rectenna’s operating frequency (5.8 GHz) has such a
short period in comparison with the RLC time constant, the exponential decrease in the
voltage can be approximated by a straight line as shown in Fig. 3. By series expanding,
(2) becomes
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10
'
/
v
R lc )
l—
(3)
r lc
Since the decreasing voltage has been approximated as a straight line, the linear terms o f
(3) are kept and the minimum voltage at t - T becomes
I
.
T )
(
1
— \ = VP I —
fR Lc
Rlc )
\
(4)
Once the diode voltage drops to Vmin, the diode turns on and the voltage again
approaches Vnuix = VP. The peak-to-peak ripple o f the voltage waveform is
V
Vr = Vmax - V nun = —
/ tj
(5)'
✓-*
v
and the average DC diode voltage present across the load resistor is
Vttux - V nun
j/
1
~ -JR-lC .
* yP
(6)
The period o f the incoming 5.8 GHz energy is 172.4 ps. The capacitance o f the DC-pass
filter is approximately 2400 pF.
This translates to R[C »
T. Therefore, the ripple
voltage Vr is very small, and the average diode DC voltage is VD - VP. This average DC
diode voltage is also known as the self-bias voltage used in further analysis.
The diode conversion efficiency (//D) is key in determining the rectenna’s
performance. The diode efficiency is defined as the following ratio:
_
DC output power
RF power incident on diode
A diode model described by Yoo [38] is used to predict the rectenna diode’s efficiency.
The model depends only on the diode electrical parameters and microwave circuit losses
at the fundamental frequency o f operation.
Harmonic effects are not included. This
diode theory accounts for various power levels incident upon the rectifying diode.
i
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tl
The diode's rectifying behavior is presented in Fig. 4. The voltage wave incident
upon the diode is expressed as
V[ = -V q + Vp cos (cot)
(8)
where VD is the self-bias DC output voltage across the resistive load RL, and VP is the
peak voltage amplitude o f the incident power. The rectifying diode acts as a mixer and
produces a self-bias voltage. As more power is incident upon the diode, the rectified
self-biasing will become more reversed biased.
Phase
0 = cot -(p
Fig. 4.
Diode IV curves with the incident fundamental and diode junction voltage
waveforms.
The diode junction voltage is
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12
(9)
where Ko and Vji are the DC and fundamental frequency components o f the diode
junction voltage, respectively. Vbi is the built-in tum-on voltage o f the diode. When the
diode’s junction voltage exceeds Vbt, the diode operates in forward conduction. The
tum-on angle denoting forward bias operation is Qon. Fig. 4 also shows that the diode's
junction waveform slightly lags the incident power by the phase difference (ft.
The equivalent circuit used for determining the diode’s efficiency is shown in
Fig. 5. The diode parasitics are excluded from the circuit. The model consists o f a series
resistance /?y, both a nonlinear junction resistance R, and capacitance Cy, and a load
resistor R l connected in parallel to the diode.
R, is assumed to be zero for forward bias
and infinite for reverse bias. By using K irchoff s voltage law, equations describing the
diode's efficiency and input impedance are obtained.
i
*- i
W-,-- -
+
Fig. 5. Equivalent model for the rectifying circuit.
The next step in determining the diode’s efficiency is to find Gon. A series o f
steps is carried out to determine 9on- First K irchoff s voltage law is used to obtain
(1 0 )
and
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13
VD = t D RL
(ll)
V, must be expresses as the DC voltage VJ lic to distinguish it from its time-varying form
Vj. Combining (10) and (11), the output DC voltage VD is
vn = -v. , — RI-—
D
j^
d 2)
+r l
rs
The DC output voltage across the load resistor R l is determined from the rectified
voltage wave across the diode junction ( Vj). The average value o f Vj over one cycle is
1 ®on
t-'r ~@on /
\
V. . = —
I V ,.d d + —
f
\ - V . n + V ..c o s 0 d0
J'dc I n - q
hl
In a
\ J°
A
)
°on
°on
The first integral term in (13) represents a forward-biased junction.
(13)
Similarity, the
second term accounts for the reverse-biased case. Computation o f (13) gives
r
= ^°!L y _ v
j.d c
iT hi
jO
0,on
n
\
V
— sin0o„
n
.
(14)
When the diode is forward-biased. Vt is equal to V,„. Applying this to (14) gives
~Vjo + Vjj cosQon = V^.
( 15)
When the diode is reverse-biased. R, is infinite. Applying K irchoff s voltage law to the
other circuit loop yields
-V f + fRs + Vj = 0
(16)
and
dev.
/ = —7—
Jt
(17)
Combining (16) and (17) gives
d [c j yj )
dt
(18)
Rs
where C, is expressed as a harmonic function o f VD.
C j = C q c o s ( f y r -<f>) + C1 cos{2cot
+ ...
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(19)
14
This Cj expression is inserted into (18) to yield
coRs ( q V jQ - CQVjX js in 9 = V .Q - V D + [vp c o s $ - VjX Jcos9 - Vp sin <f>sin 9 (20)
where 9 = ax - tf>. Collecting similar terms results in
>
(21)
= VD
V jX=Vp cos<p
l p sin<f>= coRs
( 22 )
- C qVj X)
(23)
Applying (21) to (14) and inputting (12) into (14) gives
9r
1 sin 9on - —
RS _
RL
VD
1+
Vbi ^
(24)
<T
k
The phase difference <pbetween the voltage waveforms can be assumed to be zero. This
approximation results in Vp = V/{.
Inserting this and (21) into both (15) and (24)
provides
/T Rr,
tan 6on ~ 0On = '
R,
1+
V
bi
(25)
r
D
This transcendental expression allows for 9on to be obtained iteratively. 9„„ is dependent
upon the input power which determines both Vhl and VD.
The diode efficiency is
Id
dc
(26)
PL + P<ic
where Ptic is the DC output power across R l, and PL is the power dissipated by the diode.
Puc and P l are given by
p,
dc
j
L
H
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(27)
15
P r
L
— L
n +
on,R^
L
r r
+ Z.
j- j
on,diode
n
o ff
(28)
The diode loss P l is separted into its three components. These are expressed as
i
"on
I
( V , - V b i )
L „ =—
f — ----- ^ ^ d 9
on.R^ 2,t _a
/?c
°on
S
(29)
I 2* - % n { V r - V t .)
- « • » = —
° f f * S3
,
I
2*
—
9
°on
----- —
(30)
d 9
RSc
i * r ( yr
—
yb , K te
....
rs—
<31)
de
These losses are simply the current flowing through an element multiplied by the voltage
across the element. In the case o f (31). the current flowing through the diode junction is
(V - l)„) Rs and the voltage across the junction is V,„. The power dissipated is the timeaverage o f their product. The loss due to the diode's o ff cycle is negligible since
R ,
is
assumed to be infinite. The series resistance loss for one cycle is found from (29) and
(3 0 )to be
RS
®on .
.2
,
\2
j [~VD - Vbi + Vp cos9) d9 + \coRs C jV p
2kR
S ~®on
Oon
j
s in ' 9d9
@on
(32)
To solve this expression, the second integral is obtained from the RF current rather than
using voltage. (30) is rewritten as
° ff-RS
3
2k
q
aon
2k
S
a
aon
R c
S
where I is the RF current flowing through the diode in reverse bias. Assuming that there
is no current flowing through R, in reverse bias, all o f the current flowing through Rs
flows through C;. Thus ( 17) is written as
dV
r = c Ji ~dtr
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<34>
16
The phase <f>is equal to zero since the voltage drop across Rs is small during the off
portion o f the cycle. From (24), this results in Vjt = VP. Thus
I =C
cl
J dt
■V0 + Vp cos(iot) = -coC jV p sin 9
(35)
The diode’s junction loss over one cycle from (31) is rewritten as
I
^on
t
\
L ,. , = — -—
f V, . ( —Vn —V ..+ Vp c o s9 )d 9
diode
A
b i\ D
bi
P
I
~ S ' eon
(36)
where VP is found from the diode’s off-state as
=
V'
+ V, .
D ' bi
cos 0.on
(37)
Using the results from (32) and (36) and inserting them into (26). the diode's RF-to-DC
conversion is written as
1
n D ~ 1+A+B+C
(38)
where
Rl^ ! l + - bi
.4 = —
flRc
D
B=
9,on 1 + -
RS RLCJ~c°~ '
Rr^~
c =—
rrRa
l
2 cos“ 9,on
1 ^ hi 1 -T @on
VD J U o s -9 ,on
+^
r. * ( tan&on
yD ) VD
— tan 9,on
tan 0,on
&on )
(39)
(40)
(41)
and co is the angular frequency (2 xf). The diode’s junction capacitance C, is
bi
c / = c /< w w +
' t
(42)
D
where CJO is the diode’s zero bias junction capacitance.
The diode's input impedance is determined from the current / flowing through
Rs- The current during one cycle is
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17
/ = / q + /^cos(< yr) + / 1/.sin(<yf)
(43)
where In is the DC component and 7/r and //, are the real and imaginary parts o f the
fundamental frequency current component, respectively.
The individual current
components are given by
I
f°
2xR ,
l/ '
= -----
.T R ,
x
-X 9on /
j (vr vbi)de+ J
dO
[yt ~ vj
(44)
9on ,
x
~/T 9on
J [ V f- V ^ . Jcos(0-h0)dO +
)
\ V [ - V j jco s(0 + 0 )r/0 > (45)
~9on
1
9on
I
u n
h
9on ,
/
x
—
~ u n
i
\
on ,
—
9on
,
“>T ?on
J [ V j - V hi ) s i n ( 0 + 0 ) r / 0 +
J
^ - F y j s i n {0 + (/))dQ
v =—
li
x R S( I " Owon
rtrt
O nn
won
u n
/
\
(46)
The input inpedance o f the diode at the fundamental frequency o f operation is
Z n = ------^ ---D hlr ~ jl\
J 1/
(47)
Assuming that during forward-bias there is no current flow through C, and that the
opposite is true during reverse-bias. the diode current in one cycle is found by integrating
1 9on ,
x
(° C jV p - K ~9on -)
I. - / / , - = ------ I \ - V n - V , . + VDcosO \cos0d0 + j
----|
s\n~ Odd (48)
lr
Xl x R s - e r ..X D
bi
P
!
*
on
on
The diode input resistance is defined as
ZD =
(49)
X -0 ,
0,
—- + sin 6,on
cos 0,on
92— - sin 0,on + jcoR^C
J cos 0.on
cos 0,on
The DC-pass filter located near the diode is used to tune out the imaginary part o f this
diode impedance in order to match the diode to the other circuit elements.
The diode used in the rectenna circuit is the M/A COM detector diode
MA4E1317. It has series resistance Rs = 4 Q, zero-bias juction capacitance C,0 = 0.02
pF, built-in tum-on voltage Vbi = 0.7 V, and breakdown voltage VB = 7 V. The load
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18
resistance (R l) has been chosen to be 250 Q. For this load resistance, Zo = 170.1 - j 9.1
Q at 5.8 GHz and V&1 = 3.5 V as shown in Fig. 6.
300
250
0
200
CO
150
O
c
0
0
0
0
o
c
CO
o
-15 0
0
a:
CE
Diode R esistance
100
-20
Diode R eactance
-25
50
130 155
180 205 230 255 280 305 330
Load R esistance (Q)
355 380
Fig. 6. Calculated diode impedance versus load resistance for VD = 3.5 V.
The DC-pass filter (capacitor) acts as a shorted stub matching network to not only tune
out this diode reactance but also to optimize the remixing o f the power at the harmonic
frequencies. The diode should not be designed to operate more than 3.5 V since this
would exceed V# 2 and could force the diode into avalanche breakdown. However, this
diode has been shown to produce output voltages up to 5 V. Fig. 7 shows the effects the
diode output voltage has on the diode impedance.
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19
600
3
550
-30
500
-70
450
-110
| 400
CO
w 350
cn
£ 300
Diode R esistance
Diode R eactance
©
-150 (J
c
03
o
CO
-230
250
-270
200
-310
150
A
-350
2
3
Diode Voltage (V)
Fig. 7. Calculated diode impedance versus diode voltage for RL = 250 Q.
The diode should be pushed to its voltage limits to minimize the reactance. The diode
resistance at 3.5
V
is slightly above 170 Q. The CPS transmission line which allows
power to flow between the various rectenna components is designed to have a
characteristic impedance Z0 = 172 Q. This minimizes the reflection o f the 5.8 GHz RF
power at the diode terminals thus increasing the rectenna’s efficiency.
B. Simulated and Measured Data fo r Rectenna Components
The rectenna outlined in Fig. I consists o f an antenna, band-reject filter, Shottky
detector diode, DC-pass filter and a resistive load. The antenna and band-reject filter are
designed using the full wave electromagnetic simulator IE3D [39]. IE3D allows for all
o f the sections to be analyzed together and can de-embed sections when necessary. For
an analytical characterization o f the rectenna see Appendix I.
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20
I) Coplanar Stripline (CPS) Characteristic Impedance
Coplanar stripline is used because o f its compact size and high characteristic
impedance. A 2-D view o f the coplanar stripline structure is shown in Fig. 8.
w
Electric Field Lines
g
VV ’
Magnetic Field Lines
►
Fig. 8. Coplanar stripline (CPS) structure (2-D)
The coplanar stripline (CPS) width (w) and gap (g) are 0.824 mm and 0.4 mm.
respectively. The substrate thickness (h) is 10 mils and the conductor thickness (t) is 1
ounce copper or 1.4 mils thick. The dielectric constant o f the substrate is 2.33. The very
thin 10 mil substrate is chosen so that the rectenna will have air (er - I) both above and
below its antenna. This allows for radiation efficiencies very close to 100 % since there
is no impedance mismatch due to different adjacent mediums. The CPS dimensions
provide the proper size for diode and capacitor bonding and the desired CPS
characteristic impedance (172 Q).
The impedance o f CPS is higher than that of
microstrip and matches better to the real input impedance o f the diode. The calculated
CPS characteristic impedance is [45]
Z
I20;r
where
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(50)
21
g
k = 1\
t g + 2w,
(51)
The width and gap are represented by w and g, respectively. IE3D reveals the effective
dielectric constant at 5.8 GHz to be 1.37.
From Equation (50), the calculated CPS
characteristic impedance is 180 Q. The electromagnetic simulator IE3D simulated CPS
characteristic impedance and guided wavelength data is listed in Table I. The imaginary
part o f Z0 is due to slight mismatch predicted by IE3D.
Table I. CPS Line Characteristics
Z0 (Q)
Aa (cm)
Ag (cm)
5.8 GHz
172.4- j 0.2
5.17
4.47
11.6 GHz
174.6- j 1.5
2.59
2.24
17.4 GHz
177.8- j 4.5
1.72
1.49
2) Circular Polarized (CP) Dual Rhombic Loop Antenna (DRLA)
The rectenna uses a dual rhombic loop antenna (DRLA) configuration [40] as
seen in Fig. I. The authors o f [40] suggest the width o f the rhombic loop sections to be
0.016 Aa or 0.824 mm at 5.8 GHz.
This also corresponds to the width o f the CPS
transmission line. In addition, the perimeter length o f one rhombic loop square section
should be approximately 1.29 A0 or 66.7 mm (= 16.1171 mm x 4).
The third
recommendation from [40] is that the middle o f the CPS lines should be separated by
0.025
or 1.29 mm. The center o f the CPS lines is separated by 1.224 mm. This
determines the separation o f the two rhombic loops o f the antenna.
The DRLA is
terminated with two gaps. The positioning o f the gaps as shown in Fig. I yields lefthand circular polarization. If the gaps are mirrored to the opposing sides o f the antenna,
the DRLA will become right-hand circular polarized.
Circular polarization is very
sensitive to the gap position. The advantages for using the DRLA are high CP gain,
wideband performance, and fabrication simplicity. The reflecting plane located 11 mm
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
22
(0.21 Ao) behind the antenna increases the gain by directing the beam broadside in one
direction. The separation o f 0.21 k a is suggested by [40] and shown to be desirable from
IE3D simulation. The CPS tuning stubs yield a real impedance at the antenna’s input
terminals and allow for the individual rectenna to be connected to other rectennas in an
array. IE3D simulated antenna input impedance data is shown in Fig. 9.
300
350
DRLA R esistance
300
200
DRLA R eactance
100
W1 250
<D
O
8
|1/5 200
C
o
C/D
c 150
-100
100
-200
CO
CD
300
5
5.2 5.4
5.6 5.8 6 6.2 6.4 6.6 6.8
Frequency (GHz)
7
Fig. 9. LE3D simulated input impedance o f the DRLA located 11 mm above a reflecting
plane.
The input impedance (Zm) at the antenna’s input terminals for the resonant
frequency 5.8 GHz is shown to be 250 Q. A slight saddle region exist around 5.8 GHz
improving the antenna’s bandwidth. To find the antenna’s simulated input impedances,
radiation patterns and circular polarization, the antenna must be simulated in IE3D with
the band-reject filter in place since the filter will couple to the antenna and affect the
radiation. The filter is then de-embedded in IE3D to find the input impedances.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
23
3) Coplanar Stripline Band-Reject Filter (CPS BRF)
The coplanar stripline band-reject filter (CPS BRF) shown in Fig. 10 is used to
pass 5.8 GHz from the antenna to the diode and block the 2nd harmonic 11.6 GHz from
flowing from the diode to the antenna. The filter’s geometry improves upon existing
band-reject designs [41] by adding additional stubs on the outside o f the main CPS lines
for better rejection. The CPS BRF uses )J4 stubs to block 11.6 GHz. This filter has
high harmonic rejection in comparison with other planar CPS geometries o f comparable
size.
The filter's simulated S-parameters from LE3D are shown in Fig. 11.
IE3D
predicts an insertion loss o f 0.3 dB and a return loss o f 30 dB at 5.8 GHz from the
antenna to the diode. The filter blocks 11.6 GHz flowing from the diode to the antenna
by more than 20 dB.
The diode-side port o f the CPS BRF is terminated to the
characteristic impedance o f the CPS or 172 Q. The antenna-side port o f the filter has a
different port impedance (Zm) for every different frequency. At 5.8 GHz, the CPS BRF’s
antenna-side port impedance is 250 Q, and the diode-side port impedance is 172 Q.
Therefore, at 5.8 GHz. the filter matches the DRLA to the resistance o f the detector
diode.
The filter's antenna-side impedance can be determined by de-embedding the
filter from the antenna - filter 1E3D simulation. However, for many o f the frequencies,
the real part o f the antenna input impedance (Z,„) is negative as revealed by the de­
embedding process.
These negative values cannot be interpreted by IE3D as port
terminations to determine the filter’s insertion loss. To determine the insertion loss of
the filter, the following method must be used.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 10. CPS BRF layout and dimensions (in mm).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
25
0 T
Insertion Loss
Return Loss
-30 — *------------------------------------ u --------------------------------------5
6
7
8
9 10 11 12 13 14 15 16 17 18
Frequency (GHz)
Fig. 11. IE3D simulated CPS BRF S-parameters.
The relative gain
o f the antenna is related to its directive gain
by
(52)
where q, is the total overall radiation efficiency o f the antenna ~ filter combination and
both the gain and directivity are in ratio numbers. The overall radiation efficiency is
defined as
(53)
where qr represents the antenna radiation efficiency (product o f the conductor and
dielectric efficiency losses), T is the reflection coefficient and IL is the insertion loss o f
the band-reject filter. T is denoted by
(54)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
26
where Zp is the impedance looking into the diode-side o f the filter + antenna and ZQis the
characteristic impedance o f port which is always set by IE3D to 50 Q. Zp has a real part
Re (Zp) and an imaginary part Im (Zp). The mismatch loss (I -
|r|~) is
7
lOOIm(Zp)
(55)
( Re ( Z p ) + 5o)“ + Im ( Z p )“
( Re( Z p ) + 5o)“ + Im ( Z p )
IE3D provides simulated data for the maximum gain and directivity and radiation
efficiency ( rjcti} of the antenna + filter over a defined frequency range. Since rjr is very
close to 100 %. it does not have a significant affect on the filter’s insertion loss. The
gain data is lower than the directivity by both the mismatch loss and the antenna's
radiation efficiency according to (53) as well as the additional loss IL. This additional
loss is embedded in lE3D’s simulated gain data. The insertion loss o f the filter is given
as
Gg { 0 .t)
(56)
If the filter is lossless. [L is equal to 1 (0 dB) as is nearly the case at 5.8 GHz. This
process makes it possible to witness the filter’s behavior as shown in Fig. 11 since useful
measured data is impossible to obtain due to the variation o f the antenna-side port
impedance versus frequency.
4) Microstrip to Coplanar Stripline (CPS) Baiuns
In order to measure various patterns and S-parameters o f the antenna and bandreject filter, a balun must be designed which matches the 172 Q CPS BRP diode-side
impedance to 50 Q microstrip line. For measurement purposes, two o f the baluns must
be placed back-to-back. The return and insertion losses are shown in Fig. 12.
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
27
0
-5
XXXJ
A
T§ "10
(1)
I'E -15
§ -20
05
-25
-30
/V /
■ > /
*
1
f
r x x /i
•* *
,<\
a
I
J '
• 1
i
A / v
/ v
' * • ' I 1
' 1
' A ; ■». i # /
'
t 1 *. •* •
; •. <
A
•»
/ i
'
■•*
« :«
;»
' i*
H
____________ *______ ||
8
IT T
«\ ^ A
' 4' ' i 1
A •
»j
•»* l |
» : ' ■ ■ »! j
^
* *. i
;
»■ '■
•.
I
A
1 I l!
? ,!
«l
»• i
? j
• I
*■ ».
•_____ U
j. . . Return Loss !
—
Insertion Loss i
10
12
14
Frequency (GHz)
16
18
20
Fig. 12. Measured back-to-back 50 Q microstrip to 172 Q CPS balun S-parameters.
The return losses at 5.8 GHz, 11.6 GHz and 17.4 GHz are listed in Table 2.
Table 2. 50 Q to 172 f i Balun Performance
Return loss (dB)
Insertion loss (dB)
Vz Insertion loss (dB)
5.8 GHz
20
0.42
0.21
11.6 GHz
20
0.44
0.22
17.4 GHz
10.2
l .l
0.55
Zi o f the total loss represents one side o f the back-to-back balun circuit or one microstrip
to CPS transition. The balun is impedance-matched at both 5.8 and 11.6 GHz. The
back-to-back balun shows a broadband operation with an insertion loss o f less than 2 dB
and a return loss better than 10 dB for 5 to 20 GHz.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
28
5) Antenna + CPS BRF + Balun Linear Polarized (LP) Measured Results
To obtain an accurate measurement for the rectenna, the antenna and band-reject
filter must be both simulated and measured together due to coupling between the two
sections.
The circuit used to obtain the rectenna’s return loss, patterns and gain
measurements is shown in Fis. 13.
13.69
16.12
2.75
0.82
0.82
Balun Ground
0.4
6.8
18.42
36.3
Rectenna Circuit Layer
Metallization
2.02
Substrate ( g ,- 2.33, Thickness = 10 mils)
d = 10.5 mm Air Gap
f
Balun
Ground
Fig. 13. Rectenna pattern and gain measurement circuit layout. (All dimensions in mm).
The circuit includes the DRLA, CPS BRF and CPS to microstrip balun. Using
the HP 8510B network analyzer measurement system, the return loss or 5// was obtained
as shown in Fig. 14.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
29
-3
3 -io
■15
^o
.?n
»u
Simulated Return Loss with balun
■Measured Return Loss with balun
Simulated Return Loss without balun
-25 -30
5
6
7
8
9
10 11 12 13
Frequency (GHz)
14
15
16
17
18
Fig. 14. Measured and IE3D simulated return loss o f the pattern and gain measurement
circuit.
Slight differences between the simulated and measured return losses are
attributed to difficulties in precisely aligning the balun’s top layer with the balun’s
ground layer. At the fundamental frequency 5.8 GHz, S n = -18.3 dB. At the second
harmonic frequency 11.6 GHz. S u = -1.1 dB. and, at the third harmonic 17.4 GHz, Su =
-8.8 dB. Therefore. 5.8 GHz will pass through with low loss, and the second harmonic
11.6 GHz will have high loss. The 2:1 VSWR bandwidth centered about 5.8 GHz is 10
%.
In order to find the rectennas circularly polarized gain, the rectenna’s linearly
polarized gains must first be characterized in an anechoic chamber. Fig. 15 shows the
positioning o f the hom antenna with respect to the rectenna.
For the LP gain
measurement, the rectenna is held stationary while the hom antenna is rotated at 45°
increments as shown.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
30
Fig. 15. Hom rotation with respect to the rectenna (not to scale).
Eight different hom orientations are used, i.e. 0°, 45°, 90°, 135°, 180°, 225°, 270°, and
315°. Fig. 16 presents the LP rectenna gains versus frequency for different spacings
between the rectenna and its reflecting plane.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
31
45°
1 3 5 °225°
315°
5 .4
5.5
5 .6
6.1
5 .7
5 .8
5 .9
F req u en cy (G H z)
6.2
(a)
11
45°
135°~
225°
31 S ^ -
iO
18 0 °
270°
9
a
7
o
o>
5
4
3
2
1
0
5.4
5.5
5.6
5.7
5.8
5.9
Frequency (GHz)
6.1
6.2
(b)
Fig. 16. Linearly polarized rectenna gains: (a) d = 8mm, (b) d — 9 mm, (c) d = 10 mm,
(d) d = 11 mm. (e) d - 12 mm, (0 d = 13 mm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
32
5.7
5.8
5.9
Frequency (GHz)
(C)
11
10
45°
13 5 ° ’'
225°
315°
90°
180°
270°
9
8
7
m
2.
ffl
6
■a
3
C
O
l
CO
5
4
3
2
1
[■
5.4
5.5
5.6
5.7
5.8
5.9
6.1
Frequency (GHz)
(d)
Fig. 16. Continued.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6.2
33
11
10
90°
180°
270°
9
8
co
®
■
3o
C
0
m1
2
7
6
5
4
3
2
1
5.4
5.5
5.6
5.7
5.8
5.9
6
6.1
6.2
Frequency (GHz)
(e)
11
-
0°
•45°
135° 225°
315°"
90 °
180°
270°
10
9
8
7
m
■o o
O
C
TJ)
5
4
3
2
1
0
5.4
5.5
5.6
5.7
5.8
5.9
Frequency (GHz)
6
6.1
(f)
Fig. 16. Continued.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6.2
34
The symmetry o f the rectenna and hom antenna cause the LP gain curves for 0° and 180°
to lie on top o f one another as seen in Fig. 16. Similarly, the curves for 45°, 90° and
135° correspond to the curves for 225°, 270° and 315°, respectively. As d is increased
from 8 mm to 10 mm the curves converge between 5.6 and 5.9 GHz. As d is increased
past 10 mm. the curv es diverge and the CP performance degrades.
The air gap thickness (c/) separating the rectenna from the reflecting plane greatly
affects the axial ratio as revealed by the measurement data shown in Fig. 17.
9 ,
-----
---------
------
8
7
_ 6
m
I
03
-
03
5
4
< 3
2
1
0
5.4
5.5
5.6
5.7
5.8
5.9
Frequency (GHz)
6
6.1
6.2
Fig. 17. Measured rectenna axial ratio for different reflecting plane spacings (d).
The LP gain curves o f Fig. 16 are used to determine the axial ratio. The center frequency
for the range o f best axial ratios is 5.76 GHz. Moving the reflector 10 mm away from
the rectenna circuit creates an axial ratio better than I dB from 5.62 to 5.89 GHz. This
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
35
correlates to a fractional bandwidth o f 4.7 %. The reflector allows the rectenna to be
tuned for not only the best axial ratio but also maximum gain. This optimal d spacing
for the single element occurs at about 0.17 Aa where Aa is the free-space wavelength.
When d is extended beyond 0.21
the antenna gain drops significantly. The best axial
ratio (.-I/?) o f 0.6 dB at 5.71 GHz is obtained when d = 10 mm. When d < 10 mm for the
0° rectenna orientation, the H-plane LP gain is greater than the E-plane LP gain.
Similarly, when d > 10 mm. the E-plane gain is greater.
Broadside linear gain pattern measurements are taken using a rotating linearly
polarized Narda 642 standard gain hom located a distance away along the normal or raxis o f the rectenna (see Fig. I for coordinates) in order to substantiate the axial ratio.
These measurements for 0°. 45°, 90°. 135°, 180°, 225°. 270°. and 315° hom orientations
are shown in Fig. 18.
10
r
—
-
5.71 GHz
14 dB
11.42 GHz
2 . -10
c -20
O)
I -25
-30
-35
-40
-180 -150 -120
-90
-60
-30
0
30
Angle (degrees)
60
90
120
150
180
Fig. 18. Measured rectenna linear polarized gains at 5.71 GHz for 0°, 45°, 90°, 135°.
180°. 225°. 270°. and 315° hom orientations.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
36
Fig. 18 reveals that the CPS BRF suppresses the 2nd harmonic at 11.42 GHz by
14 dB below the fundamental 5.71 GHz gain. The highest gain at 11.42 GHz occurs 40°
o ff broadside.
Although IE3D predicts the CP frequency as 5.8 GHz., measurement
results reveal that 5.71 GHz is indeed the CP frequency. The rhombic loop antenna
pattern is measured for hom orientations o f 0°, 45°, 90°, 135°, 180°, 225°, 270°, and
315°. The broadside ( 9= 0°) LP gains ( G l p ) and 3 dB beamwidths are listed in Table 3.
Table 3. Linear Polarized Gains for Antenna + CPS BRF + Baiun
0=0°
LP Gain (dB)
LP Beamwidth (°)
0
6.6
48
45
6.1
45
135
6.5
40
90
6.3
40
180
6.7
48
225
6.1
42
270
6.3
40
315
6.4
40
The axial ratio (/I/?) is determined by subtracting the smallest broadside gain from
the largest. From the axial ratio, the gain correction factor (GCF) for scaling LP gains
into CP [15] gains is determined. GCF in dB is defined as follows:
'
GCF = 20 •log
AR
'
1 0 20 +1
AR
V2-1020
(57)
where if AR = 0.6 dB, then GCF = 2.72 dB. If the rhombic loop antenna was exactly
circular polarized, i.e. AR = 0 dB, GCF would equal 3 dB. Using GCF, the adjusted CP
gain is:
G ^ p = G ^p + GCF
(58)
By taking the broadside (0 = 0 ° ) LP gain average and adding GCF, the adjusted CP gain
o f the rectenna + balun is 9.1 dB. If the CPS BRF, balun, and connector losses are de­
embedded, the DRLA can be shown to have a CP gain o f 9.8 dB. This scaling acts as an
approximation for CP gain and should be supported by CP-to-CP antenna measurements.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
37
6) DC-Pass Filter
The DC-pass filter consists o f the 50 VDC C08BLBB1X5UX DC-blocking
capacitor manufactured by Dielectric Labs. The capacitor is used to reflect all o f the
microwave signals generated from the nonlinear action o f the diode from reaching the
load resistor, thus returning the RF energy back to the diode.
The capacitor’s
characteristics across the CPS line are shown in Fig. 19 and listed in Table 4.
0
:
Capacitor
-25
-30
Insertion Loss
Return Loss
7
9
11
13
Frequency (GHz)
15
17
Fig. 19. Measured balun-capacitor-balun S-parameters.
Table 4. Capacitor Performance
Return loss (dB)
Insertion loss (dB)
5.8 GHz
1.96
16.8
11.6 GHz
2.33
23
17.4 GHz
4
21.31
The capacitor blocks 5.8, 11.6 and 17.4 GHz greater than 16.8 dB. This translates to less
than 2 % o f the total RF power leaking to the load.
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38
7) Diode Efficiency' Direct-Measurement
The diode used in the rectenna circuit is the M/A COM flip-chip detector diode
MA4E1317 with negligible parasitics.
The diode converts the incoming 5.8 GHz
microwave energy coming from the CPS BRF into a large DC component and smaller
power levels at each o f the harmonic frequencies.
The diode efficiency direct-
measurement circuit and curves for VD and rjD versus power delivered to the diode (P,i)
for various R l are shown in Fig. 20.
90
■ - r
nD. R =50 a
n0. flL=ioon
nc. R = 1 5 0 0
70. R =200 Q
no. R f Z 50 a
# . . . vn. R =50 a
K - - • Vg. R = 1 00 Cl
m -'-V r,. r l = 150 n
- • v D. R =200 n
••
o
C apat^or ^ 5 mr^
20
5.4
4.8
4.2
o
3.6 05
o
j >o
3
2.4 a.
2
v a- R =250 n
1.8
o
03
T3
O
1.2
Ground
0.6
9.5 mm
0
20
40
60
Diode
80
100
120
Input Power (mW)
0
140
160
180
Fig. 20. Direct-measured diode conversion efficiency and output voltage versus power
delivered to the diode for various load resistances.
After varying the load resistance RL and capacitor to diode /(/c spacing at various incident
powers to the diode, the optimum l,ic distance was found to be 9.5 mm.
voltage increases according to the relationship Vd 'Rl as R t increases.
The diode
The detector
should not be designed to operate at more than 3.5 V since this would exceed VB/2. R l
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
39
between 150 and 250 Q produces the optimum diode efficiency performance. Over 80
% conversion efficiency was achieved with an Rl o f 250 Q.
S) Rectenna Axial Ratio and Efficiency Measurement
C oax - 2 0 dB
Directional >C oupler i-L,
P ow er
M eter
Circularly P olarized
Rectifying
A nten na
t
50 Q
HP 8341 B
S y n th e siz ed
S w eep er
Incident Energy
(not a plane w ave)
4 6 dBm
(40 W)
Amplifier
Path L oss ©
Path L oss ©
C oax - 1 6 dB
Directional
Linearly Polarized
C oupler
Narda 6 4 2
Standard
to © = 4 1 .5 dB
Gain Hom
Gt = 15.1 dB
to © = 0 .8 6 dB
Voltmeter
Fig. 21. Rectenna element or array measurement setup. Both 5.61 GHz path losses are
measured using a network analyzer.
The measurement setup to determine the rectenna and array’s RF-to-DC conversion
efficiency is shown in Fig. 21. An HP 8341B sweeper is used to generate the RF power
which is then amplified using a 40 W amplifier.
This amplified power is then
transmitted by a hom to the rectenna. A power meter is used to monitor the source
power being transmitted. Fig. 22 shows the S-parameters between the points I, 2 and 3
shown in Fig. 21.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
40
* X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Xlt
-10
-20
I -30
=* -35
40 * * *
-45 [
* * AA A^ A h
4
AAAAA
------------------------
-50
5
5.5
6
Frequency (GHz)
6.5
7
Fig. 22. S-parameters between the points 1. 2 and 3 shown in Fig. 21.
The band surrounding 5.8 GHz is well matched. Power flows from the 40 W amplifier
to the hom antenna with less than a dB o f loss. The loss from the amplifier to the power
meter varies from 40 to 45 dB over the frequency range 5 to 7 GHz.
In order to obtain the rectenna's efficiency, linearly polarized energy is transmitted
from a hom antenna to the rectenna located a distance 5 from the transmitting hom. The
rectenna's efficiency is simply the ratio o f the converted DC power to the received RF
power. The rectenna CP efficiency
is defined in terms o f the rectenna’s effective area
■•Ir ’’ as
PDC
rec
47ts~ V
R,
Ptra nGs ^ tra
A n s R eff i
' pol
(59)
where Ptrans and G,rans represent the transmit power and the hom antenna’s gain,
respectively.
VD is the voltage across the rectenna’s load resistor R l- The distance
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
41
between the hom antenna and the rectenna is s, and Lpoi represents the polarization
mismatch between the two. The effective CP area o f each rectenna is defined as
7
(60)
where D„ is the CP directivity or the CP gain at broadside, and k 0 is the free-space
wavelength o f the incoming energy.
The hom antenna and the rectenna have polarization mismatch. Lpoi in (59) represents
the polarization loss factor between the polarization (/*v) o f the incoming linearly
polarized wave emitted by the hom antenna and the polarization (p „) o f the left-hand
circularly polarized antenna or
(61)
This means that the CP rectenna will receive half o f the transmitted energy due to
polarization mismatch.
The single rectenna element efficiency curves are shown in Fig. 23. At 5.71 GHz
the rectenna is circularly polarized with an axial ratio o f around 0.6 dB when d = 10 mm.
For an incident CP power density o f 6.7 m W /cm \ the rectenna achieves a RF-to-DC
conversion efficiency o f 81 % when the load is 150 Q.
The 81 % efficiency is
competitive with the highest recorded linear rectenna efficiencies with the added
advantage o f being circularly polarized. The DC power generated by the rectenna for
this power density is 95 mW. and the voltage appearing across the load is 3.7 V.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
42
'
A ,
X _ . . . ■
=
R, =
RA =
Ra =
Ra =
Ra =
Q1
o
uL
tr
0
1
2
3
i
i
uc>*
0}
'o
S
LU
C
o
(/)
a>3
c
0
O
O
• • • • ^
50 Q, m easu red
100 Q, m ea su red
15 0 Q, m easu red
2 0 0 Q , m easu red
5 0 Q , c a lc u la te d
2 0 0 n , c a lc u la te d
4
5
6
7
8
9
C ircularly P o la r iz e d P o w e r D e n sity (m W /c m 2 )
Fig. 23. Measured single element rectenna efficiency curves at 5.71 GHz and d = 10 mm
for 50 Q incremental loading.
Calculated curves are shown for the 50 and 200 Q
loading.
Fig. 23 also shows calculated efficiency curves for 50 and 200 Q loading. These
curves are generated from the theoretical diode model proposed by Yoo and Chang [38],
The model predicts the efficiency at Rf_ = 50 Q accurately but diverges with increased
loading with an error o f up to 7 % for 200 Q. This difference between the measured and
calculated curves is due to the absence o f harmonic effects in the model. The remixing
o f the energy at the harmonic frequencies by the Schottky diode results in higher RF-toDC conversion efficiencies.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
43
CHAPTER III
CIRCULARLY POLARIZED RECTIFYING ANTENNA ARRAY
A. Array Operation Theory
a adjustment screws t —;
Metal Reflecting Plan
I II—I I I » I I »
(a)
Fig. 24. ia) Array using a honeycomb lattice. The array is etched on 10 mil substrate with a dielectric constant o f
2.33.
(b) Array layout showing both rectenna and array effective areas along with all relevant spacmgs.
The
innermost 9 elements with the dotted unit cell areas represent the 3 x 3 array that rectifies the incident microwave
energy. The remaining elements are present in order to account for the mutual coupling between adjacent rectenna
elements. This allows the performance o f the 3 x 3 array to predict the performance o f larger arrays.
*<r 2002 IEEE. Parts o f this chapter are reprinted, with permission, from B. Strassner and K. Chang, "A Circularly
Polarized Rectifying Antenna Array for Wireless Microwave Power Transmission with over 78% Efficiency." IEEE
\tT T -S Int Microwave Symp. Dig . Seattle. WA. June 2002. pp. 1535-1538.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
44
3 x 3 Array Average Gain Area ( A Getr) = A a b
Rectenna Effective Area (A 9IT) = nr1
Rectenna Unit Cell Area (A Aelfl9 ) = d yd t
A Re" Overlapped Regions
2 r = 56.4 mm
d . = 42.12 mm
1.165
73.69
Schottky
Diode
0.824
0.4
All O lm ansions in mm
Rectenna Array Circuit Layer
R J 3 = R4/3
d mm Air Gap
UVW J
■AAAr
- ^ ♦
Uy/VV
(b)
Fie. 24. Continued.
Many rectenna elements can be cascaded together to form a rectenna array like
the one shown in Fig. 24. Due to mutual coupling between the adjacent rectennas, the
circularly polarized frequency is 5.61 GHz for the array [42] as opposed to 5.71 GHz for
the single rectenna element. This is shown in the following array analysis.
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45
Using a circularly polarized spiral antenna, the CP patterns o f each o f the dual
rhombic loop antenna are shown in Fig. 25.
The fundamental frequency 5.61 GHz
patterns are shown along with the 2nd harmonic 11.22 GHz patterns.
5.61
5.61
11.22
11.22
CD
2,
Gl-fe, x-z
GKfc. y-z
Ghfe. x-z
Ghfe, y-z
plane
planeplane
plane
19 dB
-5
4 ' 10
i- ,5
J 1 -20
-25
-30
-35
^0
-1 8 0
-1 5 0
-1 2 0
-90
-60
-30
0
30
A n g le (d e g r e e s)
60
90
120
150
180
Fig. 25. Fundamental and 2nd harmonic circularly polarized rectenna patterns for d = 8
mm. A microstrip to coplanar stripline balun is used to acquire the patterns.
The filter suppresses the 2nd harmonic to about 19 dB below the peak gain o f 5.61 GHz.
The gain o f 5.61 GHz has a maximum CP gain close to 11 dB at 0°, and the maximum
11.22 GHz gain occurs off-broadside near 40°.
Array spacing is governed both by the DC-pass filter placement and the effective
areas o f each individual rectenna. The capacitors (DC-pass filters) not only optimize DC
conversion but also isolate the array elements. Each capacitor should be placed 8.5 mm
away from the middle o f the nearest antenna and 9.5 mm away from the nearest diode as
indicated in Fig. 24.
These dimensions have been determined from calculated and
measured impedance matching data.
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46
Fig. 26. S-parameters o f the DRLA * CPS BRF - Balun for various capacitor to diode
spacings. The circles correspond to 5.61 GHz impedances.
Proper capacitor placement will enable each rectenna to capture energy at 5.61 GHz with
negligible reactance. Under this state o f zero reactance, the array is perfectly matched.
The capacitor to diode spacing is chosen by measuring the Sn o f Fig. 13 for when there
is no capacitor on the tuning stubs and then when there is as shown in Fig. 26. When the
impedance with and without the capacitor produces the same real impedance at the
desired frequency, the proper spacing is determined.
The second design criteria
concerning array spacing is found by computing the effective area o f each rectenna from
its corresponding measured CP directivity. Given that the DRLA’s measured broadside
CP gain is 11 dB at 5.61 GHz, Equation (60) results in a rectenna effective area o f 25
cm2 that can be approximated as circular in shape or
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47
ARef f = rzr~
where r represents the radius o f the circular area.
(62)
By equating this relationship to
Equation (60), r is calculated to be 28.2 mm. Since the effective area o f each element is
circular, the array layout is chosen to be the honeycomb lattice shown in Fig. 24. Each
array column contains 5 rectennas that are separated by dy o f 42.12 mm. Likewise, the
element columns are separated by dx o f 39 mm. Both dx and dy are made to be less than
2r. These distances ensure that the adjacent rectenna effective areas (Areff) will overlap
with one another. In other words, this 2-D spacing captures all o f the microwave power
incident upon the array’s surface by eliminating undesirable void regions.
The array
elements can also be spaced closer together and achieve the same array RF-to-DC
efficiency performance. This is due to the fact that whether the elements are spaced as
shown in Fig. 24 or moved closer together, the same amount o f RF power gets collected.
The design is optimized by moving the elements as far away from one another as
possible while maintaining effective area coverage over the entire array with the use of
the effective area overlap between adjacent rectennas. Minimizing the void results in
higher overall array efficiencies, while minimizing the overlapped regions results in
fewer necessary elements.
Diodes are placed on the innermost 9 elements o f the 5 x 5 array for RF-to-DC
rectification. The “unactivated” surrounding rectennas are etched in order to account for
mutual coupling effects. This allows the performance o f the 3 x 3 prototype array to
predict the performance o f a larger array. The interior 3 column x 3 row rectenna array
of Fig. 24 has an optimal output load resistance RA o f 150 Q. Since there are 3 seriesconnected columns, each column will have a DC input resistance o f 50 Q. On each
column, there are 3 parallel DC-connected “active” rectennas resulting in each rectenna
seeing a load resistance o f 150 Q. The rectennas on each column each produce DC
currents that are summed at the end o f that column. Likewise, the DC voltages o f each
column are summed resulting in the voltage VA across the load resistor RA.
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48
The array’s efficiency measurement is simply the ratio o f the converted DC
power to the received RF power. The array efficiency is defined in terms o f the array's
effective area
as
4n s 2
_ PDC _
*.4 =
ef f >
rec
P G
A
■”pol
trans trans A
(63)
V, is the voltage across the array’s load resistor RA- In order to obtain the axial ratio and
efficiency o f the array, linearly polarized energy is transmitted from a hom antenna to the
array’s surface as shown in Fig. 21. The transmitting hom and the rectenna array have a
polarization mismatch o f Lp„i = 0.5. Gtrn„s needs to be determined carefully using the
following procedure.
Fig. 27. The left chart represents the Narda 642 standard gain hom 5.61 GHz E-plane
and H-plane patterns and their 2nd order polynomial approximation Gf/0). Gi/0) has
better than 0.2 % accuracy over the interval -10 < 0< 10 degrees. The right contour plot
shows the array illumination when the array is positioned 180 cm from the hom antenna.
The 9 dotted regions in the array layout represent the effective area o f the 3 x 3 array
(147.8 cm2) with an average gain o f 15.077 dB.
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49
A plane wave incident at the surface o f the array is ideal; however this is hard to
manifest given limitations on transmit power especially in the case o f large arrays. This
non-plane wave gain distribution is shown in the contour plot o f Fig. 27. A plane wave
could be realized if the array is moved far away from the transmitting hom. However,
the power received and delivered to the Schottky diode would not be sufficient enough to
drive the diode into its high efficiency range. To accurately find the array’s efficiency,
the average gain over the entire array must be used in place o f G,rans• Small changes in
the horn's gain can result in significant changes in efficiency. The power density at each
point on the array is determined by the corresponding hom gain GtAfx,y,sJ at that point.
Similarly, the average power density is found from the average transmit gain across the
array's surface. This average gain is found using the following theory. The hom co­
polarization patterns for both the E- and H-planes are shown in Fig. 27. A second order
approximation G,/0) for the E- and H-plane gains can be approximated by the following
equation.
G g(0) = -0.01240“ +0.0010 + 15.1,
- 1 0 ° < 0 < \O °
(64)
where 0 is in degrees, and the maximum 5.61 GHz gain o f the hom (15.1 dB) is found at
broadside. Over the interval -10° < 9 < 10°. this approximation has less than 0.2 %
error. This second order polynomial is then expressed as the Fourier cosine series
C g ( 0 ) = Gf c s (0m !a.0 ) = ‘^
^
( Ox 1
l + f an (^max ) cos rt
H=1
v^max .
_
(65)
where the series coefficients a<>and an are given by
max
a o (^ n iax ) ~
an (^m ax ) V^ m a x J
f O0 {6)dO
v ^max j
max
\ G0 (0 ) cos
0
( 66 )
°
0
'
On '
d 0 , rt = 0,1,2,...,
(67)
V^max }
Qmax is the maximum 0 angle described by the Fourier cosine series.
Since the
polynomial series approximation is expressed over the interval -10° < 9 < 10°, 0max =
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50
10°. G,cj0max.6') can now be expressed in terms o f .t and y distances from the array's
center point as
10,
180
arctan
12 +y2
\jx
( 68 )
/T
V
The average gain is found by integrating the gain distribution over both .t and y and
dividing by the total array area. If the total array area for averaging the gain A q ^ is
rectangular and equal to 4ab as seen in Fig. 24, the average gain is
G
avS
’
=
f | G.t, v (x , y , s ) dxdv
4ab I fr - a
(69)
where a and b are the distances in .t and y from the center o f the array to its edges. The
effective array area or A / ,]r is the summation o f the 9 unit cell areas o f each rectenna seen
in Fig. 24. If we assume that A \ ’f = 9cixdx as depicted in Fig. 24 and use G„v? in place o f
G,r„ns. (63) becomes
4/Tj "
V^A
R .
(70)
PtransGavg {a .b ,s)(9 d xd v ) L ^
It is important to not equate A / /jr with 9ARr ff (ARr 'f is given in (62).) since A / /jr is a
physically measurable area. The area computed from 9A Rreff is greater than the 3 x 3
array's physical area due to ARre^ overlap. Using 9:tr2 instead o f 9Jy/v would result in
incorrect low array RF-to-DC efficiencies.
The array's DC output power is measured as a voltage V t across a single load
resistor. This array load resistor is defined by
‘Yr
R A, = R Lr —
N
(71)
where N x is the number o f columns in the array and Ny is the number o f rectennas in each
column. R l is the optimal load resistance for each individual rectenna which has been
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51
shown to be 150 Q.
The diodes are connected in parallel in each column, and the
columns are connected in series.
B. Array Measurements
The array’s efficiency measurement is computed from measured voltage (VA) data
by Equation (70). To obtain accurate measured results, free-space measurements were
done using a N’arda standard gain hom at a distance s o f 50, 100 and 180 cm. Both the
array effective area A / ' f and average gain G„v? over the array’s surface for the 9 element
array are calculated by Equation (69) and presented in Table 5.
Table 5. 3 x 3 Array Average Gain and Effective Area
s
50 cm
100 cm
180 cm
a
63.7 mm
••
**
b
64.5 mm
j
•70
164.3 cm"
**
G«vjr
14.772 dB
15.019 dB
15.077 dB
dx
39 mm
••
••
d
42.12 mm
••
••
A /"
147.8 cm"
*•
The wave incident upon the array better resembles a plane wave as 5 increases.
However, due to limitations on available transmit power, smaller distances between the
hom and the array are necessary to drive the diodes into their maximum efficiency
regions. Correlating the data at the various distances gives an accurate representation of
the array performance over a broad range o f incident power densities.
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52
2 .5
o
<r
"ra
ra
X
<
0 .5
0
5 .4
5 .4 5
5 .5
5 .5 5
5 .6
5 .6 5
5 .7
5 .7 5
5 .8
F re q u en cy (G H z)
Fig. 28. Array axial ratio versus frequency when d = 8 mm. The curve is based on freespace measurement data taken at 10 MHz increments.
Fig. 28 presents the axial ratio o f the array with respect to changing frequency
when s = 180 cm. Rotating linear measurements using a C-band Narda standard gain
hom were carried out to find the array’s circularly polarized operating frequency. The
best axial ratio o f 0.25 dB occurs at 5.61 GHz. To achieve this axial ratio, the distance d
between the reflector and the array substrate is tuned to 8 mm. The mutual coupling
between the array’s rectennas is responsible for shifting the circularly polarized operating
point from 5.71 GHz for the single element to 5.61 GHz.
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53
14
>
<
D
0)
03
R A = 50 ft
RA = 1 0 0 ft
R , = 1 5 0 f t ____
R
0
2
4
6
8
a
10
= 2 0 0 ft
12
14
Circularly P o la rized P o w e r D en sity (m W /cm 2)
Fig. 29. Array output voltage versus circularly polarized power density at 5.61 GHz for
various R ( values.
Fig. 29 shows the array’s output voltage versus circularly polarized power density
for this reflector spacing. Once the array's voltage hit 15.8 V with an array loading of
200 Q. a diode blew on the array. In this case, each column was rectifying 5.3 V DC
when the failure occurred. When operating this array, the column voltage (diode voltage
FD) should be kept under this threshold with some safety margin.
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54
1.4
1.2
1
<D 0.8
3
o
Q- 0.6
3
Q.
3
= so n
r a =100 n
ra
0 .4
= 150 Q
0.2
r a =200
n
0
0
2
4
6
8
10
12
14
Circularly P olarized P o w er D en sity (m W /cm 2)
Fig. 30. Array output power versus circularly polarized power density at 5.61 GHz for
various array load resistances (/? ,).
Fig. 30 shows the array's output power versus circularly polarized power density.
The maximum output power occurs for an array loading o f 150 Q. The maximum output
power measured by the 9 element array for this loading is 1.38 W.
This power
corresponds to an array voltage of 14.4 V or a voltage o f 4.8 V across each diode.
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55
>, OU
o
c<U
o
50
LU
C
o
in
0>)
c
o
r a
O
O
a
o
= 50 n
~
RA =100 Q
R„=150Q
R . = 200 Q
LL.
0
2
4
6
8
10
12
14
Circularly P olarized P o w er D en sity (m W /cm 2)
Fig. 3 1. Array RF-to-DC conversion efficiency versus circularly polarized power density
at 5.61 GHz for various array loading
Fig. 31 shows the array’s RF-to-DC conversion efficiency versus circularly
polarized power density for various array loading. A best efficiency occurs o f 78 %
occurs at an input power density of 7.6 mW/cm" (—125 mW RF incident upon the diode)
for an array loading o f 150 Q. The array’s output voltage at this power density is around
11 V meaning that each diode has 3.66 V across its terminals. This is close to half o f the
diode's breakdown voltage or Fa/2 = 3.5 V which is usually considered a device
rectification safety threshold for extended periods o f operation. At Ffl/2, the conversion
efficiency o f the array is 77.4 %. The array’s DC output power at 7.6 mW/'cm’ is 0.86
W. Table 6 describes the most likely operating point o f the array based on the highest
possible efficiency.
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56
Table 6. 3 x 3 Array Results for Best Operating Conditions
frequency
5.61 GHz
CP P tlens
7.6 mW/cm2
vA
Pa
11 V
0.86 W
Axial Ratio
0.25 dB
Efficiency
78%
To avoid Schottky diode failures on the array, Zener diodes are used to prevent
over-voltages on the CPS lines.
Fig. 32 illustrates the measurement effects o f using
Zener diodes to protect the array’s Schottky diodes.
80
70
5?
^
U
c
ra
= 150 n
W ithout Z e n e r D io d e s
60
Z e n e r C lipping
^ = 150n
Ui
ssA ;
With Z e n e r D io d e s \ /
I35 40
w
g
30
Z
10
Zener Diode
o
o
o 20
Q
o
tr
0
0
2
4
6
8
10
12
14
Circularly P olarized P o w e r D en sity (m W /cm 2)
Fig. 32. Array RF-to-DC conversion efficiency versus circularly polarized power density
(with and without Zener diodes) at 5.61 GHz for RA = 150 Q.
The Zeners used to acquire the measurement curve have breakdown voltages o f 4 V.
These protective diodes severely clamp the array output voltage and subsequently reduce
the RF-to-DC conversion efficiency. This clamping is due to the parasitic resistance that
appears in parallel with the load resistors. To reduce these effects, the Zener must have a
very sharp breakdown or a higher breakdown voltage.
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57
C. Conclusions
A 3 x 3 circularly polarized rectenna array has been developed to rectify RP
energy to DC power with 78 % efficiency at 5.61 GHz. The capacitor blocks the RP
energy by mo e than 17 dB, and the CPS BRP suppresses the 2nd harmonic signal to
around 19 dB below the peak fundamental gain. This results in minimal radiation at the
2nd harmonic frequency. The electromagnetic simulator IE3D models each microwave
circuit section o f the rectenna with reasonable accuracy providing the insight necessary
to facilitate the design. This 9 element array can be expanded to larger arrays in order to
provide an efficient means o f rectifying large amounts o f microwave power incident
upon the array's surface.
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58
CHAPTER IV
RADIO FREQUENCY IDENTIFICATION FOR DRILL PIPE
This chapter describes the RFID tag used for monitoring oil drill pipe. A variety
o f issues including pressure, temperature (see Appendix II), data rate, pipe movement,
read distance and the presence o f mud on the drill pipe are addressed.
A. Operational Theory and Component Design
A block diagram o f the tag is shown in Fig. 33. The tag consists o f both an RF
section and a digital section denoted by DC. The reader interrogates the tag using a
continuous wave o f energy at 5.8 GHz.
The tag then simultaneously returns its ID
modulated on the 5.8 GHz carrier back to the reader.
a 5.8
GH z
a 5.8
GHz + ID
W | »
Circular Patch
Antenna
t”
RF Path
hi —
i»
Capacitor
Schottky
Diode
(Rectifier)
Ground
PIN-Diode (Modulator)
ID Code
Capacitor ✓
YhFig. 33.
1v
Voltage
DC-to-DC
Converter
3.0 V
CLK -
Clock
RFID Tag circuit block diagram. RF and DC represent the microwave and
digital portions, repectively. The voltage VH is the rectified voltage from the Schottky
diode.
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59
I). Tag System Components
The tag’s placement in the tool joint o f the drill pipe and the interior o f the tag
are presented in Fig. 34.
25.4 mm
Teflon
Teflon
Circular patch
antenna
Nylon filled
coaxial lines
Tag steel
housing
3 mm
/ Antenna
4 .7 mm
Nylon
\
— Digital circuit board
Circumscnbed
recess for
o-ring seal
RF circuit —
board
Schottky
diode
LA 1 3 mm
1 0 mm
Pressure Lip (Protects
electronics from
outside p ressures)
diode
RF Board Parameters
V G. Ground
Converter
= 5
DC voltage output
V.c . ID Code input
Coaxial center conductor contact point
Fig. 34. Tag recess and 3-D structure view.
The tag is recessed 19 mm (-0.75 in. ) into the tool joint o f the drill pipe. A 5 mm (-0.25
in.) thick Teflon cover is then placed over the tag in order to protect the tag from the
“down-hole” environment. The Teflon’s inherent slick surface also helps to clear the
drill mud from the surface o f the tag.
The circular patch located behind the Teflon
couples RF power in and out o f the tag. The patch has two ports that are orthogonally
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60
spaced [43] on its surface 4.5 mm away from the patch’s center. The patch is linearly
polarized with one port being H-plane polarized and the other E-plane polarized. These
orthogonal ports are also isolated and thus can perform receive and transmit functions
simultaneously.
The patch is connected to the RP circuitry by two Nylon-filled coaxial lines.
These coaxial lines have a cross-sectional area o f 7.1 mm2. Assuming the 20,000 psi
exterior pressure is uninhibited by the Teflon or the antenna, 220 lbs o f pressure will be
applied to each o f the Nylon coaxial lines.
The Nylon maintains its rigidity at this
pressure so as to not change the electromagnetic properties o f the coaxial lines. The
short lip section between the Nylon coaxial lines and the diodes keeps the pressure on
the tag’s Teflon surface from reaching the RF and digital circuit boards.
After the 5.S GHz energy is collected by the patch antenna, it flows down the
coaxial line leading to the Metellics MSS30-142-E20 Schottky rectifying diode depicted
in Fig. 33 and Fig. 34.
This diode then converts a major portion o f the microwave
energy into a DC power with a voltage VH. The remaining power is distributed at 5.8
GHz and its higher order harmonic frequencies.
This rectification is responsible for
making the tag passive since it generates the DC power that operates all of the "on­
board” electronics.
A DC-to-DC converter is then used to step up the rectified DC
voltage in order to lower the Schottky’s rectification requirement which ultimately
lowers the transmit power necessary to tum-on the tag’s electronics. The converter used
is a MC33466H-30KT1 manufactured by Motorola. It uses a 1 V input to produce a 3 V
output. The converter’s 3 V output drives both the 16 MHz clock oscillator and the
Motorola MC68HC908JK3-CDVV microcontroller. The microcontroller produces a 64bit ID unique to the tag and is programmed to repeat the code until it shuts down due to a
lack o f tum-on voltage. This repeating 64-bit ID sequence o f l ’s (3 V) and 0’s (0 V) is
used to modulate the 5.8 GHz energy remaining from the Schottky diode mixing process.
This 5.8 GHz energy that remained in the Shottky diode travels through the low loss
capacitor C/ and couples to a MA/COM 4P804-129 PIN diode. When V[D = 3 V, this
PIN diode shorts and allows the 5.8 GHz energy to pass through it. Conversely, in the
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61
case where F/D = 0 V, the PIN open-circuits to reflect the 5.8 GHz energy back to the
Schottky diode where it remixes and creates more DC power.
Thus the PIN diode
functions as a switch [44] to modulate the ED code on the 5.8 GHz carrier frequency.
The modulated signal then travels through another low-loss capacitor C? to reach the
connection to the coaxial line. The coaxial line is connected to the patch antenna where
it radiates back to the reader. Both low-loss capacitors are required to separate the three
voltage levels, i.e. ground, high, and the ID code. At the locations o f these three voltage
levels are three /i/4 wavelength stubs that are used as RF chokes to isolate the microwave
energy from the digital circuitry. The 64-bit ID sequence has 2M or 1.8 x I0 |l) different
code combinations with which to ID the drill pipe. Each year approximately 400.000
new drill pipes are manufactured. Thus there exist enough unique code sequences to
identify all newly manufactured drill pipes for the foreseeable future.
Drill
P ip e
CO
(0.0.0)
u.
H o rn
Tag
( 0 . 0 — .)
u, = x ,.r+ v, v
Fig. 35. 3-D spatial orientation o f the tag with respect to the reader's horn antenna. The horn antenna is
fixed at the point (.r-.0.0) and the tag rotates about and moves vertically along the z axis. The vector t(l is
normal to the tag's surface and represents the tag's broadside orientation.
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62
2). Tag/Reader Link
In order to determine the transmit power necessary to operate the tag, a
mathematical analysis of the tagreader link is formulated. Fig. 35 presents a 3-D view
o f the tag's orientation with respect to the reader’s horn antenna. The reader’s hom
antenna is located along the.t axis. The tag has been placed along the f axis. Assuming
X2 »
d l l where the diameter o f the drill pipe is represented by d, and the horizontal
distance between the hom antenna and the tag located on the drill pipe is .t_% the ratio of
the power received by the tag to the power transmitted by the reader is given by the Friis
transmission equation [45] as
V
, 4/T |ii: _
P;
(72)
Gt { d ,^ ) G r {er4 r )\p, p r
where P r and P, are the received and transmitted power, respectively. The length |ii:
represents the distance between the hom and the tag’s circular patch antenna. The freespace wavelength
a„ of
the 5.8 GHz energy is 5.17 cm. The gains o f the reader and tag
antennas for an arbitrary orientation are represented b y a n d
Gr {6r.<f>r ) where
0t, 0r, <pr and (pr are in degrees. Fig. 35 shows that 9t = 0r. The quantity P, Pr
stands
for the polarization mismatch and is assumed to be unity since both antennas are linearly
polarized and well aligned. The tag rotates about the f axis at an angular speed co and
moves vertically along the f axis at a vertical speed v. Contrarily. the reader’s hom
antenna is held fixed so that it always faces the i axis.
Thus, the hom has no <p
dependence only 0 dependence, and (72) becomes
P
P
Gr{Or )Gr {Gr.(Pr )
4/T^.r,' - r,'
where the distance z t represents the tag’s vertical displacement from the origin.
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(73)
63
From Fig. 35 it can be shown that the angle £ between the line-of-sight vector z7,
connecting the tag and reader and the normal vector z7, o f the tag’s antenna is found
from the dot product between the two vectors as
\
/
/
IK
i i
■> /
W - V + T . ' V-r:'
•z7;
z - cos 1 1 . 1- 1 = cos 1
It can also be shown that tan0r =
v , /.rt
(74)
)
and tan#, = z j .t , . Using these two equations
and the trigonometric identity I -r tan: a = sec2 a - l/cos2 a . Equation (74) reduces to
^ = cos
= cos 1( cos (f>r cos 0r )
(75)
sj.r," * V,2 tan' <pr yjx2~ ~ r,2 tan' 0r
The gain o f the tag Gr (&r.tpr ) can now be expressed in terms o f the single variable i as
Gr ( i ) . Therefore, given z/, .r_% 0r and <pr, one can calculate Pr in terms o f P„
3) Data Rate
The data rate is chosen based on the interrogation time experienced by the tag.
This interrogation time has been chosen to be the time in which the tag located at point
(0.0^/) appears within the 3-dB beam width o f the reader’s hom antenna located at
(.t_\0.0).
To complete this transmit/receive link, a clock speed for the data must be
chosen based upon the interrogation time which is a function o f both the rotational
angular velocity co and the ascent/descent velocity v. Two cases for determining the
interrogation time are analyzed here. The first case looks solely at the pipe’s vertical
movement in the x - z
plane when
= 0°. and the second looks at the rotational
movement in the x —y plane w hen &r = 0°. The separation o f the vertical and rotational
components allows for an easy determination o f the approximate digital clocking
necessary to communicate multiple data reads between the reader and the tag as the tag
passes the hom antenna.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
64
For the first case, the length between the tag and the reader’s transmit hom is x 2.
The time that elapses during the tag’s vertical movement from - r , f to c,f in terms of
the angle 0r is
= —L = — tan (0r )
v
(76)
v
where v represents the vertical speed o f the tag.
For the second case, the angular rotational velocity co o f the drill pipe is taken
into account. The angle between the normal vectors o f both the tag’s circular patch and
the reader hom antenna is represented by
The time that elapses during the tag’s
rotation for which its normal vector sweeps from the point (.r/,-v/,0) to the point (.t/,y/,0)
is
r, ==£-
(77)
co
For determining the interrogation time of the tag. the 40° 3-dB E- and H-plane beam
widths o f the reader's hom antenna are inputted into (76) and (77) as 20r and 2$.,
respectively. The horn’s 3 dB beam widths are used since they are narrower than the 75°
orthogonal beam widths o f the tag's patch antenna.
For most drilling operations, the
distance x 2 between the tag and the reader’s hom antenna is 1.0 ft (30.5 cm). For this
distance and given that the vertical drill pipe velocity v = 8.8 ft/s = 268.2 cm/s and the
angular rotational velocity co = 350 rev/min = 5.833 rev/s = 36.652 rad/s. t/ = 82.8 ms
and (2 = 19.1 ms.
The smaller time t2 determines the number o f reads during
interrogation depending upon the number of bits
in each read. Since t2 is always the
shorter time for the given co and v. the number o f reads nr is represented by
n = lc u r ±
rh
(78)
where J'clk represents the frequency o f the clock used for the tag’s identification
sequence, and
is the number o f bits in the tag’s ID. The crystal oscillator denoted as
CLK in Fig. 34 operates at 16 MHz. However, the microcontroller slows this down to
33.3 kHz in order to view the sequence on an oscilloscope. This 33.3 kHz clock rate is
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
65
the data rate /
clk-
If the drill pipe uses 64-bit identification and r> = 19.1 ms. the number
of reads nr = 10. More reads means better data correction for averaging out erroneous
bits.
The frequency 5.8 GHz is chosen primarily on the size limitation o f the antenna.
However, this frequency also provides enough carrier oscillations in each information bit
to provide detectable information at the reader. The period o f the clock is Tclk = I I f clk
= 30 ps.
Similarly, the period o f the carrier frequency 5.8 GHz is Trf = 172.4 ps.
Therefore the number o f carrier oscillations n0 in a single clock cycle is
n = ^~
°
or 174 thousand cycles.
transmit correctly.
(79)
T
1 RF
If Trf is on the order o f or less than Tclk the data will not
If more reads are necessary for better error correction, the clock
frequency can be increased. The CW energy at 5.8 GHz provides plenty of oscillations
on the 33.3 kHz ID to produce a clean distinguishable modulated ID sequence. Thus the
tag's vertical and rotational movements do not create any data rate complications in
providing a link between the reader and tag at 5.8 GHz.
B. Digital Subsection
I ) Digital Components
The components used for producing the 64-bit ID code are shown in Fig. 36.
These components include the DC-to-DC coverter, 16 MHz clock (CLK) and the
microcontroller unit (MCU).
DC-to-DC
Converter
Fig. 36.
ID
CLK
MCU
3V
Main blocks o f the digital subsection: DC-to-DC converter, clock and the
microcontroller.
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66
The DC voltage level produced from the Schottky diode must be at least 1 V in order for
the electronics to operate properly. The first digital component used is the DC-to-DC
converter. The DC-to-DC converter schematic is shown in Fig. 37.
MBRD520LT1
i
M
1
MC33466H-30KT1
120 uH
vo
O
X
T
22 pF
Fig. 37. DC-to-DC converter schematic.
The two 22 uF capacitors remove noise from the system in order to provide a steady
voltage level. The voltage Vfl is the IV input and Va is the 3V output. This converter
produces the voltage ouput listed in Table 7.
Table 7. DC-to-DC Converter Output
Vh
Vo
VH < IV
iv < v„<3v
VH> 3V
Vh
3V
Vh
As long as the detector diode provides between 1 and 3 V. the converter will provide a
constant 3 V output.
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67
The second component o f the digital section is the clock. The clock uses a 3 V
input to produce a 16 MHz clock. The clock uses CMOS technology for low voltage
operation and fast switching time.
The third component o f the digital circuit is a Motorola MC68HC908JK.3
microcontroller. A microcontroller is a microprocessor with internal RAM and ROM.
This particular microcontroller offers power-on-reset eliminating additional components,
low voltage operation at 3V, a small package o f 20 pins, and 8-bit Flash memory. This
microcontroller also has an internal clock; however. Motorolla recommends that an
external clock be used in tandem with the microcontroller in order to achieve greater
stability. The following section addresses the programming o f the microcontroller.
2) Microcontroller Programming
The MCU does not provide an instruction for allowing serial output.
Serial
output is achieved by setting a single output pin either high or low. corresponding to the
value o f each bit o f the ID code.
Each bit is tested, and a variable is needed to track the bit position under
examination. A 64-bit number equates to 8-bytes. The MCU is an 8-bit microcontroller
that operates on bytes o f information, and a second variable is needed to track which byte
is under examination. Somewhere in the memory, the ID code is hard-coded so that it is
not lost when there is no power is applied to the system.
represented with two bytes and holds one byte o f data.
Each memory location is
Another variable is used to
indicate which memory position (of the ID code) is under examination. The byte o f data
under examination needs to be held in a fourth variable. When all bits o f the ID code
have been outputted, a short string o f alternating “ l ”s and "0”s is outputted to indicate
that the next bits will be from the beginning o f the ID code again.
The MCU has two useful registers, instructions that operate these registers and
instructions that transfer data between the registers and memory locations. One register
is the 8-bit Accumulator (A) and the other is the 16-bit Index Register (H:X), with H and
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68
X registers representing the upper and lower bytes, respectively.
Since the memory
locations or addresses are 16-bits, they are kept in the Index Register.
The 8-bit
accumulator corresponds to the byte o f data under examination. Only RAM locations
remain which store the variables that track the ID code’s bit and byte positions.
Given the MCU’s inherent instructions, the software tests each bit o f the ID code
and then repeats the following process:
1)
Initialize variables with the ID code’s location and length.
2)
Move the left-most byte o f the ID code into the Accumulator.
3)
Test each bit o f the Accumulator’s byte by
a. Test the left-most bit o f the Accumulator.
b. Output a zero or a one depending upon the testing result.
c. Check if the bit-position variable indicates the entire ID code has been
tested.
If additional bits need to be tested then test the bit
immediately to the right o f the one previously tested and go to step
3b: otherwise go to step 4.
4)
Check if the bvte-position variable indicates that the entire byte has been
tested. If additional bytes need to be tested then load the Accumulator
with the byte immediately to the right o f the one previously moved into
the Accumulator and go to step 3; otherwise, oscillate the output pin a
few times to indicate the start/end o f the ID code and go to step 1.
The flowchart o f Fig. 38 depicts these four steps and the way each relates to one another.
R eproduced with perm ission o f the copyright owner. F urther reproduction prohibited w itho ut perm ission.
69
X = F8
BY = BY - 1
BY = 8
A = the contents o f
memorv location FBOO + X
BI = 8
Move the left-most bit from A to the “Carry
bit o f the Status Register and shift the
remaining bits o f A to the left bv one.
------------ ► Output = 1
V
Output = 0
Does
Carrv” = 0?
Output = 0
u
Output
A =A- 1
N o ^
Does
BI = BI - 1
Fig. 38. Flowchart depicting the basic microcontroller instructions.
Now these steps are coded using the Assembly directives and instructions listed in
Appendix HI.
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70
3) Hardware Implementation
MC68HC908JK3-CDW
MBRD520LT1
IRQI
VSS
OSCI
MC33466H-30KTI
CLK
RST
PTD4
OSC1
PTD5
O SCIPTA6
PTD2
Z H t-C VDD
PTD3
1 (Z PTB?
PTBO
PTB6
PTB1
PTB5
PTB 2
O PTD7
ID
■Cl PTD6
PTB4
(a)
0.67"
ID
MCU
DC-to-DC Converter
(b)
Fig. 39. (a) Hardware connections for the DC-to-DC converter, CLK and MCU. (b)
Etched PCB with components. Circles represent vias.
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71
The hardware connections and subsequent etched PCB are shown in Fig. 39.
The
capacitors Cj and O are both 22pF. The inductor L/ is 120 pH. The circles represent
vias that connect the two layers. The cost o f each tag’s electronics is around S8.50 with
the breakdown listed in Table 8.
Table 8. Cost Breakdown o f Tag’s Electronics
2
1
I
I
I
I
22 pF Capacitor
120 pH Inductor
Schottky Diode
DC-to-DC Converter
16 MHz Oscillator
Microcontroller
3.5 mm x 2.8 mm x 1.9 mm
4.6 mm x 2.5 mm x 2.2 mm
MBR0520LT1
MC33466H-30KTI
7.0 mm x 5.0 mm x 1.4 mm
MC68HC908JK3-CDW
S0.82
S0.43
SO. 11
S0.59
S4.73
S I.82
This concludes the description of the digital circuit o f the RFID tag. The cost effective
combination o f the DC-to-DC converter, CLK. and MCU enable the tag to produce a
repeating 64-bit ID code with which to identify itself.
4) Digital ID Code
The microcontroller, which is powered by a 3 V input, outputs the 64-bit code
shown in Fig. 40. This code is used to bias the PIN diode in order to modulate the 5.8
GHz carrier. The ID code is 6A7B49D20135FEC8,6 = 0110 1010 0111 1011 0100 1001
1101 0010 0000 0001 0011 0101 1111 1110 1100 10002. This 64-bit code varies from 0
(off-state) to 3 V (on-state). Each bit takes 30.5 us to process resulting in the 64-bit
sequence taking 1.952 ms.
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72
U /2 I1 /0 0 02:15:17 PM
200.0u«7<frr
2fcptr'l.
f
•rv i
T
CHANl
2.000 V /div
Raikai
C l:
f ~
I ; !;
.............
’.'S f c V .
ll
"•'T'
" '
^
CHAN1
•#i—
3.000 V
XtfcBO.OOOut
CHAN1
^^Y S flo .O O O V
') S |3 1 0 .0 0 0 u i
rr.r * - * .'-.--
'
A 1-3.000 V
......
"Y2
..
’■£'
. . ' ' ’5
‘
-f •'
*-
A |3fl.000u>
(a)
(b)
Fig. 40. (a) Microcontroller output for biasing the PIN diode, (b) Microcontroller output
for the three 3 (is oscillations, (c) Microcontroller output when the 0.9V < VH< IV.
R eproduced w ith perm ission o f the copyright owner. Further reproduction prohibited w itho ut perm ission.
rtgn/iwtgaaatm:
1""~1
? r*
i 1!
>X2
M *kw
OIAN1
IOWM _____
I CHANI
T j
Y t |? 438 V
X t j-8 9 5 OOOus
"21 Y2 10.000 V
xzf-ash an ou s
A [-2.438 V
A |3Q QOOui
(C)
Fig. 40. Continued.
Fig. 40 shows code slewing which occurs in the region where the tag is barely turned on,
i.e. 0.9 < Vh < 1V. It is important to provide enough rectified voltage to avoid unwanted
glitches in the code.
C. Measured Data fo r R F Subsection
I ) Circular Patch Antenna
The return loss and port isolation for the circular patch antenna with no recess
and no Teflon cover is shown in Fig. 41. The ports are orthogonally spaced 4.5 mm
from the center o f the patch, and the patch’s diameter is 17.5 mm. Port 1 is the input
port connected to the Schottky diode. Port 2 is the output port connected to the PIN
modulator. With no Teflon cover, the patch has a resonant frequency o f 6.04 GHz. The
orthogonal ports are isolated by more than 20 dB (S 21 in Fig. 41) from 5.6 to 6.4 GHz.
R eproduced w ith perm ission o f the copyright owner. Further reproduction prohibited w itho ut perm ission.
74
This isolation makes it possible for the tag to receive E-plane and transmit H-plane or
vice-versa with minimal crosstalk between the ports.
17.5 mm
0
6.4
Frequency (GHz)
Fig. 41. Circular patch dimensions and S-parameters with no recess or Teflon cover.
The circular patch is etched on Duroid 5870 with sr = 2.33 and a thickness o f 1.524 mm.
As the Teflon cover thickness is increased, the tag’s center resonant frequency
decreases as shown in Fig. 42.
When the drilling pipe is manufactured, the tag is
recessed and covered with a 5 mm Teflon cover. The resonant frequency for the 5 mm
cover is 5.74 GHz. As the pipe is used and worn down, its diameter d decreases. This
causes the Teflon thickness t to also decrease from the initial 5 mm to 3 mm. When the
Teflon thickness reaches 3 mm, the pipe must be replaced due to its decrease in diameter
in order to avoid failure down-hole. At this point the resonant frequency has shifted up
to 5.82 GHz.
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75
n
5.9
Old Pipe
3 5.8
LL.
New Pipe
Teflon
Steel
Anten na
5.6
0
2
1
4
3
5
7
6
Teflon Thickness (mm)
Fig. 42. Tag resonant frequency versus Teflon thickness t.
—
V -
8 dB
15.3 dB
E-plane
co-pol
E -plane
H-plane
"c o -p o r
-
H -planeN ^
co-pol
'
a
05
-24
*30
180-150-120 -90 -60 -30
0
30
60
90
120 t50 180
180 *150 *120 *90 -60
Angle (degrees)
30
0
30
60
90
120 150 180
Angle (degrees)
Fig. 43. The left chart shows the E- and H-plane patterns for the standard gain hom
antenna with polynomial approximation *#(#) in dB. This approximation is good for 30°<6?f<30°. The right chart shows the E- and H-plane patterns for the tag’s circular
patch antenna with polynomial approximation ^ ( c ) in dB. This approximation is good
for -90°< c< 90°. All angles are measured o ff broadside.
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76
The E- and H-plane patterns for both the hom and the patch antenna are shown in
Fig. 43. The hom and patch have 5.8 GHz broadside gains o f 15.3 and 8 dB in E- and Hplane, repectively. Their polynomial gain approximations *F^0t) and
shown in Fig.
43 are used to compute the hom and patch gains at any angles as
(Mrt I
; -O OI2 4 rt- .1) 00119 >15 3 !
10
G ,( 0 ,) = IO 10 =10
(80)
and
v ( .-)
-O O O IS j- - 0 0 0 3 2 ; -8 I
Gr (<f) = 10 10 = 10
(81)
Note that 9, = 9r. By inserting Equations (80) and (81) into Equation (73), it is possible
to predict the power received by the tag depending on its orientation with respect to the
reader.
The attenuation through a material is defined in Np/m as [45]
a
=
coyfjis
I-
where co is the frequency in rad/s, fi = 4tt
x
a
v (D£ j
-I
(82)
Jj
10' H/m. e= srSo where er = 2 for Teflon and
So - 8.854 x 1 0 12 F/m. and <r = 1 0 16 S/m for Teflon (insulator).
expansion on (82) and assuming that Teflon is a good dielectric, i.e.
Using binomial
(OS
«l.
(82)
looses its frequency dependence and becomes
“ =£ J -
(83)
which for Teflon results in a = 1.33 x I O'14 Np/m = 1.16 x I O' 1' dB/m. Thus the
electromagnetic energy incident upon the Teflon travels through the Teflon cover to the
patch antenna with negligible loss.
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77
2) PIN Diode Modulation Circuit Performance
The S-parameters for the PIN diode modulation circuit are shown in Fig. 44. The
circuit consists o f three
stubs at 5.8 GHz which act as RP chokes to isolate the RF
energy from the electronics. Two 0603 3A102K dc-blocking capacitors manufactured by
AVX Corporation, each with a value o f 2400 pF, are also present in the microwave
circuit in order to separate the three distinct voltage levels ( V{D, VH and VG). These
capacitors provide a low loss RF path in order to propagate the 5.8 GHz energy with
little attenuation. When F/o - Vc, = 0 V. the PIN diode has zero bias and is therefore in
its o ff state reflecting the power incident upon it. When V/D- Vc, = 2>V, the PIN is in its
on state and passes the 5.8 GHz energy through its terminals. When the PIN is off, the
measured insertion loss (isolation) for the RF circuit is 23 dB at 5.8 GHz. When the PIN
is on. the insertion loss is 1.5 dB. The RF circuit has a return loss better than 10 dB from
5 to 6.5 GHz when the PIN is on.
Port I
10
Port 2
*
-20
PIN D iode
5.25
6
6.25
Frequency (GHz)
6.5
675
Fig. 44. Measured PIN diode modulation for both on- and off-states o f the diode. For
the on-state, V{D - VG = 3 V. Similarly, the off-state occurs when V[D - VG = 0 V. The
RF circuit is etched on Duroid 6010.8 with er = 10.8 and a thickness o f 0.635 mm.
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78
3) Tag Free-Space Performance
For the free-space test o f the tag illustrated in Fig. 45, a signal generator is used
to provide microwave energy at various frequencies. This microwave energy is then fed
to a 7 W amplifier in order to provide the necessary RP power for conversion to DC
power to operate the tag’s electronics. A hom then transmits the amplified signal to the
tag which is recessed into a cross-sectional slice o f drill pipe. The tag’s return signal is
received by another hom rotated 90° with respect to the transmitting hom.
This
incoming signal is then detected by the reader with the use o f a Schottky detector diode
and displayed on an oscilloscope.
O scilloscope
D etec to r D io d e
,R x 1
Pow er
M eter
HP 83 4 1 B
S y n th e s iz e d
S w eep er
5 .8 G H z P a s s iv e
Linearly P o la rized
R adio F re q u en cy
Identification T ag
(Embedded m a dnll pipe)
□
© —
1 7 7 ,0 0 0 R F c y c le s
p er c lo c k p eriod
—
3 8 dB m
(7 W )
A m plifier
Q
c
C o a x - 16 dB
D irectional
C ou p ler
Linearly P o la rized N a rd a 6 4 2
S tan d ard G ain H orn s G, = 1 5 .3 dB
(H/E-plane transmit. E/H-piane receve)
Fig. 45. RPID measurement setup. When the tag is oriented to receive energy from the
hom in the H-plane, the receive hom should be E-plane oriented and vise-versa.
The system was successfully demonstrated in the laboratory for a distance of.v_> =
30.5 cm and a maximum transmit power o f 7 W. The received demodulated code for
broadside interrogation, i.e. Qr = 0°.
= 0° and consequently c = 0°, is shown in Fig. 46.
A detector diode located on the receiving hom recovers the 64-bit code. The code has a
400 mV difference between its high and low levels. This difference results in the code
being easily interpreted at the reader.
The recovered code also matches the
microcontroller’s PIN diode biasing code shown in
Fig. indicating successful
backscatter.
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Fig. 46. Demodulated received signal. Vertical scale: 100 mV/div. Horizontal scale:
200 (is/div.
Fig. 47 presents the rectified voltage Vh versus frequency for different linearly
polarized power densities incident upon the tag’s 5 mm thick Teflon surface when the
distance .r? = 30.5 cm.
From Fig. 42, the 5 mm Teflon thickness will result in the
resonant frequency 5.74 GHz. As expected, this is close to the center frequency o f Fig.
47 as indicated by the vertical line.
These curves are measured for broadside
interrogation, i.e. 0r = 0°, $- = 0° and consequently c = 0°. By applying these angles to
(75) and inserting them into (73), the ratio o f received to transmitted power becomes
(84)
The shaded area o f Fig. 47 reveals the voltage region Vh > IV required for the tag’s
electronics to produce the 64-bit identification code.
To turn on the tag at 5.8 GHz, a
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80
linearly polarized power density o f about 13.5 mW/cm2 is needed. The hom needs to
transmit 4.6 W to achieve this power density when .r> = 1 ft = 30.5 cm. Therefore, (84)
reveals that the received power (Pr) or the 5.8 GHz energy incident upon the Schottky
diode needed to cause Vh to equal 1 V is approximately 170 mW.
0.8
0 .7
New Pipe
0.6
5 .4
5 .5
5 .6
5 .7
5.8
5 .9
6
6.1
F re q u en cy (GHz)
Fig. 47. Measured rectified voltage Vf! versus frequency for different linearly polarized
power densities incident upon the tag’s Teflon surface. The Teflon thickness t - 5 mm
which corresponds to a new drill pipe. The shaded area reveals the voltage region ( Vff >
IV) for when the tag’s electronics are producing the 64-bit identification code. These
curves are generated for broadside interrogation, i.e. Qr = 0°,
= 0° and f = 0°.
Fig. 47 also reveals that the tag has broadband performance due to tag’s recessed
position in the drill pipe and broadband matching caused by the diode and capacitor
placements. For an incident linearly polarized power density o f 20 mW/cm2, the tag
operates from 5.45 to 6 GHz. This broadband performance is very important since mud
films o f varying thicknesses can cover the Teflon and shift the tag’s resonant center
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81
frequency. With the additional bandwidth, the reader/tag link can be established at 5.8
GHz even with the thin mud film variations.
45
70 W
80 W
30-
6.8 W
64 W
60 W
56 W
52 W
48 W
46W
o>
54 W
58 W
62 W
66 W
-3090W
too w
tt 0 w
-45
-1 5
-10
12.0 W
5
0
Qr (d e g re e s )
5
10
15
Fig. 48. Contour plot showing the transmit power needed to provide the 170 mW o f 5.8
GHz energy to the Schottky rectifying diode for x2 = 1.0 ft s 30.5 cm. The angle
varies from -45° to 45°. and the angle 9r ranges from -15° to 15°.
The contour plot o f Fig. 48 predicts the transmit powers needed, based on (73)
and (75), to operate the tag for various 0r‘s and #.‘s when x2 = 30.5 cm. At this distance.
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82
x: »
d!2, since most offshore drill pipe is 5 in. in diameter.
For 7 W o f available
transmit power, -10.5° < 0r < 10.5° and -30° < fa < 30°. W hen.o = 30.5 cm, Qr = 10°, fa
= 30° and consequently q = 31.5°, the horn must transmit 9.3 W to get the 170 mVV to
the Schottky diode.
This indicates that large transmit powers are necessary in
maintaining the reader/tag link when the pipe is moving. This also justifies a need for
low-power electronics [46], [47] and multiple reader antennas to interrogate at different
positions around the pipe in order to reduce the transmit power levels.
While high
powers are readily available on the drilling platforms, being exposed to certain levels of
it are a concern
(See Appendix V).
Fortunately, personnel are normally at some
distance away from the location o f the reader’s antenna, and a thick metal barrier will
also separate the two.
D. Conclusions
A new tag has been designed which has the potential o f greatly reducing the
operating costs o f oil drilling and exploration. The passive tag is designed to operate
without a battery and to withstand large pressures normal to its surface. The operational
frequency 5.8 GHz allows for small size and a very high data rate to communicate
multiple reads between the tag and reader.
The tag’s integration results in a wider
bandwidth than a conventional patch antenna making it possible for the tag to operate
when thin mud films o f various thicknesses are present on the tag’s Teflon surface.
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83
CHAPTER V
MICROSTRIP DIPLEXERS
This Chapter looks at the simulated versus measured results for various diplexer
structures. Simple two band diplexers are presented as well as multiple band diplexers.
All o f the diplexers presented are three port devices to be used behind antennas for
transceiver applications.
A. What is a Diplexer?
A diplexer is a three terminal device that allows a designer to separate various
powers at different frequencies. The diplexers discussed are passive and use a variety o f
different filter geometries to achieve frequency separation. Diplexers are very important
in separating receive and transmit frequencies behind multiple frequency or large
Diplexer (3 - port)
P ort 2
P ort 3
f,
Fig. 49. Diplexer Schematic.
*C 2001 IEEE. Parts o f this chapter are reprinted, with permission, from B. Strassner and fC. Chang. "Wide-Band
Low-Loss
High-Isoiation
Microstrip
Periodic-Stub
Diplexer
for
Multiple-Frequency
Applications."
Transactions on Microwave Theory and Techniques, vol. 49. pp. 1818-1920. October 2001.
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IEEE
84
bandwidth antennas.
When a diplexer separates more bands requiring more ports
(channels), the structure is known as a multiplexer.
Fig. 49 shows a diplexer block
diagram.
Two types o f diplexers are analyzed here.
The first is a two channel / two
frequency diplexer. This diplexer separates two frequencies to two different ports. The
second diplexer type is a two channel / four frequency diplexer. These diplexers split
four frequencies to two ports. Two frequencies go to one port and the other two go to
another port. For the diplexer to operate effectively, ports 2 and 3 should be isolated so
that S:j and Sjj < -30 dB.
B. Two Channel / Two Frequency' Band stop Diplexer
Port 2
0.54 mm
Fig. 50. Rejection stub diplexer for 5.8 and 11.6 GHz.
The diplexer in Fig. 50 has both 5.8 and 11.6 GHz incident at port I. It then splits the
two frequencies so that 5.8 GHz comes out o f port 2 and 11.6 GHz comes out o f port 3.
The two 11.6 GHz rejection stubs near port 2 are designed to be about a quarter
wavelength for 11.6 GHz as is the spacing between the stubs and incoming center feed.
Similarly, the two 5.8 GHz rejection stubs near port 3 are approximately a quarter
wavelength in length and spacing for 5.8 GHz.
The measured S n curve for the Fig. 50 diplexer is shown in Fig. 51.
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85
0
-10
-15
-20
-25
-30
5
6
7
8
9
10
Frequency (GHz)
11
12
13
Fig. 5 1. Measured rejection stub diplexer return loss at port 1.
The S21 and S31 curves are shown in Fig. 52.
Insertion Loss (dB)
0
-10
-15
-20
-25
-30
S31
S21
-40
6
7
8
9
10
Frequency (GHz)
11
12
Fig. 52. Measured rejection stub diplexer insertion loss.
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13
86
The tabulated results for both 5.8 and 11.6 GHz are shown in Table 9.
Table 9. Rejection-Stub Diplexer Performance
S 1 1 measured (dB)
S 2 1 measured (dB)
S31 measured (dB)
5.8 GHz
-18.6
-0.65
-38.4
11.6 GHz
-16.1
-28.2
-1.03
The pass band regions (S21 and S 12 for 5.8 GHz and S31 and S 13 for 11.6 GHz) are low
loss and the isolation is around 30 dB for both frequencies.
This type o f rejection
diplexer has bandwidths greater than a GHz at both 5.8 and 11.6 GHz. The diplexer has
reasonably good isolation and very simple fabrication.
C. Two Channel / Four Frequency Parallel-Coupled Bandpass Diplexer
Fig. 53 shows a two channel/ four frequency diplexer. The diplexer uses two
parallel-coupled line band pass filters to form pass bands at 9.4. 11.5. 18, and 21.7 GHz.
Port 2
0.54 mm
0 .5 mm
1.42 mm
1.42 mm
0.5 m m
Fig. 53. Parallel coupled line bandpass filter dual frequency diplexer for 9.4, 11.5, 18,
and 21.7 GHz.
9.4 and 18 GHz flow between ports I and 2 while 11.5 and 21.7 GHz go between ports I
and 3. This diplexer uses two parallel-coupled line band pass filters. The filters are
designed for 9.4 and 11.5 GHz. The filter accommodates both 18 and 21.7 GHz with its
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87
harmonic repetition. Another advantage o f this geometry is that all three ports are DC
isolated from one another. This could be important in applications where amplifiers are
cascaded with the diplexers and drain and gate biases must be separated.
The return loss at port 1 is shown in Fig. 54.
0
-10
15
•j -20
as
-25
-30
8
10
12
14
16
18
Frequency (GHz)
20
Fig. 54. Parallel-coupled line band pass filter dual frequency diplexer return loss.
The insertion losses are shown in Fig. 55.
sr -io
2 -20
10
12
14
16
18
20
Frequency (GHz)
Fig. 55. Parallel-coupled line band pass filter dual frequency diplexer insertion loss.
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88
The data for the pass band frequencies are listed in Table 10.
Table 10. Parallel-Coupled Line Dual-Frequency Diplexer Performance
SI 1 measured (dB)
S21 measured (dB)
S31 measured (dB)
9.4 GHz
-33.8
-2.3
-29
ll.5 G H z
-24.3
-45
-2
18 GHz
-12.6
-2.8
-27.5
21.7 GHz
-20.2
-20.6
-7.4
The harmonic to fundamental frequency ratio for the parallel-coupled line band pass
filters used is 1.9. Since the pass band o f this type o f filter is narrow, it is very difficult
to design for the desired frequencies. The pass band at 21.7 GHz has high loss making it
a bad choice if this frequency is important.
D. Two Channel / Four Frequency Cymbal Band Pass/LPF Diplexer
Fig. 56 shows another diplexer which uses a low pass filter and a cymbal band
pass filter such as the one described in Appendix VI to provide the pass band regions.
The low pass filter is designed for a center frequency o f 9.5 GHz, and it passes 18 GHz
using its harmonic pass band region. The cymbal band pass filter is designed for a
fundamental frequency o f 11.9 GHz, and it passes 20.4 GHz in its harmonic pass band
regions.
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89
12.8 mm
Port 2
^
t
54 mm
6.48 mm
0.34 mm 6.25 mm
Port
7.21 mm
0.5 mm
0.34 mm
1.47 mm
10.1 mm
Port 3
Fig. 56. Low pass filter / cymbal band pass filter dual frequency diplexer for 9.5, 11.9,
18. and 20.4 GHz.
The measured return loss at port I is shown in Fig. 57.
-10
-25
-30
8
9
10
11
12 13 14 15 16 17 18
19 20 21 22 23
Frequency (GHz)
Fig. 57. Low pass filter / cymbal band pass filter dual frequency diplexer return loss.
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90
The measured insertion loss is charted in Fig. 58.
ffl -10
C/3
C/3
- I }
o
-20
o
o
= -30
-
S31
S21 J
-40
8
9
10
11
12 13
14 15 16 17 18
Frequency (GHz)
19 20 21 22 23
Fig. 58. Low pass filter / cymbal band pass filter dual frequency diplexer insertion loss.
Table 11 lists the measured return and insertion losses at the design frequencies.
Table 11. LPF/Cymbal Diplexer Performance
11.9 GHz
00
oJ1
SI 1 measured (dB)
S21 measured (dB)
S 3 1 measured (dB)
9.5 GHz
-14
-1.17
-21.8
-28.3
-1.39
18 GHz
-15
-2.87
-46.6
20.4 GHz
-16
-37.6
-3.77
This geometry allows for DC blocking on port 3 but not on port 2. It also has very broad
pass band regions. The cymbal band pass filter has a harmonic to fundamental frequency
ratio o f around 1.7. The low pass filter as in the previous diplexer has a harmonic to
fundamental frequency ratio o f 1.9.
This filter structure has wide pass bands with
reasonably low insertion loss.
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91
E. Two Channel / Four Frequency’ Periodic Structure Diplexers
Port I (10. 12, 19. 21 GHz)
17.4864 mm
5.9517 m m f
32.024 mm
3.15 mm
All stubs have a 0.4 mm width.
Port 3 (12,21 GHz)
Port 2 (10, 19 GHz)
1.478 mm
27.624 mm
1111111111
50 Q Transmission Line
a— o
ITIITTIIJT
10 GHz and 19 GHz Blocking Network
12 GHz and 21 GHz Blocking Network
(b)
Fig. 59. (a) Diplexer layout (top-view). (b) Equivalent circuit model.
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92
This particular type of diplexer offers wideband, low-loss, high isolation and easy
manufacturing [48]. The diplexer schematic, as well as its individual filters shown in
Fig. 59, was simulated using the full-wave electromagnetics simulator IE3D [39], The
diplexer uses two periodic filter structures with open-circuited stubs to achieve the
required stop bands [49]. The centers o f the stop bands occur when the lengths o f the
open-circuited stubs are at odd multiples o f a quarter wavelength creating shunt short
circuits at the middle o f the main line. Low-loss pass bands are formed between the
adjacent stop bands. Each filter must be designed individually with IE3D to yield the
desired stop bands before combining the two as a diplexer. Stop bands can be shifted in
frequency by changing the stub lengths.
Making the stubs longer will shift the stop
bands towards lower frequencies as well as shorten the pass bands. Making the stubs
shorter will shift the stop bands towards higher frequencies and lengthen the pass bands.
The filters should be designed such that the lowest possible harmonic stop bands are
used to create the desired pass bands since higher order harmonics will have more loss.
The filters are designed and fabricated on 20 mil Duroid 5870 with a dielectric constant
o f 2.3. All o f the ports are terminated into 50 Q. The input signals at port 1 (10, 12, 19,
21 GHz) are separated by the diplexer into two channels (10, 19 GHz and 12, 21 GHz)
with minimal distortion. The highest frequency in the IE3D simulation was chosen to be
23 GHz and the gridding was set at 15 cells per wavelength. The measured data was
acquired from the HP 8510 network analyzer measurement system.
The diplexer uses quarter wavelength balanced stubs to achieve band stop
characteristics.
Each stub can be represented by a short-circuited RLC series circuit.
The equivalent circuit o f the diplexer is shown in Fig. 59. Each open-ended stub has an
input impedance Z,„ that can be characterized in terms o f a series RLC circuit. Assuming
that the losses o f the stubs due to their corresponding resistances (R's) are negligible,
each o f the stubs’ input impedances is defined as [50]
Z in = —j Z a cot (31 = ja>L - j - ^ ~
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(85)
93
2k
where Z0 is the characteristic impedance o f each o f the six stubs, P = — , and the stub
Ag
length C= nXv .
The guided wavelength o f the each stub is k g = —
VV
wher e ka
represents the free-space wavelength o f the microwave energy.
When resonance occurs, the resonant frequency from Equation (83) is f r = -----\ = 2k \ I L C
The equivalent RLC values are given by Matthaei [51] as
R=
(2m - P
L=
4
( 2m-\
Z 0aAg
\
8
C = -------=
(2K f r )-L
Z,
2fr^r
m = 1,2,3,...
m = 1.2.3,...
-------------Z (1k
(86)
fr(2m- \ )
(87)
m = 1,2,3,...
(88)
where a is the attenuation o f the stubs.
For resonance to occur. Zin = 0 . If Z m = 0 , an equivalent short circuit appears on the
main line o f each filter rejecting the incident energy for which the stub length is a
multiple o f a quarter wavelength or
m = l— 3—
(89)
Each blocking network filter has ten stubs with spacing determined by IE3D. The stubs
in the 10, 19 GHz blocking network each have a length C= 13.1 mm, characteristic
impedance Za = 105 Q an d effective dielectric constant
=1.84 (from EE3D).
Similarly, the stubs in the 12, 21 GHz blocking network each have a length
( = 1 5 .2 7 mm. characteristic impedance Za = 105 Q a n d effective dielectric constant
s,rf = 1.84 (from 1E3D). The resonant frequency (£) for these stubs is
f
r
=
~
Ag \ I £e/r
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(90)
94
For the 13.1 mm stubs, when m = 1,2, and 3, the stopbands will occur a tfr = 4.22, 12.66,
and 21.1 GHz, respectively. For the 15.27 mm stubs, when m = 1,2, and 3, the stopbands
will occur at f r = 3.62. 10.86, and 18.1 GHz, respectively. These frequencies represent
the center o f the stopbands shown in Fig. 60 through Fig. 63.
The diplexer uses two periodic filter structures to achieve the required pass bands
and stop bands. The vertical filter (Filter 1) o f Fig. 59 passes 10 GHz between the Ist
and 2nd harmonic stop bands. Similarly, Filter 1 passes 19 GHz between the 2nd and 3rd
stop bands.
-10
-20
3
-30
1 -40
-70
'Simulated
• Measured
-80
-90
0
7
4
6
8
10
12
14
16
18
Frequency (GHz)
Fig. 60. Insertion loss for 10. 19 GHz filter.
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20
22
95
0
-10
15
-20
-25
-30
Simulated
Measured
-40
0
4
6
8
10
12
14
16
18
20
Frequency (GHz)
Fig. 61. Return loss for 10, 19 GHz Filter.
The simulated and measured insertion and return losses are summarized in Table 12.
Table 12. Simulated and Measured Results for Filter 1
Su Simulated (dB)
Si i Measured (dB)
S;i Simulated (dB)
S;i Measured (dB)
10 GHz
-21
-17
-0.37
-0.6
12 GHz
-0.35
- l.l
-48
-47
19 GHz
-10
-11
-1.2
-2.5
21 GHz
-0.78
-2.3
-45
-45
The horizontal filter (Filter 2) o f Fig. 59 passes 12 GHz between the 2nd and 3rd
harmonic stop bands. Likewise, Filter 2 passes 21 GHz between the 3rd and 4th harmonic
stop bands.
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96
Simulated
Measured
-90 ---------------------------------------------------------------------------------------0
2
4
6
8
10
12
14
Frequency (GHz)
16
18
20
22
18
20
22
Fig. 62. Insertion loss for 12, 21 GHz filter.
Simulated
Measured
0
2
4
6
8
10
12
14
16
Frequency (GHz)
Fig. 63. Return loss for 12. 21 GHz filter.
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97
The simulated and measured insertion and return losses are listed in Table 13.
Table 13. Simulated and Measured Results for Filter 2
12 GHz
-11
-10
-2
-3
19 GHz
-0.63
-1.7
-41
o
in*
S 11 Simulated (dB)
Si i Measured (dB)
S:i Simulated (dB)
Sji Measured (dB)
10 GHz
-0.25
- 1.8
-57
-48
21 GHz
-17
-11
-0.89
-0.94
Both filters use the 2nd and 3rd rejection bands for blocking the frequencies of
choice. 1E3D provides good simulations for the filter’s performance as shown in Fig. 60
through Fig. 63.
The multi-frequency diplexer is formed by connecting the two aforementioned
filters with the T-junction shown in Fig. 59. The positioning o f the filters from the Tjunction was determined using 1E3D. These distances greatly affect the return loss or
matching o f the system as well as the insertion loss. However, the isolations do not
fluctuate much (<5 dB) with the variations o f filter placement since the isolation created
by the stop bands depends on the lengths o f the open-circuited stubs. Each filter uses 10
stubs to achieve more than 50 dB in isolation. All o f the main lines have a width of
1.478 mm corresponding to a characteristic impedance o f 50 Q.
The diplexer’s
performance is plotted in Fig. 64 through Fig. 66.
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98
0
Insertion Loss (dB)
-10
-20
-30
-40
Measured
Simulated
-50
-60
9
10
11
12
13
14
15
16
17
18
19
20
21
22
20
21
22
Frequency (GHz)
Fig. 64. S21 and Si; Insertion loss o f the diplexer.
-10
a
^
-20
C/J
q
-30
c
Measured
Simulated
-50
-60
9
10
11
12
13
14
15
16
17
18
19
Frequency (GHz)
Fig. 65. S31 and S 13 Insertion loss o f the diplexer.
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99
q
c3
-15
-20
— Measured
■ 'Simulated
-25
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Frequency (GHz)
Fig. 66. Si i return loss o f the diplexer.
The simulated IE3D data and measured data agree very well. The results at 10, 12, 19.
and 21 GHz are summarized in Table 14.
Table 14. Simulated and Measured Results for the Diplexer
1
1
P
Si i Simulated (dB)
Su Measured (dB)
S;i Simulated (dB)
S:i Measured (dB)
S31 Simulated (dB)
S31 Measured (dB)
10 GHz
-25.3
-15.5
-0.42
-62.2
-51
12 GHz
-35.2
-12.7
-50
-53.3
-1.8
-3.4
19 GHz
-14.7
-18.3
1.1
-1.25
-52.1
-60.1
-
21 GHz
-10
-10
-56.1
-57.9
-1.9
-2.4
The diplexer has very good pass band insertion loss performance due to the inherent lowloss in the periodic filters. The measured insertion loss varies from 0.4 dB to 3.4 dB for
the four frequencies. The isolation is extremely good and exceeds 50 dB for all four
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100
frequencies. Each o f the pass bands has very good bandwidth o f around 1 GHz as shown
in Fig. 64 through Fig. 66. The return loss is better than 10 dB.
One o f the disadvantages o f this diplexer can be witnessed when it is used in a
transceiver (T/R) module.
In a T/R module, two opposing diplexers are used with
amplifiers placed between them. When the system is operational, low frequency noise (<
3 GHz in this case) gets continuously amplified until the system becomes unstable. In
such an application, it may be more advantageous to use the diplexer shown in Fig. 53 in
which narrowband bandpass filters are used.
In order to minimize dispersion, the signal time delay o f the frequencies of
interest must be equal [50]. The energy at 10 and 19 GHz must flow from port I and
reach port 2 at approximately the same time. Likewise, the energy at 12 and 21 GHz
must flow from port I and reach port 3 at about the same time. The signal time delay ( r)
sometimes referred to as the group delay from port 1 to port 2 is
dco
where Z S 21 is the insertion phase and co is the frequency in rad/sec. Fig. 67 shows the
time delay for both channels o f the diplexer. From port I to 2. 10 and 19 GHz have time
delays o f 1.41 ns and 1.72 ns, respectively. Similarily, for port 1 to 3, 12 and 21 GHz
have time delays o f 1.78 ns and 1.64 ns, respectively. The pass bands containing 10. 12,
19. and 21 GHz have uniform time delay varying from around 1.3 ns to 1.8 ns. This
constant time delay for the pass bands is caused by the imaginary portion o f the
propagation constant being an almost linear function o f frequency.
This results in
minimal dispersion.
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101
Port I to Port 2
3.5
- - Port 1 to Port 3
2y
C3
«■<
9
10
11
12
13
14 15 16 17
Frequency (GHz)
18
19
20
21
22
Fig. 67. Time delay for both diplexer channels.
The simulated and measured data matches extremely well.
IE3D predicts the
diplexer's behavior very well. The use of the periodic stub architecture allows many
resonant sections to be used to achieve high isolation while maintaining low-loss
performance and minimal distortion. This diplexer is used for transmitting 10 and 19
GHz and receiving 12 and 21 GHz or vise-versa. The filter could be built on a higher
dielectric substrate for size reduction. The diplexer is very easy to manufacture since no
coupling gaps are necessary.
transmission
line mediums
This stopband topology can also be applied to other
such as the coplanar stripline filter used in the
aforementioned rectenna array and the stripline filter described in Appendix VII.
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102
CHAPTER VI
CONCLUSIONS
In summary, this dissertation presents novel technological solutions to
complicated real-world problems. The rectenna array provides a possible solution for
clean energy and has been shown to be realistic from a development standpoint. The
RFID tag meets the demand for the real-time monitoring o f oil drill pipe. Additional
studies will need to be done in order to transform these prototypes to their final forms,
but the work described in this dissertation is big step in the right direction.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
103
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[27] T. Razban, R. Lemaitre, M. Bouthinon, and A. Coumes, “Passive transponder card
system -
identifying objects through microwave interrogation,” Microwave
Journal, pp. 135-146, October 1987.
[28] L. Turner, “Passive electronic labels for remote object identification utilizing
modulated rf backscatter,” Journal o f Petroleum, vol. 11, pp. 1-14, April 1994.
[29] P. Salonen, M. Keskilammi, L. Sydanheimo, and M. Kivikoski, “An intelligent
2.45 GHz beam-scanning array for modem RFID reader,” in IEEE International
Conerence. on Phased Array Systems and Tech., pp. 407-410, 2000.
[30] P. Salonen, M. Keskilammi, L. Sydanheimo, and M. Kivikoski, “An intelligent
2.45 GHz multidimensional beam-scanning x-array for modem RFID reader,” in
IEEE Antennas and Propagation Society International Symp., vol. 1, pp. 190-193,
2000.
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106
[31] G. Matthaei, L. Young and E. M. T. Jones, Microwave Filters, ImpedanceMatching Networks, and Coupling Structures, sec. 16.05, New York: McGrawHill, 1964.
[32] G. Matthaei and E. G. Cristal, “Multiplexer channel-separating units using
interdigital and parallel-coupled filters,” IEEE Transactions on Microwave Theory
and Techniques, vol. MTT-13, pp. 328-334, May 1965.
[33] R. J. Wendel, “Printed-circuit complementary filters for narrow bandwidth
multiplexers,” IEEE Transactions on Microwave Theory and Techniques, vol.
MTT-16, pp. 147-157, March 1968.
[34] M. H. Capstick, “Microstrip lowpass-bandpass diplexer topology,” Electronic
Letters, vol. 35, no. 22, pp. 1958-1960, October 28th, 1999.
[35] G. Czawka, “A new ring microstrip diplexer,” in International Conference on
Microwaves and Radar 1998, vol. 2, pp. 518-522, 1998.
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Conference on Microwaves and Radar 1998, vol. 2, pp. 620-623, 1998.
[37] A. F. Sheta, J. P. Coupez, G. Tanne, S. Toutain, and J. P. Blot, “Miniature
microstrip stepped impedance resonator bandpass filters and diplexers for mobile
communications,” in IEEE MTT-S, vol. 2, pp. 607-610, 1996.
[38] T. Yoo and K. Chang, “Theoretical and experimental development o f 10 and 35
GHz rectennas,” IEEE Transactions on Microwave Theory and Techniques, vol.
40, no. 6, pp. 1259-1266, June 1992.
[39] IE3D Release 6.1, Zeland Software, Inc., Fremont, California, August 1998.
[40] H. Morishita, K. Hirasawa and T. Nagao, “Circularly polarised rhombic hula loop
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Wave Letters, vol. 7, no. 8, pp. 214-216, August, 1997.
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[42] B. Strassner and K. Chang, “A circularly polarized rectifying antenna array for
wireless microwave power transmission with over 78% efficiency,” in IEEE MTTS Int. Microwave Symp. Dig., Seattle, WA, June 2002, pp. 1535-1538.
[43] H. F. Lee and W. Chen, Advances in Microstrip and Printed Antennas. New York:
John Wiley & Sons, Inc., 1997, pp. 165-177.
[44] K. Chang, Microwave Solid-State Circuits and Applications. New York: John
Wiley & Sons, Inc., 1994, pp. 208-218.
[45] C. Baianis, Antenna Theory Analysis and Design. New York: John Wiley & Sons,
Inc., 1982, pp. 64-65.
[46] D. Friedman, H. Heinrich, and D. Duan, “A low-power cmos integrated circuit for
field-powered radio frequency identification tags,” in IEEE International SolidState Circuits Conference., pp. 294 - 295, 1997.
[47] U. Kaiser and W. Steinhagen, “A low-power transponder IC for high-performance
identification systems,” IEEE Journal o f Solid-State Circuits, vol. 30. pp. 306 310, March 1995.
[48] B. Strassner and K. Chang, “Wide-band low-loss high-isolation microstrip
periodic-stub diplexer for multiple-frequency applications,” IEEE Transactions on
Microwave Theory and Techniques, vol. 49, pp. 1818-1920, October 2001.
[49] R. N. Bates and R. E. Pearson, “Designing bandstop filters for microwave
frequencies,” Electron. Engineering, pp. 39-41, April, 1978.
[50] D. Pozar, Microwave Engineering, New York: Wiley & Sons, 1998.
[51] G. Matthaei, L. Young, and E. M. T. Jones, Microwave Filters. ImpedanceMatching Networks, and Coupling Structures. New York: McGraw-Hill, 1964.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
108
APPENDIX I
RECTENNA PROGRAM
This section presents a matlab program for determining the rectenna operating
conditions based on desired criteria. The matlab code is shown between the rows o f
asterisks.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%
%%%%%%%
This p r o g r a m computes the rectenna d i m e n s i o n s
as well as diode a n d c a p a c i t o r s p a cing
%%%%%%%
%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%% cons t a n t s %%%
VdcV=100;
Vout=100;
%%%
%%%
voltage across diode, make large initial%%%
%%%
c o n d i t i o n ,meaningless right no w
1
%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%
%%% u s e r inputs %%%
% %%%%%%%%%%%%%%%%%%
% %%%% %%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%
1
t
i
i
\/
'
%%% CPS dimens i o n s %%%
g a p = 0 .4;
w i d t h = 0 .824;
e e f f =1.4;
%%%
%%%
%%%
gap between cps lines in m i l l i m e t e r s
%%%
width between cps lines in mill i m e t e r s
%%%
effective d i e l e c t r i c constant from ie3d %%%
Zocps=175;
c p s l a m d a ^ 4 4 .7734
R matc h = Z o c p s ,-
%%%
%%%
%%%
CPS char a c t e r i s t i c impedance in ohms
CPS w a v e l e n g t h in m m from ie3d
M a t c h diode res to this resist a n c e
%%%
%%%
%%%
f= 5 . 8 e 9 ;
w=2*pi*f;
C=3e8;
lamda=c/f ,-
%%%
frequency of o p e r a t i o n in hertz
%%%
%%%
%%%
speed of light in m/s
free space w a v e l e n g t h in m
%%%
%%%
cp_pol_loss=3;
%%%
C i rcular p o l a r i z a t i o n loss in dB
%%%
%%% diode parameters %%%
Rs=4 ;
Cjo=0.02e-12;
Vbr=ll
V b i = 0 .7;
%%%
%%%
%%%
%%%
series resistance in ohms
%%%
zero bias j u n c t i o n c a p a c i t a n c e in farads%%%
breakdown v o l t a g e in volts
%%%
built in poten t i a l in volts
%%%
Vomax = V b r / 2 . 2
%%%
m a x voltage acro s s diode in v o l t s
%%% link constants %%%
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
%%%
109
GrdB=ll;
GtdB= 17;
%%%
%%%
B R F 5 _ 8 1 o s s d B = 0 .3;
D c m = 10;
%%%
%%%
%%%
g a i n of rhombic loop from ie3d
g a i n of standard g a i n h o r n
%%%
%%%
S21 loss of low pass filter
%%%
m a x d i m e n s i o n of h o r n
%%%
link distance in meters for "far field"
(largest antenna)
%%%
if
((D c m / 1 0 0 ) / l a m d a c O .3)
R m = l .6*lamda;
elseif ( (Dcm/100)/ l a m d a < 2 .5)
Rm=5*Dcm/100;
else
Rm=2*(Dcm/100)*2/lamda;
end
R f t = R m * 1 0 0 / (2.45*12)%%%
%%% loop ranges
d i stance
of link in feet
%%%
%%%
wg_powermindBm=25;
%%%
wg_powermaxdBm=3 5 ;
%%%
w g _ p o w e r s t e p = .5 % % %
m i n i m u m waveguide source power
m a x i m u m waveguide source power
w a v e g u i d e source po w e r step
%%%
%%%
%%%
s p d B m m i n = 0 .5;
spdBmmax=50;
spstep=0.5;
%%%
%%%
%%%
m i n i m u m source power in dB m
m a x i m u m source p o w e r in dBm
source p o w e r step in d B m
%%%
%%%
%%%
minRl=5;
maxRl = 300;
Rlstep=5;
%%%
%%%
%%%
m i n i m u m load resistance
in ohms
m a x i m u m load resistance
in ohms
load resistance step in volts
%%%
%%%
%%%
minVo=l;
m a x V o = V b r / 2 .2;
V o s t e p = 0 .05;
%%%
%%%
m i n i m u m diode voltage in volts
output diode voltage step in volts
%%%
%%%
error of resistance in ohms
error of
voltage in volts
%%%
%%%
%%%error tolerances%%%
r e s i s t a n c e _ e r r o r = 5 %%%
v o l t a g e _ e r r o r = .2 % % %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%«%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%Compute e ffective area for rhombic loop a n t enna to deter m i n e a r r a y spacing%%
%%%maximum effective area in mm*2
A emins q uaremm=lamda*2/ (4*pi) * (10'* (GrdB/10) ) *1000*1000
coverageradiusmm=sqrt(Aeminsquar emm/pi)
%%%free space w a v e l e n g t h s q u a r e d in mm*2
1a m d a s q u a r e d i n s q u a r e m m = 1a m d a *2*1000*1000
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%Computation of rhombic loop dimensions in m illimeters%%%
l i n e w i d t h i n m m = 2 * 0 .008*lamda*1000
gapwidthinmm=0 .01S*lamda*1000
p e r i m e t e r i n m m = l .12*lamda*1000
side l e n g t h i n m m = p e r i m e t e r i n m m / 4 ;
centertogapinmm=0;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
110
%%%CPS ca l c u l a t e d Zo%%%
kpssqrt ( (1- (gap/gap+2*width) ) *'2) ;
Z o=120»pi‘"2/ (log (2* (1+sqrt (kp) )/ (1-sqrt (kp) ) ) *sqrt ( (eeff+1) /2) ) ;
%%%capacitor impedance calculation%%%
for
C a p _ v a l u e = 2 e - 1 0 :- l e - 1 2 :le-12
%%%chooses
s m allest
working
capacitance%%%
Z c = l / (j » w * C a p _ v a l u e ) ;
zcnorm=Zc/Zocps;
if a b s (i m a g ( z c n o r m ) )<.001 %%%very close to short circuit%%%
c apacitan c e = C a p _ v a l u e
va=zcnorm;
end
end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%Waveguide simul a t o r incident power density on r e ctenna calculation%%%
wg_sidelengthcm=6;
p o w e r = [];
d e n s i t y = [];
for so u r c e p o w e r d B m = w g _ p o w e r m i n d B m : w g _ p o w e r s t e p :w g _ p o w e r m a x d B m
power=[power sourcepowerdBm];
p d e n s m w _ c m 2 = ( 1 0 * (sourcepowerdBm/1 0 ) ) / ( w g _ s i d e l e n g t h c m * 2 )
densitys: [density pdensmw_cm2] ;
end
;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
v o l t a g e = [];
for Vo=m i n V o : V o s t e p : m a x V o
volt a g e = [ v o l t a g e V o ] ;
C j = C j o * s q r t ( V b i / ( V b i + a b s ( V o ) ));
% % % j u n c t i o n capacitance%%%
R l o a d s [] ;
effRl= [] ;
r e a l d i o d e Z s [];
imagdiodeZs[ ] ;
l e n g t h d c s [];
o n t h e t a s [];
for Rlsm i n R l : R l s t e p r m a x R l
Rloads[Rload R l ] ;
% % %theta o n calculation%%%
% % % Increase u p p e r rainge if eff curve has w i e r d disconuity%%%
for t o n s O .0001:.001:30
a=tan(ton) -ton-pi* (Rs/Rl) / (l^Vbi/cibs (Vo) ) ;
if cibs (a) <0 .001
thetaonston;
thetaondegreessthetaon*180/pi;
break
e nd
end
onthetas[ontheta thetaondegrees];
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ill
% %%efficiency c a l c u lation%%%
tl=(thetaon* (1 + 1/ (2*cos (thecaon) *2) ) - 3 / 2 * t a n (thetaon) ) ;
cerml=Rl/ (pi*Rs) * {1+Vbi/abs (Vo) )*'2»tl ;
c2= ((pi-thetaon)/ (cos(thetaon)*2 ) + e a n ( t h e t a o n ) )
term2=Rs*Rl*Cj *2*w*2/ (2*pi) * (1+Vbi/abs (Vo) ) *t2
C3=(can(thetaon)-checaon);
cerm3=Rl/(pi*Rs) * ( l + V b i / a b s ( V o ) )* V b i / a b s ( V o ) * t 3 ;
eff = l/ (l+cerml-t-term2-t-cer!Ti3) ;
effRl=[effRl e f f ];
%%%diode impedance calcula c i o n s % % %
%
r d= p i*Rs/cos(thetaon)* 1 / ( ( c h e c a o n / c o s ( t h e c a o n ) - s i n (C h e t a o n ) )) ;
t4=j*w*Rs*Cj* (sin(thetaon) + (pi-chetaon) / (cos (checaon) ) )
z d = pi*Rs/(cos(checaon)* ( c h e t a o n / c o s ( c h e c a o n ) - s i n ( t h e c a o n ) )♦ C 4 ) ;
zd n o r m = z d / Z o c p s ;
y d n o r m = 1/z d n o r m ;
realzd=real (zd)
imagzd=imag (zd)
%%%Smith Chart c o n v e rsions%%%
i magydno r m = i m a g ( y d n o r m ) ;
r eal z d n o r m = r e a lz d / Z o c ps ;
i magzdno r m = i m a gz d / Z o c ps ;
c5= (l + 2*realzdnorm+realzdnorm*2 + i m a g z d n o r m A'2) ;
gammar= (r e a l zdnorm‘‘‘2+imagzdnorm',‘2 - 1) / 15 ;
g ammai=2*imagzdnorm/ (l+2*realzdnorm+realzdnorm',‘2-t-imagzdnorm*2) ;
g a m m a m a g = s q r c ( g a m m a r ^ Z + g a m m a i - Z );
if (gammar>0 & gammai>0)
g a m m a a n g = ( a c a n ( g a m m a i / g a m m a r ) )*180/pi;
elseif (gammar>0 & gammai<=0)
g a m m a a n g = - ( a c a n (g a m m a i / g a m m a r ) )*180/pi;
elseif (gammar<=0 & gammai>0)
g a m m a a n g = 1 8 0 - (( a c a n ( g a m m a i / g a m m a r ) )* 1 8 0 / p i ) ;
else
g a m m a a n g = ( a c a n ( g a m m a i / g a m m a r ) )* 1 8 0 / p i - 1 8 0 ;
end
realdiodeZ=[realdiodeZ r e a l z d ] ;
imagdiodeZ= [imagdiodeZ imagzd]
%%%cuning out reactance w i c h capa c i c o r an d solve for
%%%distance between di o d e a n d c a p a c i t o r in terms of l a m d a
%%%
%%%
distdc=l/ (2*pi) *acan(1/imagydnorm)
%%%in w a v e l e n g c h s % % %
if imagydnorm>0
ldc=distdc,else
ldc=abs(discdc)+ 2 * ( 0 .25-ab s ( d i s c d c ) );
end
lengchdc= [lengchdc ldcl
%%%transmit recieve a n a l y s i s % % %
%%%macches diode resist a n c e to Rmatch%%%
if tabs(realzd-Rmatch)<resistance_error)
psource= []
VOlC= [] ;
pdensity= []
d i o d e _ p o w e r = [) ;
d c _ p o w e r = [1 ;
for P t d B m = s p d B m m i n : s p s t e p :sp d B m m a x
%%%source p o w e r % % %
p s o ur c e = [ p s o u r c e P t d B m ] ;
t 6 = 1 0 ~ ( P C d B m / 1 0 ) * 1 0 ‘ (GtdB/10)*10A ( G r d B / 1 0 ) ;
cerm= (lamda/ (4*pi*Rm*lOO/ (2.45*12) ) )
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
112
PrdBm=10*logl0 (t6*term*2) -cp_pol_loss ,•
P d d B m =PrdBm-BRF5_81assdB ;
P d c W = e f f • ( 1 0 * (PddBm/10))* 1 0 * - 3 ;
VdcV=sqrt(PdcW*realzd);
volt=[volt Vd c V ] ;
t7= 1 0 * ( P t d B m / 1 0 ) * ( 1 0 * (GtdB/10));
P d m w _ c m 2 =C7/ (4*pi* (Rf t*12*2 .54) *2) ;
pdensity=[pdensity Pdmw_cm2];
diode_power=[diode_power P d dBm];
dc_ p o w e r = [ d c _ p o w e r P d c W * 1 0 0 0 ] ;
VdcV;
VO;
if abs(VdcV-Vo)<v o l t a g e _ e r r o r
loadresiscanceinohras=Rl;
outputvoltageacrossdiodeinv=Vo,sourcepowerindBm=PtdBm;
dcconversionef f iciencyinpercent=ef f * 100 ,capaci tortodiodelen g t h i n m m = l d c » c p s l a m d a ,d c p a s s c a p a c i t a n c e i n p f = c a p a c i c a n c e / ( l e - 1 2 ) ,Pdmw_cm2;
zd;
s u b p l o t ( 3 , 3 , 1 ) .plot(psource,pdensity).grid on,
t i t l e ( ' P o w e r D e n sity vs Source Power'!,
x l a b e l ('Ps ( d B m ) '),y l a b e l ('Pd (mw/cm*2)')
s u b p l o t (3,3,2),p l o t ( R l o a d , r e a l d i o d e Z . R l o a d , i m a g d i o d e Z ) ,g r i d on,
title ( ' D i o d e Res and Reac vs Load Res'),
xlabel('Rl, XI (ohms)'),y l a b e l (’R d (ohms)')
s u b p l o t (3,3,3),plot(Rload , o n t h e t a ) . g r i d on,
title( ' T h e t a o n vs Load Res'),
x l a b e l (’Rl (ohms) ’). y l a b e l ('thetaon (degrees) ')
s u b p l o t ( 3 , 3, 4 ) . p lot(psource,diode_power).grid on,
t i t l e ( ' P o w e r to Diode vs Source Power'),
x l a b e l ( ’Ps (dBm)'),y l a b e l ('Pd (dBm)')
s u b p l o t (3,3,5),plot (Rload,lengthdc*cpslamda).grid on,
t i t l e ('Di o d e->Cap Length vs Load Res'),
xl a b e l ( ' R l (ohm s ) '). y l a b e l ('L (mm)')
s u b p l o t ( 3 , 3 , 6 ) .plot(Rload,effRl*100).grid on,
t i t l e l ' D C C onv Eff vs L o a d Res'),
x l a b e l ('Rl (oh m s ) '),y l a b e l ('Eff (%)')
s u b p l o t (3,3,7),p l o t ( p s o u r c e , v o l t ) .grid on,
title ( ' D i o d e voltage vs Source Power'),
x l a b e l (’Ps (dBm)'). y l a b e l ('Voltage (V ) ’)
s u b p l o t (3,3,8),p l o t (psource,dc_ p o w e r ) . g r i d on,
t i t l e ('Output DC Power vs Source Power'),
xl a b e l ( ' P s (dBm)'). y l a b e l ('Pout ( m W ) ')
e nd
end
en d
end
end
s u b p l o t ( 3,3,9).plot(power,density).grid on,
t i t l e ( 'WG inc p o w e r dens vs Source Power'),
x l a b e l ( ' P s (dBm)'). y l a b e l ('Pd (mW/cm*2) ')
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
113
This program looks at a range o f source power, subsequent voltage and load
resistance in order to characterize the performance o f the rectenna.
An operating
condition is established by first choosing a diode voltage and load resistance which in
turn determines a DC conversion efficiency. Then Friis equation is used in conjuction
with the aforementioned efficiency to determine the diode voltage for a determined
distance between the hom and rectenna.
This diode voltage is compared with the
previous diode voltage to find if they match within a certain error. If not either or both
the diode voltage and load resistance are incremented, and the process is repeated. The
terminal output in matlab is
» rectenna
cpslamda =
44.7734
Vomax =
5
Rft =
1.7007
Aeminsquaremm =
2.6803e+03
coverageradiusmm =
29.2088
lamdasquaredinsquaremm =
2.6754^-03
These variables represent the 5.8 GHz wavelength in the CPS, maximum diode voltage,
edge o f far field (distance chosen between the hom and rectenna), effective aperature o f
the rectenna, radius o f the circular effective aperature area, and the square o f the freespace wavelength. The program also produces the charts shown in Fig. A l.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
114
IM to n w U M M t
ZOO
IS O
ISO
f 45
r
5
i»
IOO
40
•to O M i v tS eu rct Pmmr
200
900
DC C an v B T v t u n i t e s
D M * e> * ap u n f i t v c u a t f M s.
00
30
■10
40
100
50
n
v t S o u rc a P o v n r
100
ZOO
200
300
O u tp u t O C P o w o r v o S o u r * P o w u r
140
100
120
100
£3
*£ «o
& 60
1
f 2
60
^ 40
1
40
20
30
0
to
20
30
SO
Fig. A l. Matlab output charts.
Going from left to right and top to bottom, the plots show power density versus
source power, diode resistance and reactance versus load resistance, theta-on versus load
resistance, power delivered to the diode versus source power, diode to capacitor distance
lllc versus load resistance, DC conversion efficiency versus load resistance, diode voltage
versus source power, output DC power versus source power, and incident power density
in a C-band waveguide versus source power. The middle-middle chart shows he to be
about 10.8 mm.
This is reasonably close to the 9.5 mm measured distance.
efficiency is around 80% while the output rectified DC voltage is 5 V.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The
115
APPENDIX H
RFID TEMPERATURE CHARACTERISTICS
This section describes the heat transfer characteristics o f the RFID tag. Since the
down-hole environment can have very high temperatures, knowledge o f the temperature
increase inside the tag at the electronics is very important. This importance stems from
the fact that the silicon used to construct the microcontroller and several o f the diodes
degrades its electrical characteristics at around 150 °C.
The ambient temperature To outside the drill pipe is chosen to be 245 °C. This
temperature is at the higher limit o f temperatures that the tag will encounter. Since the
tag is contained in the drill pipe with no convection, radiation or conduction cooling,
there is no way to keep the tag from ultimately heating to the outside temperature To.
The maximum temperature ratings for the tag’s electronic components are listed in Table
A l.
Table A l. Maximum Temperature Ratings for the Tag’s Digital Electronics
Operating
Storage
DC-to-DC Converter
80 °C
125 °C
Oscillator
85 °C
125 °C
Microcontroller
85 °C
150 °C
One way to at least slow the tag’s rise in temperature is to use insulating foams. Various
layered strata in the tag can form temperature gradients that slow the rise in temperature.
Some o f the insulators being considered are listed in Table A2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
116
Table A2. Insulating Foam Thermal Conductivities and Costs per Tag
Marketech Int.
Aerogel
Inspec Foams
Densifled HT
HT - 340
unspecified
Orion Industries
0.02
0.06
0.032
0.046
0.4 - 0.8
$6.76 - $8.60
$11.91 -$15.16
$0.04 - $0.30
$0.17-$0.50
$0.50 - $0.80
The heat transfer analysis described in this section pertains to the tag structure
shown in Fig. A2. This structure varies somewhat from the tag structure o f Chapter V
that was actually built and tested.
complex undertaking.
Modeling the actual tag would be an extremely
However, the importance of the insulating foam on the tag’s
heating will be clearly shown.
Duroid
T„ = 245°C
■nfO
r' ; = T1 0 - '( T‘ l a - T1 ! ) 'C
nlQ
T. = T ,~ (T,o - T ,)c iU'Lmc1tL;t
1.524 mm - 2 (0.635 mm)
Aluminum
3 mm
Insulation
1.35 mm
Air
5.628 mm
Digital Electronics
2.65 mm
Air
5.628 mm
rc =T0 - { T :o- T 0) c ^ » L
1.35 mm
3 mm
Insulation
3 mm
1.35
mm
16.7 mm
1.35 3 mm
mm
Fig. A2. Tag structure for heat transfer analysis. The tag size is a cylinder with a 1’
diameter and a 1” height.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
117
The two fundamental equations to characterize the heat performance o f the tag
are given by [A l] as
and
Q „ = m cA T + Qoul
(A2)
where 7# is the ambient temperature outside o f the outer insulation or 245°C, T o is the
initial temperature o f the electronics inside o f the inner insulation or 20°C, k is the
thermal conductivity in W/(m K.), A is the outer surface area o f the insulation in m2, L is
the thickness o f the insulation in m, m is the mass o f what is inside o f the insulation in
kg, c is the specific heat o f what is inside the insulation in kJ/(kg K), and t is time in
seconds. In (A2), Qi„ is the heat flowing into the layer whereas Qout is the heat flowing
out o f the layer. When multiple layers are used, Qou, o f the ith layer is Qm o f the (i+ l)‘h
layer and so on.
The values for m and c come from a single layer as opposed to a
dependence on the layers collectively.
The inner insulation is a cylinder 1.35 mm thick. The digital components are
assumed to be only the microcontroller with dimensions 12.95mm x 10.55mm x 2.65
mm. Not counting the outer layer the system is a cylinder with a height and diameter o f
one inch. The outer insulation has been analyzed for a thickness o f Omm, 1mm and
2mm thicknesses.
Equations (Al) and (A2) are applied to each interface boundary at adjacent
mediums.
These boundaries include the outer insulation/aluminum, aluminum/inner
insulation and the inner insulation/MCU/air interfaces. The initial temperature o f each
medium is assumed to be around room temperature or 20°C.
The matlab program describing the heating characteristics o f the tag is shown
between the asterisks. The surface area o f the inner insulation, aluminum and outer
insulation is Ac 2 , Azi and A„io, respectively.
Likewise, the thickness o f the inner
insulation, aluminum and outer insulation is L a , L ,t and L„w, respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The n
118
subscript is 0, 1 or 2 depending on whether the outer insulation is 0mm, 1mm, or 2mm
thick.
%surface a rea of the inner insolation
Ac2 = 1 . 6 0 3 26 9 0 8 5 1 * 1 0 * - 3 ;
% surface a rea of the aluminum
A21 = 2.81729358378*10*-3;
%surface area of the outer
ins for 0mm thick
A010 = 2.533462675*10*-3;
%surface area of the outer
ins for 1mm thick
A110 = 2 -77606834835*10*-3 ;
%surface area of the outer
ins for 2mm thick
A210 = 3 .02488248651*10*-3 ;
%thickness of inner insulation
Lc2 = 1 ,35*10*-3 ;
%thickness of a l uminum
L21 = 3*10*-3;
%thickness of o u t e r ins for 0m m thick
L010 = l*10*-30;
%thickness of o u t e r ins for 1mm thick
L110 = 1 * 10 * -3 ;
%thickness of o u t e r ins for 2m m thick
L210 = 2 * 10 * - 3;
%thermal condu c t i v i t y of a l u m i n u m in W/(m fC)
k21 = 205;
%thermal conductivities of insulators
k = [0.02 0.06 0.046 0.0321]
%densities of the insulators in kg/m3
p = [100 500 6.4 32] ;
%mass of ai r in kg
mair = 2 .95861295196*10*-6 ;
%specific heat of air in kJ/(kg K)
cair = 712;
%mass of the electronics
mchip = 1 .810248125*10*-3 ;
%specific heat of electronics
cchip = 8 30;
mc2 = m a i r *■ m c h i p ;
cc2 = ( c a i r *mair/mc2)-► (cchip * m c h i p / m c 2 ) ;
%volume of insulator
vinsul = 1 .86264228896*10*-6 ;
%specific heat of insulator
C21 = 1 0 0 0 ;
%mass of the aluminum
mlO = 1.76742567045*10*-2;
%specific heat of aluminum
clO = 903;
%initial temp inside insulation
Tco = 20;
%initail temp at insulation/Al b o undary
T2o = 20;
%initail temp at other ins/Al b o u n d a r y
Tlo = 20;
%temperature outside insulation (ambient)
TO = 24 5;
%range of time
t = 0:1800;
%increment
for a = 1:4;
for all four types of insulators
m2 1 = vinsul*p(a);
kc2 = k(g) ;
klO = k ( g ) ;
for i = 1:1801
%i large eno u g h to reach ste a d y state temp
uc2 = -kc2*Ac2/(Lc2*mc2*cc2) ;
u21 = -k21*A21/(L21*m21*c21) ;
uO 10
-kl0*A010/(L010*ml0*cl0);
ullO
-kl0*A110/(L110*ml0*cl0);
u210
-kl0*A210/(L210*ml0*cl0);
TO 10 (
T 0 + ( T l o - T O )* e x p ( u 0 1 0 * t ( i ) );
T110 (
T 0 + ( T l o - T O )* e x p ( u l ! 0 * t ( i ) ) ;
T210 (
T0+(Tlo-TO)*exp(u210*t(i)) ;
T021 (
T 0 1 0 ( i ) + (T2O-T010(i))* e x p ( u 2 1 * t ( i ) )
T121 (
T 1 1 0 ( i ) ♦ (T2O-T110(i))* e x p ( u 2 1 * t (i ) )
T221 (
T 2 1 C ( i ) + (T2O-T210(i))* e x p ( u 2 1 * t (i ) )
A0 (g,
T 0 2 1 ( i ) + (TCO-T021(i))* e x p ( u c 2 * t ( i ) )
Al(g,
T 1 2 1 (i)+ (TCO - T 1 2 1 (i ) )* e x p ( u c 2 * t (i ) )
A2 (g.
T 2 2 1 (i ) f ( T c o - T 2 2 1 (i ) )* e x p ( u c 2 * t (i ) )
end
end
figure
p l o t ( t , A 0 , ’:');
%a plot of temp vs time for 0mm t h i c k ins
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
119
l e g e n d ('k = 0.02', 'k = 0 . 0 6 ’, 'k = 0.046','k = 0.032');
y l a b e l (’Internal Temperature [ C l ')
xlabel ( ' T i m e [sec]')
t i t l e ('Internal T e m p erature vs Time (0mm insulation)')
axis ( [0,300,0,250] ) ,figure
%a plot of temp vs time for 1m m thick ins
plot (t,Al, ':’),legend('k = 0 . 0 2 ' , 'k = 0 . 0 6 ' , 'k = 0.046','k = 0.032');
y l a b e l ('Internal Temperature [ C ] ' )
xlabel ( ' T i me [sec]')
t i t l e ('Internal Temperature vs T ime (1mm i n s u l a t i o n ) ’)
a x i s ([0,300,0,250]);
figure
%a plot of temp vs time for 2 m m thick ins
p l o t ( t ,A 2 ,':');
l e g e n d (1k = 0 . 0 2 ' , 'k = 0.06', 'k = 0 . 0 4 6 ’,'k = 0.032');
y l a b e l (’Internal Temperature [ C ] ' )
xlabel('Time [sec]')
t i t l e ('Internal Temperature vs T ime (2mm insulation)')
a x i s ([0,600,0,250]);
***********************************************************************
250
k = 0 .0 6 .
200
150
c.
100
100
150
200
250
300
Tim e (sec)
Fig. A3. Internal temperature versus time when no outer insulation is used.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
120
This program characterizes the temperature o f the electronics for various foams
and outer insulation thicknesses. Fig. A3 shows the microcontroller temperature with no
outer insulation.
After about 50 seconds for k = 0.02 W/mK, the MCU has already
reached 150°C. After 150 seconds, the MCU is close to the outside temperature To =
245°C. Lower thermal conductivities ffc’s) o f the foam cause the MCU to heat slower
protecting the MCU longer. The lower the conductivity o f the foam is the better an
insulator it is.
Fig. A4 shows the MCU heating when an outer insulating foam with 1mm
thickness is used.
250
A: = 0 .0 6
200
U
A: = 0 .0 3 2
150
u
c.
£
u
a
100
ck.
100
150
200
250
300
T im e (sec)
Fig. A4. Internal temperature versus time for 1mm thick outer insulation.
The result is better insulation for the MCU. The MCU now takes about 260 seconds to
reach 150°C. Fig. A5 shows the MCU heating for an outer foam thickness o f 2mm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
121
200
k = 0.046
U
uUrn
3
• A:= 0.032
150
c
«
H
k = 0.02
100
200
300
400
500
600
Time (sec)
Fig. A5. Internal temperature versus time for 2m m thick outer insulation.
The result is even better insulation for the MCU over the I mm thickness. The MCU
now takes about 490 seconds to reach 150°C. Unfortunately, this amount o f time is far
too short to protect the electronics. The drill pipe can stay in very high temperatures for
days, possibly weeks. This means that the only way to operate the tag successfully in
such high temperatures with no heat dissipation is to have electronics that have a storage
and operating temperature > To. It is also important to note that 245°C is an upper limit
for To- T0 will most likely be close to 150°C. Since silicon loses its electrical properties
around 150°C, new semi-conducting materials need to be discovered for the tag to
operate in such extreme heat. Cooling techniques such as liquid flowing within the pipe
could also be used to get the heat away from the tag, but such techniques could
compromise the strength o f the pipe and would be extremely challenging to implement.
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122
APPENDIX m
ASSEMBLER DIRECTIVES AND INSTRUCTIONS
RAMStart
ROMStart
V ectors tart
EQU
EQU
EQU
S0080
SF600
SFFFE
;Valid for all JL3, JK3, JK1
IDLoc
PIN
PORT
EQU
EQU
EQU
SFBF8
6
50003
location to store the tag’s ID code
;set output pin
;set output port / memory location
ORG
DW
VectorStart
Start
ID3
ID2
101
ORG
FDB
FDB
FDB
IDLoc
S6A7B
S49D2
S0135
;store the upper 2 bytes
through....
IDO
FDB
SFEC8
;thc lower 2 bytes o f the tag’s ID c o d e
BY
Bl
D
ORG
RMB
RMB
RMB
RAMStart
1
1
1
;make room for 1 byte o f memory to track..
;...th e Byte o f the ID code. Bit o f each byte.
;...and counter o f the delay loop
ORG
MOV
CLRH
LDX
MOV
LDA
MOV
LSLA
BCC
BSET
BRA
BCLR
BSR
DBNZ
INCX
DBNZ
ROMStart
*S40,S0007
START
REPEAT
NXBY
SHL
SERI
SERO
SKIP
*SF8
#S8,BY
SFB00.X
« 8 ,B I
;Shift Left
SERO
PIN,PORT
SKIP
PIN,PORT
DELAY
BI,SHL
;output a SERial “ 1”
;output a SERial “0”
BY,NXBY
LDA
BSET
BSR
BCLR
BSR
DBNZA
BRA
#3
PIN,PORT
DELAY2
PIN,PORT
DELAY2
FINID
REPEAT
DELAY
LOOP
MOV
DBNZ
RTS
#SI3,D
D,LOOP
DELAY2
RTS
FINID
;NeXt Byte
;FINish the ID code, mark the end
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123
Now each section o f the code is analyzed to explain its function.
Note semicolons
denote comments in Assembly.
RAMStart
EQU
S0080
This command signifies that the start o f the RAM is at the address location S0080. This
particular microcontroller allocates RAM in the addresses $0080 to S00FF taking up 128
bytes.
ROMStart
EQU
SF600 ;Valid for all JL3, JK3, JK1 (suffix for microcontroller)
This command signifies that the start o f the ROM is at the address location SF600. This
particular microcontroller allocates ROM in the addresses SEC00 to SFBFF taking up
4096 bytes. The ROM is designated as “FLASH” memory.
VcctorStart
EQU
SFFFE
This command signifies that the start o f the Vector is at the address location SFFFE.
This particular microcontroller allocates user vectors in the addresses SFFDO to SFFFF
taking up 48 bytes. The location SFFFE points to reset vector (high). This means that
when the reset vector is high the program starts over (resets).
IDLoc
EQU
SFBF8
{location to store the tag’s ID code
This command signifies that the start o f the ID is at the address location SFBF8. Since
the end o f the ROM is at address FBFF, 8-bytes (64-bits) o f memory are available for
storing the ID code. Thus, the final byte o f the ID code is stored at the end o f ROM.
PIN
EQU
6
;set output pin
PORT
EQU
S0003
;set output port / memory location
These two commands operate in tandem to output the ID code to pin PTD6 on the 20-pin
microcontroller package. The I/O registers occupy 64 bytes o f memory from S0000 to
S003F. Memory location S0003 pertains to Port D Data Register (PTD). By setting the
variable PIN to 6, the output pin that produces the ID code is PTD6.
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124
ORG
VectorStart
DW
Start
This command prompts the microcontroller o f the start o f the main program.
ORG
IDLoc
ID3
FDB
S6A7B
;store the upper 2 bytes
1D2
FDB
S49D2
; ...through....
IDI
FDB
S013S
I DO
FDB
SFEC8
;the lower 2 bytes o f the tag’s ID code
These commands first tell the microcontroller to access the memory location IDLoc in
order to store ID3, ID2, ID I, and IDO. IDLoc occupies 8-bytes from SFBF8 to SFBFF
where the ID code is stored as 6A7B49D20135FEC8,6 = 0110 1010 0 1 11 1011 0100
1001 1101 0010 0000 0001 0011 0101 l l l l l l i o llOO 10002. A detailed explanation
o f the MCU’s numbering system is given in Appendix IV.
ORG
RAMStart
BY
RMB
I
;make room for I byte o f memory to track...
Bl
RMB
I
; ...the BYte of the ID code. B it o f each byte...
D
RMB
I
;...and counter o f the Delay loop
These commands tell the microcontroller to reserve the memory locations at S0080 to
S0082 in RAMStart for storing BY, BI and D. BY, BI and D act as flags to track the
byte o f the ID code, the bit o f each byte and the counter o f the delay loop explained later.
ORG
ROMStart
This command tells the microcontroller to access the memory location ROMStart.
START
MOV
#$4030007
This command stores the number 40t6 = IOOOOOOt at the memory location S0007. The
location S0007 pertains to the Data Direction Register D (DDRD) I/O register. The
DDRD determines whether each port D pin is an output or an input. Writing a logic one
to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero
disables the output buffer. Thus $40 enables pin 6 (PTD6).
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125
CLRH
This command clears the index register H.
REPEAT
LDX
#SF8
This command loads the number F8i6 = 111IOOO2 = 24810 into the index register X.
MOV
#S8,BY
This command stores the number 8i6 = IOOO2 = 8t0 as BY at $0080.
NXBY
LDA
SFBOO.X
;NeXt Byte
This command loads accumulator A with the contents at the address SFBOO + X’s
contents. For the first execution of this command X contains F8i6. Thus, A receives the
contents at address SFBF8 which is the first byte location o f IDLoc. The contents at this
location for the first execution of this command is the first byte o f the ID code or 6Ai6 =
0 1 IOIOIO2MOV
*S8,BI
This command stores the number 8t6 = IOOO2 = 810 as BI at $0081.
SHL
LSLA
;SHift Left
This command executes a logic shift left on accumulator A.
Before this command
accumulator A contained 0 1 IOIOIO2- After the shift the left most bit gets forced out of
the accumulator and becomes the “carry” bit. The right-most bit in the accumulator
becomes a 0 so that accumulator A now contains 1IOIOIOO2.
BCC
SERO
This command branches to SERO if the carry bit is clear. For the first execution o f this
command the carry bit is a 0. Thus the program branches to SERO. If the carry bit is a I,
the program will proceed to the next line o f code.
SERI
BSET
PIN.PORT
;output a SERial “ 1”
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126
This command sets the bit-position PIN (6) at the address location PORT (S0003) to a 1.
Thus, PTD6 has a I for an output.
BRA
SKIP
This command causes the program to branch to the subroutine SKIP.
SERO
BCLR
PIN,PORT
;output a SERial “0”
This command clears the bit-position PIN (6) at the address location PORT ($0003) to a
0. Thus, PTD6 has a 0 for an output.
SKIP
BSR
DELAY
This command causes the program to branch to the subroutine DELAY.
After the
execution o f DELAY, the program will come back to the next line.
DBNZ
BI,SHL
This command decrements BI so that now BI = BI - I and branches to SHL if BI * 0.
When this is first executed BI = 8l0 - 1 = 7\o- When the first 8-bits have been processed,
1.e. BI = 0, the program will proceed to the next line.
INCX
This command increments the X register by 1, i.e. X = X + I. For the first execution o f
this line X = 24910 = F9,6 = 1 1 1 1 10012.
DBNZ
BY,NXBY
This command decrements BY so that now BY = BY - I and branches to SHL if BY *
0. When this is first executed BY = 8to - I = 7I0. When BY * 0, the program branches
to NXBY where the contents o f SFBF9 are loaded into accumulator A. The contents o f
SFBF9 is the number 7B i6 which is the second byte o f the ID code. When the 8-bytes
located at IDLoc have been processed, i.e. BY = 0, the program will proceed to the next
line.
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127
The following 6 lines o f code create the three oscillations which signify the
beginning o f the 64-bit ID code.
LDA
FINID
BSET
#3
PIN,PORT
;FINish the ID code, mark the end
This command sets the bit-position PIN (6) at the address location PORT (S0003) to a I.
Thus, PTD6 has a 1 for an output.
BSR
DELAY2
This command causes the program to branch to the subroutine DELAY2.
After the
execution o f DELAY2, the program will come back to the next line.
BCLR
PIN,PORT
This command sets the bit-position PIN (6) at the address location PORT (S0003) to a 0.
Thus, PTD6 has a 0 for an output.
BSR
DELAYS
This command causes the program to branch to the subroutine DELAY2.
After the
execution o f DELAY2, the program will come back to the next line.
DBNZA
FINID
This command decrements accumulator A by I and branches to FINID if A * 0. After
three decrements A = 0 and the program proceeds to the next line.
An arbitrary output frequency o f 32.768 kHz corresponding to a period of
30.5175 ps has been chosen as the data rate for the ID code. Three oscillations have
been included in the coding to mark the beginning and end o f the 64-bit code. These
three oscillations have bits that are one tenth as long as an ID code bit. When a 16 MHz
external clock is used to generate an internal clock, the CPU clock has a frequency o f 8
MHz. One cycle for an instruction is equal to two CPU periods. Thus 1 cycle = 2 CPU
periods = 2 (8MHz)‘l = 2 (125 ns) = 250 ns.
For the pulsed sequence between
repetitions o f the ID code, the time for each bit is one tenth o f the desired ID bit rate or
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128
time = 3.05175 ps = 3051.75 ns x (I cycle / 250 ns) = 12.207 cycles = 12 cycles. Each
instruction can require a different number o f cycles as shown in Table A3.
Table A3. Cycle Time for Triple Oscillation Delay.
Cycles
Code
4
4
4
BSET
BSR
RTS
DELAY2
PIN,PORT
delay:
The total time for a single bit o f the triple oscillation is 12 cycles.
BRA
REPEAT
This command branches to repeat where the whole process o f outputting the 64-bit ED
code to PTD6 is repeated.
The following three commands execute the delay necessary for reducing the data
rate.
DELAY
MOV
#S13,D
DELAY stores the number 1316 = 19io = 100112 at the RAM address D (S0082).
LOOP
DBNZ
D,LOOP
LOOP decrements the number at the RAM address D ($0082) and branches to LOOP as
long as the number does not equal 0.
Thus the microcontroller decrements 19 times to
use a certain amount o f time. The delay is based on the following theory.
An arbitrary output frequency o f 32.768 kHz corresponding to a period of
30.5175 ps has been chosen as the data rate for the ID code. Three oscillations have
been included in the coding to mark the beginning and end o f the 64-bit code. These
three oscillations have bits that are one tenth as long as an ID code bit. When a 16 MHz
external clock is used to generate an internal clock, the CPU clock has a frequency o f 8
MHz. One cycle for an instruction is equal to two CPU periods. Thus 1 cycle = 2 CPU
periods = 2 (8M Hz)'1 = 2 (125 ns) = 250 ns.
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129
Since the desired output period is much longer than the amount o f time for a
single cycle, the aforementioned delay loop is included. Each instruction can require a
different number o f cycles as shown in Table A4.
Table A4. Cycle Time for Data Rate Delay
Code
Cycles
l
3
4
3
4
4
5
5
5
4
SHL
SERI
SERO
SKIP
DELAY
LOOP
LSLA
BCC
BSET
BRA
BCLR
BSR
DBNZ
MOV
DBNZ
RTS
SERO
PIN,PORT
SKIP
PIN,PORT
DELAY
BI,SHL
*S13,D
D,LOOP
Assuming that there are an equal number o f 0 and 1 bits in the ID code and including the
knowledge that the combined lines o f “SERI BSET PIN,PORT” and “SERO BCLR
PIN,PORT” will never both be executed, the length o f time for this section o f code is
time = 1 + 3 + 1 . 5 + 4 + 4 + 5 + 5 + (19 x 5) + 4 cycles = 27.5 + (19 x 5) cycles = 122.5
cycles = 122.5 cycles x 250 ns / 1 cycle = 30.625 ps. Thus, this section o f code gives the
desired 32.768 kHz output frequency with an extra 107 ns/bit as the shortest time
between bits. By varying the cycles through the delay loop(s), other output frequencies
are possible.
RTS
This command causes the program to return from the subroutine LOOP.
DELAY2
RTS
This command causes the program to return from the subroutine DELAY2.
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130
Assembler directives and instructions for the HC08-family are explained in the
following text. ‘A ’ refers to Accumulator, ‘X’ refers to the lower byte o f the Index
Register (X register) and ‘H ’ refers to the upper byte o f the Index Register (H register).
When a bit is set, it is forced to “ 1”, and, when a bit is cleared, it is forced to “0”.
Assembler Directives:
DW - Declare Word, stores the value in memory (similar to FDB)
EQU - EQUate, a variable is replaced by a constant in the code
ORG - ORiGinate, memory location to store the following code
FDB - Form Double Byte, stores the exact bytes in memory
RMB - Reserve Memory Byte, set aside RAM to be used later
Instructions:
BCC
label
•
Branch if Carry bit Clear
•
if Carry = 0 then branch to label
bit-position, location
BCLR
•
Bit CleaR in memory
•
force data bit-position at address location to zero
BRA
label
•
BRanch Always
•
branch to label
BSET
bit-position, location
•
Bit SET in memory
•
force data bit bit-position at address location to one
BSR
'label
•
Branch to SubRoutine
•
store the current place o f the program and branch to label
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131
CLRH
» CleaR the H register
► H=0
variable, label
DBNZ
► Decrement and Branch if Not equal Zero
► variable = variable - I; if variable * 0 then branch to label
DBNZA
label
» Decrement and Branch if Not equal Zero, operated on the
Accumulator
» A = A - I; if A ^ 0 then branch to/afee/
INCX
•
INCrement the X register
•
X= X+ 1
LDA
offset, X
LDA
value
•
LoaD Accumulator
■ A = data located at the memory address computed by the contents
o f the Index Register + offset
•
LDX
A = value
value
•
LoaD X register
•
X = value
•
Logical Shift Left, operated on the Accumulator
•
Carry = left-most bit o f the A, shift the A’s bits to the left one bit-
LSLA
position, and force the right-most bit to zero
MOV
value, variable
•
MOVe
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132
•
store data value at memory location variable
•
ReTum from Subroutine
RTS
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133
APPENDIX IV
NUMBERING SYSTEMS FOR THE MICROCONTROLLER
Base ten or decimal is the most commonly used numbering system. The decimal
number 463 is understood as 463 = 4 x 100 + 6 x 10 + 3 = 4 x 10" + 6 x 101 + 3 x 10°. If
multiple numbering systems are used, the number’s base follows the value as a subscript,
i.e. 463io. Computer related calculations are often executed using binary (base 2) and
hexadecimal (base 16). The ten unit values making up the decimal numbering system
are 0 through 9. Binary has two values or 0 and 1. Similarly, hexadecimal has sixteen
numbers including 0 through 9 as well as A through F. Some number constructs of
binary and hexadecimal are 1101i = 1
x
23 + I
x
22 + 0
x
2i + 1 x 2 ° = I
x
8 + 1
x
1 = I 3l0 and C 7l6 = C x I6 l + 7 x 16° = 12 x 16 + 6 = 199l0.
Table A5. Numbers in Relevant Bases
D ecim al
B in a ry
E x ten d ed B in a ry
0
0
0
0000
1
1
I
0001
2
2
10
0010
3
3
11
0011
4
4
100
0100
5
5
101
0101
6
6
110
0110
7
7
111
0111
S
H exad ecim al
8
1000
1000
9
9
1001
1001
A
10
1010
1010
B
11
1011
1011
C
12
1100
1100
D
13
1101
1101
E
14
1110
1110
F
15
1111
1111
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4 + 1
x
134
A summary o f relevant numbers is given in Table A5 with ‘Extended Binary’
extending the binary numbers to four digits. A bit corresponds to a single binary digit,
and a byte corresponds to eight bits.
A hexadecimal digit corresponds to four bits;
therefore, one byte is represented by two hexadecimal digits.
The microcontroller uses additional characters to distinguish numbers. Numbers
with a “$” prefix are hexadecimal and numbers with no prefix should only be used when
the number can be equally represented in both base 16 and base 10 (0 through 9). In
addition, computers need to distinguish between addresses and data at a given address
where a byte o f data is stored. Numbers with a “#” prefix are data and numbers without
this prefix are addresses.
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135
APPENDIX V
RFID SAFETY ANALYSIS
This section investigates the safety aspects o f the RFID link in terms o f the safe
distance that personnel can be located under broadside interrogation. The FCC limits on
Maximum Permissible Exposure (MPE) is presented in Fig. A6.
1.000.
Occupational/Controlled Exposure
General Population/Uncontrolled Exposure
100
u
5
0.2
0.03
0.3
300
1.34
Frequency (MHz)
3.000
30,000
1500
300.000
100.000
Fig. A6. Plane wave power density versus frequency with FCC MPE limits.
For the range o f frequencies around 5.8 GHz, the FCC MPE for uncontrolled exposure is
1 mW/cm2. In the RFID measurement test, a 15.3 dB at 5.8 GHz hom was used to
interrogate the tag. The safe distance for standing in the broadside path o f the antenna is
found from the formula for power density or
PG
47ZS
(A3)
where Pt and Gt are the transmit power and gain o f the hom, respectively. The distance s
is the distance between the hom and personnel assuming broadside interrogation.
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136
Curves showing the plane wave power density versus s for various source powers are
presented in Fig. A7.
10
1--------1------- 1------- r
P = 46 dBm
P =40 dBm
P = 30 dBm
.../>,= 35 dBm
Fig. A7. Power density Pa versus distance s away from 15.3 dB radiating source for
various transmit power levels Ps.
Using the 40 W (46 dBm) amplifier available in the Electromagnetics and Microwave
Laboratory, an individual must be located at least 10 feet to meet MPE requirements for
safe exposure. Using the 7W (38 dBm) amplifier, one must be around 5 feet away.
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137
APPENDIX VI
WIDEBAND DC-BLOCK MICROSTRIP CYMBAL BANDPASS FILTER
Most bandpass filters use end-coupled or parallel-coupled lines. These filters
usually require several sections to have a return loss o f better than 20 dB [SI]. Each of
the resonant sections is separated by a gap. Reducing this number o f gaps would result
in lower loss as well as lessen the chance o f error in the design or etching o f the filter.
Such errors can greatly affect the operating frequency and return loss o f bandpass filters.
The smallest width and gap o f the proposed filter are much greater than the etching
tolerances.
This new filter utilizes two coupled triangular-shaped microstrip patch
resonators [A2], [A3] in a parallel-cascaded geometry [A4], [A5].
The microstrip
patches have lower conductor loss than the end- and parallel-coupled designs allowing
for greater power handling at the expense o f being slightly larger in size.
H
Port 1
Port 2
Fig. A8. Bandpass filter schematic and its test fixture.
A series o f equations were derived from electromagnetic simulation curves to
facilitate the design and govern the filter’s behavior. These equations can be used as the
design guidelines.
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1.5
2
2.5
3
L (mm)
Fig. A9. IE3D simulated resonant frequency versus L for various W when er = 10.8 and
H = 0.635 mm.
The filter design was done using the full-wave EM simulator IE3D [7].
Every
dimension o f the filter shown in Fig. A8 was varied in order to formulate design
equations that predict the filter’s center frequency and to determine the minimum return
loss.
Fig. A9 illustrates the effects o f different W and L on the resonant frequency.
Based on these curves, IT determines the center frequency by
(A4)
where W is in meters, c is the speed o f light (3 x 108 m/s), er is the substrate dielectric
constant, and the center frequency / is in Flz. The dimension L in meters is chosen to
provide the lowest return loss by the equation
(A5)
where the center frequency / i s in Hertz, c is the speed o f light in m/s and L and W are in
meters.
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139
The following ratio is used to yield G for the L determined in Equation (A5).
£ .5
(A6)
This ratio provides the gap needed to achieve the best return loss characteristics.
Equations (A4) through (A6) determine all o f the filter’s dimensions. These dimensions
should produce a filter with an insertion loss around 0.5 dB and a return loss better than
20 dB at the desired center frequency.
The thickness o f the substrate H has little effect on the filter’s resonant
frequency, but does play a role in determining the filter’s bandwidth as illustrated by Fig.
A 10. This figure shows the simulated S-parameters for a filter with W = 11.6 mm, L =
1.83 mm, G = 0.37 mm, and er = 10.8 as determined by (A4) through (A6).
As H
increases so does the filter’s bandwidth. The optimal bandwidth o f the filter at 10 GHz
is around 10%.
-10
S „ . H = 20mil
S j,, H = 20 mil "
5 ... H = 25 mil :
to -2 5
-30
5 ... H = 25mil !
S „ . H = 31 mil i
S jt. H = 3 1 mil ;
-3 5
-40
7
8
9
10
11
12
13
Frequency (GHz)
Fig. A10. IE3D simulated S-parameters for different substrate thickness H. W - 11.6
mm, L = 1.83 mm, G = 0.37 mm, and
= 10.8.
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140
Unlike the substrate’s thickness, changes in its dielectric constant greatly affect
the operating frequency.
The design equations take into account different dielectric
constants. Fig. A 11 shows the simulated S-parameter curves for three different filters on
different substrates.
Since changing the dielectric constant changes the resonant
frequency, different tv's, determined by (A4) through (A6), are used for each filter in
order for all o f the filters to resonate at 10 GHz.
-10
-30
-3 5
-4 0
7
8
10
9
11
12
13
Frequency (GHz)
Fig. A 11. IE3D simulated S-parameters for different substrate dielectric constants when
H = 25 mil. When £r = 8, W= 13.5 mm, L = 2.12 mm, and G = 0.42 mm. When er = 10,
W = 12.1 mm, L = 1.9 mm, and G = 0.38 mm. When er = 12, W = 11 mm, L = 1.73 mm,
and G = 0.35 mm.
The electromagnetic simulator IE3D shows all o f the filters to be resonant at 10
GHz proving the validity o f the design equations for changes in the dielectric constant.
Similar IE3D analysis for changes in the filter’s dimensions and substrate dielectric
constant was carried out at both 5 and 15 GHz. IE3D proved the effectiveness o f the
design equations at both these frequencies.
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141
Fig. A12 shows measured and simulated S-parameter curves for a filter with W=
11.6 mm, L = 1.83 mm, G = 0.37 mm, H = 0.635 mm, and er = 10.8. Note that W/L =
6.35 and L/G = 5 were used as specified by the design guidelines in (A5) and (A6).
Using our design (A4), these dimensions compute a resonant frequency o f 10 GHz. The
IE3D electromagnetic simulation accurately predicts the filter’s behavior. Using an HP
851OB measurement system, the filter’s insertion loss is measured to be 0.5 dB, and the
return loss is measured at around 25 dB at 10 GHz. The filter’s return loss curve clearly
shows the two-poles o f the filter’s coupled resonators.
The filter’s measured results
yield a 2:1 VSW R bandwidth o f around 10%. Also shown in Fig. A12 is the 0.6 dB
insertion loss o f a C08BLBB1X5UX dc-block chip capacitor manufactured by Dielectric
Laboratories. The insertion loss o f the filter is slightly lower than that o f the lumped
capacitor, and has the advantages o f having bandpass characteristics.
o
5
-10
f -15
CO
I -20
a -25
S „ . simulated r
30
S2t. simulated
S ,,, measured S2I. measured
-35
S2), capacitor measured
-4 0
7
8
9
10
11
12
13
Frequency (G H z)
Fig. A12. Measured and simulated S-parameter curves for W = 11.6 mm, L = 1.83 mm,
G = 0.37 mm, H = 0.635 mm, and er = 10.8.
A curve representing the measured
insertion loss o f a chip capacitor is also shown.
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142
APPENDIX V n
LOW LOSS, COMPACT STRIPLINE BAND STOP FILTER
This appendix describes a stripline band stop filter has been designed to pass 18.8
to 2 1.2 GHz with better than 0.5 dB insertion loss and better than 15 dB return loss. The
filter also blocks 27 to 31 GHz by more than 27 dB except for a spike at 28.2 GHz. The
filter, etched on 31 mil Duroid with er = 2.33, is constructed in stripline to achieve low
loss and for easy fabrication. The filter has a small size o f 2.66 mm x 1.57 mm x 4.58
mm.
The shape and performance of microwave filters varies greatly. These filters are
manufactured using a variety o f transmission lines such as microstrip, coplanar stripline,
coplanar waveguide, and stripline.
Unlike the first three types o f transmission lines
mentioned, stripline does not have losses due to radiation. This is due to the fact that the
stripline structure contains the electromagnetic fields between two metal plates. These
metal plates are seen in the filter layout shown in Fig. A13 and are represented by the 5
mm thick aluminum sections. Since, there are no radiative losses, the stripline filter
presented achieves very low loss. Since the circuit is sandwiched by the two substrates
and metal blocks, no additional cover or packaging is required.
Size is another consideration in the design o f the filter.
Different filter
architectures are analyzed to determine which shapes produce the best performance
while maintaining small size. Many o f the classic lowpass filters afford low passband
loss, but they cannot meet the cutoff requirements unless many filter sections are present.
By adding more sections, not only does the size become too large, but the loss increases
as well. Numerous bandpass filters were also looked at such as the parallel line and
parallel-coupled designs. These filters provide better isolation in the rejection band than
that o f the lowpass, but also create more passband loss due to the presence o f gaps in the
filters. The alternative to both the lowpass and bandpass filters is to use a filter with
periodically spaced quarter-wavelength stubs [50]. The stubs generate the rejection band
and have low loss in the passbands.
Not many stubs are needed to achieve good
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143
isolation in the rejection band. This makes it ideal when small size is a requirement as it
most often is.
0.88 mm 0.88 mm
Aluminum
Aluminum
Fig. A13. (a) Planar top-view o f the metallization and its dimensions, (b) Equivalent
circuit model with open-ended stubs represented by series RLC resonators, (c) 3-D view
o f the stripline filter and its aluminum housing.
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144
The layout o f the stripline filter is shown in Fig. A13. The filter uses quarter
wavelength balanced stubs to achieve band stop characteristics. In microstrip circuits,
the guided wavelength is defined in terms o f s eg -; however, in the case o f stripline and
other symmetric transverse electromagnetic structures, se^ - s r [51].
The filter has four stubs o f length £ = 1.46 mm and Za = 105 Q.Assuming that m
= 1, the resonant frequency ( f ) for these stubs is f r =
c
j = = 33.6 GHz. The two
longer stubs o f length £ = 1.86 mm and Z 0 = 105 Q have a resonant frequency
fr = 26.4GHz
when m = I. The different stub lengths widen the rejection band and
match the various 50 and 65 Q transmission lines to one another.
Using (86) through (88), Ri = R} = 0.6 Q, Z,/ = Z.j = 0.17 nH, and C/ = Cj = 0.13
pF when a = 6 dB/andf r = 33.6 GHz. Similarly, R i = 0.8 Q, L i ~ 0.21 nH, and C> = 0.17
pF assuming a - 6 dB/m and f r = 26.4 GHz. These resonate RLC networks provide
short circuits to the main line in order to block the microwave energy at the desired
frequencies.
Using more stubs will create sharper cutoff frequencies and greater
isolation in the rejection band at the expense o f greater passband losses.
The 3-D layout o f the stripline filter is presented in A13. The filterisetched 31
mil Duroid with s r = 2.33.
A top layer o f the same Duroid is placed on top o f the
etched piece to fabricate the stripline circuit.
An Aluminum housing is then placed
around the filter to press the Duroid pieces together and expel any air that was trapped
between the different layers.
The filters dimensions are determined using the full wave electromagnetic
simulator IE3D [39]. IE3D’s simulated performance o f the filter is shown together with
the filter’s measured data in Fig. A14. Fig. A14 shows close agreement between the
simulated and measured data.
Differences between the two are due to slight
uncertainties inherent in the TRL calibration used to acquire the measured data and also
due in part to the dielectric/air interfaces at the edges o f the filter for which IE3D does
not account for.
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145
S11 measured H
S21 measured U
S11 simulated
S21 simulated
-10
w
09
E
2
-10
■45
-50
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Frequency (GHz)
Fig. A 14. Simulated and measured performance o f the stripline filter. The passband is
18.8 to 2 1.2 GHz, and the rejection band is 27 to 31 GHz.
The worst loss in the passband (18.8 GHz - 21.2 GHz) is 0.5 dB at 19.3 GHz,
and the return loss is better than 15 dB. The center o f the passband is located at around
20 GHz. The stubs collectively reject 27 GHz to 3 1 GHz by more than 25 dB.
In order to minimize dispersion, the signal time delay o f the frequencies o f
interest must be equal [50]. The energy o f the frequencies in the passband must flow
from port I and reach port 2 at approximately the same time. The signal time delay ( r)
sometimes referred to as the group delay from port I to port 2 is shown in Fig. A15. The
time delay is fairly constant in both the passband and rejection band regions with a
maximum delay difference in the passband o f about 1.5 ns. This constant time delay for
the pass bands is caused by the imaginary portion o f the propagation constant being an
almost linear function o f frequency. This results in minimal dispersion.
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146
1.5
Rejection Band
Passband
0 .5
C
>>
<D
O
JS
|
-0 .5
18
20
22
24
26
28
30
32
F r e q u e n c y (G H z)
Fig. A 15. Measured time delay.
A stripline filter has been fabricated to provide less than 0.5 dB loss in the
passband while creating a rejection band with greater than 25 dB suppression. The
periodic stubs have inherent low loss performance and fabrication simplicity. The filter
is also very small in size (2.66 mm x 1.57 mm x 4.58 mm) excluding the additional
aluminum and the 7.34 mm feed lines.
Further considerations can be given to the edge effects o f the air dielectric
interface. Some o f the microwave energy is dispersed in the dielectric and travels to the
edges o f the filter’s structure. Minimal effects are noticed due to the 30 mm width o f the
stripline structure. However, a totally enclosed housing might be necessary in product
development.
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147
REFERENCES
[A1 ] F. Incropera and D. Witt, Introduction to Heat Transfer. New York: John Wiley &
Sons, Inc., 1990.
[A2] J. Hong and M. Lancaster, “Microstrip Triangular Patch Resonator Filters,” IEEE
MTT-S, pp. 331-334, 2000.
[A3] H. Kobeissi and J. Abdulnour, and M. Stubbs, “A CAD Technique for Filter
Applications with Arbitrarily Shaped Planar Patch Resonators,” Canadian
Conference on Electrical and Computer Engineerin., vol. I, pp. 261-263, 1995.
[A4] V. Osipenkov and S. Vesnin, “Microwave Filters o f Parallel-Cascade Structure,”
IEEE Trans. Microwave Theory Tech., vol. 42, no. 7, pp. 1360-1367, July 1994.
[A5] J. Hong and M. Lancaster, “Couplings o f Microstrip Square Open-Loop
Resonators for Cross-Coupled Planar Microwave Filters,” IEEE Trans. Microwave
Theory Tech., vol. 44, no. 12, pp. 2099-2109, December 1996.
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148
VITA
Bemd Herbert Strassner II was bom in Houston, Texas on August 20, 1973. In
May o f 1995 he received a Bachelor o f Science degree in electrical engineering from
Rose-Hulman Institute o f Technology in Terre Haute, Indiana, and, in December 1997,
he received his Master o f Science in electrical engineering from Texas A&M University.
Bemd worked for Lockheed-Martin at the Johnson Space Center during the summer
months o f 1992, 1993, and 1995 in the areas o f space shuttle navigational controls,
power systems, and communication systems, respectively. In the winter o f 1994, Bemd
worked for AgriLogic, Inc. on a global positioning system for optimizing crop rotation
and fertilization.
In the summer o f 1994, he worked at the University o f Hamburg-
Harburg in Harburg, Germany on microwave de-embedding processes assisting a
doctorial candidate. In the summer o f 1996, Bemd was employed at Sandia National
Laboratories in Albuquerque, New Mexico working on communication systems to be
used for nuclear weapon monitoring.
From January to September o f 1997, he was
employed again at Sandia National Laboratories to study the effects o f harmonic
terminations on power amplifier performance. After his stay at Sandia, Bemd has been
employed as a research assistant in the Electromagnetics and Microwave Laboratory at
Texas A&M University under the advisement o f Dr. Kai Chang. His present research
includes radio frequency identification for oil drillstrings, circular rectifying antennas for
space solar power applications and reflecting antenna arrays. Bemd Strassner’s present
address is 10700 Academy Road NE #1912, Albuquerque, New Mexico, 87111.
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