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Development of silicon germanium HBT's and micromachined passive components for monolithic microwave integrated circuits

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DEVELOPMENT OF SiGe HBT’S AND MICROMACHINED
PASSIVE COMPONENTS FOR MONOLITHIC
MICROWAVE INTEGRATED CIRCUITS
by
Liang-Hung Lu
A dissertation submitted in partial fulfillment
o f the requirements for the degree of
Doctor o f Philosophy
(Electrical Engineering)
in The University o f M ichigan
2001
Doctoral Committee:
Professor Pallab Bhattacharya, Co-chair
Professor Linda Katehi, Co-chair
Professor Erdogan Gulari
Research Scientist Saeed M ohammad!
D octor George Ponchak
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UMI N um ber: 3001000
Copyright 2001 by
Lu, Liang-Hung
All rights reserved.
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Liang-Hung Lu
All Rights Reserved
2001
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To my parents
ii
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ACKNOWLEDGMENTS
First o f all, I would like to thank my advisors Prof. Linda Katehi and Prof. Pallab
Bhattacharya. W ithout their support, guidance and encouragement, I might have not
reached this far. I would also like to thank my committee members Prof. Gulari, Dr.
Saeed Mohammadi and Dr. George Ponchak for their comments and suggestions on my
thesis.
My special thanks should go to Dr. Jae-Sung Rieh. As a mentor for my Ph. D
research, his perseverance and enthusiasm for work has always been a stimulation for me.
A significant portion of the thesis has been achieved based on extensive cooperation with
him.
I am very grateful to my former and current colleagues, especially Dr. Katherine
Herrick, Dr. J. D. Shumpert, Dr. Kyoung Yang, Sergio Pacheco and James Becker for
their friendship and precious suggestions. In addition, I extend my thanks to all the
members o f the TICS Lab and SSEL Lab for making the working environment an
enjoyable one.
Dr. Cheng-Hui Lin and Dr. Yu-Ting Cheng deserve great gratitude for their
friendship and help during my stay in Ann Arbor. I would also like to thank all my
friends who support me and encourage me for the past few years.
The SiGe MMIC project was funded by NASA/JPL under contraction 961358. I am
very thankful to Dr. E. T. Croke and Dialmer-Chrysler Research Center for the epitaxial
growth of SiGe HBT structures.
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I would like to express my sincere appreciation to my brothers Liang-Chi and LiangMing. Throughout m y life, they have always been there for me when I need them. M ost
importantly, my deepest gratitude is reserved for m y parents. W ithout their devoted love,
encouragement and support, I could not have fulfilled the dream of pursuing m y Ph. D.
degree.
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TABLE OF CONTENTS
D E D IC A T IO N ................................................................................................................................. ii
A C K N O W L E D G M E N T S ...........................................................................................................in
L IS T O F F IG U R E S ....................................................................................................................viii
L IST O F T A B L E S ....................................................................................................................... xii
CHAPTER
I.
IN T R O D U C T IO N .......................................................................................................... 1
H.
D E V E L O P M E N T O F H IG H -S P E E D AND L O W -P O W E R SiGe
H B T ’S ................................................................................................................................ 6
2.1 Introduction................................................................................................................ 6
2.2 Fundamental Principles of SiGe H B T Operation.................................................6
2.3 Design o f SiGe HBT Structure................................................................................ 8
2.3.1 Substrate......................................................................................................... 8
2.3.2 Subcollector layer......................................................................................... 9
2.3.3 Collector layer...............................................................................................9
2.3.4 Base lay e r.....................................................................................................12
2.3.5 Spacer layers................................................................................................ 15
2.3.6 Em itter layer................................................................................................ 15
2.3.7 Em itter cap lay er.........................................................................................16
2.3.8 Epitaxial growth of the heterojunction structure.................................. 16
2.4 Fabrication of SiGe HBT’s..................................................................................... 18
2.5 D C and RF Characteristics of the SiGe H B T’s ..................................................20
2.5.1 D C characteristics.......................................................................................20
2.5.2 RF characteristics.......................................................................................23
2.6 S u m m ary ...................................................................................................................25
HL
D E V E L O P M E N T O F M U L T I-F IN G E R SiG e P O W E R H B T ’S ..................26
3.1 Introduction.............................................................................................................. 26
3.2 Design o f M ulti-Finger SiGe Pow er H B T’s....................................................... 27
3.2.1 Vertical design of power H B T structure............................................... 27
3.2.2 Layout design of multi-finger devices....................................................30
3.3 Fully Self-Aligned Technology for M ulti-Finger HBT D evices.................... 32
3.4 D C Characteristics................................................................................................... 37
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3.5 RF Characteristics and Small-Signal Equivalent Circuits................................38
3.6 Pow er Performance and Large-Signal M odeling o f the Power
D ev ices.................................................................................................................. 43
3.7 S u m m ary.................................................................................................................. 46
IV. MICROMACHINED TECHNOLOGY FOR MICROWAVE
LUMPED PASSIVE COMPONENTS............................................................... 49
4.1 Introduction..............................................................................................................49
4.2 Implementation of Thin-Film R esistors.............................................................. 50
4.3 Implementation o f Capacitors...............................................................................52
4.3.1 Interdigitated capacitors........................................................................... 53
4.3.2 Metal-insulator-metal (MIM) capacitors............................................... 54
4.4 Implementation o f MMIC Inductors....................................................................57
4.4.1 Spiral inductors..........................................................................................57
4.4.2 M icromachined structure for spiral inductors...................................... 60
4.4.3 Experimental results.................................................................................. 62
4.5 Fabrication Technology for the M icromachined Passive Components
64
4.6 S u m m ary.................................................................................................................. 6 6
V.
MICROWAVE PASSIVE INTEGRATED CIRCUITS USING
MICROMACHINED LUMPED COMPONENTS..........................................67
5.1 Introduction..............................................................................................................67
5.2 Lum ped Equivalent Networks for Transmission Line Segm ents................... 6 8
5.3 W ilkinson Power D ividers.................................................................................... 69
5.3.1 Analysis of Wilkinson power dividers...................................................70
5.3.2 Design o f lumped Wilkinson power dividers....................................... 72
5.3.3 Experimental results and discussion...................................................... 73
5.4 Quadrature (90°) Hybrids.......................................................................................76
5.4.1 Analysis of quadrature (90°) hybrids..................................................... 77
5.4.2 Design o f lumped quadrature (90°) hybrids..........................................80
5.4.3 Experimental results and discussion...................................................... 82
5.5 180° H y b rid s............................................................................................................8 6
5.5.1 Analysis of 180° hybrids.......................................................................... 8 6
5.5.2 Design o f lumped 180° hybrids............................................................... 87
5.5.3 Experimental results and discussion...................................................... 8 8
5.6 S u m m ary .................................................................................................................. 91
VI. DESIGN AND FABRICATION OF Si-BASED MONOLITHIC
MICROWAVE INTEGRATED CIRCUITS.....................................................93
.1 Introduction..............................................................................................................93
6.2 Fabrication Technology for Si-based M M IC’s ..................................................94
6
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6.3 A m plifier Design and Implementation................................................................. 95
6.3.1 Small-signal analysis for amplifier d e s ig n ............................................ 96
6.3.2 Implementation o f single-stage am plifier.............................................. 97
6.3.3 Implementation o f two-stage a m p lifier..................................................99
6.3.4 Implementation of three-stage am plnfier..............................................101
103
6.4 Design o f X-band Oscillators.........................
......................................................104
6.5 Design o f SiGe HBT Power Am plifiers
6 . 6 S u m m ary .......................................................... - .....................................................109
v n . CONCLUSIONS AND SUGGESTIONS F O R FUTURE
RESEARCH........................................................
7.1 C onclusions......................................................
7.2 Suggestions for Future R esearch...................
I ll
Ill
114
BIBLIOGRAPHY................................................................................................................116
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LIST OF FIGURES
F igure
2.1
Epitaxial structure of SiGe HBT’s for high-speed and Iow-power
applications..................................................................................................................... 17
2.2
Fabrication process flow of the double-mesa SiGe H B T ’s .................................... 19
2.3
(a) Schematic cross section o f the fabricated SiGe HBT. (b) Photo­
micrograph o f the fabricated common-emitter SiGe H B T with em itter
area o f 5x5 Jim 2 .............................................................................................................. 20
2.4
I-V characteristics of the SiGe HBT (A e = 5x5 p.m2) .............................................21
2.5
Gummel plot o f the SiGe HBT (A e = 5x5 Jim2) ......................................................22
2.6
Frequency response o f the SiGe HBT (A e = 5x5 Jim2) with DC bias Ic =
7 mA and VCE = 4 V ...................................................................................................... 24
2.7
Bias dependence o ffmax for the SiGe HBT (Ae = 5x5 Jim2) .................................25
3.1
(a) Epitaxial structure o f SiGe HBT’s for power applications, (b)
Secondary ion mass spectrometry (SIMS) analysis p ro file ...................................29
3.2
Layout o f the 10-finger common-emitter SiGe H B T..............................................31
3.3
Base/subcollector exposure using selective KOH etch, (a) Photo­
micrograph. (b) Schematic cross section....................................................................33
3.4
Self-aligned base/collector metalization. (a) Photomicrograph, (b)
Schematic cross section................................................................................................ 34
3.5
Fabrication process flow of the fully self-aligned SiGe H B T’s ........................... 35
3.6
Photomicrograph o f the fabricated 10-finger common-emitter dev ice.............. 36
3.7
Schematic o f the multi-finger devices with isolated pads for em itter
contacts.............................................................................................................................36
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3.8
I-V characteristics o f the fabricated multi-finger SiGe HBT (A e =
2x2x30 pm 2) ..................................................................................................................37
3.9
Gummel plot of the fabricated multi-finger SiGe HBT (A e = 2x2x30
pm 2) ..................................................................................................................................38
3.10 Frequency response o f the fabricated multi-finger SiGe HBT (A e =
2x2x30 p m 2) with DC bias Ic = 28 mA and Vce =
6
V ......................................... 39
3.11 The bias dependence of frequency response for the fabricated multi­
finger SiGe HBT (A e = 2x2x30 pm 2), (a) Fixed Ic = 28 mA. (b) Fixed
Vce = 6 V .........................................................................................................................40
3.12 T-model equivalent circuits and the extracted parameters for the
fabricated m ulti-finger SiGe HBT (A e = 2x2x30 pm 2) ......................................... 41
3.13 S-param eter characteristics from the small-signal equivalent circuit vs.
measurem ent...................................................................................................................42
3.14 M easurement setup for the load-pull system............................................................44
3.15 Power gain, output power and PAE of the 10-finger common-emitter
d ev ic e.............................................................................................................................. 45
3.16 Power gain, output power and PAE of the 10-finger common-base
d ev ice.............................................................................................................................. 45
3.17 Gummel-Poon model and the extracted parameters of the fabricated 10finger device...................................................................................................................47
4.1
Photomicrograph and the equivalent circuit o f the thin-film resistors................ 52
4.2
The extracted resistance of the thin-film resistors with varying geom etry
4.3
Photomicrograph and the equivalent circuit of the interdigitated
53
capacitors.........................................................................................................................55
4.4
The extracted quality factor of the interdigitated capacitors with various
finger num bers................................................................................................................55
4.5
Photomicrograph and the equivalent circuit of the M IM capacitors....................56
4.6
(a) The extracted capacitance and (b) quality factors of the MIM
capacitors.........................................................................................................................58
4.7
The design o f a rectangular spiral inductor............................................................. 59
4.8
The equivalent circuit o f the spiral inductors.......................................................... 59
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4.9
Photomicrograph o f the fabricated micromachined spiral inductor
(N=4.5)......................................................................................................................... 61
4.10 Potential etch profiles using a micromachined technology..................................61
4.11 The extracted Q-factor o f a 3.5 turn spiral inductor with various etch
depths............................................................................................................................63
4.12 The fabrication process flow for micromachined passive com ponents............ 65
5.1
A transmission line segment and its ABCD m atrix ..............................................69
5.2
(a) Lumped T network and its ABCD matrix, (b) Lum ped K network and
its ABCD m atrix ......................................................................................................... 69
5.3
Schematic o f an equal-split Wilkinson power d iv id er..........................................7 1
5.4
Even-odd mode analysis of the Wilkinson power d iv id er...................................71
5.5
Schematic and photomicrograph o f the lumped W ilkinson power
dividers, (a) X-band design, (b) K-band design.....................................................74
5.6
S-parameter measurement results of the lumped W ilkinson power
dividers, (a) X-band design, (b) K-band design.....................................................75
5.7
Schematic o f quadrature (90°) hybrids.................................................................... 81
5.8
Even-odd mode analysis of quadrature hybrids, (a) Even-mode
excitation, (b) Odd-mode excitation....................................................................... 81
5.9
Schematics and photomicrographs of the lumped quadrature hybrids, (a)
Design H 90_l. (b) Design H90_2. (c) Design H90_3. (d) Design H 90 _ 4 ....... 83
5.10 S-parameter measurement results for the lumped quadrature hybrids, (a)
Design H 90_l. (b) Design H90_2. (c) Design H90_3. (d) Design H 90_4....... 84
5.11 Schematic o f 180° hybrids (ring hybrids)................................................................87
5.12 Schematics and photomicrographs of the lumped 180° hybrids, (a)
Design H 180_l. (b) Design H180_2........................................................................89
5.13 S-parameter measurement results for the lumped 180° hybrids, (a)
Design H 180_l. (b) Design H180_2........................................................................90
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.1
6.2
The process flow for SiGe MMIC fabrication.......................................................95
(a) Schematic of the single-stage amplifier, (b) Photomicrograph of the
single-stage am plifier..................................................................................................98
6.3
S-parameter measurement results of the single-stage am plifier..........................99
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6.4
(a) Schematic o f the two-stage amplifier, (b) Photom icrograph o f the
two-stage am plifier....................................................................................................... 1 0 0
6.5
S-parameter m easurem ent results of the two-stage am plifier.............................101
6 .6
(a) Schematic o f the three-stage amplifier, (b) Photom icrograph of the
three-stage am plifier.....................................................................................................1 0 2
6.7
S-parameter m easurem ent results of the three-stage am plifier.......................... 103
6 .8
(a) Block diagram o f a two-port negative resistance oscillator, (b)
Schematic o f the X-band oscillator design............................................................... 105
6.9
Block diagram o f a balanced am plifier................................................................... 106
6 .10
Schematic o f the amplifying stage for the balanced am plifier desig n ..............107
6 .1 1
Schematic of the X-band balanced power am plifier with lumped passive
com ponents....................................................................................................................108
6.12
Simulated small-signal performance o f the balanced am plifier.........................108
6.13
Simulated pow er saturation curve of the balanced am plifier............................. 109
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LIST OF TABLES
Table
3.1
fir and f nuix o f the m ulti-finger devices in common-emitter and commonbase configurations........................................................................................................ 43
4 .1
Materials for thin-film resistors.................................................................................... 51
4.2
The equivalent circuit parameters of the fabricated thin-film resistors.................52
4.3
The equivalent circuit parameters o f the fabricated interdigitated
capacitors......................................................................................................................... 54
4.4
Frequently used materials for MIM capacitors......................................................... 55
4.5
The equivalent circuit parameters of the fabricated M IM capacitors...................58
4.6
The equivalent circuit parameters of the fabricated spiral inductors
(N =3.5).............................................................................................................................63
4.7
The Q-factor and the resonant frequency of the fabricated spiral
inductors.......................................................................................................................... 64
5.1
Lumped designs for equal-split Wilkinson power d iv id e rs .................................. 73
5.2
Circuit performance o f the lumped Wilkinson pow er dividers............................ 75
5.3
Lumped designs for the 3 dB quadrature hybrids................................................... 82
5.4
Circuit performance o f the lumped quadrature h y b rid s.........................................85
5.5
Lumped designs for the 180° hy b rid s....................................................................... 8 8
5.6
Circuit performance o f the lumped 180° hybrids.....................................................91
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CHAPTER I
INTRODUCTION
W ith the fast-growing markets in wireless communication, there is an increasing
demand for low-cost and high-performance microwave and millimeter-wave systems.
Recently, monolithic microwave integrated circuits (MMIC’s) have received increased
attention in applications such as cellular phones [l]-[ 6 ], global positioning systems (GPS)
[7][8 ], and automotive collision-avoidance radar systems. The idea of monolithic
integrated circuits was first proposed by Dummer in 1952 [9]. In the past, microwave
circuits were mostly implemented with a hybrid approach in which discrete components
are fabricated separately and then assembled on a dielectric substrate. On the other hand,
M M IC’s are microwave circuits where all active and passive components, as well as
interconnects, are fabricated on a single substrate by a sequence o f semiconductor
processing technologies. Compared with hybrid microwave circuits, M M IC’s exhibit
attractive features for modem communication systems. First, by utilizing a monolithic
approach, the components required in a microwave system can be integrated without
bonding pads and wire bonds, resulting in a smaller chip size and weight. Small chip size
allows a large number o f chips to be fabricated on a single wafer, and thus, the cost per
chip is reduced. Moreover, smaller chip size and less weight are also favorable in
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portable communication devices and air or space applications. Second, high-frequency
parasitics, which may limit the frequency response of the circuits, resulting from
interconnection and bond wires between discrete components in a hybrid system is
minimized. In addition, reduced parasitics enable both passive and active components to
be accurately characterized for circuit design, leading to a significant improvement in
circuit performance, especially
at higher frequencies. M oreover,
labor-intensive
processes such as assembling, wire bonding and characteristic tuning o f the devices are
no longer required. Consequently, more reliable and reproducible microwave circuits can
be implemented to fulfill the system requirements.
The choice of the substrate material is o f great importance for planar integration of
microwave circuits. The substrate m ust be mechanically stable as a carrier for the devices
fabricated upon it, as well as a Iow-loss dielectric for supporting transm ission lines.
Moreover, it must be technologically compatible with the fabrication process for both
active and passive components. The higher carrier mobility, saturation velocity and semiinsulating properties o f m -V compound semiconductors such as GaAs resulted in their
wide spread use for MMIC applications over the past few decades. T he first attempt to
fabricate Si-based MMIC can be traced back to the 1960’s [10]. Si has been a potential
candidate as a substrate material for MMIC applications due to its com patibility with
high-quality oxides, mechanical stability, high thermal conductivity, m atured processing
technology and lower manufacturing cost. Furthermore, monolithic integration of the Sibased microwave circuits with Si BiCMOS circuitry has also been strongly motivated in
order to realize the concept of system on a chip. However, the developm ent o f Si
monolithic microwave circuits has long been impeded by several obstacles, the m ost
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significant o f which are the absence o f a semi-insulating substrate and the inferior
frequency operation o f Si-based transistors.
Recently, these two shortcomings have been removed by the availability o f highresistivity Si substrates and the emergence o f high-quality SiGe epitaxial layers. W ith
advanced techniques in Si crystal growth and wafer preparation, the impurity
concentration can be well controlled, leading to Si substrates with a resistivity higher than
10 k£I-cm. As a result, the dielectric loss o f fabricated waveguide structures in
microwave circuit implementations is reduced significantly and becomes negligible with
regard to conductor loss [11]. On the other hand, recent advances in silicon-germanium
eptiaxial growth have led to high-quality SiGe/Si heterostructures and, consequently, to
high-performance Si-based heterojunction devices. For a SiGe heterojunction bipolar
transistor (HBT), a strained SiGe alloy is em ployed as the base layer. W ith the bandgap
discontinuity introduced by Si/SiGe heterojuctions, an extremely thin base with high
doping concentration is utilized to enhance the high-frequency characteristics o f the
devices. SiGe HBTs with cut-off frequency (ff) over 100 GHz [12] and maxim um
oscillation frequency (fmax) up to 160 GHz [13] have been reported, opening a possibility
for Si-based monolithic integrated circuits
for microwave and millimeter-wave
applications.
W ith the availability of high-resistivity substrates and high-performance microwave
transistors, there have been a number o f reports on successful implementation o f Si-based
M M IC’s. Recently, a 47 GHz oscillator [14] and monolithic voltage controlled oscillators
(VCO’s) with oscillation frequencies of 26 and 40 GHz [15] have been dem onstrated
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using SiGe H B T’s. In addition, X-band active mixers [16] and Ka-band MMIC amplifiers
[17] have also been implemented on Si substrate.
Although Si-based M M IC’s have been demonstrated using SiGe HBT’s, m ost o f the
circuits are designed with distributed passive components. Since the physical dimension
of a distributed design is proportional to the wavelength at the operation frequency, the
chip size becomes prohibitively large and drives M M IC costs higher, especially at
frequencies below 30 GHz. At lower frequencies, lum ped designs have been em ployed to
implement m icrow ave integrated circuits. However, due to the low quality factor (Q) and
low resonant frequencies (fres) of the lumped passive components, especially inductors,
these circuit dem onstrations have been confined to frequencies up to a few GHz [18] [19].
Use of sim ilar designs for M M IC’s at X-band to K -band frequencies requires highperformance lum ped components.
The m ain objective o f the research described in this thesis is to address the design and
technology issues o f SiGe HBT devices and lumped passive components for Si-based
MMIC implementation. The thesis consists of eight chapters. In chapter n , the principles
of SiGe HBT operation are studied in order to elucidate the design parameters o f the
epitaxial layers according to performance requirements. W ith a standard double-mesa
technology, SiGe H B T ’s for high-speed and low-power applications are demonstrated.
The development o f SiGe power HBT’s is described in chapter HI. In order to achieve
high output pow er and efficiency, the device design is suitably modified. In addition, a
multi-finger device layout and a novel process technology for the fabrication o f the fully
self-aligned m ulti-finger SiGe HBT’s are described. The fabricated devices are
characterized for D C, RF and high power operation. Chapter IV describes the studies
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directed towards the realization of microwave lumped passive components. W ith a
micromachined structure, a significant improvement in the quality factor and the resonant
frequency o f spiral inductors is achieved, leading to the use of lumped designs for
integrated circuits at microwave frequencies. The design and implementation of passive
microwave circuits are presented in chapter V. Coupler circuits such as Wilkinson power
dividers, quadrature hybrids and 180° hybrids have been demonstrated at X-band and Kband frequencies using the micromachined lumped components. In chapter VI, a process
technology for Si-based M M IC’s, integrating SiGe HBT devices with micromachined
passive components, is described. X-band monolithic multi-stage amplifiers, oscillators
and power amplifiers have been designed and demonstrated to complete this work.
Finally, chapter VII concludes the thesis, including suggestion for future work.
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CHAPTER II
DEVELOPMENT OF HIGH-SPEED AND
LOW-POWER SiGe H BT’S
2.1 Introduction
Heterojunction bipolar transistors in silicon technology have been extensively
investigated in the past few years due to the increasing demand for high frequency
electronics and wireless communications. By em ploying silicon/germanium alloys to
create a bandgap discontinuity, a thin base layer with high doping concentration can be
em ployed to improve high-frequency performance o f the devices, yet maintain a
reasonably high current gain. Recently, SiGe HBT’s with high cut-off frequency f r
[12][20]-[22] and m axim um oscillation frequency fmax [13][23] have been dem onstrated
for high-speed applications. Owing to its com patibility with advanced Si process
technologies, SiGe H B T ’s have become one o f the m ost promising candidates for Sibased MMIC applications.
2.2 Fundamental Principles of SiGe HBT Operation
A heterojunction is defined as a p-n junction form ed between two dissim ilar
semiconductors, and w as first studied by Shockley [24] in 1951. In a typical HBT design,
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the heterojunction has been created by selecting a wide bandgap material as the em itter
and a narrow bandgap material as the base. W ith the bandgap difference introduced by
the heterojunction, the carrier injection from base to em itter can be suppressed, leading to
a significant increase o f forward current gain p. Therefore, the constraints on the doping
concentration ratio and base width are lifted, and the device can be optim ized for high­
speed operations.
At 300° K the energy bandgaps of bulk Ge and Si are 0.66 and 1.12 eV, respectively.
Addition o f Ge results in a reduction of the bandgap o f Si. Therefore, SiGe alloys have
been widely used as the narrow bandgap material for the base layer in Si-based HBT
structures. W ith a lattice mismatch of 4.18 % between Si and Ge at room tem perature, the
SiGe alloy layer has to be confined below critical thickness such that the lattice is
accommodated elastically and no misfit dislocations are created. The resulting SiGe
layers are considerably strained. For growth o f strained SiGe alloys on (100) Si
substrates, the presence o f degeneracy in conduction band and valance band is lifted,
leading to splits o f 6 -fold degeneracy valleys. As a result, the overall bandgap shrinkage
of a strained SiGe layer is increased over that o f an unstrained one with the sam e Ge
mole fraction. The bandgap shrinkage resulting from strained Si[.xGex alloys at room
temperature is approximated by [25]
A £ /x ) = 0 .9 6 ;c -0 .4 3 ;c 2 + 0.17x3 (eV).
(2.1)
The bandgap difference AEg obtained from (2.1) is made up of a conduction-band offset
(AEc) and a valance-band offset (AEv), and how they are lined up at the heterojunction
has a crucial im pact on device performance. A ccording to Bean [25], AEv, which is
proportional to G e composition x, can be approximated as
7
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AEv (x) = 0.84x (eV).
(2.2)
It is noticeable the energy gap AEg appears principally as a valance-band step, resulting in
a situation o f considerable benefit for the formation o f n-p-n SiGe HBT’s.
2.3 Design of SiGe HBT Structure
For a heterojunction bipolar transistor, the design o f the epitaxial structure has a
significant impact on device performance. In order to optimize the performance o f an
HBT device, the alloy composition, thickness and doping concentration of each one o f
the layers have to be carefully designed based on the desired DC and RF operations. In
this section, the HBT structure is described starting with the substrate and built up a layer
at a time.
2.3.1 Substrate
The properties of the substrate are crucial to the epitaxial growth of any
heterojunction structure. In terms o f mechanical stability, thermal conductivity and
crystal quality, Si is favorable as the substrate material. However, the lack o f a sem iinsulating (high-resistivity) substrate has long impeded the progress o f Si-based
monolithic integrated circuits for microwave applications. With recent advances in Si
technology, substrates with a resistivity of the order of
104
Q-cm can be grown by float-
zone technology. W ith the availability of high-resistivity Si substrates, the dielectric loss
o f passive components such as transmission lines, inductors and capacitors, which are
integrated with active devices for circuit implementation, can be minimized and becomes
negligible compared with conductor loss at microwave frequencies. In this work, a 540
8
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(im-thick (100) Si wafer with a resistivity higher than 10 kQ-cm is employed as the
substrate for the fabrication o f the SiGe HBT devices.
2.3.2 Subcollector layer
In a vertical bipolar transistor, a buried n+ layer , called the subcollector, is frequently
added underneath the lightly doped collector to reduce both contact and access/spreading
resistance o f the device. For minimum device parasitics, a thick n-type Si layer with high
doping concentration is predominantly favored for the subcollector layer. However, the
resulting dopant out-diffusion and excessively large step heights may result in problems
for epitaxial growth and fabrication. The optimum doping concentration and thickness of
the subcollector layer have to be determined by taking into consideration device
performance as well as process reliability. To prevent step coverage problems during the
device fabrication, a maximum thickness o f 1.5 pm is chosen for the subcollector layer in
this design. With an n-type doping concentration of lx lO 19 cm-3, the estimated sheet
resistance o f the Si subcollector layer is 40 Q / n .
2.3.3 Collector layer
For a double heterojunction structure, an epitaxial Si layer is employed as the
collector layer. The device characteristics strongly influenced by collector design in a
bipolar transistor include maximum collector current density Jc,max, the base-collector
junction breakdown voltage BVCbo, base-collector junction capacitance Cbc and collector
depletion-layer transit time
Tc s c l -
Therefore, the thickness and doping concentration of
9
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the collector layer have to be determined based on performance requirem ent o f the HBT
device.
The maximum collector current density Jc.max o f a bipolar transistor is prim arily
limited by the Kirk effect which is defined as following [26]:
(2.3)
where vs is the electron saturation velocity, V cb is the collector-base voltage, and N c and
W c are the doping concentration and the thickness o f the collector layer, respectively. To
prevent base widening resulting from the Kirk effect, the collector doping concentration
N c has to be high enough such that the J k obtained from (2.3) is larger than Jc.max o f the
device.
Assuming an abrupt base-collector junction with lightly doped collector layer, the
breakdown voltage B V cbo can be expressed as
(2.4)
where E c is the critical field and £si is the perm ittivity o f Si. This expression implies that
the larger Wc, the larger BV cbo can be obtained for a fully depleted collector. As W c
exceeds a value o f
e
F
, the collector is no longer fully depleted, resulting in a
maximum junction breakdown voltage as
BVSB O,max
(2.5)
10
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As can be seen from (2.3) and (2.5), the product o f Jc.max and BVcBO,max is nearly constant
for a bipolar device. Therefore, a trade-off can be made in the collector design to
optimize the device in terms o f breakdown voltage and maximum operating current.
Another im portant consideration regarding collector design is the delay time related
to the collector region. To evaluate the high-speed operation o f a bipolar device, the total
emitter-collector transit tim e Tec is defined as [27]
~Z 7 ~ = Tec =
z.7UfT
■*" ^escl ^c -
( 2 .6 )
where Tg and Tb are the em itter delay and base transit time, respectively.
T c sc l
is the
collector depletion-layer transit time, which is given by
W
JUf
and Tc is the RC tim e constant for charging the base-collector capacitance as
BC
R E + Rc +
kT
^SjA-BC
Wc
kT
Re + Rc ^ ----4c
where Abc is the B-C junction area of the device. Both
(2.8)
Tc s c l
and Tc, which contribute as
part o f the total em itter-collector transit time, are strongly influenced by collector design
parameters. It is clear from the expressions that
Tc s c l
is proportional to W c while Tc is
inversely proportional to W c. Typically, Tc is small for a well-designed transistor and an
increase in collector thickness will eventually lead to the increase in Tec, and thus
decreasing cut-off frequency fir.
Therefore, the collector design procedure usually begins with the determination o f the
collector doping concentration with regard to the required
J c .m a x -
In the design o f low-
power devices, an H B T with em itter area o f 25 pm 2 is expected to operate at a m axim um
11
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collector current of 7 mA, leading to a
J c ,m a x
o f 28 kA/cm2. Based on (2.3), the resulting
collector doping concentration Nc is 5 x l0 15 cm '3. Then the collector width is optimized
on the basis o f the trade-off between the breakdown voltage and the operation speed of
the device. For a collector thickness of 3000
voltage
BV cbo
A,
the delay time Tcscl and breakdown
are estim ated 1.5 ps and 17 V , respectively.
2.3.4 Base layer
In a SiGe HBT structure, a Sii.xGex alloy layer is adopted as the base layer to create
the bandgap discontinuity at E-B and B-C junctions. Therefore, base design parameters
such as thickness
(W b),
doping concentration
(N b),
Ge composition (x) and its profile
play a cmcial role for device performance.
The frequency response o f an HBT device is strongly influenced by the base design.
The figures o f merit that are typically used to evaluate the high frequency behavior o f a
bipolar transistor are the cut-off frequency f r and maximum oscillation frequency f riax. f r
is defined as the frequency at which the current gain h.21 o f a transistor decreases to unity,
and an approximate expression for f r is given as (2.6). In (2.6), the base transit time Tb
which represents the average time per carrier spent in diffusion across the neutral base
region is given as [28]
W2
(2-9)
n v n,B
where the field factor
77
accounts for the effect of the induced quasi-electric field in the
base region. On the other hand,
is the frequency at which the unilateral power gain U
12
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decreases to unity, and it is widely used to estimate power gain o f a microwave transistor.
For bipolar transistors, a convenient approximate expression o f f max is
(2 - 10)
max
where
Rb
is the base resistance and
C bc
is the base collector junction capacitance. From
(2.9), it is obvious that a thin base layer reduces the base transit time, resulting in a high
f r o f a transistor. However, the base width can not be reduced too much as this will also
lead to problems such as base punchthrough and degraded f nmx due to the larger base
resistance.
Another im portant characteristic regarding the base design is the DC current gain of
the transistor. F o r a bipolar device operating in the active mode, the common-base
current gain (a) is defined as the product o f the em itter injection efficiency (y) and the
base transport factor (ax) [29]:
a = y -a T .
( 2 . 11)
Accordingly, the comm on-emitter current gain (3 is given by
(2. 12)
l-y D C r
In order to achieve high current gain, the base current components have to be minimized
with regard to the carrier injection from em itter into base. The two m ost important
components of the base current are carrier injection from base into em itter and
recombination w ithin the base. Since the form er is the predominant cause for base current
in most integrated circuit transistors, the current gain can be expressed as [30]
Dn,BWBN B(N cNv)
C
V 'E
E
(2.13)
kT
13
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In the above equation, DPie and D„,b are minority carrier diffusion constants in em itter
and base region, W e and N e are emitter thickness and doping concentration, and N c and
N v are effective density o f states of conductor and valence band, respectively, and
A Ev
is
the valance band offset voltage at the E-B junction. As can be seen from (2.13), an
increase o f Ge composition in the base layer, which enlarges the valance band offset
A Ev
between em itter and base, leads to a significant increase in current gain by suppressing
the injection o f holes from base to emitter.
In a typical SiGe HBT structure, AEv is designed to be large enough to ensure a
sufficiently high current gain, no matter what doping levels exist in the em itter and the
base. It allows a high doping concentration in the base and a relatively low doping
concentration in the emitter. Therefore, the thickness of the base layer can be further
reduced without suffering from problems such as base punchthrough and large base
resistance. As a result, the device benefits from its reduced parasitics and sm aller base
transit time, and a significant improvement i n / 7- a n d o f the device can be achieved.
However, the increase o f Ge composition also degrades the minority electron m obility in
the base region due to alloy scattering. It has to be taken into consideration for the choice
o f Ge composition in base design.
The base design starts with Ge composition and profile. A uniform Ge composition of
40% is chosen for the base layer, resulting in an estim ated valance band offset o f 0.34
eV. In order to optimize the high-frequency performance of the devices, the thickness and
the doping concentration o f the base layer are designed to be 200 A and 2 x 1 0 19 cm '3,
respectively. Based on the design parameters, the base transit time of the device is
estimated 1.2 ps and the SiG e base layer exhibits a sheet resistance of 2.5 k Q /D .
14
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2.3.5 Spacer layers
For an n-p-n SiGe HBT structure, boron is widely used as the in-situ doping species
for the base layer. During epitaxial growth, circuit fabrication and even circuit operation,
the boron tends to diffuse out o f the SiGe base region due to an increase of temperature,
moving the base-emitter junction toward the emitter. A common solution to the boron
outdiffusion problem is to insert unintentionally doped SiGe spacer layers at the E-B and
B-C heterojunctions. Insufficient spacer thickness will generate a parasitic barrier in the
conduction band due to boron outdiffusion, while excessively thick spacer layer will
deteriorate the heterojunction structure and result in degraded base contact for the device.
Therefore, the thickness o f the spacer layers has to be carefully chosen for optimum
device performance. In this design, unintentionally doped Sio.6 Geo.4 layers with a
thickness o f 50 A are adopted as spacers for the HBT structure.
2.3.6 Emitter layer
An n-type silicon layer is used for the emitter layer to ensure a large bandgap offset at
the emitter-base junction. The design parameters o f the em itter layer include the
thickness
(W e )
and the doping concentration
(N e ).
From (2.13), it is obvious that the
higher N e , the higher the current gain that can be achieved. However, high doping
concentration in the em itter region also increases the E-B junction capacitance
C be
and
decreases the junction breakdown voltage. Thus, in considering the frequency response of
the device, a thick emitter layer with low doping concentration is favored for smaller C b e
and Te based on (2.13).
15
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Therefore, a trade-off has to be made to optimize the em itter design with respect to
current gain, parasitic resistance and the device speed. As a result, a thickness of 1000 A
and a doping concentration o f 2 x l0 18 cm ' 3 are chosen for the em itter layer. According to
the device parameters, the current gain of the SiGe HBT’s can be estimated by (2.13),
and the resulting current gain o f this design is 150.
2.3.7 Emitter cap layer
Due to the exponential dependence of the current gain with respect to bandgap
difference in E-B junction, high emitter doping concentration is no longer required to
maintain a sufficiently high current gain of an HBT device. In this case, an excessively
thick emitter layer should be avoided since the undepleted em itter region will lead to an
increase in parasitic emitter resistance. To obtain a low em itter contact resistance, it is
common to grow an em itter cap layer with high doping concentration on top of the
intrinsic emitter. The thickness o f the emitter cap layer is chosen to be reasonably thick
for process consideration. For double-mesa HBT fabrication, a minimal step height of
3000 A is required for em itter mesa in order to employ self-aligned base contact without
shorting the emitter and the base electrodes. Therefore, a
2000
A-thick n-type Si layer
with high doping concentration ( - 2 x 1 0 19 cm'3) is utilized as the em itter cap layer.
2.3.8 Epitaxial growth of the heterojunction structure
Growth o f high-quality epitaxial layers is crucial for the successful development of
high-performance devices and circuits. For high-speed low-power applications, the n-p-n
double heterojunction SiGe structure as shown in Fig. 2.1 was grown by molecular beam
16
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epitaxy (MBE), except for the thick subcollector layer, which was developed through
chemical vapor deposition (CVD).
The growth starts with the subcollector layer; an 1.5 jim-thick arsenic-doped Si layer
is grown by CVD on a (100) Si substrate, whose resistance is higher than 10 k£2-cm.
Then, the wafer is loaded into the MBE chamber for the growth o f the HBT structure.
o
The thickness o f th e antimony-doped Si collector layer is 3000 A and a doping
concentration o f Ix lO 16 cm ' 3 is chosen to maintain reasonably high breakdown voltage o f
the device. The base layer is a boron-doped SiGe alloy with a uniform Ge composition of
40% . To ensure high f r and
doping concentration
of the transistor, a thin base layer (-200 A) with high
(~ 2 x l0 19 cm*3) is employed
in this design.
unintentionally doped SiGe spacers with a thickness o f 50
A
Furthermore,
are inserted at the E-B and
B-C junctions to suppress boron outdiffusion. Again, antimony-doped Si layers are
grown on top of the structure as emitter layer and em itter cap to complete the
heterostructure. All o f the M BE epitaxial layers are grown at a rate o f
2
A/s
with a
background pressure o f 6 x l0 ' 9 torr. The growth temperature is fixed at 415 °C for the
Emitter cap
Emitter
Spacer
Base
Spacer
Collector
Subcollector
Substrate
Si
Si
Sio.6Geo.4
Sio.6Geo.4
Sio.6Geo.4
Si
Si
Si
n+
n
i
+
P
i
n'
n+
P
2 x l 0 19
2 x l 0 18
2 x l 0 19
5 x l 0 15
I x lO 19
Ix lO 12
200 nm
100 nm
5 nm
20 nm
5 nm
300 nm
1.5 pm
540 M-m
Fig. 2.1 Epitaxial structure of SiGe HBT’s for high-speed and Iow-power
applications.
17
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collector and emitter layers and 550 °C for the base layer.
2.4 Fabrication of SiGe HBT’s
M esa-type HBT’s have been fabricated with standard lift-off and etching techniques
[31]. The process starts with em itter metal contact formation (Cr/Au=500/2000 A) on the
highly doped emitter cap layer by evaporation and lift-off process. In order to improve
the contact resistance, rapid thermal annealing (RTA) is performed on the em itter contact
at a tem perature of 400 °C for 20 seconds.
The em itter metal pattern is used as an etch mask for emitter m esa formation, which
exposes the base layer for metalization. As can be seen from (2.8), the base resistance R B
plays an important role in the frequency response of a transistor. Therefore, baseexposure is the most critical step in the fabrication process of mesa-type H B T’s. Over­
etching o f the base layer and undercutting o f em itter layer should be minimized for a
small R b.
To
optimize the etch profile for em itter mesa formation, a two-step etch is
employed. First, an anisotropic reactive ion etch (RIE) with SF 6 and O 2 gas mixture
removes m ost o f the emitter/emitter cap layer without undercut. Second, a KOH-based
solution (KOH/H 2 O = 50g/200ml) selectively etches the remaining em itter layer and
stops on the SiGe base layer. Due to the orientation dependence o f sidewall profile o f the
KO H etch process, a minimal undercut is also introduced simultaneously for self-aligned
base metal deposition.
A fter the self-aligned base metal deposition (Pt/Au=200/1300 A), the base m esa is
formed by RIE, exposing the highly doped subcollector layer for collector contact. Again,
collector metal (Ti/Au=500/2000
A)
contact is formed by evaporation and lift-off,
18
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following by another RTA (370 °C, 5 seconds) for base and collector contact sintering.
Then an RIE step etches away the remaining epitaxial layers outside the active device,
leaving the high-resistivity Si substrate exposed. In order to suppress surface
recombination, plasma enhanced chemical vapor deposition (PECVD) SiC>2 layer is
employed to passivate the HBT devices. RIE via hole formation followed by
interconnection metal deposition (Ti/Al/Ti/Au=500/11000/500/3000 A) completes the
fabrication process. The complete process flow o f the SiGe HBT fabrication is shown in
Fig. 2.2, and Figure 2.3 shows a schematic diagram o f the device cross-section and a
photomicrograph o f the fabricated common-emitter SiGe HBT with emitter area o f 5x5
(xm2.
Emitter metal
(Cr/Au = 500/2000 A)
Collector metal
(Ti/Au = 500/2000 A)
Emitter m esa
D evice isolation
Base metal
(Pt/Au = 200/1300 A)
D evice passivation
(PECVD S i0 2)
Base m esa
Via hole
Interconnection
Fig. 2.2 Fabrication process flow of the double-mesa SiGe HBT’s.
19
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(a)
(b)
Fig. 2.3 (a) Schematic cross section o f the fabricated SiG e HBT. (b)
Photomicrograph o f the fabricated common-emitter SiGe HBT
with emitter area o f 5x5 jim 2.
2.5 DC and RF Characteristics of the SiGe HBT’s
Based on the heterostructure and process technology described in the previous
sections, SiGe HBT’s with emitter area o f 5x5 pm 2 were fabricated fo r high-speed and
low-power applications. DC and RF m easurem ent are performed on the fabricated HBT’s
for device characterization.
2.5.1 DC characterisitcs
The DC characteristics of the fabricated SiGe HBT’s have been measured using
HP4155 semiconductor parameter analyzer. W ith a collector thickness o f 3000 A and a
doping concentration of 5 x l0 15 cm"3, the open-em itter breakdown voltage
open-base breakdown voltage
B V ceo
B V cbo
and the
are 18 V and 5 V, respectively. Figure 2.4 shows
the common-emitter I-V characteristics o f the device. It is observed from Fig 2.4 that the
device suffers from the Kirk effect due to its relatively low collector doping
concentration. This effect appears to be m ore severe when the device is biased at low Vce
20
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and high Ic- This can be ascribed to low er injection carrier velocity at low junction
voltage, leading to a higher effective carrier concentration. However, by operating the
device outside the region influenced by the Kirk effect, the small-signal operation o f the
device would not be seriously degraded. The offset voltage of the device is very close to
zero, implying the symmetry o f E-B and B-C heterojuctions as a consequence o f uniform
Ge com position across the base region.
Figure 2.5 shows the Gummel plot o f the same device, and the collector and base
ideality factors are extracted from the slope o f the plot. From the extraction, the value o f
the collector ideality factor nc is 1.04, which is quite close to unity. However, the value o f
the base ideality factor rib is 1.79. Insufficient passivation is believed to be responsible for
AE=5x5|inr2
A ge=10x12pm'
lb ,s te p =
1 0 p A
-2
0
1
2
3
4
Vq e IV]
Fig. 2.4 I-V characteristics o f the SiGe HBT
(A e
= 5x5 pm 2).
21
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5
the large base ideality factor. Although a PECVD SiC>2 layer is adopted as device
passivation during the fabrication process, it was observed that the narrow openings
between emitter and base metals become pinched o ff by the SiC>2 deposited on emitter
and base metal edges, preventing the SiC>2 deposition on the emitter sidewall. This leads
to an insufficient suppression of surface recombination. The DC current gain (3 is
measured at the fixed collector-emitter voltage Vce = 4 V, as shown in the inset. Values
higher than
100
are obtained for most o f the operating current range with the maximum
value of 109 occurring at Ic = 10.4 mA.
le-02
1000
le-03
CO.
i—i
le-04
<
^
i—i
u
~
le-05
Ic [mA]
le-06
le-07
le-08
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Vc
e
CV]
Fig. 2.5 Gummel plot of the SiGe HBT
(A e
= 5x5 (lm2).
22
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2.5.2 RF characteristics
To characterize the frequency response o f the SiGe HBT devices with em itter area of
5x5 (im“, the S-parameters are measured using a vector network analyzer and a on-wafer
probe station. Based on the following expressions [32] for current gain / 12/ and unilateral
power gain U in terms of S-parameters, the frequency response of the fabricated device is
shown in Fig. 2.6.
(2.15)
I S2l / 5 12 —112
jr
(2.16)
t - I S n |2 —1S22 |2 +1 A I2
2 1Sl2 I • 1S2l I
(2.17)
I A N SuS22—S2lSl2 I
(2.18)
As mentioned in section 2.2, the figures of merit that are typically used to evaluate the
high frequency behavior o f a bipolar transistor are the cut-off frequency f r and maximum
oscillation frequency / „ . Experimentally, f r and fmax can be determined by extrapolating
the gains with the - 6 dB/octave roll-off assumption based on the one-pole approximation.
For a common-emitter SiGe HBT (emitter area = 5x5 pm 2) operating at Ic = 7 mA and
Vce = 4 V, the f r and fmax exhibited from the extrapolation are 28 GHz and 52 GHz,
respectively. Furthermore, the bias dependence of fmax is shown in Fig. 2.7 based on Sparameter measurement.
Stability is also one of the most important characteristics for a high-speed transistor.
Based on two-port network analysis, the transistor is unconditionally stable at a given
frequency only if the following conditions are valid:
23
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k>l
(2.19)
IA k 1
(2.20)
As given in (2.17) and (2.18), the stability factor k and the S-parameter determinant IA1
can be obtained as a function of frequency based on the S-parameter m easurem ent
results. It is observed that IAI is lower than unity for the entire frequency range measured.
However, k becomes smaller than unity for frequencies lower than 7 GHz, which implies
that the device is unconditionally stable only for frequencies higher than 7 GHz.
30
25
20
-S
<3
o
IH 2 1 I
I
10
100
frequency [GHz]
Fig. 2.6 Frequency response of the SiGe HBT (AE = 5x5 (J.m2) with DC
bias Ic = 7 m A and V C e = 4 V.
24
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50
4 5
4 0
3 5
N
3 0
CD
25
X
|
20
15
3V
10
0
2
4
6
8
10
12
14
lc [mA]
Fig. 2.7 Bias dependence offmax for the SiG e H B T (Ag = 5x5 (im2).
2.6 Summary
In this chapter, the design considerations and the principles of performance trade-off
for HBT structure optim ization are discussed. Follow ing these guidelines, the SiGe
H B T’s for high-speed and Iow-power applications has been designed and grown by
MBE. Standard double-m esa process technology has been developed for device
fabrication. The fabricated devices were characterized by DC and RF measurements. A
common-emitter SiG e HBT with emitter area o f 5x5 Jim2 was found to exhibit a
maximum DC current o f 109. With a bias condition o f Vce = 4V and Ic = 7 mA, t h e / r
and fmax o f this device are 28 and 52 GHz, respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER III
DEVELOPMENT OF MULTI-FINGER SiGe POWER HBT’S
3.1 Introduction
A microwave power transistor is an essential component in modem R F transmitters.
High-performance power transistors are characterized by high power added efficiency
(PAE), output power and power gain at microwave frequencies. Among all candidates,
bipolar junction transistors (BJT’s) in particular have been investigated due to their high
current-handling capability per-unit-area and high-voltage operation. Owing to the
material system’s higher mobility and carrier saturation velocity, m odem power
transistors have been dominated by III-V compound semiconductors [33]-[39]. However,
severe thermal stability problems have been a major concern when IH-V based devices
are used in power applications due to the poor thermal conductivity of such substrate
materials. Special thermal designs, such as ballast resistors [40], thermal shunts [41], or
increased finger spacing for m ore effective heat sinking, have been widely used to
suppress the inherent thermal stability problems. In contrast, Si-based devices do not
share these same problems because o f their higher substrate thermal conductivity. With
recent advances in epitaxial growth of SiGe heterostructures, high-speed SiGe HBT’s
have been reported for low-power applications. Power performance of SiGe H B T’s has
26
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only been dem onstrated at lower frequencies [42]-[44]. In this work, effort has been
made to further investigate the power performance o f the SiG e H B T’s. By incorporating
the high-frequency performance o f heterojunction devices and the high thermal
conductivity o f the Si substrate, SiGe H B T ’s exhibit a strong potential for power
applications in X-band or even up to K-band frequencies.
3.2 Design of Multi-finger SiGe Power HBT’s
The design o f m ulti-finger SiGe pow er H BT’s can be divided into two parts; the
vertical layer structure and the device layout. In general, the design o f the vertical
heterostructure establishes the intrinsic characteristics o f the transistor operation. On the
other hand, the layout design is more focused on reducing device parasitics. Both parts
are equally im portant with regard to device performance, and require thorough
understanding o f device operations.
3.2.1 Vertical design of power HBT structure
Based on the guidelines as discussed in section 2.2, the SiGe HBT structure has been
designed and optim ized for power applications. In order to achieve high gain and high
output power at m icrow ave frequencies, device characteristics such as maximum
oscillation frequency, breakdown voltage and maximum operating current have to be
taken into consideration.
The design o f base layer is optimized for fmax. Therefore, a thin SiGe base layer (-200
A) with a doping concentration of IxlO 20 cm -3 has been employed, resulting in a small
base transit time Tb without sacrificing base resistance Rb. A uniform Ge composition
27
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profile o f approximately 30% is used for the base layer to ensure there exists a bandgap
difference at the heterojunctions. Furthermore, 50 A-thick unintentionally doped SiG e
spacers are inserted at the both sides of base region to suppress boron outdiffusion.
The collector layer is designed based on the consideration of output power. Since the
R F output pow er is proportional to the product of the output voltage and the operating
current, a power transistor is required to have a high breakdown voltage and a high
m axim um operating current. H igh B-C junction breakdown voltage can be achieved by
reducing the collector doping concentration N c and increasing the collector thickness WcHowever, reducing N c will lim it
J c ,m a x
o f the bipolar transistor due to the Kirk effect, and
so a trade-off has to be made between breakdown voltage and maximum operating
current for an optimum power performance. Accordingly, the N c and W c are chosen to
be 1x1016 cm-3 and 5000 A, respectively, to achieve high junction breakdown voltage,
w hile maintain a reasonably high
Jc .m a x -
W ith a fixed doping concentration and Ge composition in the base region, the current
gain can be adjusted by the doping concentration and the thickness of the em itter layer.
For an HBT operating in the com m on-emitter configuration, the open-base breakdown
voltage
B V ceo
can be expressed as
BVceo= BVa
^ P -,
lf/3
(3.1)
which implies that the current gain (3 can be traded for
current gain is chosen in order to achieve higher
B V ceo-
B V ceo,
Therefore, a m oderate
and the resulting doping
concentration and thickness of the em itter layer are IxlO 18 cm-3 and 500
A, respectively.
28
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(100) Si wafers with a resistivity higher than 10 k£2-cm were used as substrates. The
epitaxial growth o f the HBT structure starts with the subcollector layer by CVD, followed
by M BE growth o f the successive layers. Figure 3.1 shows the design of the HBT
structure along with the secondary ion mass spectrometry (SIMS) analysis profile.
S i o . 7 G e 0.3
P'
IxlO 19
O
Si
Si
Si
IxlO 20
O'
S i o . 7 G e 0.3
X
S i o .7 G e o .3
IxlO 20
Ix lO 18
O
n+
n
i
p+
i
n'
n+
Si
Si
X
*—1
Emitter cap
Emitter
Spacer
Base
Spacer
Collector
Subcollector
Substrate
250 nm
50 nm
5 nm
20 nm
5 nm
500 nm
1 pm
540 pm
(a)
1e+21
o 1e+19
g le + 18 -
52 1 e + 1 7
O ie+ 1 6
1e+150.2
0 .4
0.6
Depth (pm)
(b)
Fig. 3.1 (a) Epitaxial stracture o f SiGe HBT’s for power applications, (b)
Secondary ion mass spectrometry (SIMS) analysis profile.
29
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3.2.2 Layout design of multi-finger devices
In addition to the vertical design of the HBT structure, layout design also has a strong
influence on the device performance. Since the output power of a bipolar transistor is
proportional to the emitter periphery, devices with large dimensions are usually required
for power applications. In this case, the layout o f the device has to be carefully designed
for minimal parasitics in order to achieve high output power, while maintaining the high
frequency performance. An efficient way to reduce the parasitics o f the device is to
employ long and narrow fingers for the emitter, and the output power is achieved by
connecting multiple o f fingers in parallel.
In order to have a uniform current distribution along the emitter, the finger length L
should be determined by considering the potential difference induced in the longitudinal
direction on the emitter due to the finite conductivity o f the emitter contact metal. For a
given emitter current density J e and emitter metal sheet resistance RSh, the longitudinal
potential difference can be approximated as [45]
AV£ =-j / £Z?K*.
(3.2)
The rule o f thumb for emitter finger design is to keep AVe smaller than
. Assuming
an emitter current density o f 30 kA/cm2, a finger length of 30 (im is selected for the
layout design.
The emitter finger width W is determined based on a consideration o f base resistance
R b, which is crucial for high frequency operation. Base resistance can be divided to two
parts. The first part is the resistance due to the extrinsic base region, and can be
minimized by self-aligned contact structures. On the other hand, the second part (base-
30
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spreading resistance) is the resistance between the edge of the em itter and the site within
the intrinsic base region at which the current is actually flowing. R educing the em itter
w idth can improve the base-spreading resistance and prevent em itter current crowding.
Based on the lithography limitation and process stability, the emitter width was chosen to
be 2 pm for the multi-finger devices.
M ulti-finger HBT devices have been designed based on the above analysis, and the
layout o f a 10-finger common-emitter device is shown in Fig. 3.2. The em itter fingers are
surrounded by base electrodes with a w idth of 1.5 pm , and the intrinsic base is accessed
from both sides o f the fingers. Emitter contacts are made through isolated emitter pads,
which connect to the intrinsic part of the device via emitter air-bridges. B y employing the
isolated em itter pads, no lithographic patterning is required for vias on the intrinsic part
Em itter
USH
Base
Collector
Em itter
Fig. 3.2 Layout of the 10-finger common-emitter SiGe HBT.
31
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o f the em itter fingers. Therefore, a narrow finger width of 2 p m is allowed for the multi­
finger devices. Furthermore, the area for emitter pads can be excluded from the area
accountable for the
B -C
junction, leading to a reduction o f
C bc
for optimum RF
characteristics. Assuming that the collector region is fully depleted, the junction
capacitance
C bc
estimated from the device layout is 34.7 fF/finger. In order to alleviate
thermal stability problems, the spacing between two emitter fingers is chosen to be 12
pm . In addition, the collector electrodes, which are connected together by interconnection
through vias, are inserted in between the em itter fingers to reduce the collector spread
resistance. As a result, the efficiency o f the device can be improved, especially for highpow er operations. It is noted that the capacitance due to the crossover of the collector
interconnection and the base electrodes also contributes to the
1 pm
SiC>2 inter-metal dielectric
Cbc
o f the transistors. With
layer, the additional parasitic capacitance is
approxim ately 1.4 fF/finger, w hich is about 4% o f the total Cbc for the multi-finger
devices.
3.3 Fully Self-Aligned Technology for Multi-finger HBT Devices
A novel fully self-aligned process technology has been developed to fabricate the
double-m esa SiGe HBT. The fabrication starts with emitter metal (Cr/Au=500/2000 A)
deposition, followed by two consecutive reactive ion etch (RIE) steps for base mesa
form ation and device isolation, respectively. An SF6 (20 seem) and O 2 (3 seem) gas
m ixture is used for the RIE etch with RF pow er o f 65 W. For base mesa formation, which
defines the base contact area, a cham ber pressure o f 5 m T is used to achieve an
anisotropic etch profile. On the other hand, the chamber pressure is increased to 40 mT
32
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Emitter cap/Emitter
Collector
Subcollector
Substrate
Before KOH process
(b)
Fig. 3.3 Base/subcollector exposure using selective KOH etch, (a) Photo­
micrograph. (b) Schematic cross section.
for the device isolation step in order to create undercuts for the emitter air-bridge
structure, ensuring the mesas of the em itter pads are isolated from the active devices.
Up to this point, neither the p+ base nor the n+ subcollector has been exposed for
contact formation. A KOH etch step is next performed to expose base and subcollector
layers simultaneously without lithographic patterning. Due to the etch selectivity o f KOH
between Si and SiGe, only Si layers are etched away, creating undercuts underneath the
em itter metal and the SiGe base as shown in Fig. 3.3. After the KOH process, metal
layers
(Ti/Au=500/1000)
are
deposited
for
base
and
collector
33
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metalization
Emitter cap/E m itter
Base
Collector
Subcollector
Substrate
(b)
Fig. 3.4 Self-aligned base/collector contact metalization. (a) Photo­
micrograph. i(b) Schematic cross section.
simultaneously, resulting in a fully self-aligned double-mesa structure as show n in Fig.
3.4. In this structure, the b a se metal contact is self-aligned to the edge o f em itter metal,
resulting in a minimal lateral distance which accounts for the base access resistance.
Furthermore, the collector m etal contact is also self-aligned to base contact ow ing to the
undercut underneath the S iG e base layer. As a result, both Rb and Rc can be m inim ized,
leading a significant im provem ent on fmax and device parasitics.
Following the self-alignecfl metalization for base and collector contacts, a 1 pm -thick
PECVD SiOo deposition w ith substrate temperature o f 200 °C is employed fo r device
passivation, followed by via formation using RIE. Then a deposition o f 1.5 pm -thick
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
interconnection (Ti/AI/Ti/Au) by evaporation and lift-off process com pletes the device
fabrication. The complete process flow o f the fully self-aligned H BT technology and
photom icrograph of the fabricated SiGe HBT with 10 emitter fingers are shown in Fig.
3.5 and Fig. 3.6, respectively.
This unique process technology provides several advantages. First o f all, self-aligned
base and collector metalization is utilized, resulting in a reduction in both base and
collector access resistance. Second, the laterally etched undercut created underneath the
SiGe base layer reduces the area accountable for extrinsic base-collector capacitance
C bc,
which plays an important role in the / max o f the device. In addition, the K O H process,
which is performed after the device isolation, also removes the Si layers underneath the
em itter air-bridges. As a result, isolated pads (as shown in Fig. 3.7) for em itter contacts
are available for this technology, resulting in smaller parasitic capacitance
C be
Emitter metal
Base/collector metal
Base mesa (REE)
Device passivation
PECVD SiO,
Device isolation (RIE)
Via hole
Base/subcollector
exposure (KOH)
Interconnection
Fig. 3.5 Fabrication process flow o f the fully self-aligned SiGe H B T’s.
35
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and
C bc-
Fig. 3.6 Photomicrograph of the fabricated 10-finger common-emitter
device.
Collector
Isolated pads for emitter contacts
Fig. 3.7 Schem atic o f the multi-finger devices with isolated pads for
em itter contacts.
36
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3.4 DC Characteristics
To characterize the performance of the power devices, both common-emitter and
common-base multi-finger SiGe HBT’s with finger numbers o f 2, 10 and 20 have been
fabricated and tested. The DC characteristics of the devices have been measured with a
HP4155 semiconductor parameter analyzer. The I-V characteristic o f a two-finger
common-emitter device as shown in Fig. 3.8 exhibits a maximum DC current gain (3 of
26 and a maximum differential current gain A(3 of 33. It may be noted that the current
gain is selected to be lower than the one obtained in the Iow-power design by lowering
Ge composition and increasing doping concentration in the base region. In the power
device, current gain is traded for increased
B V ceo
in order to maximize the output power
o f the devices. W ith a collector thickness of 5000 A and a doping concentration of IxlO 16
cm*3, the open-base breakdown voltage
B V cbo
and the open-emitter breakdown voltage
301
20
“
10
0
2
4
6
8
VCE (V)
Fig. 3.8 I-V characteristics of the fabricated multi-finger SiGe HBT
(A e = 2x2x30 (J.m2).
37
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
B V ceo
are 25 V and 10 V, respectively. As can be seen from Fig. 3.8, the m ulti-finger
device is allowed to operate at a maximum collector current density o f 30 kA/cm 2
without suffering from K irk effect. Furthermore, the I-V characteristics also exhibit small
series resistances (R e and Rc) achieved through use o f the fully self-aligned technology.
Figure 3.9 shows the G um m el plot of the same device, showing a collector ideality factor
of 1.01 and a base ideality factor of 1.3.
3.5 RF Characteristics and Small-Signal Equivalent Circuits
For small-signal R F characteristics, on-wafer probing S-parameter measurement has
been performed on the m ulti-finger HBT’s using HP85 IOC network analyzer from 2 GHz
to 40 GHz. Figure 3.10 shows the current gain h2j and unilateral power gain U o f the
common-emitter device (em itter area = 2x2x30 p.m2) at a DC bias o f Ic = 28 m A and Vce
30
0Q.
20
10
10
20
30
40
lc (mA)
0
0.2
0.4
0.6
0.8
VBE. V ce (V)
Fig. 3.9 Gummel plot o f the fabricated m ulti-finger SiGe HBT
(A e = 2x2x30 p.m2).
38
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1.0
= 6 V. The values o f fi- and fmax, extrapolated with the assumption o f —6 dB/octave roll
off, are 37 GHz and 78 GHz, respectively. The bias dependence o f the frequency
response with both fixed Ic and Vce are shown in Fig. 3.11. For a wide range of Ic and
Vce, the frequency response in terms of h2i and U is nearly constant, which implies the
pow er devices are also favorable for high efficiency pow er amplifiers.
In order to investigate the device performance by employing the full self-aligned
process technology, a small-signal T-model has been used to characterize the HBT
device. Following the method proposed by Pelhke [46], the parameters o f the equivalent
circuits have been extracted based on the S-param eter measurement. T he measured Sparameters are first converted to /z-parameter, and then the small-signal equivalent circuit
parameters are extracted from the obtained /z-parameters. Figure 3.12 shows the T-model
3cr
2.0
1.5
CD
20
o.o
■O
10
20
30
40
Frequency (GHz)
10
max
10
1
100
Frequency (GHz)
Fig. 3.10 Frequency response of the fabricated multi-finger SiGe H BT
(A e = 2x2x30 (im2) with DC bias Ic = 28 mA and V ce = 6 V.
39
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CD 20
U (Vce=6V)
U (Vce=5V)
U (Vce=4V)
U (Vce=3V)
U (Vce=2V)
U (VCE=1V)
10
Frequency (GHz)
(a)
30
U (lc =28mA)
U (lc =21mA)
U (lc=12mA)
U (lc =5mA)
10
1
10
Frequency (GHz)
(b)
Fig. 3.11 The bias dependence of frequency response for the fabricated
multi-finger SiGe HBT ( A e = 2x2x30 (im2). (a) Fixed I c = 28
mA. (b) Fixed V ce = 6V.
40
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equivalent circuit along with the extracted parameters at a. bias point of Ic = 28 m A and
V
ce
= 6V .
As can be seen from Fig. 3.13, the extracted equivalent circuit param eters
exhibit a close prediction o f the device performance com pared with the S-param eter
measurement.
For circuit applications, devices with 2, 10 and 20 fingers have been characterized in
both common-emitter and common-base configurations. 'T he small-signal performance as
determined from the measured S-parameters is tabulated in Table. 3.1. For com m on-
r -ii
_C pc.
-b
R,B
B a se
'B E '
Cp.fr
J5«£
Rr
*-c
Collector
^BE
t
Rp
CP2
Emitter
DC bias: Ic = 28 mA, VCE = 6 V
Rb
Lb
R be
C be
Re
Le
a
50 pH
R bc
Cbc
33 kQ
7 9 fF
i.8 i a
270 fF
Rc
14 a
3 0 pH
i.i a
30 pH
Cpi,2
1 .7
Lc
a0
17 fF
0.96
Fig. 3.12 T-model equivalent circuits and the extracted parameters for the
fabricated multi-finger SiGe HBT (A e = 2o<2x30 pm 2).
41
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em itter devices, th e/ „ : decreases as the finger number increases, while fi- is not strongly
influenced by the num ber o f fingers. Since
Tb
and
Tc s c l
dominate the total em itter-
collector transit tim e Tec in this design, th e / 7*is more sensitive to vertical layer structure
than the device layout. On the other hand, device parasitics such as Rb and
significant impact on fmax- As finger number increases, the increase o f
C bc
C bc
have a
is alm ost
linearly proportional to the finger number, while the Rb does not decrease accordingly
due to the interconnection between fingers and the non-uniform distribution o f the
current. Therefore, the larger the finger number, the lower the fmax of the device. In
general, devices in common-base configuration exhibit higher fmax than the ones in
□ S u_model
SI2_modeI
V S2I_model
- S„_model
22
—
120
* S2I
* S 12
,2 + S22
60
.3 0
150
180
'/W - 5 .0
-0 . 2'
^T7T5
Frequency 2.0 to 20.0 GHz
Fig. 3.13 S-parameter characteristics from the small-signal equivalent
circuit vs. measurement.
42
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common-emitter configuration. However, common-base devices tend to be unstable
especially at lower frequencies.
3.6 Power Performance and Large-Signal Modeling of the Power Devices
Load-pull measurem ent has been performed on fabricated devices using a Focus
Microwave Systems instrument in an effort to characterize device power performance.
The measurement setup is shown in Fig. 3.14. No special setup for heat dissipation is
employed during the measurement. Both source and load tuners are optimized for
maximum output pow er during the measurement. Then the pow er gain G, output pow er
Pout and power added efficiency PAE are measured as a function o f input power Pjn at 8.5
GHz in CW mode.
For class-A operations, a 10-finger common-emitter device is biased at V be = 0.82 V
and V ce = 6V. The source and load tuners are optimized for maximum output power.
With a source impedance o f 0.702Z173.60 and load impedance o f 0.42Z99.20, the pow er
saturation curve is obtained by sweeping the input power from —20 dBm to 20 dBm as
shown in Fig. 3.16. As input power increases, the power gain decreases from an initial
value o f 10.7 dB, which is the small-signal gain of the device. A t an input power o f 18
Common-emitter
Common-base
f r (GHz)
fmax (GHz)
fmax (GHz)
2-finger
37
78
81
10-finger
33
52
70
20-finger
31
34
40
Table 3.1 fi- andfmax o f the multi-finger devices in common-emitter and
com m on-base configurations.
43
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Power
meter 2
Spectrum
analyzer
Power
meter 1
VNA Port L
VNA Port 2
Switch
Switch
RF source
Tuner 1 SB A Tuner 2
Coupler
Isolator
Isolator
Coupler
La
Harmonic
Tuners
Fig. 3.14 Measurement setup for load-pull system.
dBm, the PAE reaches a maximum value of 26.9% while the pow er gain and output
power are 6.13 dB and 24.13 dBm, respectively.
Similar measurement has been performed on a 10-finger common-base device in
class-A operations. The DC bias voltages for V Be and V cb are —1.1 V and 6 V,
respectively. The power saturation curve of the device is shown in Fig. 3.18. A maximum
PAE o f 33.1% is obtained at an input power of 17 dBm, and the resulting power gain and
output power are 7.6 dB and 24.6 dBm, respectively. Without the limitation of B V ceo
due to carrier multiplication in the common-emitter configuration, a bipolar device can
operate at even higher output voltage in common-base configuration, leading to a higher
output power for a device with the same emitter periphery.
First power measurement results on SiGe HBT’s were reported by Erben et al. [42]
with a PAE o f 33% at 5.7 GHz. In 1996, SiGe power HBT’s were demonstrated to
deliver 1 W RF power at 1.9 GHz with a PAE of 44% for a class-A operation [44]. Most
o f the efforts on SiGe pow er HBT’s were limited at frequencies below C-band. It requires
44
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30
CQ
30
out
20
20
Gain
CO
(D
"0
m
>
10
CQ
~cs_
PAE
o
Q.
10
0
10
-10
-20
10
0
20
Pin [dBm]
Fig. 3.15 Power gain, output power and PAE o f the 10-finger commonem itter device.
30
40
out
20
30
"O
Gain
>
m
10
20
-o
PAE
Q_
-10
0
-20
-10
0
10
20
Pin [dBm]
Fig. 3.16 Power gain, output power and PAE o f the 10-finger commonbase device.
45
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further optim ization in terms of layer design and device technology to extend the
operation frequency into X-band. W ith high-quality SiG e epitaxial layers and the fully
self-aligned structure, multi-finger devices can deliver high R F power, while maintain
high pow er gain at X-band frequencies. For the first tim e, SiGe power HBT’s have
dem onstrated 24 dBm output power with a PAE of 33% for class-A operation at 8.5 GHz.
In addition to the load-pull measurement, the Gummel-Poon model is also employed
to characterize the devices for large-signal applications based on the technique proposed
by [47]. First, the measurement of the junction characteristics is used to extract the
parameters for forw ard and reverse diodes. Then the I-V characteristics are used to adjust
the intrinsic model parameters. In order to use the devices for circuit designs, models for
the transistors should be able to accurately predict both large- and small-signal
operations. Therefore, the model parameters representing device parasitics are optimized
with regard to S-param eter and load-pull measurement under various bias conditions. The
Gum m el-Poon model and the extracted parameters for a 10-finger device are exhibited in
Fig. 3.17.
3.7 Summary
In order to achieve the device performance required for SiGe pow er HBT’s, both the
vertical structure and the device layout have to be carefully designed. The vertical layer
design is optim ized for high gain and high power at m icrow ave frequencies, while the
layout design is focused on minimizing the device parasitics for optimum device
efficiency. In this chapter, a novel process technology with a fully self-aligned structure
has been discussed for the fabrication o f multi-finger devices. By adopting this
46
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Collector
bd
B ase
Su bstrate
sc
_
Cf„+Ct- -
se
Emitter
Rb
Pf
Is
I lf
Re
Ise
i.2 a
24
18.4 fA
1.024
0.1 Q.
2e-18 A
ne
Pr
nr
Ise
nc
rc
7
0.238
1.023
35 nA
1.89
4
Fig. 3.17 Gummel-Poon model and the extracted parameters of the
fabricated 10-finger device.
technology, the device parasitics such as
R b, R c
and
C bc
can be minimized, resulting in a
significant improvement on fmax and efficiency of the device.
Multi-finger devices with finger numbers of 2, 10 and 20 have been fabricated in
common-emitter and common-base configurations. The DC measurements exhibit an
open-emitter breakdown voltage
B V ceo
B V cbo
of 25 V and an open-base breakdown voltage
of 10 V with a differential current A (3 o f 33. From small-signal S-parameter, the.fr
and fmax of the fabricated 2-finger HBT in common-emitter configuration are 37 GHz and
78 GHz, respectively. Furthermore, load-pull measurement has been perform ed on the
fabricated 10-finger devices at 8.5 GHz to characterize their power performance.
47
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Operating in class-A mode, the common-emitter device exhibits maximum PAE o f
26.9% with power gain of 6.16 dB and output power o f 24.13 dBm, while common-base
devices show a m axim um PAE o f 33.1% with power gain o f 7.6 dB and output power o f
24.6 dBm.
To further investigate the device operations, both small-signal and large-signal
equivalent circuits have been employed to model the m ulti-finger devices. With close
prediction to the m easured device performance, the equivalent circuits can be used for
computer simulation in circuit designs.
48
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CHAPTER IV
MICROMACHINED TECHNOLOGY FOR MICROWAVE
LUMPED PASSIVE COMPONENTS
4.1 Introduction
W ith recent progress in Si process technology, Si-based M M IC’s have received great
attention
as potential candidates
for the wireless communication
market.
The
developm ent of high performance passive components, especially the spiral inductors
that play an important role in circuit implementation, remains a challenge. Limiting
factors such as the quality factor (Q), resonant frequency (/res) and distributed effects o f a
spiral inductor have to be carefully investigated in microwave frequencies to allow for
successful circuit design. Recently, efforts to improve the characteristics o f spiral
inductors by using a stacking metal layer [48], employing a suspended structure [49] and
patterned ground shields [50] have been reported. M ost of the proposed approaches have
been demonstrated at frequencies well below X-band. Therefore, a novel m icrom achined
technology is proposed [51] to improve the Q-factor and the resonant frequency o f a
spiral inductor, resulting in lumped designs that can be used in microwave circuits up to
20 GHz.
49
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4.2 Implementation o f Thin-Film Resistors
A resistor is one o f the most important passive components and is widely used for
termination, bias circuits, impedance matching and feedback networks in microwave
circuits. Typically, resistors are realized either by a thin film of lossy metal or a
semiconductor film with a proper doping concentration on a semi-insulating substrate.
The resistance o f a thin-film resistor is given by
C4- 1)
where p (£2-cm) is the resistivity o f the thin-film material and £, d and W represent the
length, thickness and the width, respectively. As the frequency increases, the resistance
will deviate from (4.1) due to the finite skin depth o f the thin-film material. Therefore,
the resistance is normally given by the sheet resistance RSheet (£2/111), especially for thin
films with a thickness larger than 1p.m. Thus,
* =» - £ •
(4.2)
To properly select a material used for thin-film resistors, characteristic parameters
such as sheet resistance, temperature coefficient, power handling capability and reliability
need to be investigated. Since semiconductor films exhibit nonlinear behavior at high DC
current density due to electron velocity saturation and a positive temperature coefficient
of resistance, it is desirable to use metal thin films fo r planar resistors. The materials
frequently used for thin-film resistors are listed in Table 4.1.
In microwave applications, the physical dimensions o f a lumped resistor should be
small compared with the wavelength at the operating frequencies to minimize distributed
effects. On the other hand, it is desirable to have a maximum area as far as power
50
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
dissipation is concerned. Therefore, the design parameters such as I, d and W are
determined based on the resistance, operating frequencies and maximum pow er
capability required in circuit applications.
In this study, NiCr is used for resistor implementation due to its good stability and
low temperature coefficient. Thin-film resistors with various width and length are
designed, fabricated and characterized. On-wafer probing using HP8510 network
analyzer has been performed for S-parameter measurement, then the measured results are
used to model the resistors for circuit applications. Figure 4.1 shows a photomicrograph
and the equivalent circuit o f the thin-film resistor, where R and Lj are the resistance and
the parasitic inductance, respectively, and Cpi and Cp2 represent the parasitic capacitance
to ground. In order to characterize the device at microwave frequencies, the equivalent
circuit parameters (as shown in Table 4.2) have been extracted from S-param eter
measurements. According to the extracted resistance as shown in Fig. 4.2, an evaporated
N iCr layer with a thickness o f 700 A exhibit a sheet resistance of 28-30 Q /D .
Metal films
Resistivity (jiQ-cm)
Cr
13
Ti
55-135
Ta
180-220
NiCr
60-600
TaN
280
Ta2N
300
Table 4.1 Materials for thin-film resistors.
51
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
W idth x Length
R (Q )
Ls(pH )
C pi (fF)
Cp2 (fF)
10pmx50pm
151
73
3.4
4.2
10(imxl00(JJii
282
163
3.2
7.1
10p.mx200jJ.rn
548
374
1.5
2.4
20pm x50pm
79
72
3.3
3.9
20pm x 100pm
138
127
6.4
5.8
20jjm x200pm
249
166
5.1
8.7
30pm x50pm
53
66
1.7
2.1
30pm x 100pm
95
96
4.1
1.0
30pm x200pm
161
178
6.3
2.7
Table 4.2 The equivalent circuit parameters of the fabricated thin-film
resistors.
Portl
Fig. 4.1 Photom icrograph and the equivalent circuit of the thin-film
resistors.
4.3 Implementation of Capacitors
A capacitor provides an open circuit at DC and a positive susceptance at RF
frequencies, and is typically implemented by interdigitated and m etal-insulator-metal
52
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600
4
E
W = 1 0 |im
*
W =20nm
4
W =30nm
O 400-
(D
O
c
ca
x
OT
m 200
DC
(D
y
-
0
0
50
100
150
200
Length (pm)
Fig. 4.2 The extracted resistance o f the thin-film resistors with varying
geometry.
(M3M) structures. Ideally, a capacitor is a lossless lumped com ponent and its susceptance
increases linearly with frequency. In reality, however, it has a finite Q-factor and resonant
frequency due to parasitics. Thus, the frequency response of a capacitor needs to be
characterized for circuit applications.
4.3.1 Interdigitated capacitors
The interdigitated capacitor can be implemented by a single m etalization scheme. The
capacitance is formed by the fringing fields coupling through the gap o f two
interdigitated conductors, and is suitable for applications where the capacitance required
is less than 1.0 pF. Assuming the dimensions of the interdigitated structure are much
smaller than the wavelength at the operating frequencies, the interdigitated fingers can be
represented by an effective distributed shunt admittance across the two terminals. A
com plete analysis o f the interdigitated capacitors has been reported by Alley [64].
53
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
For 10 |im width, 5 pm spacing and a finger length of 60 pm , interdigitated
capacitors with finger num ber 4, 6, and 8 are examined. Figure 4.3 shows a
photomicrograph and a equivalent circuit of the interdigitated capacitor, where C is the
capacitance, Ls, Rs and Cp are the parasitic inductance, resistance and capacitance,
respectively. S-param eter measurements have been performed on the interdigitated
capacitors, and the extracted parameters of the equivalent circuit are listed in Table 4.3.
Since the capacitance com es from the edge-coupled fields, high charge and current
concentrations near the edges tend to limit the Q-factor. Figure 4.4 shows the Q-factor of
the fabricated interdigitated capacitors versus frequency. The Q-factor obtained from the
measurement ranges from 5 to 15 at X-band.
4.3.2 Metal-insulator-metal (MUM) capacitors
An M IM capacitor is realized by sandwiching a dielectric layer in between two
parallel conductor plates. In MMIC applications, the dielectric thickness norm ally used is
0.05 to 0.5 Jim depending on the capacitance required and consideration o f dielectric
breakdown. Materials frequently used as a dielectric layer in MIM structures are listed in
Table 4.4.
Fingers
C (pF)
Rs (&■)
Ls (pH)
CP[ (fF)
C P2 (fF)
4
0.26
0.27
87
2.2
8.2
6
0.32
0.13
56
1.3
5.6
8
0.37
0.17
59
3.2
7.7
Table 4.3 The equivalent circuit parameters of the fabricated inter­
digitated capacitors.
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
<z>
Port2
l&ya WD33
2- 18KU.
Fig. 4.3 Photomicrograph and the equivalent circuit o f the interdigitated
capacitors.
25
20
£ 15
10
2-finger
4-finger
6-finqer
0
0
20
10
30
40
Frequency (GHz)
Fig. 4.4 The extracted quality factor of the interdigitated capacitors with
various finger numbers.
Dielectric material
Relative dielectric constant
S i0 2
4-5
Si3N4
6-7
Ta2C>5
20-25
a i 2o 3
6-9
Polyimide
3-4.5
Table 4.4 Frequently used materials for MUM capacitors.
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Portl
Fig. 4.5 Photomicrograph
capacitors.
and the equivalent circuit o f the M IM
Figure 4.5 shows a photom icrograph and equivalent circuit o f a M IM capacitor,
where C and G are the capacitance and conductance from the insulator layer,
respectively. Rs and Ls are the parasitics arising from the conductor plates, and the
parasitic capacitance to ground is presented by Cp. At low frequencies, the M IM structure
behaves as a capacitor with a positive susceptance. The capacitance deviates from its
original value as frequency increases, and self-resonance takes place at the resonant
frequency (Do due to the parasitic inductance Ls, causing a change o f sign in susceptance.
Therefore, the effective capacitance below the resonant frequency is approxim ated by
(4.3)
and the Q-factor o f the M IM capacitor is given by
(4.4)
Q=(.Qc + Qd)KQcQd)
■c*Z'd> »
where Qc = 1/(a>RsC) and Qd = 1/tan S are the quality factors accounting for conductor
and dielectric losses, respectively. The Q-factor can be obtained experim entally from the
admittance matrix parameter Yi i as
Q = Im(Tj, )/R e(T,,)
(4.5)
56
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To characterize MIM capacitors, a PECVD SiCK layer with a thickness o f 0.25 pm
has been used as the insulator layer. Capacitors with various areas have been fabricated
and characterized by the S-parameter measurem ent from 2 to 40 GHz. The extracted
parameters for the equivalent circuit are tabulated in Table 4.5, and the extracted
capacitance and the related Q-factor versus frequency are plotted in Fig. 4.6.
4.4 Implementation of MMIC Inductors
Structures frequently used for planar inductor implementation include highimpedance line sections, meander lines and spiral inductors. Both high-im pedance line
sections and m eander lines only require a single metalization scheme, however, they can
only be effectively used for inductance values less than 1 nH. Hereby, the work will be
concentrated in the implementation of spiral inductors for microwave applications.
4.4.1 Spiral inductors
For a rectangular spiral inductor with a coplanar ground, the design parameters as
shown in Fig. 4.7 include number o f turns
(N ),
inner/outer diameter
( D j / D 0) ,
line width
(W) and line spacing (S). Such an inductor may be analyzed as a tw o-port network and
can be modeled by the equivalent circuit as shown in Fig. 4.8 (a), where L is the
inductance and Rs is the series resistance due to conductor losses and dissipation from the
induced eddy currents in the substrate. C 0 and Cp represent the parasitic capacitance
between the loops and from the loops to the ground. To minimize the substrate loss, a
high-resistivity Si substrate is chosen for the fabrication, thus m inim izing the loss due
57
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4
40
Capacitance
u_
Q.
CD
CO
o
Resonant frequency
3
30
-3 0
3
{D
3
Tl
—
t
-20 X2
C
CD
3
O
*<
10
Q
X
CD
O
C
co 2
'o
CO
Cl
co 1
O
CD
-
N
0
0
5000
10000
20000
15000
C apacitor Area (pm2)
(a)
100
C =0.49
C =0.65
C =0.80
C =0.94
C =1.08
C=1.2 2
C =1.37
C=1.51
o
co
LL.
O
40-
0
5
10
15
20
pF
pF
pF
pF
pF
pF
pF
pF
25
Frequency (GHz)
(b)
Fig. 4.6 (a) The extracted capacitance and (b) quality factors of the MIM
capacitors.
Area
C (pF)
R*(Q)
Ls (pH)
G (1/GQ)
C pi (fF)
CP2 (fF)
40x90pm 2
0.71
0.87
61
0.53
11.2
24.9
65x90pm 2
1.28
0.66
74
0.42
28.4
11.4
90x90pm 2
1.65
0.61
86
0.13
22.7
27.5
115x90pm2
2.21
0.44
91
0.12
19.3
30.9
Table 4.5 The equivalent circuit parameters o f the fabricated MIM
capacitors.
58
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to the finite substrate resistance and eddy currents. From the sim plified equivalent circuit,
the input impedance is given by the inverse o f the adm ittance m atrix param eter as
1
Yu
K
, . L(1—(D2LC) —R fC 2
(1 —o)zL C )2 + a f R 2C 2
(\-Q )2L C )+ co2R 2C
where C=C0+Cpi. The spiral structure can be used as an inductor only for frequencies
below the structure’s resonant frequency, which can be obtained analytically by zeroing
the imaginary part o f 1/Y n . Equation (4.6) indicates that the higher the inductance, the
lower the resonant frequency.
J
M
r
I
a
I
Di
S
Do
W
Fig. 4.7 The design o f a rectangular spiral inductor.
o
Portl
T
I
I
Rc
'p-\
I
<=>
Port2
'P2
Fig. 4.8 T he equivalent circuit of the spiral inductors.
59
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Another important issue to be considered in circuit design is the Q-factor. The
definition o f the Q -factor is given by
to(l!Y A = ^ L _ o r W
Red/S',,)
R,
R,
At low frequencies, the Q-factor can be approximated by (coL)/Rs , and its value first
increases with frequency. However, the second and the third terms in (4.7) dominate at
higher frequencies, causing Q to decrease with frequency. The Qmax is defined as
maximum Q-factor at f r e q u e n c y /g ^ .
4.4.2 Micromachined structure for spiral inductors
Since the roll-off o f the Q-factor and the low resonant frequency o f the spiral inductor
are mainly caused by higher frequency parasitics, one effective technique to improve the
Q-factor and increase resonant frequency is to minimize the parasitic capacitance CQ and
Cp as presented in Fig. 4.8. For a planar structure such as a spiral inductor, the effective
permittivity ( £r_rff) is approximated by (I + £subslrale) / 2 ■ By removing the substrate
material between the lines, s r_cff can be reduced. As a result, spiral inductors with
enhanced Q and increased resonant frequency can be achieved due to the reduction of
parasitic capacitance. Hereby, a micromachined technology is proposed to remove the
substrate material by Si dry etch, and a photomicrograph o f a fabricated spiral inductor is
shown in Fig. 4.9. Spiral inductors with various etch depths have been fabricated and
characterized. M oreover, with a well-calibrated etch profile, an undercut can be
introduced during the dry etch to further remove the substrate material as shown in Fig.
4.10, resulting in a semi-suspended micromachined structure. In this case, an effective
60
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permittivity sim ilar to the suspended structure can be achieved while the spiral structures
are still supported by the substrate for better mechanical stability.
:
MG6
18KU
Fig. 4.9 Photomicrograph of
inductors (N=4.5).
X220
the
100>’tn WD46
fabricated
micromachined
spiral
Metal pattern
Dielectric layer
Si substrate
t
X
High aspect ratio by
anisotropic dry etch
Undercut created by
high-pressure dry etch
Fig. 4.10 Potential etch profiles using a micromachined technology.
61
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4.4.3 Experimental results
On-wafer probing for two-port S-parameter measurements has been performed from 2
to 40 GHz The spiral inductors were also characterized using the one-port impedance by
grounding the second port. The Q-factor is determ ined by the ratio o f the imaginary part
to the real part o f \/Yx, , and the resonant frequency is chosen at the frequency at which
the imaginary part o f 1fYn crosses the zero point.
To investigate the performance characteristics o f this micromachined technology, a
set of inductors with 10 p m line width, 10 p m spacing and 50 p m inner diam eter are used
for the study. During the process, inductor samples with etch depths o f 0, 5, 10 and 20
p m , respectively, are prepared. For a spiral inductor with a turn number o f 3.5, a 20 p m -
deep etch increase the resonant frequency from 18.5 GHz to 25.6 GHz, and the maximum
Q o f 20.2 is observed at 14.5 GHz. The Q-factor o f this inductor with various etch depth
is shown in Fig. 4.11, and it is obvious that both Qmax and fQmax increase as the etch depth
increases. Based on the equivalent circuit shown in Fig. 4.8, the model parameters were
extracted from the S-parameter measurement using HP-EEsof LIBRA. From the
extracted model parameters as shown in Table 4.6, it is observed that the inductance L
and the series resistance Rs are almost independent of the etch depth, however, the
capacitance is reduced significantly due to the reduction of the effective permittivity by
the deep etch. Since the etch was performed not only between the loops, but also in the
area between the spiral lines and the coplanar ground, both C0 and C p were reduced
substantially.
An exhaustive study was undertaken for inductors with different geometry, and the
performance o f this technology is summarized in Table 4.7. As indicated by the
62
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measurements, the deeper the etch, the higher the resonant frequency and the larger the
Q-factor.
25
—
—
20
o
o
£
planar
5 jim etch
10 jim etch
20 jim etch
15
>*
% 10
o
5
0
10
15
20
F re q u en cy (G H z)
Fig. 4.11 The extracted Q-factor of a 3.5 turn spiral inductor with various
etch depths.
Etch depth
L (n H )
R*(Q)
Co(fF)
Cpi (ft*)
C p2 (fF)
0 Jim
1.91
4.2
31.6
2.7
4.9
5 Jim
1.87
4.7
26.4
2.3
3.8
10 Jim
1.93
3.8
21.1
1.4
3.4
2 0 Jim
1.95
4.5
16.9
1.2
2.9
Table 4.6 The equivalent circuit parameters o f the fabricated spiral
inductors (N=3.5).
63
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4.5 Fabrication Technology for the Micromachined Passive Components
Fabrication o f the micromachined passive components starts with a high-resistivity Si
substrate with a resistivity of 2000 Q-cm. A PECVD oxide layer with a thickness o f 0.3
jim is deposited as the isolation layer between the substrate and the first metal layer
(M l), which is used as the lower plate for M IM capacitors and the underpass contact to
return the inner terminal of the coil to the outside. A 0.25 Jim-thick PECVD oxide and a
patterned Ti/Au metal layer are used to define the area for M IM capacitor. A fter an 1 [imthick inter-metal dielectric grown by PECVD, a N iC r layer with a thickness o f 700 A is
Etch
Turns
8 .5
7 .5
6 .5
5 .5
4 .5
3 .5
2 .5
Depth
Inductance
1 4 .7
1 0 .7
7 .6
5 .0
3 .2
1 .9
1 .1
Qim)
(nH)
0
/r e s ( G H Z )
4 .0
5 .5
7 .1
9 .5
1 3 .5
1 8 .5
3 0 .0
Q m ax/
5 .5 /
5 .7 /
6 /
6 .3 /
6 .6 /
7 .6 /
/ qm ax (GHz)
2
2 .5
3
5 .5
6 .5
1 2 .6
5
10
20
f res (GHz)
4 .8
6 .0
7 .5
1 0 .5
1 5 .2
2 0 .4
3 3 .2
Q m ax/
10/
1 1 .1 /
1 1 .7 /
1 2 .6 /
13/
1 3 .4 /
1 6 .6 /
Z jm a x ( G H Z )
2
3
3
4
6 .5
9 .6
1 8 .7
5 .2
6 .5
8 .5
1 1 .5
1 6 .9
2 2 .5
3 6 .6
Q m ax/
1 0 .6 /
1 1 .5 /
1 2 .8 /
1 3 .6 /
1 3 .3 /
1 5 .4 /
2 0 .7 /
fQm ax (GHz)
2
3
3 .5
5 .5
6 .5
1 1 .5
22
/re s ( G H Z )
5 .7
7 .5
9 .7
1 3 .5
2 0 .1
2 5 .6
> 4 0
Q m ax/
1 2 .8 /
1 4 .3 /
1 3 .8 /
16/
1 3 .6 /
2 0 .2 /
31/
3
3
4
6
9 .5
14
23
/re s
(GHz)
m ax
(GHz)
Table 4.7 The Q-factor and the resonant frequency of the fabricated
spiral inductors.
64
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deposited for TFR. The spiral loops and the interconnection are formed by the second
metal layer (M2). Both M l and M2 are evaporated A1 layers with thickness o f 1 (im and
3 (im, respectively. At this point, standard CMOS process steps have been used to
fabricate the inductors. To apply the micromachined structure to the spiral inductor, the
metal layer are covered by a 0.1 um-thick Ni layer which is then used as self-aligned etch
mask. Finally, a 20-fim-deep trench created by RJE using SFg and O 2 gas mixture
completes the fabrication process. The process flow o f the micromachined technology is
shown in Fig. 4.12.
Pad oxide
(PECVD SiOj)
Via (R1E)
Metal 1
Thin-film resistor
(NICr)
MIM insulator
(PECVD SiOj)
Metal 2
MIM capacitor
Substrate etch
(RIE)
Inter-metal dielectric
(PECVD S i0 2)
TFR
MIM
Spiral inductor
Fig. 4.12 The fabrication process for micromachined passive components.
65
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4.6 Summary
For microwave
applications, lum ped passive components including thin-film
resistors, interdigitated capacitors, M IM capacitors and spiral inductors have been
fabricated and characterized from 2 to 40 GHz. A novel m icrom achined technology
proposed in this chapter reduces the parasitic o f the spiral inductor by rem oving substrate
material between the lines, resulting in a significant improvement in resonant frequency
and Q-factor. By applying this technology, etched depth adds one more design parameter
to the spiral inductor that aids one in m eeting circuit requirements for frequencies
through K-band.
66
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CHAPTER V
MICROWAVE PASSIVE INTEGRATED CIRCUITS USING
MICROMACHINED LUMPED COMPONENTS
5.1 Introduction
Transmission lines are widely used in microwave circuits to carry information or
energy from one point to another. Normally, the physical dimension of a transm ission
line is a considerable fraction o f the wavelength at the operating frequency. Therefore,
the transmission line is considered a distributed circuit component, where voltages and
currents can vary in m agnitude and phase along its length.
A TEM
transm ission
line can be characterized by four basic parameters:
characteristic impedance (Zo), the phase velocity (vp), the attenuation constant (a) and the
electrical length. By properly choosing the design parameters, transmission lines can be
used as circuit elem ents for applications such as filters, impedance transformers,
couplers, power dividers and delay lines. Since the dimension of the distributed circuit is
proportional to the wavelength, its size becomes prohibitively large at frequencies below
20 GHz, resulting in a higher cost for MMIC products. Recently, design methodologies
[52]-[56] have been reported for new compact components and circuits. However, the
chip size is still considerably large. A lumped design is favorable considering its sm aller
chip size at those frequencies. Due to the low quality factor (Q) and low resonant
67
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frequency (f^ ) of the lumped components, especially for spiral inductors, most circuit
demonstrations using lumped design concept are confined to frequencies up to a few
GHz. Use o f similar designs at higher frequencies requires high-performance lumped
components, such as those dem onstrated in chapter 4.
5.2 Lumped Equivalent Networks for Transmission Line Segments
The m ost important design parameters of transmission lines used for passive circuits
include the characteristic impedance and electrical length. Given the characteristic
impedance and the electrical length, a lossless transmission line segment can be
represented by an ABCD matrix at its center frequency as shown in Fig. 5.1. The
technique used for a lumped design concept is to replace the transm ission line segments
in a distributed passive circuit with lumped equivalent networks [57]. The simplest forms
o f lumped equivalent networks are T networks and 7t networks which consist of three
lumped passive components as shown in Fig. 5.2. By equating the ABCD matrix of a
transmission line segment to the one of the lumped equivalent networks at the center
frequency, one can have a lumped design for any distributed circuit. The parameters for
the lumped components used in the equivalent networks are given as:
1
,
c o sB i - \
K network: Yal = ---- — —
™ ^ -----n\
— and Yk2
F_, = -----jZ Qsin p i
jZ Qsin p i
(5.1)
T network: Zn = — —— and Zr2 = j^°(cos
—11
1 jsin p i
T1
j sin p i
(5.2)
In the lossless case, the lumped network performs identically to the transmission line
segment at the center frequency, and the characteristics deviate upon moving away from
the center frequency.
68
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By using a single section o f a T or n network to replace a transmission line segment,
the lowest device count can be achieved, and is favorable in terms o f chip size and loss.
However, in many circuit applications, it is common to cascade two or m ore lumped T or
7t networks for broader bandwidth at the expense o f higher loss.
5.3 Wilkinson Power Dividers
In many microwave applications such as power amplifier, mixers and antenna
systems, power dividing/combining is required. W hile there is a variety of power
--------- -------- -------- 1
t
1
■— i—i
i—i— ■
i
i
i
i
i
i
« ,
*
■— i—i
i—«— ■
t 1........................
J «
i
i
B
C D
cos p i
A
-1
jY 0s m p l
jZ 0 sin f i l
cos p i
Zo,/?£
Fig. 5.1 A transmission line segment and its ABCD matrix.
Jt2
B
C D
A
1 + ^22.
-T1
-TI
2 Zr2 +
Z 7*2
2
B
C D
A
-T1
1 + 2 t 2L
-TI
irl
2
jc\
(a)
/rl
(b)
Fig. 5.2 (a) Lumped T network and its ABCD matrix, (b) Lum ped 7t
network and its ABCD matrix.
69
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dividing devices, W ilkinson pow er dividers [58] are especially popular at microwave
frequencies. A two-way W ilkinson power divider provides isolation between ports, and
while lossy in the general case, such a device becomes lossless w hen its output ports are
matched. That is, pow er dissipation only occurs for the reflected pow er resulting from a
mismatch at the output ports. In addition, such a device can be m odified to give unequal
pow er division as well as N-way power division, depending on the application
requirement.
5.3.1 Analysis of Wilkinson power dividers
Figure 5.3 shows a schem atic o f an equal-split two-way W ilkinson power divider
which consists of two quarter-wavelength transmission line segments and a resistor
connecting two output ports. To analyze this three-port network, an even-odd mode
analysis technique [59] is applied as shown in Fig. 5.4.
Even-mode: For even-m ode excitation, Vgl =Vg3 = 2 V . There is no current flowing
through the resistor or the short circuit connecting the inputs because o f equal potential at
both ends. Therefore, it can be bisected with open circuits at these points. The input
(>/2Zn)2
impedance is obtained as Zineven = ------- 2— , resulting in
2Z0
= 0 . Assuming the
traveling wave in the transm ission line segment is V (x )= V * me~Jfix +V~meJPx, at x = 0 ,
v =Kcn+Ken
V~en =
1 - a/2
~
V . At x = ^
=
— 7§z“ '
Then
we
have
V+en= -- ^
, the voltage can be expressed as V2evm = —j y j 2 V .
70
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V
and
Odd-mode: For odd-m ode excitation, V 2 = —Vr3 = 2 V . B ecause there is a voltage null
along the symmetric plane, we can analyze it by bisecting it with grounding the
symmetric point o f the circuit. Again, the input impedance and the reflection coefficient
are given by Zinjmld = Z0, and Todd = 0 . Because of the virtual ground in the symmetric
plane, the voltage at point 2 can be easily obtained as
= 0.
Port 2
Port 1
m
2 Z,
Port 3
4
Fig. 5.3 Schem atic of an equal-split W ilkinson power divider.
A/WV
2Zr
2Z,
x =0
Fig. 5.4 Even-odd mode analysis of the W ilkinson pow er divider.
71
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The input reflection coefficient can be examined by terminating the output ports of
the power divider. Since the potentials at the output ports are equal, the resistor can be
treated as open-circuited. Looking into the input port, it is equivalent to two 2Zo
impedance in parallel, resulting in a matched port at input.
From the above analysis, we have
Su = 0 ,
^22 = ^33 = 0 >
S|2 —Soi
V+V
*^13 —*^31 —
S23 —S 32
~J
fi'
—0 .
Therefore, the S-param eter of a equal-split two-way W ilkinson power divider is given as:
0
S=
V2
~j
.V2
~J
~J
S.
J2
0
0
0
0
(5.3)
5.3.2 Design of lumped Wilkinson power dividers
As shown in Fig. 5.3, the schematic of an equal-split two-way Wilkinson power
divider consists o f two quarter-wavelength transmission segments and a resistor. Another
possible design that provides the equal power dividing characteristics at its center
frequency is to use 270° in electric length instead o f 90° for the transmission line
segments. It is not desirable to use 270° transmission line segments in practical circuit
72
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implementation for a distributed design due to its larger chip size, higher loss and
narrower bandwidth. H ow ever, we would like to explore how it performs in a lumped
form, so both designs using 90° and 270° transm ission line equivalents are included in
this section.
To design a lumped W ilkinson power divider, lumped equivalent networks (T
network or K network) are uised to replace the transm ission line segments w hich can be
either 90° or 270° in electric length. Thus, fo u r different designs of lumped W ilkinson
power dividers have been d eriv ed and listed in T able 5.1.
5.3.3 Experimental results a n d discussion
Among the four differen t lumped designs as outlined in Table 5.1, W PD_1 was
chosen for circuit im plem entation at X-band and K-band due to its minimal chip size and
insertion loss. The micromacihined technology developed for lumped passive com ponents
has been employed for circu it fabrication. Figure 5.5 shows the schematics and
photomicrographs o f the fabricated X-band and K -band power dividers.
Design
Electric length
Equivalent network
WPD_1
90°
7t network
WPD_2
90°
T network
WPD_3
270°
n network
WPD_4
270°
T network
Table 5.1 Lumped, designs for equal-split W ilkinson power dividers.
73
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On-wafer probing o f the Wilkinson power dividers was performed using HP8510B
network analyzer with the S-parameter measurem ent covering the frequency range from
0.5 GHz to 25.5 G Hz. Figure 5.6 shows the S-param eter measurement for the 8.5 GHz
and 20 GHz designs. F or both the X-band and K-band designs, an excess loss better than
0.6 dB at the center frequencies is obtained for 3 dB coupling while the return loss is
better than 15 dB for a bandwidth of 25%. Due to the use o f high-Q inductors, the loss
introduced by the lum ped Wilkinson power divider is even lower than some distributed
designs [55] [60]. The performance of the X-band and K-band W ilkinson power dividers
is included in Table 5.2.
0 ■ 9
L1 C 2 ,
r
Portl
C1
I
I
12 C3 r
I
Port2
R1
■ o
Port3
C1=0.54 pF
C2=0.27 pF
C3=0.27 pF
L1 =1.34 nH
L2=1.34 nH
R1=100fll
(a)
Port2
Portl
Port3
C1=0.22 pF
C2=0.11 pF
C3=0.11 pF
L1 =0.56 nH
L2=0.56 nH
R1=100Q
0002
10KU
XI60 100HB HD46
(b)
Fig. 5.5 Schem atic and photomicrograph o f the lumped W ilkinson power
dividers, (a) X-band design, (b) K -band design.
74
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One of the m ost important reasons for using lumped design is the smaller chip size.
U sing lumped components to replace the transmission line segments, we can reduce the
chip size at 8.5 GHz from over 4 mm in length for a distributed design on silicon, to
850x700 pm 2 for the lumped design (including the pads). The area required o f the divider
itself can even be smaller (less than 300x400 pm 2) when integrated with other microwave
circuits.
Other than a smaller chip size, wider bandwidth is also a potential advantage o f the
lumped design over standard Wilkinson power dividers which are limited by the quarter
co
T3
CM
CM
CO
.- IQ
U
CO’
CM
CO
CM
-1 0
CO
- -1 5 ■
S11
S21.S31
S23
S22. S33
CO
-3 0
0
5
10
15
20
CM
-20
S11
S21.S31
S23
S22. S33
-2 5
0
25
Frequency (GHz)
10
5
20
15
Frequency (GHz)
(a)
(b)
Fig. 5.6 S-param eter measurement results o f the lumped Wilkinson
power dividers, (a) X-band design, (b) K-band design.
fo
Return loss
Return loss
Insertion loss
(GHz)
(Sn [dB])
(Szz, S33 [dB])
(S21, S 3I [dB])
8.5
-24.5
-28.1
-3.57
-14.1
20
-23.5
-20.1
-3.60
-9.6
Isolation
( S 23
[dB])
Table 5.2 Circuit performance of the lumped W ilkinson power dividers.
75
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25
wavelength requirement. However, the advantage o f broadband characteristics for a
lumped design is compromised by the poor linearity o f passive components. The validity
o f replacing the quarter wavelength by K network is based on a constant reactance (coL)
and susceptance (coC). D ue to the finite resonant frequency o f the lumped components,
the inductance and capacitance increase at higher frequencies, the effects of which are
especially significant for spiral inductors with lo w ^ s . The nonlinear characteristics of L
and C values reduce the center frequency and result in a reduction o f bandwidth. By
applying the micromachined technology demonstrated in this work, the spiral inductor
can be operated linearly to higher frequencies with an enhanced Q-factor. Therefore, it
has a direct impact on the circuit performance in terms o f insertion loss and bandwidth of
the power divider.
5.4 Quadrature (90°) Hybrids
A quadrature hybrid is a four-port network providing all ports matched with
directional coupling and isolation at the output ports. The incident power is divided and
fed to the output ports o f through and coupled arms with a 90° phase difference, while the
fourth port is isolated from the input port. This type o f hybrid is often made in microstrip
form and is also known as branch-line hybrid. With a modification of the characteristic
impedance o f the transmission line segments, the quadrature hybrid can be designed for
arbitrary power coupling. It is an indispensable component for applications such as phase
shifts, power amplifiers and balanced-structure microwave circuits.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
5.4.1 Analysis of quadrature (90°) hybrids
A distributed quadrature hybrid as shown in Fig. 5.7 consists o f two pairs o f
transmission line segments (series and shunt arms) with characteristic impedance (Zoi,
Z 02 ) and length (£u h)- Because o f its high degree o f symmetry, any port can be used as
the input port. To analyze this four-port network, even-odd m ode analysis [59] is
employed to bisect the circuit based on its symmetry. Given
y , = Z 0/ Z 01 and
y% —Z q/ Z vl >the circuit is analyzed as the following.
Even-mode: By applying even-mode excitation at port 1 and port 4, the circuit can be
bisected from the plane of symmetry with open circuits in the middle o f the shunt arms as
shown in Fig. 5.8(a). Thus,
(5.4)
3>a
.even
cot p £ x+ j y l
(5.5)
.even
(5.6)
.even
The conditions for all port matched ( ycxvm = 1) are given as the following
yf + 2y,y2 cot J3lxtan
(5.7)
y xcot/3£x- y I2y2t a n - ^ 2-+ 2 y 12y2c o t2 ft£ xt a n ^ ~ + y2 t a n - ^ 1
(5.8)
77
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Odd-mode: W hen odd-mode excitation is applied to port 1 and port 4, it is equivalent
to virtually grounding the shunt arms from the middle due to the symmetry o f the circuit
as shown in Fig. 5.8(b).
y.w ,u =1-/Vi c o t-^ .
(5.9)
y t cot p i , + j y Aj>dJ
yCM = y BMd - j'y2 tan
Bi
(510)
.
(5-i i)
Again, the conditions for all port m atched ( y Cjldd = 1) are given as:
y,2 —2y, y 2 cot p i , c o t- ^ ^ — y2 cot2
y,3cot
— 1 = 0,
(5.12)
, + y 2y2c o t-^ ^ - —2y 2y, cot2 P I , cot-^y2-—y2 c o t - ^
(5.13)
—3y ,y2 c o t , cot 2 ^ 2 —y 2cot3~ ^ 2- —y , cot
,= 0•
Based on the above analysis, the four-port network is matched at all ports if the
following conditions are valid:
t a n ^ - = ± l,
2
(5.14)
cot p t x = 0 ,
(5.15)
( |o . ) 2 = (Z o_) 2 + 1
( 5 16)
A n
02
From (5.14) and (5.15), the electric length of the series and the shunt arms can be either
90° o r 270°. Therefore, four different prototypes derived from the electric length
78
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conditions have been analyzed separately to examine the full extent of the quadrature
hybrid design.
5
2
Prototype A: (/?£, = — and /?£, = —)
T
T
even
«</</
tt
i
J
r
Vl
T
V *
Tr
z.
^
-
y i
y A,even
Jf
Jl
~ J 'y '
1
1 +
-
«~
3W
,
-
’
73^2
^ 1
.
i-/y 2
*
■S1, = 2^ T - . + T » " ) = 7l +^ y2
T '
<5' 17)
■ S „ = ^ -( T „ „ - T ,^ ) = ^ - .
2
l + y.
(5.18)
Prototype B: (/?<?, = — and
4
T rvffn-
t
T »• -
^
- y2 _
odd
i./
y'
-
vx
-
y^uvo,
_
y AjldJ
=— )
4
‘
t
.
’
-m
1+ jy 2 '
S * = U T„ „ + T , ^ ) = - ^ V ,
2
l + y,
(5.19)
S3, = 3-cr™ , - T^ , )
2
(5.20)
= .
l + y,
•25
2
Prototype C: (/% , = — and fit-, = —)
4
“ 4
TAev«i -
X7 -
V z
jJ
y '
-
i ,
.
1 + 7y2
»
79
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Prototype D: (/ft?, = — and 0E-, = — )
even
.even
: y. _
y A«jj
m
1+Jy 2 '
(5.23)
Revert + ^ndd )
(5.24)
even
For a coupling ratio k = |S 3,/S 2I| = y 2 at the outputs, the characteristic impedances are
given by Z^, = Z Q/ k and Z0I = ^(Z ^Z q ) / (Z^> + Zq ) . A phase difference o f 90° can be
obtained between the output ports (port 2 and port 3), where port 3 is leading in phase for
prototypes B and D, and lagging for prototypes A and C.
5.4.2 Design of lumped quadrature (90°) hybrids
A sim ilar technique as used in designing the W ilkinson pow er dividers is applied to
the design o f the quadrature hybrids. Again, lumped T or 7t networks have been em ployed
to replace the transmission line segments in the four prototypes o f the distributed designs.
80
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Table 5.3 concludes all sixteen lum ped designs for a 3 dB quadrature hybrid. T he sixteen
lum ped designs provide the flexibility for circuit implementation, and the final choice is
m ade based on the application requirement and the availability o f the lumped components
at the operating frequencies.
Zoi’ P i^i
O
Portl
HO
—o
Port2
1A
Z qt>P t^2
2B
2A
^iA’ T1b: series arms
T2A, T2B: shunt arms
IZ qz P ^ 2
1 1B
CD-
o Port4
- o
Port3
Z0l,
Fig. 5.7 Schematic of quadrature (90°) hybrids.
yc
yB
yA
a— t
yc
+1/2
^ Teven
Open-circuited stubs
—>
Short-circuited stubs
+ 1/2
- >
yB yA
o
■
(a)
1/2
L J_
(b)
Fig. 5.8 Even-odd mode analysis of quadrature hybrids, (a) Even-mode
excitation, (b) Odd-mode excitation.
81
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■odd
5.4.3 Experimental results and discussion
The first four designs in Table 5.3 have been chosen for circuit implementation due to
the superior circuit performance based on com puter simulations. Since only Tt networks
have been employed for all transmission line segments, the shunt lumped com ponents at
the ports can be merged at the center frequency. Due to the lowest device count made
Prototype
Series arm
Shunt arm
length
equivalent
H 90_l
A
90°
7t network
90°
H90_2
B
90°
it network
270°
7t network
H90_3
C
270°
it network
90°
it network
H90_4
D
270°
it network
270°
K network
H90_5
A
K network
90°
T network
H90_6
B
7t network
270°
T network
H90_7
C
270°
Tt network
VO
i 9
equivalent
T network
H90_8
D
270°
7t network
270°
T network
H90_9
A
90°
T network
VO
o0
length
so
oo
Lum ped
so
O0
Electric
Tt network
o
B
90°
T network
270°
K network
H 9 0 _ l1
C
270°
T network
90°
Tt network
H90_12
D
270°
T network
270°
Tt network
H90_13
A
o0
Lumped
SO
Electric
T network
H90_14
B
SO
Design
H90_15
C
H90_16
D
network
270°
T network
270°
T network
90°
T network
270°
T network
270°
T network
SO
T network
------
T network
O0
o'
Os
o0
l
k
Table 5.3 Lumped designs for the 3 dB quadrature hybrids.
82
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possible with this configuration, these designs are favorable in terms of chip size and
insertion loss for circuit applications.
Design H 90_l through H90_4 have been fabricated using the micromachined
technology developed for passive components; schematics and photomicrographs o f the
fabricated circuits are shown in Fig. 5.9. To verify the circuit performance, on-wafer
probing S-parameter measurement has been performed on the quadrature hybrids. Figure
5.10 shows the measured S-parameters of the hybrid designs.
C1
C2
P ortl
Port2
12
O
i r » \
Port4
-o
Port3
C3
C4
P ortl
I00)un
^
X -b an d D esig n (f0=8.5GHz)
L1=L2=0.656 nH
L3=L4=0.929 nH
C 1=C2=C 3=C 4=0.9 pF
X -band D esig n (f0=8.5G Hz)
L1=L2=0.656 nH
0 1= 0 2 = 0.3 75 pF
C 3=C4=C5=C6=0.155 pF
Port4
(a)
Port2
■
Portl
m
=:c3
Port3
X -b an d D e sig n (f0=8.5GHz)
L1=L2=0.929 nH
L3=L4=L5=L6=2.24 nH
C 1=C 2=0.53 pF
(c)
Port4
X -band D esig n (f0=8.5G Hz)
L1=L2=L3=L4=0.385 nH
C1 =C2=0.53 pF
0 3= 04= 0.375 pF
>L4
(d)
Fig. 5.9 Schematics and photomicrographs of the lumped quadrature
hybrids, (a) Design H 90_l. (b) Design H90_2. (c) Design
H90_3. (d) Design H90_4.
83
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In design H 90_I, the series and shunt arms o f the quadrature hybrid are replaced by
low-pass 7t networks, resulting in a low-pass frequency response for the through and
coupling ports. Therefore, a flat coupling characteristics at the output ports can be
obtained with a phase difference of 90°. The bandwidth defined by 15 dB return loss is
6.5% , and an isolation o f 20 dB is provided at the center frequency. As shown in the
schematic o f design H90_2, series and shunt arms are replaced by low-pass and high-pass
k networks, respectively, resulting in a low-pass characteristic o f S 21 and a band-pass one
of
S 31.
Ideally,
S 21
and
831
should be equal in magnitude (-3 dB) with a phase difference
0
0
180
T)
CD
■5
-45 g
■5
CO
CO
CO-10
co
-90
10
-
15
- 45
90
CO
co
CO
-1 3 5
-20
-20
■180
0
5
10
15
0
20
5
10
15
20
Frequency (GHz)
Frequency (GHz)
(a)
(b)
180
2
m
■30 8
co
s-10
CO
CO-15
co
co
■60
90 s
•90S.
■20
45
-120
0
5
10
15
20
-
Frequency (GHz)
20 '
5
10
15
Frequency (GHz)
(d)
(C)
Fig. 5.10 S-param eter measurement results for the lumped quadrature
hybrids, (a) Design H 90_l. (b) Design H90_2. (c) Design
H90_3. (d) Design H90_4.
84
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20
o f 90° at the center frequency. However, the measurement shows an extra insertion loss
o f 1.5 dB and a phase deviation of 13° due to the parasitics o f the lum ped components.
By replacing the series and the shunt arms with high-pass and low-pass 7t networks,
respectively, a high-pass S 21 and a band-pass S31 can be obtained in design H90_3.
Compared with the perform ance of design H90_2, similar phase deviation and insertion
losses are observed in the S-param eter measurement. In design H90_4, all transmission
line segments in the branch-line hybrid are replaced by high-pass 7C networks as can be
seen in the schematic. Therefore, both S 21 and S 31 show high-pass characteristics in
frequency domain. At the center frequency of 8.5 GHz, the insertion losses o f S 21 and S 3 1
are 5.0 and 5.3 dB, respective, with a phase difference of 90°.
To summarize the perform ance o f the fabricated quadrature hybrids, the S-parameter
measurements at the center frequency o f 8.5 GHz are listed in Table 5.4. Each design of
the lumped quadrature hybrids has its unique characteristics in term s o f frequency
response, insertion losses, isolation, bandwidth and phase difference. Therefore, the
fo = 8.5 GHz
H 90_l
H90_2
H90_3
H90_4
Return loss (Su)
18 dB
19 dB
21 dB
18 dB
Insertion loss (S 21 )
4.6 dB
4.9 dB
4.5 dB
5.0 dB
Insertion loss (S 31 )
5.2 dB
4.3 dB
4.2 dB
5.3 dB
Isolation (S 41 )
20 dB
18 dB
19 dB
21 dB
Phase(S3i/S2i)
-90.3°
77°
1
00
0
0
choice can be made based on the requirement of the circuit applications.
89°
Bandwidth
6.5 %
10
%
11
%
6 .5 %
(15 dB return loss)
Table 5.4 C ircuit performance o f the lumped quadrature hybrids.
85
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5.5 180° hybrids
In a planar form , a 180° hybrid is typically implemented by a ring hybrid or rat-race.
This four-port netw ork provides in-phase coupling as well as out-of-phase coupling at the
output ports depending on how the signal is applied to the network. The signal applied to
port 1 will be equally split into port 2 and port 3 in the same phase with an isolation at
port 4. On the other hand, signal applied to port 4 will be split into two equal components
with a phase difference o f 180° at port 2 and port 3. Due to its phase property, a 180°
hybrid is frequently used to generate the sum and the difference o f two R F signals in
circuit applications.
5.5.1 Analysis of 180° hybrids
Figure 5.11 shows the schematic of a ring hybrid, which consists of four transmission
line segments connecting the four ports. Transmission line segments T ia, Tib ana T ic are
identical in length {£ i) with a characteristic impedance of V2Z0. To has a different length
(12 ) with the same characteristic impedance. Two different prototypes o f the distributed
ring hybrids are presented as the following:
Prototype A: In a typical design,
i and pfo are chosen as
Using even-odd m ode analysis, the S-parameters of a 3 dB 180° hybrid at the center
frequency can be expressed as:
86
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0
5=
1 1 0
1 0
0 - 1
1 0
0
(5.25)
1
0 - 1 1 0
Prototype B: It is also possible to construct a 180° hybrid by choosing the electrical
lengths o f the transmission line segments as:
4
From even-odd mode analysis, the S-parameters has the following form:
S =
1
1 0
0
0 - 1
0
0
(5.26)
1
0 - 1 1 0
5.5.2 Design of lumped 180° hybrids
Based on the two prototypes derived for 180° hybrids, lumped designs can be
Z0l,
O
—
Portl
Z 0I,
-
T.1A
1B
~^2
o
Port2
\Z q2> @2^2
T1C
o
Port4
- o
O
Z 0l,
Port3
Fig. 5.11 Schematic of 180° hybrids (ring hybrids).
87
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implemented by replacing the transmission line segments with equivalent n or T
networks. Table 5.5 includes eight different designs for lum ped 180° hybrids. For circuit
implementation, choice o f the appropriate configuration can be made based on circuit
requirements such as chip size, insertion losses, return losses, isolation and phase
considerations.
5.5.3 Experimental results and discussion
Among the designs listed in Table 5.5, the first two have been chosen for circuit
implementation due to the lowest device count. Since only 7C networks have been
employed in these two designs, the shunt components can be merged at the ports. The
device count is further reduced because the shunt inductive and capacitive elements
cancel each at the center frequency at port 2 and port 4.
Design
Prototype
t2
T ia, T ib, T ic
Electric
Lumped
Electric
Lum ped
length
equivalent
length
equivalent
H180_l
A
90°
K network
270°
7t network
H180_2
B
270°
it network
90°
K network
H180_3
A
90°
7t network
270°
T network
H180_4
B
270°
7t network
90°
T network
H180_5
A
90°
T network
270°
K netw ork
H180_6
B
270°
T network
90°
7t network
H180J7
A
90°
T network
270°
T network
H180_8
B
270°
T network
90°
T network
Table 5.5 Lumped designs for the 180° hybrids.
88
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The lumped designs for 180° hybrids have been fabricated using the micromachined
technology developed for passive components. Figure 5.12 shows schematics and
photomicrographs o f the fabricated circuits. On-wafer probing S-parameter measurement
has been performed on the fabricated hybrids. Both in-phase and out-of-phase coupling
are included in the m easurem ent (as shown in Fig. 5.13) to characterize the circuit
performance.
As can be seen from the S-parameter measurements, design H180_l shows a lowpass response for in-phase coupling, and the measured S 21 and S 31 at the center frequency
(9.5 GHz) are -4.3 and -4 .6 dB, respectively. The out-of-phase coupling occurs when the
signal is applied to port 2 or port 4, and a high-pass characteristic of S 24 with the value of
—3.6 dB at the center frequency is observed in the measurement. Due to the parasitics and
fabrication error, the phase deviations for in-phase and out-of-phase coupling are 6 .6 ° and
4°, respectively. Design H180_2 exhibits a high-pass characteristic for in-phase coupling
and a low-pass response for out-of-phase coupling in frequency domain. The insertion
losses (S 21 and S 3 O at the center frequency are about 0.5 dB higher than design H 180_l,
•C 2
C3 4 .
L1
L3I
-o
-o
L2
P o rtl
L2
P o rtl
P ort3
t
L3
O
Port2
P o rt4
P o rt2
C1
X -b a n d D e sig n
L1 =L2=L3=1.323 nH
C1 = 0 .5 2 8 pF
C 2 = C 3 = 0 .2 6 4 pF
Port3
C2
C1
C 3!
L1
-o
P o rt4
X -b a n d D e s ig n
L1 = 1 .3 2 3 nH
C 1 = C 2 = C 3 = 0 .2 6 4 p F
L 2=L 3=0.666 p F
(a)
(b)
Fig. 5.12 Schematics and photomicrographs of the lumped 180° hybrids,
(a) Design H 1 80_l. (b) Design H180_2.
89
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03
TJ
-<3CO
CO
0
60
03
C
O
■5
-10
03
-15
<M
-20
-3 0
CO
CO
CO
S11
S21
S41
S31
Z(S31/S21)
03
-25
-0
c l
CD
CO
-30
-30
5
20
10
ro
CD
CD
Frequency (GHz)
m
g.
o
03
CM*
■
'1-
270
S22
S12
S32
S42
Z(S42/S12)
CM
CO
-10
" 180
90
03
CM
CO
CO
CO
-20
—90
CO
CM*
CM
CO
03
-30
10
5
Q.
H}——— "-180
CD
CO
---------- 1—270
CD
CD
20
Frequency (GHz)
(a)
CD
■o
0
03
C/3
CD
CO
-- 3 0
-10
CO
S11
S21
S41
-20
CO
--6 0
Q_
__ 331
CD
CO
Z(S31/S21)
CO
CO
Si
ro
CO
CM
CO
-30
0
-n
-90
5
10
15
CD
CD
20
Frequency (GHz)
CD
TD.
o
270
CM
CO
CO
cm “
- 180
cn
CD
-10
CM
S22
S12
S32
S42
^(S42/S12)
▼
— -20
CO
cm*
CM
-30
CO
- 90
4*
co
-- 9 0
ro
CO
CO
03
--1 8 0
Q.
CD
CQ
20
-270
3
CD
Frequency (GHz)
(b)
Fig. 5.13 S-parameter measurement results for the lumped 180° hybrids,
(a) Design H180_1. (b) Design H180_2.
90
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however, it provides a w ider bandwidth which is essential for broadband applications.
To summarize and com pare the performance of the fabricated 180° hybrids, the Sparam eter measurement results are listed in Table 4.6. Originally, both 180° hybrids were
designed to be centered at 8.5 GHz. However, the center frequency o f design H180_l is
shifted to 9.5 GHz in the m easurem ent due to fabrication error and the parasitics o f the
lumped components. M inor adjustm ent in the passive components has to be done in the
design to compensate the shift in center frequency.
H180_l
H180_2
9.5 GHz
8.5 GHz
Return loss (Sn)
19 dB
16 dB
Return loss (S22 )
28 dB
23 dB
Insertion loss (S 21 , S 34 )
4.3 dB
4.9 dB
Insertion loss (S 31 )
4.6 dB
5.0 dB
Insertion loss (S42 )
3.6 dB
3.5 dB
Isolation (S41 )
28 dB
24 dB
Phase(S 3 i/ S 21)
6 .6 °
- 12°
Phase(S24/ S 34)
-176°
173°
Bandwidth
1 0
%
30%
Center frequency (Jo)
(15 dB return loss)
Table 5.6 Circuit perform ance of the lumped 180° hybrids.
5.6 Summary
Using T or 7t equivalent networks to replace the transm ission lines in distributed
designs, microwave passive circuits can be implemented w ith lum ped components. In
91
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this chapter, a systematic analysis and design techniques have been developed to explore
the lumped design to its full extent. Using the process technology developed for highperformance lumped components, microwave circuits such as W ilkinson power dividers,
quadrature hybrids and 180° hybrids have been designed and fabricated at X-band and Kband. In addition, S-parameter measurements have been made to characterize their circuit
performance for MMIC applications.
92
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CHAPTER VI
DESIGN AND FABRICATION OF Si-BASED
MONOLITHIC MICROWAVE INTEGRATED CIRCUITS
6.1 Introduction
In the past few decades, high-performance microwave systems have been dominated
by waveguide components and hybrid technologies. However, use o f these components
in mass production o f commercial products has been impeded due to the excessive
expense incurred in the fabrication of precision machined parts, and by the laborintensive assembly o f the waveguide and the hybrid integrated circuits. W ithin the fast
growing wireless communication market, reliable microwave systems with high
performance and low cost are required. As a result, monolithic technology has been
avidly pursued for implementation of microwave integrated circuits, due to its potential
as a low cost solution.
The concept o f using silicon as the base material for m icrowave integrated circuits
was first discussed in 1965 [10]. Owing to the availability o f high-resistivity substrates
and high-performance heterojunction devices, nowadays, Si-based M M IC ’s exhibit a
great potential in communication systems. In the past few years, M M IC’s such as
amplifiers, oscillators, VCO’s, switches and mixers have been dem onstrated using SiGe
H B T’s. However, most o f the circuits have been implemented with distributed designs,
93
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leading to a relatively large chip size. To further reduce chip size and lower the cost of
microwave integrated circuits, SiGe M M IC’s using lumped passive components have
been investigated in this work.
6.2 Fabrication Technology for Si-based MMIC’s
The fabrication technology for Si-based M M IC’s demands integration o f the process
steps for SiGe HBT devices with those for micromachined passive components. The
fabrication starts with epitaxial growth o f an HBT structure on high-resistivity Si
substrates as described in section 2.2.8 and section 3.2.1, the details o f which depend on
the device performance required for circuit applications. The process steps developed for
SiGe HBT technology are adopted for transistor fabrication to the step prior to device
passivation. Up to this point, the high-resistivity Si substrate is exposed for area outside
the active devices. Then the process technology developed for micromachined passive
components is used to complete the circuit fabrication. The PECVD SiO i layers required
for passive components are also used as the device passivation while the interconnection
metalization is shared for both active devices and passive components. Since the spiral
inductors and the MIM capacitors are designed to be self-aligned to the deep RJOE
process, which creates the micromachined structures, only the area for transistors and
thin-film resistors needs to be protected by photoresist during the etch. It should be noted
that the process technology developed in this work can be adopted for both HBT
structures as described in chapter 2 and chapter 3. The complete process flow for Sibased M M IC’s is shown in Fig. 6.1.
94
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Pad oxide
(PECVD SiO,)
Em itter metal
OR
M etal 1
Em itter m esa
Base mesa
Base metal
Device isolation
Base m esa
Base/subcollector
exposure (KOH)
Collector m etal
Base/collector metal
M IM insulator
(PECVD S i0 2)
M IM capacitor
Inter-metal dielectric
(PECVD S i0 2)
Device isolation
Via (RIE)
Thin-film resistor
(NICr)
M etal 2
Substrate etch
(RIE)
Fig. 6.1 The process flow for SiGe M M IC fabrication.
6.3 Amplifier Design and Implementation
The first effort on Si-based MMIC implementation undertaken in this work is the
design and fabrication o f X-band multi-stage amplifiers for low-power applications
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[61][31]. SiGe HBT’s with emitter area o f 5x5 mm2 as developed in chapter 2 are
investigated and employed for circuit designs.
6.3.1 Small-signal analysis for amplifier design
F or small-signal am plifier designs, the transistors are biased for optim um frequency
response, exhibiting S-parameters at the center frequency o f 8.5 GHz as:
S=
0 .2 7 Z -8 1 .8
0.078Z53.8
2.25Z86.8
0 .7 6 Z -1 2 .0
From S-param eter measurement, the device is unconditionally stable based on (2.18) and
(2.19), implying that the maximum power gain can be achieved with simultaneous
conjugate match at input and output o f the transistor. Simultaneous conjugate match is
provided by [62]
r; = s + M iL
(6.i)
r ; = s„ +
(6. 2)
i-s „ rL
and
- i- s ur5
By solving (6.1) and (6.2), the source impedance r Ms and load impedance TMl required
for simultaneous conjugate match can be expressed as
Bx± J b ? —4[C,|2
“ =
2C,
2 C,
( 6
’
' 3 )
(6'4)
where
96
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B2 = l + [ S „ [ 2 —|S n |2 —|A |2
C , = S ',, — A S 22
C2 =
52 2 -
A
5*.
Based on S-param eter measurement, r Ms and T ml are 0.19^184° and 0.74Z160,
respectively. For m ulti-stage amplifier designs, matching networks using lumped passive
components are added at input, output and between stages to achieve simultaneous
conjugate match for all transistor stages. As a result, maximum power gain can be
achieved with low reflection coefficients at input and output o f the amplifiers.
6.3.2 Implementation of single-stage amplifier
Figure 6.2(a) show s a schematic of the single-stage amplifier design. In this design, a
common-emitter SiG e HBT is employed as the amplifying stage while passive networks
(L i,
Q ) and
(L 2 , C 2 )
are used as input and output matching, respectively. The
D C
bias for
the base o f the transistor is fed through a coplanar pad at the input port. As the capacitor
C3
provides an RF short to the ground, collector bias voltage is applied from the
D C
pad
without affecting the load impedance. Equivalent circuits, which are extracted from
measurements to characterize the active and passive devices, are employed for circuit
design and simulation.
A photomicrograph o f the fabricated single-stage amplifier is shown in Fig. 6.2 (b).
Due to the application o f lumped components for the amplifier design, the chip size
(0.75x0.65 mm2) is estimated to be less than 20% o f the corresponding design using
97
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distributed matching networks. Figure 6.3 shows the power gain along with the input and
output return of the fabricated am plifier. At a frequency o f 10 GHz, the amplifier exhibits
a power gain o f 4 dB. The output return loss shows values better than 20 dB, while the
input return loss has a value o f 7 dB around the center frequency.
91—
O
C,
Output
< z>
c,
c,
c3
0.20 pF
0.13 pF
0.78 pF
L,
Li
0.51 nH
1.80 nH
(a)
(b)
Fig. 6.2 (a) Schematic o f the single-stage amplifier, (b) Photomicrograph
o f the single-stage amplifier.
98
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•a
-10
o
-15
-20
-25
5
10
7.5
12.5
15
Frequency [GHz]
Fig. 6.3 S-param eter measurement results o f the single-stage amplifier.
6.3.3 Implementation of two-stage amplifier
A schematic and the design parameters o f the two-stage amplifier are shown in Fig.
6.4 (a). In this design, LC networks (L[, Q ) and (L 3, C 3 ) w ith low-pass characteristics are
used for input and output matching. As a result, the DC bias for the base of Qi and the
collector of Q 2 are applied through the input and output ports, respectively. L 2 and C 2
provide the inter-stage m atching as well as a bias netw ork and DC block between the
stages. The D C bias for the collector of Qi is applied through L 2 while the bias for the
base o f Q 2 is provided through a voltage divider (R t and R 2). Figure 6.4 (b) shows a
photomicrograph o f the fabricated two-stage amplifier which has a chip size of 0.98x0.80
mm". The S-parameter measurement results o f the two-stage amplifier are shown in Fig.
99
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6.5. A maximum power gain of 5.7 dB is obtained at 10 GHz with input and output return
loss between 5 to 10 dB.
_C—
H
Output
1r 1
c,
c2
c3
0.11 pF
0.18 pF
O.lOpF
c4
Li
Li
0.78 pF
0.37 nH
1.55 nH
l3
Ri
Rz
1.20 nH
400 Q
1400 n
(a)
(b)
Fig. 6.4 (a) Schematic o f the two-stage amplifier, (b) Photomicrograph
o f the two-stage amplifier.
100
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10
5
0
•5
■22
-10
5
7.5
10
12.5
15
Fig. 6.5 S-parameter measurement results o f the two-stage amplifier.
6.3.4 Implementation o f three-stage amplifier
Similar techniques have been utilized for three-stage amplifier design. Figure
6 .6
(a)
and (b) show a schematic diagram and a photomicrograph of the fabricated amplifier,
respectively. This design is actually an extension of the two-stage design by inserting an
additional amplifying stage and inter-stage matching network. In order to adjust the DC
bias to achieve best circuit performance, separate DC pads are employed for power
supply Vcci and VCC2 - Computer simulation using the equivalent circuits o f the active
and passive components was employed to verify the design before circuit fabrication. The
chip size o f the fabricated circuit is 1.15x0.84 mm2.
As evident from the S-parameter measurements shown in Fig. 6.7, the three-stage
amplifier provides a maximum power gain of 12.6 dB at 11.1 GHz with input and output
return loss better than 10 dB. As can been seen from Fig. 6.7, the power gain o f the
101
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three-stage am plifier exhibits some fluctuation, in particular, at low er frequencies,
implying a tendency toward instability. Although the stability o f transistors was verified
during circuit design for all frequencies, the fabrication variation m ay lead to a shift o f
CCl
CCT
O
Output
In p u t
C,
c2
C3
c4
Cs
0.10
0.18
0.17
0.10
0.78
pF
pF
pF
pF
pF
c6
L,
u
U
U
0.78 pF
0.38 nH
1.46 nH
1.55 nH
1.20 nH
Ri
Rz
r 3
R4
1400 Q
400 £2
1400 Q.
400 Q.
(a)
(b)
Fig.
6 .6
(a) Schem atic of the single-stage amplifier, (b) Photom icrograph
o f the three-stage amplifier.
102
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15
10
^
5
PQ
T3
“
c
3
0
O
-5
'22.
-10
-15
5
7.5
10
12.5
15
Frequency [GHz]
Fig. 6.7 S-param eter measurement results of the three-stage amplifier.
stability circles as well as input and output impedance on the T planes. Once the
impedance at input or output moves too close to the edge of the stability circles, the
stability of the multi-stage amplifier deteriorates, resulting in gain ripple, especially, at
lower frequencies.
6.4 Design of X-band Oscillators
With the fabrication technology developed for Si-based MMIC’s, an X-band
negative-resistance oscillator is designed at 10 GHz using multi-finger SiGe H BT’s and
the micromachined passive components. A typical two-port negative-resistance oscillator
[62] consists o f an active device, a terminating network and a load network as shown in
Fig.
6 .8
(a). The active tw o-port network is required to be potentially unstable at the
103
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oscillation frequency. By properly choosing the term inating network, which provides an
impedance located in the unstable region on T plane, a negative resistance is obtained in
port impedance Z IN. Then the load network Z l is designed to cancel the imaginary part of
Z in, leaving a net negative resistance to initiate the oscillation.
Figure
6 .8
(b) shows a schematic of the negative-resistance oscillator designed to
operate at 10 GHz. For circuit implementation, a common-base SiGe HBT (emitter area =
2x2x30 (im2) with an external feedback (L2) is em ployed as the active network due to its
low stability factor k at the oscillation frequency. T he termination network
(L 3 ,
Ci) is
design to provide a reflection coefficient T t such that the magnitude of Tin is maximized,
and the associated Zin is -92.5-j20.7 £2 from com puter simulation. Therefore, the load
network L[ is designed accordingly, and the resulting Z l is 50+J20.7 Q at 10 GHz.
It is noted that only small-signal characteristics o f the active and passive devices are
utilized for the oscillator design, and that the design procedure ensures oscillation by a
net negative resistance. As the oscillation power increases, the oscillation frequency will
shift somewhat from its design value. Therefore, large-signal models as developed in
section 3.6 are employed to simulate the oscillator design under large-signal operation.
From harmonic balanced simulation, the resulting oscillation frequency and output pow er
are 10.4 GHz and 12.4 dBm, respectively.
6.5 Design of SiGe HBT Power Amplifiers
Pow er dividing/combining techniques are widely used in a power amplifier design
when the required output power exceeds the pow er that can be provided by a single
transistor. The use o f a balanced structure for am plifier design as shown in Fig. 6.9 is a
104
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Zl
(TO (r iN)
ZoUT
Zp
(T out)
(T t )
Active
two-port network
Load network
Termimating
network
(a)
<=>
Output
cc
EE
L
U
l2
Ae = 2x2x30 (j.m2
0.32 nH
0.45 pF
Ci
0.6 nH
5 pF
c2
U
3.0 nH
Rs
50 a
u
V ff
5 nH
Rl
50
-0 . 8 V
VCc
6
Q.
a
V
(b)
Fig.
6 .8
(a) Block diagram of a two-port negative resistance oscillator, (b)
Schematic o f the X-band oscillator design.
105
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practical method to com bine pow er at the output while providing flat gain and low input
and output VSWR.
For circuit implementation, first, amplifying stages consisting o f two common-emitter
1 0 -finger
devices along with input and output matching networks are designed for
maximum output power. Figure 6.10 shows a schematic of the am plifying stage including
the matching and bias networks. Then the lumped quadrature hybrids as developed in
section 5.4 are then utilized to construct the balanced amplifier. Owing to the balanced
structure, any reflected pow er due to circuit mismatch will be dissipated at the 50 Q.
termination, resulting in low V SW R ’s at input and output ports. A com plete schematic o f
the balanced power am plifier is shown in Fig. 6 . 11.
90° Hybrid
i
. i-------
o
Input
Output
Input matching
and DC bias
Output matching
and DC bias
Fig. 6.9 Block diagram of a balanced amplifier.
106
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r s
rL
r
BB
Input
C:
Output
Input matching
and DC bias
Qi
Li
Ln
l3
U
V bb
Output matching
and DC bias
A e = 10x2x30 Jim 2
0.15 nH
2.0 pF
Ct
1.0 nH
0.4 pF
Co
5 nH
10 pF
C3
5 nH
10 pF
C4
0.81 V
8V
Vcc
Fig. 6 .10 Schematic o f the am plifying stage for the balanced amplifier
design.
In order to design and verify proper operation o f the balanced amplifier, small-signal
equivalent circuits for the active and passive components are used in computer
simulation; the resulting performance is shown in Fig. 6.12. From the simulation results,
a flat gain (G = 9±1 dB) is achieved over a wide range o f frequencies (5.8 ~ 8.5 GHz)
w ith return loss better than 16 dB at 8.5 GHz. In addition to the simulation o f smallsignal characteristics, the pow er perform ance is also predicted using the large-signal
models. The simulated pow er saturation curve is shown in Fig. 6.13. With a maximum
107
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PAE o f 16.6% for class-A operation, the balanced power amplifier exhibits a power
o f 6.1 dB and an output power o f 26.2 dBm.
90° Hybrid
Input
Output
Input matching
and DC bias
Output matching
and DC bias
Fig. 6.11 Schematic o f the X-band balanced power amplifier with lumped
passive components.
T3
C /0
00
--10
-20
-30
2.0
12.0
Frequency 2.0 GHz/DIV
Fig. 6.12 Simulated small-signal performance o f the balanced amplifier.
108
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30
25
20
10
0
OUT
-10
-20
-30.0
30.0
Pow er 10.0 dBm/DIV
Fig. 6.13 Sim ulated pow er saturation curve o f the balanced amplifier.
6.6
Summary
B y integrating m icrom achined passive components with the SiGe H B T’s, a
fabrication technology has been developed for Si-based M M IC ’s. With standard double­
m esa HBT devices as described in chapter 2, m ulti-stage amplifiers with lumped
matching and bias netw orks
were demonstrated at X-band. From S-parameter
measurements, the single-stage am plifier exhibits a pow er gain of 4.0 dB at 10 GHz,
while the gains o f the X -band two- and three-stage am plifiers are 5.7 dB and 12.6 dB,
respectively. In addition, m ulti-finger SiGe HBT’s fabricated by the fidly self-aligned
technology are em ployed fo r oscillator and balanced pow er amplifier designs. Based on
large-signal modeling, the sim ulation results of the oscillator design show an oscillation
frequency of 10.4 GHz w ith an output power of 12.4 dBm. Computer simulation predicts
109
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a maximum PAE o f 16.6% for class-A operation o f the balanced power amplifier with an
output power o f 26.2 dBm.
110
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CHAPTER VH
CONCLUSIO NS AND SUG G ESTIO NS FO R
FUTURE RESEAR C H
7.1 Conclusions
The work in this thesis has been mainly focused on the development of SiGe HBT
devices and micromachined passive components for use at microwave frequencies. By
integrating the SiGe HBT devices with the micromachined passive components, a Sibased MMIC process technology is then presented for circuit fabrication. Finally,
microwave circuits such as multi-stage amplifiers, oscillators and balanced power
amplifiers have been designed and demonstrated at X-band.
The availability o f high-performance transistors is indispensable for monolithic
microwave applications. Hence, this study was initiated with the design and process
optimization for SiGe H B T’s. With a layer design suitable for high-speed and low-power
applications, standard double mesa HBT process technology was employed to fabricate
the transistors. For a fabricated HBT with em itter area of 5x5 fim2, a maximum current
gain of 109 has been achieved. From small-signal S-parameter measurement results, the
extrapolated/r andfniax o f this device are 28 and 52 GHz, respectively.
Due to the demand o f high gain, efficiency and output power for a microwave power
transistor, both intrinsic transistor operation and device parasitics have to be carefully
111
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investigated, posing a challenge on the device layout design as well as epitaxial layer
design. Based on the experience gained from the low-power HBT development, the
design o f the heterojunction structure has been modified to optimize the breakdown
voltage and the m axim um operating current o f the device, without deteriorating its
frequency response. Additionally, a multi-finger device structure with a fully self-aligned
HBT process technology has been developed to minimize the parasitics for optimum
device performance. W ith improved epitaxial quality and advanced process technology, a
fabricated two-finger SiGe HBT (Ae = 2x2x30
J im 2)
exhibits a breakdown voltage
B V c e o of 10 V , while maintains high gain at microwave frequencies (fr= 37 GHz, f max =
78 GHz). To investigate the power performance of the multi-finger SiGe HBT’s, loadpull measurements were performed on the fabricated devices. Operating in class-A mode,
a maximum PAE o f 30.3% was achieved for a 10-finger device with an output power of
24.6 dBm at 8.5 GHz. Furthermore, both small-signal equivalent circuits and large-signal
models have been extracted from the measurement results for detailed characterization of
the device performance.
For MMIC applications, the circuit performance is also strongly influenced by
passive components. W ith this in mind, lumped passive components such as spiral
inductors, MIM capacitors and thin-film resistors were fabricated and characterized at
microwave frequencies. W ith a novel micromachined structure for the spiral inductors,
the parasitic capacitance is reduced by the removal o f the substrate material, leading to a
significant improvement in Q-factor and resonant frequencies. As a result, the use of
lumped passive components in microwave circuit designs can be extended to X-band or
even K-band frequencies.
112
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Microwave couplers such as W ilkinson power dividers, quadarture hybrids and 180°
hybrids are widely used for power dividing/combining. In this work, a systematic
analysis and design technique have been presented to im plement these coupler circuits
using lumped passive components. With the m icrom achined technology developed for
passive components, coupler circuits have been designed and fabricated with a center
frequency of 8.5 GHz. S-parameter measurements were performed on the fabricated
couplers to characterize the circuit performance in terms o f insertion loss, return loss and
bandwidth. Approximately, two order of magnitude area reduction has been achieved by
this approach com pared with distributed designs.
In order to demonstrate the potential o f the Si-based MMIC’s, the process
technologies for SiGe H B T’s and micromachined passive components are integrated for
circuit fabrication. First, multi-stage amplifiers has been designed and fabricated using
the low-power HBT devices. From S-parameter measurements, a gain of 12 dB has been
achieved at X-band for a three-stage amplifier with a chip size of 1.15x0.84 mm2.
Furthermore, design and simulation of X-band oscillators and power amplifiers using
multi-finger HBT devices are also included in this work. Based on large-signal modeling
o f a two-finger device (A e = 2x2x30 fim2), the sim ulation results of the oscillator design
show an oscillation frequency o f 10.4 GHz with an output power of 12.4 dBm. In the
balanced power am plifier design, a maximum PAE o f 16.6% is obtained for a class-A
operation with an output power o f 26.2 dBm in com puter simulation.
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7.2 Suggestions for Future Research
In this work, fully self-aligned process technology has been developed to fabricate
multi-finger devices. W ith improved epitaxial quality and reduced device parasitics, a
two-finger HBT with em itter area o f 2x2x30 |im 2 exhibits h ig h /r (37 GHz) and /max (78
GHz). However, as the num ber o f fingers increases, the fmax o f the device decreases,
leading to a deteriorated pow er gain. It implies that nonuniform characteristics o f device
operation, which may be caused by additional device parasitics or thermal feedback from
adjacent em itter fingers, have been introduced while connecting m ore em itter fingers in
parallel. Therefore, more detailed analysis and simulation may be required to investigate
the correlation o f em itter periphery and frequency response for the HBT device. As a
result, the layout arrangem ent o f the multi-finger devices can be further optimized.
For device characterization, both small-signal equivalent circuits and Gummel-Poon
model were extracted from measurement results. Even though these models are
successful in predicting the small-signal and large-signal properties o f the multi-finger
SiGe HBT’s, discrepancy has been observed while the devices are operating at low
collecter current. Furthermore, they do not contain noise information of the devices.
M ore sophisticated m odeling technique is required to incorporate noise characteristics
into a nonlinear model. As a consequence, more accurate simulation results can be
obtained to predict circuit performance in MMIC designs.
In additional to high-frequency gain, noise performance o f a microwave transistor is
of crucial importance in circuit implementation. Recently, SiG e HBT devices with a
noise figure o f 1.4 dB at 10 GHz have been reported [63]. W ith a vertical device structure
and a low base sheet resistance, SiGe HBT’s have become a potential candidate for use in
114
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microwave receivers. By modifying the equipment setup, the load-pull system, which has
been used for pow er measurement, can be used to measure the noise performance of the
fabricated devices. Thus the noise characteristics of the SiGe HBT can be further
investigated for low-noise applications.
115
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116
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