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Investigation of gallium indium phosphide/gallium arsenide double heterojunction bipolar transistors for microwave power amplifier applications

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UNIVERSITY OF CALIFORNIA, SAN DIEGO
Investigation o f GalnP/GaAs Double Heterojunction
Bipolar Transistors for Microwave Power Amplifier Applications
A dissertation submitted in partial satisfaction o f the
requirements for the degree o f Doctor o f Philosophy in Electrical
Engineering (Applied Physics)
by
Pin-Fan Chen
Committee in charge
Professor Peter Asbeck, Chair
Professor Chung-kuan Cheng
Professor Lawrence Larson
Professor Michael Sailor
Professor Edward Yu
2001
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UMI Num ber 3001274
Copyright 2001 by
Chen, Pin-Fan
All rights reserved.
___
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UMI
UMI Microform 3001274
Copyright 2001 by Bell & Howell Information and Learning Company.
All rights reserved. This microform edition is protected against
unauthorized copying under Title 17, United S tates Code.
Bell & Howell Information and Learning Company
300 North Zeeb Road
P .O .B o x 1346
Ann Arbor, Ml 48106-1346
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Copyright
Pin-Fan Chen, 2001
All rights reserved.
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The dissertation o f Pin-Fan Chen is approved,
and it is acceptable in quality and form for
publication on microfilm:
Professor Edward Yu
Professor Lawrence Larson
Professor Michael Sailor
Chair
Professor Peter Asbeck
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T able of Contents
Signature Page ......................................................................
Table o f Content ...........................
iv
List o f Figures and T ables.............- .......................................................................... vi
Acknowledgements....................... - .......................................................................... xii
Vita and Publications .................. - ........................................................................... xv
A b stract......................................................................................................................... xvii
1. Introduction......................................................................
1.1. Requirement for D evices in Communication Systems .......................
1.2. Competing Technologies ........................................................................
1.2.1. Radio Transceiver Architecture ...............................................
1.2.2. Silicon T echnologies.................................................................
1.2.3. m -V Compound! Semiconductor Transistors Technologies
1
1
6
6
9
IH-VHBTs .................................................................................................
1.3.1. Single Heterojunction Bipolar Transistors (HBTs) ..............
1.3.2. Double Heterojumction Bipolar Transistors (DHBTs) ..........
1.3.3. Material Choices for HBTs and DHBTs ...............................
Introduction to Power Amplifiers .........................................................
Scope o f this work ....................................................................................
11
12
13
16
17
18
20
2. DHBT Design and Processing ..........................................................................
2.1. Layout Related Issues ...........................................................................
2.1.1. Current Crowding and Effectiveness o f the Emitter Area ....
2.1.2. Base resistance .........................................................................
2.1.3. Thermal Effects ........................................................................
2.2. Device Design ..............
2.2.1. Epitaxial Layer Design .............................................................
2.2.2. AEc Consideration ...................................................................
2.3. Device Processing
...........................................................................
2.3.1. Self-Aligned Process ................................................................
2.3.2. Non-self-aligned Process .........................................................
24
24
24
25
27
29
30
33
35
36
41
3. Device Characteristics .............
3.1. DC Measurements
...........................................................................
3.1.1. Process 2 GalnP DHBT DC Characteristics .........................
3.1.2. Process 3 GalnP DHBT DC Characteristics .........................
3.1.3. Current Blocking Effect ...........................................................
3.2. S-Parameter M easurement ....................................................................
3.3. DHBT Modeling .........
45
45
46
51
55
64
68
4. Heatsinking Techniques .................................................
4.1. Introduction...................
72
1.3.
1.4.
1.5.
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7
4.2.
4.3.
4.4.
4.5.
4.6.
4.1.1. Flip-chip Heatsinking ...............................................................
4.1.2. Heatsink Design .......................................................................
Device Structure and Fabrication .........................................................
Measurement Results ............................................................................
Power Measurement ...............................................................................
Backside Via Modeling ..........................................................................
Summary ..................................................................................................
74
73
75
77
79
80
83
5.
Saturation Charge Storage Measurements .....................................................
5.1.
Charge Storage Effect ...........................................................................
5.2.
Charge Storage Effect in Heterojunction ............................................
5.3. Experimental Methods and Results .....................................................
5.3.1. Device Structures .....................................................................
5.3.2. Test Setups ...............................................................................
5.4. Measurement Results ..............................................................................
5.5. A nalysis.....................................................................................................
85
86
89
92
92
94
97
100
6.
Amplifier Designs .............................................................................................
6.1. Class AB Amplifiers ...............................................................................
6.1.1. Biasing Methods ......................................................................
6.1.2. Transistor Matching Methods ................................................
6.1.3. DHBT Measurements Results ................................................
6.2. Class D Amplifier ..................................................................................
6.2.1. Idealized Class D Operation ...................................................
6.2.2. All N PN Totem Pole Type ......................................................
6.2.3. Measured R e su lts.....................................................................
109
109
110
119
122
125
126
127
130
7.
Conclusions and Future Works .......................................................................
7.1. Summary o f the Dissertation .................................................................
7.2. Future Work ............................................................................................
7.2.1. Undercutting Structures for Reduced C b c DHBTs ..............
7.2.2. Reduction o f AEc Use o f Nitrogen-contained Compounds
133
133
134
135
135
7.2.3.
High Speed DSP implementation o f the class S amplifier
.
136
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List of Figures
Figure 1.1. Spectrum Usage from 800MHz to 3 GHz ......................................... 3
Figure 1.2. Simplified architecture diagram ........................................................ 6
Figure 1.3. Si and SiGe HBT band diagram ........................................................ 11
Figure 1.4. Band diagram o f HBT ........................................................................ 14
Figure 1.5. Bandgap vs. Lattice constant diagram o f semiconductor material .. 15
Figure 1.6. Band diagram o f DH BT....................................................................... 17
Figure 1.7. Band alignment for GalnP/GaAs and AlGaAs/GaAs heterojunction
18
Figure 2.1 Current crowding effect (Dark area shows lowered base emitter voltage)
............................................................................................................... 25
Figure 2.2 Self-aligned base contracts .................................................................. 26
Figure 2.3 Basic layout o f an unit cell for the HBTs ........................................... 27
Figure 2.4 Limiting the current hogging with emitter ballasting resistors
29
Figure 2.5 (a) Bandgap alignment of GaAs to GalnP (b) electron transport across a
GaAs/GaTnP p-n heterojunction ....................................................... 33
Figure 2.6. (a) The effect o f setback layer (b) The effect of n-type pulse doping
............................................................................................................... 35
Figure 2.7 (a)-(i) Self-aligned HBT and DHBT fabrication process ................ 38
Figure 2.8 (a) Proper etching profile for self-aligned base (b) Improper etching
p rofile.................................................................................................. 41
Figure 2.9 Emitter ledge structure formed by GalnP layer ................................ 42
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Figure 3.1 Test setup to minimize transistor oscillation...................................... 45
Figure 3.2 Gummel Plot for 40pm2 Process 2 GalnP D H B T ............................. 48
Figure
3 .3
Common Emitter Characteristics o f the 40pm 2 Process
2
DHBT
(Ib
step=50pA) ........................................................................................ 48
Figure 3.4 Offset voltage for the 40pm2 Process 2 DHBT ................................. 49
Figure
3 .5
Offset voltage for the 40pm2 AlGaAs/GaAs SHBT
(Ib
step=10pA)
............................................................................................................... 50
Figure 3.6 Measurement setups for breakdown voltage evaluation .................. 50
Figure 3.7 Gummel Plot for the Process 3D GalnP DHBT (Emitter Area=40pm2)
................................................................................................................ 53
Figure 3.8 Common Emitter IV Plot o f the Process 3D DHBT (Emitter Area=40pm2)
................................................................................................................ 54
Figure 3.9 Gummel Plot for the Process 3F DHBT (Emitter Area=40pm2) ...... 54
Figure 3.10 Common Emitter IV Plot for Process 3F DHBT (Emitter Area=40pm2)
................................................................................................................ 55
Figure 3.11 The reduction of charge density in collector SCR due to injected current
................................................................................................................ 57
Figure 3.12 Charge in the base-collector SCR under current injection ............. 57
Figure 3.13 Increased carrier blocking due to increased collector current density
................................................................................................................ 57
Figure 3.14 Gummel plot showing the AEc current blocking effect (40 pm2 NDI
DHBT, Current blocking at 2.2 x 104 A/cm2) .................................... 58
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Figure 3.15 IV plot showing the AEc current blocking effect (40 pm2 NDI DHBT, Ib
Step = 50 pA) ..................................................................................... 59
Figure 3.16 Simulated potential and conduction band diagram o f the base-collector
junction................................................................................................. 61
Figure 3.17 Simulated conduction band diagram with and without pulse doping
62
Figure 3.18 Simulated and measured current density for a 20pm2 Process2 DHBT
62
Figure 3.19 CV Measurement o f the Process2 junction ....................................... 63
Figure 3.20 Doping profile calculated from the CV measurement ..................... 64
Figure 3.21 High frequency measurement configuration...................................... 65
Figure 3.22 High frequency behavior o f a NDI 40pm 2 D H B T ............................ 66
Figure 3.23 High frequency behavior o f Rockwell 60pm i (Wafer F) ................. 67
Figure 3.24
fj
and/w/vx versus current (Rockwell 60pm2, wafer F ) .................... 68
Figure 4.1 Transistor topology for backside inter-connection ............................. 74
Figure 4.2 Schematic diagram o f the flip-chip heatsinking scheme .................... 74
Figure 4.3 SEM picture o f the backside probe pads ............................................. 77
Figure 4.4 Variation in V be and beta versus power and temperature under constant
current ................................................................................................... 78
Figure 4.5 Simulation result versus measured resu lts........................................... 79
Figure 4.6 Power output characteristics o f the heatsinked transistor................... 80
Figure 4.7 Top view o f the via modeling structure................................................ 81
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Figure 4.8 Schematic o f the via modeling structure ............................................ 81
Figure 4.9 Measuring via inductance using one port m e th o d ............................. 82
Figure 5.1 Using BJT or HBT as a switch ............................................................. 85
Figure 5.2 BJT band diagram showing the effect o f reduced BC potential
87
Figure 5.3 Minority carrier level during the transition from saturation to forward
a c tiv e .................................................................................................... 88
Figure 5.4 Cross-section o f a Schottky clamped d io d e ........................................ 89
Figure 5.5 Bandgap diagram o f a DHBT ............................................................... 91
Figure 5.6 DHBT and SHBT structure used for charge storage effect demonstration
................................................................................................................ 92
Figure 5.7 The common emitter IV curves o f the device under te s t .................. 93
Figure 5.8 (a) Switching circuit (b) input emitter current pulse (c) output collector
waveform with delay from charge storage e ffe c t............................ 95
Figure 5.9 Setup for characterizing chage storage effect in HBT base collector
junction ................................................................................................ 96
Figure 5.10 Measured result o f the chage storage te s tin g ................................... 97
Figure 5.11 Current component o f the charge storage m easurem ent.................. 98
Figure 5.12 De-embedded voltage waveform for a base-collector homojunction
................................................................................................................ 99
Figure 5.13 De-embedded voltage waveform for a base-collector heterojunction
................................................................................................................ 99
Figure 5.14 Fundamental component of the sinusoidal response ....................... 102
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Figure 5.15 (a) Detailed view of the sinusoidal response waveform, (b) Charge
storage time versus input sinusoidal amplitude ............................... 106
Figure 5.16 Measured charge storage time at different frequency...................... 107
Figure 6.1 Load line analysis of the amplifier classes used in communication systems
110
Figure 6.2 Typical biasing m ethod......................................................................... 113
Figure 6.3 Typical FET drain current versus gate voltage characteristics .......... 114
Figure 6.4 Typical HBT Gummel p lo t................................................................... 114
Figure 6.5 Current controlled mode HBT c o m m on emitter characteristics
115
Figure 6.6 Voltage controlled mode HBT common emitter characteristics
115
Figure 6.7 Influences o f input power on base bias voltage and current under constant
voltage biasing ..................................................................................... 116
Figure 6.8 Influences o f input power on base bias voltage and current under constant
current b iasin g ..................................................................................... 116
Figure 6.9 Biasing the base with finite impedance ............................................... 118
Figure 6.10 Construction o f a double stub tu n e r................................................... 120
Figure 6.11 Computer controlled automatic load pull system ............................ 121
Figure 6.12 Sample result o f a load pull m easurem ent........................................ 122
Figure 6.13 Load pull contour of a 896pm2 DHBT at 1GHz ............................ 124
Figure 6.14 Power output characteristics at 1GHz ............................................... 124
Figure 6.15 Power output characteristics at 2GHz ............................................... 125
Figure 6.16 Schematic drawing of the all NPN class D am plifier...................... 128
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Figure 6.17 Chip photograph o f DHBT class D am plifier................................... 1 29
Figure 6.18 Difficulty in implementing the emitter follower with the driver HBT off
................................................................................................................ 1 30
Figure 6.19 Time domain response o f the class D am plifier.............................. 131
Table 2.1 MURIDHBT/SHBT device layer structures ........................................ 3-1
Table 3.1 Process 2 GalnP DHBT layer structure ............................................... 4-7
Table 3.2 Process 3F and D layer structures......................................................... 5 2
Table 3.3 High frequency performaces o f GalnP DHBTs .................................. 6»8
Table 3.4 Gummel Poon Models Parameter for 60pm2 H B T ............................. 7'0
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Acknowledgements
Like all the members the UCSD High Speed Device Group, I am deeply
grateful for the guidance o f Professor Peter Asbeck. With his patience and insistence
to understand the core o f HBT physics and circuits, he has taught me everything I
know about this subject matter.
Furthermore, his method o f studying each new
subject with such scientific approaches will be my example to many challenges ahead.
It should also be mentioned that Professor Asbeck’s parties are some o f the most
memorable events, perhaps in the history o f UCSD
I am also fortunate to receive guidance from many o f the UCSD professors as
well as many researchers in the GaAs community. Specifically I would like to thank
Professor Larson, Professor Yu, Professor Sailor and Professor Cheng for serving on
my committee and provided valuable advice in my qualify and defense exams. Dr.
K.C. Wang, Dr. Frank Chang, Dr. Pete Zampardi, and Dick Pearson have helped me
with the collaboration in Rockwell Science Center. Without them, this work would
not have been completed. Dr. Wu-jing Ho o f Network Device Incorporated has also
help me with processing during his busy schedule of starting a new company. In
addition, I have also benefited from the curriculum of UCSD ECE department. The
instructions from great teachers such as Professor Lau, Professor Tu, and many others
have helped me in my career thus far.
I must also acknowledge my good friends who suffered through the graduate
studies with me. First o f all, I would like to thank our most senior members— Dr.
Vincent Ho and Dr. Charles Chang for teaching me how to use firearms. Vincent has
always provided me with in-depth analysis’s o f HBT physics and an accurate vision
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o f future direction. Charles has taught me microwave measurements. He has also
helped me with circuit designs in the days when I was struggling with RTD logic
circuits. Continuing down the history o f high-speed device group graduates, I would
also like to thank Dr. Shyh-Liang Fu for being a great tennis partner during his UCSD
years. He has also been very helpful in many discussions regarding research direction
and career choices. Dr. Hsin-hsing Liao and Dr. Yue-ming (Tony) Hsin have gotten
me to waste all my money on photography equipment. I own several thousand dollar
worth o f cameras because o f these guys. Despite o f the apparent financial loss, the
joy I get from photography is immeasurable. Hsin-hsing has also got me hooked on
riding motorcycles (which he’s going to need in Taiwan).
Tony helped me by
providing me with my first look at GalnP/GaAs DHBT.
There is also Dr. Sang Park who lived on my living room floor for a while. I
can always count on him to give a very different but insightful view o f life. Dr. Robb
Johnson has always been a great friend. He was truly the layout master and quite an
RF artist. There is also Dr. J.Arun who tried to teach me Delta Sigma modulation.
Although I still don’t under stand the subject, I did enjoy all those breaks that we took
to get coffee.
O f course, there is the rest o f the gang who came afterwards. There is my
good friend Dr. Gary Hanington. He has taught me the meaning o f life. The trips that
we took to Denver and Baltimore for MTT-S has been some o f the best trips ever.
Dr. M att Wetzel has always had a secret evil streak and a sense o f humor that ithas
always been fun to be around him. In addition to helping me out with UNIX systems,
Matt even helped me getting a decent shirt for my defense. On that note, I must
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mention that Nick Farcich is such a great guy; he brought me food on the day o f my
defense. We also had many interesting discussions on the subject o f politics and
other non-technical issues. Sorry about that whole Knicker Bocker bit.
Andre Metzger was one o f the best student when I taught the electronic class.
He turned out to be an excellent electronic engineer. I leam from him that we should
all have fun. And I would like to give all the credit to Becky Welty for processing
those great DHBTs which helps me to graduate. She is one of the best processing
engineers. I know she would have a lot of success in research. Masaya Iwamoto has
also provided me with many insightful discussion on the implementation o f class S
amplifier. I leam quite a lot from them.
I would also like to express my gratitude to Dr. R.T. Huang, Dr. Daniel, Dr.
Yuefei Yang and many others at Global Communication Semiconductors.
I am
fortunate to be working with them and continuing my studies in HBT engineering.
Finally, my family has always been the foundation o f my moral support. My
parents have encouraged me to pursue this degree and helped me at time o f need. I
also look to my brother and sister as examples and leam from them. I am also glad
that I meet my wife Pin-Pin here at UCSD. She brings constant joy to my life and
supported me through all the up and downs. Without her, I would not be complete
this study.
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Vita
January 11, 1970
Bom, Taipei, Taiwan
June 1992
B.S. in Electrical Engineering
University o f California, Los Angeles
June 1993
M.S. in Electrical Engineering (Applied Physics)
University o f California, San Diego
1993-1998
Research Assistant
University o f California San Diego
March 2001
Ph.D. in Electrical Engineering (Applied Physics)
University o f California, San Diego
Publications
P.F. Chen, R.A. Johnson, M.C. Ho, W.J. Ho, A. Sailor, MJF.Chang, and P.M.
Asbeck, “Microwave and Thermal Characterization o f the Flip-Chip Heatsink
structure,” Electronics Letters, September 26, 1996 Vol.32 no.20 pp.1931-1932
P.F. Chen, Y.M. Hsin, P.M. Asbeck, “Charge Storage Measurements o f the
GalnP/GaAs/GalnP DHBT,” International Symposium on Compound
Semiconductors, San Diego, September, 1997
C.E. Chang, P.F. Chen, L. Tran, A. Oki, D. Streit, P.M. Asbeck, “Lightly Doped
Emitter HBT for Low Power Circuits,” IEEE Microwave and Guided Wave Letters,
Vol. 7, no. 11, 1997, pp.377-379
P.F. Chen, R.A. Johnson, M. Wetzel, P. De La Houssaye, G. Garcia, I. Lagnado,
P.M. Asbeck, “SOS MOSFET Distributed Amplifier Implemented with Coplanar
Waveguide,” RFIC Symposium, Baltimore, 1998
J.Arun, P.F. Chen, P.M. Asbeck, “Linear High-Efficiency Microwave Power
Amplifiers using Bandpass Delta-Sigma Modulators,” IEEE Microwave and Guided
Wave Letters, Vol. 8, No. 3, March 1998, pp. 121-123
M.Wetzel, R.A. Johnson, P.F.Chen, P.R. de la Houssaye, B.Xavier, P.M.Asbeck,
LLagnado, “Prospects o f CMOS Power Amplifiers on Thin Film SOS for Wireless
Applications,” First Annual UCSD Conference on Wireless Communications, San
Diego, March 1998, pp. 67-73
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G. Hanington, P.F.Chen, P.M.Asbeck, “A 100MHz DC-DC Converter for High
Efficiency Power Amplification RF Transmitters,” First Annual UCSD Conference
on Wireless Communications, San Diego, M arch 1998, pp. 74-78
P.M. Asbeck, T. Itoh, Y. Qian, M.F. Chang, L. Milstein, G. Hanington, P.F. Chen, V.
Schultz, D.W. Lee, and J. Arun, "Device and Circuit Approaches for Improved
Linearity and Efficiency in Microwave Transmitters," IEEE MTT-s, Baltimore, 1998,
pp. 327-329
Gary Hanington, P.F. Chen, V. Radisic, T. Itoh, P.M. Asbeck, "Microwave Power
Amplifier Efficiency Improvement with a 10MHz HBT DC-DC Converter," IEEE
MTT-s, Baltimore, 1998, pp. 589-592
P.F. Chen, Y.M. Hsin, R.J. Welty, P.M. Asbeck, and others, “Application of
GalnP/GaAs DHBT's to Power Amplifiers for Wireless Communications,” IEEE
TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1999 AUG,
V47 N8:1433-1438.
P.F. Chen, Y.F. Yang, and R.T. Huang, “Load-Pull Characterization of InGaP/GaAs
HBTs for Power Amplifiers,” IEEE POWER AMPLIFIER WORKSHOP, San
Diego, 1999
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Abstract of the Dissertation
Investigation of GalnP/GaAs Double Heterojunction Bipolar
Transistors for Microwave Power Amplifier Applications
by
Pin-Fan Chen
Doctor of Philosophy in Electrical Engineering (Applied Physics)
University of California, San Diego, 2001
Professor Peter M. Asbeck, Chair
Heterojunction Bipolar Transistors (HBTs) fabricated with the AlGaAs/GaAs
material system are presently being successfully applied to power amplifiers for
wireless communication handsets. For future use, a variety o f device improvements
would be worthwhile, including reduced offset voltage, greater ruggedness, and
higher gain in high efficiency modes o f operation. In this thesis, the characteristics of
GalnP/GaAs/GalnP Double Heterojunction Bipolar Transistors (DHBTs), in which
GalnP is used for both '.'he emitter and collector o f the device, are investigated in
relation to microwave power amplifier applications. The design, fabrication, DC and
high frequency electrical characteristics, and thermal characteristics o f the DHBTs are
studied. Saturation charge storage in the devices is investigated for the first time.
Several novel amplifier configurations which exploit the
u n iq u e
characteristics o f the
DHBTs are proposed.
Several lots o f GalnP/GaAs DHBTs were fabricated for this work with both
self-align and non-self-aligned techniques.
It was shown that high base collector
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breakdown voltage can be achieved with relatively thin (4000A) collector regions.
The small geometry devices in this work have shown cut-off frequency (fr ) as high as
70GHz, which is the highest to date for GalnP/GaAs DHBTs.
Thermal effects are also important considerations in designing transistors for
power applications. A novel heatsinking technique was proposed and implemented in
this work. This technology combines the flip-chip approach and through-substrate via
holes, to use the front side o f the HBT substrate as the heatsink and the backside o f
the wafer for interconnect. The thermal resistance was reduced by 5 times.
The hole barrier at the base collector junction o f the DHBT prevents hole
injection into the collector during the saturation regime o f the transistor operation.
This was shown for the first time in GalnP/GaAs DHBTs, using a novel technique to
determine the charge storage behavior of a heterojunction.
To demonstrate the microwave gain and power output capability o f the
GalnP/GaAs DHBTs, load pull measurements were performed.
A unit cell with
aggregate emitter area o f 896pm2 was demonstrated to provide 250mW output power
with >50% power added efficiency. The relationship between the biasing scheme and
the loadpull results was examined. Several switching amplifier architectures that take
advantage o f the fast switching ability o f the DHBTs were also proposed.
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Chapter 1. Introduction
1.1 Requirements for Semiconductor Devices Used in Communication Systems
Information service is one o f the largest growing industries today.
Many
technologies work to bring various forms of information to the consumers—telephone,
television, radio, cell phone, internet, etc. Because information can be used to make our
lives better, the desire for information can often be described by the demand for “more”
and “faster” service. People have been creating technology to enable the construction o f
the information superhighway from the early invention o f telegram to telephone, radio,
television, e-mail, and recently internet. These networks can bring us various forms o f
information at high speed.
The development o f solid state electronic devices is driven by this same desire
for “more and faster” to supply the need for information.
Because o f this,
semiconductor engineers design faster and more densely packed transistors to drive the
data across the infrastructures at a higher rate and handle more data at the same time.
In recent years, because o f the global development o f commerce, individuals
began to develop heavier demands for instant data retrieval when they are away from
their offices. Wireless networks constructed in cellular format are set up to meet this
demand.
The constant connectivity may be a nuisance to some; but this newfound
mobility is welcomed by many. After all, people and physical objects are constantly on
the move due to improvements in the transportation infrastructure.
The ability to
remain connected to one's information sources or to emit information is highly valued.
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2
Although transistors were first invented to replace the vacuum tubes as
am plify in g
devices, the main driving force o f the semiconductor industry is the high­
speed, high-density digital computer throughout the last two decades due to the
popularization o f the personal computers. However, due to this recent growth of the
cellular telephone industries (as well as satellite and cable broadcasting companies),
there is a renewed interest in developing transistors for analog applications. Radio
design for wireless c o m m unication, a m ajor analog circuit research area, creates a new
set o f demands on semiconductor technologies both in the device technologies and the
circuit technologies.
One o f the major differences between analog and digital circuit design relates to
the power that the transistors have to physically deliver to transmit information. This is
especially true when the information is to be sent across a distance.
In digital
computation, the amount o f energy used to achieve this transmission o f information can
be reduced via scaling. The smaller the transistors are made and thus the shorter the
distance it is between the transistors, the less the energy would be transmitted.
However, for communication applications, the distance between two locations can not
be scaled down. In addition, the ana'og interface to the physical world is designed to
adapt to the requirements such as the attenuation o f signal in the atmosphere, reflection
o f the signals by mountains, trees, etc. as well as the existing human designed regulation
to share limited resources.
W ith all the above considerations, the objectives in the area o f transistor design
are to design transistors that have high cutoff frequency (/t) and high maximum
oscillation frequency
(fmax)
in order to enable transmitting signals at higher frequencies.
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3
The transistors must also have low noise to ensure the quality o f the transmission and
high breakdown and be able to handle high current to deliver the required power.
The requirement on the frequencies stems from the availability o f the radio
frequency spectrum. Since the conception o f radio communication by Marconi various
bandwidths have been assigned for different usage such as AM and FM radio
broadcasting, television, aviation, radar, or other military applications.
continuing growth in new applications —
With a
Such as the upcoming high definition
television (HDTV), Local Multipoint Distribution System (LMDS), and automotive
radar, plus growing utilization of the cellular network, the logical frontier for more
bandwidth is simply higher frequency.
See figure 1.1 for the usage o f the spectrum
from 800MHz to 3GHz in the U.S.[1-1]. Most o f these frequencies are used up by land
based applications.
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4
t£frW aAK }taO -t99CU H £A f€A U .OCA T s m K S :T 9 « -tS 3 3 im e
« o e s G w ffE c s q r m . c e c a p c s o e v c s s
6M -2 4 S iC .5 C U H z
Figure 1.1 Spectrum usage from 800MHz to 3 GHz
In addition to the availability o f the radio frequency spectrum, higher frequency
can also mean a larger bandwidth for more users.
This is important because data
communication, which often has much wider bandwidth than voice communication, is
becoming increasingly important.
The level o f noise generated by the transistors is also a m ajor concern for circuit
elements such as the low noise amplifiers (LNAs) as well as variable gain amplifiers
(VGAs). Excess noise can degrade the signal to noise ratio (SNR) o f a receiver and thus
reduce the overall performance o f a communication system.
High breakdown voltage is needed in order to create large RF voltage for the
amplification o f power. This is traditionally achieved by the addition o f a drift region to
reduce the peak electric field. It will be explained in later chapters that the drift region
in a bipolar transistor is simply part o f the collector, and in field effect transistors it is
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fabricated as a lightly doped drain (LDD) region. Regardless o f the construction, the
finite time requirement for carrier to travel across the drift region reduces the cutoff
frequency (/x) o f the transistor, thus reducing the operating frequency. Novel materials
are constantly being sought after for their ability to withstand higher electric field in
order to achieve higher breakdown without degrading the frequency performance.
Another consideration is the inherent linearity o f the transistors. A linear device
can accurately reproduce the transmitted signal without distortion. In communication
accurate reproduction o f the original signal is an important criterion. In addition to
erroneous symbols caused by nonlinearities, power spectrum will also appear in nearby
channels causing unwanted interference.
The interference is more severe for more
complicated digitally modulated signals such as the Code Division Multiple Access
(CDMA) technology, which utilizes a spread spectrum and thus is most vulnerable to
third order intermodulation distortion (1MD3) o f the amplifying device.
In addition to the research into technology striving toward ideal transistors (ones
with high / r , good linearity, low noise and high breakdown), extensive studies on the
methods o f applications are also important. That is, the circuit design issues are also
under careful investigation today. In this area o f research, the emphasis (in addition to
noise, linearity, and power) has been on efficiency.
On a mobile platform,
electrochemical cells with limited stored energy are the basic sources of power. Until
one can generate or store unlimited amount o f energy, power must be carefully
dispensed to extend the duration o f the connectivity.
Various classes o f power amplifiers have been studied by radio engineers. [1-2]
For the linearity requirement on the complex modulation schemes, most o f the
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6
amplifiers used today are o f the type class AB. However, higher classes o f amplifiers,
such as the class F and class E amplifiers, are constantly being examined as candidates
to replace the less efficient class AB amplifiers.
hi this study, the main focus is on the application o f GalnP/GaAs DHBT as a
candidate for the power amplifying device. Furthermore, the ability for GalnP/GaAs
DHBT to be used as switching power amplifier is also discussed. Several advantages
and disadvantages o f the InGaP/GaAs DHBT technology (both devices and circuits) will
be shown and discussed.
1.2 Competing Technologies
1.2.1 Radio Transceiver Architecture
LNA
LNA
440M H z
Image
reject
Image
reject
filter
filter
Baseband I
SAW
Filter
Baseband Q
Programmable
co
Q
c
T3
G a in
CO
90'
Baseband I
SSB
mixer
IF level
control
XJ
CD
co
co
CD
440M HZ
PA
CL
55
Buffer
Baseband Q
Figure 1.2 Simplified architecture diagram
Figure 1.2 shows a typical radio architecture used in wireless communications
using the quadrature phase shift keying (QPSK) modulation[l-3].
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Various
7
semiconductor technologies are employed to process the signal into modulated
electromagnetic waves and as well as down converting the high frequency signal back to
baseband digital signal. Since no single material or device technology can claim to be
ideal for the entire radio, there remains a lot of room for competition amongst the
various technology suppliers.
In the baseband, most o f the signal processing is done with standard silicon
CMOS logic circuits.
The high integration and low power capability enable this
technology to implement sophisticated digital signal processing (DSP) at minimum
power dissipation.
In the various intermediate frequency (IF) stages, where the
frequency ranges around 200 MHz to 400 MHz, the analog signal processing is mostly
performed by silicon bipolar transistors or high speed CMOS technologies designed for
analog or mixed signal applications. In the radio frequency (RF) stage, because o f the
requirement on higher frequency, devices made of Gallium Arsenide material systems
begin to show up.
For most systems, the final power amplifiers are made o f Gallium Arsenide
based technologies.
The high frequency capability o f this material can deliver the
required gain to the system with greater ease than silicon technologies, although silicon
technologies are improving rapidly. The study of the power amplifier is an important
consideration for mobile communication systems because the power amplifier often
consumes the most power. At present, a typical power amplifier for a mobile phone can
output 1 watt o f RF power at around 50% efficiency. That means it would consume 2
watt of power when during the 1 watt operation. Therefore, there is a lot o f attention
focused in this study, which is the goal for this thesis as well.
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8
Today, the semiconductor manufacturers continue to develop and various
products to meet the demands from various components o f the radio, hi a sense, the
battle for dominance continues among the various technologies.
We will briefly
describe the competing technologies.
Various network solid materials have been investigated since the invention o f
transistors. Among these are Germanium (Ge), Silicon (Si), Gallium Arsenide (GaAs),
Indium Phosphide (EaP), and combinations o f these materials.
Most o f the
commercially available transistors are made o f Silicon. GaAs devices have traditionally
being used for photonic and microwave applications by defense manufacturers. With
the change in political climate o f our world, military oriented industries experienced
widespread downsizing.
The growth o f wireless communication provided a logical
civilian market for the GaAs technologies, since many o f the requirements for the
cellular communication are the similar to that of the military mobile communication.
Having already spent defense dollars, many US corporations with the GaAs
technologies pushed to have the GaAs technology put into early cellular telephones.
However, because o f the growing market, companies who manufacture Si devices are
also looking into upgrading their Si technology to handle the requirements o f the
wireless market. The final verdict is not quite out yet.
Asides from the competition in materials, there is also competition among
engineers who have developed different device structures. M ost o f the devices can be
classified as field effect transistors (FETs) or bipolar junction transistors (BJTs). Both
types of the transistors can be found in every application. In logic circuits, it is clear
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9
that FETs (specifically MOSFETs) dominate the market. However, in gigahertz logic
and analog applications, both FET and BJT technologies are used.
1.2.2 Silicon Technologies
Silicon technology is the dominant workhorse for all electronic systems. It has
the advantage o f being one o f the most inexpensive and widely available semiconductor
substrate; it also has a high quality native oxide which is important for structures such
as gates for the metal oxide semiconductor field effect transistors (MOSFETs) and
passivation for silicon bipolar junction transistors (Si BJTs). Along with these natural
advantages, silicon technologies also have fifty years o f collaborative efforts in
developing processing procedures and equipment.
Today, almost all o f the digital
computers and other electronic products use silicon devices for computation, controls,
and signal processing.
The two main transistor structures used in silicon technologies are MOSFETs
and BJTs. Between them, MOSFETs are far more prevalent because of the personal
computer (PC) industries. In each PC, the CPU alone would have more than 5 million
MOSFETs.
BJTs are traditionally used for analog applications such as stereos,
televisions, etc. In a radio architecture, as mentioned in the previous section, mostly
MOSFETs are used for baseband DSP applications. In the IF and RF analog signal
processing, both BJTs and MOSFETs are used depending on designers.
Because o f the wide availability o f MOSFETs and their constant improvements
in operating frequency, many efforts were made to use MOSFETs in high speed (RF)
analog applications as well as digital applications.
One major disadvantage o f the
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10
MOSFETs is its high gate resistance (which attribute to a reduction o f / max and
increased noise) due to the polysilicon gate material. The figures o f merits to quantify
these properties are explained in appendix A. Some recent works propose to reinforce
the gate with metal T-gate structures to reduce the gate resistance in order to achieve
higher/max and lower noise.[l-4] In addition, the conductive silicon substrates tend to
degrade high frequency performances o f the transistors (higher loss tangent).
To
combat the effects o f the conductive substrate, high resistance substrate and silicon on
sapphire[l-5] technologies have been proposed.
Although enjoying wide popularity today, MOSFETs were not the first
transistors invented.
Si BJTs were invented in 1948 by Shockley, Bardeen and
Brattain.[l- 6 ] They were the first solid state devices invented to replace vacuum tube
triodes. The basic notion is to control the current flow o f the device by a controlled
potential barrier region called the base. The potential barrier can control the carrier flow
from the emitter to the collector.
Si BJTs have high transconductance, low input capacitance, and small geometry.
However, due to the requirement for the current gain which is a function of the emitter
doping and base doping, the base doping must be kept lower than the emitter doping by
about 100 times. This is detrimental to the high frequency behavior o f the transistor
because o f the added base resistance.
This figure o f merit that concerns the base
resistance will also be explained in appendix A.
To combat the limitation at the base, Germanium (Ge) is added to the base to
create Si/SiGe heterojunction bipolar transistors (HBTs).
Germanium in the base can reduce the bandgap.
The addition o f the
The composition profile o f
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11
G erm aniu m
in the base composition profile can be tailored to create an electric field to
reduce the base transit time, thus increasing the cutoff frequency o f these transistors.
AEg.Ge(grade)
= AEg.Ge(x=Wb)-AEg.Ge(x=0)
drift field
e-
p -S iG e v
b a se
n+ Si
emitter
n- Si
collector
p- Si
I
\
Figure 1-3. Si and SiGe HBT band diagram
This technology is currently receiving a lot o f attention as an important
contender in the RF technologies.[l-7][l-8][l-9] And there are reported works in the
power amplifier area for this technology as well. [ 1- 1 0 ]
1.2.3 m - V Compound Semiconductor Transistors Technologies
Although the computer industries spend billions o f dollars on the development
o f fast silicon transistors, most o f the gigahertz radio front end circuitry was first
developed with transistors made o f the compound semiconductor technologies with
circuit topologies that are simitar to the UHF designs which uses silicon components.
Compound semiconductor materials are usually an alloy o f group III and group V
chemical elements; therefore, they are referred to as IH-V materials. The advantages o f
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12
m -V materials include the higher electron mobility and larger breakdown field. These
inherent characteristics allow transistors to operate at higher frequencies (microwave
frequency) with higher breakdown voltages for higher power.
Early efforts in these compounds involved the design o f metal semiconductor
field effect transistors (MESFETs).
As better crystal growth techniques were
developed, dissimilar m -V materials could be grown with high quality interfaces. The
availability o f the heterojunction is another advantage these compound semiconductors
offer. The advantages include minority carrier blocking effect, which can be used for
heterojunction bipolar transistors (HBTs), and two dimensional electron gas (2DEG),
which can be used in high electron mobility transistor (HEMT) and pseudomorphicHEMT (pHEMT). These devices hold the records for highest cutoff frequencies
( / t 's )
and highest maximum frequency o f oscillation ( / m a x ' s ) to d ate [l-l 1],
The main focus o f this thesis is on heterojunction bipolar transistors (HBTs).
HBTs have wide bandgap emitter, the valence band discontinuity blocks the hole back
injection into the emitter increasing the emitter efficiency and thus increases the gain o f
the transistor.
Along with the improvement in gain, the base doping can also be
increased to reduce the base resistance. Today, many digital cellular phones use HBTs
as the power amplifier device.
1.3 III-V HBTs
M ost o f this thesis will concentrate on the design and application o f HBTs.
There are several variations in HBTs. Two of the major classifications are single HBTs
and double HBTs.
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13
1.3.1 Single Heterojunction Bipolar Transistors (HBTs)
As mentioned before, the base doping o f a Si BJT must be kept low in order for
the bipolar transistor to achieve an appropriate gain. However, when the base doping is
kept low, the resistance o f the base is high, requiring a RC time constant for the
controlling signal to charge the base. To increase the operating speed, one must reduce
the geometry o f the transistors to reduce the charge stored in the base capacitance. For
analog circuit, one can not shrink the lateral geometry because o f the power handling
requirements. Therefore, one must seek means to reduce the base resistance to increase
the speed o f the operation.
Heterojunction bipolar transistor, with its modified emitter, changes the current
gain by improving the emitter efficiency, and thus improves the high frequency
performances o f the bipolar transistor. The concept o f heterojunction bipolar transistors
or HBTs was proposed by Shockley and Kroemer in 1948 as in Claim2, US. Patent 2
569 349 and was explained in detail by Kroemer in 1957.[1-12] The operation and
construction o f the HBTs is similar to that o f the bipolar transistors. The difference is
that in this transistor, the base-emitter junction is made by different material (e.g. GaAs
and AlGaAs.) Different semiconductor materials have different bandgap values. When
two distinct materials are brought in contact, the difference in bandgap is exhibited as
discontinuities in the conduction band and the valence band o f the semiconductor versus
depth. A discontinuity in the valence band will block holes from diffusing into the
emitter from the base and reduce the base current. This will remove the requirement to
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14
keep the base doping low, resulting in lower base resistance and improving high
frequency performance o f the devices.
Base
Em itter
collector
AV,
AEv
Figure 1.4 Band diagram o f the HBT
The current gain o f this device can be expressed as
n E Vn
P
b
•exp
v p
q A E g
( 1- 1)
kT
where AEg is the difference in bandgap. The terms vn and vp are the electron velocity (in
the base) and hole velocity (in the emitter) respectively.
This
concept
was
not
demostrated
until
1969[1-13]
with
GaAs/Ge
heterojunction grown by Liquid Phase Epitaxy (LPE). Today, most o f the HBTs are
made o f Alo.3Gao.7As and GaAs. These transistors became more popular in the 1980s
when molecular beam epitaxy (MBE) and other epitaxial reactors became available.
With these techniques, dissimilar material can be grown with high quality interface,
allowing the realization o f HBTs.
The most frequently used among them is Gallium Arsenide (GaAs) in
conjunction with Aluminum Gallium Arsenide (AlGaAs) or Indium Gallium Phosphide
(InGaP). The other popular material systems are Indium Phosphide and Aluminum
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15
Indium Phosphide. Figure 1-5 [1-14] shows a diagram o f the various possible bandgap
that can be achieved by the DI-V compounds.
LATTICE MISMATCH TO SILICON (% )
20
4 .5 r
a.
O
0.4
3.0
A lP
5 2-0
cr
ZnSe
°
CdS
A tS b
uj
iii
S
Si GaAs \
1.0
9^B U L K
!
IS L E
(G e)
5.5
InP
\
tiG e
\
0.5 ~
Z nTe
Gapi-—. Al f s
'O sj ~
CdTc
ui
1.0
G aSb
>
InAs
6.0
^
1.5
2.0
3.0
InSb
IqTe ~ 5.0
6.5
LATTICE CONSTANT (&)
Figure 1.5 Bandgap vs. lattice constant diagram o f semiconductor materials
There were many early demonstration o f HBTs in the area o f high speed ECL
circuits. In recent years, because o f the boom in the wireless communication market,
HBTs are becoming more widely used for its linearity in the wireless communication
areas. [1-15][1-16]
DI-V HBT offers the following advantages over other devices. As mentioned
already, compared to Si BJTs, HBTs have lower base resistance and their material has
higher electron mobility.
Furthermore, gold metalization is available in the DI-V
technologies compared to silicon technologies where gold is a fast diffusing deep donor
and also causes "purple plague" which is a gold-aluminum interaction.
The low
resistivity o f gold can also be used to improve the performances o f the circuits.
Compared to DI-V FET technologies, the HBT is a vertical device which naturally
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16
makes the control region shorter for faster transport without elaborate photolithography
steps. The vertical devices also utilize the active area more effectively, allowing higher
current drive for the same layout area.
1.3.2 Double Heteroj unction Bipolar Transistors (DHBTs)
The HBT mentioned in the previous section is sometimes referred to as the
single heterojunction bipolar transistor (SHBT) as it contains only one heterojunction at
the base-emitter interface. A double heterojunction bipolar transistor (DHBT) is similar
to the SHBT but it consists o f two heterojunctions for both the base-emitter and basecollector interfaces.
In addition to the aforementioned property o f hole blocking in the base-emitter
junction, the DHBT also has the following advantages. First o f all, the collector now is
made o f wide bandgap material as well, thus, the breakdown voltage o f the base
collector junction
(B V cbo)
is higher. This is suitable for power applications. The base-
collector junction and the base-emitter junction are also more symmetric in terms of
tum-on voltage. This will lower the saturation voltage
V b e ,o n - V b c ,o n ,
where V
b e ,o n
( V sa t)
because VS AT equals to
and V b c .o n are the turn on voltages o f the base-emitter and
base-collector junctions. A lowered
V sa t
is beneficial because it extends the voltage
swing o f the transistor. The base-collector junction hole blocking capability can also
enhance the DHBT switching capability as explained in chapter 5.
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17
E
B
C
Electron flow
unimpeded
hole
injection
blocked
Figure 1.6 Band diagram o f a DHBT
1.3.3 Material Choices for HBTs and DHBTs
There are many material systems which can be used in HBT and DHBT designs.
Most commonly used is the AlGaAs/GaAs system for many o f the applications in the
low gigahertz range up to the 20 GHz range. Another system that is InP/InGaAsP
system which can achieve very high mobility.
This system is frequently used for
applications with frequency in excess o f 50 GHz. However, due to the high cost o f the
InP substrate, this material system is not economically competitive.
The material
system this work will be investigating is the InGaP/GaAs system, which typically uses
GaAs substrate and its cost is similar to the cost o f AlGaAs/GaAs epi-ready wafers.
InGaP/GaAs system has the following benefits that could be o f interests for HBT
applications.
Compared to the AlGaAs/GaAs system, InGaP/GaAs has a bandgap
alignment that is more favorable for HBTs. This is shown in figure 1.7 by the larger
ratio for the valence band (AEv) offset to the conduction band offset (AEc).
This
discontinuity can achieve high emitter efficiency even at temperature as high as 200°C.
InGaP material also has fewer deep-level traps (DX centers) because indium is less
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18
reactive to oxygen than aluminum. This leads to better noise figures at low frequencies
[1-17].
The availability o f a selective etching methods for InGaP/GaAs is also an
attractive feature. InGaP can be etched by several common HC1 based chemical which
would not attack the GaAs surface. This can improve the processing yield when etching
the emitter mesa.
[1-18]
One final note, the InGaP/GaAs HBTs have also been
reported to be more rehab le because o f the quality o f the crystal compared to
AlGaAs.[l-19][l-20]
AEc=0.18eV
AEc=0.22eV
AIo.3Gao.7As
E g=1.79eV
GaAs
Eg=1.42eV
AEv=0.15eV
Ino.49 Gao.51 P
Eg=1.89eV
G aAs
E g= I.42eV
AEv=0.29eV
Figure 1.7 Band alignment for InGaP/GaAs and AlGaAs/GaAs heterojunctions
1.4 Introduction to Power Amplifiers
Having investigated the available transistors, this study will further investigate
the applications o f these technologies in various classes o f power amplifier
configurations.
As mentioned before, the power amplifier is one o f the most
troublesome elements to implement in designing a cellular telephone handset because o f
its limited efficiency and the dependency o f the battery time on this efficiency.[l-2 1 ][l22 ]
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19
Furthermore, efficient use o f the bandwidth also depends on how well each
allotted band is used. This also sets a limitation on the maximum interference each user
will produce on nearby bands. This quality closely depend on the linearity o f the power
amplifiers.
Traditionally, the efficiency and linearity o f the power amplifiers are presented
as a trade-off Most o f the PAs sold today for CDM A telephone application use the
class AB architecture. To achieve the linearity requirement, the nominal power output
must be backed o ff from the 1 dB compression point where the highest efficiency is
achieved.
In this thesis, class D switching amplifiers are studied for their power added
efficiency. Class D amplifiers are considered high efficiency switching amplifiers. The
operation o f these amplifiers is that the transistor behave as a double pole switch. It will
toggle the output voltage to be either at the maximum supply voltage,
V cc,
or the lowest
supply voltage, Vee- This behavior generates a square waveform at the output nodes of
the amplifying transistors.
The transistors either have high voltage across its terminals
and no current flow or high current flow and low voltage across its terminals, resulting
in small power dissipation in the amplifying devices.
This kind o f amplification is, however, nonlinear in nature.
To remedy the
linearity deficiency o f the class D amplifiers, class S amplifiers are proposed. A Class S
amplifier use a pulse width modulated (PWM) signal to drive a switching amplifier,
whose output can be filtered to recover the analog information represented by the PWM
waveform. [ 1-23 ]
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20
1.5 Scope o f this work
The scope o f this work includes the device physics o f the HBT and the DHBT,
as well as associated device modeling and circuit designs. Since our discussion can not
be all inclusive, the content o f this thesis will be limited to the following areas.
Chapter 2 will discuss the design and fabrication o f the DHBTs and comparable
HBTs.
The geometry o f the transistors is important for the transistor to exhibit
minimum parasitics while maximizing performance and profit. A key design issue is
self-heating. A flip chip heatsink was investigated. This chapter will also show another
main design consideration in DHBT which is the collector design. The effect o f AECon
collector current will be discussed.
The details o f the processing steps are also
discussed in this chapter.
In chapter 3, the performance o f the DHBTs are characterized and modeled.
This is done through DC measurements as well as high frequency s-parameter
measurements. From the DC measurements, the effect o f AEc current blocking effect is
explained.
T h & fj
andy^AX o f these transistors will be evaluated here. Full model o f the
DHBT will also be extracted.
Chapter 4 investigates further improvement to the transistor by adding
heatsinking structure to the transistors. The details includes the simulation and design
o f the heatsinks as well as the modeling o f the parasitic effects.
Chapter 5 studies the collector charge storage effect in detail. A novel charge
storage measurement method is proposed.
In this method, base-collector diode is
driven with sinusoidal excitation and the charge storage effect is observed in the
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21
negative half cycle o f the output. A detailed mathematical evaluation is also given in
this part.
Then the focus is shifted to amplifier designs in chapter 6 . The typical class AB
bias conditions were evaluated with manual loadpulling techniques to show that the
DHBTs are capable o f delivering competitive performance compared to commercial
class AB amplifiers. Designs that take advantage o f the fast switching behavior o f the
DHBTs are the class D and class S amplifiers.
The details in circuit designs and
measurement results are discussed here.
Finally, chapter 7 will provide a summary and conclusion. This chapter will also
discuss further improvements that can be done for the InGaP DHBTs and related
circuits.
In addition, the basics of the transistor transit time and figure o f merits are
explained in appendix A. In appendix B, some measurement results that shows the
material characteristics. From the breakdown voltages, we investigated the breakdown
field o f the InGaP material.
Furthermore, a new method o f measuring saturation
velocity through extracted C bc has been proposed in appendix C.
applied to GaAs, but not to InGaP.
This method is
The Cbc extraction yield interesting results
indicating that charges has been trapped and stored in the quantum well formed by the
AECregion in the collector.
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22
Reference
1-1.
F C C U .S . F r e q u e n c y A llo c a tio n C h a r t,
U.S. Government Printing Office, Washington
D.C., 1996
1-2. H.L. Krauss, C.W. Bostian, and FJH. Raab,
York, 1980
1-3. Behzad Razavi, R F
M ic r o e le c tr o n ic s ,
S o lid S ta te R a d i o E n g in e e r in g ,
Wiley, New
Prentice Hall, NJ, 1998
1-4. PJR.. del la Houssaye, C.E. Chang, B. Offord, G. Imthum, R. Johnson, P.M. Asbeck, GA.
Garcia, I. Lagnado, "Microwave Performance of Optically Fabricated T-Gate 100 nm
Thick Silicon on Sapphire MOSFETs," I E E E E le c tr o n D e v i c e L e tte r , vol. 16, no. 6 , pp.
289-292, Jun. 1995
1-5. C.E. Chang, PM . Asbeck, P.R. de la Houssaye, G. Imthurm, G.A.Garcia, and I. Lagnado,
"Microwave Characterization of Sub-micron n- and p- channel MOSFETs Fabricated with
Thin Film Silicon-On-Sapphire," 1 9 9 4 I E E E M T T - s I n t e r n a t i o n a l M ic r o w a v e S y m p o s iu m
D i g e s t , vol. 1, pp. 405-408, May 1994.
1-6. W. Schockley, U.S. Patent 2,569,347 (1951)
1-7. D.L. Harame, J.H. Comfort, J.D. Cressler, E.F. Crabbe, J.Y.-C. Sun, B.S. Meyerson, and
T.Tice, "Si/SiGe Epitaxial Transistors—Part I: Materials, Physics, and Circuits," IEEE
Transaction on Electron Devices, vol 42, no. 3, pp. 455-468, March 1995
1-8. D.L. Harame, J.H. Comfort, J.D. Cressler, E.F. Crabbe, J.Y.-C. Sun, B.S. Meyerson, and
T.Tice, "Si/SiGe Epitaxial Transistors—Part II: Process Integration and Analog
Applications," IEEE Transaction on Electron Devices, vol 42, no. 3, pp. 469-482, March
1995
1-9. D.C. Ahlgren, et al, "Manufacturability Demonstration of an Integrated SiGe HBT
Technology for Analog and Wireless Marketplace," I E D M D i g e s t , 1996
1-10. G. N. Henderson, M.F. O'Keefe, T.E. Boles, P. Noonan, J.M. Sledziewski, and B.M.
Brown, "SiGe Bipolar Junction Transistors for Microwave Power Applications," 1 9 9 7
l E E E - M T T - s I n te r n a tio n a l M ic r o w a v e S y m p o s iu m D ig e s t, pp. 1299-1302
1-11. M. Rodwell, et al, “Transferred-Substrate HBT integrated circuits,” S o lid - S ta te
E l e c t r o n i c s , vol.43, no. 8 , Aug. 1999, p. 1489-95
1-12. H. Kroemer, "Theory of Wide-Gap Emitter for Transistors," P r o c .
1957
IR E ,
vol. 45, p. 1535,
1-13. D.K. Jadus, D.L. Feucht, "The realization of a GaAs-Ge Wide Band Gap Emitter
Transistor", I E E E T ra n s. E le c tr o n D e v ic e , vol. 16, p 102, 1969
1-14. S.M. Sze, H i g h - S p e e d
S e m ic o n d u c to r D e v ic e s ,
Wiley, New York, 1990
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23
1-15. M. Salib, et al, "A Robust 3W High Efficienty 8-14 GHz GaAs/AlGaAs Heterojunction
Bipolar Transistor Power Amplifier," 1 9 9 8 I E E E - M T T - s I n te r n a tio n a l M ic r o w a v e
S y m p o s iu m D ig e s t, pp. 581-584
1-16. T. Iwai, S. Ohara, T. Miyashita, and K. Joshin, "63.2% High Efficiency and High
Linearity Two-stage InGaP/GaAs HBT Power Amplifier for Personal Digital Cellular
Phone System," 1 9 9 8 I E E E - M T T - s I n te r n a tio n a l M ic r o w a v e S y m p o s iu m D ig e s t, pp.
435-438
1-17. R. Plana, J. Graffeuil, S.L. Delage, H. Blank, M.A. di Forte-Poisson, C. Brylinski, and E.
Chartier, "Low Frequency Noise in Self-Aligned GalnP/GaAs Heterojunction Bipolar
Transistors," E le c tr o n ic s L e tte r s , vol. 28, p. 2354, 1992
1-18. JJR. Lothian, JJVI. Kuo, F. Ren, and S.J. Pearton, "Plasma and Wet Chemical Etching of
InGaP," J . E le c tr o n i c M a te r ia ls , vol. 21, p.441, 1992
1-19. T. Takahashi, S. Sasa, A. Kawano, T. Iwai, and T. Fujii, "High-reliability InGaP/GaAs
HBTs fabricated by Self-Aligned Process," 1 9 9 4 I E D M d i g ., p.191, 1994
1- 2 0 .
N. Pan, J. Elliott, M. Knowles, D.P. Vu, K. Kishimoto, J.K. Twynam, H. Sato, M. T.
Fresina, and G.E. Stillman, High Reliability InGaP/GaAs HBT, E le c tr o n D e v ic e
L e t t e r s , vol. 19, no. 4, p. 115, 1998
1- 2 1 .
L. Larson, R F a n d M ic r o w a v e
House, Boston, 1996
C ir c u it D e s ig n f o r W ir e le s s C o m m u n ic a tio n s ,
Artech
1-22 J. Walker, H ig h P o w e r G a A s F E T A m p l i f i e r s , Artech House, Boston, 1993
1-23. H.L. Krauss, C.W. Bostian, and F.H. Raab, S o l i d
Yor, 1980, p.458
S ta te R a d io E n g in e e r in g ,
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Wiley, New
Chapter 2 DHBT Design and Processing
2.1 Layout Related Issues
In general, the goal o f the semiconductor manufacturer is to make the most
devices in the smallest area for the highest profit.
Therefore, when laying out the
transistors, the trend is to pack the devices as densely as possible. This is a natural
move for high density digital circuitry. By minimizing the area, parasitic capacitance is
minimized as well. Thus the performance o f the high speed logic would benefit from
scaling. There are some unpleasant side effect such as high cost in lithography and
physical effects such as short channel effect and lowered breakdown voltage. However,
compactness has been the aim for most layout strategy.
For analog devices, however, the power requirement often dictates the sizes o f
the transistors. Therefore, one does not arbitrarily scale the transistor down to increase
operation speed. One also has to take in consideration effects such as electroraigration
or thermal effects. Electromigration is a mass transport phenomenon during which the
high electric field induced by the flow o f electric current causes physical movement of
atoms.
This effect is detrimental to transistor operations.
Thermal effects will be
considered in a later section.
2.1.1 Current crowding and effectiveness of the emitter area
Because the sheet resistance o f the base, the center o f the base-emitter region
suffers from resistive voltage drop, reducing effectiveness o f the transistor in the center
region (compared to the perimeter).
Figure 3.1 shows the decreased base-emitter
voltage in the center o f the emitter area. Therefore when designing the transistor lateral
24
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25
geometry, it is important to limit the distance from the center o f the transistor to the base
contact. In this work, most o f the transistors are laid out with the following unit cell.
Each emitter size is 2pm by 10pm, and each unit cell has two emitter fingers.
decrease id
base em tter
voltage
imitter
Base
Figure 2.1 Current crowding effect (Darkened area shows lowered base emitter voltage)
2.1.2 Base resistance
Internal base resistance is a function o f the base doping and base thickness and
these topics will be discussed in the layer design section. The external base resistance,
in addition to being a function o f the doping and thickness, is also a function o f the
layout (lateral geometry). However, the area beneath the external base also add to the
external base-collector capacitance (C bc)- A s discussed in appendix A of this work,
Cbc
is a feedback capacitance and, along with Rb, will reduce the frnax of the transistor.
Therefore, it is undesirable to have excess base contact area.
For this work, we chose self-aligned base. The self-aligned base takes advantage
of the base contact etch step, and evaporate contact metal to surround the emitter. The
self-aligned base, which allows the base contact to be as close to the emitter as possible,
will lower the base resistance and reduce the base pedestal area. [2-1] The conceptual
sequence o f the self-aligned base processing is illustrated in figure 5.2.
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26
(1) etch to base
>ase/ photoresist
with undercut
Z
/
\
j l
(2) Deposite base metal
(3) Lift off
7 m \
L
e
/-
Figure 2.2 Self-aligned base contacts
T o complete the description o f the unit cell transistor, there are two collector
contacts on either side o f the emitter, spacing 2.5pm away from the base pedestal. The
collector contacts must be etched down to the highly doped sub-collector for low
collector contact resistance. In power transistors technologies such as the transistors
designed in this thesis, the depth o f such etch can be as large as 1 pm. Since this is
large to the 0.5 pm thick interconnect metal, it became imperative to strategically place
several dielectric "steps" to allow the interconnect metal to fall into the collector contact
area gracefully without breakage. Figure 2.3 shows the basic layout o f the transistor in
this w ork.
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27
em itter
collector
- —b a s e Figure 2.3 Basic layout o f an unit cell for the HBTs
2.1.3 Thermal effects
GaAs material has one drawback compared to silicon substrates and that is the
thermal conductivity is a lower in GaAs. The conductivity o f GaAs is 0.46 W/cm K,
compared with silicon’s 1.5 W/cm K This means that GaAs transistors are more likely
to suffer from thermal effects if not designed properly.
The use o f AlGaAs/GaAs HBTs in power amplifiers has been heavily
investigated in recent years, partially because o f high RF power handling capability,
linearity and power-added efficiency. One o f the problems faced with HBTs is self­
heating due to the relatively low thermal conductivity o f GaAs substrates as stated
above.
This self-heating effect is manifested by a reduction o f forward current gain,
since the gain o f the HBTs can be calculated by the following equation.
«
«
qAE'
-expkT
( 2 - 1)
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28
Thus, in an HBT common emitter IV curve, one would observe the reduction of current
at higher Vce (higher power) region, leading to the appearance o f negative resistance.
At even higher power levels, and when the transistor has more than one emitter
finger, the current gain can also collapse because o f thermally-induced current hogging
[2-2] by non-uniformity in the emitter fingers. This effect will cause a single transistor
to take up more current than the rest. It is a positive feed back situation where the end
result is the complete collapse o f gain. Heat sinking structures can reduce the self­
heating effects by facilitating better heat transport, and thermal shunting structures can
reduce the tendency toward current collapse by minimizing temperature differences
among emitter fingers [2-3]. Heatsinking approaches to date include wafer thinning and
gold plating, etching bathtub via structures into the backside, and flip-chip bonding to
bump heatsink on top o f each transistor emitter [2-4],
In this thesis, the multi-cell transistors are laid out with the base pedestals being
32 pm apart.
•<------ 32 |jm — ►
Figure 2.3 Layout for a multi-cell transistor
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29
Another method to limit thermal instability is to use emitter ballast resistors.
The resistors are connected to each emitter finger. One way to describe this effect is to
visualize the cells o f the transistors to be individual transistors connected in parallel.
Due to processing variations, one of the transistor cells inevitably has higher gain than
others. This would cause this transistor cell to carry more collector current, driving the
temperature higher. As this particular cell heats up, collector current will increase for
the same
V Be -
This would cause the transistor cell to heat up even more in a positive
feedback fashion causing the instability in current gain. To combat this effect, negative
feedback is used in the form o f emitter degeneration resistors. As the emitter current
increases, the voltage across the ballast resistor increases. Thus the
V be
is reduced
making the gain o f each cell even.
Figure 2.4 Limiting the current hogging with emitter ballast resistors
2.2 Device Design
The device design consist of epitaxial layer designs and device processing
designs, where the epitaxial design governs the vertical structure o f the transistors and
the processing governs the lateral structures o f the devices.
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30
2.2.1 Epitaxial Layer Design
HBTs are fabricated with epitaxial materials.
That is the emitter, base, and
collector dopings are grown into the crystal layers at the surface o f the wafer rather than
diffused or implanted into the bulk o f the substrate. Because o f the advances in the
epitaxial crystal growth techniques, precise thickness and doping level can be easily
achieved with MBE or MOCVD reactors.
The definition o f the devices begins by the vertical description o f the layers that
make up the emitter, base and collector. Then the lateral geometry described in the
previous section can be applied to these layers to define specific location o f the contacts
to these layers. As stated in the last chapter, the material system chosen for the HBTs in
this work corresponds to InGaP matching to GaAs. InGaP is chosen because o f the
lattice matching to GaAs, low DX center, and favorable bandgap alignment with GaAs.
The various layer structures used in this project are listed in table 2.1. These
structures were fabricated at various facilities and evaluated to demonstrate the benefits
o f the InGaP DHBTs. Process 1A and IB were fabricated at UCSD Central Fabrication
Facility (CFF) by Dr. Yue-ming Hsin. Process 2 was carried out at Network Device
Inc., a commercial GaAs foundry service. Process 3A, D, and F were fabricated at
Rockwell Science Center. The processing techniques are similar and are described in a
later section o f this chapter.
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31
Table 2.1 MURIDHBT/SHBT Device Layer structures
H m H
HHRH
i HQI
m
mm
1200A
n-InGaAs
1.0E19
300A
n-IuGaAs
to n-GaAs
1E19
300A
GaAs (Si)
1.0E19
1400A
n-InGaAs
1E19
400A
n-InGaAs
to n-GaAs
1E19
400A
GaAs (Si)
5.0E18
3000A
InGaP (Si)
5E18
3 00A
InGaP (Si)
4.5E17
600A
GaAs (C)
4.0E19
500A
GaAs (Si)
3.0E16
InGaP (Si)
4.5E17
400A
GaAs (C)
4.0E19
500A
GaAs (Si)
3.0E16
200A
200A
InGaP (Si)
4.5E17
InGaP (Si)
5.0E17
200A
200A
InGaP (Si)
3.0E16
4000A
InGaP (Si)
5.0E18
500A
GaAs (Si)
5.0E18
6000A
InGaP (Si)
3.0E16
8000A
InGaP (Si)
5.0E18
500A
GaAs (Si)
5.0E18
6000A
InGaP (Si)
3.0E17
500A
GaAs (C)
4.0E19
600A
GaAs (Si)
3.0E16
3 00A
InGaP (Si)
5.0E17
100A
InGaP (Si)
3.0E16
3600 A
InGaP (Si)
5.0E18
500A
GaAs (Si)
5.0E18
6000A
InGaAs Cap
none
none
InGaAs
Grading
none
none
Emitter cap
GaAs (Si)
5E18
GaAs (Si)
5E18
1200A
InGaP (Si)
5.0E18
300A
InGaP (Si)
4.5E17
600A
GaAs (C)
4.0E19
500A
GaAs (Si)
3.0E16
3000A
Emitter
Base
Collector
Sub­
collector
GaAs (Si)
3.0E17
3500A
GaAs (Si)
5.0E18
6000A
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none
none
GaAs (Si)
1.0E19
5 00A
GaAs (Si)
5.0E18
2500A
InGaP (Si)
3.0E17
600A
GaAs (C)
4.0E19
600A
GaAs (Si)
3.0E16
3 00A
InGaP (Si)
5.0E17
100A
InGaP (Si)
3.0E16
3600A
InGaP (Si)
5.0E18
500 A
GaAs (Si)
5.0E18
7000A
32
All o f the wafers listed above are grown by Kopin Corporation by MOCVD.
The growth techniques are mature and the reliability o f the devices fabricated by this
process has been reported in the literatures [2-5]. The thickness o f each layer is designed
as follows. The emitter cap is used for lowering the emitter resistance. Some o f the
processes has InGaAs cap which can further reduce the emitter resistance. The thick
InGaAs cap can also help creating undercutting structures for self-aligned base contacts
described in section 2.3. The intrinsic emitter is made o f the InGaP material and has
3el7 n-doped at a thickness o f 400A to 600A. The wide bandgap property o f InGaP is
used to block holes from back injection into the emitter. Lighter doping in emitter can
reduce the base emitter capacitance (C be)[2 -6 ] thus increase the / r especially at lower
current density. However, this will also reduce the DC current gain Iife- To counter the
undesired drop in gain, pulse (delta) doping methods are used. For this thesis, the focus
was to investigate the usage o f DHBTs at low gigahertz switching applications and
reduced C be Lightly Doped Emitter (LDE) methods were not used.
The bases are 5 0 0 A or 6 0 0 A thick and highly p-doped at 4el9.
The high
doping can reduce the base resistance to a minimum. The layer beneath the base are the
collector layers. For a SHBT, the entire collector is made up o f GaAs lightly doped.
For DHBTs the main drift region of the collector is InGaP. However, in the transition
region region between base and collector between there is concern regarding the
conduction band discontinuity (AEC) and therefore, the design o f the transition region is
more complicated and will be explained in section 2.2.2.
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33
2.2.2 AEc consideration
In a DHBT, the charge carriers, electrons, travel from the emitter through the
base into the collector. However, at the interface o f the GaAs and InGaP, there exists an
energy barrier. Because o f the difference in electron negativity of the two materials, the
bandgaps are lined up such that the conduction band energy o f the InGaP material is
higher than the conduction band energy o f GaAs by 0.18eV as shown in chapter 1. The
presence o f this barrier impedes the flow o f electrons from the base to the collector.
The charges are "blocked" by the barrier and will recombine in the base region, resulting
in higher base current, thus lower gain. Figure 2.5 shows the current blocking effect o f
the AEc-
electron flow
partially
blocked
A E c = 0.1 8 e V
k ________
t
GaAs
GaAs
InGaP
(a)
InGaP
(b)
Figure 2.5 (a) Bandgap alignment of GaAs to InGaP (b) electron transport
across a GaAs/InGaP p-n heterojunction
Various methods can be used to combat the effects o f AEc. In the AlGaAs/GaAs
system, linear grading o f Aluminum composition can be used to grade the junction.
However, InGaP can not be graded to GaAs unless InGaAsP is used, which complicates
both the material growth and the subsequent processing. Another approach is to use a
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34
chirped superlattice, in which multiple quantum wells create an intermediate state to
enable the current transport[2-7]. This is an expensive and time consuming process,
requiring the growth method to be MBE rather than MOCVD.
A widely accepted method to reduce the current blocking effect o f the AEc is to
use a GaAs undoped set back layer combined with a n-type dipole doping at the
GaAs/InGaP interface. [2-8]
In this method, the function o f the setback layer is to
provide a depleted n-type GaAs region allowing the collector conduction band to be
lower than the edge o f the base conduction band, even after the discontinuity (AEc). A
n-type pulse doping layer (5el7, 200A) was added at the interface pulling the
conduction band down further lowering the energy barrier to allow electron flow.
Figure 2.6(a) show the function o f the setback layer and figure 2.6(b) shows the effect o f
adding n-type pulse doping. As electron diffuse across the base and enter the collector,
they will be swept into the collector because o f the presence o f electric field in the
setback layer. The electrons will pick up some energy as they accelerate due to the
electric field.
The energy o f the electron allows the electron to travel across the
quantum well o f the AEC.
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35
o o o
electron flow
undisturbed
X
i
Effect of n type
pulse doping
(in d ash lines)
G aA s
In G a P
(a)
(b)
Figure 2.6 (a) The effect o f setback layer (b) The effect o f n-type pulse doping
This method has been found successful in many reported results. However, as
the current density increases, the collector conduction band energy is raised due to the
presence o f the injected electron which will compensate the positive space charge to
bring up the entire band structure, which can cause the AEc to protrude higher than the
edge o f the base conduction band and cause the current blocking effect again.
2.3 Device Processing
The devices are processed at UCSD, Rockwell Science Center, and at Network
Device Incorporated. The devices made at UCSD were fabricated by Dr. Yue-Ming
Hsin. Rockwell Science Center (Thousand Oaks, California) is the research center for a
major GaAs HBT production company. Network Device Incorporated, NDI, at
Sunnyvale, California is a commercial GaAs foundry service. The availability o f the
GaAs foundry service and their ability to process InGaP HBTs shows the increasing
importance o f both the emergence o f the high frequency electronics industry and the
suitability GaAs technology in this area.
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36
The process 3 (Rockwell Science Center process) will be described in detail [29] in this work because o f this author's involvement in the fabrication process.
Rockwell self-aligned process was used.
The
The benefit o f the self-aligned b a se as
mentioned before is to allow the base contact to be as close to the emitter as possible
reducing the base resistance as well as the size for base pedestal.
Process 2 (1NDI
Process) was a non-self-aligned base where the base contact etch and base comtact
metalization are done with separate photo-resist mask. Though extra steps were needed,
non-self-align base contact processes tend to have higher yields and are widely accepted
in the industry. Process 1 was fabricated at UCSD and is similar to process 3 withiout
the planarization steps.
2.3.1 Self-Aligned Process
The details o f the process 3 self-aligned HBT processing are shown in figure 12.7.
Figure 2.7 (a) and (b) show the formation o f the base pedestal. The area outside the
pedestal is chemically etched away. The wafer then is planarized by timed deposition o f
SiO, an additional polyimide deposition, and a polyimide etch.
planarization is shown in figure 2.7(c).
(a) Epitaxial grown wafer
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The result o f the
37
(b) Formation o f base pedestal
(c) Planarization by SiO and polyimide
Photoresist
(d) Self-Aligned base contact metalization and the formation o f emitter mesa
|
I
(e) Photoresist removal and metal lift-off process
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(f) SiN deposition
(g) Etch collector contact
(i) Interconnect metalization
Figure 2.7 (a)-(i) Self-aligned HBT and DHBT fabrication process
The self-aligned base is formed in step d and e. A single photolithography step
is used for base contact etch, metal deposition and the subsequent lift-off. Base metal
deposited was 150A Pt/200A Ti/350A Pt/800A A u/2 5 A Ti.
This allows the base
contacts to be as close to the emitter as possible. However, this also increase the chance
o f the base contacts being shorted to the emitter. The undercutting etch o f the emitter
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39
will be explained further. For process 2, two separate photolithography steps were
taken for the base contact etch and the patterning o f the base metal.
After the base contact is formed, PECVD deposited SiN is used to protect the
transistors' base emitter structures. Then a lithography step was done to define the area
for etching away the SiO dielectric materials in order to form the collector contacts. In
order to ensure the connection o f metal 1, the removal o f the dielectric and the
subsequent etch down to the sub-collector were spaced apart by at least 1.4 pm to
ensure the metal does not break.
Collector metal mask was applied after the dielectric
etch and collector metal (1200A AuGe/300A Ni/1200A Au) was deposited.
Following the formation of the collector contact, a critical alignment was done to
align an emitter contact to the emitter mesa, which is the smallest feature for these
devices. The current technology allows 0.25 pm alignment tolerance on either side of
the emitter contact. Emitter metal deposited was 1200A AuGe/300A Ni/1200A Au and
was annealed for 2 minutes at 370°C.
After the devices are fabricated, two levels o f interconnect metals were
deposited, with SiN and polyimide as the intermetal dielectric. Metal 1 is 0.5 pm thick
and metal 2 is 2 pm thick to support the low resistance necessary for microwave
circuits. A Metal 1-SiN-Metal 2 structure can also be used as the MIM capacitors as
part of the biasing and matching structures for the circuit designed in this work.
In this work, GaAs and InGaP materials can be etched with wet etching. The
chemical used to etch away the GaAs material is a combination o f KbOiHiPO^EkOz
(200:10:10) at an etching rate of around 30A/sec.[10] This is one o f the most popular
etching systems used for polishing and mesa etching. The InGaP material can be etched
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40
away with "pure" or "from the bottle" HC1 (in our process, this is 38% HC1, 62% H 2O).
The etch rate is around 200A/sec. At the interface o f GaAs and InGaP, the material may
take longer to etch depends on the quality o f the material. Alternating etch between the
GaAs etch and InGaP etch may be required at these interfaces. However, due to the
selective etching nature o f this material system, precise etching rate and the degree o f
difficulty in timing has been drastically reduced.
Different concentration o f the etchants will cause the material to etch at different
rate at different crystal orientations. This is an important consideration for self-aligned
base contacts. If the slope o f the resulting grove has the improper profile, the self­
aligned base contact will end up shorted to the emitters (figure 2.8). Non-self-aligned
InGaP DHBTs fabricated at NDI does not suffer the same problem.
Emitter Mesa
Base Contact
(a)
(b)
Figure 2.8 (a) Proper etching profile for self-aligned base (b) Improper etching profile
The devices are isolated with He+ ion implants. During the implant, thick photo
resist was used to protect the transistor area. Proper care was taken (during the layout
and mask fabrication phase) to ensure that the implantation were far enough removed
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41
from the active device so that it will not damage the edge o f the base region, which will
degrade the gain by increase the base current in traps generated by the implant damage.
2.3.2 Non Self-Aligned Process
The NDI process, which was used to fabricate a portion o f the devices used in
this thesis, is similar to the Rockwell process in terms o f the emitter-base-collector layer
designs and lateral structures.
However the details o f the processing steps are
proprietary and are not available to their customers at this time.
There are several advantages for non-self-align process. One o f these is the
ability to place base contact at arbitrary distance from the emitter mesa. This reduces
the chance o f the base emitter shorting as discussed above. Along with the ability to
place the base contact further away, the non-self-align process also allows a natural
formation o f the emitter ledge structure[2-l 1]. A InGaP emitter ledge can be formed by
the thin InGaP emitter layer itself. Emitter ledge is important in suppression o f lateral
recombination at the surface o f the exposed GaAs base region[2-12] and is important
for reliability o f the HBT [2-13].
Emitter ledge
a s f o r m e d by
InGaP layer
\
Figure 2.9 Emitter ledge structure formed by InGaP layer
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42
The disadvantage o f the non-self aligned process is the increase in base
resistance, Rb, due to the distance away from the emitter mesa. Another disadvantage is
the increase in the base mesa size which increases the base collector capacitance,
Both the
R b
and the
C bc
C bc-
decrease the maximum frequency o f oscillation, /max- For
large HBTs used for power transistors (1W devices), the / m
a x
in recent years has been
reported to be around 20GHz. (The lowered HBT performances for large transistors are
due to the large parasitic components o f the
m ax im u m
C b c -)
Thus, at PCS band (near 2GHz), the
available gain would be around 20dB. Further decrease o f the/max can limit
the usefulness o f the devices.
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43
Reference
2-1 M.F. Chang, PM . Asbeck, K.C. Wang, G.J. Sullivan, N.H. Sheng, J. Higgins, D.L. Miller,
"AlGaAs/GaAs Heterojunction Bipolar Transistors Fabricated Using a Self-Aligned DualLift-Off Process," IEEE Eletron Device Letter, vol. EDL-8, p. 303, 1987
2-2. William Liu, "Thermal Coupling in 2-Finger Heterojunction Bipolar Transistors," I E E E
T r a n s a c tio n s o n E le c tr o n D e v ic e s , vol. 42, pp. 1033-1038, June 1995
2-3. J. Sewell, L.L. Liou, D. Barlage, J. Barrette, C. Bozada, R. Dettmer, R. Fitch, T. Jenkins,
R. Lee, M. Mack, G. Trombley, and P. Watson, “Thermal Characterization of ThermallyShunted Heterojunction Bipolar Transistors,” I E E E E le c tr o n D e v ic e L e tte r s , vol. 17, pp.
19-21, Jan. 1996
2-4. H. Sato, M. Miyauchi, K. Sakuno, M. Akagi, M. Hasegawa, J.K. Twynam, K. Yamamura
and T. Tomita, “Bump Heat Sink Technology—A Novel Assembly Technology Suitable
for Power HBTs,” IEEE GaAs IC Symposium, pp. 337-340, 1993
2-5. That reliability paper reported by Kopin
2-6. Charles Chang, N o v e l L o w
P o w e r H B T T e c h n o lo g y ,
Ph.D. Thesis, UCSD, 1995
2-7. A.C. Seabaugh, Y.C. Kao, W.R. Frensley, J.N. Randall, and M.A. Reed, "Resonant
transmission in the base/collector junction of a bipolar quantum-well resonant-tunneling
transistor," A p p l ie d P h y s ic s L e tte r s , 59, pp. 3413-3415, 1991
2-8. J.I. Song, C. Caneau, W.P. Hong, and K.B. Chough, "Characterisation of GalnP/GaAs
Double Heterojunction Bipolar Transistors with different collector Designs," E le c tr o n ic s
L e tte r s , Vol. 29, No. 21, pp. 1881-1883, 1993
2-9. Mau-Chung F. Chang, Peter Asbeck, K.C. Wang, G.J. Sullivan, Neng-Huang Sheng, John
A. Higgins, and D.L. Miller, “AlGaAs/GaAs Heterojunction Bipolar Transistors
Fabricated Using a Self-Aligned Dual-Lift-Off Process,” I E E E E le c tr o n D e v ic e L e tte r s ,
vol 8, No. 7, pp. 303-305, 1987
2-10. Ralph Williams, M o d e m
101-106, 1990
G a A s P r o c e s s in g M e th o d s ,
Artech House, Boston, MA pp.
2-11. K. Hirata et al, “I n G a P /G a A s S u b -s q u a r e -m ic r o n e m itte r H B T w ith f MAX > 1 0 0 G H z ,"
Japanese Journal of Applied Physics, Part 1-Regular Paper Short Notes & Review
Papers, 1997 Mar, V36, N38, pp. 1799-1803
2-12. M. Wetzel, M. Ho, P. Asbeck, P. Zampardi, C. Chang, C. Farley, and M. Chang,
“Modeling Emitter Ledge Behavior in AlGaAs/GaAs HBTs,” International Conference3
on GaAs Manufacturing Technology, 1997, pp. 89-92
2-13. T. Henderson, D. Hill, W. Liu, D. Costa, H.F. Chau, T.S. Kim, and A. Khatibzadeh,
“Characterization of Bias-Stressed Carbon-Doped GaAs/AlGaAs Power Heterojunction
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
44
Bipolar Transistors,” I n te r n a tio n a l E le c tr o n
D e v ic e M e e tin g ,
1994, pp.187-190
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Chapter 3. Device Characteristics
This chapter discusses the measured results for the transistors described in
chapter 2. The characterization includes static (DC) characteristics and dynamic (RF)
characteristics.
3.1 DC Measurements
DC Characteristics o f particular importance include DC gain, the thermal
behavior, parasitic resistance elements and the breakdown voltages. In addition to these
commonly measured values, we will also pay special attention to the saturation voltage
and the behavior in the saturation region to evaluate the problems that can possibly arise
with various designs o f InGaP DHBTs.
Termination
load
Termination
load
HP 4145
Parameter
Analyzer
Figure 3.1 Test setup to minimize transistor oscillation
Measurements were done with on-wafer probing and a HP4145B Parameter
Analyzer.
The transistors were designed to have high gain up to several tens o f
gigahertz. At some frequency, the output noise signal is reflected back to the device
from the cables and testsets. This output signal is coupled back to the input through
feedback capacitance internal to the device. Then, it is possible that positive feedback
45
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46
m ay occur and wide band oscillation would take place, causing large swing in voltage
and current. If oscillation occurs, it becomes difficult to obtain the proper DC behavior.
One can reduce this oscillation effect by using ferrite beads around lead wires
that lead to the curve tracer or parameter analyzers[3-l]. This is particularly effective in
the emitter lead because the high RF impedance in the emitter can effectively reduce the
RF gain in the transistors. However, the beads may be less effective at high frequencies.
Another approach is to use bias tees and properly terminate the coaxial cables used for
the measurements. Although the transistors do not necessarily have 50 ohm input and
output impedance, the terminations help to absorb some o f the noise energy and reduce
the oscillation. If oscillation persist, then matching with proper resistive termination
other than 50 ohm might become necessary. Figure 3.1 shows the configuration of this
oscillation suppression method.
The following sections will describe in detail the DC results o f each lot
described in the previous chapter.
3.1.1 Process 2 GalnP DHBT DC Characteristics
The process A lot o f InGaP DHBTs was processed by Network Device
Incorporated (NDI), a commercial GaAs foundry service. The device structure is shown
in table 3.1. These devices were fabricated with procedures similar to the techniques
described in chapter 2 except the base contact was formed with a non-self-aligned
process.
In a non-self-aligned technology, the emitter mesa and base contacts are
formed with different mask steps. This sets the base contact further away from the
emitter mesa thus increasing the base resistance. However, this process will eliminate
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47
the possibility o f the base contact metal shorting with the emitter mesa, promoting
higher yield in large quantity production.
Table 3.1 Process 2 GalnP Layer structure
NDI DHBT
Process
InGaAs Cap
InGaAs Grading
Emitter cap
Emitter
Base
Collector
Sub-collector
2
1.0E19
n-InGaAs
n-InGaAs to n-GaAs 1.0E19
1.0E19
GaAs (Si)
4.5E17
InGaP (Si)
4.0E19
GaAs (C)
3.0E16
GaAs (Si)
5.0E17
InGaP (Si)
InGaP (Si)
3.0E16
5.0E18
InGaP (Si)
GaAs (Si)
5.0E18
Figure 3.2 shows the Gummel plot (log
lc
and log
Ib
3 00A
3 00A
1400A
400A
500 A
200A
200A
8000A
500 A
6000A
versus
V be
with
V bc= 0)
of
a 40pm2 emitter area (2pm x 10pm x 2 emitter fingers) device and figure 3.3 shows the
common emitter characteristics (lc versus Vce with stepped Ib) o f the same device. The
DC current gain for this device can be determined from the Gummel plot to be 40. For
microwave amplifier applications, this current gain is adequate. If the current gain is
higher, the transistor m ay cause the amplifier to oscillate; it can also reduce B V c e o -
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48
1.00E-01
1.00E-02 -1.00E-03 - 1.00E-04 --
c
3
1.00E-05 -1.00E-06 -1.00E-07 1.00E-08 -1.00E-09 -1.00E-10
0.9
1
1.2
1.1
1.3
VBE [V]
Figure 3.2 Gummel Plot for a 40 Jim2 Process 2 GalnP DHBT
8.0 0 E -0 3
7 .0 0 E -0 3 ■6 .0 0 E -0 3 - •
5 .0 0 E -0 3 ■-
<
u
4 .0 0 E -0 3 ■3 .0 0 E -0 3 - ■
2 .0 0 E -0 3 - 1 .00E -03 ■O.OOE+OO - ,
-1.0 0 E ^)3
0
1
2
3
4
5
Vce [V]
Figure 3.3 Common Emitter Characteristics o f the 40 jim2 Process 2 DHBT (Ib
step=50(iA)
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49
Another important feature o f the DHBT can be seen in the common emitter
behavior. Figure 3.4 shows a close up look o f the common emitter offset voltage. For
the process 2 DHBTs, the offset voltage is 0.04V. The offset voltage is defined as
V be(on)-Vbc(on) ^ ie same measurement for an AlGaAs/GaAs SHBT with identical
lateral geometry and similar layer thickness (manufactured by the same foundry) is 0.15
V (figure 3.5) and some may reach as high as 0.25V.
In recent years, the circuit
designers and the wireless industry have been promoting low voltage mobile
applications in an effort to reduce the weight o f the batteries and extend the usage o f the
circuits as the battery voltage drops at the end o f its discharge cycle.
The 0.1 V
extension in operation range can be significant (—5%) for some o f the recent
applications with the 1.9V technologies.
1.00E-03
5.00E-04 --
0.00E+00
-5.00E-04 --
-1.00E-03
0
0.1
0.2
0.3
0.4
0.5
Vc e M
Figure 3.4 Offset voltage for the 40 p.m2 Process 2 DHBT (IB step=T0pA)
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50
1.00E-03
5.00E-04
<
O.OOE+OO
-5.00E-04
0
0.1
0.2
0.3
0.4
0.5
V c e [V]
Figure 3.5 Offset voltage for the 40 fim2 AlGaAs/GaAs SHBT (IB step=10(iA)
The other possible advantage is the breakdown voltage. Figure 3.6 shows the set
up for measuring B V cbo and B V ceo corresponding measured values for the Process 2
DHBTs are 2 8 V and 2 2 V respectively. These measurement results contribute to further
understanding o f the InGaP material. Details for the material properties related to these
breakdown voltages are discussed in the appendix B.
B V ceo Measurement
Figure 3.6
B V cbo M easurement
Measurement setups for breakdown voltage evaluation
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51
Another benefit o f the InGaP material system is the high temperature current
gain behavior o f the device. Because the large valence band discontinuity o f the InGaP
to GaAs, the hole blocking effect at high temperature can still hold. Figure 3.7 shows
the the behavior o f the InGaP/GaAs DHBT at 200°C. The forward current gain, (3,
drops to 60% o f the current gain at 25°C. The current gain o f an AlGaAs/GaAs HBT
typically drop to 30% at 200°C [3-2].
From the discussion above, the process 2 InGaP DHBT has achieved an
adequate DC current gain, low
V c e ,s a t ,
high breakdwon and good thermal behavior.
However, the collector resistance seems to be high from the common emitter
characteristics. The detail o f this high collector resistance will be discussed in section
3.2.
3.1.2 Process 3 GalnP DHBT DC Characteristics
Under the MURI program, Rockwell Science Center also processed several lots
o f the InGaP DHBT. Process 3 (Rockwell InGaP DHBT) structures can be found in
table 3-2. The process used in for these devices is the Rockwell Dual Lift-off Self­
aligned process described in chapter 2 and in reference [2-8]. There are two variations
in the structure.
Structure 3F has InGaAs cap that will help to reduce the emitter
resistance and will increase the gain. However, the added thickness and extra material
growth could increase the complexity in processing and reduce the yield. In structure
3D, 500A o f highly doped GaAs is used to perform the same function as the emitter
ohmic contact.
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52
Because o f the experimental nature o f the processing, the outcome o f these
devices had a varying degree o f success in fabrication. The DC characteristics o f these
devices will be discussed in this section.
Table 3.2 Process 3F and D Layer structure
Rockwell ML RI A,F
Rockwell ML'RI D
Process 3F
Process 3D
InGaAs Cap
n-InGaAs 1.0E19
1.0E19
InGaAs
n-InGaAs
|
to n-GaAs
Grading
Emitter cap
GaAs (Si) 5.0E18
Emitter
Base
Collector
Sub-collector
InGaP (Si)
GaAs (C)
GaAs (Si)
InGaP (Si)
InGaP (Si)
InGaP (Si)
GaAs (Si)
3.0E17
4.0E19
3.0E16
5.0E17
3.0E16
5.0E18
5.0E18
none
none
400A
400A
3000A
500A
600A
3 00A
100A
3600A
500 A
6000A
GaAs (Si)
GaAs (Si)
InGaP (Si)
GaAs (C)
GaAs (Si)
InGaP (Si)
InGaP (Si)
InGaP (Si)
GaAs (Si)
1.0E19
5.0E18
3.0E17
4.0E19
3.0E16
5.0E17
3.0E16
5.0E18
5.0E18
500A
2500A
600A
600A
300A
100A
3600A
500A
7000A
The DC IV curves o f the Process 3 Rockwell DHBTs vary depending on the
wafer. Typical Gummel plot and common current-voltage (TV) plot emitter for a 40pm
device o f wafer D are shown in figures 3.17 and 3.18. The Gummel plot and common
emitter IV plot for wafer F are shown in figures 3.19 and 3.20.
From these plots, it can be observed that wafer F has higher current gain (80).
There are many factors that can cause variation in gain. One o f the factors is the emitter
resistance. Emitter resistance can cause the current level to level out even as higher V be
is applied.
Since the current gain is usually a function o f the current density, peak
current gain could not be demonstrated if the current density has been limited by the
emitter resistance. One can observe that the wafer D has higher resistance than wafer F.
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53
The difference in emitter resistance is due to the addition o f the InGaAs cap. There
might also be some improvement needed for wafer D emitter contact processing.
Another possible culprit for the reduction in gain in wafer D is the thickness of
the emitter. Since wafer D has a thinner emitter cap, the undercutting will be less for
during the self-aligned base contact process. This allows the base contact to be closer to
the emitter and allows greater base current to develop (reducing the current gain).
1.00E-02
1.00E-03 - 1.00E-04 - 1.00E-05 - „
1.00E-06 -1.00E-07 -1.00E-08 • 1.00E-09 —
1.00E-10 -1.00E-11
0.5
0.7
0.9
1 .1
1.3
1.5
V be[V ]
3.7 Gummel Plot for the Process 3D DHBT (Emitter Area=40jxm)
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54
3.006-03
2.506-03 - -
2.006-03 ■-
^
1.50E-03 - -
1.006-03 - -
5.006-04 - -
0
1
3
2
4
5
VceM
3.8 Common Emitter IV Plot o f the Process 3D DHBT (Emitter Area=40(im)
1 .0 0 E -0 2
1 .0 0 E -0 3 - 1 .0 0 E -0 4 - 1 .0 0 E -0 5
■-7 1 .0 0 E -0 6 - —
1 .0 0 E - 0 7 - 1 .0 0 E -0 8
-
1 .0 0 E -0 9 - 1 .0 0 E -1 0 - 1.00E-11
0 .5
0 .7
0 .9
1.1
1.3
1.5
V B E [V]
3.9 Gummel Plot for Process 3F DHBT (Emitter Area=40p.m)
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55
1.80E-G2
1.606-02 - 1.406-02 - 1.206-02 - •
5* 1.006-02 • •
6.006-03 • 4.006-03 • -
0.006+00
0
1
3
2
4
5
VceM
3.10 Common emitter IV Plot for Process 3F DHBT (Emitter Area=40fim)
We concentrated our measurement effort on wafer F.
There are several
characteristics from wafer F that are unlike those o f conventional DHBTs. First o f all,
in the common emitter IV plot, one can observe that the offset voltage V ce,sat is higher
for wafer F than wafer D. One possible explanation is that as the base contact become
over-annealed, the base contact metal would spike through the base layer, forming
Schottky-like contacts. Thus, the base collector contact may form parallel Schottky
diode clamp, similar to that o f the Schottky TTL family. In that case, the saturation
voltage will be higher because the Schottky diode tum-on voltage is around 0.8 V .
3.1.3 AEc Current Blocking Effect
From the aforementioned results, the DHBT has satisfied the goal o f obtaining
adequate current gain, low offset voltage, and high breakdown. However, this transistor
characteristics have a larger than usual collector resistance for the collector region
associated with the 40p.m2.
This can be observed in figure 3.3 with the slow rise of
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56
collector current in the saturation region.
Despite a low saturation voltage at low
collector current, the knee voltage o f this transistor is high at high collector current Ic,
which makes this device less ideal for power amplifier designs.
Rather than a larger collector resistance, the cause for this non-ideal behavior is
due to the presence o f the conduction band barrier AEc- The actual sheet resistance o f
the sub-collector region is 17 Ohm/sq. which is standard to HBT technologies. It was
mentioned in chapter 2 that the conduction band discontinuity can block collector
current as the carriers are swept across the collector space charge region (SCR). This is
especially true as the current density increases. As the current density in the collector
increases, the carriers (electrons) which enter the space charge region (which is
positively charged) will reduce the net charge o f the collector SCR. Since the electrons
can travel at a maximum speed o f V
Sa t
(saturation velocity), they will be present in the
SCR for a finite amount o f time. Then the effective charge of the SCR will be reduced
by Jc/V s a t - This effect is pictured schematically in figure 3.11 and the effect o f current
injection on the charge density in BC-SCR is shown in figure 3.12. Because the electric
field at the base edge o f the BC-SCR is determined by the charges in the SCR region,
the difference in potential between base and collector will reduce, allowing the
discontinuity to disrupt the collector current flow even more. This effect is shown by
the energy band diagrams in figure 3.13.
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57
, ^ Space Charged
| ^ ~ region
# -J c i »
/TV
/TV
v j/
v j/
/T v
/TV
/T v r /T V
Q7
/TV
sj7
E
B
/TV
/TV
vJ7
vJ7 \J 7
vJ7
/TV
/TV
vJ7
/TV
v j/
\J 7
/TV
sJ7
/T v
/TV
vJ7
/TV
\J 7
^7
/TV
/TV
v j7
C
\J 7
sub-Coliector
Figure 3.11 The reduction o f charge density in collector SCR due to injected current
ch arg e
effective charge
decrease by Jc/(q
Vs a t )
distance from the BC junction
Depletion region
increases and CgC
decreases
Figure 3.12 Charge in the base-collector SCR under current injection
portions o f collector current
becam e blocked a s current
density increase
increasing current density
(decreased electric field in the SCR)
InGaP
Figure 3.13 Increased carrier blocking due to increased collector current density
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58
The end result can be seen in the Gummel plot o f a 40 pm2 emitter area DHBT
(figure 3.14) as an abrupt saturation in current density while the base-emitter voltage
continues to increase.
The effect can also be seen in the saturation region o f the
common emitter IV plot (figure 3.15) of the same transistor. For these devices this
current density is around 2.2xl04A/cm2 when the base collector bias is fixed at zero
volt. The increase in base collector bias can increase the current density at which the
carrier blocking effect occurs, because the electrostatic potential for higher base
collector bias is larger and thus allowing more charges to enter the SCR before the AEc
protrude higher than the base conduction band energy.
1.00E +00
1.00E-01
1.00E -02
Current B lo c k in g --------------------Effect
y'
-
1.00E -03 1 .OOE-04 S .
1.00E -05 -
1k _
1.00E -06 -
3
1.00E -07 1.00E -08 1.00E -09 1.00E -10 1.00E -11 1.00E -12 0.5
---- i-----1-----1-----i-----1----- 1-----i-----i----0.6
0.7
0.8
0.9
1
1.1
1 .2
1.3
1.4
1.5
VBE [V]
Figure 3.14 Gummel plot showing the AEc current blocking effect (40 pm 2 NDI
DHBT, Current blocking at 2.2 x 104 A/cm2)
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59
2 .0 0 E -0 2
1.80E -02
1.60E -02
1 .40E -02
1.20E -02
<
1.00E -02
8.00E -03
6.00E -03
4 .0 0 E -0 3
2 .0 0 E -0 3
O.OOE+OO
-2.0 0 E -0 3
0
1
2
3
4
5
VCE[V]
Figure 3.15 IV plot showing the AEc current blocking effect (40 pm 2 NDI DHBT, Ib
Step = 50 pA)
A maximum current density o f 2.2 x 104A/cm2, the Process 2 DHBT is sufficient
to satisfy most o f the power amplifier applications. Most commercially available HBT
power amplifiers for cellular phone handsets operates below this current density for
thermal reason. However, the current density at which this undesirable carrier blocking
effect occurs is unexpectedly lower than our original design. The design procedure in
chapter 2 has been shown to be effective in reported literature.[3-3][3-4]
Some
investigation in order to understand the phenomenon and improve future designs will be
discussed in the following paragraphs.
Because o f previous successes in fabricating DHBTs without carrier blocking
effects, we suspected the problem to be deviations from nominal design that occurred
during the material growth. One possible reason can be that this structure lacks the
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60
pulse doping that was designed to pull the conduction band edge down. To verify this
hypothesis, some calculations were done to show the effect o f the pulse doping.
The calculation uses electrostatic model and abrupt junction approximation. The
electric field is calculated from the integration o f the charge in the SCR. The potential
is calculated in turn from the integration o f the electric field. The conduction band
differs from the potential by an abrupt energy increase at the interface where the
material is changed from GaAs to InGaP. The effect o f injected current is modeled by
subtracting injected charge from the collector doping.
That is, in the space charge
region, the charge density is the doping, qNc, less the injected electron charge,
J c/ V s a t -
The build-in potential is calculated to be V bi = 1.55. The integral o f the electric
field (which is an integral o f the charge) across the depletion region must equal to
V bi+V bc- This criterion sets the limits on the depletion region.
shape o f the conduction band can be obtained.
Thus, the over all
Figure 3.17 shows the simulated
conduction band for the current blocking effect.
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61
0.1
200
100
-
0.1
--
-
0.2
--
300
!> -0.3 --
a -0-4 -Potential
-0.5 --
Q. -0.6 --0.7 --
0.8
- -
-0.9 --
Distance [nm]
Figure 3.16 Simulated potential and conduction band diagram o f the base-co Hector
junction
We assume that the carriers will be blocked if the discontinuity of the
conduction band is higher than the base conduction band edge. Conduction band with
and without pulse doping was calculated. The result is shown in figure 3.17.
Maximum current density without carrier blocking as a function o f
V ce
calculated for the case o f base-collector junction without the pulse doping.
can be
The
maximum current can be measured from the Gummel Plots by fixing the Vce to be
constants. They are the onset o f the current blocking effect. This theoretical result is
compared to measured results in figure 3.18.
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62
"Withoutpulse doping
■With puls e doping
o
O
-0.2S
■0.3
a
SO
iao
ISO
D epth [nm]
Figure 3.17 Simulated conduction band diagram with and without pulse doping
45.00
40.00 • -
max calculated current
35.00 - -
max measured current
30.00 - 5* 25.00 • -
9
20.00
- -
15.00 ■10.00
-►
5.00 -0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
VCE [V]
Figure 3.18 Simulated and Measured Current Density for a 20 pm2 Process 2
DHBT
The prediction from this theoretical calculation was able to predict the non-ideal
behavior o f the NDI DHBTs assuming the doping pulse was absent. This can be a
confirmation o f a problem in the material not grown to the specified doping profile.
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63
Capacitance versus voltage (CV) measurement o f a large area base collector diode was
performed in attempt to verify the error in the material. The data o f this measurement is
shown in figure 3.15, and the doping calculated from this CV profile is shown in 3.16.
The data is noisy and does not reveal the details o f the doping profile. However, it does
suggest fairly low doping.
Further investigation with doping
profiler must be
performed to conclude the mistake in material.
B ase-C ollector C ap acitan ce
171 pm2
2.506-11
2.006-11
1.006-11
5.006-12 -
•1
0
0.5
1
VCB [V]
Figure 3.19 CV Measurement o f the Process 2 BC junction
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64
ttf l---4E+17
3E »17
3E »17
If
a.
o
a
1------
Ill
y
1000
2000
,
3000
D e p th
4000
45000
..'
6000
[A]
Figure 3.20 Doping profile calculated from the CV measurements
3.2 S-Parameter Measurement
Dynamic performance o f the transistors is an important part o f the device
characterization. It is important for circuit designers to have accurate AC models in
order to properly determine the frequency response o f the circuits—such as cutoff
frequency or the rise time, etc.. For our microwave devices, AC data were obtained
using HP 8510B network analyzer. The devices were probed on wafer using GGB
Picoprobe (ground-signal-ground configuration) on an Alessi probe station. The probes
are constructed with 50 Ohm air coplanar waveguides, which can carry the microwave
signal from network analyzers to the device under test. The transistors are typically
connected to the probe pad in common emitter mode. The probe pad configuration is
shown in figure 3.21.
Two main figures o f merit (FOM) are the unity current gain frequency (/) and
the maximum frequency o f oscillation (/max). Unity gain frequency,/, is defined as the
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65
frequency at which the short circuit current gain is equal to one.
This figure is
important for the digital circuitry where the outputs are usually driving the input
capacitance o f the next logic gate circuit. The maximum frequency o f oscillation is
defined as the frequency where the maximum available gain o f a two port device is
equal to one. This FOM is used to determine the frequency response o f the power gain
under ideal matched condition and therefore is important for power amplifiers.
In
HBTs, the f is equal to 1/27tT ec and f max is equal to 1/(87cR bC bc)°'5- The details o f the
derivation, as well as other related figures o f merit, are given in appendix A.
O
Figure 3.21 High frequency measurement configuration
S (scattering) parameters are obtained from the network analyzer.
After
applying de-embedding techniques, the s-parameters can be converted to z- (impedance)
parameters, y- (admittance) parameters, or h- (hybrid, combination o f z and y)
parameters. These parameters can be used to calculate the current gain and power gain
as functions o f frequency as well as help determining a nonlinear model described in
the next section. In particular,^ is extrapolated from the small signal current gain (h21)
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66
and ./max is extrapolated from the maximum available gain / maximum stable gain
(MSG/MAG) [3-5]. Plots o f h21 and MSG/MAG for the NDI DHBT (40 pm2) and for
the Rockwell DHBTs (60 pm2) are shown in figure 3.21 and 3.22.
30
20
->s
10
0
1
10
F r e q u e n c y (G H z )
Figure 3.21 High frequency behavior o f a NDI 40pm 2 DHBT
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100
67
3.50E+01
3.00E +01
2.50E +01
MAG/MSG
2.00E +01
O
Q
■a
1.50E+01
1.00E+01
5.00E + 00
O.OOE+OO
1.00E +09
1.00E+11
1.00E+10
frequency [Hz]
Figure 3.22 High frequency behavior o f Rockwell 60pm2 (Wafer F)
The y- and z- parameters are also used frequently in extraction o f AC models for
transistors. In our work, a Gummel-Poon large signal model was extracted for design
and verification o f the application circuits. The details o f the extraction techniques are
discussed in a later section o f this chapter.
The values o f f
t
and
f m^
are functions of the bias.
This is because many
capacitance components in the HBTs are either depletion or diffusion capacitaces (such
as the base-collector capacitance,
C bc
and base-emitter capacitance
with biases. The discussion on the dependence of C bc and
C be
C be )
which change
on bias and this effect
on f t andTmax will be explored in chapter 5 and also can be found in appendix A.
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68
80
70
N
X
1.00E-02
1.00E-03
1.00E-01
Collector Current [A]
Figure 3.23 fr and fjviAX versus current (Rockwell 60pm2, W afer F)
The list for the peak/is a n d y ^ s are hsted in table 3.3
Table 3.3 High frequency performances GalnP DHBTs
Devices
Process 2
Process 3F
ft
35 GHz
70 GHz
./max
59 GHz
70 GHz
Among this results process 3F shows 70 GHz o f f t, which, to this author’s
knowledge, is the highest to date for a InGaP based DHBT. It shows the capability o f
this material system and the device structure.
3.3 DHBT Modeling
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69
Gummel-Poon models [3-6] were used to model the DHBTs to further simulate
circuits for design and circuit analysis purposes. As mentioned earlier, many o f the
device AC parameters can be directly extracted with the z- and y- parameters. Similarly
the DC parameters can be directly extracted from the DC Gummel plots.
Key parameters o f the Gummel-Poon models are as followed. The description
o f the collector current can be determined by the term IS and NF. The collector current
Ic then follows the equation Ic=IS*(EXP[VBE/(NF*VT)]-l).
For a silicon BJTs, the
base current then can be desribed by current gain beta. In the forward active regime, the
base current is determined by IS/BF and in the reverse active regime, it is determined by
IS/BR. However, in an HBT, the emitter injection efficiency, y, is very high due to the
valence band hole blocking capability.
Therefore, a widely accepted method o f
simulating this effect is to arbitrarily set the term BF to a large number and use the
recombination components o f the base current provided in the G-P model.
The
recombination components o f base current are described by ISE, NE, ISC, and NC.
One can quickly determine a DC model by fitting the measured Ic in the
Gummel plot with IS and NF, and fit lb to ISE and NE. The reverse current can be
roughly estimated since the reverse active regime is not usually used. In addition, one
applies some method o f determining terminal resistance such as RE, RB, and RC.
Finally, one can fit the high current region with IKF.
This process would usually
provide an adequate description of the DC behavior o f the HBTs in the lower power
region o f the device.
At higher power, the transistor gain suffers from self-heating
effect and there is negative slope in the IV characteristics, which is not represented by
the Gummel Poon Model.
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70
The AC behavior is mostly set by the capacitance components. There are two
major depletion capacitance components— C
the s-parameter measurement data.
be
and
C bc-
In particular,
C bc
They can be extracted from
can be extracted with the
following formulation[3-7]:
C BC
= — Im
(3-1)
co
C be
can be extracted from the low current slope o f the
After
C bc
and
C be
l/2 7 if r
versus 1/Jc graphs[3-8].
versus bias has been extracted, the remaining terms that
describes the bias dependence o f the depletion capacitance components— MJC, VJC,
MJE, and VJE— can be found by curve fitting to the Gummel Poon equations.
The diffusion capacitance o f the two junctions can be describe by the terms TF
and TR. TF can be extracted by the y-intercept o f the graph
l/(2 7 ifr )
versus 1/Jc- TR
can be extracted using time domain charge storage measurement.
The extracted parameters for the 60pm 2 are shown in the following table:
Table 3.4 Model Parameters of a 60pm2 DHBT
IS
1.4e-24
BR
le5
RE
5
MJE
0.5
VJC
1.4
BF
le5
NR
1.025
RC
5
TF
1.4e-12
MJC
0.5
NF
1.025
VAR
1000
XTB
-3
XTF
3
XCJC
0.85
VAF
le5
IKR
1
EG
1.4
ITF
0.7
TR
3.5e-10
KF
0.07
ISC
8.9e-15
XTI
3
VTF
50
CJS
0
ISE
1.9e-21
NC
1.616
CJE
2.2e-13
PTF
50
NE
1.32
RB
14
VJE
1.4
CJC
6e-14
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71
References
3-1.
H P 4 1 4 2 P a r a m e t e r A n a ly z e r U s e r 's M a n u a l
3-2. Internal data, Global Communication Semiconductors.
3-3 . J.I. Song, C. Caneau, W.P. Hong, and K.B. Chough, "Characterisation of GalnP/GaAs
Double Heterojunction Bipolar Transistors with different collector Designs," E le c tr o n ic s
L e tte r s , Vol. 29, No. 21, pp. 1881-1883, 1993
3-4. S.L. Fu, N o v e l A p p lic a tio n s o f G a ln P to G a A s B a s e d H e te r o ju n c tio n
(H B T s ), PhJD Thesis, UCSD, pp. 30, 1996
3-5. G. Gonzales,
3-6.
T r a n s is to r M ic r o w a v e A m p lifie r s ,
B i p o l a r T r a n s is to r s
McGraw?
S e m ic o n d u c to r D e v i c e M o d e lin g w ith S P I C E .
3-7. D. R. Pelhlke and D. Pavilidis, “Evaluation of the factors determining HBT equivalent
circuit from measured S-parameters,” I E E E T r a n s . M ic r o w a v e T h e o r y a n d T e c h n iq u e s ,
vol. 40, pp. 2367-2373, Dec. 1992.
3-8. Charles Chang, N o v e l L o w
P o w e r H B T T e c h n o lo g y ,
Ph.D. thesis, UCSD, 1995, p. 100.
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Chapter 4. Heatsinking Techniques
4.1 Introduction
From the discussion o f the self-heating and thermal run-away in chapter 3., one
can conclude the importance o f minimizing the junction temperature rise an<3 the
variation in temperature among sections o f a large transistor. One approach is to
properly space out the emitter fingers to avoid overheating. Another approach is t o use
the emitter ballasting resistors as negative feedback to reduce gain non-uniformnity.
However, if the spacing is too large, there would be an increase o f inductance hn the
transistor interconnects and the associated signal phase delay would decrease _gain.
Larger area can also increase the chance o f non-uniformity.
Furthermore, larg e
transistor area would be demand valuable real-estate, reducing manufacturers' p ro fit
margin.
The approach using ballasting resistor will reduce the transistor igain.
Therefore, in addition to these commonly used methods, other approaches to red u ce the
self-heating effects must be investigated.
4.1.1 Flip-chip heatsinks
One approach used in this study to reduce the thermal effects is the flip-chip
heatsinking structure.
Other methods mentioned in the literature were to
add
heatsinking structures, such as bath tub shaped metalization[4-l], to the bottom o f the
substrates which the transistor is fabricated on. However, since most o f the therm al
energy generated by the transistor is at the collector o f the HBTs (or the top surface o f
the substrate), the heat would have to be transferred across a rather thick substrate t o the
72
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73
heatsinks, making these approaches less effective.
Therefore, it is natural to build
heatsinking structures nearby the transistors itself—on top o f the transistors. In some
transistors technologies, the thick interconnect metal layers can sometimes be used to
form heatsinks[4-2]. However, the finite thickness o f the interconnect metals and the
protection layers above the substrate might limit surface area for heat exchange and
contribute to thermal resistance.
We devised another approach, which is to use the backside o f the substrates as
the interconnect layer, allowing the usual connectivity, leaving the front side for heat
exchange. A similar approach has been recently reported by other researchers [4-3].
Our approach uses metal two (top metal) as the heatsink which can be attached to the
metal package or brass fixture, making the entire fixture to be the body for heat
dissipation. There is the possible draw back of limiting the transistor to be tied to the
ground with one or more o f its terminals; however, in RF circuits, especially for power
amplifier applications, most to the transistors used will be either in the common emitter
or the common base form.
So that the limitation would not severely degrade the
versatility o f this technology.
4.1.2 Heatsink Design
The HBT used for this project is a conventional AlGaAs/GaAs HBT fabricated
at Rockwell Science Center. Device layout as seen from the top is shown in figure 4.1
below. This device is connected with the first metal to nearby pads, which then can be
linked to the backside metal with through substrate vias.
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74
em itter
em itter
collector
M1 form s
c o n ta c t
pads
\,vsssss»vss.
ZSi,YS~V.V~‘
M2
form s
h e a tsin k
on to p o f
e m itter
via to
th e
b a c k sid e
base
Figure 4.1 Transistor topology for backside inter-connection
On top o f emitter, large metal 2 area were laid down to act as adhesive pad to
external heatsink structures which can effectively transfer out the heat generated in the
device. This pad can also act as a thermal shunt structure, allowing emitter fingers to
heat up evenly; thus reducing the current-hogging effect. The cross-sectional view of
the intended heatsink configuration is shown in figure 4.2.
Backside B ase C ontact
Backside Via
Collector
Sub-collector
S.I. GaAs Substraj
Metall
Base
B rass Heatsink Fixture
o N N\ > \ x x \ x
Emitter
Metal2
Indium solder
Figure 4.2 Schematic Diagram o f the flip-chip heatsinking scheme
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75
The junction temperature can be simulated with 3D Poisson solvers which can
solve the heat transfer equation can determine the junction temperature to determine the
necessary spacing between the emitter fingers. The heat transfer equation is
d 2T d~T d 2T 1
dT
r-H
—H - = ----------------------------dx
dy~ dz~ a dt
(4.1)
and in steady state (under CW condition) this equation becomes
d 2T d 2T d 2T .
— -+ — r +—r =0
dx2
d y 2 dz2
,.
(4.2)
The emitter areas behave as power sources from which the heat radiate outwards. The
simulation can aid designing the optimum finger spacing while minimizing valuable
transistor real-estate. The comparison between the simulated results and the measured
result is shown in section 4.3.
4.2 Device Structure and Fabrication
The HBTs were fabricated in Rockwell Science Center using the conventional
AlGaAs/GaAs technology [4-4]. This technology is similar to the self-aligned base
contact technology described in chapter 2. The main difference is the emitter material is
AlGaAs rather than InGaP. As discussed in chapter 1, AlGaAs/GaAs HBT is a more
mature technology, although InGaP/GaAs HBT technology has been advancing rapidly.
After the fabrication o f the HBTs, the substrate is lapped down from the
backside to a thickness of 3 mil (75pm).
Reducing the thickness o f the wafer is
important for the formation of the backside via holes. The etching would be difficult if
the substrate is thick. In addition, thinning the wafers also help heat dissipation.
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76
After lapping, lithography is done on the backside, using either an infrared
backside aligner or by aligning to holes that were etched from the front side. After the
alignments, through substrate via were chemically etched, and the entire backside was
electroplated with 3 pm o f gold.
The plated gold on the backside will contact to Metal 1 (300A Ti/6000A Au) on
the front side through the via holes.
The transistor contacts are made to the base and
collector with first level metal and these Metal 1 form large pad area to be contacted
from the backside above and below the transistor. These contacts are covered with 2000
A thick SiN and 1 pm thick polyimide interlevel dielectric. Contact is made to the
emitter with second level metal (300 A Ti followed by 4 pm o f gold.) The second level
metal connected to the emitter extends across the 500 pm x 500 pm die surface and
serves as the electrical ground. The wafers were thinned to 75 pm (3 mil). Backside
(through substrate) vias were etched to form links to the front-side interconnects to base
and collector.
The transistors used in this experiment had 6 emitter fingers, each with
dimensions 2.2 pm x 10 pm (total area equals 132 pm2).
The final step is to pattern the backside metalization with a final lithography
step. The circuit then can be probed or bonded to from the backside o f the dice. A
SEM picture o f a transistor die as seen from the back side is shown in figure 4.3. The
semispherical nature o f the backside via is the result o f isotropic chemical etch. For
higher aspect ratios, anisotropic dry etch should be used. However, thick metal plating
should be used to ensure that the metal coverage for such via is continuous.
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77
Figure 4.3 SEM picture o f the backside probe pads
After dicing, the chips were bonded to a gold-plated-brass microwave fixture
using indium (97%)/silver (3%) solder (20 pm thick), with the transistors connected in
a common emitter configuration. The direct contact o f the emitter contact to the
heatsink fixture significantly reduces the thermal resistance, R*.
The backside
connection for these HBTs eliminates the need for specialized flip-chip aligners. Wire
bonding can be used to connect the transistors in hybrid circuits.
4.3 Measurement Results
Thermal resistance o f the bonded devices was measured by procedures similar to
those described by J.R. Waldrop et al [5]. With this method, Vbe at a fixed Ic was
measured versus substrate temperature, and then Vbe was measured at constant heatsink
temperature as the power dissipation in the HBT was changed by changing VbC- From
these data, the approximate junction temperature increase is estimated during the
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78
constant heatsink temperature measurement by matching the two sets o f values for VbeR* was calculated from the junction temperature rise at different powers.
In our
experiment, Rth was calculated to be 0.23 K/mW for the devices with emitter area 132
pm2. For comparison, conventional devices that were thinned down to 75 pm and goldplated on the backside were also measured. The Rth was calculated to have an average
value o f 0.64 K/mW, which is 2.7 times higher than for the flip-chip devices.
66 55 54 53 •
(0 5 2
•
© 51 ■
CD
50 -
49 48 47 4 6 -I
150
250
300
55
P o w er [mW]
65
T e m p e ra tu re
Figure 4.4 Variation in Vbe and beta versus power and temperature under constant
current
Thermal resistance can be extracted by the measurement o f Vbe versus Ic at
different temperatures. The equation used to describe the temperature o f the transistor
is as followed:
Tq = Tsub + 0 Pdiss
(4.2)
In the first measurement, the Pdiss is kept constant and Tsub is varied. This will give us
a set o f conditions o f When additional power (i.e. larger Vce) is added to the transistor,
the behavior o f Vbe under constant Ic can be used to predict the thermal resistance.
As stated previously, simulations were carried out for the temperature rise
expected with this structure [2-6].
Fig. 4.5 shows the simulated results and the
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79
experimental results, which are in close agreement.
Thermal simulations were
performed with a three-D simulator (Silvaco Atlas Thermal). And they are verified here
with measured data to validate the design process for future heatsinking designs. The
simulation results are shown below.
flip-chip
(m easured)
=— flip-chip
(simulated)
O
80
non-flip-chip
(m easured)
non-flip-chip
(simulated)
100
150
Delta P [mW]
Figure 4.5 Simulation result versus measured results
4.4 Power Measurement
To demonstrate the usefulness o f the bonded HBTs in power amplifiers, CW
power measurements at the frequency o f 9 GHz were made with external tuning. The
HBTs were biased with Vce o f 9 V and tuned for the maximum power output. An
output power as high as 25.5 dBm was obtained for the device, corresponding to a
power density as high as 2.9 mW /pm2 o f emitter area. The power-added efficiency was
found to be 30%. No ballast resistors were needed to provide thermal stability. This
power density is high compared to conventional HBT PA used in commercial cellular
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80
phone handsets. Power density in cellular phone HBT power amplifiers is limited by
thermal effects.
26
25
24
23
m
22
a
21
o
20
^
19
s'
s'
s
—
V
18
17
16
8
10
12
14
16
18
P in [ d B m ]
Figure 4.6 Power output characteristics o f the heatsinked transistor
4.5 Backside Via Modeling
It is important to accurately model the backside bias. In the past, modeling the
backside via can determine the ground inductance present at each device.
Ground
inductance affects the S21 (forward gain) o f a device. In our case, the via inductance
affects the input and output parasitic inductance and thus affects matching conditions o f
the device.
The vias can be modeled as inductors connecting to the input o f the transistors.
Individual via are characterized through the following method. The vias are connected
to a 2 port ground signal ground (GSG) probe pads (Figure 4.7). The vias are connected
to the backside ground. The plane o f reference for the network analyzer is calibrated to
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81
the tip o f the GSG probes. Therefore, the entire structure can be modeled as shown in
figure 4.8.
B ack sid e
v ias
Figure 4.7 Top view o f the view modeling structure
L1
Port 1
L2
YYY^—r^YYY^
P o rt 2
5/4*Lvia
Figure 4.8 Schematic o f the via modeling structure
Z-parameters can be obtain from the model in figure 4.8. The values for the
parameters are
•^ 1 1
— Z Ll +
Z lvU
(4.3)
(4.4)
Z
21
= —. Z
4
LVIA
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(4.5)
82
(4.6)
The 5/4 factor is referred to the fact that the main (center via) contributes the inductance
o f one via, where as the 4 other via on the ground plane o f the coplanar probe pads
contributed
V* o f the
via inductance (Figure 4.7).
Another popular method o f determining the via inductance is through one port
measurement. The probe configuration and the associated model is shown in figure 4.9.
The input pad inductance LI must be de-embedded through a separate measurement. It
is difficult to accurately determine the value o f LI because o f the inaccuracy of probing.
Therefore, it is advantageous to use the two-port method to measure the via inductance.
L1
P ort 1
vias
Figure 4.9 Measuring via inductance using one-port method
By measuring the two port s-parameter o f the modeling structure and converting
to z-parameters. The value o f the via inductance can be directly measured from the
imaginary part o f the Z 12 or Z 21. Similarly, the values of the via resistance can also be
extracted. In our case, each via adds 15pH o f inductance and 3mQ o f the resistance.
The slight amount o f resistance would not affect circuit operation.
The added inductance can be used as part o f the matching and should not
degrade the power performance o f the transistor at high frequencies. The base emitter
capacitance can also be slightly increased due to the proximity o f the base contact to the
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83
grounded heatsink structure which is directly connected to the emitter. However, this
increase is small, such that the
f
and Tmax o f these devices are not affected by the
inclusion o f the heatsink. The added parasitic capacitance between the base contacts
and ground, as well as between the collector contact and ground, estimated to be 0.03
pF which is small compared with the overall input diffusion capacitance o f 0.24 pF at a
current density o f 6.0x 104 A/cm2.
The values o f ft and fmax were found to be 55 GHz and 75 GHz, respectively (at a
current density o f
6.0xl04 A/cm2 and Vce = 4 V).
The measured HBT had small
emitter inductance, which was difficult to directly extract. Thus, this inductance does
not affect the gain o f the transistor when the transistor is connected in hybrid microstrip
configuration.
4.6 Summary
A novel heatsinking geometry was demonstrated for AlGaAs/GaAs HBTs which
leads to thermal resistance lower by a factor o f approximately 2.2 than the conventional
structure. The structure leads to a slight increase in parasitic capacitance on input and
output, and decreased ground inductance.
It was shown to be consistent with high
microwave gain for large HBTs at 9 GHz. An output power density o f 2.9 mW/um2 o f
emitter area was demonstrated.
This technology can be applied to high power
applications.
Although the heatsink method has been shown to be successful as part o f the this
work, it was not implemented in the m ain DHBT work to reduce the complication. This
method will be implemented in the future w ith GalnP DHBTs.
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84
Reference
4-1. PR Bestwick, I. Davies, K.C. Vanner, “N o v e l I n te g r a l H e a t s i n k S tr u c tu r e s f o r
M M I C S f Electronics Letters, Jul 5, 1990, V26, N14, pp. 1050-1051
P ow er
4-2. H. Sato, M. Miyauchi, K. Sakiuno, . Akagi, M. Hasegawa, J.K. Twynam, K. Yamamura,
and T. Tomita, “Bump heat sink technology—A novel assembly technology suitable for
power HBTs,” IEEE GaAs IC Symposium, 1993, pp. 337-340.
4-3. D. Hill, A. Khatibzadeh, W. Liu, T. Kim, and P. Ikalainen, “HBT with reduced thermal
impedance,” IEEE Microwave and Guided Wave Letters, 1995, Vol. 5, no. 11, pp. 373375
4-4. M.C. Ho, R.A. Johnson, C.E. Chang, W.J. Ho, D.R. Pelke, P J . Zampardi, ME. Chang,
and P.M. Asbeck, “Base-collector capacitance reduction of AlGaAs/GaAs heterojunction
bipolar transistors by deep ion implantation,” IEEE Electron Device Letters, 1995, Vol.
16. Pp.512-514.
4-5. J.R. Waldrop, K.C. Wang, and P.M. Asbeck, “Determination o f Junction Temperature in
AlGaAs/GaAs Heterojunction Bipolar Transistors by Electrical Measurement,” I E E E
T r a n s a c tio n o f E le c tr o n D e v ic e s , vol. 39, pp. 1248-1250, 1992
4-6. Atlas User’s Manual—Device simulation software, Silvaco International, 1995
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 5. Saturation Charge Storage Measurements
Saturation charge storage effects can degrade bipolar transistor performance for
both analog and digital applications.
The saturation phenomenon occurs when the
collector voltage falls below the base voltage during circuit operation, in circumstances
where there is large base drive and large voltage drop across collector and load
resistance. One can expect this mode o f circuit operation to occur in power switching
operation, such as in a switching power supply, or in a digital circuit such as TTL logic
circuitry. If the transistor is used as a switch, then the transistor saturates when it is
on .
Utilization o f switching transistors is not common in the RF circuits, because the
nonlinear behavior o f switches can degrade linear communication signals.
Another
reason for not considering switching architecture for RF circuits is the lack o f high
speed switching transistors[5-l].
However, there exist several classes o f amplifiers
(Class D, E, F, and S) which can achieve very high power added efficiency (PAE).[52][5-3] In the quest to prolong talk time for the mobile units, designers are beginning to
pay more attention to these switching amplifiers.[5-4]
control
voltage
I
load
load
Figure 5.1 Using a BJT or HBT as a switch
85
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+
86
Ideally, the switching amplifier use a simple control voltage to turn the main
switching transistor fully on or fully off. When all components are ideal, the switch
would not dissipate any power and therefore all the power is transferred to the load,
establishing 100% efficiency. A BJT or HBT can be used to function as a switch by
using the collector and emitter as the two terminals o f the switch while using the base as
the controlling terminal.
Figure 5.1 shows a typical configuration for a BJT in a
switching application.
The switching behaviors o f HBTs are not well understood. Before circuit and
system designers begin to apply switching techniques to microwave amplifiers, further
characterization must be carried out. This chapter will show methods o f measuring
charge storage time. Both the InGaP/GaAs SHBTs and DHBTs will be measured to
show that DHBTs can reduce the charge storage time and therefore are suitable for high
speed switching applications.
5.1 Charge Storage Effects
When a bipolar transistor is used as a switch, the two main mode o f operation
for the device is either "on" or "off'. During the "on" operation, the base terminal is
driven with a large drive voltage, allowing as much collector current to flow through the
device as the external circuit allows. The collector emitter voltage V ce (the voltage
across the switch) drops to a minimum, allowing the possibility for the base voltage to
become higher than the collector on voltage. As the base-collector junction becomes
forward biased, holes are injected from the p (base) to the n (collector) region and
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87
electrons are injected from the n to the p region. An excess o f minority carriers become
stored in the neutral regions o f the collector and base, for the holes and electron
respectively. Figure 5.2 shows the energy band diagram o f the bipolar transistor in the
saturation region.
During the "off" operation, the base voltage is dropped below the turn on voltage
o f the transistors. The transistor enters the cutoff regime, and the collector current drops
to practically zero. (The current density in this state can be as low as l*10"9A/cm2). As
the transistor changes from the on state (saturation regime) to the o ff state (cutoff
regime), the minority carriers stored in the base and collector during the on operation
have to be displaced before the state can change. Figure 5.3 shows schematicallly the
minority carrier concentration as a function o f time during this transition.
A major
concern in electronic circuits is the speed o f the transition. For bipolar transistors, this
switching speed is limited by the time it takes for the injected minority carriers to be
removed from the neutral base and collector regions via the reverse current and
recombination.
Electron flow (JE)
hole injection into collector
(Charge storage effect)
Figure 5.2 BJT band diagram showing the effect o f reduced B-C potential
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88
m inority c a rrier level
minority earners
decrease with
n
region
(emitter)
P
region
(base)
n
region
(collector)
Figure 5.3 M inority carrier level during the transition from saturation to forward active
A common method to prevent charge storage is to connect a Schottky diode
across the base-collector junction.[5-5] The Schottky diode has a lower tum-on voltage
than the base collector junction diode and does not suffer from charge storage effect.
This diode will turn on before the base-collector diode turns on, preventing charge
storage in the base collector junction. This approach is very commonly used in the TTL
logic circuits. However, the addition o f an extra schottky barrier diode would increase
base collector capacitance. Clever layout and processing techniques are used to place
this diode as close to the base collector as possible. In the sihcon bipolar technology
this layout technique simply extend the base contact onto part o f the lightly doped
collector region (figure 5.4). However, this kind o f convenience is not quite available in
the layered epitaxial structure o f the HBT technologies.
Besides the unavailability of the Schottky diode in HBT technologies,
the
incorporating the Schottky diode necessitate the increase in base collector capacitance
which, as indicated in appendix A, is detrimental to the ^max o f the transistors.
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89
Furthermore, Schottky diode can reduce base collector breakdown voltage
( B V c b o )-
This makes the transistors unattractive for power applications, hi addition, Schottky
diode clamping leads to an increased value of V c e ,s a t , which is the “on” voltage o f the
transistors. The increase o f the “on” voltage can be detrimental to switching efficiency.
Finally, Schottky diodes will also increase the overall transistor area. Therefore, this
implementation, though widely used in TTL circuits, has not been used in switching
power amplifiers.
oxide
contact
Figure 5.4 Cross Section o f a Schottky Clamped Diode
In this chapter, we propose to use the property o f the heterojunction to reduce
the charge storage effect. We have investigated the saturation charge storage time o f
InGaP/GaAs DHBTs, and have shown that there is a significant reduction in the charge
storage for the DHBTs.
To demonstrate this effect, we also applied a novel
measurement method, previously not performed on HBTs.
5.2 Charge storage effects in heterojunction
When the base-collector junction o f an HBT becomes forward-biased, minority
carrier concentrations increase from their equilibrium values. This corresponds to the
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90
build-up o f excess electrons in the base o f the device, and excess holes in the quasi­
neutral collector. In general, the excess minority carrier charge in the base is much
smaller than that stored in the collector, since the base is highly doped; therefore, the
injection ratio o f holes to electrons is very high. Further more, the base region is thin;
therefore, the minority carriers do not have to travel far to be swept back into the
collector by the reverse flowing current. For simplicity, the analysis throughout the rest
o f this chapter will only consider the hole injection into the collector as the dominant
participants o f the charge storage effect. This build-up o f minority carrier charge in the
collector, or the stored charge, can prevent the junction voltage from changing rapidly
after the sudden application o f a reverse bias. This ability to hold a voltage constant
until the dissipation o f charge is similar to the behavior o f a capacitor whose voltage
charge behavior is exponential rather than linear.
Our approach to reduce the charge storage is to block the hole injection into the
lightly doped n region (collector).
This can be achieved by the application o f
heterojunction[5-6], by using a material for the collector having a bandgap larger than
that o f the base. The wide bandgap collector has the same function as the wide bandgap
emitter o f an HBT, that is, it creates a potential barrier (AEv) to prevent hole injection.
The design regarding the choice o f the material system has been explained in chapter 2.
Because o f the barrier in the valence band, the hole injection will be reduced drastically.
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91
E lectro n flow (Jg)
oo•
i
hole
injection
blocked
Emitter
Collector
Base
Figure 5.5 Bandgap diagram o f a DHBT
The hole concentration at the collector edge o f the B-C depletion region can be
expressed as
Pn
=
exP
r qV ^
(5-1)
nK T j
where V is the potential difference between the quasi-fermi level for the p type and the
n-type regions. This voltage is equal to the applied junction voltage. The quantity pno is
the equilibrium hole density in the collector.
concentration n; o f the collector and
P no
is related to the intrinsic carrier
its doping level
nc
through pno^i2/ ^ . With the
use o f GalnP in the collector in place o f GaAs, (with a bandgap greater by
AEg=0.45eV), the value o f n,- is lower, which in turn reduces the value o f pn by a factor
o f exp(-AEg/kT). The expression for the charge injection then becomes the following
qV
Pn
~
PnO{CaInP)
eXP (— ) =
q V
PnO(GaAs)
eXp(
AE
) eXP(_ ~ kT ~ ^
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(5 2)
92
From the above expression, one can see that the minority carrier injection into the
o
GalnP collector is thus reduced by a factor o f exp(-AEo/kT) which equals to 3x10' .
5.3 Experimental Methods and Results
The following sections discuss the experiment that was carried out to examine
the reduction in minority carrier injection.
5.3.1 Devices Structures
GalnP DHBTs similar to the ones described in the previous chapters were used
to under go the large signal tests. These transistors were fabricated by Y.M. Hsin at
UCSD. Their layer structure is nearly identical to those described in chapter 2 o f this
thesis. SHBTs were also used for comparison purposes to demonstrate the effect o f
charge storage.
Figure 5.6 shows the layer structure of the transistor used for this
experiment.
GaAs(Si)
1200A
5x 101 * cm -3
InGaP(Si)
300A
5x101* cm*3
InGaP(Si)
600A
GaAs(C)
SOOA
G a A s ( S i ) 200A
GaAs(Si)
1200A
InG aP(SI)
5 x 1 0 1 * c m -3
300A
5 x 1 0 1 * c m -3
4 .5 x 1 0 1 7 cm*3
InGaP(Si)
60 0 A
4 .5 x 1 0 1 7 c m -3
4 x 1 0 1 * cm -3
GaAs(C)
sooA
4 x 1 0 1 * c m -3
G a A s ( S i ) 3000A
3 x 1 0 1 * c m -3
G aAs(Si)
3500A
3 x 1 0 1 7 c m -3
G aAs(Si)
50 0 A
5 x 1 0 1 * c m -3
undoped
InG aP(Si)
200A
5x10 17 c m -3
InG aP(Si)
4000A
3x 101 * c m -j
InG aP(Si)
500A
5x101* cm -3
GaAs(Si)
500A
5x101* c m -3
G a l n P D H BT S t r u c t u r e
G a l n P HBT S t r u c t u r e
Figure 5.6 DHBT and SHBT structures used for charge storage effect demonstration
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93
The HBTs and DHBTs were fabricated with MOCVD grown material from
Kopin Corporation. For the purpose of reducing charge storage, the wide bandgap o f
the DHBT provides the desired blocking o f the hole injection into neutral collector. The
collector is designed such that the conduction band is pulled down by the undoped
GaAs setback layer and the heavily doped InGaP layer, thereby minimizing the potential
barrier associated with the conduction band discontinuity between GalnP and GaAs [57]. The use o f the GalnP collector also provides for higher breakdown voltage, because
o f its lower impact ionization coefficients at a given electric field [5-8]. The details o f
the design and fabrication can be found in chapter 2.
Devices used for this study had emitter dimensions of 5 x 12 pm2 and basecollector junction dimensions o f 15 x 22 pm2.
0.016
A e: 75 x 75 pm2
0.014 ■
0.012
_
<
0.010 ■/
'■£ 0.008 •1
~~ 0.006
0.004
lB: 2 5 |iA /step
0.002
0.000
0
2
4
6
8
10
12
14
16
Vc e W
Figure 5.7 The common emitter IV curves o f the device under test
The devices made exhibit DC common emitter curves as shown in figure 5.6.
The IV curves illustrate low offset voltages for the DHBTs used to reduce the B-C
conduction band barrier, which indicate that the technique, which is described in detail
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94
in chapter 4, was effective.
The high breakdown o f these devices once again
demonstrated the inherent advantage o f this material system. These devices exhibit/t’s
and Umax's values o f 25 and 25 GHz, respectively. This means that these devices have
small parasitic capacitances and inductances, making large signal analysis more
accurate.
5.3.2 T est Setups
The most direct method for measuring the switching time o f a BJT is to connect
the transistor as a switch with a resistive load, and observe the output waveform for the
necessary switching behavior.
This test is frequently illustrated in semiconductor
textbooks. [5-9] [5-10] The setup involves driving the transistor in the common base
format w ith a large current pulse and observing the output voltage developed across the
load resistance.
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95
C
E
(a)
vcc
(b)
E
c
(c)
Figure 5.8 (a) Switching circuit (b) input emitter current pulse (c) output collector
waveform with delay from charge storage effect
However, this approach is unavailable for high frequency characterization due to
the limitation on the instruments.
There exist several models o f high frequency
oscilloscopes that can capture events with picosecond resolution. However, the current
pulses generators are not as widely available. Among the most promising is Picosecond
Pulse Lab’s model 4015B TDR Amplifier, which can be used in conjunction with the
HP54120B high speed digital oscilloscope.
For our devices, we device a different method to demonstrate the charge storage
effect in base collector junctions.
This method is sometimes referred to as the
Krakauer’s method and has previously used to characterize high speed switching
diodes.[5-l 1] Similar method was applied to HBTs in this work for the first time. This
approach consists o f a time-domain measurement o f a diode’s transient response to a
large signal sinusoidal voltage input.
These sources are widely available.
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By
96
appropriate fitting o f the observed transients, the charge storage tim e o f the diode may
be obtained. W ith subsequent modeling (for example, within SPICE) the behavior of
the transistor can be obtained. The complete setup o f the measurement is shown in
figure 5.9.
Biasing Voltages
Figure 5.9 Setup for characterizing charge storage effect in HBT base collector junction
The base collector diode is DC biased near the turn on voltage (Vd,on=1.3V,
Vdc=1.16V).
As the incoming sinusoidal excitation drives the base voltage in the
positive direction, the diode turns on and conducts forward current. The forward current
is a result o f the injected electrons and holes which are stored in the neutral regions of
the base and collector. As the input drops below the turn on voltage, the stored charges
keep the diode turned on and the negative going input voltage causes a reverse current
to extract the stored charges. In the absence charge storage effect, then the output signal
is a half-wave rectified sine wave, as verified for the case o f the Schottky diode.
Bias-tees were used to allow flexibility in establishing dc bias conditions. In our
data, the effect o f the output bias-tee has been de-embedded by numerical calculation
from the measured oscilloscope waveform. The details o f the de-embedding method is
discussed in the next section.
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97
5.4 M easurem ent Results
Representative results are shown in figure 5.10. One can observe a noticeable
voltage dip at conclusion o f each “on” half cycle for the SHBTs. The DHBTs do not
have such dip in the time response o f the outputs. This effect is the charge storage
effect that we are looking for. However, in order to better understand the output data,
the effect o f the bias tees had to be de-embedded first.
0.4 ■
0.3
0.2
•
2 0-1 •
a
f °'
° -0.1 -
0.2
'
-
-0.3 -0.4 2.00E-08
2.20E-08
2.40E-08
2.60E-08
2.80E -08
3.00E-08
time [s]
Figure 5.10. Measured results o f the charge storage testing
In the frequency range o f the experiment the bias Ts are were not ideal. In fact
the current through the inductor o f the output bias T (in figure 5.11) was not strictly dc,
but had a time dependence that had to be subtracted from the observed current. The de­
embedding method is as followed.
Due to the large coupling capacitance, we can
assume that the voltage at the collector (or the cathode o f the base collector diode) is
identical to the waveform observed at the sampling scope. Then we can determine the
voltage difference across the biasing inductor on the collector side (it is equal to the
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98
external DC voltage subtracting the collector voltage waveform). From this, we can
subtract out the biasing current from the current that across the resistor and we can
achieve our de-embedding. The de-embedded output o f this measurement is shown in
figure 5.12 and figure 5.13.
co llecto r
Total
OUT
so n
Itotal
Figure
5.11
I L
I collector
Current components o f the charge storage measurement
To summarize, the procedures for de-embedding the biasing T current is shown
below.
1 . V Ou t = ( I c + I l) * 5 0 Q
2.
Voltage across the biasing inductor
V l
equals to
V bias- V Coiiector=
-Vout. Furthermore,
VL=LdIiydt. Thus, inductor biasing current II can be derived from the integral of the
output voltage waveform Vl3.
Subtracting the inductor current from the output waveform current
( V Ou t / 5 0 Q )
obtain the collector current, which is a rectified sinusoidal signal (Figure
figure
5.13).
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5.12
to
and
99
120
100
80
ow
c
oa.
M
s
•40
18
20
22
24
26
28
30
time [ns]
5.12 De-embedded voltage waveform for a base-co Hector homojunction
160
140
120
100
r
so
20
•20
18
20
22
24
26
28
30
time [ns]
5.13 De-embedded voltage waveform for a base-collector heterojunction
There is significant reverse current (which manifested itself as a negative “dip”)
as observed in the rectified sinusoidal waveform for the SHBT base-collector junction
(GaAs homojunction).
In the response for the DHBT base collector (GalnP/GaAs)
heterojunction, the reverse current has significantly reduced amplitude.
This is an
indication o f the reduction in stored charge. From the integral o f the reverse current, the
magnitude o f the charge storage for the GaAs homojunction can be estimated to be at
least 20 times lower than the magnitude o f the GalnP/GaAs heterojunction. Due to the
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100
limited resolution o f the oscilloscope and parasitic elements in the setup, it is difficult to
accurately determine the charge storage time o f the DHBTs. However, it can be readily
seen that the reduction in charge storage effect is dramatic with a heterojunction. For
the SHBT BC junction, the duration of the reverse current were measured and plotted
against the magnitude o f the input sinusoidal excitation as shown in figure 5.12. The
charge storage time is approximately a constant at 550ps. The life time o f the minority
carrier in GaAs then is approximately 1.9ns from the analysis below.
5.5 Analysis
The complete analysis of the current transient waveforms obtained in HBTs is
complex.
A simplified treatment, however, can provide a semi-quantitative
understanding o f the relationship between the observed transient waveforms and the
charge storage time o f the diode, in a manner similar to the well-known derivation o f
the minority carrier response to a step excitation [5]. The minority carrier distributions
within the collector is calculated from drift-diffusion transport equations.
The
saturation charge storage time is the time needed for the minority carrier density to fall
to zero at the base collector junction.
In a classic explanation, Kingston [5-12] derived the step response o f the
p-n junction. The analysis starts out with the standard drift diffusion equations.
dt
dx~
Tp
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(5-3)
101
where p(x,t) is the minority carrier distribution in the collector. The hole storage in the
collector is assumed to be dominant because the collector is long and lightly doped.
Equation (5-3) can be re-written as
3P= £ £ ._
dT
(5-4)
p
dX~
where T = l/xp and X=x/Lp. The function p(x,t) in equation (5-4) can be solved via
Laplace transformation method.
+
(J f
pr =
I—
J S )L P
- - - -
'
^ I{X , V r )
(5 -5 )
where
l ( x , z ) = - ^ = T e u le
yjTT *
and
x2/4"2d u
(5-6)
l{ 0 ,z ) = e r f{ z )
(5 -7 )
/(x , oo) =
(5-8)
e~x
In this solution, the initial condition is assumed to be a steady state constant forward
current. At time t=0, the voltage is suddenly switched to a large negative bias voltage.
Our analysis is carried out in similar fashion with a variation o f the equation 5.3.
With sinusoidal excitation equation 5 .3 is subject to the following boundary conditions.
p —> 0
J (0 )
=
as x —» co
J0
cos (cot)
= Dp
(5 .9 )
dP
&
(5.10)
x=0
These conditions reduce equation 5.3 to equation 5.11.
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102
D P^
— p { - + je o ) =
OX'
X
0
(5.11)
Because the excitation is a repetitive sinusoidal wave, a steady state solution is used to
solve equation 5.11. An assumption is made that at the fundamental frequency, the
response to the sinusoidal excitation should take the form
p { x ,t)
= R f ^ p { x ] e J<M]
(5.12)
Although higher frequency components exist in the response (in fact, quite strongly
similar to that o f a step recovery diode), the fundamental component is sufficient for our
analysis.
A c tu al r e s p o n s e
In p u t S ig n a l
O u tp u t r e s p o n s e
fu n d a m e n ta l c o m p o n e n t
Figure 5.14 Fundamental component o f the sinusoidal response
We can further guess the solution for p(x) to be the following
p ( x ) = A e ' * + B e 1*
(5.13)
In equation 5.13, the value o f B should be zero because the function p(x) should
approach zero as x approaches infinity (defining x=0 at the base collector junction).
When the expression for p(x) is introduced to equation 5.11, we obtain
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103
D y2
(5.14)
- ( - + jc o ) = 0
The solution for y would be
y = J
1
jco
— + -—
D r
(5.15)
D
When the boundary condition in equation 5.10 is applied, the coefficient A in equation
5.13 can be solved.
-
yD A
(5.16)
= J 0
(5.17)
A = - ^ ~
yD
The final solution for the drift diffusion equation (5.3) is
P (x A ) =
1
exp
Re
jc o
-+ -
D t
D t
X + JCOt
(5.18)
D
D
For the diode response, it is important to observe the behavior o f the charges at
the junction. Therefore,
Jn' lD
D-yJ 1+
exv \ j c o t \
(5.19)
jC O T
and rationalizing this expression,
p ( Q ,t)
=R e
J
n
D (1 +
^
D
co2 t
T exP
jc o t — j —
2
tan 1cot
2 ) 4
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(5.20)
104
Equation 5.20 shows that the fundamental element o f the charge responding to a
sinusoidal excitation in a p-n junction has a delay to the current excitation.
'This
excitation takes the form
—y-^-tan-1 co x
(5.21)
This calculated response shows that the charge builds up with input current, and
then drops to the minimum as the applied voltage goes negative. It also shows the
charge density can drop below zero. However, physically the charge density can not
drop below zero. At this point the simple approximation leading to equation 5 .1 8 no
longer apply. Higher harmonic responses to the sinusoidal excitation is req u ired to
calculate the actual measured response. However, for the purpose o f simplification,, we
can view the point where the charge density drops below zero to be the point in tim e
where the diode cease to be forward biased and the current is abruptly cut off. /As a
result o f this analysis, we can define that
Ts
= — t a n 'V r )
2co
(5.22)
where Ts is the duration o f the negative recovery transient, x is the recombination tim e
o f minority carriers within the collector, and co is the angular frequency o f the sinusozidal
input signal.
This simple result embodies some approximations, including the following:
1) the current waveform is taken to be strictly sinusoidal (while in the experiment, the
device voltage is more accurately sinusoidal).
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105
2) details o f the circuit embedding o f the device are ignored, and the effect o f elements
such as B-C depletion capacitance is omitted.
3) low level injection has been assumed; similarly, the finite extent o f the collector
region, and the possibility o f built-in drift fields within are ignored.
4) the junction is taken to be effectively one-sided, and all the current (in both forward
and reverse directions) flows due to hole diffusion.
The total minority charge storage in the collector for a one-sided junction is o f
the order of Jmax'c. For a more realistic situation in which the total current flow has
contributions from hole diffusion, electron diffusion in the base, and recombination in
the space-charge region, the hole storage is given by yJmaxX, where y is a factor
describing the fraction o f the total forward current contributed by hole diffusion in the
collector.
From expression 5.22, the minority carrier lifetime can be extracted from the
width o f the dip in the sinusoidal measurement. Figure 5.15 shows the details o f the
delay in the measurement. From figure 5.15b, it can be observed that as the charge
storage delay approaches a constant at larger sinusoidal voltage. The larger time delay
with the smaller amplitude can be accounted by the parasitic base collector depletion
capacitance. The minority carrier life time extracted from this measured data (taken at
high input amplitude) is around 1.9ns, which is comparable to the reported for GaAs
lifetime in literatures.
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106
1100
10
1000
900
800
E -10
700
600
•30
500
400
-40
22
22.5
23 .5
23
24
500
600
700
800
900
1000
Input Sinusoidal Amplitude [mV]
tim e [ns]
(a)
(b)
Figure 5.15 (a) Detailed view o f the sinusoidal response waveform (b) Charge storage
time versus input sinusoidal amplitude
Another interesting observation can be made with expression 5.22, that is the
delay has a frequency dependence.
In theory the dip one observe in the sinusoidal
response should decreas.e in width with respect to the increase of the excitation
frequency. In our experiment, both 100MHz and 150MHz excitations were used. The
resulting responses are shown in figure 5.16.
The data shows the response to the
different frequencies is similar to the prediction by the theory.
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107
,-,8 0 0
0)
•v
f 750
i 700
o
\
\
——
■
*
\
1
« 650
o
w 600
T s(T heory)
T s(m e a s)
:\
Xx
X
X
X11
o
O) _ _ _
<5 550
£
° 500
40
90
140
F requency [MHz]
Figure 5.15 Measured charge storage time at different frequency
Conclusion
The saturation charge storage has been measured for HBTs and DHBTs for the
first time, using a sinusoidal excitation response method.
The results indicate
recombination times o f the order of 1.9 nsec for the HBTs with a GaAs collector, and
show that the total stored charge is dramatically less in the case o f HBTs with widebandgap collectors.
These results suggest that DHBTs will be useful devices for
operation under conditions o f transistor saturation, for example, in switching mode
power amplifiers.
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108
Reference
5-1. Nathan Sokal, "RF Power Transistor Storage Time: Theory and Measurements"
J o u r n a l o f S o lid - S ta te C ir c u its , April 1976, pp. 344-346
5-2. H. Kraus, C. Bostian, and F. Raab, S o l i d
1980
S ta te R a d io E n g in e e r in g ,
IE E E
Wiley, New York,
5-3. F. H. Raab, "Idealized Operation of the Class E Tuned Power Amplifier", IEEE
Transactions on Circuits and Systems, vol. CAS-24, No. 12, Dec. 1977, pp. 725-735
5-4. T. Sowlati, A.T. Salama, J.Sitch, G. Rabjohn, and D. Smith, “Low Voltage, High
Efficiency GaAs Class E Power Amplifiers for Wireless Transmitters,” I E E E J o u r n a l o f
S o l i d - S t a te C ir c u its , vol. 80, no. 10, October 1995, pp. 1074-1080
5-5. David Hodges and Horace Jackson, A n a ly s is a n d D e s ig n
second edition, McGraw Hill, New York, 1988, p. 247
5-6. H. Kroemer, P r o c e e d in g s
o f IE E E ,
o f D i g i t a l I n te g r a te d C ir c u its ,
70, 1982, p. 13
5-7. J.I. Song, C. Caneau, W.P. Hong, and K.B. Chough, “Characterisation of GalnP/GaAs
Double Heterojunction Bipolar Transistors with Different Collector Designs,” E le c tr o n ic s
L e tte r s , October 14, 1993, vol. 29, no. 21, pp. 1881-1883
5-8. S.L. Fu, T.P. Chin, B. Zhu, C.W. Tu, and PM. Asbeck, “Impact Ionization Coefficients in
(100) GalnP,” A p p l i e d P h y s ic s L e tte r s , June 19, 1995, vol. 66, no.25, pp.3507-3509
5-9.
S.M. Sze, P h y s ic s
o f S e m ic o n d u c to r D e v ic e s ,
2nd ed., Wiley, New York, 1981, p. 109
5-10. S.M. Sze, P h y s ic s
o f S e m ic o n d u c to r D e v ic e s ,
2nd ed., Wiley, New York, 1981, p. 179
5-11. Motorola, M o to r o l a
R F D e v ic e D a t a ,
volme IT, Rev. 3, Q4, 1988
5-12. Robert Kingston, "Switching Time in Junction Diodes and Junction Transistors,"
P r o c e e d i n g s o f th e IR E , May, 1954, pp.829-834
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 6. Amplifier Designs
In the previous chapters, we have shown that GalnP/GaAs DHBTs have
advantages over conventional HBTs. In this chapter, we will show the result o f the
GalnP/GaAs DHBT used in class AB power amplifiers similar to the ones used in
conventional mobile telephone handsets. Furthermore, with the improvement in the
transistor technology by the usage o f GalnP, the next step for the improvement in power
amplifier technology is through the investigation o f novel classes o f amplifiers.
Therefore, in addition to the conventional class AB amplifiers, we will also study the
GalnP used in switching amplifiers.
Two different types o f amplifiers will be
proposed—class D and class S. The class S amplifier proposed in this work employ a
novel bandpass delta sigma modulation to achieve both high power added efficiency and
preservation o f linearity.
6.1 Class AB Amplifiers
AlGaAs/GaAs HBT amplifiers are commonly used for telephone handsets with
CDMA modulation both in the cellular (900MHz) band and Personal Communication
System (PCS) band (1800 MHz). Most o f these amplifiers are implemented with class
AB amplifiers for linearity and efficiency. As a first check for the capability o f this
DHBT technology, we apply this DHBT technology to the PCS style power amplifiers.
There are several classes o f amplifiers commonly used in communication
systems. These are the class A, B, and AB amplifiers[6-l]. These classes o f operation
109
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110
are determined by their bias points.
An effective method o f analyzing the various
amplifier classes is through the load line analysis shown in figure 6.1. Class A is biased
such that the quiescent point (the operating point when no input signal is applied) is
exactly half way o f the m axim u m current level and half o f the output voltage. This
allows the output waveform to stay in the linear region until the entire voltage and
current range have been utilized. The ideal class B amplifier input terminal is biased
exactly at the threshold voltage o f the device, such that there would be no current output
in the absence o f input signal- The amount o f current used for biasing is related to the
input power and the output power o f the amplifier. This operation reduces the average
biasing current achieving higher power added efficiency.
c l a s s A b ia s
p oin t
Imax
s
V knee
c l a s s A B b ia s
p o in t
Vmax
c l a s s B b ia s
p oin t
Figure 6.1 Load line analysis o f the amplifier classes used in communication systems
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I ll
However, due to the linearity and power added efficiency (PAE) requirement for
today’s wireless c o m m u n ication, the most frequently used class of operation is the class
AB amplifier. Class AB is biased in-between class A and class B amplifiers. The
operating point is selected to be lower than the current level o f the class A operation.
The voltage bias is biased at the battery output. Because o f the need to reduce battery
weight, one or two Lithium ion or Nickel Mercury Hydride battery cell is preferred.
Currently, typical operating voltage for commercial CDMA and GSM handsets is
3.6volt (2 Lithium ion cells).
There are numerous studies on the linearity and efficiency o f these classes o f
transistors, hi general, class A has traditionally been used whenever high linearity is
required such as cellular base stations. The transistor is on during the entire class A
amplifying operation. This means the transistor will consume current even when there
is no RF power input. From the load line analysis, one can observe the voltage swing
ranges from V sat to Vcc- The maximum power output then would be
p
OUT ~
(K r-K ^Y
IP
LOAD
The DC power consumption is simply Vcc^uiescent- The maximum collector efficiency
with ideal transistors can be calculated to be 50%.
However, in actual amplifier
applications, the class A amplifier can only achieve up to 40% efficiency due to the
presence o f knee voltage and parasitic resistance.
Class B amplifiers are biased at the threshold voltage of the transistors. The
devices are normally o ff in the absence o f RF power input. However, any RF excitation
can cause the devices to turn on for half of the input cycles, hi other words, the DC bias
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112
level is adjusted “as needed”. Thus the power added efficiency can be higher. This
process is a nonlinear process; however, depending on the system, the nonlinearity may
be tolerated. In other words, although the output is not an exact scaled replica o f the
input signal, it often contain sufficient by low intermodulation products information
around the fundamental frequency to transmit desired data. The theoretical efficiency
limit for a class B amplifier is 78.5% [6-2][6-3].
Class AB Amplifiers are a compromise o f the two biasing classes described.
W hen the input signal level is low, class AB amplifiers behave similar to class A except
the quiescent current is reduced. When the signal level grow stronger, the bias level
will shift similar to that o f the class B amplifiers.
Bias shifting due to large signal in
the class AB operation is closely related to the biasing method.
Typically voltage
source is required at the input biasing. However, a large input signal can be rectified by
the nonlinear behavior o f the amplifying device. (In this case, the nonlinear behavior is
the tum-on characteristics.) The total input biasing voltage then increases and therefore
the bias point increases. The details o f the biasing method are discussed in the next
section.
6.1.1 Biasing M ethods
This section describes how to introduce the DC power and DC operating point to
the HBT. The selection o f the DC bias point (also known as the quiescent point) is
discussed in this section.
Voltage bias versus current bias for the transistors are
compared, and shown to yield different results in the power amplifier performance.
Some guidelines to optimize this difference are developed here as well.
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113
The simplest method o f biasing bipolar transistors is through the use o f bias tees.
Wide bandwidth bias tees may have a dc path resistance around 0.5 ohms, which at high
current (~1 A o f collector current) may cause the supply voltage to drop by around 0.5V.
This is a significant voltage drop for the current trend in handheld technology, which
frequently uses 3.6V Lithium ion battery cells. In actual handset applications, the bias
tee may be lower in bandwidth and specially tailored for the application with low
resistance.
Base
Biasi
L C ollector
Bjas
RF out
RF in
Figure 6.2 Typical biasing method
In our setup, the power supply (Hewlett Packard Model 6634B) is equipped with
a voltage sensor. The voltage at the collector may be sensed with this high impedance
voltage monitor in order to compensate the collector voltage accordingly. This enables
the transistor to be evaluated accurately.
The base bias method for a bipolar transistor is not an obvious matter. In an
FET based class B amplifier, one can readily define the threshold voltage of the
transistor from the logarithmic scale of the output voltage versus input current
characteristics. Typical current FET IV behavior in log scale is shown in figure 6.3 [64], which is the a plot o f the sub-threshold characteristics o f a PHEMT. Similar plot of
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114
the bipolar transistor is the Gummel plot, which is shown in figure 6.4. One can readily
observe that a distinct threshold voltage cannot be defined in the bipolar technology.
Therefore, an arbitrary threshold current density must be defined, below which the
transistor is considered to be off and above which the transistor is considered to be on.
1.00E+00
1.00E-01 -1.00E-02 --
SL
1.00E-03 --
C
0fc1
o3
c
<0
1.00E-04 -1.00E-05 --
k.
°
1.00E-06 -1.00E-07 -1.00E-08
-1.5
-
1.0
0.5
0.0
-0.5
1.0
Vgs
6.3. Typical FET drain current versus gate voltage characteristic
1 .0 0 E -0 2
N o distinct
1 .0 0 E -0 3 - -
threshold
voltage
1 .0 0 E -0 4 - -
Typical
Operatmj
1 .0 0 E -0 5 - -
r? 1 .0 0 E -0 6 -=
region.
1 .0 0 E -0 7 - 1 .0 0 E -0 8 - 1 .0 0 E -0 9 - 1 .0 0 E -1 0 -1.00E-11
0 .5
0 .7
0.9
1.3
1.5
VBE [V]
6.4 Typical HBT Gummel plot
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115
There is another difference in biasing between FET and bipolar technologies,
that is, bipolar transistors require base current. In other words, HBTs (similar to Si
BJTs) can be considered both as voltage controlled devices and current controlled
devices. The common emitter behavior is usually plotted in the current control mode
(figure 6.5) where the current gain tends to be linear[6-5], whereas the common emitter
behavior shown in voltage controlled mode is exponential and highly nonlinear (figure
6.6). FETs does not allow input current; therefore, is a voltage controlled device.
6.00E-03
5.00E-03
“
4.00E-03
U
3.00E-03
2.00E-03
1.00E-03
0
1
2
3
4
VCECV1
Figure 6.5 Current controlled mode HBT common emitter characteristics
4.50E-04
4.00E-04
“
3.00E-04
^
2.50E-04
ec
2 .0 0 E -0 4 ----1.50E-04
1.00E-04
5.00E-05
O.OOE+OO
0
1
2
3
4
VCE [V]
Figure 6.6 Voltage controlled mode HBT common emitter characteristics
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116
The m ain difference between voltage bias and current bias is that collector
current will increase with respect to input power when base voltage biasing scheme is
used. (See figures 6.7 and 6.8) The input RF power can cause the base emitter diode to
be turned on at the peak o f each cycle, increasing the overall collector current. If the
base is current biased, the relationship between the base current and the collector current
(DC current gain (3) must be observed due to the conservation o f charge. Therefore, if
the base is current biased, increased RF power will force the base voltage to decrease in
order to maintain constant base current and thus constant collector current.
Base biasing voltage
(Average voltage
various drive power)
Base
Voltage
small input
power
large input
power
Base biasing current
(Average current
increases with respect
to drive power)
Figure 6.7 Influences o f input power on base bias voltage and current under constant
voltage biasing
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117
B ase biasing voltage
(Average voltage
d ecreases with respect
of increasing drive
power)
Base
Voltage
small input
power
large input
power
B ase biasing current
(Average current remains
constant under various
drive power)
Figure 6.8 Influences o f input power on base bias voltage and current under constant
current biasing
With a voltage biased base, the increase o f collector current with respect to the
input RF power allows the bias to shift during normal operation. Therefore, the bias
current is automatically adjusted to the power level. This will contribute to increase
power added efficiency in a power controlled environment such as the CDMA IS-95
system in which the output power o f the telephone handset is determined by the signal
strength. However, the change in bias point can cause the transistor characteristics to
change, thus, it may increase the nonlinearity o f the amplifier. The drawback for a
voltage biased bipolar transistor amplifier is that as the collector current increases, the
optimum match point may also change. If the matching elements are fixed as in most
amplifiers, the amplifier would not be optimally matched during some part o f the
operation. This can cause the amplifier gain to change during under various input drives,
and often cause the effect such as gain expansion. This causes an increase in nonlinear
effects.
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118
On the other hand, a current biased amplifier can limit the current supplied to the
base, thus the collector current is limited as well. At higher RF power level, the output
power tends to compress, unless more bias current is supplied. Furthermore, with the
bias current fixed at the value required for high power output, the power added
efficiency will decrease at lower power level.
Therefore, purely current controlled
biasing scheme is not suitable for a class AB amplifier.
In actual application, the base can be biased between current mode and voltage
mode. One way to model the power supply is by a voltage source and a resistor (figure
6.9). If the resistor value is large, the power supply behave as a current source. If the
resistive value is small, the power supply behaves as a voltage source. A typical bias
supply may have a resistive value in the range o f around 100Q.
equiv. output
impedance
to output
load
base
bias
voltage
to input
source match
Bias T
Figure 6.9 Biasing the base with finite impedance
In all cases, the bias point can be defined by the quiescent current. Usually, the
quiescent current is set at around 10% o f the maximum operating current. Foundry
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119
provided load pull data should include both the quiescent current information and the
base biasing method.
The selection o f the biasing condition is as follows. Class AB scheme usually
bias th e transistors at a quiescent current that is around 10% to 20% o f the maximum
allowed current o f the device.
The GaAs based HBT power amplifier technology
generally restrict the current density in the emitter (which is generally the smallest
feature o f an emitter-up technology) to be below 20KA/cm2. This current limitation is
generally determined by thermal considerations. GaAs is a poor thermal conductor (K jh
= 0.44- W/Kcm) as compare to silicon which has K th around lW /Kcm.
Other
constraints to keep the current density low are the on-set o f Kirk effect and reliability
issues.
The transistor used for demonstrating the power amplifier capability in this
work has an area o f 800pm2, which allows a maximum current o f 160mA. To conserve
power consumption during small signal condition, 10% o f the maximum current is
selected to be the quiescent current level. This current level is 16mA and can be
achieved with a base voltage o f 1.28 V.
The optimum base biasing resistor can be determined through a series o f load
pull measurements. The details o f these load pull measurements are not shown in this
thesis. W e selected 100Q as the base biasing resistor.
6.1.2 Transistor Matching Methods
In a power amplifier design, after the class o f operation has been selected, the
input and output o f the transistor must also be carefully matched to achieve the highest
gain and efficiency.
On the input side, this process is often done through complex
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120
conjugate m a tc h in g o f the complex input impedance o f the transistors to achieve the
best power transfer from a source to the device.
The input impedance can be
determined by s-parameter measurement with the bias determined according to the class
o f operation. A t the output, one can match the impedance according to the s-parameter
measurements.
Another popular method o f determining the output impedance is
through the m ethod o f determining the necessary load impedance to achieve the desired
power output given the value of the supply voltage, hi other words, by estimating the
power as Vsuppiy2/2R, one can determine the necessary impedance level. This process is
similar to the selection o f the load line to allow the largest voltage and current swing to
achieve the highest power output.
Another common method o f matching transistor power amplifier is through
source pull and load pull measurements. This method experimentally determines the
optimum input and output matching condition for the transistors by means of
microwave tuners. The desired output parameter can be measured directly and thus the
optimum input and load conditions can be determined.
The tuners are usually
constructed with a air coaxial waveguide with characteristics impedance o f 50 ohms.
Stub elements can be brought close the to center conductor creating a mismatch to the
waveguide. The closer the stub elements gets to the center conductor o f the waveguide
the larger the reflection coefficient is.
These stubs can also be moved along the
waveguide on a slide to shift the phase o f the mismatch. A schematic representation of
a tuner is shown in figure 6.10.
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121
Micronmeters
Outside Housing
Tuning Stubs
Wave Guide
Figure 6.10 Construction o f a double stub tuner
In recent years, many computer controlled automatic tuner systems have become
available.
A computer controlled tuner system can take the effect o f cables, probes, or
fixtures into consideration during calibration o f the tuners, and the input and output
matching condition can be calculated for each tuner position and stored in the computer.
Often, the reflection coefficients and their phases are shown graphically such that the
user can select the available impedance to be presented to the devices.
After
measurements o f the desired parameter (such as power gain, power added efficiency, or
nonlinearity) are performed, the software can calculate a set o f contours from the
measured data and derive the optimum matching conditions.
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122
spectrum
DC
P o w e r S u p p ly
0
—
a n a ly z e r
TUNER
DUT
PAD
TUNER
power
meter
Figure 6.11 Computer controlled automatic load pull system
During the load pull measurement, the power level o f the input signal is kept
constant. For small signal condition, the gain contours correspond to the gain circles
predicted by measured s-parameters.
For large signal conditions (when the output
power is close to the ldB compression points o f the amplifier or transistor), the output
contour will deviate from the ideal circles.
The load pull system which can
experimentally determine these non-ideal behaviors becomes increasingly valuable
under these conditions. Large signal nonlinear model simulation under these condition
may be time consuming and the result may not be accurate.
Figure 6.11 shows the computer controlled load pull setup to determine
maximum power and power added efficiency. Figure 6.12 shows typical load pull and
source pull contours. The center o f the circles indicate a maximum (or a minimum) o f
the desired parameter, hi the case o f the power amplifiers, these parameters are usually
power gain, maximum power, power added efficiency and third order intermodulation
distortion. For amplifiers used in digital communication, adjacent channel power ratio
(ACPR) can also be measured to study the performance o f the devices or amplifiers.
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123
Highest Power added Efficiency
Highest Gain—
Output Impedance Chart
Input Impedance Chart
Figure 6.12 Sample result o f a load pull measurement
The devices fabricated in this work were tested with an automatic tuner system
(load pull measurements). The results were used to determine the capability o f the
GalnP/GaAs DHBT technology. The transistors were biased for class AB operation to
obtain suitable power added efficiency and linearity.
6.1.3 DHBT M easurement Results
The DHBTs fabricated in this work were tested with Maury load pull system.
The result shows the DHBT performance is comparable to the state o f the art HBT
performance under class AB conditions.
The load pull contour for the optimum power gain is shown in figure 6.13. For
the load matching, the maximum gain and the maximum power match loci are identical
at T l = 0.5540 < 144.35. The maximum power added efficiency matching point occurs
at a higher impedance
(T l
= 0.6030 < 115.00).
The source is matched at 0.7564 <
159.16.
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124
A power sweep was performed after the loci are determined. Figure 6.14 shows
the gain, the power out, and the power added efficiency characteristics o f the 896pm2
DHBT. Similar tests were performed at 2GHz, and the results are shown in figure 6.15.
The results show that the DHBTs fabricated in this thesis can deliver up to 250mW of
power at 60% power added efficiency for the
Currently the commercial power amplifiers typically deliver 1W o f RF power at
Fixed Load Pull
Freq=lG H z
Tsource: 0.7564 < 159.16
Pout:
m ax = 25.77 dBm
at 0.5540 < 144.35
10 contours, 0.5 dBm step
(21.0 to 25.5 dBm)
Gt:
m ax = 24.27 dB
at 0.5540 < 144.35
10 contours, 1.0 dB step
(15.00 to 24.00 dB)
Eff:
m ax = 70.58 %
at 0.6030 < 1 1 5 .0 0
10 contours, 2.0 % step
(52.0 to 70 %)
Figure 6.13 Load Pull Contour o f a 896pm2 DHBT at 1 GHz
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125
!
i
!
i
140
j
i
i
x
i
25
- 120
100
20
3o
I
80
CL
■
C 15
i
x'T
TO
O
i
mm ;
X -X -X X j
.. 60
..^
- L V . . !
10
i
x
|
x-X r*
!
1
!
10
j
15
20
■
Pout_dBm
A.
Gt dB
40
-• 20
—X— lout_mA
—X— Bf_%
25
0
30
P in [ d B m ]
Figure 6.12 Power Output characteristics at 1GHz
Pout_dBm
Gt_dB
X— lout mA
X— Eff %
3
O
0.
ef
'5
O
X -X -X -X
X -X -X '*
y-x-x-x-x-x-**
10
15
20
Pin [dBm]
6.13 Power Output Characteristics at 2GHz
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Icollector, Efficiency
30
126
From the loadpull results, it is demonstrated that GalnP/GaAs DHBTs can be a
direct substitute for standard AlGaAs/GaAs or GalnP/GaAs HBT with comparable
performance. In addition, GalnP/GaAs DHBT, as described previously, has the property
o f reduced charge storage effect.
This adds to the general attractiveness o f this
technology.
6.2 Class D amplifier
In addition to class A, class B, and class AB amplifiers, there exist many higher
classes o f amplifiers which are capable o f achieving higher power added efficiency.
These are the class F, class D, and class S amplifiers.
Many o f these amplifier
architectures forces a square collector voltage waveforms while tailoring the collector
current waveform to be 90 degree out o f phase. Because o f this, the transistor does not
dissipate any power and thus all the power are dissipated in the load o f the circuit.
Ideally, the efficiency o f the transistor would be 100%.
In particular, the class D amplifier uses the devices as switches to achieve the
square waveform. As discussed in the previous chapter, the GalnP/GaAs DHBT exhibit
very short charge storage time. This characteristic is desirable for switching. The detail
o f the class D operation is described in the next section.
6.2.1 Idealized Class D Operation
Class D amplifiers was fist discussed by Baxandall in 1959. It employees a pair
o f active devices in a totem pole configuration. The active devices are used as switches.
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127
The voltage at the mid-totem pole is either pulled all the way to the supply voltage or
the ground voltage.
The closed switch can supply to the load the current that it
demands. Thus, if the load is properly tuned to fit the specification o f the application,
the reactive filtering elements would transform the square voltage waveform at the
collector to the desired sinusoidal waveform at the fundamental frequency to the load.
In this case, the active device dissipate very little power because o f the quadrature offset
o f the voltage and current waveform.
Furthermore, the passive elements used for
matching are all reactive and, ideally, do not dissipate power as well. This allows all the
DC power to be converted to AC power and deliver to the load. The efficiency is
therefore theoretically 100%. Figure 6.14 shows the idealized operation o f the class D
operations.
Vs
high Q filter
Is1
Vs
control
voltage
load
Isi
Is2
Figure 6.14 Class D amplifier operations
The active devices used in the totem pole configuration may not be ideal
switches. Often, there may be switching time if bipolar transistors are used. In this
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128
case, there exist a short period o f time where both the pull up switch and the pull down
switch is on. This would cause the current to flow directly from the power supply to the
ground and cause the efficiency to drop. The non-ideal waveform is also shown in
figure 6.14.
6.2.2 All NPN Totem pole type
In most HBT technology, the only polarity o f the transistor available is the npn
transistors.
The pnp transistor is usually not available with some exceptions [6-6]
because o f the unfavorable bandgap alignment for the hole transport. In addition, hole
mobility in GaAs is much lower than electron mobility in GaAs.
Therefore, a
complementary totem pole (with pnp as the pull-up device and npn as the pull-down
device) is not available. This makes the design o f the class D amplifier more difficult.
In our design, we use a high voltage gain inverting stage to boost up the voltage gain in
the first stage. The second stage is followed by a emitter follower. To avoid power
dissipation in the amplifier itself, an inductive load for the inverting voltage gain stage
was used. The inductor introduced a 90° lead in the voltage waveform, which requires a
90° delay to the input waveform send to the pull-down driver device. It is assumed that
such delay may be introduced with an external delay line in the test setup. Figure
6.16
shows a photograph of the amplifier without the matching load and filter. The output o f
this circuit is leads to a bond pad. The tune circuit and matching circuits are to be
constructed with discrete parts.
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129
Vcc1
V cc2
vb2
02
tuned load
Q3
vbl
delay
line
Q1
On-chip componets
Figure 6.15 Schematic Drawing o f the all NPN class D am plifier
aaaaaHKB
Figure 6.16 Chip photograph o f the DHBT class D amplifier
Ideally, the output voltage will swing from ground to
V cc,
w ith square
waveform. If the proper tuned load is used, the current waveform will b*e 90° out o f
phase. Thus, the efficiency will be high.
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130
A drawback in this design is the presence o f the emitter follower. The intent for
the totem pole is to have the transistors to behave as perfect switches. The lack o f the
PNP HBT in this technology forces the usage o f the emitter follower. However, the
emitter follower transistor (Q2 in figure 6.15) must maintain a DC path to the ground;
otherwise, the emitter voltage will rise to turn the transistor bias off. Thus, a constant
voltage or current bias (at vbl and vb2 nodes o f figure 6.15) must be maintained in
order for this amplifier to have gain. This constant bias sets a DC path directly from the
voltage source Vcc to the ground. It is detrimental to the power added efficiency.
Drive voltage
high
999999^
Emitter voltage
rise to turn
transistor off
T ransistor
off, DC
path to
ground
not
available
Figure 6.17 Difficulty in implementing the emitter follower with the driver HBT off
Despite the non-optimal design, the purpose of this work is to demonstrate the
reduced charge storage effect rather than a good class D amplifier. During the high
V out operation, the base voltage vb2 (figure 6.15) can rise above the Vcc thus driving
the transistor into saturation region. The charge stored in the base collector junction o f
Q2 will cause the transistor to be fixed in the on operation. The reduced charge storage
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131
effect can improve the transition as the transistor Q2 is switched from the saturation
region to the on region.
6.2.3 Measured Results
The class D amplifier shown in figure 6.15 was tested under the following
conditions. Vcci was equaled to 10V, and Vcc2 was equaled to 8.8V. The input was
driven with a pulse generator. Since the purpose o f this work is to demonstrate the
charge storage effect, the load is driven into an oscilloscope to obtain the proper
waveform to observe the switching characteristics.
The small signal gain o f the
amplifier is 20dB gain. The output from the oscilloscope is a square waveform with
amplitude close to 10V.
12
10
8
6
O
>
4
2
0
■2
17
17.5
18
18.5
tim e [ns]
Figure 6.18 Time Domain Response o f the Class D amplifier
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132
The efficiency in this case is 40.84% which is due to the biasing current o f the
transistors. However, the square waveform shows that reduced charge storage effect
allows the circuit to have switching behavior.
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133
Reference
6-1. Ha Tri, Solid-state Microwave Amplifier Design, Wiley, New York, 1981
6-2. John L. B. Walker, “High-Power GaAs FET Amplifiers,” Artech House, Boston, 1993,
pp.3-18
6-3. H. Kraus, C. Bostian, and F. Raab, S o lid
S ta te R a d io E n g in e e r in g ,
Wiley, New York, 1980
6-4. Global Communication Semiconductor, private communication.
6-5. Y. Zhu, J.K. Twynam, M. Yagura, M. Hasegawa, T. Hasegawa, Y. Eguchi, Y. Amano, E.
Suematsu, K. Sakuno, N. Matsumoto, H. Sato, and N. Hashizume, “Compensation of Self­
heating Effect in DC and Pulse Characteristics o f HBTs,” I E E E M T T - S I n te r n a tio n a l
M ic r o w a v e S y m p o s iu m D ig e s t, 1999, pp-431-434
6-6. D.B. Slater, P.M. Enquist, J.A. Hutchby, A. S. Morris et 11, “PNP HBT with 66GHz
Jmaxj” I E E E E l e c t r o n D e v ic e L e tte r s , 1994 Mar., V15 N3:91-93
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Chapter 7. Conclusions and Future Works
7.1 Summary o f the Dissertation
Technological advances in communication and information science have created
a strong demand for mobile communication. With it comes a need for improvement in
power amplifier technologies for wireless communication systems. The purpose o f this
thesis is to investigate the GalnP/GaAs DHBT as a method o f meeting this need. The
areas o f this study include transistor design and characterization, as well as circuit
design and evaluation. Although it is not clear at this time that this DHBT technology is
the best available technology, the necessary characteristics and functionality have all
been demonstrated.
In this work, we designed and characterized double heterojunction bipolar
transistor using the GalnP/GaAs material system. The DHBTs were successfully
fabricated at Rockwell Science Center and Network Device Incorporated. The peak
and yjnax o f the devices are
f t
around 75GHz and 70GHz respectively, which are the
highest for GalnP/GaAs DHBTs to date.
Thermal behavior o f the HBT power amplifier was studied. A novel flip-chip
heatsink approach was demonstrated.
This technology uses the front-side second
metalization as the heatsink and utilizes through-substrate-via as interconnect to the
backside. An additional backside lithography was required to make circuit connections
at the backside. This implementation reduces the thermal resistance o f a 120pm2 by 2.7
times.
133
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134
Another study in this thesis demonstrated the demonstrated the reduced charge
storage behavior o f the base-collector heterojunction, hi this study, the base-collector
diode o f a single heterojunction bipolar transistor (SHBT) and a double heterojunction
bipolar transistor (DHBT) were driven with sinusoidal excitation. The response o f a
SHBT base collector diode (GaAs homojunction) shows a large storage time whereas
the DHBT base collector diode (GalnP/GaAs heterojunction) shows very little charge
storage time.
Detailed analysis o f the charge storage behavior under sinusoidal
excitation was shown in this work for the first time.
Power load pull measurements confirmed the capability o f DHBTs in a high
power amplifier application.
Such load pull measurements are standard transistor
evaluation tools used in the commercial wireless industry. The performance o f the
DHBTs fabricated for this thesis demonstrate that a device with emitter area o f 896(im2
that can produce 250mW at -70% power added efficiency, which is comparable to state
o f the art power amplifiers.
A class D amplifier, which makes use o f the unique
characteristics o f the DHBTs, was also proposed and demonstrated that shows 250mW
at 50% power added efficiency.
This thesis demonstrates that GaTnP/GaAs DHBTs are promising candidates for
power amplifiers in wireless communication handsets.
7.2 Future work
There are many possible avenues for improvement o f GalnP/GaAs DHBT and
power amplifiers. The following areas are promising for further studies in the future.
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135
7.2.1 Undercutting structures for reduced
C
bc
DHBTs
From this study and reported works, the importance o f to reducing base collector
capacitance
C bc
has been demonstrated again and again.
While this work has not
specifically addressed the reduction in base collector capacitance o f GalnP/GaAs
DHBTs, there exist high potential for the production o f highly reduced
C bc
DHBTs
with this material system.
The GalnP/GaAs material system is known for outstanding etching selectivity.
This brings forth the possibility o f design an undercutting etch process in order to
eliminate the high epsilon material (GalnP) beneath the extrinsic base region and
drastically reducing
C bc -
7.2.2 Reduction of AEc Use of Nitrogen-contained compounds
It is now well established that nitrogen contained material such as InGaPN
(Indium Gallium Phosphide Nitride) or GaAsN (Gallium Arsenide Nitride) with small
nitrogen content (<2%) can actually have a bandgap smaller, rather than larger, than the
bandgap without nitrogen, despite that InGaN and GaN has higher bandgaps.[7-l][72] [7-3][7-4]
The bowing factor to describe the bandgap versus composition is very
large.
A small inclusion o f nitrogen during the base collector growth process can
eliminate the base collector AECcompletely, although the nitrogen containing material
has low mobility and is difficult to grow. Most o f the difficulties arise because o f the
process o f cracking diatomic atmospheric nitrogen into monatomic nitrogen atoms. The
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136
lack o f nitrogen tend to cause clustering and create higher defect density in the material.
Many efforts in MBE and CVD techniques are overcoming this obstacle.
With the elimination o f AEc hi the conduction band, the current blocking effect
described in chapter 3 can be reduced. This will improve the operation region o f the
DHBT and improve power added efficiency.
7.2.3 High speed DSP implementation of the class S amplifier
hi this thesis, we have proposed and demonstrated a class D amplifier. The
drawback o f the class D amplifier is that the output o f this amplifier has constant
envelope. The amplification is therefore nonlinear. For future work, we propose the
possibility o f building class S amplifier at RF frequency using 2 —A modulated
signals[7-5].
This class o f amplifier samples a 800MHz RF signal with a 2 -A
modulator and generate a 2.4GHz digital sequence that contains the information in the
800MHz RF signal. The 2.4GHz signal can be amplified with a DHBT based fast
switching amplifier. The output o f the class S amplifier is typically passed through a
low pass filter that will reproduce the information in the original signal. A bandpass 2 —
A modulator demonstrated by Dr. Arun Jayaram at UCSD has demonstrated high
linearity. This would be used in conjunction with the DHBT technology to demonstrate
both high power added efficiency and good linearity.
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137
Reference
7-1. R. Bhat, C. Caneau, L. S a l a m
a n c a - R A a , W. Bi, W; and others, “ G r o w th o f G a A sN /G a A s,
G a l n A s N / G a A s a n d G a ln A sN Z G a A * q u a n tu m w e lls b y lo w - p r e s s u r e o r g a n o m e ta llic
c h e m i c a l v a p o r d e p o s i t i o n JOURNAL OF CRYSTAL GROWTH, 1998 DEC, V195
Nl-4, pp. 427-437
7-2. Uesugi, K; Suemune, I; Hasegawa, T; Akutagawa, T, et al, “ T e m p e r a tu r e d e p e n d e n c e o f
b a n d g a p e n e r g ie s o f G a A s N a l l o y s APPLIED PHYSICS LETTERS, 2000 MAR 6, V76
N10:1285-1287
7-3. Skferbiszewski, C; Perlin, P; Wisniewski, P; Suski, T, et al, “E f fe c t
o f n itr o g e n - in d u c e d
m o d ifi c a ti o n o f th e c o n d u c tio n b a n d s tr u c tu r e o n e le c tr o n tr a n s p o r t in G a A s N a llo y s ,”
PHYSICA STATUS S O T I D T B-BASIC RESEARCH, 1999 NOV, V216 N l, p p . 135-139
7-4. R.J. Welty, Y.G. Hong, H.P. Xin, K- Mochizuki, C.W. Tu, P.M. Asbeck, “Nitrogen
Incorporation in GakiP for Novel 0BTs,” IEEE Cornell Conference on Advanced
Concepts in High Performance Devices, Ithaca, New York, Aug. 2000
7-5. J.Arun, P.F. Chen, P.M. Asbeck, ‘f
in e a r H ig h - E ffic ie n c y M ic r o w a v e P o w e r A m p lifie r s
u s i n g B a n d p a s s D e lta - S ig m a M o d u la to r s ,” IEEE Microwave and Guided Wave Letters,
Vol. 8, No. 3, March 1998, pp. 121-123
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Appendix A. Figures o f Merits
Figures of merits (FOMs) are used for selecting material systems or transistor structures
for various applications. FOMs are commonly derived by selecting key material parameters and
device characteristic parameters and finding their relationship to define a constant. This can
often determine the trade off between these constants and also the maximum performance under
a given operating condition. The selection of FOM for evaluating materials and devices depends
on the task to performed by the solid state devices.
Several figures of merits were alluded to in this thesis. Li our case, the application is the
microwave power amplifiers. For that purpose we will introduce the following figures of
merits—-fufnax, Johnson's figure of merit, and Baliga figure of merit.
A.1 Cut-off frequency (/i)
The cut-off frequency^ is defined as the frequency at which the small signal current gain
(h2i) of a transistor will drop to unity. For a bipolar transistor it can be estimated with the
following equation.
1
— = x EC = r E + t b + r CSCL + r c
2^ r
tec is the
(A-l)
emitter to collector transit time. In other words, the minimum time it takes for a carrier
to travel across the entire transistor structure determines the maximum speed at which this device
can process information. The transit time is composedof delay timein each region of the bipolar
transistor. In the equation above, rE is the emitterdelay. It is made up of the following
components.
r £ = J 7 (e ® + e a ) = ^
& )+' f j
(A_2>
138
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139
where QEj- is the charge stored in the base-emitter depletion region, Qq, is the minority carrier
stored in the neutral emitter region, C be is the emitter-base depletion capacitance, and gm is the
transconductance (=qIc/kT).
The base transit time t B is related to the transit time for a carrier to travel across the
neutral base region. It can be expressed as
WB
=
( a
- 3 )
where the WB is the thickness of the base of the bipolar transistor, r| is the factor contributed by
the build-in electric field in the base region (due to doping or composition differences), D„b is
the electron diffusivity.
The term
Tc s c l
represent the transit time for the collector space charged region. It is
given by the following expression.
^
- f
where Wc is the width of the base-collector depletion region, and v(x) is the carrier velocity.
Finally, the term rc is the base-collector capacitance charging time. It can be expressed
as
kT
Tc = Q c ( R c + R e + ~ T ~ )
(A -5)
where Rc and REare the collector and emitter resistance respectively.
All these equations can be combined back into equation 2-1, and be summarized as
\
kT t
q l c \' C
be
WB2
+ C b c ) + rjD nB +
Wc
r
+
2vI(sat
\
+ R c ) C iBC
(A-6)
The equation above shows that to make a high-speed power transistor, it is necessary to have
base and collector layers that would withstand the necessary voltage and yet thin enough to allow
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140
fast carrier transit. This requires the material to exhibit high breakdown, high mobility, and high
saturation velocity at the same time. As we will see from the other figures of merits that it is
usually difficult to obtain all of the above quality especially if cost is a concern, hi addition to
the material considerations, it is also important from the device structure point of view to have
reduced CBEand CBC-
A .2
Maximum frequency of oscillation ( ./m a x )
The
m ax im u m
frequency of oscillation is determined from the frequency at which the
maximum available gain of a microwave transistor is reduced to zero. It can be estimated with
the following equation.
m ax
(A -7 )
where the RBis the total base resistance, and CBCis the base collector capacitance.
In terms of the two port small signal behavior, theyj^Ax is calculated as the frequency at
which the maximum available gain reaches one. The maximum available power gain can be
derived from s-parameter by the following equation[A.l]:
m ag= |S2i |2(i-|r s|2)/(| i - s „ r s|2 (i-|r0ltt|2)
(A-8)
Because the value foryj^Ax is related to the power gain, this FOM is applicable for
evaluating transistors to be used as high frequency power amplifiers.
A.3 Johnson's figure of Merit
The product of the breakdown field and the saturation velocity of the material is
proportional to the/i and breakdown voltage (BV). This product is called the Johnson’s figure of
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141
merit (JFOM). It can be used as a first cut evaluation for material systems when designing a
microwave power amplifier.
The expression for the JFOM is as followed.
B V ceo
cc
E b Wc
(A-9)
/r o c ^
CA-10)
B V c E o f r ^ E B Vsat
(A-ll)
This relationship can be used to evaluate an advanced material for its compatibility when
used as high frequency amplifier.
A.4 Baliga's figure of Merit
JFOM considers the relationship between^ and breakdown voltage. However, when the
transistor is used as a power switching device, the on resistance of the device should be estimated
by the mobility of the device and the efficiency of the switch should be estimated by the on
resistance of the switching device. JFOM does not take the mobility of the material into
consideration. The mobility is related to the “on” resistance (Ron) of the transistor when the
transistor is used as a solid state switch. The Baliga figure of merit (BFOM) is often used to
examine whether a material system is suitable for the use of high voltage switch. In this case, the
lower the Ron, the higher the power added efficiency the switching circuit will have.
The BFOM can be calculated with the following equation.
B V 1
euE I
(A-12)
BV is the breakdown voltage. Ron as indicated is the on resistance of the switch. EB is the
breakdown field of the material. The dielectric constant and mobility is represented by s and p..
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142
A .l David M. Pozar, M icrowave Enigneering, Addison Wesley, N ew York, 1993, p. 244
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