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Design, fabrication, and characterization of indium phosphide-based heterostructure field-effect transistors for high-power microwave applications

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DESIGN, FABRICATION, AND CHARACTERIZATION OF InP-BASED
HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS FOR HIGH-POWER
MICROWAVE APPLICATIONS
BY
DANIEL GERARD BALLEGEER
B.S., University of Wisconsin-Madison, 1990
M.S., University of Illinois, 1992
THESIS
Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy in Electrical Engineering
in the Graduate College of the
University of Illinois at Urbana-Champaign, 1995
Urbana, Illinois
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U N I V E R S I T Y O F IL L I N O I S A T U R B A N A -C H A M P A IG N
TH E G RADUATE COLLEGE
MAY 1995
WF2 H I ' R E B Y R E C O M M E N D ' F U A T T H E T H E S I S B Y
DANIEL GERARD BA LLEGEER_____________________
I N T I T L E I)
_
_________
D ESIGN. FABRICATION, A ND CHARACTERIZATION OF IiiP-BASED
HETEROSTRUCTURE F1ELD-EFFECT TRANSISTORS FOR HIGH-POWER MICROW A VE
APPLICATIONS
HI': A C C E P T E D
Fi l l - D
IN
PA R T IA L
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FU L F IL L M E N T
OF' T H E
R EO U IR E M E N T S
FOR
DOCTOR O F PHILOSOPu v
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D ire c to r of T h e sis R esearcli
H ea d of D ep artm e n t
C o m m itte e
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Final Ejcai
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t R e q u i r e d fo r d o c t o r ’s d e g r e e b u t n o t for m a s t e r ’s.
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iii
DESIGN, FABRICATION, AND CHARACTERIZATION OF InP-BASED
HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS FOR HIGH-POWER
MICROWAVE APPLICATIONS
Daniel Gerard Ballegeer, Ph.D.
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign, 1995
I. Adesida, Advisor
InP-based heterostructure field effect transistors (HFETs) have, over the past
several years, demonstrated microwave performance capabilities superior to those of GaAsbased and Si-based transistors. In particular, InGaAs/InAlAs modulation-doped field
effect transistors (MODFETs) have exhibited world-record unity current gain frequencies
(fis) as well as extremely high power cutoff frequencies (fm^ s ) and have, therefore,
become the optimum devices for small-signal applications at high frequencies, particularly
in low-noise applications. Despite these strengths, InP-based HFETs have inherent
weaknesses which limit their capabilities for large-signal, high output power applications.
Due to a combination of the poor Schottky characteristics of InAIAs, which is often the
material in contact with the metal gate, and the small bandgap of InGaAs, which is the
material often used for the channel, the devices typically have lower breakdown voltages
than their GaAs counteiparts. However, because of the phenomenally high values o f/, and
/max obtainable for these devices, there has been a growing desire to overcome these
weaknesses in order that the devices can be used for high-power applications at microwave
frequencies.
The subject of this work is the investigation of the possibility of designing InPbased HFETs for use as high-power devices. The emphasis is not on obtaining a worldrecord high frequency power device; instead, the focus is on the critical issues involved
when designing the devices for high power applications. Hence, the goal is to obtain an indepth understanding of the internal physics of the FETs when they are operating as power
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devices, and in so doing, attempt to arrive at designs and techniques which will overcome
some of the limitations of InP-based HFETs.
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ACKNOW LEDGM ENTS
Perhaps the most memorable moments of graduate school were not the actual
academic accomplishments, but the interaction with the people around me. Every action in
life obtains its value and meaning from the people associated with it; from this perspective,
I consider myself fortunate to have met and worked with with many interesting and talented
people during graduate school study.
First and foremost, I am very fortunate to have had Professor Ilesanmi Adesida as
an advisor for my entire graduate education. Over the years, I have discovered that the
impressiveness of Professor Adesida's well-rounded knowledge is surpassed only by that
of his skill at human relations, both with his colleagues and students. As an advisor, he is
adept at handling the delicate balance between demand-making and respect-giving.
There are a number of former graduate students who assisted me on countless
occasions in the junior years of my graduate study and to whom I am deeply indebted.
These include Dr. Andrew Ketterson, Dr. Kari Nummila, and Dr. Minh Tong for their help
with FET processing and measurement; Dr. Sambhu Agarwala, Bill Guggina, Tim Dow,
and (indirectly) Dr. Eb Andideh for help with dry etching; and Dr. Hong Chang and Dr.
Jong-Wook Seo for the times they assisted me with various tasks.
In addition, I have enjoyed getting to know the other students who are presently in
Professor Adesida’s research group. Certain students I had the opportunity to interact with
somewhat regularly include: Patrick Fay, whose skillful assistance and input in numerous
areas of research have been invaluable; Ron Grundbacher, without whom the research with
InP-channel FETs would not have advanced to its present point; Aaditya Mahajan, whom I
have enjoyed working with for several years and who discovered the indispensable link
between gate recess and Disc 2 of Crossroads; Walter Wohlmuth, with whom I rounded
out my skills at electron beam lithography by becoming involved with the fabrication of
MSMs with small finger widths; and Andrew Ping, with whom I have had the recent
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experience of exploring the unique area of EXFET fabrication. I am also grateful to
Roberto Panepucci who assisted with the SEM system, Chris Youtsey for his handiness in
helping me arrive at a setup for high-temperature device measurements, and Carl Scafidi for
performing some of my Hall measurements. The nature of my research was such that my
work never gave me a chance to collaborate directly with Masud Hannan, Mohamed Arafa,
Jean Fleurimont, or Gabriel Cueva, but their willingness to help me with small, random
dilemmas was obvious.
A number of other individuals were also extremely influential during my graduate
schooling. Among those who are especially worthy of notice is John Hughes, Principal
Research Engineer at the Microelectronics Laboratory. His repeated assistance was greatly
appreciated, and it is evident that he is an essential asset to the Microelectronics Laboratory.
I would also like to mention the valuable experience I gained in the Microwave Devices and
Circuits Research Laboratory of GM-Hughes Electronics, under the management of
Dr. Paul Greiling in Malibu, California. There were many people who were extremely
helpful, and I am grateful to Dr. Lawrence Larson for providing interesting and educational
summer projects, which had the effect of accelerating my thesis research rather than
hindering it. I would also like to acknowledge Dr. Mehran Matloubian for making sincere
efforts to collaborate with me while I was at the University of Illinois. I must offer my
wholehearted appreciation to Dr. Catherine Caneau of Bell Communications Research, who
single-handedly provided me with seemingly innumerable OMVPE-grown layer structures.
My thesis research would not have been successful without her constant, dependable
collaboration.
Finally, I could not conclude without extending my sincere thanks to my parents for
their seemingly endless support and patience.
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vii
TABLE OF CONTENTS
CHAPTER
PAGE
1. INTRODUCTION.......................................................................................................1
2. THEORY AND BACKGROUND..............................................................................4
2.1. One-dimensional HFET Theory................................................................... 4
2.2. Two-dimensional HFET Theory................................................................. 13
2.3. Requirements for Microwave Power Applications......................................28
2.3.1. Theoretical operating conditions of a power transistor................ 28
2.3.2. Critical issues in achieving design goals...................................... 33
2.4. References..................................................................................................... 36
3.
MEASUREMENT STANDARDS AND TECHNIQUES................................... 38
3.1. Introduction....................................................................................................38
3.2. Small-signal Measurements........................................................................... 38
3.2.1. Calibration using the LRRM technique.................................38
3.2.1.1. Background of calibration techniques......................... 38
3.2.1.2. Error models and de-embedding..................................41
3.2.1.3. Measurement of standards........................................... 43
3.2.1.4. Initial calculation of error terms................................... 46
3.2.1.5. Load inductance determination.................................... 46
3.2.1.6. Correction of error terms for load inductance.............48
3.2.1.7. LRRM calibration results.............................................48
3.2.2. Small-signal model........................................................................ 49
3.3. Large-signal Measurements..........................................................................54
3.3.1. Direct current figures-of-merit...............................................54
3.3.2. Microwave power measurements..................................................56
3.4. References.................................................................................................... 60
4. EVIDENCE OF THE GUNN EFFECT IN HIGH-POWER InGaAs/InAlAs
M O D FETs......................................................... ....... ..................................................62
4.1. General Transport Theory for Semiconductors...................................62
4.1.1. Transport properties.......................................................................62
4.1.2. Criteria for negative differential mobility.............................. 64
4.1.3. Effect of negative differential mobility in bulk
sem iconductors.......................................................................... 66
4.1.3.1. Gunn domain formation...............................................66
4.1.3.2. Criteria for a propagating domain.......................... 71
4.1.3.3. Stable microwave amplification....................................75
4.2. Relevance of Gunn Phenomena to MODFETs............................................79
4.2.1. Theoretical consideration of Gunn phenomena in MODFETs... .-.79
4.2.2. Observed Gunn phenomena in InGaAs/lnAlAs MODFETs
82
4.2.2.1. Causesof NDR in FETs...............................................82
4.2.2.2. Gated device fabrication and analysis..........................83
4.2.2.3. Gateless device fabrication and analysis......................91
4.3. Conclusion.................................................................................................... 101
4.4. References.................................................................................................... 103
5. FABRICATION OF HIGH-POWERMICROWAVE HFETs...................................105
5.1. Introduction.................................................................................................. 105
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viii
5.2. Vertical Scaling Issues.......................................................................... 106
5.2.1. B ack g ro u n d ...................................................................................106
5.2.2. Dependence of dc characteristics on barrier thickness....................108
5.2.3. Dependence of microwave characteristics on barrier
thickness.......................................................................................... 110
5.3. Asymmetric Gate Recess................................................................................ 114
5.3.1. Concept............................................................................................114
5.3.2. A four-layer electron beam resist process for asymmetric
recess................................................................................................114
5.4. InP as a Channel Material............................................................................... 125
5.4.1. Concept............................................................................................125
5.4.2. InP-channel MODFETs with nonalloyedohmic contacts............... 125
5.4.3. Effects of asymmetric recess on MODFET performance........... 133
5.4.3.1. Device fabrication.................................................... 133
5.4.3.2. Direct current characteristics...................................137
5.4.3.3. High frequency characteristics...................................... 145
5.4.3.4. Conclusions about asymmetric recess..................... 149
5.4.4. Fabrication of ohmiccontacts to InP channels............................... 151
5.4.4.1. Effect of thin interfacial A1P layer.................................153
5.4.4.2. Delta-doped InP-channel MODFET study of
ohmic contacts................................................................155
5.4.4.3. InP-channel MISFET study of ohmic contacts..........158
5.4.5. Comparison of InP-channel MISFETs to InP-channel
MODFETs........................................................................................163
5.4.5.1. D evice fabrication.................................................... 163
5.4.5.2. Device characteristics and figures-of-merit...................165
5.4.5.3. Pow er perform ance.................................................. 168
5.4.5.5. Summary of InP-channel device comparison...............178
5.5. References.......................................................................................................179
6. SUMMARY AND FUTURE RESEARCH DIRECTIONS................................... 185
APPENDIX. FREQUENCY BANDS......................................................................... 188
VITA................................................................................................................................ 189
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1
CHAPTER 1.
INTRODUCTION
InP-based heterostructure field effect transistors (HFETs) have, over the past five
years, demonstrated microwave performance capabilities superior to those of GaAs-based
and Si-based transistors. In particular, InGaAs/InAlAs modulation-doped field effect
transistors (MODFETs) have exhibited world-record unity current gain frequencies (fts) as
well as extremely high power cutoff frequencies (fmaxs) and have, therefore, become the
optimum devices for small-signal applications at high frequencies. The outstanding highfrequency characteristics of the devices have been attributed to the large conduction band
discontinuity between InAlAs and InGaAs, which results in large carrier concentrations in
the channel, as well as the superb electron transport properties of InGaAs, including a
small electron effective mass and a large saturation velocity. Commercially, InP-based
HFETs have found their niche in the front end of low-noise circuits which operate
anywhere in the frequency range of 5 to 70 GHz or even higher. Such circuits are
extremely useful for long-range communication applications which may require extremely
low noise at the front end.
Despite their superior low-noise performance at microv/ave frequencies, InP-based
HFETs have inherent weaknesses which limit their capabilities for large-signal, high output
power applications. First, the devices typically have lower breakdown voltages than their
GaAs counterparts. This is due to a combination of the poor Schottky characteristics of
InAlAs, which is often the material in contact with the metal gate, and the small bandgap of
InGaAs, which is the material often used for the channel. Second, the devices suffer from
a large output conductance, primarily because of the small bandgap of InGaAs, which
makes it difficult to obtain a state of carrier pinch-off over the entire depth of the channel.
However, because of the phenomenally high values of / f a n d /max obtainable for these
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2
devices, there has been a growing desire to overcome these weaknesses in order that the
devices can be used for high-power applications at microwave frequencies.
Because of the current need in industry for high-speed, high-power microelectronic
FETs, the subject of this work is the investigation of the possibility of designing InP-based
HFETs for use as high-power devices. The emphasis is not on obtaining a world-record
high-frequency power device; instead, the focus is on the critical issues involved when
designing the devices for high-power applications. Hence, the goal is to obtain an in-depth
understanding of the internal physics of the FETs when they are operating as power
devices, and in so doing, attempt to arrive at designs and techniques which will overcome
some of the limitations of InP-based HFETs.
Chapter 2 begins with a look at the fundamentals of HFET theory, including not
only a review of the traditional one-dimensional theory but also a look into twodimensional issues which are extremely important for high-power microwave applications.
Some fundamental concepts related to power applications are then addressed, followed by
design criteria for HFETs which are intended for use as high-power devices at microwave
frequencies.
Chapter 3 describes measurement issues and conventions used when measuring
figures-of-merit for high-power devices. Measurements at dc are covered first, followed
by high-frequency scattering-parameter measurements, with a detailed section describing a
thru-reflect-reflect-match calibration routine, which is to date one of the most accurate onwafer calibration methods for scattering parameter measurements at extremely high
frequencies.
Chapter 4 delves into an issue which until recently was not a concern in MODFETs:
negative differential resistance (NDR) due to Gunn phenomena. An in-depth description of
relevant Gunn theory appears first, followed by a characterization of actual InALAs/InGaAs
MODFETs which display NDR at both dc and high frequencies. Conventional Gunn
theory is applied to the analysis of these devices to gain an understanding of the
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mechanisms underlying their unique external behavior. Explanations are given regarding
the usual absence of observable Gunn phenomena in MODFETs and why this phenomena
can suddenly appear in certain designs of InP-based HFETs.
Chapter 5 contains experimental data involving different device designs. Vertical
scaling issues in high-power HFET design are first addressed, followed by an in-depth
look at horizontal scaling issues, including a complete description of a unique multilayer
electron-beam resist process for asymmetric gate recess. Next, devices with InP channels
are investigated, beginning with a characterization of InP-channel MODFETs with non­
alloyed ohmic contacts. Devices similar to these which have been symmetrically and
asymmetrically recessed are compared to InGaAs-channel MODFETs. A brief look into
optimizing the ohmic contacts of InP-channel HFETs is then included. This leads into the
section involving InP-channel metal insulator semiconductor field-effect transistors
(MISFETs), which, unlike conventional InP-channel MODFETs, are able to have alloyed
ohmic contacts. Device behavior at dc and high frequencies of InP-channel MISFETs with
different types of gate recess are compared to similarly fabricated InP-channel MODFETs.
Finally, the microwave power performances of both symmetrically and asymmetrically
recessed InP-channel MISFETs and MODFETs are compared and conclusions drawn.
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4
CHAPTER 2. THEORY AND BACKGROUND
2 .1 .
O ne-dim ensional H FE T T heory
To understand the physics of HFETs, it is first necessary to be familiar with the
energy band diagram present at a heterojunction. Figure 2.1 shows the equilibrium band
diagram of such an interface; the material with the larger bandgap is drawn on the left and
the smaller bandgap material is drawn on the right of the figure. Here, the surfaces of the
sample are assumed to be extremely far away from the interface so that they have no effect
on the shape of the energy bands in this region. In this example, the high bandgap material
is assumed to be heavily doped with donors except for a spacer layer of undoped material
of thickness tsp next to the interface, and the low bandgap material is assumed to be
undoped. When these two materials are brought into contact, there is significant electron
transfer from the n-type, high bandgap material to the low bandgap material, which creates
a depletion region in the n-type material next to the interface and an extremely thin layer of
electrons in the low bandgap material next to the interface. Because the electrons which are
transferred to the low bandgap material exist in a potential well which prevents motion in
one direction, the congregation of electrons is often referred to as a two-dimensional
electron gas (2-DEG). The precise expression for the sheet concentration of the 2-DEG
present at the interface can be exceedingly difficult to derive. The concentration of charge
per unit area depleted from the high bandgap material is found by using Poisson's equation
and results in [2.1]
"*0 =
M oS
f
- E f H Ndhp2 - Hd'sp
(2.1)
where Ehb is the dielectric permittivity of the high bandgap material, q is the magnitude of
the electron charge, Nd is the donor concentration in the high bandgap material, AECis the
conduction band discontinuity (which in the Anderson model is the difference between the
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5
-vac
electrons reside in this well
(electron affinity)
AE,
^c
Eg jb (low bandgap)
EF
Ev
Eg hb <h‘gh bandgap)
AE,
high bandgap material
low bandgap material
Fig. 2.1. Band diagram of heterojunction of two materials with different energy bandgaps.
Tliv left material has the higher bandgap and is doped n-type with an undoped spacer
thickness of tsp, and the right material has the lower bandgap and is undoped.
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6
electron affinities of the two materials [2.2]), tsp is the undoped spacer thickness, and 6p is
the difference between the conduction band edge in the bulk of the high bandgap material
and the Fermi energy, Ep. The energy reference is the conduction band edge of the low
bandgap material at the heterojunction. The concentration of charge accumulated in the
potential well by charge conservation is equal to (2.1) but is also given by an expression
found by applying Fermi-Dirac statistics in the low bandgap material [2.1]:
m kgT
* s O = - ^ l n "(l + eq(E' - E°)lk°TJ l + ertE'~E>)/k’T y
(2.2)
where m* is the effective electron mass in the low bandgap material, h is Planck's constant
divided by 2tc, kjj is Boltzmann's constant, T is the temperature, and Eo and Ej are the
positions of the first two allowed energy subbands in the 2-DEG potential well (in this
expression, all other subbands are assumed to be high enough to be ignored). The values
for Eo and Ei are found by applying Schrodinger's equation to the well, but they are
dependent on the shape of the well, which in turn depends on the electron concentration.
An exact analytical expression for nso is, therefore, difficult, and in practice, it is found
numerically.
In an actual HFET, the low bandgap material is used as the channel material, and
the electrons in the 2-DEG carry the current. Figure 2.2(a) is a depiction of the crosssection of a typical HFET. The two main types of HFETs, MISFETs and MODFETs,
differ mainly in the location of the dopants. In a MODFET, the high bandgap material is
doped n-type and the electrons supplied by these donors transfer to the undoped channel,
where there is very little impurity scattering; this is the basic principle of modulation
doping. In a MISFET, the channel or a portion of the channel is doped and the high
bandgap material is completely undoped; in fact, this material can be a conventional
insulator such as Si02 [2.3]. For structures which are grown epitaxially on InP substrates,
however, the high bandgap material is commonly InxAli-xAs and the channel material is
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7
source
p H
cap layer
high bandgap material
(Schottky/charge
supply layer)
ohmic
ohmic
low bandgap material
(channel layer)
2-DEG
buffer layer
charge concentration is modulated
(active channel region)
(a)
electron concentration
N
Ey
gate
3
h►
H
T3
h-H
<D
O
a
o,
T3
C
S
S '
undoped InAlAs spacer
sa> J§S
ao o
-a
c
3
<
>
20 nm
undoped InAlAs
(buffer)
InP substrate
(b)
Fig. 2.2. (a) Generic HFET layer structure illustrating various regions of the device,
(b) Energy band diagram of InGaAs/InAlAs MODFET. The layer structure and
electron concentration are also shown.
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8
often InyGai-yAs or InP, both of which have extremely good properties for electron
transport.
As shown in Fig. 2.2(a), ohmic drain and source contacts are fabricated on the
surface of the HFET structure, and for conventional alloyed contacts, the sample is alloyed
so that the metal diffuses downward into the channel (a diffusion distance on the order of
30 nm for most layer structures). The gate contact is formed by recessing a trench in the
cap material and placing the gate contact on the high bandgap material. This contact is
meant to have a Schottky characteristic so that the gate can be reverse biased with minimal
gate current
Figure 2.2(b) shows an InGaAs/InALAs MODFET layer structure, rotated 90° from
the orientation of Fig. 2.2(a), with its associated energy band diagram and electron
concentration profile, calculated using a computer simulation program. Here, the gate,
drain, and source are all held at the same potential. As is apparent, the standard quantum
well at the InAlAs/InGaAs interface exists due to the conduction band-bending in the
InGaAs. Furthermore, the entire InGaAs channel is a quantum well as a result of being
surrounded by the InAlAs donor layer and the InAlAs buffer layer. The conduction band
offset between InGaAs and InAlAs is on the order of 0.52 eV [2.4]. As a consequence,
the carriers are confined to the InGaAs with the largest concentration at the conventional
location of the 2-DEG, close to the interface of the donor and channel materials. Figures
2.3(a) and 2.3(b) are similar diagrams for an InP-channel MODFET and an InP-channel
MISFET, respectively. Because the junction of InAlAs and InP is a Type II interface, the
conduction band offset between the two materials is on the order of 0.25 eV [2.5] even
though the energy bandgap difference between the two materials is only 0.1 eV. The result
is less carrier confinement in the 2-DEG potential wrell, and in the case of the InP channel
MISFET, the largest electron concentration is actually in the center of the channel material.
What should be noted in Figs. 2.2(b), 2.3(a), and 2.3(b) is that the Schottky barrier
potential of the gate metal-InAlAs contact actually depletes some of the donors in the
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electron concentration
gate
undoped InAlAs
(buffer)
'O
<D
O,
O
"O
undoped InAlAs spacer
InP substrate
20 nm
electron concentration
undoped InAlAs
(buffer)
gate
Q.
O
T3
InP substrate
10 nm 10 nm
(b)
Fig. 2.3. Energy band diagram, layer structure, and electron concentration of (a) InPchannel MODFET, (b) InP-channel MISFET.
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10
material, which results in less charge in the channel. This implies that at zero gate bias, the
carrier concentration in the channel is less than it would be if the heterojunction were
infinitely far from the surface. When the gate is positively biased and the drain and source
are grounded, more carriers will be attracted to the channel from the external bias circuitry.
In the case of a MODFET, this attraction exists because there must be additional electrons
in the channel to terminate the additional electric flux lines which exist due to the positively
biased gate. The channel carrier concentration can increase to the point at which it equals
nso of (2.1). At this point, the donor layer is no longer completely depleted and electrons
will appear in the donor material if the gate bias is increased [2.6]. In the case of a
MISFET, a positively biased gate simply reduces the number of depleted donors in the
channel, which increases the number of electrons present. The maximum number of
electrons in this case is roughly equal to the number of donors present. To achieve this
electron level, however, the gate would have to be biased to the point at which the gate
voltage was equal to the Schottky barrier voltage of the material, and extreme forward gate
current would result, making the device useless for most applications.
Conversely, when the gate is negatively biased, electrons will be driven out of the
channel material to the external bias circuitry. If the gate voltage is made negative enough,
the channel will be in the pinched-off state, at which point virtually no carriers are present
in the channel. Figure 2.4 is a generic HFET layer structure with n-type doping regions
present in the high and low bandgap materials and with a Schottky layer which may or may
not be of a different material than the high bandgap material. If the cap is recessed so that
the gate metal is deposited on the high bandgap Schottky material, the expression for the
gate-to-channel pinchoff voltage Vpo can be determined by a straightforward application of
Poisson's equation, yielding
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11
cap layer
tschot _
undoped Schottky layer
tdnr ,
n-type high bandgap material (donor layer), conc'n =
*spcr,
undoped high bandgap material (spacer layer)
^D ch ,
undoped low bandgap material (2DEG-channel layer)
‘MISch,
n-type low bandgap material (MISFET channel layer), conc'n =
undoped low bandgap material (channel/sub-channel layer)
buffer material
Fig. 2.4. Schematic of generic HFET structure.
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12
/
V
*po
A E C + ^ E C j d + 5 F ,lb
-r»,
V b
-q W ch a n tM lS ch l
t schot
\ e schot
.
n
(fid n r]
\
tsch o t
|
(,£ schot
2 Shb j
, W ( fspcr ]t2Dch | {MISch )
£ hb
£ hb
£ lb
(2.3)
2 e lb )
where q>B is the Schottky barrier height of the gate contact; AEC is the difference between
the conduction band edge of the high bandgap material and that of the low bandgap material
at their interface; A E c^ is the difference between the conduction band edge of the Schottky
material and that of the high bandgap material at their interface; 8F,ib is the energy
difference between the conduction band edge at the point in the channel at which the electric
field is zero and the Fermi level is constant; Nd is the number of donors in the high bandgap
donor layer per unit volume; Nchan is the number of donors in the doped channel layer per
unit volume; tschot. tdnr. tspcr. *2Dch and tMiSch are the thicknesses of the Schottky, donor,
spacer, 2-DEG undoped channel, and doped channel layers, respectively; and
Eschot. £ hb>
and £ib are the dielectric permittivities of the Schottky, high bandgap, and low bandgap
materials, respectively.
Note that for many layer structures, either Nd = 0, as in a
conventional MISFET, or NChan = 0, as in a conventional MODFET, and (2.3) simplifies
considerably. Frequently, planar doping is used instead of uniformly doped regions, and
the square-bracketed [] terms in (2.3) must change accordingly to sheet donor densities.
For example, if the uniformly doped region in the high bandgap material in Fig. 2.4 is
replaced by planar doping, Ndtdnr in (2.3) should be replaced by N^sheet. the planar doping
concentration per unit area. Also, since in this case tdnr = 0, the other term involving tdnr
would simply drop out of the expression altogether.
In a conventional MODFET with the drain and source both grounded, the channel
sheet electron concentration ns is linearly dependent on the gate-to-channel voltage Vgc if
this voltage is sufficiently greater than the pinchoff voltage [2.7]:
£ hb
ns =
-i
'
'
Co
f ( V - v r ) s — (Vt c - V r )
Q yspcr ■*"tdnr + tschot )
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(2.4)
13
where the gate capacitance per unit area, Cg, has been defined. Here it has been implicitly
assumed that Eschot - Ehb- The term V j is known as the threshold voltage for the linear
charge control regime and is technically slightly greater than the pinchoff voltage.
However, in many cases, Vpo is roughly equal to V j; hence, the two terms are often used
interchangeably in literature. Figure 2.5(a) is a plot of the simulated sheet carrier
concentration for the InGaAs/InAlAs MODFET layer structure of Fig. 2.2(b), verifying
that the carrier concentration does indeed have a linear dependence on Vgc over a large
range of gate voltages. Figure 2.5(b) shows the simulated electron distribution in the
channel at different gate voltages for the same structure. Figures 2.6(a) and 2.6(b) are
similar plots for the InAlAs/InP MISFET structure of Fig. 2.3(b). As is apparent, the
dependence of sheet concentration on gate voltage for MISFETs is not linear in nature.
Analytically, it is easy to show that for a MISFET structure similar to Fig. 2.4 with Nd = 0,
i.e., the high bandgap material completely undoped, and t2Dch = tschot = 0, and defining
tins = tspcr + tdnr. the sheet concentration is given by
ns ~ N chan ^M lSch^hns
^
gc
^Ec
^f)
(2.5)
where for simplicity it has been assumed that the electric permittivities of both the channel
and the high bandgap materials are equal to e. Although (2.5) is approximate, it is clear
that ns has a nonlinear dependence on the gate-to-channel voltage, Vgc.
2.2.
Tw o-dim ensional H FE T Theory
Section 2.1 described the effect of the gate voltage on the channel carrier
concentration when the drain and source were grounded. Obviously, the situation is much
more complex when the drain is biased as well. This section will address the issues
involved when a MODFET is biased as a three-terminal device. The analytical expressions
for a MISFET will vary somewhat from those derived here, but the final conclusions
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14
£
CO
CD
Q.
CD
C
c
CO
x:
o
c
c
o
CO
c
CD
o
c
o
o
CD
CD
sz
cn
G ate voltage
(a)
0
E
3
O
>
'c
3
increasing gate bias
i—
0
CL
c
o
0
c
0
< — edges o f channel
layer
o
c
o
o
c
2
T3
©
LU
Vertical distance from gate
Gate
(b)
Fig. 2.5. (a) Channel sheet electron concentration versus gate bias in InAlAs/InGaAs
MODFET, (b) Electron concentration profile in InAlAs/InGaAs MODFET at different gate
biases. The source and drain are assumed to be grounded.
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(0
G ate voltage
(a)
a>
E
=>
o
increasing gate bias
>
‘c
3
>—
CD
Q.
c
o
2
c
0)
o
c
o
o
c
ou .
< — edges o f channel
layer
Vertical distance from gate
Gate
(b)
Fig. 2.6. (a) Channel sheet electron concentration versus gate bias in
InAlAs/InP MISFET, (b) Electron concentration profile in InAlAs/InP MISFET
at different gate biases. The source and drain are assumed to be grounded.
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16
drawn from the MODFET analysis will also apply to MISFETs, at least on a qualitative
level.
A zeroth-order model for the MODFET might assume that when the drain is
positively biased, all electrons in the channel travel at the saturation velocity Vsat in which
case the drain current Id would be equal to qnsVsatW, where W is the width of the channel.
Use of (2.4) in this expression would, therefore, enable a straightforward calculation of the
zeroth-order estimate of the device transconductance gf^:
(2 .6)
In reality, the saturated velocity approximation is inadequate, and only at large gate
biases does it even resemble actual device behavior [2.8]. A more rigorous analysis
involves the gradual channel approximation used in MOSFET analysis, which assumes that
the vertical fields originating from the gate bias are much stronger than the fields in the
direction of current flow, which originate from the drain bias [2.9]. This approximation
allows the use of (2.4) in determining the electron concentration at each point in the
channel. Although analysis similar to the analysis that follows has appeared before in
literature, the analysis presented here will have a unique emphasis on certain issues
involving velocity saturation in the channel, which reveals concepts important for
understanding the behavior of HFETs when they are used as power devices.
The sheet current density, Js, in a MODFET is given by
J s = Qnsvd =
= Q W -r
(2.7)
where V is the potential at a position x in the channel, |i is the electron mobility, Vd is the
electron drift velocity, and £ is the electric field in the direction of cuiTent flow. The
noticeable absence of minus signs in (2.7) arises from the following convention: the
quantity vd is assumed to be positive when the electrons are traveling in the +x direction,
and Js and £ are assumed to be positive when oriented in the -x direction. This convention
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is shown in Fig. 2.7(a). Diffusion is neglected, similar to standard MOSFET analysis
[2.9]. The source region is defined to be at x = 0 and V = 0, and the drain region is
assumed to be at x = Lg and V = Vds, where Lg is the physical gate length and Yds is the
drain-source bias.
Finally, a two-piece linear model of the electron velocity-field
characteristic is assumed, in which the velocity is given by Vd = |i^ for £ < £c and Vd = Vsat
for £ £ ^c. This model is shown in Fig. 2.7(b).
The quantities V and ns are functions of x; it would be expected, for example, that
because V increases with x, and ns is dependent on (Vg - V-Vx) = (Vgc -Vt ), as is apparent
from (2.4), ns would be expected to decrease with x. In contrast, because of current
continuity, Js is constant. Algebraically, this condition implies that
J j = nCg(Vg - V —V j ) — = constant
dx
(2 .8)
Integrating with respect to x, solving for V, and discarding the nonphysical solution yield
(2.9)
where for the moment it is implicitly assumed that V < Vg - Vx at all points in the channel
so that the linear charge control approximation is valid. It is easy to find the electric field
from (2.8); use of (2.9) in the resulting expression gives
(2. 10)
Expression (2.9) can be used in (2.4) to find the sheet carrier concentration as a
function of position in the channel:
(2. 11)
This function has a parabolic shape and is plotted in Figs. 2.8(a)-2.8(c). When the gate
bias is considerably greater than the threshold voltage, as in Fig. 2.8(b), the profile has a
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18
V=0
V = V,ds
x=0
x=L
'g
+x direction
source region
channel
drain region
£ field
vd
(a)
▲
slope = \i
Drift velocity
sat
Electric field %
Fig. 2.7. (a) Schematic of a channel showing direction conventions used,
(b) Two-piece linear model for drift velocity-field characteristic of the
channel material.
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c
c
o
*3
CQ
t>
uc
o
c
oJ
C
c
go
2 J VL,
13
<
OD
J=
CO
x=0
Position in channel, x
x=L
cW
c
o
•a
£
ocS
o
o
c
§u
.22
13
x= 0
Position in channel, x
x=L
c
.2
03
.b
aoc>
c
o
o
e
§o
JS
13
9
2/ rLp
(l'8 -V T )2 > » - J r 1
a8
CO
x=0
Position in channel, x
x = L.
(C)
Fig. 2.8. Sheet electron concentration as a function of position in the channel
for various gate bias/current conditions. It is assumed that the drain-source bias
is below the value required for current saturation.
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20
linear shape, and when the gate bias is much greater than the threshold voltage, as in Fig.
2.8(c), the sheet concentration has a near constant value.
The expressions (2.9)-(2.11) are valid for drain-source biases which are small
enough that the critical field for velocity saturation, defined as
in Fig. 2.7(b), is never
reached in the channel. When this value is reached, v equals Vsaj, which is the maximum
velocity obtainable. At this point, (2.9)-(2.11) become invalid.
To address this issue, the special case of a drain-source bias such that %=
at
x = Lg will first be considered. It will be shown that this is the minimum bias at which Js
is equal to Jssat. the saturation sheet current density. In this special case, (2.10) becomes
(2.12)
Solving for Jssat results in
(2.13)
It is now interesting to calculate the expression for Vdssat. the minimum drain bias at which
v = Vgat at x = Lg. Using (2.13) in (2.9) yields
= V g - V T - J(V g - V T)2 + ( t cLs )2 + S cLs
(2 .1 4 )
This expression is plotted versus Vg - V t in Fig. 2.9(a), where all quantities have been
normalized to £,cL g.
Although (2.14) is somewhat cumbersome, it is simplified
considerably for two extreme cases. First, when Vg - V j is much greater than £cLg,
Vdssat ~ £cLg» which can be seen to be equivalent to the case illustrated in Fig. 2.8(c); in
such a situation, the sheet charge density is nearly constant throughout the channel, as is
the electric field. Second, when Vg - Vx « ^cLg> Vdssat approaches Vg - V j; in other
words, for gate biases just above threshold, the channel is nearly pinched off at the edge of
the channel near the drain. This also implies that under these circumstances current
saturation is obtained at extremely small drain biases. These two cases are shown in
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21
0.8
0.6
'g
0.4
0.2
0
1
2
3
4
5
6
7
8
9
10
Vg ~ VT
(a)
3
2. 5
= 3. 5
2
saturation threshold
1.5
Cgvsat%cLg
1
= 0.5
0.5
0
0
0.5
1
1.5
Vdssat
2.5
(b)
Fig. 2.9. (a) Minimum value of the normalized drain-source voltage required for
current saturation versus normalized gate voltage in a MODFET. (b) Normalized
drain I-V characteristics of a MODFET, with a trace displaying the threshold of
current saturation, where a two-piece linear velocity-field characteristic is assumed.
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Fig. 2.9(a). Finally, when (2.9) is rewritten for the special case of the onset of current
saturation, the resulting expression is
(2.15)
An expression for (Vg - V j) in terms of Jssat may be obtained from (2.12). Plugging this
into (2.14) and simplifying produces the relation
(2.16)
with
(2.17)
(2.18)
This relationship is plotted in Fig. 2.9(b), with the normalized drain-source voltage
displayed on the horizontal axis. Normalized drain I-V characteristics are drawn in dashed
lines to illustrate how (2.16) dictates the point at which the current saturates. The current
traces in the region below saturation were calculated with the aid of (2.9). The abrupt
kinks in the traces at the point of current saturation arise from the assumption of the twopiece linear velocity-fxeld relation of the channel material. Note that at high gate biases the
current trace tends to take on the shape of the velocity-field relation, which arises from the
fact that the electron concentration and longitudinal field are nearly constant at these biases
(see Fig. 2.8(c)).
The next issue to be addressed is the effect of increasing Vds above Vdssat- 1° this
situation, the saturation velocity is reached at the point x = xsat, where Xsat < Lg. The
velocity cannot increase beyond this value, which implies that between x = x^t and x = Lg,
the velocity is constant. Because current continuity requires the charge density-velocity
product to be constant at all points in the channel, it can be seen that ns is constant in this
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23
region as well and is at its minimum value of nsmin. Hence, the current density truly
saturates (see Fig. 2.9(b)), the gradual channel approximation as well as the charge control
approximation are not valid in this section of the channel, and excess carriers exist due to a
strong longitudinal component of the electric field rather than to the modulation of the
transverse electric field by the gate. The sheet carrier concentration takes on a profile
illustrated in Fig. 2.10(a). In the region 0 < x < Xgat, the electric field is given by (2.9),
which was derived using the charge control and gradual channel approximations. In the
region Xsat < x < xmax, where xmax is the point at which the electric field has its maximum
value, the electric field is related to the excess carrier concentration by Poisson’s equation,
which can be integrated to obtain
g=j
(2.19)
£
This relationship is plotted in Fig. 2.10(b). Thus, in the region x^t < x < xmax, the electric
field is quite large. For x > xmax, the electric field decreases to zero due to a depletion
region which is associated with the accumulated electrons in the region of x ^t < x < xmax.
Therefore, the high-field region exists because of a stationary dipole domain that forms on
the drain side of the channel to support the external bias. Monte Carlo simulation reveals
that the electric field in this domain has a transverse component in addition to the
longitudinal one, since much of the electric flux inside the domain must originate from
positive donor ions in the donor layer [2.10] and [2.11]. When the drain bias is increased
well above Vdssat* it is evident that the gate will tend to deplete the carriers on the drain side
of the channel, xmax will exceed Lg in order to sustain the larger voltage drop, and the
longitudinal electric field will become quite strong in order to support a larger dipole
domain. This phenomenon is shown in Fig. 2.11; as illustrated, the extension of the
depletion region on the drain side of the gate at high drain biases is often called the drain
depletion region, which causes the effective gate length of the device to increase as Vds is
increased. If the two-piece linear velocity-field model is replaced by the true velocity-field
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24
c
c
o
•a
Bl
ac
oVG
O
O
G
e
Jj
13
x
sat
x=0
x = x.
Position in channel material, x
(a)
213
ta
o
• f i
8
E
x=0
p
, Xsat
Position in channel, x
x = xmax
(b)
Fig. 2.10. (a) Electron concentration and (b) electric field profiles in
the channel of a MODFET with a drain-source bias such that the
current is well into the saturation region, i.e.,
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25
M s > Mssat
source
drain —?
ir InGaAs
n 1"InGaAs
1
v_
T
2-DEG
tk
w
/
/
i-InAlAs
n-InALAs
i-InAlAs
channel
high field/dipole region
drain depletion region
Fig. 2.11. Schematic of InGaAs/InAlAs MODFET biased well into
the region of current saturation.
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26
relation of the channel material, complete with the negative differential mobility region, the
dipole domain in the channel associated with the drain depletion region is even greater in
magnitude, even when the device is stable.
In Chapter 4, this and other negative
differential mobility issues will be addressed.
It is now possible to return to the issue which was first addressed in this section;
i.e., the expression for the transconductance of the device when the current is saturated.
This can be calculated from (2.13):
_ S\id I
w c gvsal( y s - v T)
1/ ( | ct s )2 + (l' 8 - F T )2
g0
m( v g - v T)
J e t cLg )2 + ( V g - V T f
where the results of (2.6) have been used. It is apparent that at large gate biases, i.e., for
Vg - V j »
£cLg> gm approaches
since the saturated velocity model is more valid
when there is an abundance of charge in the channel. This trend is shown by the top trace
(Rs = 0) of Fig. 2.12, which is a plot of the ratio of gm to g° versus Vg - V j, where the
latter quantity has been normalized to E,cLg- The analysis up to this point has assumed a
source resistance Rs of zero. For a nonzero source resistance, the term (Vg - V j) in (2.13)
must be replaced by (Vg - V j - IdRs)- The values of drain current and transconductance at a
given gate voltage must then be solved numerically. The resulting transconductance curves
are also plotted in Fig. 2.12 for g ^R s product values which are reasonable for the
InGaAs/InAlAs material system.
Finally, the dashed lines indicate how the
transconductance decreases at larger gate biases due to parallel conduction in the donor
layer [2.6] and [2.7]. In practice, the transconductance characteristics of MODFETs have
slightly different appearances, including a more narrow shape with a higher peak value,
due to issues which have been ignored in this discussion, such as the peaked nature of the
true velocity-field characteristic, velocity overshoot, and subthreshold current.
As was mentioned at the beginning of this section, the exact analytical expressions
for MISFETs are slightly different than the MODFET equations presented here. However,
certain issues which will be important for power performance are true for both types of
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27
0.8
,0R =0.5
0.6
8m
8m
0.4
0.2
parallel conduction
0
0.5
1
1.5
2
2.5
3
3.5
4
Vg ~ VT
ZcLg
Fig. 2.12. Transconductance ratio versus the normalized difference
between the gate and threshold voltages in a MODFET. Traces are shown
for different values of source resistance. The dashed lines illustrate how the
transconductance in a MODFET degrades at larger gate voltages because of
parallel conduction in the donor layer.
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28
devices. First, the velocity of carriers in the channel reaches a saturation level when the
drain-source bias is increased. Second, current saturation occurs at very small drain biases
when the gate is biased just above threshold. Finally, when the drain-source bias is
increased further after current saturation has been obtained, there is a high-field domain
which forms on the drain end of the device near the edge of the gated region of the channel.
What remains to be addressed is the effect these issues have on the power performance of
HFETs.
2 .3 .
R equirem ents for M icrowave Pow er Applications
2 .3 .1 . T heoretical operating conditions of a pow er tran sisto r
Now that the fundamental device behavior of HFETs has been analyzed, it is
necessary to investigate what attributes the devices must possess to be suitable for largesignal amplification. Figure 2.13(a) shows a simplified biasing scheme for Class A
operation. For this discussion, an optimum resistance Ropt is assumed to be connected to
the drain, where the value of Ropt is such that the maximum possible value of output power
is extracted from the device when the DC source Vdcopt is used as the positive voltage rail.
For such a biasing configuration, the load-line diagram is shown in Fig. 2.13(b). The
maximum output signal of the device swings from a fully "on" condition, with Vds = V^nee
and Id = Imax. to a fully " o ff condition, with Vds equal to the drain-to-source breakdown
voltage BVds and Id = Ipinchoff- This swing corresponds to an input voltage signal swing
from
V g S = V g sm a x
(approximately
0 .4 V -0 .5
since the barrier height of this material is 0 . 5 5
V if InAlAs is the Schottky contact layer,
V - 0 .6 5 V )
to Vgs = V p inchoff. Note that if
the gate-source bias is driven more positively than Vgsmax, excessive forward gate current
will result and also the drain-source voltage will fall out of the linear amplification region.
In addition, if the gate-source bias falls below
V p inchoff>
the device will enter class AB
mode. Finally, if Vds is driven above BVds, significant reverse gate current will result and
the device may undergo catastrophic breakdown.
Thus, the load line shown in
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29
dcopt
opt
(a)
gs y gsmax
lax
Q point (class A)
vpinchoff W gs Vpinchoff)
BY.
knee
(b)
Fig. 2.13. (a) Simple biasing schematic for FET in class A mode of operation, (b)
Corresponding load line diagram.
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30
Fig. 2.13(b) does indeed represent the ideal class A biasing configuration for maximum
output power from this device.
The quiescent dc bias point, or Q point, for this device as shown in Fig. 2.13(b) is
the median point between I max and Ipinchoff as well as Vj^ee and B V ds. The peak amplitude
of the microwave output voltage is hence 0.5(BVds - Vknee) and the peak amplitude of the
microwave output current is 0.5(Imax - Ipinchoff)- An additional factor of 0.5 must be
present to compute the time average power since the output is sinusoidal (i.e., it is a linear
amplification of the input, which is assumed to be sinusoidal). Note also that because the
output voltage and current waveforms are 180° out of phase, the power factor is -1 (i.e.,
the reactive power is zero and the microwave power is being supplied by the transistor).
The maximum microwave output power of the FET in class A is, therefore, given by
Po max A
^ (B ^ d s
^jt/ieeXAnax
Ipinchoff )
(2.21)
It is apparent from (2.21) which quantities must be minimized or maximized in order to
obtain maximum microwave output power. While the maximum output power is an
important quantity, it provides no information about the gain of the device. It is possible to
imagine a circuit configuration which provides high output power simply by combining the
outputs of a large number of low-power devices. Therefore, a more significant quantity is
the power added efficiency (PAE), defined as
PAE
P
-P
= °"f- - 1,1
(2 .22 )
where Pout, Pin. and Pdc are the output microwave power, input microwave power, and dc
input power, respectively. By making use of the available microwave gain of the device
Ga, the PAE can be rewritten as
=D E (1~ )
(2.23)
with the drain efficiency DE defined as
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31
DE = ^SHL
(2.24)
Pdc
The maximum PAE of the device is obtained when the gain of the device is very
large, in which case the PAE approaches the drain efficiency given by (2.24). Maximizing
the output power capabilities of the device is indeed beneficial, because this in turn
maximizes the obtainable PAE of the device.
In an ideal device, Vknee ~ Ipinchoff *” 0 can be been assumed. In class A operation
with the bias configuration of Fig. 2.13(a), the dc bias point is, therefore, at
Vds = 0.5(BVds), at which a drain current of 0.5(Imax) flows (Fig. 2.13(b)). It can be
seen that the dc input power in Class A is given by
(2-25)
4
It is, therefore, possible to calculate the maximum PAE obtainable for class A operation:
A=« W
/I =
^dcA
\ = 50%
1
(2.26)
where (2.21), (2.25) and (2.26) have been used with Vknee = Ipinchoff = 0- The upper
efficiency limit for class A mode is, therefore, 50%.
The output voltage and output current waveforms for class B operation are shown
in Fig. 2.14. Again, the ideal condition of Vknee ~ Ipinchoff ~ 0 has been assumed. The
microwave components of these waveforms are essentially sinusoids with amplitudes of
BVds and Imax> respectively, but are clamped to zero for precisely one-half of the cycle.
It
can be seen that the maximum time-average microwave output power produced by the
device will be precisely one-half of the power that would be produced by the corresponding
unclipped sinusoidal waveforms; i.e.,
^omaxfl = 2 X ^undipped ~ ^ x ^ ( ^ V ^ ) ( /max) = ~ (5 V ^ )(/max)
(2.27)
The dc power supplied to the device is slightly more complicated to determine. The
clearest way to find this quantity is to calculate the total time-average power at the output of
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32
ds
T im e
(a)
max
T im e
(b)
Fig. 2.14. (a) Output voltage and (b) output current waveforms of optimally biased FET in
class B mode of operation.
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33
the device, realizing that this represents a combination of the dc power being consumed by
the FET and the microwave output power being supplied by it. Referring to Fig. 2.14, it is
apparent that
1 T [2
PtotalB ~
2 k
2 k
- J lBVds - BVds sin(— r)] [/max sin(-^-/)] d!
to ta lB
K
(BVdsX/max)
4
(^^faXAnax)~ ^dcB
maxB
(2.29)
On the right side of (2.29) the total power has been broken into its two components. The
calculation of the maximum PAE is now straightforward:
PAEmMS = DEm„ B =
= i f l = - - 78.5%
P ic B
II*
4
(2.30)
The upper efficiency limit for class B operation is, therefore, 78.5%.
Based on this discussion, a list of design goals for microwave high-power HFETs
can be compiled. First, the gain should be maximized at high frequencies. Figures-ofmerit for determining the gain of HFETs will be discussed in Chapter 3. Second, the offstate drain-source breakdown voltage should be maximized and the knee voltage minimized
to allow for a large output voltage swing. Third, the device should have a large output
current swing, with the largest possible full-channel current and the smallest possible
current at pinchoff. In practice, simultaneously optimizing the device in all three of these
areas can be quite challenging, since in reality there are usually trade-offs involved.
2 .3 .2 .
C ritic a l issues in ach iev in g design goals
The above design goal summary, as well as the available data in recent literature,
reveals the strengths and weaknesses of InP-based HFETs in relation to high-power
microwave applications.
In particular, significant work has been done with
InGaAs/InAlAs MODFETs. The relatively high conduction band discontinuity of ~0.52 eV
at the InAlAs/InGaAs interface allows extremely high channel carrier sheet concentrations
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34
to be obtained, often as high as 3 x 1012 cm-2 at 300 K [2.12]. This allows greater charge
modulation capabilities and, hence, transconductances which can exceed 1000 mS/ram for
gate lengths on the order of 0.15 pm [2.13]. Superior electron transport properties of
InGaAs, including low electron effective mass and large T-L valley separation, allow high
carrier velocities in the channel to be obtained [2.14]. Because of the high carrier velocities
and concentrations, full-channel current densities over 700 mA/mm are quite common for
InGaAs channel MODFETs [2.15]. The high mobility of InGaAs [2.16] lowers the
parasitic access resistances, and this, in combination with the extremely good charge
modulation properties, would be expected to result in extremely good high-frequency gain
characteristics [2.17] and [2.18]. The experimental results confirm this notion; for
example, an f t of 250 GHz was obtained for an 80 nm InGaAs/InAlAs MODFET [2.19].
By increasing the channel InAs mole fraction, it is possible to enhance all of the above
characteristics. Currently, the best three-terminal device gain characteristics at room
temperature have been obtained from a 50 nm pseudomorphic AlInAs/Gao.2lno.8As
MODFET, which yielded a transconductance of over 1700 mS/mm and an f t of 340 GHz
[2.20].
From this description of the current state-of-the-art InP-based MODFETs, it is
evident that the high frequency gain and the maximum channel current characteristics of
these devices are excellent The pinchoff current levels can in principle be kept sufficiently
low as long as the device is fabricated properly; for example, in the InGaAs/InAlAs
material system, the InGaAs channel cannot be made too thick, because the high number of
intrinsic carriers present in InGaAs must be depleted by the gate bias. This depletion is
difficult to accomplish with a submicron gate if the InGaAs material is too distant (i.e., it
would require such a large voltage that significant gate current would result before pinchoff
occurred). In addition, the buffer material must be semi-insulating. If these criteria can be
met, the pinchoff current should be of little concern. The knee voltage can also be kept
very low in InGaAs/InAlAs HFETs despite the high current levels due to the low values of
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35
drain and source resistances which can be obtained as well as the low resistance of the
channel itself when it is in the conducting state. When these three resistances are low, the
knee voltage is low as well.
The remaining design goal is to maximize the off-state drain-source breakdown
voltage BVds- Because the majority of the voltage drop occurs between the gate and the
drain under normal bias conditions, the phenomena limiting BVds is actually breakdown
between the gate and the drain, i.e., a low gate-drain breakdown voltage (BVgd). Both
BVgd and BVds are usually defined as the voltage at which a drain current of 1 mA per mm
of channel width is obtained. For most devices with good pinchoff characteristics, BVds is
roughly equal to the absolute value of BVgd plus the value of the gate-to-source pinchoff
voltage, since BVds is measured with a pinched-off channel. For example, in a device with
BVgd = - 4 V and a Vgs of -1 V to pinch off the channel, BVds would be roughly equal to
1-4 VI + (-1 V) = 3 V, since this is the off-state drain-source voltage corresponding to a
gate-drain bias of -4 V, at which point the device begins to break down.
The typically low values of BVds that presents a problem for InGaAs/InAlAs
HFETs. When the gate-drain bias is negative, electrons have some probability of tunneling
through the barrier layer and into the channel material [2.21] and [2.22]. When this
occurs, the transferred electrons have excess energy and are further accelerated by the highfield domain at the edge of the channel on the drain side (Fig. 2.11), which leads to impact
ionization and eventually avalanche breakdown [2.23] and [2.24]. Techniques for
suppressing this breakdown mechanism in InP-based HFETs will be discussed in
Chapter 5.
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36
2 .4 .
R eferen ces
[2.1]
D. Delagebeaudeuf and N. T. Linh, "Metal-(n)AlGaAs-GaAs two dimensional
electron gas FET," IEEE Trans. Electron Devices, vol. ED-29, pp. 955-960,1982.
[2.2]
M. Shur, GaAs Devices and Circuits. New York: Plenum, 1987, pp. 513-610:
[2.3]
P. Saunier, R. Nguyen, L. Messick, and M. Khatibzadeh, "An InP MISFET with a
power density of 1.8 W/mm at 30 GHz," IEEE Electron Device Lett., vol. 11, pp.
48-49, 1990.
[2.4]
J. Huang, T. Chang, and B. Lalevic, "Measurement of the conduction-band
discontinuity in pseudomorphic InxG ai-xAs/Ino.52Alo.48As heterostructures,"
Appl. Phys. Lett., vol. 60, pp. 733-735, 1992.
[2.5]
S. Nakajima, M. Murata, N. Shiga, H. Hayashi, and M. Inoue, "High electron
mobility in modulation-doped /i-AlInAs/InP heterostructures grown by low
pressure organometallic vapor phase epitaxy," Appl. Phys. Lett., vol. 59, pp.
1606-1607, 1991.
[2.6]
K. Lee, M. Shur, T. Drummond, and H. Morcoc, "Parasitic MESFET in (Al,Ga)
As/GaAs modulation doped FETs and MODFET characterization," IEEE Trans.
Electron Devices, vol. 31, pp. 29-35,1984.
[2.7]
D. Delagebeaudeuf and N. Linh, "Charge control of the heterojunction twodimensional electron gas for MESFET application," IEEE Trans. Electron Devices,
vol. 28, pp. 790-795, 1981.
[2.8]
K. Lee, M. Shur, T. Drummond, and H. Morcoc, "Current-voltage and capacitance
voltage characteristics of modulation-doped field effect transistors," IEEE Trans.
Electron Devices, vol. 30, pp. 207-212,1983.
[2.9]
R. Muller and T. Kamins, Device Electronics fo r Integrated Circuits, 2nd ed. New
York:Wiley, 1986, pp. 422-474.
[2.10] Y. Awano, "New transverse-domain formation mechanism in a quarter-micrometregate HEMT," Electron. Lett., vol. 24, pp. 1315-1317,1988.
[2.11] Y. Awano, M. Kosugi, K. Kosemura, T. Mimura, and M. Abe, "Short-channel
effects in subquarter-micrometer-gate HEMT's: simulation and experiment," IEEE
Trans. Electron Devices, vol. 36, pp. 2260-2265,1989.
[2.12] M. Tong, K. Nummila, A. Ketterson, I. Adesida, L. Aina, and M. Mattingly,
"OMVPE-grown InAlAs/InGaAs/InP MODFETs with performance comparable to
those grown by MBE," IEEE Trans. Electron Devices, vol. 39, pp. 2411-2413,
1992.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
37
[2.14] R. Lai, P. Bhattacharya, D. Yang, T. Brock, S. Alterovitz, and A. Downey,
"Characteristics of 0.8- and 0.2-jim gate length InxGai_xAs/Ino.52Alo.48As/InP
(0.53 < x £ 0.70) modulation-doped field-effect transistors at cryogenic
temperatures," IEEE Trans. Electron Devices, vol. 39, pp. 2208-2213,1992.
[2.15] M. Matloubian, A. Brown, L. Nguyen, M. Melendes, L. Larson, M. Delaney, M.
Thompson, R. Rhodes, and J. Pence, "20 GHz high-efficiency AlInAs-GalnAs on
InP power HEMT," IEEE Microwave Guided Wave Lett., vol. 3, pp. 142-144,
1993.
[2.16] E. Toumi6, L. Tapfer, T. Bever, and K. Ploog, "Structural properties and transport
characteristics of pseudomorphic GaxIni_xAs/AlyI n i.yAs modulation-doped
heterostructures grown by molecular-beam epitaxy," J. Appl. Phys., vol. 71, pp.
1790-1797, 1992.
[2.17] M. Foisy, P. Tasker, B. Hughes, and L. Eastman, "The role of inefficient charge
modulation in limiting the current-gain cutoff frequency of the MODFET," IEEE
Trans. Electron Devices, vol. 35, pp. 871-878,1988.
[2.18] P. Tasker and B. Hughes, "Importance of source and drain resistance to the
maximum f t of millimeter-wave MODFETs," IEEE Trans. Electron Devices, vol.
10, pp. 291-293, 1989.
[2.19] L. Nguyen, L. Jelloian, M. Thompson, and M. Lui, "Fabrication of an 80 nm self­
aligned T-gate AlInAs/GalnAs HEMT," IEDM Tech. Dig., pp. 101-104,1990.
[2.20] L. Nguyen, A. Brown, M. Thompson, and L. Jelloian, "50-nm self-aligned-gate
pseudomorphic AlInAs/GalnAs high electron mobility transistor," IEEE Trans.
Electron Devices, vol.39, pp. 2007-2013,1992.
[2.21] M. Kamada, H. Ishikawa, and M. Feng, "Gate current in AlInAs/GalnAs
heterostructure insulated-gate field-effect transistors (HIGFETs)," IEEE Trans.
Electron Devices, vol. 40, pp. 1358-1363,1993.
[2.22] R. Trew and U. Mishra, "Gate breakdown in MESFET’s and HEMT’s," IE E E
Electron Device Lett., vol. 12, pp. 524-526,1991.
[2.23] D. Newson, R. Merrett, and B. Ridley, "Control of gate leakage in InAlAs/InGaAs
HEMTs," Electron. Lett., vol. 27, pp. 1592-1593,1991.
[2.24] A. Moolji, S. Bahl, and J. del Alamo, "Impact ionization in InAlAs/InGaAs
HFET's," IEEE Electron Device Lett., vol. 15, pp. 313-315, 1994.
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38
CHAPTER 3.
3 .1 .
MEASUREMENT STANDARDS AND TECHNIQUES
In tro d u c tio n
Designing, fabricating, and characterizing HFETs for high-power microwave
performance not only requires an understanding of the principles involving device physics
which were presented in Chapter 2, but also efficient, accurate, and precise ways of
measuring the devices to assess their capabilities. In addition, the conventions used when
defining certain figures-of-merit must be known. This chapter addresses these issues,
beginning with small signal measurement and characterization, involving the determination
of the high-frequency 5-parameters of an HFET, and concluding with large-signal
measurement and characterization at dc and high frequencies.
3 .2 .
S m all-sig n al M e a su re m e n ts
Much insight into an HFET's capabilities at high frequencies can be learned by
performing microwave 5-parameter measurements on the device. Such measurements
require accurate calibration of the test equipment, but when completed can be used to model
the device and determine certain figures-of-merit which are essential to predicting its
microwave performance for not only small-signal amplification but also large-signal
amplification. In this section, a useful calibration technique will first be presented,
followed by small-signal models and definitions used for device characterization.
3 . 2 . 1 . C a lib ra tio n u sin g th e L R R M te ch n iq u e
3.2.1.1.
Background of calibration techniques
Because on-wafer probing equipment is constantly being designed for use at higher
frequencies, there is an increasing need for accurate vector network analyzer calibration
techniques at these frequencies. The most dominant technique used has probably been the
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39
short-open-load-thru (SOLT). The advantages of this technique include simplicity of error
term calculation and the fact that this calibration routine is often found in the standard builtin functions of most modem network analyzers. However, this technique must have the
impedances of all four standards accurately defined, which presents complications. In
particular, the open standard is extremely difficult to define at high frequencies, and the
parasitic reactance of the coplanar resistor used for the load standard depends on how the
resistor is probed.
An improvement over the SOLT calibration technique is the thru-reflect-line (TRL)
technique, which uses a length of transmission line with a certain characteristic impedance
to define the reference impedance. Originally, bandwidth limitations required that multiple
lengths of line be used to cover a large frequency range, but improvements have been made
to eliminate this drawback, in addition to the requirement of a precise specification of line
length [3.1]. However, the TRL technique still has the disadvantage of ignoring the
inherent dispersion in coplanar waveguide transmission lines, which ultimately yields a
reference impedance that depends on frequency.
Recently introduced was the line-reflect-match (LRM) [3.2] and [3.3], which uses a
match instead of a section of transmission line to define the reference impedance. The
impedance of the reflect standard is never specified, and the line standard can be a zero or
near-zero length thru. The only difficulty that arises is the definition of the match standard.
Davidson et al. have devised a model for a coplanar match standard measured with a
microwave probe tip having the standard ground-signal-ground (GSG) configuration [3.3]
and [3.4]. This model agrees well with experimental data and consists simply of a
frequency independent resistance (e.g., a 50 Q resistor for a nominal 50 Q standard) in
series with a frequency independent inductance. Depending on the probe tip overlap when
the standard is probed, the inductance can have a negative or positive value and takes into
account both the physical series inductance of the standard and the small effective shunt
capacitance arising from excessive overlap [3.3].
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40
Although the enror terms calculated with the LRM method may be corrected to take
into account the load inductance, this inductance can be determined only if it is assumed
that it is identical for both the port 1 and port 2 measurements. This assumption is correct
only if the match standard is probed with exactly the same overlap for both measurements,
which in practice is difficult. For this reason, a variation of LRM was developed [3.4],
known as line-reflect-reflect-match (LRRM). The LRRM method uses two reflect
standards on each port but a match standard on only one port, in contrast to the LRM
method which uses one reflect standard and one match standard on each port. As with the
LRM reflect standard, the two LRRM reflect standards do not have to be defined, but for
best results they should have reflection coefficients that are large and widely separated on
the Smith chart. Usually, a nonideal short and a nonideal open are chosen as the two
reflect standards. The LRRM match inductance can be determined in exactly the same
manner as the LRM match inductance is calculated. The main advantage of LRRM over
LRM is that the LRRM match inductance applies only to a single standard measured on one
port, whereas the LRM match inductance must be assumed to be the same for both port
measurements.
Davidson et al. [3.4] have given a partial explanation of automatic match inductance
determination for both the LRM and LRRM methods. However, no mention is made of the
specific calculations involved when error terms are calculated using the LRRM technique or
the way in which the load inductance can be used to correct the error terms. In addition,
there seems to be a complete absence of a mathematical treatment of the LRRM method
elsewhere in the literature. Barr and Pervere [3.5] and Silvonnen [3.6] have devised
general algorithms for performing the calculations necessary for most calibration
techniques, but application of these algorithms has been primarily to techniques with three
calibration standards. Because the LRRM method involves four standards, the application
of their algorithms to this method is not obvious, especially since the match measurement is
performed on only one port and, hence, introduces an inconvenient asymmetry.
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41
In this section, the specific calculations involved in the LRRM calibration method
will be addressed, including device parameter de-embedding and error term calculation.
Moreover, a detailed description of the determination of the match inductance will be given.
Finally, results from an actual LRRM calibration will be presented to illustrate the impact of
a nonzero match inductance and the result of correcting for this inductance.
3.2.1.2.
Error models and de-embedding
Figure 3.1(a) shows the assumed flowgraph of the overall measurement setup, with
the Aij error terms representing the input measurement error and the Bij error terms
representing the output measurement error. Although there seem to be eight unknowns
corresponding to the eight error terms, it will be shown that there are actually only seven
terms that have to be known to de-embed the s-parameters of the device under test (DUT).
The requirement of only seven terms is a result of the fact that the information required of
the DUT is always a ratio bi/aj. Figure 3.1(b) shows the corresponding block diagram of
the system. The two error term matrices may be calculated in conventional 5-parameter
[S]a and [S]b, after which they can be converted to a cascadable AT-parameter
format, [K]aand [K]b, where the AT-parameter matrix is defined by
format,
U J - k
jrJL J
(31)
The Af-matrices may be cascaded by simple multiplication and may be calculated
from 5-parameters using the following relation:
where
1 f 1 ~ s22
[K] = —
S21 VJI1 ~ A s.
(3.2)
Ar = sn s2z ~ si252i
(3.3)
[K]a and [K]b are known, the device parameters may be de-embedded from the
measured A'-parameters, [K]m
eas, by way of the following equation:
Once
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Input errors
I
Device-under-test
Output errors
\
(a)
[B]
[A]
(b)
Fig. 3.1. (a) Flow diagram and (b) block diagram displaying the assumed
measurement error model used in the LRRM calibration routine.
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43
[K]DUT=([K]a)-![K]meas(Mb)"1
(3.4)
After using (3.2) and carrying out the matrix inversions, (3.4) becomes
[K]Dut
a
Bm
eas |I - * nA
_ c»»*»
*22
s 22
V*ll
*12 5X2 *21
-As™
BA
—As
*22
<~ sn
1
(3.5)
from which it can be seen that there are indeed only seven quantities that must be found for
•
AA BB AB BB
AA
de-embedding: Sn, s22 , *n> *22* *12*12* *12*21*an(i *12*21- For simplicity, these terms
will be denoted A n , A22, B n , B22, A 12B12, B 12B21, and A 12A21, respectively, which is
in accordance with Fig. 3.1(a). In other words, it should be assumed that the error terms
are in 5-parameter format unless specified otherwise. Since de-embedding does not require
that the terms A 12, A21, B 12, and B21 be found individually, one of these terms can be set
to unity with no loss of generality, which makes it possible to express [A] and [B] as
individual matrices.
Finally, once [K]dut has been found, [S]dut may be calculated using
[s]dut—K„1d1ut
3.2.1.3.
DUT^
UT
-K , D
kT
ak
1
12
(3.6)
y
Measurement of standards
Line (thru) standard. Here a zero length thru will be assumed for the line standard.
Theoretically, a nonzero length of transmission line could be used but this would introduce
additional error when the load inductance is calculated, as will be shown. Figure 3.2(a)
shows the resulting flow diagram for the thru measurement. Straightforward analysis
yields the following four relations for the measured 5-parameters:
T_ *1 I
mn =
* .
T
"
al
T
I
3
A ”
=
Bn A12A 2i
+
1_ A
___
B
1 a 22b 11
Ai2Bi2
73
^
0 .8)
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44
(a)
(b)
Fig. 3.2. Flow diagrams for (a) thru standard and (b) reflect standard measurements.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Reflect 1 (open): An appropriate choice for the open reflect standard is simply a
measurement with both probes in the air. Figure 3.2(b) shows the corresponding flow
diagram. At this point, nothing about the open probe impedances is specified. However,
the assumption is made that the two open probe impedances are equal. Analysis of
Fig. 3.2(b) produces the following relations:
<
> A„ +
(3.11)
1-
a
22i r o
„RO _ r,
. r ROB12B21
22 - B22 + V p r.
(3.12)
1 ~ ^ll1 RO
Equations (3.11) and (3.12) may be both be solved for Tro and the resulting expressions
set equal to each other, which provides the equation
wn ° ~ ^ n
^ 2 2 * —B 22
_ A12A2i + A.22(mn° ~ An )
®12®21
®11 (w 22? ~ ®22)
Reflect 2 (short): The analysis of the short reflect measurement is precisely the
same as the open reflect measurement analysis. Once again, the impedance of the standard
is not specifiedbut assumed to be the same for both port measurements.The resulting
expression fromthe short reflect measurement analysis is similar in form to (3.13):
~ ^ 1 1 _ A12A2i + A 22(/?ffi - An )
m 22 ~ ® 2 2
®12®21 + ® l l ( m 22S —^ 22 )
Match: As was mentioned previously, the match standard is measured on only one
p o rt In this analysis, it will be assumed that the measurement is made on port 1, although
it could just as easily be made on port 2. As was revealed at the beginning of this section, a
nominal 50 Q match standard has, in general, an input impedance of (50 + jcoLmatch) ^
when measured with a probe tip having the GSG configuration. At this point, Lmafchis not
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46
known; however, note that the reference impedance of the DUT has not yet been defined.
It is advantageous, therefore, to initially define the DUT reference impedance to be
(50 + jtoLmatch) & which forces the reflection coefficient of the match standard, r match, to
be zero. The analysis of the match measurement is then trivial and immediately produces
mn = An
3.2.1.4.
(3.15)
Initial calculation of error terms
Once the measurements of the standards have been performed, the error terms may
be calculated. Equations (3.7)-(3.10) and (3.13)-(3.15) may be rearranged to give
( ^ T2 - B 22)(WiT1 - ^ )
mnT m2TX
mn ~ m n
RS n
f Bn]
<A22, \ m22 ~°22
_ (m/i
A T.
-_ A22iJn
(3.16)
RS
)(1 ~ A 22Bn ) + A22Bn (mff* —
( m 22 ~ ^ 22 ) 0 ~
^
22^ 11) +
)
A22Bij(»J^ —B 22 )
( T> ^ ( mnRO - m uM A _ (^ n ~
)(1 ~ A22B) 1 ) + A22B ,| ( mR O^ —.Mi)
RO p
(ffjJ2 —B22)(l —A 22B11) + A22B11(w^P —B22)
<A 22> \ m22 ~ a 21J
(3.17)
(3.18)
The above expressions may be treated as a system of three equations and three unknowns
where the unknowns are B 11/A22, A22B 11, and B22. These quantities may be found
numerically, after which all of the error terms of the [A] and [B] matrices may be readily
found.
3.2.1.5.
Load inductance determination
The error terms calculated in Section 3.2.1.4 assumed a DUT reference impedance
of (50 + jcoLmaich) O. The value of Lmatch may now be determined by calculating the open
probe admittance with these error terms and assuming that the real part of this admittance is
zero. Davidson et al. [3.4] have verified this assumption for frequencies as high as
40 GHz and have found it to be accurate.
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47
The reflection coefficient of the open standard may be found by rearranging (3.11):
•p
_
_ A
_________ "»*i1RO
1
_________
lR 0 _ A n A 2 l+ A v ( m ? ° - A u )
.
(3' 19)
where all quantities on the right side of (3.19) are known from the initial error term
calculations. The open probe admittance is given by
=
-1
Z„
"ref
I i-Tro_
Ji+Fro
f
1 1(/ t + j •u )\
►-n
open
aN
Y
t +ju
= — -----— ------50 + j(oLmatch
(3.20)
Note that t and u are known quantities. By making use of the fact that Y 0pen = j Bopen,
i e., Y open is purely imaginary, Lmatch can be found by solving the real and imaginary parts
of (3.20) separately. The resulting expression is
^ match
-t
-5 0 1
—
=
C0Bopcn
03U
(3.21)
The match inductance may, therefore, be calculated separately at each frequency and an
average value found. It may be desirable to weigh this average less heavily at the lower
frequencies, since the open probe admittance is quite small at these frequencies. Some
experimentation can be used to determine what weighting scheme gives the best results.
At this point, it should be noted that if a length of transmission line is used in place
of a thru, there will technically be a small error when the load inductance is calculated,
since a transmission line has a characteristic impedance which in general will not be equal
to (50 + jcoLmatch) £2- The error arises due to an inconsistent definition of the DUT
reference impedance. Since Lmatch is not initially known and is dependent on the manner
in which the match standard is probed, it is virtually impossible to define the scattering
parameters of the transmission line referenced to the match impedance. This problem does
not arise with the thru standard, since an ideal thru does not have a characteristic impedance
associated with it.
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48
3.2.1.6.
Correction of error terms for load inductance
Once the load inductance is known, it is desirable to find the new error terms with a
DUT reference impedance of 50 £2 rather than (50 + jcoLmatch) Q- This would make it
possible to load the error terms into the network analyzer and immediately obtain the 50 £2
S-parameters of the DUT, as is conventional. The only straightforward way to change this
reference impedance without changing the definition of the thru standard, which is known
to have the same S-parameters regardless of reference impedance, is to find Tmatch at each
frequency based on the value of Lmatch and perform the LRRM calculation sequence again
using this nonzero value of Tmatch. Equation (3.15) now becomes
An =
mn
~
-f ™ f > 2A21
1
A 2 2 I match
(3.22)
An initial guess for the new value for A n may be found using (3.22) and the old values of
A 12, A21, and A22 found above. It is then possible to solve (3.16)-(3.18) as before,
except that
must now be replaced with A n in these three expressions. Once all of the
other error terms have been found, it is then necessary to compute a new value for A n by
using the new values of A 12, A21, and A22 in (3.22). If the new value of A n is
significantly different from the initial guess for A n . iteration is necessary until a consistent
value of A n is determined. All load inductances obtained in the actual application of this
calibration method were less than 20 pH in magnitude, and for these inductance values no
iteration was necessary; i.e., the initial guess of A n using the old error terms in (3.22) and
the value of A n calculated using the new, corrected error terms in (3.22) were within
0.05% of each other.
3.2.1.7.
LRRM calibration results
The LRRM calibration routine described was used to calibrate an on-wafer Sparameter measurement setup using Cascade Microtech probes. Calibration was performed
using the short, thru, and match standards on a sapphire impedance standard substrate
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49
(ISS). The match standard was intentionally probed with excessive overlap to obtain a
significantly negative value for the match inductance. The probes were left in the air for the
open reflect measurement. The calibration was performed over a frequency range of 1 to
35 GHz and the match inductance was determined to be -14.8 pH. Figure 3.3(a) shows
the value of the match reactance versus frequency determined after de-embedding the 5parameters of the match from the external 5-parameters of the calibration match
measurement. Before the error terms were corrected for load inductance, the match
reactance was zero, and after match inductance correction, the match reactance decreased
linearly with frequency, verifying that the error terms were successfully corrected for the
match inductance. Figure 3.3(b) is a plot of the de-embedded value of the open probe
conductance versus frequency. The conductance was calculated from the open reflect
measurement. Before match inductance correction, the open-probe conductance was non­
zero since the match impedance was improperly defined. As can be seen, the match
inductance correction brought the open probe conductance back to zero, once again
verifying that the error term correction was successful.
3 . 2 . 2 . S m all-sig n al m odel
Once the measurements of a device have been determined, these data can be applied
to a small-signal model. The most widely used and perhaps the most physically accurate
model used for HFETs is shown in Fig. 3.4 and is taken from [3.7]. To extract the circuit
element values from the measured 5-parameters of the device, the effects of the external
pad capacitances are first stripped from the measurements using measured 5-parameters of
dummy FETs which contain only pads, but no gates or active mesa regions.
Once the pad parasitics have been stripped from the measurements, the gate, drain,
and source parasitic inductances and resistances are determined in order that these can also
be removed. These parasitics are assumed to be bias-independent and can be found using
one of several techniques, including fitting the measured 5-parameters versus frequency at
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50
0.5
0
-0.5
without inductance correction ”
-1
match=-14-8 PH
a -1.5
•2
-2.5
with inductance correction
3
-3.5
0
5
10
15
20
25
Frequency (GHz)
30
35
30
35
(a)
0.0001
with inductance correction
0
■without inductance correction
-0.0003
0
5
10
15
20
25
Frequency (GHz)
(b)
Fig. 3.3. (a) Match reactance and (b) open probe conductance
versus frequency calculated with and without correction for the
match inductance.
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51
gdpad
gate
gspad
Intrinsic
source
Fig. 3.4. Small-signal model of an HFET.
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52
a single bias point [3.8] or by performing high-frequency measurements when the device is
under extreme bias conditions [3.9]. In addition, when the gate is in the center of the
drain-source gap, the source and drain resistances may be readily found using either gated
TLM measurements [3.10] or by measuring the slope of the HFET drain I-V characteristics
at low drain biases (e.g., in the range of 0 -100 mV). At such low biases, it can be shown
that the device behaves like a resistor, made up of the drain, source, and channel
resistances in series [3.11].
Once the intrinsic 5-parameters of the device have been de-embedded from the
parasitics, the values for all of the intrinsic circuit model elements in Fig. 3.4 may be
calculated directly [3.7]. In Chapter 5, the values of the small-circuit model elements will
be extracted for real HFETs using this technique in order to better understand their
behavior.
Finally, two figures-of-merit are often quoted for FETs to indicate the upper limit
on their operating frequency. The first is f f , the unity short-circuit current gain frequency,
which is the frequency at which the hybrid parameter h2i has decreased to a value of unity
[3.12]. The second i s / max» the frequency at which the maximum unilateral gain, the
maximum stable gain, and the maximum available gain are all equal to unity [3.13] and
[3.14]. In practice, the parameter h2i of most HFETs has a steady rolloff of 20 dB/decade,
and, by linear extrapolation, the determination of f f is straightforward. Furthermore, the
analytical expression for f f can be used once the values of the circuit model elements in
Fig. 3.4 are known [3.15]:
/ r = — rr----------- Tv----------- — ----- i----------------------- T
^
+ Cgdj [ l+ {^s + ^ d )#ds]+ ^gdSmi^s + ^ d )j
(3.23)
The value o f/max is usually more difficult to obtain. If the stability factor K of the
device is greater than about two, the maximum available gain can be assumed to have a
steady roll-off of 20 dB/decade [3.7], and f max can be extrapolated from this trace.
However, if K is smaller than this value, this assumption cannot be made; furthermore, if
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53
K < 1, as is most common with microwave HFETs, the device is potentially unstable, and
the maximum available gain cannot be defined [3.16]. Therefore, the maximum stable gain
or the maximum unilateral gain are often extrapolated to obtain a value fo r/max [3.17] and
[3.18]. However, due to the fact that the roll-off slopes of these traces are usually not
constant, and the traces are on a logarithmic scale, the estimated value of /max varies
drastically with the extrapolation technique used. Therefore, perhaps the most consistent
technique is calculating the theoretical value o f/max using the circuit model element values,
as is done in [3.7]:
/m“ = i/4W%»(1 + F)
<3' 24)
with
f _ 2 n fTLs [ 4 n fTCgd
Rin
! , Rg , r f T Ls
Sds
f
(3.25)
Rin
im
2 n(Cgs+Cgd)
(3.26)
= Rg + Rs + Rgs
(3-27)
„
Rin
Rin
The significance o f f max for power HFETs is that the maximum unilateral gain of a
device is greater than one for frequencies less than /max. which means that the device is
active at these frequencies [3.13]. Therefore, power gain would definitely not be expected
for frequencies above this value. For power applications, the significance of f y is in its
relationship to /max- It is relatively easy to show that
r,
max
I h
\2
Rout
(3.28)
4 Rin
where Rout and Rjn are on the order of the output and input resistances of the device,
respectively, for small high-frequency input signals and with the device at the dc bias point
of interest. The relationship (3.28) has two significant implications. First, a s / r increases,
/max also tends to increase, which implies that the former figure-of-merit is a quick way to
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54
compare the predicted power performances of various HFETs, since it is an easy quantity
to determine. Second, for practical applications involving amplifiers with cascaded gain
stages, the value of / max should not be much greater than 2fy, since this makes it very
difficult to match the output impedance of one stage to the input impedance of the next
stage. Therefore, both high-frequency figures-of-merit are valuable for predicting the
usefulness of an HFET at microwave frequencies.
3 .3 .
3 .3 .1 .
L a rg e -sig n a l M easu rem e n ts
D irect c u r r e n t fig u res-o f-m erit
The common dc figures-of-merit of HFETs were mentioned at the end of
Chapter 2. First, the full-channel current for HFETs is often defined as the saturation
current at which the forward gate bias at which significant gate current begins to flow; for
an InAlAs Schottky layer, this value is usually around 0.4 V.
Second, the pinchoff current is usually defined as the minimum current obtainable
in the device with a drain-source bias which is the same as that used for the measurement of
the maximum transconductance.
Third, the drain-source breakdown voltage, BV(js, is determined by finding the
drain-source voltage at which the drain current is equal to 1 mA per mm of channel width
when the device is fully pinched off. In practice, this value should be maximized by trying
different gate biases. For example, if the gate bias is not negative enough, the channel will
not be fully pinched off and the measured value of BVdS will be too low. Conversely, if
the gate bias is made too negative, the gate-drain voltage will be significant even at low
drain biases, and 1 mA/mm will result at a low bias due to breakdown between the gate and
the drain. It is apparent that for a center-fed gate, double source-pad design which is
common for microwave FETs with channel widths less than about 200 pm, the fu ll device
should be measured rather than just one-half of the device, since the gate-drain leakage
current will flow in both halves of the device (see Fig. 3.5).
For example, in a
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55
^drain>®
Source
ourci
Gate-drain leakage current
Fig. 3.5. Diagram of a typical center-fed, double-source pad layout of
an HFET illustrating how gate-to-drain leakage occurs in both halves of
the device.
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56
2 x 50 fim device, if only half of the device is used to determine BVds, a current level of
1 mA/mm theoretically corresponds to 50 |iA flowing in the right half of the device.
However, the actual drain current measured will also include the gate-drain leakage current
flowing in the left half of the device, and the measured value of BVds will be too low. This
can be a common error.
Finally, the determination of the gate-drain breakdown voltage, BVgd, is
accomplished by a two-terminal measurement with the source floating and is defined as the
voltage at which the magnitude of the gate current reaches 1 mA/mm, where again the
width used to normalize the current is the full width of the device.
3 . 3 . 2 . M icrow ave p ow er m easu rem en ts
Figure 3.6 is a schematic of a typical setup for on-wafer power measurements at
microwave frequencies. Although at the input stage it may seem self-defeating to put an
attenuator at the output of the microwave power source, followed by a power amplifier,
possibly followed by another attenuator, this design actually provides more flexibility for
range of input powers supplied to the device. The power amplifier is often necessary
because of significant loss in the measurement setup. However, the available power range
of the microwave power source will not in general be perfectly compatible with the input
capabilities of the amplifier; hence, an attenuator is often required between the two
instruments to avoid saturating the amplifier. Each device has a characteristic range of
input powers which is optimal; because the power supply has a limited range, another
attenuator may be required to obtain the desired range of input powers. After this, an
isolator is placed in the line to allow power flow only in the forward direction and, hence,
avoid standing wave patterns which might destroy the equipment The isolator typically
has a frequency bandwidth which is narrower than that of the power source and amplifier.
After the isolator, a bias tee is placed in the line in order that the microwave and dc
biases may both be coupled into the device under test but will remain isolated from each
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57
Microwave
Power Source
Power Meter
Attenuator
vV v
Power Amplifier
dc bias
(gate)
(Attenuator)
Isolator
(Device under test)
Tuner
Tuner
Bias Tee
Isolator
A *
r~ P ~ i
Bias Tee
Microwave
Probes
DC bias
(drain)
Fig. 3.6. Schematic of a typical instrument setup for on-wafer microwave
power measurements.
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58
other. Next in line is a microwave tuner for matching the input of the device to the
characteristic impedance of the setup, which is most often 50 £2. This is followed by the
input and output microwave probes for measuring devices with the standard GSG coplanar
waveguide configuration. The output microwave probe is followed by another tuner to
transform the 50 £2 impedance of the system into the optimal load for the device under test,
followed by the output bias tee, another isolator, and a microwave power meter. When
measuring devices with large enough output powers to saturate the power meter, an
attenuator is placed directly in front of the power meter and must be accounted for when the
calibration is performed.
The calibration routine for on-wafer power measurements is much simpler than the
routine for small-signal 5-parameter measurements. First, the setup is disconnected at
points A and B in Fig. 3.6, and the power meter is connected directly to the output of the
power amplifier (or the attenuator at the output of the power amplifier, if one is present).
The power source is then swept to determine what actual power level will be supplied at
point A for a given level of the power source. Second, the setup is reconnected in the
standard fashion and a thru calibration standard is probed. The same power levels are
swept on the power source as were swept in the first step, and the new power readings of
the meter are stored. Finally, the second power readings are subtracted from the first
power readings to determine the total loss in the equipment between points A and B. By
symmetry, the loss between point A and the thru, i.e., the input loss, can be assumed to be
the same as the power loss between the thru and point B, i.e., the output loss. In this way,
for a given level from the power meter, the actual input power to the device can be
calculated by subtracting the input loss from the external input power, and for a given
reading on the power meter, the actual output power from the device may be determined by
adding the output loss to the power reading.
In practice, on-wafer power measurements of an HFET are extremely timeconsuming. First, because the calibration values and tuner positions are valid only at one
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59
frequency, measurements must be performed at only one frequency. In addition, the
device should be biased at several different combinations of drain and gate biases to
discover the optimal bias condition for the device and/or determine the effect of dc bias on
the performance of the device. If it is determined that the input power range being used is
not suitable for the device, the power levels must be changed, which makes it necessary for
the setup to be recalibrated; in other words, the whole process must be repeated, and
iteration may be necessary. Probably the most difficult step, however, is adjusting the
input and output tuners to their optimal positions for each dc bias condition of the device.
In particular, if the optimal load resistance required by the device is much greater than
100 £2 for a 50 £2 system, matching will be extremely difficult with typical passive tuners.
If possible, more elaborate active tuners may be used to circumvent this problem.
However, if passive tuners are all that are available, as is often the case, the concepts
presented in Section 2.3.1 show that the ratio of BVds to
Imax
should not be much greater
than 100 £2, since this ratio is on the order of the optimal load resistance of the device. For
this reason, many layer structures require a rather large power device width, often in the
range of 500 |im to over 1 mm, in order to have a large enough
Imax
to pull down the
optimal load resistance to a value close to 100 £2.
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60
3.4.
[3.1]
R eferences
R. Pantoja, M. Howes, J. Richardson, and R. Pollard, "Improved calibration and
measurement of the scattering parameters of microwave integrated circuits," IEEE
Trans. Microwave Theory Tech., vol. MTT-37, pp. 1675-1680,1989.
[3.2] H-J. Eul and B. Schiek, "Thru-match-reflect: One result of a rigorous theory for
de-embedding and network analyzer calibration," in Proc. 18th European
Microwave Conf., pp. 909-914, 1988.
[3.3] A. Davidson, E. Strid, and K. Jones, "Achieving greater on-wafer S-parameter
accuracy with LRM calibration technique," IEEE Automatic RF Techniques GroupConference Digest, pp. 60-66,1989.
[3.4] A. Davidson, K. Jones, and E. Strid, "LRM and LRRM calibrations with automatic
determination of load inductance," Cascade Microtech Publication, 1991.
[3.5] J. Ban- and M. Pervere, "A generalized vector network analyzer calibration
technique," IEEE Automatic RF Techniques Group-Conference Digest, pp. 51-60,
1989.
[3.6] K. Silvonen, "A general approach to network analyzer calibration," IEEE Trans.
Microwave Theory Tech., vol. MTT-40, pp. 754-759, 1992.
[3.7] B. Hughes and P. Tasker, "Bias dependence of the MODFET intrinsic model
elements values at microwave frequencies," IEEE Trans. Electron Devices, vol. 36,
pp. 2267-2273, 1989.
[3.8] H. Kondoh, "An accurate FET modelling from measured S-parameters," in IEEE
Microwave Theory Tech. Symp. Dig., 1975, pp. 377-380.
[3.9] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, "A new method of
determining the FET small-signal equivalent circuit," IEEE Trans. Microwave
Theory Tech., vol. 36, pp. 1151-1159,1988.
[3.10] S. Baier, M. Shur, K. Lee, N. Cirillo, and S. Hanka, "FET characterization using
gated TLM structures," IEEE Trans. Electron Devices, pp. 1919-1928,1987. .
[3.11] D. Delagebeaudeuf and N. T. Linh, "Metal-(n)AlGaAs-GaAs two dimensional
electron gas FET," IEEE Trans. Electron Devices, vol. ED-29, pp. 955-960,1982.
[3.12] A. Sedra and K. Smith, Microelectronic Circuits, 2nd ed. New York-.HRW, 1987,
pp. 599-670.
[3.13] M. Gupta, "Power gain in feedback amplifiers, a classic revisited," IEEE Trans.
Microwave Theory Tech., vol. 40, pp. 864-879,1992.
[3.14] R. Spence, Linear Active Networks. London:Wiley, 1970, p. 215.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
61
[3.15] P. Tasker and B. Hughes, "Importance of source and drain resistance to the
maximum^- of millimeter-wave MODFET’s," IEEE Electron Device Lett., vol. 10,
pp. 291-293, 1989.
[3.16] G. Yendelin, A. Pavio, and U. Rohde, M icrowave Circuit D esign. New
York:Wiley, 1990, pp. 1-65.
[3.17] S. Bahl, B. Bennett, and J. del Alamo, "Doubly strained Ino.4iAlo.59As/n+Ino 65Gao 35As HFET with high breakdown voltage," IEEE Electron Device Lett.,
vol. 14, pp. 22-24, 1993.
[3.18] L. Nguyen, P. Tasker, D. Radulescu, and L. Eastman, "Characterization of ultrahigh-speed pseudomorphic AlGaAs/InGaAs (on GaAs) MODFET's," IE EE
Electron Device Lett., vol. 36, pp. 2243-2248, 1989.
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62
CHAPTER 4. EVIDENCE OF T H E GUNN EFFE C T IN H IG H -POW ER
InG aA s/InA lA s M OD FETs
4 .1 .
G eneral T ra n sp o rt Theory for Sem iconductors
4 .1 .1 . T ran sp o rt properties
The energy band structure plotted in momentum-space (k-space) of most III-V
compound semiconductors has a form similar to that shown in Fig. 4.1(a). The plot is
traced along the path from the L valley at the Brillouin zone boundary edge located at (27t/a)
(0.5ajcx + 0.5aky + O.Sajcz), where §kx, Sky and akZare the unit vectors in k-space, to the T
valley at the Brillouin zone center, to the X valley at the Brillouin zone boundary edge at
(2tt/a) akx. The precise energies of the X and L valleys relative to the F valley depends on
the material. In InGaAs, the T-L valley separation is 0.55 eV and the T-X valley separation
is 0.67 eV [4.1].
The presence of the X and L satellite valleys in III-V compound semiconductors
makes the steady-state velocity-field characteristic for electrons which are traveling in these
materials have a shape similar to that shown in Fig. 4.1(b). At low fields, the slope of the
curve, which is defined as the electron mobility, is relatively constant. In this region, the
scattering processes are dominated by polar optical phonon scattering [4.2]. As the electric
field is increased, the mean energy of the electrons rises and some electrons will transfer to
the lowest satellite energy valley. In this valley, the curvature of the energy-wave vector
characteristic is smaller, which leads to a higher electron effective mass [4.3]. The higher
effective mass implies a higher density-of-states, which makes transfer to the satellite
valleys very probable for the electrons which have sufficient energy. As the electric field is
increased further, more electrons have sufficient energy to transfer to the satellite valley,
and because the effective masses of the transferred electrons are greater in the satellite
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63
w
t-.>
(U
c
<u
■o
c
CO
x>
c
o
o3
T3
C
8
L
r
x
2jt/af-I! l l
(0 0 0)
2jr/a(1 0 0)
V2 2 22
Wave vector, k
(a)
Average electron velocity
low field/linear
negative differential
mobility
saturation
peak
sat
Magnitude of electric field
(b)
Fig. 4.1. (a) Conduction band diagram of a typical III-V compound
semiconductor plotted in k-space. (b) Corresponding velocity-field relation.
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64
valley, the mean velocity of the electrons in the material decreases, and a region of negative
differential mobility can result. In Fig. 4.1(b), the onset of this phenomena occurs at an
electric field intensity of 1^. Once the electric field has increased to the point that a majority
of the electrons can transfer, the velocity remains relatively constant at a saturation value.
4 .1 .2 . C riteria for negative differentia! mobility
One important point is that the presence of satellite valleys in the E-k relation of a
material does not necessarily guarantee negative differential mobility. A list of certain
criteria must be met [4.4], It is worth considering whether or not InGaAs meets these
criteria:
1. The energy gap between the T valley and the lowest satellite valley must be significantly
larger than kgT, the thermal energy. If this is not true, electrons can be excited to the
satellite valley through random thermal processes and do not rely as heavily on an external
electric field to make the transfer. In InGaAs, the lowest satellite valley is the L-valley,
with a T-L valley separation of 550 meV, which is over twenty times greater than the room
temperature value of ksT, which is roughly 26 meV.
2. The T valley-satellite valley separation energy must be smaller than the energy bandgap
between the valence band edge and the T valley. If this is not true, impact ionization will
occur before k-space transfer, and more electrons will populate the T valley, which will
tend to eliminate an observable negative differential mobility. The bandgap of InGaAs is in
the range of 0.75-0.77 eV, which is in fact greater than the 0.55 eV F-L valley separation.
3. The effective mass in the satellite valley must be significantly greater than that in the T
valley, which will result in a larger density-of-states in the satellite valley; hence, the
electrons which have enough energy to occupy either valley will most likely occupy the
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65
satellite valley. This will be the case if the E-k relationship is similar to that shown in
Fig. 4.1(a), as it is for InGaAs; the electron effective mass in the T valley is 0.041 m0,
where mo is the free electron mass. The L valley is ellipsoidal in k-space, with an effective
mass of mt = 0.162 mo in the two transverse directions and mj = 1.98 m0 in the
longitudinal direction. This results in an average conduction effective mass nriL in the L
valley given by
(4.1)
This yields a value of oil = 0.233 mo, which is 5.7 times the effective mass in the T valley.
4. The electron mobility in the satellite valley must be less than that in the central valley, in
order that the velocity of the carrier will decrease when transfer occurs. The electron
mobility |i is defined by the relation Vd = -|i^, where Vd is the drift electron velocity and £, is
the electric field, and is given by
e<?>
m
(4.2)
where e is the electronic charge, < t > is the average scattering time, and m is the effective
mass. Experimental data [4.5] show that the effective mobility in InGaAs is smaller in the
L valley than in the central valley, due at least in part to the larger effective mass.
Because all of the above conditions are met for InGaAs, negative differential
mobility would be expected in this material. Monte Carlo simulations [4.6], as well as
measured results, [4.1] and [4.5] show that there is in fact a region of negative differential
mobility in InGaAs, although there is some disagreement over the precise value of the peak
velocity and the electric field Ec at which it occurs. In the remainder of this chapter, the
experimental results of Shikegawa et al. [4.5] will be used, since in that work several data
points were taken at and just beyond Ec, where the negative differential mobility has the
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66
greatest magnitude. It is that region which is the most important for the discussion that
follows. Table 4.1 displays the velocity-field data from [4.5], with an additional column
displaying the average slope between the data points, which is on the order of (id. the
differential mobility. This data is plotted in Fig. 4.2.
4 .1 .3 . Effect of negative differential m obility in bulk sem iconductors
Since negative differential mobility does exist in InGaAs, the next issue to be
addressed is the expected behavior of a bulk sample of InGaAs when an external bias is
applied. There are a variety of different scenarios possible, especially when external
circuitry is utilized to take advantage of the device as an oscillator. In this chapter, no such
circuitry configurations will be addressed; the goal is simply to describe two different
scenarios which occur quite naturally when a simple dc bias is applied: Gunn domain
formation and the stable amplification mode.
4.1.3.1.
Gunn domain formation
When a bulk piece of uniformly-doped semiconductor with a velocity-field
characteristic similar to InGaAs is biased with an external voltage Vdc > ^c/L, where L is
the length of the sample, a steady dc current could in theory result such that the average
drift velocity of the electrons equaled the correct point on the velocity-field characteristic.
This point would lie in either the negative differential mobility region or the saturated
velocity region of Fig. 4.1(b). However, this situation is extremely unstable and highly
unlikely. Realistically, there will be slight doping fluctuations in the semiconductor and
random noise generated by the bias source. Either of these two situations would cause a
very small nonuniformity in the electron concentration, as shown in Fig. 4.3(a). This
nonuniformity in effect would be a miniature dipole traveling toward the anode, with the
electrons accumulating at the trailing end of the dipole and a corresponding positively
charged region depleted of electrons at the leading end of the dipole. The electric field
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67
Table 4.1. Drift velocity versus electric field intensity in InGaAs, taken from [4.5]. The
associated differential mobility at each point was also calculated and listed in the last
column.
Electric field, E,
Electron drift velocity,
Av<i/A£ ~ |ia
{kV /cm )
Vd (107 cm /s)
(cm 2/(Y s ))
0
0
1
0 .7 5
7500
1.5
1. 16
8200
2
1.4
4800
2. 5
1.7
6000
3
2
6000
4
2. 23
2300
5
2. 4
1700
6
2. 32
-800
7
2. 16
-1600
8
2. 17
1 00
9
2. 06
-1100
10
1. 94
-1200
11
1. 85
-900
12
1.8
-500
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68
2.5
Electron drift velocity (10
cm/s)
10000
8000
>
<N
6000
4000
3
2000
0.5
-2000
0
2
6
8
10
Electric field (kV/cm)
4
12
Fig. 4.2. Plot of electron drift velocity data for InGaAs
taken from [4.5]. The differential mobility calculated
from these discrete data points is also plotted.
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69
e~
drift
x=0
x=L
*>$C
Charge
E le c tr o n a c c u m u la tio n
field|
g
x
velocity
(a)
^high > ^>c
g
fieldl
* J \_
%low <
(b)
Fig. 4.3. (a) Instantaneous velocity and field profiles of a device with negative
differential mobility which experiences a sudden accumulation of electrons at one
point of the sample, (b) Electric field profile after steady-state has been reached.
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70
created by the dipole adds to the applied electric field, which results in a total electric field
which is greater inside the dipole than outside. The electric field intensity across the sample
at this instant of time is also shown in Fig. 4.3(a). In a more common situation, the
differential mobility would be positive; hence, the velocity in the dipole domain would be
greater because of the higher electric field, which would cause the congregated electrons to
speed up and naturally eliminate the dipole domain. However, for the sample being
considered here, the differential mobility is negative, and the electrons slow down inside
the domain, creating a larger accumulation of electrons at the trailing edge of the domain.
This additional accumulation increases the total electric field inside the domain even more,
which creates more accumulation of electrons due to a further reduction of velocity. The
domain increases in magnitude until the steady-state result shown in Fig. 4.3(b) is reached;
a constant electric field intensity of £iow exists outside the domain and a greater and varying
intensity exists inside the domain, with a peak value of £high at the junction of the
accumulation and depletion regions. This domain propagates to the anode, where it is
collected, and the current rises abruptly due to the elimination of the voltage drop in the
domain. However, the abrupt increase in current is quickly halted as the electric field
intensity rises above £,c in the bulk of the semiconductor, which causes another domain to
form near the cathode (because near the contacts is the point at which most nonuniformities
exist in real devices) and sharply decreases the current to its former value as the new
domain absorbs a large portion of the applied voltage. The resulting I-V characteristic for
the device is a constant current level with very narrow current spikes occurring at intervals
equal to the transit time of the device.
The values of £iow and ^high in Pig- 4.3(b) depend on many factors, including the
shape of the velocity-field characteristic and the diffusion coefficient D. The standard
expression for the total current density J in any system is the addition of the drift,
displacement, and diffusion current densities:
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71
J
=
-n e v d
-
e
( 4 .3 )
Where n is the electron density and e is the electric permittivity. Outside the domain, n and
I; are both constant, and the current is completely due to drift. Note that in the steady-state,
the drift velocity v j of the electrons outside the domain is the same as the domain velocity,
since the domain does not change shape.
For the special case of D = 0, the situation that results is illustrated in Fig. 4.4(a).
The domain is completely depleted, with an infinitely thin skin of electrons at the trailing
edge. These electrons travel solely due to drift and are pulled along at an electric field
intensity of ^high. with v(^high) = v(^Iow) = Vd- Inside the domain, the current is solely
due to the displacement current.
For the more realistic case in which D is nonzero, the result is shown in Fig.
4.4(b). In this case, there is still a very thin electron accumulation layer at the trailing edge,
but this layer has a nonzero width. The overall domain velocity is still the same vd, the
drift velocity of the electrons outside the domain, but the actual drift velocity of electrons
inside the domain is less than vd, since the current density is a combination of the drift,
diffusion, and displacement current densities. At the junction of the accumulation and
depletion regions, the maximum field £high exists, with:
(4.4)
Therefore, there is no displacement current, and the electron flow at this point is due to
diffusion and drift, which are illustrated in Fig. 4.4(b).
4.1.3.2.
Criteria for a propagating domain
Section 4.1.3.2 described that the existence of differential negative mobility would,
under most circumstances, form a steady propagating domain if biased with a sufficiently
high dc voltage. However, it is possible to think of situations that would hinder the
formation of a propagating Gunn domain. One such situation might occur if the device
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Average electron velocity
72
peak
lo w
Magnitude of electric field
Average electron velocity
(a)
peak
drift current
OW
Magnitude of electric field
(b)
Fig. 4.4. Velocity-field plot in a material with (a) a diffusion constant D
of nearly zero, (b) D 0.
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73
were very short. In this case, a small congregation of electrons might not grow into a
steady domain, because the surrounding charge would not have time to react to the
concentration fluctuation before it was collected by the cathode. Quantitatively, this implies
that for a domain to form, the transit time of the domain, Xtrans, should be at least three
times as large as the dielectric relaxation time of the material, Tdjei [4.7]:
f* ,,-
3£ ]
( l
Vvd
_
^
—Ttrans
(4.5)
J
which becomes
nL > (nL)crit = —j—
Am
(4. 6)
where l|idl is the magnitude of the negative differential mobility at the dc bias point of
operation. There is thus a critical charge density-length product that must be satisfied for
domain formation. Another way of stating this fact is that for a given charge concentration,
the dimension of the device in the direction of current flow must be equal to a certain
minimum length.
The derivation of (4.6) assumes the other two dimensions of the device are virtually
infinite. An interesting situation arises when one of the lateral dimensions becomes small.
As shown in Fig. 4.5, this confinement has the effect of spreading out the electric flux
caused by the electron accumulation layer of the forming domain, which decreases the
electric field in the direction of propagation [4.4], This in turn reduces the drift velocity
difference across the space-charge region which is responsible for the growth of the
domain. Furthermore, when one of the lateral dimensions d is extremely small compared
to the length of the device, there is a more stringent requirement for the formation of a
propagating domain [4.7]:
(4.7)
Am
which is an accurate expression for most material systems when
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74
electron accumulation
electric flux
(a)
direction of electron flow
>
electric flux
///
electron accumulation
(b)
Fig. 4.5. Shape of electron accumulation and associated electrix flux in a sample with
(a) a large value and (b) a small value of d.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
Here e a(jj refers to the dielectric constant of the adjacent material. Although
( 4 .7 )
does not
depend on L, it should be pointed out that technically both
( 4 .6 )
must be
( 4 .7 )
and
satisfied, except that (4.7) is the more restrictive criterion when the inequality (4.8) holds.
This is the case when the current is being carried by the carriers in the 2-DEG of a
MODFET. In the latter situation, nd = ns, where ns is the channel sheet concentration
which is usually quoted for MODFETs.
4.1.3.3.
Stable microwave amplification
When the charge-length product is less than the critical value, the device is said to
be subcritically doped and will, in fact, conduct a steady dc current even when biased with
Vdc > £c/L. Since a domain cannot form, electrons are forced to accumulate over the entire
length of the sample and distribute themselves such that the current density is constant
throughout the device. Consider a uniformly doped bar with a length L of a III-V material
such as InGaAs with an ohmic contact on either end, one biased as the cathode and one
biased as the anode (see Fig. 4.6). In the steady state, the electron concentration and the
electric field must obey the following two relations:
dx
£
J ~ -nev(£) = constant
(4.10)
where N d is the donor density and all donors are assumed ionized. Equation (4.9) is
simply Poisson's equation, and (4.10) is the current continuity equation where diffusion
has been neglected. Including the effects of diffusion would make the situation slightly
more complicated but would not significantly alter the qualitative arguments about to be
made. Imbedded in (4.10) is a third relation, i.e., the velocity-field relation of the material.
In addition, the ohmic cathode and anode contacts impose boundary conditions: the electron
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76
electron flow
x=0
cathode
anode
electrons
x=L
donors
73
'rrun
0
x = x0
x=L
Electric field
=
Fig. 4.6. Illustration of steady-state electron concentration and electric field
intensity in a uniformly subcritically doped bar of a semiconductor
material with negative differential mobility.
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77
concentrations are very large at x = 0 and x = L, due to the high donor densities present.
This in turn causes the electric field to go to zero at the ends of the device.
At the cathode, there is a negative field gradient in order to satisfy Poisson’s
equation (4.9). Moving into the device away from the cathode, therefore, the magnitude of
the field grows larger, which causes the drift velocity to increase as well. To satisfy
current continuity (4.10), the electron density n must decrease. This, in turn, makes the
field gradient less negative. Finally, at x = xo, the concentration gets low enough that the
drift velocity has reached its peak value for the material. This is, therefore, the point of
lowest concentration and, hence, the lowest magnitude of the field gradient (in fact, there is
an inflection point in the electric field plot, as shown in Fig. 4.6). Because this is at the
field strength of the onset of negative differential mobility for this material, the drift velocity
decreases as the field intensity continues to grow more negative. Hence, the electron
concentration increases, which causes the electric field gradient to grow more negative
again. This continues until the anode is reached, at which point an abrupt increase in Nd
occurs. When n = Nd, the field gradient is zero, and the field reaches its most negative
value (this also requires an additional inflection point to occur just before n = Nd, which is
also shown in Fig. 4.6). Just beyond this point, Nd » n and the electric field quickly rises
to zero at the end of the device.
Interestingly, in the steady state, such a device does not have a dc negative
differential resistance (NDR). This fact can be seen at the point x = xo. Here, the diffusion
current is precisely zero since the concentration gradient is zero, and the current density
J = -enminvmax- As the external bias is increased, all of the electric field gradients
increase, including at x = xo, which increases nmjn and thus J. Therefore, the dc resistance
is positive because, as the external voltage increases, the stored charge in the device
increases which more than compensates for the decrease in velocity which occurs on the
anode end of the device. Note that a small increase in current requires all of the charge
concentrations to increase, which in turn increases the electric field gradient throughout the
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78
sample; hence, the electric fields become very large. Thus, a very large increase in voltage
is required for a small change in current, which is what causes most III-V materials to have
their familiar current-limiting behavior.
However, the transient response of the device is quite different. If, for example,
the external voltage supplied to the device is increased abruptly, the electron accumulation
in the device will take some time to increase and to redistribute itself accordingly. At first,
the field increases throughout the device, which causes all of the velocities of the electrons
between x = 0 and x = xo to increase (except in the immediate vicinity of xo) and all of the
velocities of the electrons between x = xo and x = L to decrease. Therefore, electrons start
to accumulate in the anode region, rapidly causing the electric field to become much more
negative in this region as well. This buildup of the electric field causes more of the voltage
to be dropped in the anode region of the device, where the velocities are slower. The
electric field in the depleted cathode region must, therefore, decrease, which in turn
decreases the electron velocities in this region. The net transient response to the abrupt
increase in external voltage is, therefore, a decrease in current. However, since the device
is subcritically doped, this effect does not last long, due to the efficient collection of the
electrons accumulating at the anode and the electrons being injected at the cathode. As this
happens, the concentrations tend to even out to the steady-state profile shown in Fig. 4.6,
and the current increases to a greater value than the value before the voltage drop, due to
increased electric field gradients in the device. The time required to reach the steady state is
thus on the order of the transient time of the device.
From the transient response, it is apparent that if an additional ac voltage is applied
to the described device with a period less than the transit time of the device, the charge in
the device will not have time to reach the "steady-state" distribution and the device will
display NDR at frequencies greater than or equal to the transit frequency. In algebraic
form, this means the device will display NDR at a frequency f if it satisfies the condition
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79
(4.11)
where the value of the drift velocity v^ is the average drift velocity in the device. When
such an external voltage is supplied, a small alternating space charge distribution
propagates through the device. However, when the frequency increases to a value much
higher than the transit frequency, the space charge wavelength becomes extremely small
and is eliminated by diffusion, thus eliminating any evidence of microwave NDR. Hence,
diffusion places an additional restriction on the presence of NDR, which can be shown to
occur only if [4.7]
(4 .1 2 )
For a 2-DEG in a MODFET, the principles which led to (4.7) can be extended to show that
diffusion imposes the following condition for microwave amplification:
. ^ 4 tt£D
—T
(4.13)
eM
In most cases, diffusion causes the frequency range of stable microwave amplification to be
on the order of 1 GHz [4.7].
4 .2 .
R elevance o f G u n n P henom ena to M O D FE T s
4 . 2 . 1 . T h eo re tic al co n sid eratio n o f G unn ph en o m en a in M O D F E T s
Section 4.1 described how materials such as GaAs and InGaAs display negative
differential mobility and explained two possible phenomena that can occur as a result: a
propagating domain or stable microwave reflection gain. It is then interesting why
MODFETs which have GaAs or InGaAs channels have not ever been reported to display
any Gunn phenomena, especially since many reports have been made about such
phenomena in GaAs [4.8] and [4.9] and InP [4.10] MESFETs. Consideration of the
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80
theory presented in Section 4.1 leads to the conclusion that there are three natural qualities
present in standard MODFETs that can suppress the occurrence of Gunn phenomena.
The first quality that all MODFETs possess is the confinement of the high-field
region to a relatively small section of channel. As was discussed in Chapter 2, this section
begins underneath the drain-side edge of the gate and extends a short distance toward the
drain; in addition, the carriers are highly depleted in this region. Therefore, it is extremely
difficult for carriers to form a dipole domain during their journey across the high-field
region before they reach the low-field region of the drain ohmic contact. Moreover, the t
confinement of the carriers in a MODFET to two dimensions weakens the fields of
developing dipoles and further suppresses Gunn domain formation. Hence, the chargelength requirements of (4.6), (4.7), (4.12), and (4.13) are not satisfied due to the small
values of n and L, and no Gunn phenomena exist.
A second quality which InGaAs channel MODFETs possess is the tendency for
impact ionization to occur in the channel. As was discussed previously, this tendency
inhibits the formation of a Gunn domain. Although simple k-space transfer occurs for a
large number of electrons at electric field intensities below that required for impact
ionization, the confinement of the carriers to two dimensions as well as the small chargelength products in MODFETs require that higher fields be applied to obtain a Gunn
domain. For standard InGaAs/InA1 As MODFETs, these fields will usually lead to impact
ionization before domain formation can occur.
The third quality is the tendency for real-space transfer of high-energy electrons
from the channel into the nearby donor layer when the drain voltage is increased. Realspace transfer is present to some extent in virtually all GaAs-based and InP-based
MODFETs when they are biased at high drain voltages; when special conditions are met,
this transfer mechanism can cause some of these devices to display NDR. The theory of
this phenomenon has been characterized in considerable detail [4.11] and [4.12], and NDR
due to real-space transfer has been witnessed in both GaAs-based [4.13] and [4.14] and
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81
InP-based [4.15] MODFETs. Regardless of whether or not the real-space transfer causes
NDR, this transfer mechanism significantly impedes the formation of Gunn domains,
because the electrons do not remain in one place long enough to accumulate and create a
dipole. In particular, for a GaAs/AlGaAs MODFET; the conduction band discontinuity at
the heterointerface is only 0.25 eV, while the F-L valley separation is 0.33 eV. In
comparison, for InGaAs/InAlAs MODFETs, the conduction band discontinuity is 0.52 eV,
while the F-L valley separation of InGaAs is 0.55 eV. In reality, however, there are other
issues which inhibit significant quantities of charge from undergoing real-space transfer at
low or moderate fields in addition to the conduction band discontinuity; these issues
involve adherence to current continuity and Poisson's equation. Despite this fact, even in
InGaAs-channel MODFETs, Gunn domain formation would be at least slightly hindered by
some of the charge undergoing real-space transfer.
For MODFETs, it is evident that the probability of Gunn phenomena increases as
the device is designed for higher output power densities. For example, one technique used
to enhance the gate-drain breakdown voltage of a device is to reduce the field intensity in
the channel by causing it to extend over a greater region. Unfortunately, this technique
increases the likelihood of Gunn domain formation in the device in the longer high-field
region, which is especially true if the device is doped heavily enough so that there is
significant charge in this high-field region. Such high doping levels are also common in
power MODFETs due to the higher current levels obtainable. In addition, doping planes
are sometimes grown in the channel and/or below the channel to increase the charge
further, which negates the strict confinement of the channel carriers to two dimensions and
further increases the likelihood of Gunn domains. Finally, Schottky materials with larger
barrier heights are also often used to prevent tunneling of electrons from the negatively
biased gate to the channel, thereby reducing impact ionization. Although a reduction in
impact ionization is desirable for higher breakdown voltages, it also makes Gunn domain
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82
formation more probable. Oscillation due to the Gunn effect is, therefore, a significant
concern in the design of InGaAs/InAlAs MODFETs for power applications.
4 .2 .2 . Observed G unn phenom ena in InG aA s/InA lA s M ODFETs
4.2.2.1.
Causes of NDR in FETs
Devices such as MESFETs and MODFETs which have been fabricated from DI-V
compound semiconductor materials have at times been reported to display negative
differential resistance (NDR) regions in the drain current versus drain-to-source voltage
characteristics. Such regions of NDR can be caused by four different mechanisms. First,
NDR can result in the dc characteristics from simple thermal heating [4.16] Second, dc
NDR can occur as a result of the kink effect [4.17], i.e., the trapping of electrons in the
layers adjacent to the channel layer. Third, as was mentioned in Section 4.2.1, highenergy electrons in the channel of a MODFET can transfer in real space to the donor layer
via tunneling or thermionic emission where the saturated velocity is lower [4.18]. Finally,
NDR can occur due to k-space transfer of electrons, i.e., the Gunn effect.
Thermal heating and the kink effect are phenomena that can create NDR only at dc
and, therefore, can be disregarded as possible mechanisms when devices display NDR at
microwave frequencies. In contrast, real-space and momentum-space transfer can result in
NDR at both dc and microwave frequencies. As was mentioned previously, there have
been published reports of such NDR behavior from real-space transfer for both GaAsbased [4.13] and [4.14] and InP-based [4.15] MODFETs. Both predicted and observed
NDR behavior due to Gunn phenomena have been reported for GaAs [4.8] and [4.9] and
InP [4.10] MESFETs; however, to date, there have been no such publications for
MODFETs of any material system. The section will describe a unique occurrence of NDR
behavior at dc and microwave frequencies due to the Gunn effect in InAlAs/InGaAs
MODFETs. Because real-space transfer can also cause NDR at both dc and rf, the aims of
this section will be to characterize the behavior of the devices and to illustrate how this
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83
behavior can be explained by traditional concepts related to Gunn phenomena and differs
from NDR behavior exhibited by devices for which real-space transfer is the underlying
mechanism. Two sets of devices will be described: gated MODFETs and nongated
devices.
4.2.2.2.
Gated device fabrication and analysis
The gated MODFETs in this study were fabricated on a layer structure (see
Fig. 4.7) consisting of a 250 nm InAlAs buffer layer grown on an InP substrate, followed
by a Si planar-doped layer, a 5 nm InAlAs spacer layer, a 20 nm InGaAs channel, a 1.5 nm
InAlAs spacer layer, a 5.0 nm Si-doped InAlAs layer, a 25 nm pseudomorphic
Ino.4Alo.6As Schottky layer, and a 7 nm InGaAs cap. The room temperature sheet
concentration and mobility for this structure were 4.3 x 1012 cm '2 and 8500 cm2/Vs,
respectively.
Figure 4.8 displays the drain current (Id) versus drain-source voltage (VdS)
characteristics of a device having a width of 50 |im, a drain-source spacing of 2 (im, and a
gate length of 0.15 pm. The curve trace was taken with the source grounded and the gate
and drain probes capacitively coupled to ground. If this was not done, oscillation resulted,
especially in the regions in which there was a sharp NDR region in the drain current, such
as that which appears in the Vgs = -200 mV and Vgs = 0 V curves in Fig. 4.8. As will be
illustrated, the cause of this sharp decrease in current is most likely due to the formation of
a high-field Gunn domain which periodically propagates from the edge of the active
channel on the drain side to the drain contact, where it is collected. This domain absorbs a
major portion of the voltage drop across the channel; thus, the drain current decreases
abruptly when the domain is formed. Figure 4.9 is a magnified view of the drain I-V
characteristic for this device with Vgs = -200 mV. In addition, the gate current is plotted,
which displays a sharp decrease in magnitude at the same point the drain current decreases.
The negative gate current represents a positive flux of electrons traveling from the
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84
7 nm undoped InGaAs cap
25 nm undoped InQ 4AIQ gAs Schottky
5 nm n++ InAlAs donor
1.5 nm undoped InAlAs spacer
20 nm InGaAs channel
5 nm InAlAs spacer
’
" "Si doping plane
250 nm InAlAs buffer
InP substrate
Fig. 4.7. Layer structure of gated MODFETs displaying
NDR due to the Gunn effect.
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85
800
700
600
I500
§400
200 mV/step
fc
3 300
c
| 200
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Drain voltage (V)
Fig. 4.8. Current-voltage characteristics of InGaAs/InAlAs MODFET
displaying NDR in the V ^s = -200 mV and V^s = 0 V traces.
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600
-0.04
400
0.06
*300
0.08
V „n = -200 mV
c 200
100
-
0.1
-
0.12
Gate current (mA/mm)
0.02
500
-0.14
-0.16
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Drain voltage (V)
Fig. 4.9. Drain and gate current of InGaAs/InAlAs MODFET at
a gate-source bias of -200 mV.
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87
negatively biased gate to the positively biased drain via tunneling from the gate to the
channel [4.19].
From the dc characteristics of these FETs, important differences between these
devices and devices displaying NDR due to real-space transfer can already be seen. First,
GaAs/AlGaAs MODFETs displaying real-space transfer have always been reported to
exhibit NDR in the drain current at gate biases which are positive or at the lowest, zero.
[4.14,4.18]. Presumably, this characteristic exists because a negatively biased gate repels
hot electrons from the donor and Schottky layers as the electrons travel from the source to
the drain. Conversely, if the gate is forward biased, the potential and field profiles are
more favorable for tunneling and thermionic emission of electrons into the high-bandgap
material, and many of these electrons can be efficiently collected by the gate [4.18]. It is
important to note that the InGaAs/InAlAs MODFETs in [4.15] did display NDR at gatesource voltages as low as -200 mV; this NDR was attributed to real-space transfer.
However, the Fig. 4 in that work shows that the oscillatory behavior of the device was
definitely strongest at positive gate biases and decayed very rapidly as the gate bias was
brought below 0 V, with very little NDR being displayed at Vgs = -200 mV. For our
devices, the precise opposite was true: the NDR always peaked at negative gate biases,
usually in the range of -400 to -200 mV, and died out as the gate was brought positive, as
is evident in Fig. 4.8. Furthermore, it was stated in [4.15] that no gate current change
occurred in conjunction with the abrupt drop in drain current. Real-space transfer devices
fabricated in the GaAs material system [4.14] and [4.18] often display an increase in the
magnitude of the (positive) gate current due to the collection of transferred electrons by the
gate. In sharp contrast to both of these cases, our devices always showed a small but
abrupt decrease in the magnitude of the (negative) gate current at the same point the sharp
decrease in drain current occurred, as is shown in Fig. 4.9.
The latter behavior is understood by considering the fact that, without a Gunn
domain present, a large portion of the applied gate-drain bias occurs across a small section
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
88
of the channel immediately adjacent to and on the drain side of the gated region, because the
carriers are most depleted in this region of the channel; hence, the longitudinal field is
strongest in this region to insure current continuity along the channel. The gate current
arises because the electrons on the negatively biased gate tunnel to the higher potential area
of this depleted channel region, which is in close proximity (< 0.1 pm). Normally, this
current increases with drain bias because the drain-gate potential difference Vdg increases,
creating a larger tunneling probability. This trend continues until the bias is increased such
that Vdg/Ldg ~ Ec, where Ldg is the lateral drain-gate separation and Ec is the critical electric
field at which the negative differential mobility is large enough in magnitude for the
formation of a propagating domain [4.7]. At this point, the high-field propagating Gunn
domain forms, absorbing a large portion of the voltage drop in the channel, which causes a
decrease in the time-averaged potential difference between the gate and the channel region
in close proximity to the gate, which in turn diminishes the gate current due to reduced
tunneling efficiency.
At this point, it should also be noted that propagating dipole domains oriented
perpendicular to the heterointerface can arise from real-space transfer as well [4.20].
However, the dipole domains in this case must be excited by a large external voltage pulse;
thermal noise cannot generate such domains [4.20]. Also, because these domains alternate
their polarization direction at a very high frequency as they propagate, it is unlikely they
would affect the gate current the way a Gunn domain would.
The second obvious difference at dc between the devices in this study and realspace transfer NDR MODFETs is evident from Fig. 4.8. As Vgs is increased, the point at
which the drain current sharply decreases occurs at a larger Vds. The likely explanation for
this behavior is that the high electric field region on the drain-side edge of the active channel
region narrows as Vgs is increased and VdSis held constant, since more carriers are present.
The shorter length of the high-field region causes the effective charge density-length
product to fall below the critical value necessary for Gunn domain formation, given by
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89
(4.6). Thus, when the length of the high-field region is decreased, carriers do not have
sufficient time to form a domain due to the nonzero dielectric relaxation time. Therefore, in
order to obtain NDR when Vgs is increased, Vds must be increased as well to once again
extend the depleted, high-field region on the drain side to a length sufficient for domain
formation. This trend is opposite to the trend observed in MODFETs with real-space
transfer; in the latter devices, a more positive gate bias makes tunneling and thermionic
emission of electrons into the donor layer more likely; hence, the NDR occurs at a lower
value of Vds because less energy is required of the electrons for the transfer to occur [4.18].
It is clear that a great deal of information about the underlying mechanism of the
NDR in these devices may be determined from the dc characteristics. As was mentioned in
the beginning of this section, NDR was observed at high frequencies as well. Figure
4.10(a) shows the magnitude of S22 versus frequency at various drain biases for a typical
device, with the gate as port 1 and the drain as port 2. The measurements were taken with
a Cascade Microtech probe station. For this device, Vgs was fixed at 0 V. As can be seen,
below a certain threshold value of Vds, the device is well behaved, with IS22I < 1■ When the
threshold value of Vds is reached, S22 becomes erratic, with a magnitude greater than one at
nearly all frequencies. The magnitude of S22 at 11.2 GHz for this device is plotted versus
drain voltage in Fig. 4.10(b), along with the drain I-V characteristics of the device. As is
evident, the point at which IS22I exceeds unity is the same bias point at which the abrupt
drop in current occurs in the Id*Vds characteristic measured with the Cascade probe station,
which was true of all devices at all frequencies. Note that the dc NDR occurred at higher
drain biases with the Cascade measurement setup, since a significant series resistance was
present in the setup and it was not a four-point probe measurement setup like the dc probe
station, which automatically corrects for the probe and cable resistances. The erratic nature
of S22 is consistent with the notion of the formation of the propagating Gunn domain. In
contrast, [4.14] and [4.18] showed much more well-behaved plots of S22 versus
frequency, even when the magnitude of S22 exceeded unity.
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90
3.5
Increasing V
0.5
0
5
10 15 20 25
Frequency (GHz)
30
35
(a)
700
600
500
<
a 400
e
0.8
8 300
3
0.6
e 200
0.4
100
0.2
O
a
N
X
a
03
CN
00
Q
0
0
0
0.5
2
1.5
Drain voltage (V)
1
2.5
(b)
Fig. 4.10. (a) Magnitude of S22 of InGaAs/InAlAs MODFET plotted as a
function of frequency at various drain biases, (b) Drain current and magnitude
of S22 at 11.2 GHz as a function of drain bias.
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91
The NDR exhibited both at dc and microwave frequencies by these InGaAs/InAlAs
MODFETs has characteristics which sharply contrast those of NDR MODFETs involving
real-space transfer. However, the observed behavior is consistent with current theory
involving momentum-space transfer and, therefore, supports the notion of the existence of
high-field Gunn domains in these devices.
4.2.2.3.
Gateless device fabrication and analysis
To further characterize the NDR behavior of layer structures such as these, gateless
devices were fabricated on a similar layer structure which contained a 250 nm undoped
InAlAs buffer layer, a Si delta-doped layer, a 5 nm InAlAs spacer layer, a 20 nm InGaAs
channel, a 2 nm InAlAs spacer layer, a 6.6 nm n-type InAlAs donor layer, a 20 nm
Ino.4Alo.6As Schottky layer, a 10 nm InAlAs Schottky layer, and a 7 nm InGaAs cap layer
(Fig. 4.11). The room temperature carrier sheet concentration for this structure was 5.1 x
1012 cm '2, with a corresponding Hall electron mobility of 9810 cm2/(Vs). Devices with
drain-to-source spacings of 2 pm, 3 pm, and 4 pm were measured, all with channel widths
of 50 pm. Measurements were performed on the devices at dc, and scattering parameter
measurements were performed over a frequency range of 1 to 35 GHz.
Figure 4.12(a) is a plot of drain current and the magnitude of S22 at 21.06 GHz as a
function of drain voltage for one of the gateless InGaAs/InAlAs MODFETs. The drainsource separation of this device was 3 pm. A reference level of IS22I = 1 is also shown.
The device definitely displays NDR in the dc drain I-V characteristic. As was the case for
the gated devices, the bias point of dc NDR corresponds precisely to the bias point at which
the magnitude of S22 increases sharply at a given frequency. In Fig. 4.12(b), which
displays the magnitude of s22 of the same device plotted versus frequency at different drain
voltages, this bias point is where S22 becomes completely erratic and exceeds unity at
nearly every frequency. Hence, this bias point corresponds to the voltage at which a
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92
7 nm undoped InGaAs cap
10 nm undoped InQ 4AIQ gAs Schottky
20 nm undoped Ing ^AIq gAs Schottky
6.6
nm n++ InAlAs donor
2 nm undoped InAlAs spacer
20 nm InGaAs channel
5 nm InAlAs spacer
■ ---------------------------- — Si doping plane
250 nm InAlAs buffer
InP substrate
Fig. 4.11. Layer structure of gateless MODFETs displaying
NDR due to the Gunn effect.
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93
1200
1.4
1000
1.2
<
S
600
i
3
O
e 400
0.6
2
0.4
Q
N
X
o
vo
p
r —H
0.8 C
N
800
200
prop
“I<n
n
c/3
0.2
0
0
0.5
1
1.5 2 2.5 3
Drain voltage (V)
3.5
4
30
35
(a)
3
2.5
llO m V /ste p
2
Increasing V
1
0.5
0
0
5
10 15 20 25
Frequency (GHz)
(b )
Fig. 4.12. (a) Plot of drain current and magnitude of S22 at 21.06 GHz versus drain voltage
for a gateless InGaAs/InAlAs MODFET displaying NDR. The drain-source separation was
3 pm. A reference level of IS22I = 1 is also shown, (b) Magnitude of S22 of same device
plotted versus frequency at different drain voltages.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
94
propagating Gunn domain is able to form, as was the case for the gated devices. This
drain-source voltage will be defined here as Vpr0p.
In the nongated device, however, there is an additional behavioral state.
Figure 4.12(a) shows that at 21.06 GHz, IS22I actually exceeds unity at voltages just below
Vprop. However, at these voltages, IS22I actually is quite well behaved when plotted versus
frequency, as is shown in Fig. 4.12(b).
Moreover, IS22I is less than unity at low
frequencies and increases monotonically until it exceeds unity at a certain cutoff frequency,
fc and above. Hence, at these voltages, the device does not appear to be oscillating on its
own, as is the case when a propagating Gunn domain is present with IS22* > 1 at all
frequencies; instead, the device simply shows reflection gain for frequencies at or above fc,
which is an indication that the device is in the stable microwave amplification mode
discussed in Section 4.1.3.3.
Furthermore, the IS22I curves in Fig. 4.12(b) have a
somewhat peaked or Gaussian-like shape to them at these voltages over the range of
frequencies where unity is exceeded. This shape can be explained by the concepts
discussed in Section 4.1.3.3; at the lower frequencies, small propagating domains are
quenched by collection at the anode, and at higher frequencies, diffusion begins to interfere
with microwave domain formation.
Figures 4.13(a) and (b) provide a different method of presenting the different
modes of behavior for the 2 Jim and 3 |im devices, respectively. In these figures, the value
of fc is plotted versus drain-source voltage at three different temperatures, where IS22I ^ 1
for f > fc. As illustrated most clearly in Fig. 4.13(b), the devices have three different
modes of operation.
In the first mode, fc approaches infinity, IS22I < 1 at all frequencies, and there is no
reflection gain. These effects occur over the entire lower voltage range and imply that kspace transfer has not yet occurred for a number of electrons in the device which is
sufficient for the formation of either a high-field or microwave small-field Gunn domain.
Note that the voltage range of this first mode extends to voltages higher than the voltage at
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95
35
30
N
ffi
o
25
>>
o
c
<L>
20
26 °C
3
cr 15
50 °C
2
80 °C
10
o
•w
u
5 r 2 Jim drain-source spacing
0
2
2.2
2.4 2.6 2.8
3
3.2
Drain-source voltage (V)
3.4
(a)
s_2 < 1 at all
N
frequencies
u
•
26 °C
20 -
50 °C
-
—alt— 80 °C
o
3
<D
3
cr 15
2
3
u
10 r 3 pm drain-source
5
S22 > * at ^ ^recluenc*es
0
i
2
i
i
i
i
i
i
i
i
i
i
i
i
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Drain-source voltage (V)
(b)
Fig. 4.13. Lowest instability frequency for S22 in gateless InGaAs/InAlAs NDR
MODFET plotted as a function of drain bias at three different temperatures for a drainsource spacing of (a) 2 |im and (b) 3 |im.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
96
which current saturation occurs in Fig. 4.12(a). The reason for this phenomenon is related
to the weak nature of space-charge fields in 2-DEGs, as was discussed in Section 3.1.3.2.
This weakness causes the minimum voltage necessary for domain phenomena to increase
[4.7].
When Vds reaches a value such that a sufficient number of the carriers in the channel
can transfer to the L satellite valley in k-space, the differential mobility is negative over a
large section of the device, and the device changes to the second mode of operation, stable
microwave amplification. In this mode, a large number of the carriers in the channel have
just entered the negative differential mobility regime; hence, the average magnitude of the
negative differential mobility is small (refer to the point £ =
in Fig. 4.1 (b)). The
magnitude is small enough such that (4.7) is not satisfied, eliminating the possibility of a
propagating Gunn domain. However, the device can show microwave reflection gain,
provided the frequency is large enough that (4.11) is satisfied. Hence, fc is finite and
nonzero. The value of fc is initially higher as the device begins to enter this mode, because
the device is on the verge of entering the state at which microwave domains are able to
grow before being quenched by carriers being injected into or out of the device at the
contacts; thus, since higher frequency domains are not as easily quenched, the device
shows reflection gain first at these frequencies. Then, as the device fully enters the
microwave amplification mode, fc tends to level off, as is shown in Fig. 4.13.
Finally, the third state of operation is entered when V(js is increased such that the
magnitude of the average negative differential mobility is large enough and the average drift
velocity is small enough to satisfy the criterion (4.7) for high-field Gunn domain
propagation. In this state, the device oscillates independently, S22 is erratic with a
magnitude greater than unity at nearly all frequencies and, thus, fc is equal to the lowest
frequency measured, 1 GHz.
At this point, some approximate calculations are worthwhile to find how well the
observed device behavior is in reasonable agreement with simplified Gunn theory. For
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97
example, the 3 |im device of Fig. 4.13(b) has an fc of approximately 18 GHz when fully in
the microwave amplification regime. The information in Table 4.1 and knowledge that
most of the carriers in the sample at this bias are traveling at velocities below the peak
velocity, allow that a rough estimate of the average drift velocity would be 2 x 107 cm/s.
When this value in (4.11) and L = 3 pm are used, a value of 66.7 GHz would be expected
for fc. The discrepancy is readily understood when the true MODFET layer structure is
considered.
To quench a high-frequency space-charge domain, additional charge must flow to
and from the contacts to the channel. The time required for this compensation would be on
the order of the channel transit time were no other material layers present. However, when
charge enters or leaves a region of the channel, a similar event must occur in the donor,
Schottky, and cap layers as well, since a given point in any of these layers floats at a
potential which has a roughly constant offset from the voltage at the point in the channel
directly beneath i t If this charge redistribution did not occur in the other layers, the charge
in the channel at that point would be modulated due to the change in the relative potential of
the material above, similar to the effect a biased metal gate would have. This modulation
would violate the requirements of current continuity and Poisson's equation, which govern
the electric field profile and charge concentration in the channel. Therefore, the quenching
of microwave reflection gain is actually limited by the transit time of the n-type InAlAs, in
which the carriers would have a much lower drift velocity, on the order of 6 x 106 cm/s for
heavily doped InAlAs [4.21]. Substituting this value in (4.11) yields an fc of 20 GHz,
which is in much better agreement with the observed value. Reflection gain is thus
possible over a much larger range of frequencies than would be possible in a bulk InGaAs
sample.
It is now obvious why the microwave amplification regime was not
distinguishable in the high-frequency characteristics of the gated devices of Section
4.2.2.2; the correct value for L in (4.11) is the length of the depletion region on the drain
side of the gate. Even if this value were as high 0.3 pm, which would make the effective
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98
gate length three times as large as the true gate length of 0.15 nm, the corresponding value
of fc would be 200 GHz, which is far above the highest measured frequency, 35 GHz.
Another calculation may be performed to determine whether or not it is reasonable
that the microwave amplification regime would occur at drain voltages slightly less than the
onset of high-field propagating domain formation.
As was explained previously,
increasing the bias on the device has the effect of increasing the average magnitude of the
negative differential mobility of the electrons, which can effectively contribute to the
formation of domains. For microwave amplification, the magnitude of the negative
differential mobility must be large enough that it can overcome the quenching effects from
injection of carriers at the contacts, as well as the attenuating effects of carrier diffusion.
Injection of carriers is related to the transit time of the device and has been discussed. What
remains to be addressed is the minimum magnitude of negative differential mobility
necessary to overcome the effects of diffusion. If the onset of microwave amplification
occurs at a mobility magnitude of l|imin,ml» and the onset of dc high-field domain formation
occurs at a mobility magnitude of
lp min,dcl>
the condition
lp min,dc| > l|imin,ml
must hold in
this material, since microwave amplification is observed at lower voltages than the
minimum voltage at which propagating domains are observed. To verify if this situation is
possible, equations (4.6) and (4.13) may be rearranged and combined to yield
(4.14)
4neD
|^m in,m |
Here eadj is equal to the high-frequency relative permittivity of InAlAs, which has a value
of 9.8, and e is the high-frequency relative permittivity of InGaAs, which has a value of
11.1 [4.21]. The diffusion coefficient D is given by the Einstein relation:
D=
e
(4.15)
This value will be larger for electrons in the central valley than for electrons in the satellite
valley. For sake of argument, a value of 2 |1h will be used for the effective conductivity
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99
mobility p. in (4.15), where P h is the measured low-field Hall mobility for this material,
having a value of 9810 cm2/(Vs) at room temperature. This value is pessimistic because it
will yield an artificially large value of D; hence, the ratio (4.14) will be smaller. Using an
average drift velocity of 2 x 107 cm/s, and L = 2 nm, the ratio (4.14) will then have a
value of 1.65. This ratio will be larger for the 3 |im and 4 pm devices, and even larger
when a more realistic value of D is used. Hence, it is very reasonable to believe that
• P m in .d c l >
lp m in ,m l>
which rationalizes the device entering the microwave amplification
regime at voltages below the voltage necessary for high-field propagating domain
formation.
Another item of interest in Figs. 4.13(a) and 4.13(b) is the temperature dependence
of the devices. As was mentioned in Section 4.1.2, when carriers have a larger probability
of being thermally excited into the satellite valley at low fields, the satellite valley is not as
effectively isolated from the central valley, which will lead to lower magnitudes of negative
differential mobility. This phenomenon is evident in Figs. 4.13(a) and 4.13(b); at higher
temperatures, a larger voltage is necessary to achieve propagating domains, because the
smaller magnitude of negative mobility reduces the ability for domains to grow. In fact, as
is evident from Fig. 4.13(b), high-field propagating domains were not even witnessed at
80 °C. Also, at higher temperatures, fc tends to level off at a higher value in the microwave
amplification regime, apparently because the gain is not sufficient to overcome the
attenuation due to carrier injection from the contacts, which is stronger at lower
frequencies.
Figure 4.14(a) is a plot of fc versus voltage at a temperature of 26 °C for the three
different device lengths. Figure 4.14(b) is similar, except the temperature is 50 °C. In the
microwave amplification region, fc levels off at lower frequencies as the device length is
increased, which follows the trend predicted by (4.11). In addition, the microwave
amplification region and high-field domain region occur at higher voltages in the longer
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100
35
30
2 (im
25
3 |im
20
4 [im
10
T = 26
5
0
0 0.5
1 1.5 2 2.5 3 3.5 4 4.5
Drain-source voltage (V)
(a)
35
N
30
T = 50 °C
as
25
o
C
0)
3
cr
20
2 [im
15
3 |im
10
4 [im
.K
o
3
u
5
0
0 0.5
1 1.5 2 2.5 3 3.5 4 4.5
Drain-source voltage (V)
(b)
Fig. 4.14. Lowest instability frequency for S22 in gateless InGaAs/InAlAs NDR
MODFET plotted as a function of drain bias at three different drain-source spacings at
a temperature of (a) 25°C and (b) 50°C.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
101
devices, simply because a larger voltage is necessary to obtain a given electric field
intensity as the device length is increased.
It is clear that the high-frequency characteristics of the gateless devices support the
notion of Gunn phenomena as the underlying cause of NDR in these layer structures.
Particularly, the existence of two distinct modes, the stable microwave amplification regime
and the high-field propagating domain regime, further contradicts the notion of real-space
transfer as the possible mechanism of NDR, since this is not what has been observed in
real-space transfer devices.
4 .3 .
C onclusion
As was illustrated in the theoretical section of this chapter, Gunn phenomena are
inherent to most III-V compound semiconductor materials.
Nevertheless, in most
MODFETs, the short length of the high-field region on the drain side of the device in
combination with the depleted electron densities and impact ionization problems in this
region prevent high-field domains from forming. However, in MODFETs which are
designed for high output powers, methods are employed to reduce the tunneling of
electrons from the gate to the channel and, hence, reduce impact ionization, extend the
length of the high-field region, and increase the number of carriers at all points in the
channel, including the high-field region. All of these design alterations increase the
likelihood of Gunn domain formation. Such a phenomenon was observed in a particular
set of InAlAs/InGaAs MODFETs and was further characterized by measurements
performed on similar devices without gates. The behavior of the MODFETs was
distinguished from the behavior that has been observed in devices displaying NDR due to
real-space transfer, which indicates that momentum-space transfer was indeed the
underlying mechanism.
Although such behavior may be somewhat rare in general, it is clear that the
possibility of Gunn domain formation in the channel must be considered in any power
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102
HFET design. From the discussions in this chapter, tactics which can be used to decrease
the likelihood of such an occurrence might include limiting the charge present in the
channel, limiting this charge to a 2-DEG instead of having additional doping present in the
channel, increasing the likelihood of real-space transfer into a material with good transport
properties, such as by using a composite InGaAs/InP channel in the place of the standard
InGaAs channel, or completely replacing the InGaAs channel with a material such as InP,
which inherently has reduced magnitudes of negative differential mobility. These design
rules are inherently vague because Gunn domain formation in HFETs is a twodimensional, dynamic phenomena which makes a quantitative analysis of the physics very
difficult. Nevertheless, with attention to these principles, it is possible to minimize the
probability of the occurrence of undesirable Gunn phenomena in power HFETs.
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103
4 .4 .
References
[4.1]
T. Windhom, L. Cook, and G. Stillman, "The electron velocity-field characteristic
for n-Ino.53Gao 47AS at 300 K", IEEE Electron Device Lett., vol. 3, pp. 18-20,
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[4.2]
K. Hess, Advanced Theory o f Semiconductor Devices. Englewood Cliffs,New
Jersey: Prentice-Hall, 1988, pp. 95-103.
[4.3]
C. Kittel, Introduction to Solid-State Physics, 6th ed. New York: Wiley, 1986,
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[4.4]
G. Hobson, The Gunn Effect. London: Oxford, 1974, pp. 3-20.
[4.5]
N. Shikegawa, T. Furuta, and K. Arai, "High-field electron-transport properties in
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[4.7]
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K. Yamaguchi, S. Asai, and H. Kodera, "Two-dimensional numerical analysis of
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[4.10] R. Engelmann and C. Liechti, "Bias dependence of GaAs and InP MESFET
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[4.12] E. Scholl, "Theory of oscillatory instabilities in parallel and perpendicular transport
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[4.13] J. Laskar, A. Ketterson, J. Baillargeon, T. Brock, I. Adesida, and J. Kolodzey,
"Gate-controlled negative differential resistance in drain current characteristics of
AlGaAs/InGaAs/GaAs pseudomorphic MODFETs," IEEE Electron Device Lett.,
vol. 10, pp. 528-530, 1989.
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[4.14] J. Laskar, J. Bigelow, J. P. Leburton, and J. Kolodzey, "Experimental and
theoretical investigation of the dc and high-frequency characteristics of the negative
differential resistance in pseudomorphic AlGaAs/InGaAs/GaAs MODFETs," vol.
39, pp. 257-263, 1992.
[4.15] W. Kruppa and J. Boos, "Observation of dc and microwave negative differential
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[4.16] s. Sze, Physics o f Semiconductor Devices. New York: Wiley, 1981, p.96.
[4.17] L. Palmateer, P. Tasker, W. Schaff, L. Nguyen, and L. Eastman, "dc and rf
measurements of the kink effect in 0.2 |im gate length AlInAs/GalnAs/InP
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[4.18] Y. Chen, D. Radulescu, G. Wang, F. Najjar, and L. Eastman, "Observation of
high-frequency high-field instability in GaAs/InGaAs/AlGaAs DH-MODFET's at K
band," IEEE Electron Device Lett., vol. 9, pp. 1-3,1988.
[4.19] E. Abbott, M. Lee, R. Mand, M. Sweeny, and J. Xu, "A quantum gatecurrent
model," IEEE Trans. Electron Devices, vol. 40, pp. 1022-1024,1993.
[4.20] R. Dottling and E. Scholl, "Travelling domains in modulation-doped GaAs/AlGaAs
heterostructures," in Negative Differential Resistance and Instabilities in 2-D
Semiconductors. New York: Plenum, 1993, pp. 179-188.
[4.21] M. Littlejohn, K. Kim, and H. Tian, "High-field transport in InGaAs and related
heterostructures," in Properties o f Lattice-matched and Strained Indium Gallium
Arsenide. London: INSPEC, 1993, pp. 107-116.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
105
CHAPTER 5. FABRICATION OF HIGH-POWER MICROWAVE HFETs
5 .1 .
In tro d u ctio n
In previous chapters, many issues have been addressed relating to the design and
characterization of high-power HFETs, including measurement techniques and fundamental
concepts of device physics. Now another issue must be addressed: design and fabrication
techniques which can be used to optimize the power performance of InP-based HFETs at
high frequencies.
As was mentioned at the end of Chapter 2, although InAlAs/InGaAs HFETs have
proven to be the fastest devices for small-signal amplification at room temperature [5.1] and
[5.2], these devices suffer from poor breakdown characteristics, which hinders their
performance for large-signal amplification. The Schottky barrier height of the gate metalInAlAs interface is on the order of only 0.65 eV, and the overall contact quality is often
significantly less than ideal [5.3] and [5.4]. In addition, the low bandgap of InGaAs leads
to large levels of impact ionization [5.5] and [5.6]. From the discussion in Section 2.3.2,
it is clear that the combination of these two problems causes the breakdown voltages in
these devices to be low [5.7] and [5.8].
In order to increase the breakdown voltages of HFETs fabricated on layer structures
grown by molecular beam epitaxy (MBE), the AlAs mole fraction is often increased in the
InAlAs Schottky layer to a value greater than the lattice-matched value of 0.48 [5.9] and
[5.10]. This increase has the effect of improving the Schottky barrier height and, hence,
increasing the breakdown voltage. However, for layer structures grown with metalorganic chemical vapor deposition (MOCVD), this technique is not as attractive, since the
A1 content in even lattice-matched InAlAs has been known to cause high levels of
background doping when this growth technique is used, which results in poor Schottky
characteristics [5.11]. Hence, for MOCVD-grown layer structures, alternatives must be
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
106
investigated. Other techniques which have been used to increase the breakdown voltage in
HFETs have included novel junction-modulated HEMTs (JHEMTs) with regrown ohmic
contacts [5.12], use of an AlxGayIni-x.yP Schottky contact layer [5.13] and [5.14], or
asymmetric gate recess [5.15]. These methods all have disadvantages. The disadvantage
of the JHEMT design is that regrowth is required to obtain the best devices. Also, growing
AlxGayIni-x-yP Schottky layers can prove to be troublesome; devices with such layers tend
to display inconsistent and/or nonreproducible behavior [5.16]. The asymmetric gate
recess design is a reasonable alternative but usually requires an additional fabrication step.
In this chapter, several issues involving high-power microwave HFET design will
be investigated, with emphasis on techniques which are compatible with the MOCVD
growth process. First, questions involving vertical scaling will be addressed. Second, a
unique electron-beam resist process to simplify asymmetric gate recess, which involves
horizontal scaling concepts, will be presented. Finally, the plausibility of using InP as a
channel material will be assessed by examining issues such as ohmic contact formation and
the effect of using asymmetric gate recess on such devices. Furthermore, results from
power measurements on symmetrically and asymmetrically recessed InP-channel
MODFETs and MISFETs will be reported and evaluated.
5 .2 .
5 .2 .1 .
V ertic al S calin g Issues
B a c k g ro u n d
A key design issue in the fabrication of HFETs is the vertical distances of the
contacts from the channel and/or the channel charge donors. If a selective gate recess etch
and a thin cap are used, the distance between the gate and the channel is very nearly the
same as the distance between the drain or source contact and the channel. When an InGaAs
channel and InAlAs barrier layer are used, it is usually a simple matter to obtain low contact
resistances at the drain and source by alloying the ohmic contacts as long as the barrier
layer thickness is reasonably low (on the order of a few hundred angstroms). The primary
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
107
issue of interest is, therefore, the effect of the vertical distance between the gate and the
channel.
It has been well established that the channel pinchoff voltage becomes less negative
as the distance between the gate and the channel decreases [5.17].
Perhaps more
importantly, the transconductance is inversely proportional to the gate-channel separation
[5.18]. In addition, undesirable short-channel effects are removed when this separation
distance decreases [5.19]. Hence, as the gate-channel separation decreases, the charge
modulation properties improve, which plays a role in determining the high-frequency
characteristics of the device [5.20]. For this reason, a small gate-channel separation can be
desirable.
For power devices, however, there is the additional issue of obtaining a high gatedrain breakdown voltage, i.e., minimizing the level of reverse gate leakage current. This
leakage current can, in principle, travel via the surface states of the barrier layer between the
gate and the drain; however, for many typical layer structure configurations, the major
component of gate-drain current is the field- or thermionic field-emission (i.e., tunneling or
thermally-assisted tunneling) of electrons from the gate through the barrier layer to the
channel [5.7] and [5.21]. These electrons enter the channel with excessive kinetic energy
and are further accelerated by the high field region on the drain edge of the gate [5.22].
This phenomenon leads to impact ionization and even larger current levels [5.23].
The reverse gate leakage current density due to tunneling through the barrier layer is
given by the following approximate expression [5.24]:
oo
Jleak = \ N ( E jL)P(E1 ) d E 1
0
where
(5.1)
represents the kinetic energy of an electron associated with motion perpendicular
to the heterointerface. N(E±) is an effective "tunneling density of states" function and
P(E±) is the tunneling probability, with
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
108
/
4 ™ chanQkT
\ Ef - E 1 - ( V gate- V chan) y
1 + exp
kT
J
( 5 .2 )
v
■j2mbr[Ec( j ) - E ± ]
(5.3)
Here mchan and mbr are the electron effective masses in the channel and barrier material,
respectively; £ /is the Fermi energy; Vgate and Vchan are the gate and channel voltages,
respectively; tbr is the barrier layer thickness; and Ec(x) is the energy of the conduction
band edge in the barrier layer, which varies as a function of depth into the material.
Close inspection of (5.1)-(5.3) reveals that the tunneling component of the reverse
gate current will increase as the barrier layer thickness decreases (i.e., as the gate-channel
distance decreases) and as the gate-channel bias becomes more negative. Therefore, if the
gate-drain breakdown voltage is to be maximized, it is desirable to have a thick barrier
layer. However, since a thicker barrier layer results in reduced modulation efficiency, not
to mention introducing undesirable short channel effects [5.19], a compromise must be
made and a barrier layer thickness found which allows good charge modulation properties
without excessive leakage current.
5 .2 .2 .
D ependence o f dc ch a ra c te ristic s on b a r r ie r thickness
A study was performed to experimentally determine the effects of barrier layer
thickness on actual HFET performance. Figure 5.1 illustrates the five different layer
structures used, all grown by organometallic vapor phase epitaxy (OMVPE). As shown in
the diagram, the layer structures were identical except that the thickness t of the top layer of
undoped InAlAs was varied. Values of 7.5 nm, 10 nm, 15 nm, 22.5 nm, and 500 nm
were used. In actuality, layer structure 5, which had t = 500 nm, did not have donor,
spacer, channel, or buffer layers grown, since these would have been too far away from
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109
1 0 n m n + -In G a A s (> 5 x 1 0 ^ c m " ^ )
Structure
I
1
2
3
4
5
7.5 nm
10 nm
15 nm
22.5 nm
500 nm
i- I n A lA s , t h ic k n e s s = t
5 n m n - I n A lA s
3 .5 n m
i- I n A lA s
20 nm
i- I n G a A s
10 n m
i- I n A lA s
F e -d o p e d I n A lA s (2 5 n m )
lnP:Fe (25 nm)
S .I . In P
Fig. 5.1. Schematic of layer structures used for vertical scaling study.
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110
the surface to have any effect. A selective citric acid-based wet etch was used for gate
recess to remove the InGaAs cap with minimal etching into the InAlAs [5.25]. The
0.25 jlm gates were defined using electron beam lithography, and the drain-source
spacings were all 2 Jim. Device widths were 100 |im.
Figure 5.2(a) illustrates the reverse gate leakage current characteristics of the
devices. It is clear from the diagram that the leakage current decreases as the gate becomes
more distant from the channel. Figure 5.2(b) summarizes the gate-drain breakdown
voltages, defined at drain current densities of 1 mA/mm, as well as the peak
transconductances of the devices for the various values of t. Note that even with
t = 500 nm, the device still breaks down due to surface leakage; therefore, this device
represents the minimum achievable leakage without any special processing at the surface of
the device.
5 . 2 . 3 . D ependence o f m icrow ave c h a ra c te ristic s on b a r r ie r th ick n ess
Figure 5.3(a) is a plot of the high-frequency figures-of-merit for the various
devices. It can be seen that the t = 10 nm and t = 15 nm devices have comparable values of
f f and /max- Inspection of Fig. 5.3(b), which displays the sums of the gate-source
capacitance, Cgs, and the gate-drain capacitance, Cgd, as well as the intrinsic highfrequency transconductances of the devices, offers some insight. The drain and source
resistances of these devices did not differ significantly; therefore, the effects of these
parasitics on f j and/max did not change from device to device. Theoretically, the value of
f j decreases as the quantity (Cgs + Cgd) increases, but increases as the intrinsic
transconductance increases [5.26]. Figure 5.3(b) shows that the quantity Cgs + Cgd is
greater for the t = 10 nm devices than for the t = 15 nm devices, presumably because the
gate is closer to channel in the former devices and because the gate capacitances would be
expected to be roughly inversely proportional to the gate-channel separation. However, the
effect of this difference in capacitances is offset by the fact that the intrinsic
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Ill
t =500 nm
-0.4
-
0.6
t=15 nm
t = 7.5 nm
J t =22.5 nm
-
0.8
t = 10 nm
9
-8
-7
-6 -5 -4 -3 - 2 - 1 0
G ate-to-drain voltage (V)
1
(a)
1200
7
1000
CD
800
600
c
2 2
TJI
CD
CO 1
CD
400
200
E
E
co
E,
CD
O
c
eg
o
3
T3
C
o
o
w
c
(0
ko
TZ>
E
3
E
0
15
gate-dopant separation, t (nm)
25
(b)
Fig. 5.2. (a) Reverse gate I-V characteristics and (b) gate-drain breakdown voltages
and maximum DC transconductances for MODFETs fabricated on layer structures
with different gate-to-dopant distances.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
112
180
160
140
N 120
o
100
o>.
c
©
3 80
cr
© 60
X
40
®
20
/m a x
0
15
25
gate-dopant separation, t (nm)
(a)
o
105
180
TO3) 100
160
eain 9 5
+
O
<n
©
o
c
■©
*—
*
o
©
90
85
120
80
100
CL
©
o
©
15
O)
o
E
3
C/D
cr
75
70
o>
65
60
5
15
25
c
gate-dopant separation, t (nm)
(b)
Fig. 5.3. (a) High frequency figures-of-merit and (b) sum of gate
capacitances and high frequency transconductances vs. gate-dopant
separation for 100 |im-wide InGaAs/InAlAs MODFETs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
113
transconductance of the t = 10 nm devices is also greater than that of the t = 15 nm devices.
This offset is a result of the fact that the transconductance is also inversely proportional to
the gate-channel separation [5.18]. It is now apparent why the values of/7 are similar for
the two sets of devices; the transconductances and gate capacitances are scaling in a similar
fashion.
When the value of t was increased from 15 nm to 22.5 nm, however, the resulting
decrease in transconductance tended to dominate, possibly due to short-channel effects
[5.24]; and hence, a slightly lower f j was observed for these devices (see Fig. 5.3(a)).
When t was decreased from 10 to 7.5 nm, there was a larger drop in /7, which may be due
to increased tunneling from the gate to the channel. Because the short-circuit current gain
h2i is defined as the ratio of the output current to the input current when the drain and
source are shorted, it is apparent how an increase in gate current due to tunneling would
decrease h2i at all frequencies and, hence, decrease f f . The existence of this parallel
leakage path between the gate and the channel tends to make the small-signal circuit model
shown in Fig. 3.4 invalid, which explains the seemingly strange values of Cgcj + Cgs and
gm for the t = 7.5 nm devices in Fig. 5.3(b). One final interesting observation from
Fig. 5.3(a) is th at/max does not change significantly with t, possibly because the value of
/max has a relatively complicated dependence on several different variables, which is
somewhat different than the dependence o f/7.
Thus, it is evident that for this layer structure configuration, the value of t should be
in the range of 10 to 15 nm. Devices with values of t below this range tend to have lower
breakdown voltages and lower values o f /7, whereas devices with values of t above this
range tend to exhibit short-channel effects which decrease/p. Although the optimum range
of t will vary numerically with different types of layer structures, such an optimum range
does exist on a qualitative level for any HFET layer structure that is reasonably similar to
the layer structures used here.
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114
5 .3 .
A sym m etric Gate Recess
5 .3 .1 . C oncept
As was mentioned in Section 5.1, InAlAs/InGaAs HFETs consistently exhibit low
gate-to-drain breakdown voltages despite their superior high frequency performance. Two
main cap layer designs have been used in fabrication of these devices to improve these
characteristics. The first design is the use of an undoped or depleted cap [5.27], which has
the adverse effect of increasing both the drain and source resistances. To preserve the
high-frequency characteristics of these devices, an alternate design, often called a "double­
recess" or asymmetric recess design, may be used [5.28]. This design features a wide
recess trench in a doped cap which extends farther on the drain side of the gate than on the
source side and is, therefore, asymmetric about the gate (see Fig. 5.4), which has the
advantage of preserving a low source resistance while increasing the drain resistance to the
desired value. However, this design usually requires a separate lithography step to define
the asymmetric recess trench. For this reason, a multilayer electron beam resist process
was developed which enables asymmetric recess to be performed and a submicron T- or Tshaped gate to be metallized using a single lithography step. This process is described in
the Section 5.3.2.
5 .3 .2 . A four-layer electron beam resist process for asym m etric recess
Figure 5.5(a) shows the desired resist profile for producing a T- or T-shaped gate
in an asymmetric recess trench. Figure 5.5(b) illustrates the gate metal and recess trench
which would be produced with such a resist profile. The extent of the recess on the drain
side, labeled Ld in Fig. 5.5(b), is greater than the extent of the recess on the source side,
labeled Ls. As is evident in Fig. 5.5(a), these recess dimensions are determined primarily
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115
n warn
r BSSsErhHHSMHBBHjMn
91
Fig. 5.4. Cross section of resist structure for gate region of FET,
showing wide recess trench on drain side of the gate.
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116
A
Layer 1
TA;
m
TB
Layer 2
Layer 3
Layer 4
4-layer
— resist
::ri c
I
device layers
(a)
Lo
\< ^
r>
&
TB
TA
jO
O :•
■
•
Source
cap
|||1 |
gate
metal
cap
Drain—>
device layers
(b)
Fig. 5.5. Resist profile dimensions for four-layer resist structure (a)
before metallization and liftoff; (b) after liftoff.
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117
by the layer 4 resist The size of Ld can be made larger than the size of Ls by performing a
weak exposure on the drain side in addition to the main exposure performed to create the
gate footprint. The layer 3 resist determines the gate footprint length, Lg, and the layer 1
resist defines the gate metal dimensions TA and TB. The layer 2 resist assists in liftoff.
It can be concluded from this discussion that the resist layers which are used must
have certain contrasts and sensitivities to obtain the appropriate multilayer resist profile.
Figure 5.6 shows the resist thickness versus the area exposure dose for each of the four
layers of resist. The resist thickness is normalized to 400 nm, which was the thickness of
each of the resist layers before exposure and development.
From these plots, the
sensitivity and contrast for each of the resists were calculated. These values are listed in
Fig. 5.6. Note that the layer 3 resist has the highest sensitivity value. This value is
essential, since it is the layer which defines the narrow gate footprint length. Layer 4 has
the lowest sensitivity value, which enables a significant undercut underneath the layer 3
resist and, hence, a recess trench which extends beyond the gate footprint. Layer 1 has an
intermediate sensitivity to provide a T or T shape to the gate metal. Layer 2 has a lower
sensitivity value than layer 1 to provide an undercut profile suitable for liftoff.
To characterize the dependence of the various resist profile dimensions on the
electron beam exposure parameters, several gates were written and developed and their
cross-sectional profile dimensions measured using an SEM. Gates were written by first
performing a strong, mainline exposure of 5.0 nC/cm followed by a weaker area exposure
on the drain side (i. e., a sidelobe exposure). No sidelobe exposure was performed on the
source side. The sidelobe area dose was varied from 80 to 130 pC/cm2, and the mainlineto-sidelobe distance was varied from 0 to 0.15 pm. The latter distance was defined to be
the distance between the edge of the mainline and the edge of the sidelobe area exposure.
Hence, even with a mainline-to-sidelobe distance of zero, there was no overlap between the
two exposures. In addition, two different sidelobe widths of 0.3 and 0.5 pm were used.
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Normalized resist thickness
118
1
1
w
C
D
c
V)
0.8
o
Resist layer 1
0.6
CO
0.6
= 80 pC/cm'
Contrast = 4.9
"co
Contrast = 5.7
E 0.2
o
0
0
10
100
10
1000
100
Dose (|iC/cm2)
D ose (jiC/cm2)
(a)
(b)
1
Normalized resist thickness
Sensitivity
C
D
TJ 0.4
C
D
N
= 120 pC/cm'
0.2
Resist layer 2
'co
Sensitivity
0.4
0.8
co
1000
1
C
D
c
CO
0.8
‘
o
x:
Resist layer 3
0.6
Resist layer 4
Sensitivity
w
’co
Sensitivity
= 56 (aC/cm
C
D
C
D0.4
_N
= 174 pC/cnf
0.4
0.8
Contrast = 5.6
To
0.2
0
Contrast = 5.7
0.2
0
10
100
1000
10
100
D ose (nC/cm2)
Dose (|iC/cm2)
(c)
(d)
Fig. 5.6. Normalized resist thickness versus dose for (a) layer 1; (b) layer 2; (c)
layer 3; and (d) layer 4 resists.
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1000
119
In all cases, the dimensions Ls and TB defined in Fig. 5.5(a) remained constant at
0.09 |im and 0.05
pm ,
respectively. Figure 5.7(a) illustrates the dependence of the
dimension Ld on sidelobe dose for various mainline-to-sidelobe distances and with a
sidelobe width of 0.3
|J.m.
The point at which Ld = Ls = 0.09
pm
corresponds to a
symmetric recess and is marked on the graph. Figure 5.7(b) is similar to Fig. 5.7(a), but
for a sidelobe width of 0.5 pm. The 0.5
pm
sidelobe exposures did not produce profiles
that resembled Fig. 5.5(a) for sidelobe doses of 120 and 130 pC/cm2; therefore, the data
for these exposures are not shown. Similarly, for a sidelobe width of 0.3 pm and a
sidelobe dose of 130 pC/cm2 , the resist profile was not useful if the mainline-to-sidelobe
distance was greater than 0.1
expected, the 0.5
pm
pm .
Certain trends are evident from Fig. 5.7. As would be
sidelobe generally creates a larger value for Ld than the 0.3 pm
sidelobe for a given dose and distance. Also, for a given dose and width, the general trend
is an increase in Ld as the distance is increased from 0 to 0.1
pm ,
but then a sharp decrease
in Ld as the distance is increased farther to 0.15 pm. For a distance of 0 to 0.1
pm ,
the
combined proximity dose from the sidelobe exposure and the main line exposure is enough
to cut through the region of the layer 4 resist immediately adjacent to the footprint even
though this region was not directly exposed. This proximity effect enables a large undercut
to be established. At a distance of 0.15
pm ,
however, the sidelobe exposure is too remote
and, therefore, the proximity dose too small to effectively cut through the layer 4 resist
adjacent to the gate footprint, which results in a much smaller undercut.
Figures 5.8(a) and (b) are similar to Figs. 5.7(a) and (b) but show the dependence
of the gate length, Lg, on the various exposure parameters. There is only a slight increase
in Lg with an increase in dose for a given sidelobe width and mainline-to-sidelobe-distance.
Also, Lg does not sharply increase when a 0.5
pm
instead of a 0.3
pm
sidelobe width is
used. Finally, there is a notable decrease in Lg as the sidelobe distance is increased from 0
to 0.1
pm ,
as opposed to the increase in Ld that occurs under these conditions (see Fig.
5.7). These are favorable results, since the process allows Ld to be increased without a
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120
Symmetric metal profile
I
Gate-to-sidelobe
distance:
£ 3 0.15 pirn
H I 0.1 pm
H
0.05 pm
Bffi 0 pm
Sidelobe width=0.3 pm
0
0.1
i I i i—i—i—
i i | i i
0.2
0.3
0.4
Ld (urn)
0.5
0.6
(a)
Symmetric metal profile
Gate-to-sidelobe
distance:
£ 3 0.15 pm
H I 0.1 pm
S 95
0.05 pm
0 pm
Sidelobe width=0.5 pm
0.2
0.3
Ld (pm)
(b)
0.4
Fig. 5.7. "Lj" resist profile dimension as a function of sidelobe dose at various mainlineto-sidelobe distances for a sidelobe width of (a) 0.3 pm; (b) 0.5 pm.
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121
Symmetric profile
Gate-to-sidelobe
distance:
130
_________________
£ 3 0.15 pm
§H 0.1 pm
£ 110
H
«> 95
Sidelobe widt i = 0.3 pm
0.05 pm
M °P m
Lg (Hm)
Symmetric profile
*
Gate-to-sidelobe
distance:
£ 3 0.15 pm
H
0.1 pm
|H 0.05 pm
|
0 pm
Sidelobe width=0.5 pm
Lg (pm)
(b)
Figure 5.8. "L " resist profile dimension as a function of sidelobe dose at various
mainline-to-sidelobe distances for a sidelobe width of (a) 0.3 pm; (b) 0.5 pm.
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122
significant increase in Lg; i.e., the process allows the extent of the recess on the drain side
to be increased without a significant increase in gate length. The smallest value of Ld is
obtained for a mainline-to-sidelobe distance of 0.15 |im, but in many cases this is because
the sidelobe exposure is too remote to have any effect on the resist profile. For example,
the smallest value of Lg that can be achieved is 0.15 (im. However, as indicated in Figs.
5.8(a) and 5.8(b), for this value of Lg, the resist profile is symmetric, which implies that
the sidelobe exposure was too distant.
Another point of interest in fabricating gates is the profile of the gate metal. It is
desirable for the gate to have a T or T shape in order to increase the cross-sectional area and
to lower the gate resistance. A low gate resistance is important in obtaining a large value of
/max. since it is a significant portion of the input resistance [5.29]. For this reason, the
dimension TA was measured for all of the exposure parameters, as shown in Figs. 5.9(a)
and (b). When TA = TB = 0.05 |im, the gate has a T-shaped profile. This point is shown
on the charts and corresponds to the cases for which the sidelobe exposure was too weak
and/or remote to cut through the layer 1 resist. For mainline-to-sidelobe distances of 0 and
0.05 (im, the sidelobe exposure always cut through the layer 1 resist and created a Tshaped profile.
Figure 5.10(a) is a scanning electron micrograph of the four-layer resist profile for
a gate written with a sidelobe dose of 95 |iC/cm2, a mainline-to-sidelobe distance of 0.1
(im, and a sidelobe width of 0.5 Jim. The 60 nm InGaAs cap has been selectively
recessed. Figure 5.10(b) is a micrograph of this gate after metallization and liftoff.
The electron-beam resist process presented here is very useful for fabricating
devices with various values of Ld, which can be accomplished by varying the exposure
parameters. With this capability, it is relatively simple to explore the effects of asymmetric
recess on device performance and determine which value of Ld is optimum for a particular
application. This procedure will be done in Section 5.4 for both InGaAs- and InP-channel
MODFETs.
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123
Symmetric metal profile
i
Gate-to-sidelobe
distance:
0.05
i i i | r i i ■! | i r r i '‘| 1i i t i 1 i i
0.1
0.15
0.2
0.25
TA (pm)
0.15 urn
H
0.1 pm
H
0.05 pm
y i 0|im
Sidelobe width=0
0
□
0.3
(a)
Symmetric metal profile
I
Gate-to-sidelobe
distance:
110
0.15 pm
<
wo
O
XI
o
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•o
@
0.1 pm
H
0.05 pm
■
0 pm
Sidelobe width=0.5 pm
0
0.05
0.1
0.15
TA (pm)
0.2
0.25
0.3
(b)
Fig. 5.9. "TA" resist profile dimension as a function of sidelobe dose at various mainlineto-sidelobe distances for a sidelobe width of (a) 0.3 pm; (b) 0.5 pm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
124
(b)
Fig. 5.10. (a) Cross section of electron beam resist structure for asymmetric gate recess
after exposure, development, and selective gate recess. The sidelobe dose was 95 pC/cm2,
the mainline-to-sidelobe distance was 0.1 pm, and the sidelobe width was 0.5 pm.
(b) Resulting gate metal and recess profile after metallization and liftoff.
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125
5 .4 .
InP as a Channel M aterial
5 .4 .1 . C oncept
Because InGaAs has a bandgap of only 0.75 eV, InGaAs channels have the
inherent problem of impact ionization at relatively low fields. Although asymmetric recess
can help to circumvent this problem, it is worth investigating the possibility of using a
different channel material for InP-based HFETs which possesses more favorable
breakdown characteristics but which still has some of the excellent transport properties of
InGaAs. A review of data in literature reveals that InP itself has a clear potential for
superior performance as a channel material in high-power applications due to its inherent
properties, which include a large electron saturation velocity [5.30], high breakdown
voltage [5.31], and large electron velocity at high electric fields [5.32]. Table 5.1 is a
compilation of data for InGaAs, InP, GaAs, and InAlAs. As is evident, at a given donor
density, InP has a very high peak electron velocity, as does InGaAs. However, due to the
lower mobility of InP, the electric field at which this velocity occurs will always be higher
than that in InGaAs. Also, InP has a higher bandgap than InGaAs, which implies that a
given level of impact ionization will occur at a higher field than that in InGaAs. These
qualities, along with the greater thermal conductivity of InP, make it appear as if an InP
channel would have advantages over an InGaAs channel for power applications.
5 .4 .2 . InP-channel M ODFETs with nonalloyed ohmic contacts
The simple desire to fabricate InP-channel HFETs and the actual ability to fabricate
such devices are unfortunately two different concepts. Numerous attempts have been made
in various industries and universities to fabricate InAlAs/InP MODFETs with simple
alloyed ohmic contacts with no success due to the inability to achieve low ohmic contact
resistances with an InP channel [5.33].
For this reason, InP-channel MODFETs were fabricated on two different layer
structures that were intentionally designed to enable nonalloyed ohmic contacts to be
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126
Table 5.1. List of material properties for four different compound semiconductors at room
temperature.
P roperty at Room T em perature
In G aA s
In P
G aA s
InA iA s
Lattice constant (nm)
0.586
0.586
0.565
0.586
Energy bandgap (eV)
0.75
1.35
1.42
1.45
Conduction band discontinuity to InP (eV)
0.25
0
Electron effective mass to free mass ratio
0.043
0.0796
0.0665
0.077
Electron mobility at donor density of
7000
3200
4000
900
Thermal conductivity (W/(cm K))
0.05
0.74
0.46
___
Peak electron velocity at donor density of
2.6
2.5
1.7
1.3
0.55
0.52
0.33
0.5
0.25
1017 cm-3 (cm2/(Vs))
1017 cm’3 (107 cm/s)
T-L valley energy separation (eV)
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127
fabricated. The two heterostructures used were grown by organometallic vapor phase
epitaxy (OMVPE) on Fe-doped InP substrates and are illustrated in Fig. 5.11. Structure A
consisted of a 25 nm Fe-doped InP epitaxial layer, a 50 nm Fe-doped InAlAs layer, a 5 nm
undoped InAlAs buffer layer, a 40 nm undoped InP channel layer, a 5 nm undoped
InAlAs spacer layer, an n+ Si doping plane, a 15 nm undoped InAlAs barrier layer, and a
10 nm n+ InGaAs cap layer. In this layer structure, the drain and source metal pads were
in good ohmic contact to the InGaAs cap and relied on the ability of the electrons to tunnel
between the channel and the cap layer on either side of the gate. Structure B was identical
to structure A, except that the InGaAs cap was undoped and the InAlAs barrier layer was
18 nm with an n+ Si doping plane placed 3 nm below the cap layer into the InAlAs layer to
enhance tunneling to the channel and, thereby, lower the source and drain resistances.
Hall measurements were performed; the structures had electron mobilities of
2250 cm2/(Vs) and sheet electron densities of 1.6 x 1012 cm' 2 at 300 K. Mobilities and
sheet electron densities at 77 K were 10,000 cm2/(Vs) and 1.5 x 1012 cm'2, respectively.
Device isolation was achieved by mesa etching. Source and drain ohmics were
formed using AuGe/Ni/Au. Electron beam lithography was used to define the 0.32 pm
gates in a trilayer resist system. Gate recess was performed using wet etching. For the A
devices, a selective gate recess was performed in a citric acid/hydrogen peroxide solution
[7], while a nonselective etch (H3PO4/H2O2/H2O) was used to recess the gates on the B
devices. For the latter, care was taken to recess just beyond the top delta-doping plane in
the InAlAs. For the T-shaped gates, Ti/Au metallization was used. All devices had a
channel width of 100 pm and a source-drain distance of 2 pm.
Figure 5.12(a) shows the extrinsic transconductance gm and drain current of a
typical B device at a drain-source voltage Vds of 2 V. The device has a peak gm of
800 mS/mm at a current density of 360 mA/mm. Also, it is shown in Fig. 5.12 that the
device maintains a gm of over 500 mS/mm over a gate voltage range of -250 to 500 mV,
which corresponds to a current density of 85 to 630 mA/mm. In general, the peak gms
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128
Structure A:
Njj > 5 x 10*8 cm‘3
10 n m In G a A s
omitted i...n . f
structure A |
3A L
/ « . . * . * x
<3 nm '-InAlAs)
n-(n+
+ delta doping plane for Structure B )
<---------
—
— - __
B:
present only in
structure B
15 n m i- I n A lA s
—n+ delta doping plane — ---------------
5 nm
i- I n A lA s
20 nm
i- I n G a A s
10 n m
i- I n A l A s
F e -d o p e d I n A lA s (2 5 n m )
lnP:Fe (25 nm)
S .I . I n P
Fig. 5.11. Schematic of layer structures used for non-alloyed InP-channel
MODFETs.
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129
700
800
600
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600
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400
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(a)
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Frequency (GHz)
(b)
Fig. 5.12. (a) Drain current and transconductance of a B device, (b) Shortcircuit current gain of a B device with extrapolation to a cutoff frequency of
92 GHz.
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130
ranged from 775 to 805 mS/mm. To date, these are the highest dc transconductances
reported for InP-channel devices. A typical output conductance, gd, of 30 mS/mm was
measured for these devices, which translates to an average transconductance-to-output
conductance ratio of over 25.
The A devices had typical peak extrinsic transconductances of 520 mS/mm at a
current density level of 200 mA/mm. In general, the peak transconductances ranged from
490 to 540 mS/mm. While still relatively high for InP channel devices, these values are
lower than those of the B devices due to the higher source and drain resistances of the A
devices. Source and drain resistances of the B devices were typically 0.36 Q-mm and were
substantially lower than the 0.93 Q.-mm source and drain resistances of the A devices.
Therefore, it is obvious that the additional delta-doping plane present in Structure B greatly
reduces the source and drain parasitic resistances of the devices.
The breakdown characteristics of these devices were also measured. With the gate
biased for the maximum transconductance, most of the A devices could not sustain a drainto-source bias over 8.5 V and most of the B devices could not sustain a drain-to-source
bias over 4.5 V. For both sets of devices, the drain-to-source bias limitation was due to
gate-to-drain breakdown. The bias limitation on the B devices is lower than the limitations
reported by Aina et al. [5.34] for their InP channel MODFETs and Matloubian et al. [5.10]
for their InGaAs channel MODFETs and is due to the proximity of the top delta-doping
plane to the gate metal. This limitation could be remedied by a wider recess trench on the
drain side of the gate. In addition, the bias capability on both sets of devices is believed to
be limited by the poor Schottky contact on the InAlAs that is further degraded by the
significant residual doping in the InAlAs donor layer, which is ~3 x 1016 cm '3. Such a
high background doping concentration can significantly increase the reverse leakage current
in the gate Schottky contact [5.11]. Therefore, a reduction in the background doping level
of InAlAs and obtaining a wider recess region on the drain side should significantly
improve the gate-to-drain breakdown characteristics of the devices. This and other effects
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
131
of asymmetric recess performed on InP-channel MODFETs with nonalloyed contacts will
be demonstrated in Section 3.4.3.
Scattering parameter measurements were performed on the devices over a frequency
range of 1 GHz to 35 GHz using a Cascade Microtech probe station and an HP 8510
network analyzer. The equipment was calibrated using a line-reflect-reflect-match (LRRM)
calibration routine. Figure 5.12(b) shows the short-circuit current gain, h2i, of a typical B
device determined from s-parameter measurements with a drain-to-source bias of 2 V.
Extrapolation of the steady 20 dB/decade rolloff yields an f r of 92 GHz. This is the
highest value ever reported for an InP-channel MODFET.
Figure 5.13(a) illustrates the dependence of/7 on drain-to-source bias for a typical
B device. As can be seen, the maximum f r is actually 95 GHz at 1.2 V, with an f j of 92
GHz at 2 V and an essentially linear decrease in f r with drain bias to 77 GHz at 4 V. This
decrease is substantially less than the decrease observed in the highest-performance InGaAs
channel power MODFETs [5.10]. This is consistent with what Aina et al. reported [5.34]
and is likely due to the slower variation of the electron velocity-electric field relation in InP
[5.30]. The current density is also shown on the same plot from which it can be inferred
that there is no evidence of channel breakdown at these voltages.
Figure 5.13(b) shows a similar plot for an A device. The peak value o f /7 is
75 GHz at 2 V which is substantially lower than the/7 of the B devices due to the larger
source and drain parasitic resistances of the A devices. Note, however, that the/7 of the A
device is essentially constant for drain-to-source voltages between 2 and 4 V, which is due
to the fact that a significant portion of each increment in the drain-to-source voltage is
dropped across the drain and source resistances, causing the increase in drain delay with
increasing external drain bias to be minimal. Therefore, at a drain-to-source voltage of 4 V,
the A and B devices have similar f r values.
Since these devices were potentially unstable over the frequency range of sparameter measurement, values fo r/max were determined by extrapolating the maximum
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132
100
400
90
5
350
80
300
o 70
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250
50
200 c
Device Group B
40
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100 Q
10
0
0
0.5
1 1.5 2 2.5
3
Drain-source voltage (V)
3.5
4
(a)
80
300
250
60
Device Group A
5.50
150 e
100 .S
3 20
5 10
0
0
0.5
1
1.5 2
2.5
3
Drain-source voltage (V)
3.5
4
(b)
Fig. 5.13. Unity current gain frequency and drain current versus drain-source
voltage for (a) a MODFET from Group B and (b) a MODFET from Group A.
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133
unilateral transducer gain versus frequency curve at a rolloff of 20 dB/decade. At a drainto-source voltage of 2 V, the values of / max were 108 and 120 GHz for the A and B
devices, respectively.
5 .4 .3 . Effects of asym m etric recess on M ODFET perform ance
Due to the poor breakdown characteristics of nonalloyed InP-channel MODFETs, it
was worthwhile to asymmetrically recess such devices using the electron beam resist
process characterized in Section 5.3. Although it was expected that this would enhance the
breakdown voltage of the devices, the effect of asymmetric recess on other device
characteristics had to be investigated to determine whether or not asymmetric recess was
desirable for nonalloyed InP-channel MODFETs. For this reason, symmetrically and
asymmetrically recessed InP-channel devices were fabricated and their characteristics
compared. In addition, in order to better understand the physics underlying the behavior of
those devices, symmetrically and asymmetrically recessed InGaAs-channel MODFETs with
alloyed ohmic contacts were fabricated for comparison.
5.4.3.1.
Device fabrication
The two MODFET layer structures were grown by organometallic vapor phase
epitaxy (OMVPE) on Fe-doped InP substrates and are illustrated in Fig. 5.14. The first
structure consisted of a 25 nm-thick Fe-doped InP epitaxial layer, a 25 nm Fe-doped
InAlAs layer, a 10 nm undoped InAlAs buffer layer, a 20 nm undoped InGaAs channel
layer, a 3.5 nm undoped InAlAs spacer layer, a 5 nm Si-doped InAlAs donor layer, a
10 nm undoped InAlAs barrier layer, and a 10 nm Si-doped InGaAs cap layer. The
second structure was similar except that the channel layer was an undoped InP layer. The
sheet electron density and electron mobility of the InGaAs-channel structure at 300 K with
the cap removed were 2.9 x 1012cm ' 2 and 9961 cm2/(Vs), respectively. The values
measured at 77 K were 2.7 x 1012 cm' 2 and 46,130 cm2/(Vs). For the InP-channel
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134
10 nm n+ InGaAs cap
10 nm S-InAlAs Schottky
5 nm n+ InAlAs Si doped
3.5 nm i-lnAIAs spacer
First set:
InGaAs channel
20 nm i-channel
Second set:
InP channel
10 nm i-inAIAs buffer
25 nm Fe-doped InAlAs
25 nm Fe-doped InP
InP substrate
Fig. 5.14. Layer structures used in asymmetric recess study.
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135
structure, the sheet electron density and mobility were 2.1 x 1012 cm'2 and 3947 cm2/(Vs)
at 300 K and 2.1 x 1012 cm'2 and 17,402 cm2/(Vs) at 77 K.
Device isolation was achieved by mesa etching and sidewall recessing [5.35] of the
InGaAs channel layer using selective etching in citric acid solutions [5.25]. Ohmic contacts
were obtained using AuGe/Ni/Au, which was alloyed for the InGaAs-channel devices but
not for the InP-channel devices.
As was mentioned previously, standard alloying
techniques are not sufficient to obtain a direct ohmic contact to the channel in a conventional
InP-channel MODFET layer structure; in fact, alloying usually made the contact resistance
higher, which probably resulted from the loss of the ohmic contact to the highly doped cap.
Therefore, the ohmic contacts of InP-channel devices were left nonalloyed, which resulted
in good contact between the InGaAs cap and ohmic metal. Hence, for the InP-channel
MODFETs, the channel charge reached the surface drain and source contacts by tunneling.
The gate patterns were formed in multilayer resists using electron beam lithography at
40 keV and was followed by selective gate recessing [5.25]. The gate metallization was
Ti/Au with devices having channel widths of 100 [im and drain-to-source spacings of
2 urn.
Three sets of MODFET devices were fabricated: one set (Group 1) using a standard
trilayer resist and the other sets (Groups 2 and 3) with the new four layer resist process.
For Group 2 exposures, no additional sidelobe exposure was performed on the drain side.
However, for Group 3 devices, an additional sidelobe exposure on the drain side was
performed to yield a significant undercut in the bottom resist layer. Gate recess was
performed using a selective wet process in citric acid solutions. For devices having similar
layouts and ohmic metal thicknesses, the resist process is very reproducible.
The lateral extent of the recess on either side of the gate's footprint is summarized in
Table 5.2 for the three sets of devices. The recesses for Groups 1 and 2 devices were
symmetrical about the gate. For Group 1 devices, the undercut that occurred during gate
recess was not measurable in the scanning electron microscope. Hence, for these devices,
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136
Table 5.2. Characteristics of symmetrically and asymmetrically recessed MODFETs which
have either InGaAs or InP channels.
C hannel
ty p e
G roup
Resist
InG aA s
1
trilayer
process used
2
InP
!
3
a
2
llillll
4-layer, no
4-layer,
additional
additional
4-layer, no
4-layer,
additional
additional
exposure on
exposure on
exposure on
exposure on
drain side
drain side
drain side
drain side
0.15 pm
0.35 - 0.59
0.15 pm
0.31 - 0.57
trilayer
Extent of
recess toward
0 pm
drain, L(j
0 pm
pm
pm
Extent of
recess toward
0 pm
0.15 pm
0.15 pm
0 pm
0.15 pm
0.15 pm
0.26 pm
0.21 pm
0.21 - 0.27
0.26 pm
0.21 pm
0.21 - 0.27
source, Ls
Gate length
pm
Source
pm
3.9 Cl
4.2 Cl
4.2 C2
9.3 a
19.13 Cl
19.13 Cl
3.9 Cl
4.2 Cl
4.9 - 7 .6 Cl
9.3 Cl
19.13 Cl
35.9 - 41.9
resistance
Drain
resistance
Cl
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137
the extent of the recess on the source side, Ls, and the extent of the recess on the drain side,
Ld, were both equal to zero. For the Group 2 devices, Ls = Ld = 0.15 |im. For the Group
3 devices, Ls = 0.15 |im but Ld was varied by changing the sidelobe exposure parameters.
A close look at Table 5.2 also reveals that the gate footprint lengths did vary as well, from
0.21 (im to 0.27 (im. When comparing the devices, the slightly different gate lengths were
considered when it was necessary; however, since many of the effects of an asymmetric
recess occur between the gate and the drain or at the edge of the gate, the small variation in
gate length was not considered a significant issue.
5.4.3.2.
Direct current characteristics
The procedure for determining the source and drain resistances of the devices
was as follows. For Group 1 devices, a standard gated transmission line model (TLM)
process was used [5.36]. The gated TLM measurements were similar to standard TLM
measurements except that gates were recessed between the ohmic pads. The gated TLM
patterns were located on the same wafer as the MODFETs; therefore, the gate recesses of
the TLM devices and the FETs occurred simultaneously. The channel sheet resistance of
the layer structure as well as the source and drain resistances could be obtained from the
gated TLM data. Because this was the standard trilayer resist process, it could be assumed
that the drain and source resistances were equal due to symmetry.
Once the drain and source resistances of the Group 1 devices were obtained from
gated TLM measurements, drain I-V characteristics were obtained from the actual FETs
over a drain-to-source voltage range of 0 to 100 mV with the gate-to-source voltage fixed at
0 V. The drain I-V characteristic at this low voltage range was linear, and the inverse of the
slope was assumed to be equal to the sum of the drain, source, and channel resistances
[5.18]. The channel resistance could be calculated from the channel sheet resistance
(determined from the gated TLM measurements), gate length, and gate width, and was
found to be small compared to the drain and source resistances. The remainder of the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
138
resistance was due to the drain and source resistances, which again could be assumed to be
equal by symmetry. The values of the drain and source resistances found from this
technique are reported in Table 5.2 and were only 5% greater than the values obtained from
the gated TLM measurements. Hence, the drain I-V technique was presumed to be valid; it
was this technique that was used to measure device groups 2 and 3. The technique was
first used on the Group 2 devices for which it could be assumed that the drain and source
resistances were equal. The measurements were then performed on the Group 3 devices;
the source resistances of these devices could be assumed to be the same as the Group 2
devices since the weak sidelobe exposure on the drain side has no effect on the resist
undercut on the source side. Finally, the drain resistances of the Group 3 devices could be
determined.
The values for the source resistances are shown in Table 5.2. The cap removal on
the source side for Groups 2 and 3 had a much more severe effect on the source resistance
of the InP channel devices than the InGaAs-channel devices. This occurred because the
ohmic contacts of the InP-channel devices were not alloyed; therefore, much of the current
flow from the contacts to the channel occurred in the heavily doped cap. The symmetrically
recessed InP-channel FETs had normalized source and drain access resistances of 0.93 Qmm. This can be seen in Table 5.2, keeping in mind that the devices had channel widths of
100 (im. Because the contacts were nonalloyed, these access resistances were primarily
composed of the effective tunneling resistances between the cap and the channel.
Also listed in Table 5.2 are the ranges of drain resistance values for the Group 3
devices. Figure 5.15(a) displays a more detailed look at the drain resistances of the devices
versus the drain recess length, Ld, where the points Ld = 0 and Ld = 0.15 ^im correspond to
the Group 1 and Group 2 devices, respectively. For the InGaAs-channel devices, the drain
resistance seems to increase more rapidly for Ld > 0.38 pm, presumably because the area
of cap removal is getting significantly close to the metal drain contact for these devices and
the doped cap material which is closest to the contact is important for obtaining a low drain
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
139
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(b)
Fig. 5.15. (a) Drain resistance and (b) gate-drain breakdown voltage
vs.
for InGaAs-channel and InP-channel MODFETs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
140
resistance in a MODFET. The InP-channel devices showed a markedly different trend. The
drain resistance of these devices increased rapiaiy as Ld increased from 0 to 0.3 pm, at
which point the resistance seemed to saturate. This increase occurred because the drain and
source contacts were nonalloyed; hence, the highly doped cap adjacent to the gate was
necessary for the carriers to be able to tunnel efficiently down to the channel. By removing
the cap next to the gate, the effective tunneling distance increased, resulting in a much
higher drain resistance. Apparently, after the initial 0.3 pm of cap removal on the drain
side, there is negligible change in the tunneling properties when the cap is recessed further.
Figure 5.15(b) is a plot of the gate-drain breakdown voltage, BVg(j, defined at a
drain current of 1 mA/mm, of the devices as a function of Ld- The breakdown voltages
increase with Ld due to a reduction in the peak channel electric field at the drain edge of the
gate [5.27] as well as a reduction in the surface leakage current between the more distant
highly doped-cap and the gate metal. The increase in BVgd is especially large for the InPchannel devices. Figure 5.16(a) shows the reverse I-V characteristic between the gate and
the drain for different values of Ld for the InP-channel devices. The linear portion of the
curves is most likely the tunneling that occurs between the gate and the drain before the
channel is pinched off. Once the gate-drain voltage exceeds the pinchoff voltage, much of
the voltage drop occurs in the pinched-off region of the channel, and further increase in
reverse gate current as the applied voltage is made more negative is due mainly to increased
impact ionization in the channel as well as to surface leakage. This corresponds to the non­
linear region of the I-V characteristics.
Because the increase in the two-terminal breakdown voltage was significant in the
InP channel devices with large values of Ld, it was necessary to see if the device
breakdown characteristics had such a marked improvement when the MODFETs were
biased as three-terminal devices. Figure 5.16(b) is a plot of the drain current versus the
drain-source voltage at pinchoff for two different InP-channel devices with Ld = 0 and
0.57 pm, respectively. If the off-state drain-source breakdown voltage (BVds) is defined
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141
■ Lh = 0.57 p.m
| -0.2
£
E.
0.37 pm
~ -0.4
in
a
CD
"O
linear region
c -0 .6
CD
13
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Drain-to-source voltage (V)
10
(b)
Fig. 5.16. (a) Reverse I-V characteristics between gate and drain for InP-channel MODFETs.
(b) Drain I-V characteristics at pinchoff for two sets of InP-channel MODFETs.
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142
at 1 mA/mm of drain current, it can be seen that the asymmetric recess resulted in an
increase in BVds from 2.8 V to 9 V when Ld was increased from 0 to 0.57 (im. In fact,
close inspection revealed that for these devices, BVds was roughly equal to
IBVgdl + Vpinchoff. where the pinchoff voltage was on the order of -1 V in most cases. In
other words, even when biased as three-terminal devices, breakdown in the MODFETs
occurred between the gate and the drain, which is to be expected since it is in this region
that the high electric fields are present. The two- and three-terminal breakdown I-V
characteristics of the InGaAs-channel devices were similar in nature; for example, the
InGaAs-channel devices with Ld = 0 had values of 4.2 V and 3.4 V for BVgd and BVds,
respectively, while the devices with Ld = 0.59 (am had values of 8.1 V and 6.8 V for BVgd
and BVds, respectively.
The maximum current capabilities of the devices in the on-state were also of
interest. Figures 5.17(a) and 5.17(b) display the I-V characteristics of InP-channel devices
with Ld = 0 and 0.37 (im, respectively. From the plots, it is evident that the saturation
current levels for the asymmetrically recessed device are significantly lower than the
symmetrically recessed device. The InGaAs-channel devices showed a similar trend,
though not as severe. Figure 5.18(a) shows the decrease in the full channel current density
with increasing Ld for both the InGaAs- and InP-channel devices. Here, the full channel
current density was defined at a gate-source voltage of 400 mV and a drain-source voltage
of 1.25 V. Interpolation reveals that for the InGaAs-channel devices, if Ld is kept to
0.25 (tm or below, the full channel current will only drop 15% or less. In sharp contrast,
in an InP-channel device, an Ld of 0.25 (im would result in over a 50% drop in full-channel
current. For both material systems, the drop in current with increasing Ld was primarily a
result of the relaxation of the highly confined, strong electric field which was present in the
channel just below the gate edge in the symmetrically recessed devices. This is the same
high-field region which was discussed in Chapter 2. The current drop was most severe in
the InP-channel devices because of the nonalloyed ohmic contacts in these devices; in the
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143
500
V„„ = 400 mV
450
E
400
200 mV/step
I
E 350
w
c
CD
■o
c
2
a
o
c
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Q
300
250
200
150
100
50
0
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2
(a)
160
= 400 mV
E
E
140
120
E
100
w
c
CD
TD 80
c
£ 60
3
o
c 40
200 mV/step
'2
Q
20
0
0
1
2
Drain-to-source voltage (V)
(b)
Fig. 5.17. Drain current-voltage characteristics for InP-channel MODFET that was
(a) symmetrically recessed; (b) asymmetrically recessed with
= 0.37 pm.
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144
800
700
600
cSO O
•o
c 400
InGaAs
3 300
InP
a 200
o 100
LL
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of re c ess toward drain, Ld (|im)
(a)
£
3400
2
3200
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I I I I I I I I 1 I
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|
1100 E
2800
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1000 ts
2400
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1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I 1 1 1 1 I 1 ' 1 ■ ;800 >
0 .1
0 .2
0 .3
0 .4
0 .5
0.6
Extent of re c ess toward drain, Ld (nm)
i ,j
-i
i ,l
. 1,
i
,i
i ,i
(b)
Fig. 5.18. (a) Full channel current density, defined at a gate-source voltage of 400 mV and
drain-source voltage of 1.25 V, versus Ld for InGaAs- and InP-channel MODFETs.
(b) Plot ofB V dsIfuii, a figure of merit for high output power capability, versus Ld for
InGaAs-channel and InP-channel MODFETs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
145
asymmetrically recessed devices, the electric field profile between the gate and the drain has
a more gradual, two-dimensional nature [5.37] and [5.38], which significantly impedes
tunneling from the channel to the cap layer.
Therefore, when performing asymmetric recess, there is an inevitable trade-off
involved even at dc; the reduction of the peak electric field increases the breakdown voltage
but simultaneously decreases the full-channel current. The power capabilities of the devices
are dependent on both of these quantities. Hence, it is important to determine whether
anything is actually being gained by using an asymmetric recess if the goal is to obtain a
larger output power. A useful figure of merit is the product of BVds and Ifunj the full
channel current. This quantity is plotted in Fig. 5.18(b) for both the InGaAs- and InPchannel devices. It can be seen that for the InGaAs-channel devices, asymmetric recess did
improve this quantity, by over 20% in most cases. For the InP-channel devices, the figureof-merit was reduced, suggesting that asymmetric recess may not be appropriate for non­
alloyed drain and source contacts if a larger output power is desired.
5.4.3.3.
High frequency characteristics
The microwave performance of the devices was evaluated by performing 5parameter measurements from 1 to 35 GHz using a Cascade Microtech probe station and an
HP 8510 network analyzer. These measurements were used to extract values of the smallsignal circuit model elements, where the model shown in Fig. 3.4 was assumed. Values
were calculated after pad parasitics had been stripped from the raw s-parameter
measurements. All devices seemed to display peak values offr , the unity current gain cut­
off frequency, at a drain-source bias of 1.3 V and peak values o f / max. the maximum
frequency of oscillation, at a drain-source bias of 3 V. This was true for both channel
materials.
Figures 5.19(a) and (b) are plots of the gate-drain feedback capacitance, Cgd, and
the gate-source capacitance, Cgs, vs. Ld for the InGaAs-channel and InP-channel devices,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
146
7
220
160 £
140 £
o
120
Q_
CO
o
§
§cc
3
u.
"D
2i 2
100 8
CD
CO
InGaAs channel
O 1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of gate re c ess toward drain, Ld (pm)
(a)
120
110
100 8
Q.
CL
InP channel
40
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of g ate re c ess toward drain, Ld (|im)
(b)
Fig. 5.19. High frequency gate-drain and gate-source capacitances of (a)
InGaAs-channel and (b) InP-channel devices extracted from S-parameter
measurements performed at 8 GHz.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
147
respectively. Values were extracted from measurements taken at a drain-source bias of
maximum/max- The general decrease in Cgd with increasing Ld for both channel materials
is to be expected since the drain is effectively isolated from the channel. The decrease
saturated because the capacitance is roughly inversely proportional to the effective gatedrain distance; hence, for larger values of Ld there was a smaller change in Cgd for a fixed
change in Ld. In addition, the gate lengths of the devices with higher values of Ld were
generally larger, which tended to increase Cgd and offset the decrease due to the isolation of
the drain.
For the InGaAs-channel devices, Cgs showed a clear upward trend for
Ld ^ 0.15 pm, which was a result of the fact that more of the charge in the channel that
was coupling with the gate during 5-parameter measurements traveled through the source
contact as Ld was increased and the drain was isolated from the channel. The initial
decrease in Cgs from the point Ld = 0 |im to Ld = 0.15 |im was simply due to the fact that
the Group 2 and Group 3 devices had cap removal on the source side but the Group 1
devices did not (see Table 5.2). The general behavior for Cgs was similar for the InP
channel devices, except that there was much more scatter in the data, perhaps due to the
complicated nature of the nonalloyed drain and source contacts.
Figures 5.20(a) and (b) show the high-frequency intrinsic transconductance and
transconductance-to-output conductance ratio as a function of Ld for the InGaAs-channel
and InP-channel devices, respectively.
Again, values were extracted from the
measurements taken with a drain-source bias of 3 V. For both channel materials there was
a decrease in the transconductance as Ld was increased, primarily because the charge
distribution and electric field profile took on a more two-dimensional nature in the
asymmetrically recessed devices, creating additional fringing effects on the drain side of the
gate with consequent deterioration in the modulation properties. However, the decrease in
transconductance was accompanied by a decrease in the output conductance, so that the
transconductance-to-output conductance ratio actually increased as Ld was increased.
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148
120
a) 110
3 100
■o
Q.
cr
InGaAs channel
o>
0.1
0.2
0.3
0.4
0.5
0.6
Extent of re c ess toward drain, Ld (|im)
(a)
100
40 -2
■o
X3
Cl
O'
InP channel
o>
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of re c e ss toward drain, l_d (pm)
(b)
Fig. 5.20. High frequency transconductance and transconductance-to-output conductance
ratio versus Ld for (a) InGaAs-channel and (b) InP-channel MODFETs. Values were
extracted from S-parameter measurements performed at 8 GHz.
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149
Figures 5.21(a) and (b) display th e /jL g a n d /maxLg products versus Ld for the
InGaAs- channel and InP-channel devices, respectively, where f j was measured at a drainsource bias of 1.3 V ,/max was measured at a drain-source bias of 3 V, and Lg was the
physical gate length. To the first order, f y a n d /max are inversely proportional to the
physical gate length [5.2]; therefore, since the gate lengths of the devices did vary to a
small degree, it was most accurate to compare the frequency-gate length products of the
devices. For this study, the values of / max were calculated using the extracted circuit
element values, as was done in [5.29].
As shown in Figs. 5.21(a) and (b), th e /rL g products of both channel materials
decreased as L<j increased. This was primarily due to a decrease in the intrinsic highfrequency transconductance, as was shown in Figs. 5.20(a) and 5.20(b), as well as the
increase in drain resistance which was illustrated in Fig. 5.15(a). A low drain resistance
and high intrinsic transconductance are both necessary for a high value of f j [17]. In
addition, for the InP-channel devices, the source resistances of the Group 2 and Group 3
devices were significantly higher than for the Group 1 devices (see Table 5.2), which
contributed to the sharp decrease in f j Lg from the point Ld = 0 to the point Ld = 0.15 pm
in Fig. 5.21(b). Interestingly, the/maxLg product of the InGaAs channel devices did not
seem to deteriorate.
For the InP-channel devices., there was an initial drop at
Ld = 0.15 pm due to the drastic increase in source resistance, but not much change
beyond this point. The relatively constant value of / max vs. Ld, even a s /7-was decreasing,
was primarily due to the increase in the transconductance-to-output conductance ratio with
increasing Ld that was shown in Fig. 5.18(b).
5.4.3.4.
Conclusions about asymmetric recess
Both positive and negative effects of asymmetric gate recess on the performance of
InGaAs-channel and InP-channel MODFETs were observed. The primary positive effect
of asymmetric recess was an increased gate-drain breakdown voltage, which was gained at
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150
S 25
•o
S
a. 20
.9.
o>
a$ 15
o> 10
max g
InGaAs channel
cr
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of gate recess toward drain, Ld (|im)
(a)
max g
O)
O)
InP channel
cr
0
0.1
0.2
0.3
0.4
0.5
0.6
Extent of gate recess toward drain, Ld (urn)
(b)
Fig. 5.21. Frequency-gate length products for (a)
InGaAs-channel and (b) InP-channel devices vs. Ld.
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151
the expense of the full-channel current. The net result was an increase in the theoretical
output power capabilities of the InGaAs-channel devices but a decrease in the nonalloyed
InP-channel devices. Other negative effects included a steady increase in the drain
resistance and degradation of modulation properties as the extent of the recess toward the
drain Ld was increased. Ultimately, this led to a decrease in f j for the asymmetrically
recessed devices. Asymmetric recess did not cause a deterioration of /max. however,
presumably because the effect of the increased drain resistance was offset by the effect of
an increased transconductance-to-output conductance ratio (gm/gds)- In fact, it is
conceivable that/max could actually be improved by asymmetric recess in a layer structure
for which the increase in gm/gds outweighs the increase in drain resistance. Such was
likely the case for the work reported by Lester et al. [5.39]. In that work, a n / max of
350 GHz was obtained from an asymmetrically recessed 0.15 |im gate-length
GaAs/AlGaAs/InGaAs pseudomorphic MODFET.
Although the high frequency
performance of similar devices which were symmetrically recessed was not reported in that
work, it is clear that high values of/max are attainable when asymmetric recess is used.
It is clear from this study that care must be taken when deciding how much, if any,
of the cap should be removed on the drain side for a particular layer structure and
application.
It was seen that if a larger output power is desired from the device,
asymmetric recess would be beneficial for the InGaAs-channel devices but not for the InPchannel devices. The greater negative impact on the InP-channel device behavior was
largely attributed to the fact that these devices had drain and source contacts which were not
alloyed.
5 . 4 . 4 . F a b ric a tio n of ohmic contacts to In P channels
Section 5.4.3 implies that InP-channel MODFETs require alloyed ohmic contacts to
be competitive for high-power microwave applications.
If the ohmic contacts are
nonalloyed, the same properties of the layer structure which allow tunneling between the
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152
drain/source contacts and the channel layer also allow tunneling between the gate and the
channel and/or the gate and the cap. This leads to small breakdown voltages. Asymmetric
recess will hinder gate tunneling, but only at the cost of severely hindering tunneling
between the cap and the channel layers as well, which decreases the current and
transconductance at dc as well as degrading the high frequency performance of the device.
For these reasons, a study was performed to attempt to arrive at a scheme which would
allow alloyed ohmic contacts to be made to InP-channel HFETs.
The fundamental principle which had to be identified in this study was the precise
mechanism hindering high-quality alloyed ohmic contacts to the 2-DEG in InAlAs/InP
MODFETs. Because ohmic contact formation to InGaAs-channel MODFETs is somewhat
trivial, initial speculation might suggest that the obstacles in InP-channel MODFET ohmic
contact formation may be the low mobility and high bandgap of InP compared to InGaAs,
which is seen in Table 5.1. However, a brief consideration of the thriving GaAs/AlGaAs
MODFET technology renders this speculation unconvincing: GaAs has a bandgap which is
higher than InAlAs and a mobility which as nearly as low (see Table 5.2), and there seems
to be no difficulty in forming an ohmic contact to the GaAs channel of a GaAs/AlGaAs
MODFET. In addition, the 2-DEG properties of a GaAs/AlGaAs MODFET are similar to
that of an InAlAs/InP MODFET. A review of the literature reveals that the conduction band
discontinuity in a GaAs/Alo.3Gao.7As heterostructure is on the order of 0.3 eV [5.40] and
[5.41], which is much closer to the value of 0.25 eV listed in Table 5.1 (and in good
agreement to the work of Nakajima et al. [5.42]) for an InAlAs/InP heterointerface than it is
to the value of ~0.52 eV for an InAlAs/InGaAs heterointerface [5.43] and [5.44].
Furthermore, the sheet electron densities in the channel for a typical GaAs/Alo.3Gao.7As
MODFET are on the order of 1.3-1.5 x 1012 cm'2 at room temperature [5.45], which is
actually less than the sheet carrier densities reported for the InP-channel MODFETs in
Sections 5.4.2 and 5.4.3.
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153
5.4.4.1.
Effect of thin interfacial A1P layer
Based on the above facts, it is reasonable to hypothesize that the ohmic contact
formation is hindered not by the properties of InP itself, but by some property of the
InAlAs/InP interface. This might explain why alloyed ohmic contacts are readily formed in
InP-channel MESFETs, which contain no InAlAs/InP heterojunction above the channel
[5.46]. It is possible that the nature of this interface is such that it impedes the proper
diffusion of the ohmic metal during alloying. In support of this theory is the recent work
of Imanishi and Kasai [5.47], from which it was concluded that the placement of two
atomic layers of A1P at the InAlAs/InP heterointerface improved its properties, evidenced
by a marked increase in channel electron mobility at 77 K. To see if this type of growth
scheme would ease the fabrication of ohmic contacts, MODFETs were fabricated on the
OMVPE-grown layer structure shown in Fig. 5.22. The structure consisted of a 25 nmthick Fe-doped InP epitaxial layer, a 25 nm Fe-doped InAlAs layer, a 10 nm undoped
InAlAs buffer layer, a 20 nm undoped InP channel layer, 2 atomic layers of A1P, a 3.5 nm
undoped InAlAs spacer layer, a 5 nm Si-doped InAlAs donor layer, a 10 nm undoped
InAlAs barrier layer, and a 10 nm Si-doped InGaAs cap layer. The InAlAs Schottky layer
was made somewhat more thick than was usual for the nonalloyed InP-channel layers for
the purpose of eliminating gate-to-channel tunneling.
Hall measurement results on this layer structure indicated a channel sheet carrier
concentration of 2.6 x 1012 cm '2 and a mobility of 4898 cm2/(Vs) at room temperature.
The respective values at 77 K were 2.3 x 1012 cm'2 and 51,409 cm2/(Vs). The mobility at
77 K is, in fact, much higher than the value of 10,000 cm2/(Vs) reported for the InPchannel structures in Section 3.4.2 and the value of 17,402 cm2/(Vs) for the InP-channel
structures in Section 3.4.3. This remarkable difference at 77 K justified making the
intermediate A1P layer a standard part of InAlAs/InP HFET structures. The effect of this
layer at room temperature was minimal, however, particularly in the area of ohmic contact
formation. A study of the ohmic contact resistances of standard TLM devices metallized
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
154
10 nm n+ InGaAs cap
17.5 nm i-InAlAs Schottky
5 nm n+ InAlAs Si eloped
3.5 nm i-lnAIAs spacer
20 nm i-lnP channel
2 atom ic layers
of AIP
(~ 0.545 nm)
1o
nm i-lnAIAs buffer
__________________________________
25 nm Fe-doped InAlAs
25 nm Fe-doped InP
InP substrate
Fig. 5.22. Layer structure for InP-channel MODFET with a thin AIP
layer at the InP/InAlAs heterojunction to improve the interface quality.
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155
with AuGe/Ni/Au contacts, where AuGe was the bottom metal layer, revealed that the
ohmic contact resistance was lowest with no alloying, having a value of 0.15 ft-mm.
Presumably, this was because the entire current flow in the nonalloyed samples was
through the InGaAs cap; this can be deduced from ohmic contact experiments to bulk nInP, which show that a minimal alloy temperature of 200 °C is needed for contacts to
behave like ohmic contacts [5.48], with the best ohmic contacts being obtained in the
alloying temperature range of 360 °C to 460 °C [5.46], [5.49], and [5.50]. In this study,
all alloyed samples had contact resistances above the nonalloyed value of 0.15 £2-mm, the
difference becoming greater as the alloying time and/or temperature was increased. For
example, samples alloyed at a temperature of 380 °C for 30 s had ohmic contact resistances
of 0.6 O-mm and those alloyed at 415 °C for 30 s had ohmic contact resistances over
2 £2-mm.
The above behavior of the ohmic contacts during alloying is qualitatively identical to
the behavior displayed by the nonalloyed InP-channel devices of Sections 5.4.2 and 5.4.3.
For all of these devices, alloying deteriorated the ohmic contact between the metal and
InGaAs cap which exists without alloying.
For an InGaAs-channel device, this is
inconsequential since the metal is able to form a contact to the channel, which is more
desirable, and the contact resistance improves as a result of alloying. In these InP-channel
MODFET structures, however, the metal is not able to form a contact to the InP channel;
hence, the contact resistance increases after alloying. Therefore, the AIP layer seems to
have little effect.
5.4.4.2.
Delta-doped InP-channel MODFET study of ohmic contacts
The answer to the disturbing question of why it is possible to obtain ohmic contacts
to InP MESFETs [5.46] but not to InP-channel MODFETs apparently lies in a different
direction than the above. A property which the InP MESFETs possess is that the channel
is n-type. In contrast, the channel of a MODFET is undoped and contains only the 2-DEG.
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156
6.5 nm i-lnGaAs cap
20 nm i-InAlAs Schottky
planar Si doping
.
5 nm i-lnAIAs spacer
2 atom ic layers of AIP
20 nm
MnP-channel"
10 nm i-lnAIAs buffer
planar Si doping,
sh e e t density = x
25 nm Fe-doped InAlAs
25 nm Fe-doped InP
InP substrate
(a)
Layer structure
d(nm )
X
10
x (cm '2)
l x 1012
Front-end contact
resistance (£2-mm)
Alloy conditions
(N2 ambient)
standard: 1.5 fl-mm
415 °C 40 s
ohmic etch: 1.1 Q-mm
400 °C 60 s
Y
5
1 x 1012
ohmic etch: 2.4 fi-mm
400 °C 45 s
Z
5
2 x 1012
ohmic etch: 2.3 fi-mm
400 °C 50 s
(b)
Fig. 5.23. (a) Drawing and (b) summary of three different layer structures used in the
study involving ohmic contacts to InP-channel MODFETs.
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157
It is, therefore, reasonable to speculate that for InP, a significant amount of charge is
needed to form an ohmic contact, and perhaps the standard 2-DEG is not a sufficient
amount of charge for ohmic contact formation. For this reason, three different InP-channel
MODFET layer structures were grown by OMVPE with additional planar doping placed in
the channel (see Fig. 5.23(a)). The layer structures consisted of a 25 nm-thick Fe-doped
InP epitaxial layer, a 25 nm Fe-doped InAlAs layer, a 10 nm undoped InAlAs buffer layer,
a 20 nm undoped InP channel layer with a Si planar doping density of x placed a distance
of d from the top of the channel layer, two atomic layers of AIP, a 5 nm undoped InAlAs
spacer layer, a planar Si doping layer, a 20 nm undoped InAlAs barrier layer, and a 65 nm
undoped InGaAs cap layer. Figure 5.23(b) displays the values of x and d for the three
layer structures. An attempt at alloyed ohmic contacts was made on each of these layer
structures using AuGe/Ni/Au contacts. The alloying was done in a conventional alloying
furnace with a N2 ambient, and the optimal alloying conditions were found separately for
each layer structure.
Structure X was the first of the three layer structures grown and had a planar Si
doping density of 1 x 1012 cm-2 placed in the center of the 20 nm InP channel in addition to
the more standard planar doping in the InAlAs. It was felt that the presence of the planar
doping in the channel might enhance the capability of ohmic contact formation in the
channel. However, the best front-end ohmic contact resistances were on the order of
1.5 fl-mm and were obtained when the devices were alloyed at a temperature of 415 °C for
40 s. It was hypothesized that perhaps the reason ohmic contact formation is more
difficult in InP-channel MODFET layer structures than in InP-channel MESFET layer
structures is due to an inability of the ohmic metals to complete the two-step process of
diffusing through the InAlAs and forming an ohmic contact to the InP. To help eliminate
the variable of diffusion through the InAlAs, an unconventional processing step was added
before the ohmic metal deposition. During this added step, denoted the ohmic etch step,
via holes were wet-etched at the source and drain ends of the mesa region in order to
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
15 8
expose the channel layer. It was then possible to deposit the ohmic metal directly on top of
the channel layer, eliminating the need for diffusion through the InAlAs during alloying.
As can be seen in Fig. 5.23(b), this did improve the contact resistance to 1.1 Q-mm, but
this was still an order of magnitude higher than what is common for InGaAs channel
MODFETs.
At this point, it was theorized that perhaps the ohmic metal had trouble diffusing
through 10 nm of undoped InP. Therefore, in Structure Y, the position of the planar
doping was raised to a level which was only 5 nm from the top of the channel. The ohmic
etch step was utilized, but the best ohmic contact resistance obtained in this structure was
2.4 Q-mm. It was then thought that the doping level should be higher as well, perhaps
due to surface depletion effects. Structure Z therefore contained a doping level of
2 x 1012 cm '2 in the channel. However, once again, the ohmic contact resistances were
poor; the best values obtained were on the order of 2.3 fi-mm.
There was much scatter in all of the data for these three layer structures due to the
poor quality of the ohmic contacts, and it was clear that the key concept in the phenomenon
of ohmic contact formation to InP had not yet been identified. Due to the scatter of the
data, caution was utilized in attempting to identify any trends. However, even with the
inherent inaccuracies, Fig. 5.23(b) does seem to indicate that raising the position of the
planar doping in the channel increased the contact resistance, which is somewhat contrary
to what might be expected without a detailed knowledge of ohmic contacts to InP. This is
another indication that the most important mechanism has yet to be revealed, and will be
made more clear in the following section.
5.4.4.3.
InP-channel MISFET study of ohmic contacts
There is one final difference between the InP-channel layer structures discussed in
Section 5.4.4.2 and the InP-channel MESFET layer structure of [5.46] which has not yet
been mentioned. In the latter layer structure, the n-type channel was 315 nm thick,
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159
whereas the channel charge in the former layer structures was roughly confined to two
planes, located at the conventional position of the 2-DEG and the position which was
intentionally doped. In a recent study of Au/Ge/Ni ohmic contact formation to n-InP, Ivey
et al. [5.51] found that in the best ohmic contacts, the compounds consumed a substantial
depth of InP, which was approximately 60 nm. Similarly, Leigh ei al. [5.52] found that
the best Au/Pd/Te ohmic contacts to n-InP extended to a depth of 44 nm. It is clear, then,
that a high quality ohmic contact to n-InP is not a planar phenomena; rather, it requires a
complex interaction of compounds which occupy a nonzero depth.
Based on this characteristic and the previous failures in establishing ohmic contacts
to InP-channel MODFET structures, it is possible that the fundamental requirement that
must be satisfied for an ohmic contact is a minimum thickness of conductive InP. For
example, in a standard MODFET layer structure, the conductive thickness in the InP
channel consists only of the 2-DEG; although in actuality this thickness is not precisely
zero, it is clear that it is quite small and near the InAlAs/InP interface (see Fig. 2.3(a)).
Hence, in a standard MODFET, ohmic contact formation is not possible. In layer
structures Y and Z in Fig. 5.23, the additional planar doping in the channel was placed near
the heterointerface, which has the effect of increasing the electron density in this region but
probably does not increase the effective conductive depth of the channel to a large degree.
In structure X, however, the doping is placed in the center of the channel, farther away
from the natural position of the 2-DEG; hence, the effective conductive depth is increased
somewhat. This explains why the ohmic contact resistances tended to be lower in this
structure compared to those for structures Y and Z. Apparently, though, the situation is
still too similar to two discrete conductive planes, causing the contact resistance to be above
1 £2-mm even in structure X.
Based on the above reasoning, it can now be seen that a low ohmic contact
resistance to an InP-channel HFET requires that a larger depth of the channel be doped,
which effectively transforms the device from a conventional MODFET to a MISFET.
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160
6 nm n-lnGaAs cap
24.5 nm i-lnAIAs Schottky
wzzm m 2 atomic layers of AIP
d
n -In P ,
= x
60 nm
i- ln P
25 nm Fe-doped InP
InP substrate
S tr u c tu r e I : d = 6 .5 n m , x = 6 .5 x 1 0 ^ cm " ^
S tr u c tu r e I I : d = 8 n m , x = 6 .5 x 1 0 ^ c m '^
S tr u c tu r e
S tr u c tu r e
S tr u c tu r e
III: d = 10 n m , x = 6 .5 x 10^ cm " ^
IV: d = 10 n m , x = 4 .5 x 10^ cm " ^
V: d = 10 n m , x = 2 .5 x 10^ cm " ^
Rg. 5.24. Drawing of InP-channel MISFET layer structures used in ohmic contact study.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
161
Therefore, an ohmic contact study was performed on four InP-channel MISFET layer
structures by fabricating TLMs with AuGe/Ni/Au metal contacts alloyed in a N2 ambient.
The OMVPE-grown layer structures are shown in Fig. 5.24; structures with n-type InP
channel layer thicknesses of 6.5 nm, 8 nm, and 10 nm were fabricated with a Si donor
density of 6.5 x 1018 cm '3, with two additional 10 nm-channel structures grown at a Si
donor density of 4.5 x 1018 cm*3 and 2.5 x 1018 cm-3.
The alloying conditions were optimized for each structure separately. The best
contact resistances were always obtained at an alloy temperature in the range of 400 °C to
435 °C for a duration in the range of 20 s to 60 s. The ohmic etch step described in
Section 5.4.4.2 was also tried on these layer structures, but was not found to lower the
minimum achievable contact resistance, although the optimum alloying conditions were
different from those of the TLMs fabricated without the ohmic etch step. The minimum
contact resistances obtained for each of the layer structures is plotted in Fig. 5.25(a) vs. the
thickness of the n-InP channel. As can be seen, the contact resistance decreases sharply as
the channel thickness increases from 6.5 to 10 nm.
However, since the doping
concentrations of structures I-III are constant at 6.5 x 1018 cm-3, the total amount of charge
increases along with the thickness. For this reason, TLMs were fabricated on structures IV
and V, which had lower doping densities but 10 nm channels. As can be seen, the contact
resistance of layer structure IV, which has a donor density of 4.5 x 1018 cm-3 and channel
thickness of 10 nm, is approximately equal to that of layer structure III, which has the same
channel thickness but a donor density of 6.5 x 1018 cm-3. In contrast, structure V, which
had a donor density of 2.5 x 1018 cm '3, had poor ohmic contacts. However, even this
structure had lower contact resistances than the sample with the 6.5 nm heavily doped
channel (structure I). This indicates that in the range of donor densities being used in this
study, a sufficiently large channel thickness is the primary requirement for low ohmic
contact resistances, with a secondary requirement of a sufficiently large amount of charge
in the channel. This can be seen more clearly in Fig. 5.25(b), which is a three-dimensional
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
162
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Front-end resistance (£2-mm)
(a)
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(b)
Fig. 5.25. Front-end contact resistances of InP-channel MISFETs (a) plotted vs. channel
thickness for three different donor densities; (b) plotted vs. channel charge and channel thickness.
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout p erm ission .
163
plot of the minimum ohmic contact resistances obtained for the five different layer
structures as a function of both the total channel charge per unit area and the channel
thickness. Obviously, the lowest contact resistance is obtained with both a large channel
charge and thickness. However, at this minimum point, the gradient in the direction of
channel thickness is greater than the gradient in the direction of channel charge, once again
implying that thickness is the primary criterion, while channel charge is the secondary
criterion. It can therefore be concluded that an ohmic contact in n-InP has the unique
characteristic of requiring that the compounds in the metal are able to interact with the ntype InP over a significant distance. If the n-type InP is too thin, the metal which has
diffused into the undoped InP is not able to interact properly to form the necessary alloys,
and a higher contact resistance results.
5 .4 .5 . Com parison of InP-channel M ISFETs to InP-channel M ODFETs
The results of the previous section revealed that in order to obtain a high-quality
ohmic contact to an InP-channel HFET, it is necessary for the channel to be doped. It is
now interesting to see how the device behavior of symmetrically and asymmetrically
recessed InP-channel MISFETs with alloyed contacts compare to symmetrically and
asymmetrically recessed InP-channel MODFETs with nonalloyed ohmic contacts.
5.4.5.1.
Device fabrication
The layer structures used in this study are depicted in Fig. 5.26. The structures
were essentially identical except for the position of the donors. In addition, it was possible
to obtain more charge in the channel in the InP-channel MISFET structure simply because
the dopants were placed directly in the channel. Results from Hall measurements showed
that the channel sheet electron concentration in the InP-channel MODFET structure was
2.1 x 1012 cm-2 with a mobility of 3947 cm2/(Vs) at 300 K, whereas the effective channel
electron concentration in the InP-channel MISFET structure was 4.5 x 1012 cm*2 with a
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164
10 nm n+ InGaAs cap
10 nm i-lnAIAs Schottky
5 nm n+ InAlAs Si doped
3.5 nm i-lnAIAs spacer
20 nm i- InP channel
10 nm i-lnAIAs buffer
25 nm Fe-doped InAlAs
25 nm Fe-doped InP
InP substrate
(a)
10 nm n+ InGaAs cap
18.5 nm i-lnAIAs Schottky
M0 nm n-InP channel
Nd = 4.5xio18cnr3
10 nm i-lnP______
10 nm i-InAlAs buffer
25 nm Fe-doped InAlAs
25 nm Fe-doped InP
InP substrate
(b)
Fig. 5.26. Drawing of InP-channel (a) MODFET and (b) MISFET layer structures
used in MODFET/MISFET comparison.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
165
mobility of 944 cm2/(Vs) at 300 K. At a temperature of 77 K, the channel sheet electron
concentration in the InP-channel MODFET structure was 2.1 x 1012 cm-2 with a mobility
of 17,402 cm2/(Vs), while the effective channel electron concentration in the InP-channel
MISFET structure was 4.6 x 1012 cm-2 with a mobility of 1300 cm2/(Vs).
The devices were fabricated with AuGe/Ni/Au ohmic contacts which were alloyed
at 435 °C for 30 sec for the MISFETs, yielding a contact resistance of 0.1 O-mm, but were
left nonalloyed for the MODFETs, yielding a contact resistance of 0.15 O-mm. Three
types of gate recess were performed on each of the layer structures. First, symmetric
recess was performed using a standard trilayer resist process. A second set of devices was
fabricated with the 4-layer resist process outlined in Section 5.3 with no sidelobe exposure;
hence, the gate recess in these devices was also symmetric but with an undercut of
0.17-0.19 |im on either side of the gate. The third set of devices was asymmetrically
recessed with a cap removal extending 0.45 to 0.5 |im from the edge of the gate toward the
drain (i.e., Ld ~ 0.45-0.5 pm). The three sets of devices are analogous to the three sets
fabricated in Section 5.4.3, but with only one value of Ld for the asymmetrically recessed
devices.
Devices had a width of 100 pm, drain-source spacings of 2 |im, and gate lengths in
the range of 0.22-0.28 pm. Device isolation was obtained by etching mesas with a dilute
HBr/Br2 solution buffered with KBr.
5.4.5.2.
Device characteristics and figures-of-merit
Figure 5.27(a) is a plot of the drain I-V characteristics of a symmetrically recessed
InP-channel MISFET fabricated with the trilayer resist.
Figure 5.27(b) shows the
transconductance and drain current of the same device vs. gate voltage at a drain bias of
2 V. In Fig. 5.28(a), the values of BVds and Imax are plotted for the symmetrically and
asymmetrically recessed MISFETs and MODFETs. Although the MISFETs fabricated
with the symmetric trilayer resist process had a lower current density than the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
166
400
V
350
300
= 400 mV
200 mV/step
250
I 200
3 150
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I 100
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Fig. 5.27. Direct current characteristics of symmetrically recessed InPchannel MISFET plotted versus (a) drain voltage and (b) gate voltage.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
167
10
8
400
6
4
200
2
MISFET
Full channel current (mA/mm)
600
MODFET
0
symmetric trilayer
symmetric 4-layer
asymmetric 4-layer
(a)
2500
2000
1500
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1000
MISFET
500
MODFET
symmetric trilayer
symmetric 4-layer
asymmetric 4-layer
(b)
Fig. 5.28. (a) Drain-source breakdown voltages and full channel current densities of
InP-channel MISFETs and MODFETs fabricated with three different gate recess
processes, (b) Power figures-of-merit of the same devices.
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168
corresponding symmetric trilayer MODFETs, the 4-layer resist process decreased the
current in the MODFETs to a greater degree than in the MISFETs. The increase in
breakdown voltage from the 4-layer resist process was substantial for both sets of devices.
To illustrate the net output power capabilities of the devices, the BVdsImax products are
plotted in Fig. 5.280?). For both the MODFETs and MISFETs, it appears that the 4-layer
resist devices have increased output power capabilities, with the MISFETs appearing to
have an edge.
Also of interest is the ability of the devices to show gain at high frequencies.
Figures 5.29(a) and 5.29(b) display the high frequency figures-of-merit for the MISFETs
and MODFETs, respectively. Although the trilayer MISFETs and MODFETs have similar
figures-of-merit, it is clear that the 4-layer MISFETs have the advantage over the 4-layer
MODFETs at high frequencies. This is due to the fact that the nonalloyed ohmic contacts
of the MODFETs suffer from any additional cap removal on the drain or source side of the
gate, as was shown in Section 5.4.3. Considering that the BVdsImax products of the
MISFETs are higher than those of the corresponding MODFETs in all three of the
fabrication categories, it appears that the MISFETs are superior power devices. However,
it is hard to predict which of the three fabrication categories will produce the best
microwave power devices since there seems to be a trade-off between the high frequency
figures-of-merit and power figure-of-merit.
5.4.5.3.
Power performance
The actual power performance of these InP-channel devices must now be
compared. On-wafer power measurements were performed on the six sets of devices at
8 GHz. The input power was swept from -8.9 to 6.0 dBm. Figure 5.30(a) displays the
maximum gain and power-added efficiency (PAE) of devices in each of the MISFET and
MODFET categories. The tuning circuitry was adjusted separately for each device at each
bias in order to obtain the maximum gain at a given input level. In all cases, this was the
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169
max
symmetric trilayer
symmetric 4-layer
asymmetric 4-layer
(a)
80
70
60
X 50
max
o 40
20
10
0
symmetric trilayer
symmetric 4-layer
(b)
asymmetric 4-layer
Fig. 5.29. High frequency figures-of-merit for symmetrically and asymmetrically
recessed (a) MISFETs; (b) MODFETs.
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170
60
50
£ 40
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MISFET
MODFET
0
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symmetric trilayer
symmetric 4-layer
asymmetric 4-layer
0.9
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0.8
MODFET
0.3
0.2
2 0.5
0.1
-0.3 f
symmetric trilayer
symmetric 4-layer
asymmetric 4-layer
(b)
Fig. 5.30. (a) Maximum PAE and power gain of symmetrically and asymetrically
recessed InP-channel MISFETs and MODFETs measured at 8 GHz. (b) Maximum
output power and gate current at maximum output power of same devices.
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171
same tuning point which yielded the highest PAE. At a given bias point, the maximum
PAE and largest output power of the device occurred at the highest input power. The
maximum gain usually occurred at low input powers.
As shown in Fig. 5.30(a), the trilayer MODFETs and MISFETs as well as the
symmetric 4-layer MISFETs all had excellent values of PAE, just above 50%. These
devices all had the highest gain as well, although the gain of the trilayer MODFETs was
slightly lower than the two sets of MISFETs, which exhibited power gain in the range of
14.9-15.1 dB. In the areas of gain and efficiency, therefore, the two sets of devices which
appeared to have the best performance were the two sets of symmetric MISFETs.
However, in terms of output power, the superior devices were clearly the trilayer
MISFETs, which were capable of 0.8 W/mm. The trilayer MODFETs experienced
catastrophic breakdown before they were able to exhibit large output powers. This is
consistent with what has been stated throughout this chapter; nonalloyed InP-channel
MODFETs which have low drain and source resistances necessarily have the problem of
gate-drain breakdown because of enhanced tunneling between the gate and the doped cap
and/or the gate and the channel.
The maximum output power of the 4-layer symmetric MISFETs was surprisingly
low, considering the high efficiency and gain of the devices. This may be a somewhat
pessimistic value, however, because of the inability to properly adjust the output tuner to
the optimum load, which, as was explained in Chapter 3, is a typical problem for low
current, high breakdown voltage devices. In fact, this tuning problem was present during
measurement of all of the 4-layer FETs, and for the 4-layer asymmetric devices as well as
the 4-layer symmetric MODFETs, which all exhibited poor power characteristics. The
output power was low enough to severely decrease the efficiency of the devices. It may
also be that all of the 4-layer devices, especially the 4-layer asymmetric devices, had the
problem that the surface states were too slow to respond to a microwave signal which was
large in amplitude, which has the effect of decreasing the microwave output power [5.15].
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172
If this is the case, it is reasonable to believe that the slow response of the surface states
would interfere with the tunneling currents of the nonalloyed ohmic contacts at high
frequencies and large input signals, which would imply that the performance of the 4-layer
MODFETs would degrade even more as a result of asymmetric recess.
Figure 5.31(a) displays the PAE and the drain efficiency (DE) of a trilayer
MISFET vs. input power. The dc bias condition was for maximum output power (and
maximum gain), which was at a gate-source voltage of -0.73 V and a drain-source voltage
of 6.5 V. Both the dc bias and the output voltage swing were thus very large compared to
those for the InAlAs/InGaAs MODFETs; the latter devices typically display their best
power performance at drain-source biases on the order of 3.5 V [5.10] and [5.53].
Therefore, the InP-channel MISFET may be the device of choice for applications requiring
large output voltages. In addition, as illustrated in Fig. 5.31(b), the MISFET shows
constant gain over a large input power range of 14 dB. The PAE for the device at its point
of maximum output power density of 0.8 W/mm, corresponding to an output power of
19 dBm, is 46.5%. The time-averaged gate current for the device is also plotted in Fig.
5.31(b); even at these bias conditions, the device is not experiencing severe gate-drain
breakdown. In faci, the 3 dB compression point has not even been reached even at the
highest input power. It is conceivable that this device could display an output power
approaching 1 W/mm at its 3 dB compression point.
Figures 5.32(a) and (b) are similar to Figs. 5.31(a) and (b) but are for a trilayer
MODFET. Note in Fig. 5.32(b) the MODFET actually encounters its 3 dB compression
point at an input power of 4.4 dBm. Inspection of the time-averaged gate current reveals
that the device begins to experience clipping as well as gate-drain breakdown, since the gate
current is negative but starts becoming less negative at the 3 dB compression point. In
other words, at higher input powers, the gate begins to conduct in the forward direction
during the half of the cycle in which the gate voltage is swept positive as well as in the
reverse direction during the half it is swept negative. When the drain bias is increased to
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173
50
45
Drain efficiency
V
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Power-added
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10
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Fig. 5.31. (a) Efficiencies vs. input power for trilayer InP-channel MISFET
biased for maximum gain at 8 GHz. (b) Output power and time-averaged
gate current vs. input power for same device.
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174
60
Drain efficiency
50
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Fig. 5.32. (a) Efficiencies vs. input power for trilayer InP-channel
MODFET biased for maximum gain at 8 GHz. (b) Output power and
time-averaged gate current vs. input power for same device.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
175
4 V, the device experiences catastrophic breakdown at the higher input powers. This can
be seen in Fig. 5.33(a), which displays the maximum gain and PAE vs. drain bias for both
the trilayer MODFET and trilayer MISFET. Here, the gate-source voltage was held at a
constant value of -0.73 V for the MISFET and -0.36 V for the MODFET.
Figure 5.33(b) is a plot of the maximum gain and PAE vs. gate bias for the trilayer
MODFET and trilayer MISFET. The drain bias was held constant at 6 V for the MISFET
and 3.5 V for the MODFET. It can be seen that for both devices, the PAE peaks at a
slightly more negative gate voltage than the point at which the gain peaks, presumably
because the device is being driven deeper into class AB, in which it is possible to have
greater efficiencies. However, when the device is brought too deep into class AB by
biasing the gate even more negative, by the PAE begins to decrease again due to the
decrease in gain.
Finally, Fig. 5.34 is a plot of the reported values of PAE vs. output power of
discrete MODFETs, MESFETs, and heterostructure bipolar transistors (HBTs) fabricated
by various companies. Values are at 10 GHz, and the output powers are not normalized in
order that the HBTs may be compared to the FETs. Therefore, the FETs with higher
output powers tend to have wider channels. A good rule of thumb is that most of the good
power FETs have maximum output power densities of around 1 W/mm at this frequency.
For comparison, the PAE of an InP-channel MISFET from this study that was fabricated
with the trilayer resist process is plotted. As can be seen, the device seems to be
competitive with the state-of-the-art devices. Admittedly, the power data in this study were
taken at 8 GHz, but the device was not driven to the 3 dB compression point as with many
of these devices, which would have increased its maximum output power. Furthermore,
the measurements were taken via on-wafer probing and without the use of lapping, via
holes, air bridges, thick metal plating, chip mounts, or wire bonds, in contrast to some of
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176
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Fig. 5.33. Maximum gain and maximum power-added efficiency for InP-channel trilayer
MISFET and trilayer MODFET plotted as a function of (a) drain bias, with Vgs = -0.73 V
for the MISFET and VgS = -0.36 V for the MODFET; (b) gate bias, with
= 6 V for the
MISFET and Vds = 3.5 V for the MODFET.
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177
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Hughes ('90)
:
This study
•
NEC ('91) O MODFET
•
-
-
TT ('92)
MESFET
A HBT
★ MISFET (8 GHz)
A
TI (’90)
:
10
0
0.01
0.1
Output power (\V)
10
Fig. 5.34. Power-added efficiencies of discrete devices of various companies plotted as a
function of output power. In this plot, power is not normalized, i.e., the higher power devices
simply represent devices with wider channels in the case of FETs or larger emitter areas in the
case of HBTs. Except for the MISFET, the frequency of measurement was 10 GHz.
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178
the devices plotted in Fig. 5.34. The latter techniques are often used to decrease the
external losses of the devices and hence increase the power performance.
5.4.5.5.
Summary of InP-channel device comparison
In conclusion, the InP-channel MISFET technology seems to be competitive with
other technologies for frequencies around 10 GHz. It was found that these devices would
be particularly useful for applications requiring large operating voltages and large output
voltage swings.
The InP-channel MODFET devices, however, have the troubles
associated with nonalloyed ohmic contacts, which automatically lowers the breakdown
voltage. The 4-layer resist process can be used during the gate recess to increase the
breakdown voltage, but often this degrades the current level and high-frequency gain of the
devices to the point that they are not capable of very high output powers. In addition, it
was speculated that electrons trapped in the surface states present in the MODFETs
fabricated with the 4-layer resist may not be able to follow large input voltages at high
frequencies; this may interfere with the tunneling of the nonalloyed ohmic contacts. The
symmetric 4-layer MISFET, however, displayed excellent gain and power-added
efficiency. Its output power was believed to be mainly limited by inadequate load matching
by the passive tuners in the measurement setup, which caused clipping to occur
prematurely. The asymmetrically recessed MISFET, in sharp contrast, displayed poorer
power characteristics. It is clear that for this type of device, the extent of undercut during
gate recess should be small. Comparison to other device technologies Tevealed that even
the best InP-channel MISFETs have power characterisics that are as good as, but no better
than, other device technologies such as GaAs-based devices, which are fundamentally
cheaper to fabricate. The main limitation of InP-channel devices is the large parasitic drain
and source access resistances which result from the low value of the mobility in the lowfield regions of the channel. In order to improve gain at high frequencies and gain a clear
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179
advantage over cheaper technologies, techniques must be discovered to reduce these
parasitic resistances.
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180
5.5.
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electron mobility transistors," IEEE Trans. Electron Devices, vol. 37, pp. 21652169, 1990.
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gate-length double recess pseudomorphic HEMT w ith /max of 350 GHz," IEEE
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185
CHAFFER 6. SUMMARY AND FUTURE RESEARCH DIRECTIONS
As with every area of research, there is no end to the enhancement of InP-based
HFET design and characterization for high-power microwave applications.
Each
advancement in this area can be compared to opening a door after crossing a small room
only to reveal a larger room filled with even more challenges and possibilities. In less
figurative terms, the results and conclusions presented in this work are not meant to be the
final word on this branch of research but rather to serve as a base of knowledge for future
work.
For example, Chapter 3 discussed the high-frequency model and figures-of-merit
often used to characterize and explain the behavior of HFETs at high frequencies. While
this is the accepted technique for predicting a device’s microwave performance even for
large signals, there is the inherent fallacy that small-signal parameters are being used to
describe large-signal behavior. Small-signal concepts such as maximum available power
gain assume that the S-parameters of the device are constant over the entire range of
operation and are therefore useless for making any concrete prediction about large-signal
response. This allows room for research. Little has been done, for example, to show any
correlation between small-signal frequencies-of-merit as a function of gate and drain biases
for an HFET and the actual power performance of the same device.
Chapter 4 showed the existence of Gunn phenomena in InGaAs/InAlAs
MODFETs. Little work has been done to attempt to eliminate Gunn domain formation by
altering the layer structure design slightly. For example, it would be interesting to grow
layer structures similar to those used in Chapter 4 but with less charge in the channel and
determine the effect that this has on the Gunn phenomenon. Also, in that chapter it was
indirectly implied that improving a device's power performance significantly also enables it
to form Gunn domains. A very challenging problem would be to find a design which has
truly superior power capabilities but no possibility of Gunn domain formation.
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186
Chapter 5 explored some of the critical fabrication and design issues for power
HFETs. Vertical scaling issues as well as horizontal scaling issues were addressed,
including the disclosure of a unique 4-layer electron beam resist process for asymmetric
recess. Hindsight reveals that it would be beneficial to have a smaller amount of undercut
in the bottom layer of resist in the 4-layer resist structure when no sidelobe exposure is
performed, since too large a recess trench was found to be detrimental to an HFET's highfrequency capabilities. Such an improvement in the resist process would reduce the
amount of recess on the source side of the gate and also allow smaller amounts of recess on
the drain side. Another area of research that was not covered in this chapter was the use of
Schottky materials other than InAlAs which can be grown by MOCVD and which would
improve the breakdown voltage of an HFET.
Also, the subject of ohmic contact formation to InP channels contains numerous
opportunities for research. A study could be performed which investigates the effect of
graded doping in an InP channel on the ohmic contact resistance. Alternatively, a standard
InP-channel MODFET layer structure might be able to be used which has dopants
implanted into the channel in the regions where alloyed ohmic contacts are desired. In
addition, it could be possible that a unique ohmic metal scheme could be found which
requires only a small thickness of free charge to form an alloyed ohmic contact to InP.
Such a scheme would likely involve a material which could create an n-type well in InP
through surface deposition and alloying. Currently, no such material has been found.
It was seen that InP-channel MISFETs do not have a clear advantage over cheaper
technologies in terms of actual microwave power performance, although they may have a
niche market in power applications requiring high dc operating voltages. To obtain higher
power gain at microwave frequencies, a design must be found which reduces the drain and
source access resistances in the low-field regions of the InP channel, where the low
mobility of InP causes problems. The high parasitic resistances of InP-channel MISFETs
mask any advantage of the high electron velocities in the high-field regions of the active
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
187
channel.
One possible solution to this problem would be the use of a composite
InP/InGaAs channel structure in which the electrons would travel mostly in the InGaAs
channel in the low-field regions of the device but be transferred to the InP channel in the
high-field regions of the device. An InP-channel MODFET with implanted ohmic contacts
would also have higher mobility in the low-field regions than an InP-channel MISFET.
It is clear that there are many opportunities for additional research. In order for
InP-based HFETs to remain competitive with other device technologies for high-power
microwave applications, it is necessary that these and other issues be explored.
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188
APPENDIX.
FREQUENCY BANDS
Below is a table of the commonly used microwave band designations (sometimes
referred to as "radar bands") found in literature. This is the convention defined by IEEE
Standard 521 in 1984 and is effectively a revision of the band designations adopted by the
U.S. Department of Defense in August 1969. This should not be confused with another
main designation standard adopted by the Department of Defense in August 1970,
consisting of bands labelled A thrjugi.' M. The latter designation standard, sometimes
named the electronic countermeasure (ECM) standard, is not often used in current journal
articles.
Band
Frequency
range (GHz)
VHF
0.03 - 0.3
UHF
0.3-1
L
1-2
TV, FM radio, long-range surveillance radar
TV, long-range missile and spacecraft surveillance, analog cellular
phone systems (0.9 GHz)
Aero navigation, global positioning system down link, digital
cellular phone systems (1.2 GHz)
S
2 -4
Microwave ovens, air traffic control
C
4 -8
Mobile TV links, C-band weather radar
X
8-12
Police radar, X-band weather radar, shipboard navigation
Ku
12-18
Direct broadcast system links
K
18-27
Police radar, navigation radar
Ka
27-40
Navigation radar, miscellaneous communications
V
40-75
Milstar up link. misc. military satellite communications
w
75-110
High frequency missile seekers
mm1"
110-300
Applications in space or for short ranges in atmosphere
Examples o f current applications
*It is also common to refer to frequencies in the range of 40 - 300 GHz as mm-wave
frequencies.
In addition, there are applications in military and commercial satellite communications and
radars in nearly every frequency band.
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189
VITA
Daniel Gerard Ballegeer was born in Moscow, Idaho, on March 1, 1968.
Mr. Ballegeer entered the University of Wisconsin-Eau Claire in August 1986 and
transferred to the University of Wisconsin-Madison, in the School of Electrical
Engineering, in January 1988.
During the summer of 1988, he worked as an
undergraduate researcher for Professor King in the Chemistry department at the University
of Wisconsin-Eau Claire. He also worked as a student hourly for Professor Nordman in
the Thin Films Laboratory in the Electrical Engineering Department. After receiving the
Bachelor of Science degree in May 1990, he worked as a summer intern under the
sponsorship of Professor Adesida at the University of Illinois at Urbana-Champaign.
During this time he began research in the area of reactive ion etching, continuing this work
for Professor Adesida under a research assistantship which began in August 1990. He
concluded this work in January 1992, and officially received the Master of Science degree
in Electrical Engineering in May 1992.
In May 1992, Mr. Ballegeer received a full-study doctoral fellowship from GMHughes Electronics. He spent the summers of 1992 and 1993 working in Malibu,
California, in the Microwave Devices and Circuits Laboratory at Hughes Research
Laboratories on projects involving InP-based power HEMTs. During the remainder of
those years, he continued to study in Professor Adesida's research group at the University
of Illinois. Mr. Ballegeer will be the first student to receive both the M.S. and Ph.D. in
Electrical Engineering under Professor Adesida.
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