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Silicon MOS field effect transistor RF /microwave nonlinear model study and power amplifier development for wireless communications

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Silicon MOS Field Effect Transistor RF/Microwave
Nonlinear Model Study and
Power Amplifier Development for
Wireless Communications
A Thesis
Presented to
The Academic Faculty
by
Deukhyoun Heo
In Partial Fulfillment
o f the Requirements for the Degree
Doctor o f Philosophy in Electrical Engineering
Georgia Institute o f Technology
October 2000
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UMI Number 9994413
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UMI
UMI Microform 9994413
Copyright 2001 by Bell & Howell Information and Learning Company.
All rights reserved. This microform edition is protected against
unauthorized copying under Title 17, United States Code.
Bell & Howell Information and Learning Company
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P.O. Box 1346
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Silicon MOS Field Effect Transistor RE/Microwave
Nonlinear Model Study and
Power Amplifier Development for
Wireless Communications
Approved:
asl
irman
David R. Hertlins
Martin A. Brooke
Date Approved_
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oo
D edicated to My Savior Jesus Christ,
My Parents, Wife, and Son
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ACKNOWLEDGEMENT
I would like to thank my Ph.D. advisor, Dr. Joy Laskar, for his guidance, support,
and encouragement throughout my research at the Georgia Institute of Technology.
I would like to thank Dr. David Hertling, Dr. April Brown. Dr. Martin Brooke and
Dr. Vikram Krishunamurthy o f the thesis committee for their advice and valuable
suggestions. I’d like to acknowledge the collaboration and support of Dr. Mike Surwartz
at National Semiconductor, TriQuint Semiconductor, and the School of Electrical and
Computer Engineering at Georgia Tech.
I gratefully acknowledge Carl Chun, Mike Hamai. Edward Gebara. Emery Chen.
Albert Sutono, Chang-Ho Lee, Dr. Sangwoo Han, Seungyup Yoo, Bobby Matinpour for
their significant support and collaborations to my thesis work. I would like to also thank
the members of Microwave Applications Group - Dr. Ramana Multy, Dr. Anh-Vu Pham.
Dr. Youngsuk Suh, Dr. Kyutae Lim, Josh Bergman. David Cresci, Daniela Staiculescu.
Hongwei Liang, Arvind Raghavan, Sudipto Chakraborty, M ekita Davis. Sebastien
Nutinck, Ade Obatoyinbo, Lakisha Pate, Neeraj Lai, Jishnu Bhattachaijee. Debanjan
Mukherjee, Lauren Jeanne McGrath.
I would like to thank my wife, Jeehee, my son, Jaeyoung, my parents, Shingil Heo
and Wonja Lee, my brothers, Juhyoun and Siyoung Heo, my parents-in-law, Jonggi Kim
iii
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and Chooja Kwak, and my brother-in-law. Hunsoo Kim and sister-in-law, Soohee Kim
for their prayer, support, love, and encouragement.
iv
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TABLE OF CONTENTS
D ED IC A TIO N ............................................................................................................................
ii
ACKNOW LEDGEMENT.........................................................................................................
iii
LIST OF T A B L E S ....................................................................................................................... viii
LIST OF FIGURES..................................................................................................................... ix
SU M M A R Y .................................................................................................................................. xiii
CHAPTER
I.
INTRODUCTION.............................................................................................................. I
II.
RF DEVICE NONLINEAR MODELING APPROACHES FO R POWER
AMPLIFIER D EVELOPM ENT......................................................................................4
2 .1.
2.2.
2.3
Active Device RF Nonlinear Modeling Approaches.................................... 4
2.1.1.
Advantages o f Physical M odeling.......................................................5
2.1.2.
Advantages o f Equivalent Circuit M odeling.....................................7
Issues on RF Nonlinear M odeling of MOS Field Effect Transistor............9
2.2.1.
Thermal E ffects..................................................................................... 10
2.2.2.
Breakdown Current Effect................................................................... 10
2.2.3.
Substrate Nonlinear Coupling E ffect.................................................12
Design Techniques in Power A m plifier...........................................................14
2.3.1.
Trends in Power Am plification.......................................................... 14
2.3.2.
Class of Power A m plifiers.................................................................. 15
2.3.3.
High Efficiency Power Amplifier D esign........................................ 16
2.3.4.
Linear Power Amplifier Design with High Efficiency.................... 18
2.3.5.
Load-Pull M easurement T echnique.................................................. 21
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2.3.6. Nonlinear Circuit Simulators using Device Nonlinear M odel
III.
23
SILICON DEEP SUB-M ICRON MOSFET NONLINEAR MODEL
DEVELOPM ENT............................................................................................................ 26
3.1.
Introduction............................................................................................................26
3.2.
An New Deep Sub-micron MOSFET RF Nonlinear M odel........................ 29
3.2.1.
Proposed Deep Sub-micron
MOSFET RF Nonlinear Model
3.2.2.
Nonlinear Channel Current
M odel.........................................30
3.2.3.
Breakdown Mechanisms in
a Long-channel M OSFET......33
3.2.4.
Breakdown Mechanisms in
a Short-channel M O SFE T .....35
3.2.5. New Breakdown Current M odel........................................................37
3.2.6. Drain-to-Substrate Nonlinear Coupling M odel...............................41
3.3.
IV.
Nonlinear Model Parameter Extraction............................................................ 44
3.3.1.
RF Performance o f n-M O SFET.........................................................44
3.3.2.
Channel Current and New Breakdown Model Extraction.............47
3.3.3.
Nonlinear Substrate Coupling Model E xtraction........................... 54
3.4.
Nonlinear Model V erification............................................................................59
3.5.
Conclusion.............................................................................................................. 71
A 1.9 GHz DECT M OSFET POWER AMPLIFIER W ITH FULLY
INTEGRATED M ULTI-LAYER LTCC PA SSIV ES................................................72
4.1.
Introduction............................................................................................................72
4.2.
Digital Enhanced Cordless Telecommunications............................................76
4.3.
4.2.1.
DECT Standard.....................................................................................76
4.2.2.
Applications for the DECT Standard................................................78
4.2.3.
Strengths o f DECT Standard.............................................................. 79
Low Temperature Co-fired Ceramics Technology..........................................81
4.3.1.
LTCC Inductors.................................................................................... 82
4.3.2.
LTCC Capacitors.................................................................................. 85
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29
4.4.
New Temperature Dependent Power MOSFET R F Nonlinear M o d el
89
4.4.1. A New Temperature Dependent Nonlinear Current M odel...........90
4.4.2. DC and AC Model Parameter Extraction...........................................92
4.5.
A New CM OS-LTCC 1.9-GHz High Efficiency Pow er A m plifier............98
4.5.1. High Efficiency Power Amplifier using LTCC Integral Passives.98
4.5.2. LTCC Passive Equivalent Circuit M odeling.....................................98
4.5.3. High Efficiency Power Amplifier Design and Perform ance
4.6.
VI.
100
Conclusion............................................................................................................. 108
CONCLUSION.................................................................................................................109
BIBLIOGRAPHY..........................................................................................................................112
V IT A ................................................................................................................................................118
vii
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LIST OF TABLES
Table
page
2.1
Advantages and disadvantages of nonlinear circuit sim ulators................................... 25
3.1
RF Performance and small signal circuit parameters of the
fabricated deep sub-m icron (0.25|im) n-MOSFET with 10 finger
and 25 |im gate w id th ........................................................................................................45
3.2
Summary of the param eters o f saturation current com ponent o f the
total channel current.......................................................................................................... 52
3.3
Summary o f the param eters o f breakdown current com ponent of
the total channel c u rre n t................................................................................................... 52
4.1
Table 4.1. Com parison between MIM capacitors and VIC
capacitors............................................................................................................................. 88
4.2
Pulsed IV Channel Current and Temperature Parameters o f Power
M O SFET............................................................................................................................. 93
4.3
Performance summary o f the MOSFET-LTCC power am plifier
viii
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107
LIST OF FIGURES
Figure
page
2.1
Flow Diagram for Physical Model Development.......................................................... 6
2.2
Flow Diagram for Equivalent Circuit Model D evelopm ent........................................ 7
2.3
Breakdown M echanism for Deep Sub-micron M O S FE T ...........................................11
2.4
Voltage and current waveforms for different classes of PA ........................................15
2.5
Harmonic tuning circuit for high efficiency (a) and waveforms of a
class F operation (b).......................................................................................................... 17
2.6
Envelope Elimination and Restoration M ethod............................................................ 19
2.7
Doherty power am plifier topology................................................................................. 20
3.1
Equivalent circuit of the proposed deep sub-micron common
source N-MOSFET (10 finger x 25-p.m )..................................................................... 28
3.2
Fabricated Test Patterns and Deep sub-micron M OSFET device............................ 44
3.3
The on-wafer dual pulse I-V measurement setup with temperature
controllable thermal cham ber......................................................................................... 46
3.4
The actual pulse waveform used to measure pulse I-V with
breakdown current. The pulse width is 400 |is for the gate and 200
p.s for the d ra in ..................................................................................................................47
3.5
The measured CW I-V and pulse I-V (Vgs:0.6~l .8 V. Step:0.2 V )..........................48
3.6
The extracted saturation and breakdown current components of the
measured Pulse I-V curves at two different V„s...........................................................50
3.7
The measured and modeled breakdown current tum-on voltage
(VBon) turnover trend with Vg* bias voltage.................................................................51
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3.8
Deep Sub-micron M OSFET layout................................................................................53
3.9
Extracted and modeled nonlinear drain-to-substrate coupling
capacitance Cdd................................................................................................................. 54
3.10
Extracted and modeled (a) Cdg. (b) Cg*. and (c) Cds.................................................... 56
3.11
Extracted nonlinear drain to source resistance Rds.......................................................57
3.12
Measured (circle) and modeled (solid) pulse I-V including
breakdown current (Vgs : 0.6-1.8 V, Step : 0.2 V). M ark denotes
the breakdown current turn-on voltag (VBon).............................................................. 58
3.13
Comparison of measured (cross) and modeled (solid line) Sparameters (a) at Vgs = 0.8 V and Vds = 1 V and (b) at
= 1 V and
Vds = 2.5 V. f = 0.1 GHz - 10 G H z.....................................
60
3.14
Comparison of measured fundamental output power (P I), second
(P2) and third harmonics (P3) and simulated data with proposed
breakdown and substrate coupling model and without these models
at Vgs = 1.3 V and V ^ = 3 V. freq. = 4.4 GHz. input termination
0.64Z800 and output termination 0.26Z1330.............................................................. 61
3.15
Pout, Gain, and PAE measured and simulated (a) at Vgs = 0.9 V
and V^ = 2 V, freq. = 3.4 GHz, input termination 0.64Z 55.50 and
output termination 0.31Z 960 and (b) at Vgs = 1.3 V and VdS= 2 V,
freq. = 4.4 GHz. input termination 0.66Z75.90 and output
termination 0.28Z1320....................................................................................................63
3.16
Fundamental output power (Pout). IM3 and IM5 measured and
simulated by the proposed model (a) using 3.4 GHz and 3.401 GHz
and (b) using 4.4 GH z and 4.401 GHz, Vgs = 0.9 V and Vds = 3 V.
50 Q input and output termination, input power sweep from -15
dBm to 5 d B m ...................................................................................................................65
3.17
Fundamental output power (Pout), 1M3 and IM5 measured and
simulated by the proposed model (a) using 3.4 G H z and 3.401
GHz and (b) using 4.4 GHz and 4.401 GHz. Vgs sweep from 0.6 V
to 2.0 V and V ^ = 2 V. 50 Q. input and output termination. 0 dBm
input power condition...................................................................................................... 67
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3.18
Fundamental output pow er (P I), second (P2) and third harmonics
(P3) measured and sim ulated by the proposed model (a) at 3.4 GHz
and (b) at 4.4 GHz,
sweep from 0.6 V to 2.0 V and
= 2.5 V,
50 Q input and output termination, 0 dBm input power condition.........................69
4.1
A 1.9-GHz DECT m odule block diagram ..................................................................... 73
4.2
LTCC process flow c h a r t................................................................................................. 81
4.3
The structure o f multi-level ground plane inductors....................................................83
4.4
The effective inductance o f multi-level ground plane inductors.................................84
4.5
The measured Q o f multi-level ground plane inductors.............................................. 85
4.6
The structure of capacitor topology................................................................................ 86
4.7
Measured and simulated results o f MIM and VIC capacitors................................... 88
4.8
Pulsed IV curves at three ambient temperatures and a static IV
curve at 294°K................................................................................................................... 92
4.9
Measured and Simulated Dual Pulse IV curves with DC Offset
(Vds=3V,Vgs=2.1V with Vgs:0.9V~2.5V. 0.4V ste p )............................................. 94
4.10
Measured(circle) and Sim ulated (solid line) S-param eters........................................95
4.11
Measured and Simulated Pow er Gain and Power Added Efficiency
at 1G H z............................................................................................................................. 96
4.12
Measured and Simulated Harmonic Power at 1GHz.................................................. 97
4.13
The equivalent circuit model o f one port 1 nH inductor........................................... 98
4.14
Simulated (+) and m odeled (solid line) S-parameters o f one port 1
nH inductor........................................................................................................................ 99
4.15
The equivalent circuit model of one port 1.9 pF cap acito r....................................... 99
4.16
Simulated (+) and m odeled (solid line) S-parameters of 1.9 pF
capacitor.............................................................................................................................100
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4.17
The circuit diagram o f the LTCC power a m p lifier.................................................. 103
4.18
LTCC layout of 1.9-GHz DECT High Efficiency Power Amplifier.................... 104
4.19
The photograph of the LTCC power am plifier.......................................................... 104
4.20
The measured (A.A.#) and simulated (solid line) gain, PAE and
output power at 1.9 G H z .............................................................................................. 105
4.21
The measured small signal performance of the pow er am plifier.......................... 106
xii
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SUMMARY
Mobile communication systems require low cost and high performance RF frontend solutions such as power amplifiers, mixers, and oscillators. The need for a high
volume, low cost, and mature technology for wireless communications has propelled the
increasing use of silicon MOS technology at RF and microwave frequencies.
One of the main objectives of this research is to develop an improved deep sub­
micron MOSFET RF nonlinear model incorporating the breakdown voltage turnover
behavior in a channel current model with infinite order o f continuity. This model also
includes a new drain-to-substrate nonlinear coupling network for the accurate prediction
of harmonics and intermodulation distortions (IMD). This research contributes to shorten
the time-to-market and improve the circuit performance of silicon based RFICs.
The other objective is to develop a high efficiency power amplifier for 1.9 GHz
wireless communications. The novel CMOS-LTCC power am plifier for a 1.9 GHz
Digital Enhanced Cordless Telephone (DECT) is implemented based on the passives on
Low Temperature Co-fired Ceramic (LTCC) and a new temperature dependent nonlinear
model for power MOSFETs. This development can contribute to reduce the design cycle,
the complexity and the cost of silicon based RF transceiver module development by
leveraging low cost deep sub-micron MOSFET process and multi-layer LTCC
technology.
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CHAPTER I
INTRODUCTION
0
The need for a high volume, low cost, and mature technology for wireless
communications has propelled the increasing industry use of silicon MOS technology at
RF and microwave frequencies. During the past decade the requirement for high-level
circuit
integration
and
higher
operating
frequencies
has
motivated
prominent
advancements in commercial silicon MOS technologies [1-3].
Mobile communication systems require low cost and high performance RF frontend solutions such as power amplifiers, mixers, and oscillators. The power amplifier (PA)
is the essential front-end component and a high power added efficiency of the PA is
generally required in order to increase the overall system efficiency.
To design MOS analog nonlinear circuits, such as power amplifiers that operate at
a high frequency and a low bias voltage, the RF circuit designer needs a reliable and
accurate nonlinear device model. As the gate length moves towards the deep sub-micron
regime, the characteristics of the device at RF frequencies can not be accurately modeled
using classical approaches such as MOS9 [4] and BSIM3 [5] without incorporating a
large number of empirical fitting parameters and additional external circuit elements.
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This is because conventional short channel models have generally been developed from
empirical extensions o f physical long channel models.
Several empirical RF nonlinear models have been proposed for silicon M OSFETs
with different gate lengths [6-7]. These models focused on the nonlinear channel current
and the nonlinear terminal charge. However, not much attention has been paid to the
second order effects in deep sub-micron nonlinear MOSFET models at RF and
microwave frequencies. As the gate length decreases to the deep sub-micron or ultra sub­
micron regime, second order effects such as breakdown behavior and substrate coupling
become more important for high frequency and low bias operation. The importance of
second order effects on the RF performance o f deep sub-micron MOSFETs provides the
motivation for an accurate deep sub-micron M OSFET RF nonlinear model.
On the other hand, passive components occupy a significant portion o f the total
chip size in RF and microwave integrated circuits. Silicon MOS passives remain one o f
the main concerns to implement on-chip RF circuits due to excessive loss mechanism [810]. There is no existing solution that truly solves the substrate loss of the silicon
substrate, a major factor responsible for low Q passives. Typical silicon MOS R F circuits
consist of a combination of on-chip and discrete passives [11-12] in order to meet the
specifications. M ulti-layer ceramic-based integrated passives have been demonstrated as
a good option [13-15] to achieve high Q passives.
One of the main objectives of this proposed research is to develop an improved
deep sub-micron M OSFET RF nonlinear model incorporating the breakdown voltage
9
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turnover behavior in a channel current model with infinite order of continuity. This model
also includes a new drain-to-substrate nonlinear coupling network for the accurate
prediction of harmonics and intermodulation distortions (IMD).
The other objective is to develop a high efficiency power amplifier for 1.9 GHz
wireless communication applications. The novel CM OS-LTCC multi-layer microwave
integrated circuit power am plifier for a 1.9 GHz Digital Enhanced Cordless Telephone
(DECT) is implemented based on the passives on Low Temperature Co-fired Ceramic
(LTCC) and a new temperature dependent nonlinear model for power MOSFETs. This
development is the first integrated CMOS PA using LTCC and a significant step towards
the realization of a highly integrated CMOS RF system using LTCC multi-layer integral
passives.
3
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CHAPTER II
RF DEVICE NONLINEAR MODELING APPROACHES
FOR POWER AMPLIFIER DEVELOPMENT
2.1 Active Device RF Nonlinear Modeling Approaches
There are two approaches one can take in expressing in the nonlinear behavior of
the active devices. They are physical modeling and equivalent circuit modeling. The first
one is developed from material property, layer structure and from the geometry of the
device whereas the second one is based upon the various measurements such as pulse IV. S-parameters and DC I-V.
These device models serve two groups of engineers: device and circuit designers.
Equivalent circuits have traditionally been geared towards engineers who are well versed
in circuit analysis and design, whereas physical models were, until recently, the sole
domain of the device physicist. The internal operations o f the device are usually of little
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interest to the circuit designer while they are of extreme importance to the device
engineer.
This demarcation is gradually being eroded as MMIC foundries start to allow the
circuit designer to have limited control over processing steps so that active devices can be
tailored to improve the overall circuit performance. M oreover it has been realized that
yield analysis are best determined using physical models. On the other hand, most
physical models are computationally expensive and cannot be used as computer aided
design tools for circuit analysis, let alone optimization. The opposition against physical
models by circuit designers can be explained by the complexity o f the physical model,
which makes the simulation time consuming.
2.1.1 Advantages o f Physical M odeling
When properly formulated, physical models have the potential to accurately
describe the terminal characteristics o f a device, even under highly nonlinear conditions.
The physical models give a direct link between physical parameters and electrical
performance by taking into account the basic equations o f charge transport in
semiconductors. These equations can be solved together with the appropriate boundary
conditions to represent the behavior o f the device.
Furthermore, the ability to examine the effect o f physical param eter and geometry
variations on these characteristics has made physical models extremely attractive to
device designers. In contrast, it is difficult to relate equivalent circuit models to the
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geometry and doping profiles in modem compound semiconductor devices. This suggests
that physical modeling will be the prevalent method chosen in the development o f new
devices.
The Study o f the device physics
Physical E q u ation F o rm u lation
E q uatio n Sim plification
Network Synl
a
Physical Model
Figure 2.1 Flow Diagram for Physical Model Development
However, once a device has been developed, it is still the case that any circuit
incorporating it will usually be designed with equivalent circuit techniques. Although
equivalent circuits usually require measurements for obtaining elem ent values, their
topology can be derived from the device physics in many cases. Indeed, the most logical
route to a reliable device model is through a detailed study o f the device physics.
Unfortunately, equivalent circuits require measurement-based parameter extraction
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procedures whether they are physically or empirically based.
The procedure of the
development of physical model is shown in the Fig. 2.1.
2.1.2 Advantages o f Equivalent Circuit M odeling
In the equivalent circuit model, the nonlinear component’s behavior is described
by analytical functions that have bias dependence on the supply voltages. The linear
components can be extracted based on the measured S-parameters at each bias condition.
In many cases parameter extraction is based on a multi-variable optimization, which
means there are no unique solutions and there are model parameters with non-physical
element values. Therefore, the main consideration to equivalent circuit modeling is the
fact that it is important to relate element values to physical parameters.
M a th e m a tic a l M o d e lin g
M o d e l V a l id a tio n
Network Synthesis
a
Figure 2.2. R ow Diagram for Equivalent Circuit Model Development
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It appears likely that equivalent circuit models will continue to be used for circuit
design while physical models will dominate device design. The optimal all-purpose
device model has allured engineers and will probably continue to do so in the future.
However, the distinction between the two basic model types is becoming blurred as
circuit designers begin to have a slight control over device parameters. Even if a physical
model can be found to simultaneously satisfy the requirements for accuracy and
computational speed, it is almost certain that circuit designers will still use an equivalent
circuit representation o f that model largely due to its simplicity, easy parameter
extraction and their familiarity with this circuit. The flow diagram for the equivalent
circuit modeling is shown in Fig. 2.2.
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2.2 Issues on RF Nonlinear Modeling of MOS Field Effect Transistors
Today, deep sub-micron CM OS processes can give high cut-off frequencies and
better noise figures, making them an attractive alternative for RF/Microwave circuit
integration [16-17]. In addition, CM OS offers very large scale integration capabilities
allowing for a high level o f integration. There is no doubt that new wireless products will
emerge utilizing CMOS technologies for RF circuit integration.
The design of a RF circuit for real components still remains a challenge because
of the limitation on power consumption, noise characteristics and lossy substrates.
Therefore, it is important to be able to predict the circuit performance in order to reduce
design cycle and succeed on the first try. For the low frequency range, the simulation of
RF circuits is relatively accurate with the available BSIM3v3 [18] or MOS 9 [19] models.
In the high frequency range, these models cannot accurately predict the performance
without taking parasitic effects into consideration.
There are three main issues in M OSFET RF nonlinear modeling approaches. The
first issue is the thermal effect such as self-heating and ambient temperature. The thermal
model including the self-heating effect is important for large-size devices for power
amplifier applications. The second issue is to build an accurate breakdown current model.
As the gate length is getting smaller and smaller, the breakdown voltage is generally
decreasing. For accurate prediction o f large-signal operation, a more precise breakdown
model is critical. The third issue is to incorporate the substrate nonlinear coupling effects.
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2.2.1 Thermal Effects
The thermal conductivity of silicon is about three times larger than the one of
GaAs. This is one of the advantages for silicon power devices. Generally, GaAs devices
have significant self-heating effects due to the operating bias power consumption. For
MOS field effect transistors, the channel current decreases as the channel temperature
increases. The increase of the channel temperature is caused by the increase of the
ambient temperature and the self-heating due to the DC bias condition. Thermal effects
due to the self-heating are insignificant in small-signal gain amplifiers. However, these
are more significant in high power devices and show a negative conductance trend on the
I-V curves.
These thermal effects are getting more important in the nonlinear channel current
modeling o f power devices. Usually in silicon MOSFET devices for small-signal gain
amplifiers, it is hard to see the self-heating effect from the I-V curves. For power
MOSFETs, this self-heating effect cannot be neglected. To develop an accurate nonlinear
device model for high performance pow er amplifiers, it is also necessary to incorporate
the thermal behavior, such as self-heating and ambient temperature effects.
2.2.2 Breakdown Current Effect
Although constant-field scaling rules are used in the designed VLSI circuits that
are implemented using sub-micrometer technology, some o f the short-channel MOS
10
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transistors may be operated at voltages very close to their gate-oxide breakdown or drainto-source breakdown, which cause reliability problems.
Drain
Depletion
Layer
6
Figure 2.3. Breakdown Mechanism for Deep Sub-micron MOSFET
Fig. 2.3 shows the breakdown mechanism in deep sub-micron MOSFETs.
Bipolar-induced breakdown or impact-ionization breakdown mechanisms for a shortchannel MOSFET have been studied [20-22]. The physics o f the problem is illustrated in
Fig. 2.3. Channel electrons that travel through the high-field avalanche region cause
impact ionization. The electric Field in this high-field region sweeps the impactionization-generated electrons into the drain, and holes into the bulk. The ohmic voltage
drop due to the hole carrier current flowing through the substrate forward biases the
11
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source junction and causes it to inject electrons. Part of these injected electrons travel to
the drain junction and will be further multiplied by the drain field, causing positive
feedback action. Due to the substrate current component, the behavior o f the breakdown
current is not simple. There is the turnover trend in the drain-to-source breakdown
voltage caused by the lossy substrate leakage current.
An accurate description of the breakdown behavior is therefore very important in
the evaluation of both circuit design and circuit reliability. The maximum allowable
oxide electric field is limited by the material properties of the gate oxide, whereas the
drain-to-source breakdown is governed by process parameters. The physics underlying
the drain-to-source breakdown is now clear due to an intense research effort during the
last decade [23-24]. An accurate breakdown model is required to predict harmonics and
intermodulation distortions due to the large signal operation around the breakdown
region.
2.2.3 Substrate Nonlinear Coupling Effect
At high frequencies, the RF signal at the drain couples to the bulk terminals
through the drain-to-substrate junction capacitance and the lossy substrate resistance.
This coupling network mainly affects the total output impedance, which is dependent
upon the biasing of the circuit.
In order to obtain a precise prediction of device output power performance, an
accurate model of substrate nonlinear coupling effect is required, especially in power
12
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devices. This is required because even small variations in the output matching condition
for power devices can cause a significant change in power performance.
13
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2.3 Design Techniques for Power Amplifiers
The power amplifier is a key component in the design of an RF/microwave
transceiver. It determines the overall efficiency and linearity of the entire transceiver
circuit. The main market drivers for the power amplifier are the cellular radio handset.
The 5 GHz ISM band may be another market driver in the near future. In five years, a 10
billion dollar market is being expected for the power amplifier business for RF frond-end.
The hand-held application requires high efficiency operation o f the PA. The device
technology focusing on the low voltage operation allows for a decrease in the supply
voltage up to 3.5 V in order to save total power consumption. To achieve better
performance, various technologies are being considered from the cost and performance
point o f view. Also, the thermal requirements are important because handheld
applications don't have much room for heat sinking.
2.3.1 Trends in Power Am plification
For high efficiency applications, a lower supply voltage is required. The bias
supply with a negative bias is preferable in the implementation o f a PA. For spectral
efficiency, more efficient digital modulation schemes, such as quadrature phase-shift
keying. Gaussian minimum shift keying, and time/code division multiple access. Digital
modulation offers a number o f advantages over analog modulation, such as increased
channel capacity and the ability to transm it and receive messages with greater accuracy
14
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than an analog communication system in the presence of noise and distortion. In digital
communication systems, a finite number of electrical waveforms, or symbols, are
transmitted. Each symbol can represent one or more bits. The job o f the receiver is to
estimate which symbol was sent by the transmitter. The amplitude or shape of the
received signal is important as long as the receiver can clearly distinguish one symbol
from another. To satisfy the requirements of digital modulation, power amplifiers require
efficient amplification with moderate linearity. The other main concern is to develop a
package to enhance cost, size, performance and ease-of-implementation. Power amplifier
design techniques can be divided into two categories; the design based on load-pull
measurements and based on the large signal model of the device in RF nonlinear circuit
simulators.
2.3.2 Class o f Power Amplifiers
Class A
Class B
C lass AB
k
C lass F
ix
V dd
k
:
3
‘s
A
id
:▲
V ds
$
▲
\ /
/N
Figure 2.4. Voltage and current waveforms for different classes of PA.
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In power amplifier applications, the operating bias determines the basic class o f
operation. In a class A. the amplifier operates in the linear region o f the transistors with
100% conduction angle. 50% efficiency and high gain. In addition, the linearity is good
in class A operation. The class B has 50% conduction angle and maximum o f 78.5%
power added efficiency. The rapid gain degradation around the pinch-off region makes it
hard to get this ideal efficiency and high power gain. This makes a class AB operation
useful for high efficiency PA design. For very high-efficiency power amplifiers, the class
F power amplifier proves to be very useful. The voltage and current waveforms o f the
various classes are shown in Fig. 2.4.
2.3.3 High Efficiency Power A m plifier Design
0
Zopt
Input
M atching
Circuitft LPF
0
2fo BPF
▼
(a)
16
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Vd, Id
Id W aveform
(Class B)
Vd : With H arm onic Tuning
0
Time
(b)
Figure 2.5. Harmonic tuning circuit for high efficiency (a) and
waveforms of a class F operation (b).
To design high efficiency power amplifiers, various classes o f operation are used.
One o f them is the class F operation that is shown in Fig. 2.5. For high efficiency
operation, the harmonic tuning circuit is required for even and odd harmonic tuning. The
even harmonics are required to be the short-circuit impedance while the odd harmonics
are required to be open-circuit impedance for class F operation. The topology for the
output-matching circuit may be a low-pass filter type to block harmonics. The class F is
17
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basically biased at the class B operation point, needing a harmonic tuning circuit. The
ideal class shows 100% power added efficiency due to no DC power consumption.
2.3.4 Linear Power Am plifier Design with high efficiency
The efficiency of the power amplifier is very important for the constant envelope
RF signal, such as frequency modulation (FM) and Gaussian Modulation Shift Keying
(GMSK) that are used in the analog cellular telephone system (AMPS) and global system
for mobile communications (GSM) standard. However, non-constant envelope RF signal
such as a CDMA signal requires a linear amplification o f the power amplifier. The design
trade-offs between linearity and efficiency makes it difficult to develop a power amplifier
satisfying both requirements for hand-held applications. The digital modulation schemes
utilized in present second-generation cellular systems, proposed 3G cellular systems and
in many other wireless applications require linear power amplifiers in the transmitter unit
of the mobile radio.
The battery life of these radios place a premium on the power amplifier circuit
exhibiting maximize efficiency with a reasonable level of linearity, both of which must
be balanced against cost and size constraints to be a viable solution. The point at which
the amplifier exhibits maximum efficiency is not necessarily at the highest transmitpower level. The use o f power control in certain systems where the radio transmits at
power levels tens o f dB from the maximum for extended periods time, may place a
18
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significantly higher weighting on amplifier efficiency under power back-off rather than at
peak conditions. The goal of improving the inherent design trade-off between efficiency
and linearity has triggered a great deal of interest in applying more advanced amplifier
architectures, including supply modulation (envelope following, envelope tracking),
phasing (LINC). feedback (polar, cartesian, harmonic), Doherty, and load modulation to
name a few.
Envelope
Detector
Amplifier
RF Input
RF Output
Limiter
Amplifier
Com biner
Figure 2.6. Envelope Elimination and Restoration Method.
One example o f the linear technologies is the envelope elimination and restoration
method. Fig. 2.6 shows the block diagram of this technology. Using an envelope detector
and limiter, the input RF signal can be amplified in the linear region of the PA and
19
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combined with the amplified envelope. The com biner can be implemented using a
switched-mode power amplifier.
The other example is a Doherty power amplifier. RF and microwave systems have
placed an increasing demand on power amplifiers to simultaneously provide low
distortion and high power-added efficiency (PAE). Promising results for a hybrid
realization of a 1.37-GHz microwave Doherty am plifier have been presented in [25] and
[26]. The circuit was reported to achieve a single-tone PA E’s greater than 60% at 5.5-dB
back-off from the 1-dB compression point.
lamda/4
Zo
RL
Z2
Figure 2.7. Doherty power am plifier topology.
20
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The standard circuit topology for a Doherty amplifier is shown in Fig. 2.7.
Amplifier 1 is referred to as the carrier amplifier and is typically operated in Class AB
mode. Amplifier 2 is referred to as the peak am plifier and is operated in Class C mode.
Both amplifiers are designed to deliver maximum power when presented with a load
impedance. The peak amplifier is gate biased to be o ff at low input drive levels and begin
to turn on when the carrier amplifier starts to compress.
The output power from the two amplifiers are combined with a quarter-wave
impedance transform er o f characteristic impedance. The actual load for the amplifier will
have to be transform ed to RL. A quadrature 3-dB hybrid is required at the input o f the
circuit so that the carrier amplifier and peak am plifier signals will combine in phase at the
output of the quarter-wave line. The hybrid is also useful for achieving a low-input
VSWR for the amplifier. Based on this technology, it is possible to achieve both power
added efficiency and linearity. The Doherty power amplifier provides a simple and
elegant method for improving efficiency without additional circuitry.
2.3.5 Load-Pull M easurem ent technique
Designing by the load-pull technique is the purely empirical approach to find the
optimum impedance point for power output, power added efficiency, harmonics and
intermodulation distortions. Using this measurement system, the tuner impedance seen by
the DUT is varied and measured for each optimum power characteristic. Based on this
measurement, the contours can be plotted on the Smith chart. With small-signal power
21
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levels, the contours correspond to constant gain circles generated from measured Sparameters. As the input power level is increased to saturate the DUT, the contours
become closer together and less circular.
Power Meter
'»uner
Timer
OUT
DC Source
••• = = c" - 2
~5.\S
’ 52.
:» _ C 3 3 Gj ” ^ o
A 2 2 r- 2
2
2 35. c . . r c e I —e
32 - 5 ' 5
■3
2 2 9 ”* >5 2 2 s,
2
=
S *_3'"
V.CC
.c
v 3*
598
25
’3 3
2'
-'-3
• 7 ~- •
V3«
'3 3
525
9 =9
*2 \ *
*5
99
;= _ e -
2.8. Loadpull setup and Measurement using 12 dBm input signal
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Fig. 2.8 shows a load-puil setup for fundamental power measurements and a
sample measurement. The load-pull system varies the source and load impedances as
seen by the device and measures its power characteristics such as power output, power
added efficiency, gain, intermodulation distortion (IMD) and adjacent channel power
ratio (ACPR). For these power characteristics, each contour can be generated after
measurements at different load or source impedances.
The sample measurement shows that the conjugate matching point is the optimum
point for gain and power output for the small signal. However, under large-signal
conditions, this is not the case. The maximum power output is not conjugately matched
anymore. This nonlinear behavior cannot be predicted by small-signal measurements
such as the S-parameter measurement. In addition, each power performance has different
optimum matching points. The disadvantages o f load-pull design include entering regions
of instability, significant investment for an autom atic tuner system and com ponent power
limitations for the active tuner case. On the other hand, when dealing with a new. and yet
unmodeled, device or investigating performance sensitivity to impedance mismatches,
carefully measured load-pull data can provide the most convincing evidence for amplifier
impedance-related behavior.
2.3.6 Nonlinear Circuit Simulators using A ctive Device Nonlinear M odel
There are mainly three non-linear simulators for circuit simulation. Tim e domain
methods are based on solving of circuit differential equations in the time domain. The
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starting point is usually chosen as the result o f a DC analysis. Methods that work entirely
in the time dom ain represent the most natural and straightforward approach to the
simulation problem. However, there are several factors which limit the applicability of
these methods to microwave circuit analysis. First, the actual circuits may contain
dispersive transm ission lines that are difficult to analyze in the time domain. Second, if
the steady state response is of major interest, a large number of time steps may be
required, thereby consum ing a large amount o f CPU time and memory.
In the harm onic balance method, variables are represented by their Fourier
coefficients rather than functions of time. The transients are naturally avoided and
therefore the com putational complexity depends only on the size of the circuit and not on
the actual frequencies or time constants present in the circuit. In this method, the linear
elements are analyzed in the frequency dom ain whereas the non-linear elements are
simulated in the tim e domain. The interface between the two domains is accomplished by
fast Fourier transformation (FFT). The Fourier coefficients of the unknown variables are
then optimized to give an approximated solution. Harmonic balance techniques have been
used extensively to analyze all kinds of non-linear microwave subsystems.
Volterra series theory was first introduced in 1930 and was improved by W einer
in the 1950s for the expansion of functionals in terms of orthogonal polynomial series.
W einer’s functional expansions, now known as Volterra non-linear transfer functions,
can handle frequency dependent systems with single valued input-output characteristics.
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Two non-linear simulators in the frequency domain have advantages and disadvantages.
Table 2.1 shows the advantages and disadvantages of these methods.
Analysis Method
Volterra Series
Frequency Domain
Analysis
Analysis
Advantages
Disadvantages
Smaller Calculation Time
Only weakly
The effect o f the internal
nonlinear circuit
elem ents to the output
simulation
No information
Harmonic
Balance Analysis
Both Tim e domain
for the effects of
Highly nonlinear circuit
and Frequency
the internal
simulation is possible
Domain Analysis
elem ents to the
output
Table 2.1 Advantages and disadvantages o f nonlinear circuit simulators
Microwave nonlinear circuit simulators can provide insight into circuit behavior
that cannot be directly measured. The steady-state solutions of harmonic balance and the
time domain transient response simulators have advantages that make both techniques
useful for circuit analysis. Using nonlinear device models, these simulators can simulate
the nonlinear behavior o f the power amplifier characteristics. Therefore, device nonlinear
modeling is one of the key issues for the development of CMOS RF components.
25
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CHAPTER III
SILICON DEEP SUB-MICRON MOSFET RF NONLINEAR
MODEL DEVELOPMENT
3.1.
Introduction
The need for a low cost and mature technology for wireless communications has
propelled increasing use of silicon MOS technology at RF and microwave frequencies.
The improvement of the cutoff frequency (fT) and the maximum oscillation frequency
(fmx) has enabled higher frequency of operation and better noise performance.
Rapid advances in deep sub-micron silicon MOSFET’s have made these devices
an attractive solution for designers to implement silicon RF and microwave circuits.
Since the maturity of silicon integrated circuit technology is well established, silicon
RFIC’s play a key role for wireless communications operating below 2 GHz.
In order to ensure the circuit performance for the required frequency bands and
also shorten the design cycle, device models are very important [27]. Also, a well-
26
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described nonlinear device model is critical for large-signal or harmonic operation. This
model should take into account parasitic effects which can be drastic at high-frequency
operation. In addition, a complete model should also take care of the nonlinear elements
where these elements are sensitive to bias conditions.
This study demonstrates the DC and RF performances of the recently developed
advanced silicon M OSFET’s for mass production with a minimum gate length of 0.25pm . Since the RF model is difficult to realize by its physical formula, empirical equations
are used to describe these nonlinear behaviors. The model parameters in the model
equations are determined by the measured results. By combining these parasitics and a
nonlinear formula. M OSFET’s with deep sub-micron gate length can be characterized
and implemented in RF circuit design.
An improved deep sub-micron (0.25-pm) MOSFET RF large signal model that
incorporates a new breakdown current model and drain-to-substrate nonlinear coupling
was developed and investigated using various experiments. An accurate breakdown
model is required for deep sub-micron M OSFET's due to its relatively low breakdown
voltage.
For the first time, this RF nonlinear model incorporates the breakdown voltage
turnover trend into a continuously differentiable channel current model and a new
nonlinear coupling network between the drain and the lossy substrate. The robustness of
the model is verified with measured pulsed I-V, S-parameters, power characteristics and
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intermodulation distortion (IMD) levels at different input and output termination
conditions, operating biases, and frequencies.
This proposed modeling approach significantly improved the accuracy of deep
sub-micron MOSFET nonlinear model for the silicon RF pow er am plifier application for
wireless communications.
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3.2. An New Deep Sub-micron MOSFET RF Nonlinear Model
3.2.1. Proposed Deep Sub-micron M O SFET RF Nonlinear M odel
The MOSFET. whose substrate is connected to the source, is widely used for RF
power amplifications. The three-terminal model of a MOSFET is simple and easy to
develop. We have developed the three-terminal nonlinear MOSFET model that is
sufficient for RF power amplifier development. The equivalent circuit o f the proposed
nonlinear model is shown in Fig. 3.1.
Rl
C ate O
H ssat
Ctk
Rth
HsB
Rs
Source, Substrate (Body)
Fig. 3.1.
Equivalent circuit of the proposed deep sub-micron common source
N-M OSFET (10 finger x 25-|im )
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This model includes a new breakdown current. IdsB- with breakdown voltage
turnover behavior and a new nonlinear coupling network consisting o f a series connection
of Cdd and Rdd between the drain and lossy substrate. This nonlinear substrate coupling is
one of the difficulties in MOSFET nonlinear modeling as the operation frequency
increases. The substrate has an electrical connection to the source.
The dashed line in Fig. 3.1 surrounds the nonlinear coupling network. This model
also includes temperature dependent nonlinear channel current Ids and nonlinear
capacitance models such as gate-to-source capacitance Ces, gate-to-drain capacitance C ed.
and drain-to-source capacitance Cds- The nonlinear channel current and capacitance
models have been implemented using continuously differentiable nonlinear models. The
pad parasitic elements are represented by the pad capacitances Cpgs, Cpgd, and CpdS as well
as resistances Rpgs, RPgd. and Rpds. These pad parasitics are not negligible due to the
coupled lossy silicon substrate.
3.2.2 Nonlinear Channel Current M odel
Much research has focused on the importance of modeling GaAs FET currentvoltage characteristics and their derivatives for accurate large signal model predictions.
This is important for accurate prediction of harmonic distortion, which is an important
aspect of modeling circuits. The non-linear current source is considered the primary nonlinearity, although contributions from the non-linear gate capacitance are also important
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and will be discussed later. The equation for the drain current is based on the nonlinear
channel current model with continuous derivatives with respect to the bias voltages.
The new drain current model includes gate voltage dependence on drain current
saturation and sub-threshold conduction. Drain-source current is modeled using a single
continuously differentiable function. This model focused on a channel current model that
ensures the continuity of all its derivatives, because the prediction o f IMD and harmonics
is strongly related to the channel current continuity. This model is summ arized by the
following equations.
(3.1)
vgst 1(Vgs • ^ds ) = ^gs - (VTO + Y^ds )
(3.2)
(3.3)
(1 + p c m Kgsl GMEXP
VGEXP (1 + X Vds ) tanh (
^dssat ^ g s -^ds ) ~ Peff ^ g s t ^
v
gst
SATEXP
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(3.4)
The trans-conductance and output conductance are obtained by differentiating
(3.4) with respect to Vgs and Vds respectively. The complete set of model fitting
parameters are a, /3. y, A, VTO, VST, ncrit, GMEXP. and SATEXP. Using (3.2), a
discontinuity in derivatives o f the drain current expression can be avoided even around
the sub-threshold conduction region. In (3.2), Vgst is asymptotically linear in V ^ i for
»
VTO, and asymptotically approaches zero for Vgsti < 0.
The addition of subthreshold conduction is extremely im portant to avoid a
discontinuity in derivatives o f the drain current expression at
= VTO. Field dependent
mobility in MOSFET’s is well known. The tangential field caused by the applied gate
voltage is responsible for two effects, it produces an inversion layer of mobile carriers
adjacent to the silicon surface and it causes mobile charge carriers to scatter more
frequently than in the absence o f an applied gate potential.
Equation (3.3) is used to represent the mobility degradation of the carrier with
gate bias voltage Vgs. The electric field profile near the source, com bined with a narrow
gate length causes carrier velocity saturation with applied drain-source voltage. The
combined effect is a trans-conductance versus gate-source voltage profile that deviates
drastically from the traditional parabolic shape.
Drain current saturation is modeled using the hyperbolic tangent function. As
mobility is degraded with an increase in applied gate voltage, the critical field for velocity
saturation is increased, which requires a higher applied drain voltage. The effect of this is
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most noticeable in the trans-conductance and will be discussed in the next paragraph.
Parameter SATEXP is used to vary the gate voltage dependence of velocity saturation. As
SATEXP approaches zero, velocity saturation is dominated by the drain-source voltage.
Modifying drain current saturation by the gate voltage causes trans-conductance to
decrease in a parabolic manor after the saturation point has been reached. Thus, for a
fixed drain-source voltage applied to the new model, the current saturation voltage
continues to decrease by the pinch-off potential defined by (3.1), as the gate voltage
increases.
This occurs most noticeably for low drain-source voltages. W ithout the VesI
variable in the hyperbolic tangent function in (3.4), trans-conductance would saturate and
roll over, but it would not display a parabolic decrease as seen in the measured device
trans-conductance. With regard to single gate devices, this characteristic is unique to
M OSFET’s. Modifying drain current saturation by the gate voltage causes trans­
conductance to decrease in a parabolic manor after the saturation point has been reached.
Thus, the nonlinear channel current model is based on the hyperbolic tangent function in
(3.4).
3.2.3. Breakdown Mechanisms in a long-channel MOSFET
The value of the various voltages that can be applied to a M OSFET device should
be limited to avoid several forms o f breakdown. One is the junction breakdown. The
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junctions formed by the substrate and the drain (or source) region will conduct a large
current if the reverse bias applied to them exceeds a certain value. This value depends on
the gate potential and can be different from that predicted by com m on pn junction theory.
The field in the junctions near the surface is influenced by the presence o f the gate.
Junction breakdown will occur even when the device is off.
When the device is on, carriers moving energetically in the channel can impact
silicon atoms and ionize them, producing electron-hole pairs. This is referred to as impact
ionization. The generated pairs can gain enough energy to impact on silicon atoms and
produce more electron-hole pairs. This is called the avalanche effect, and is more
pronounced in the pinch-off region near the drain where fields can be high. Currents
larger than those predicted by common device models will then flow, and the
phenomenon is referred to as channel breakdown.
These breakdown effects are non-destructive. Once the large voltages producing
them are removed, the device will function properly as long as no permanent damage
caused by overheating has occurred. A destructive breakdown mechanism is oxide
breakdown. It occurs when the electric field in the gate insulator exceeds a certain value,
resulting in a permanent short circuit through the insulator. Static charge, such as that
transferred to gates by handling devices with bare hands, is known to cause oxide
breakdown. For this reason, protective devices are often used at those input terminals of
an MOS integrated circuit that are connected to transistor gate.
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3.2.4 Breakdown Mechanisms in a short-channel M OSFET
The breakdown forms discussed for long-channel devices occur in short-channel
devices as well. However, the latter also exhibits an effect called punch-through. Punchthrough is attributed to the barrier-lowering effect already discussed, in which twodimensionai effects in the region between the source and drain increase the electrostatic
potential, thus reducing the barrier for the electrons’ entering that region. A current can
flow even at gate-source voltages lower than the flat-band voltage and two-dimensional
simulations show that this current flows in a subsurface path.
If the drain potential is increased, the electrostatic potential at points between the
source and drain will increase and the barrier for electrons will decrease, resulting in the
drain-induced barrier lowing effect. Thus the punch-through current will increase.
Experiments and two-dimensional numerical simulations show that the punch-through
current is decreased if the substrate potential is made more negative. To avoid punchthrough problems, the substrate doping is increased through ion implantation below the
surface, to limit the source and drain depletion regions there, thus reducing twodimensional effects and the associated barrier lowering. The implanted region does not
extend too deep, and the body effect and junction capacitances still correspond to the
more lightly doped bulk, which is desirable.
Other undesirable effects occur due to the high velocity o f electrons in the
presence of high longitudinal fields. This has already been reported for long-channel
35
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devices, but such effects can be more troublesome in short-channel devices. Highvelocity electrons can generate electron-hole pairs by impact ionization and the avalanche
effect, resulting in a form of breakdown.
Most of the electrons are attracted by the drain, but the holes enter the substrate
and constitute part of the parasitic substrate current. This situation is further complicated
by the fact that the region between source and drain can act like the base o f a bipolar npn
transistor, with the source acting as the emitter and the drain as the collector. If some of
the holes mentioned above are collected by the source and if the corresponding hole
current creates a voltage drop in the substrate material, the substrate-source pn-junction
will conduct significantly. Electrons can be injected from the source to the substrate, just
like electrons injected from em itter to base in npn transistors. These electrons can gain
sufficient energy as they travel toward the drain to cause additional impact ionization and
create new electron-hole pairs. This constitutes a positive feedback mechanism, which
can sustain itself if the drain voltage exceeds a certain value. This is observed externally
as
breakdown, causing current
values higher than
normally
expected.
Further
complications can arise due to the fact that some electrons generated because of high
fields can escape the drain field. These electrons can travel long distances into the
substrate, and can affect other devices on a chip. Impact ionization effects are less severe
in p-channel devices.
36
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Yet another troublesome phenomenon related to high electric fields, either
longitudinal or normal, is caused by high energy electrons or holes that enter the oxide
where they can be trapped, resulting in oxide charging. Sudden transients can augment
this effect. Oxide charges produced in this way accumulate with time, and tend to
gradually degrade the device performance. Thus, for given bias conditions, the device can
have a limited lifetime, after which its performance will be unacceptable for a certain
application. Such effects can also occur in long-channel devices, but are much less severe
because their electric fields are usually smaller and when such fields occur, they are
limited to a small part off the channel. Depending on the fabrication process details, one
or more of the above phenomena will limit the applicable range o f bias voltages for a
given device.
3.2.5 New Breakdown Current M odel
For circuit design and reliability analysis, an accurate expression of breakdown
current is important. The physics underlying the drain-to-source breakdown or simply the
drain breakdown of MOSFET’s is now quite clear after a great deal o f effort was put in
during the last decade. Deep sub-micron MOSFET transistors may be operated at bias
points very close to their drain-to-source breakdown voltage. The gate oxide material
limits the maximum allowable electric field on the gate while the drain-to-source
37
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breakdown voltage is dominated by process and device parameters. The drain breakdown
can be caused by impact ionization [28-29] or by the parasitic bipolar transistor [30].
For a MOS transistor operated in saturation mode, the electric Field near the drain
region, which is often called the velocity saturation region or pinch-off region, increases
significantly and causes impact ionization. The generated electrons are swept into the
drain and enhance the drain current significantly, whereas the holes flow into the
substrate. Because the conductivity o f the substrate is low, the substrate current may
cause a prominent voltage drop across the substrate. This voltage results in the body
effect, which modifies the transistor biasing and increases the channel current. Either
infinite multiplication or finite multiplication with positive feedback through the substrate
can generate the avalanche breakdown on the drain side o f the M OSFET [31].
The difference between these two breakdown modes is the dependence o f the
breakdown voltage on the gate bias voltage. For the infinite m ultiplication mode of
breakdown, the drain-to-source breakdown voltage increases as the gate bias increases.
On the other hand, for the finite multiplication mode, the drain-to-source breakdown
voltage decreases as the drain saturation current increases. This trend is physically
investigated in [31] and called the breakdown voltage turnover or the turnaround of
breakdown voltage.
The observed turnaround behavior of the breakdown voltage can be explained
with the newly developed model for breakdown voltage. The significant enhancement in
38
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the drain current about its saturation value can be caused by either infinite multiplication
or finite multiplication with the substrate current feedback effect.
In the infinite multiplication mode of breakdown, the electric field in the impact
ionization region is sufficiently large and results in a very large m ultiplication factor. In
addition, the channel current should be large enough such that the substrate current
feedback is insignificant and the finite multiplication breakdown cannot occur.
On the other hand, breakdown may take place even
when the impact
multiplication factor is finite because o f the substrate current feedback effect. This mode
of breakdown occurs when the saturation current is small and the channel current
enhancement due to the substrate current is pronounced. Breakdown characteristics are
governed by the channel saturation current rather than the gate bias alone even though the
saturation current is a function of the gate bias. The breakdown voltage is increasing with
the gate voltage as the drain saturation voltage is almost directly proportional to Vgs. As
V2S becomes larger, the breakdown voltage decreases a decrease with the gate voltage for
the finite multiplication mode o f breakdown. The breakdown voltage decreases as the
drain saturation current increases, and reducing the bulk resistivity will help to increase
the breakdown voltage due to the finite multiplication mode of breakdown.
For accurate performance prediction of deep sub-micron M OSFET transistors
operating at low voltage and high frequency, this breakdown voltage turnover behavior
should be represented in the channel current model. Two modes of breakdown, namely,
39
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the infinite multiplication and finite multiplication with positive feedback of the substrate
current should be modeled in the continuous breakdown current model.
To incorporate the breakdown voltage turnover behavior in the continuous
channel current model, a new breakdown model has been developed. The breakdown
starting point of drain-to-source voltage Vjs is assigned to VBon. Equation (3.5) represents
the breakdown voltage turnover trend with gate bias voltage. The variation of breakdown
current shape is expressed by (3.6). These two equations have a saturation mechanism
using the tanh function to help in the convergence of nonlinear simulators. This
continuous model can accurately predict VBon and breakdown current shape as a function
of V2S. The new breakdown model is summarized as follows.
V ^ V ^ V B ^ iA a H a n H A i-A z (Vgs~VBmil)+A3 ( V ^ - V ^ 2-A 4 (Vgs-VBmif))(3 .5 )
(3.6)
'/#;hap</^gs)-/' 5 ('4 6 Hanh( -(V^s-A 7 )))
VBlon( V zsY ls)
IdsB V„9Vds)= Ibdexp(
V Q>n+A9 ) ^ 1 0~7TZ------7 '
( VBon+Al j)
(3.7)
(3.8)
VB^n)
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Equation (3.8) is the breakdown current model with infinite derivatives and
breakdown voltage turnover trends. The fifteen parameters A0 -A n . VBbd, VBmm and Am
are fitting parameters for the new breakdown current model. The minimum value of
drain-to-source breakdown starting voltage can be chosen for the initial value of VBmin in
(3.5). To make it easier to extract the model parameters of total nonlinear channel current,
we separate the channel current into two components, the saturation and the breakdown
current components. Using this separation technique, we can exclude the coupling
between the model parameters of the two current components during extraction. The total
nonlinear channel current model is represented as (3.9) combining (3.4) and (3.8).
/ds = Saturation Current Component (/dssat) + Breakdown Current Component (/<isb)
(3.9)
3.2.6. Drain-to-Substrate N onlinear C oupling M odel
As the operation frequency increases, the high frequency drain signal couples to
the lossy substrate, which can be modeled as a reversed biased pn junction capacitance
and substrate resistance. The coupling between the drain and the lossy substrate affects
the output conductance in the high frequency regime. Efforts have been made to model
the effect of the substrate as an external network [32-33]. However, sufficient attention
was not paid to the nonlinear behavior o f the substrate coupling. The drain-to-substrate
41
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
junction capacitance has a reverse biased PN diode characteristic for normal active device
operation. The source to substrate junction also has a reverse biased PN diode
characteristic.
In this work, we have focused on the drain-to-substrate nonlinear coupling
because the electrical connection between the source and the substrate minimizes the
effects o f the bias dependent substrate nonlinear coupling. This coupling can be modeled
by using the bias dependent capacitance and the resistance through the lossy substrate.
This nonlinear behavior affects the device output conductance more for a low-resistivity
substrate compared to a high-resistivity substrate, due to the lossy substrate. W e used
sample devices on a low-resistivity substrate and modeled the substrate-coupling network
using the nonlinear capacitance and the resistance.
We also modeled nonlinear capacitances such as drain-to-gate capacitance Cd2,
gate to source capacitance Cg*. and drain-to-source capacitance Cds using continuous
functions similar to the equations in [34], Equation (3.10) represents the Cdd capacitance
model and B0 - B 3 are the fitting parameters.
Old (^ds ) = *0«1 + tanh
ds~ + ^3^ds"*))
(3.10)
Q ig ^ d s -^ gs ) =
c 0 ( 1 + tanh (CjVgS + CSVgs ~ ))(1 —tanh (CjV^j +■C^V^S~ +
42
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
))
(3.1 1)
^ g s ( ^ds • ^gs ) —
Dq(1 -h tanh (D x + D 2Vgs + Z>3 VgS“ ))(1 + tanh (D4 + £ 51 ^ ))
(3.12)
Q s ^ d s -^ g s > =
£ 0 (l + tanh ( E ^ + E jVgs2 »(! _ lanh ^
3 ^ds
+ ^d^ds 2 + ^S^ds2 )) (3.13)
The other nonlinear capacitances are modeled using (3 . 1 1 )~(3.13). The parameters
Co-Cs. D 0 - D 5 , and Eo~Es are fitting parameters to describe the nonlinear behavior of the
bias dependent capacitances. These equations are also continuous functions to help in the
convergence of the nonlinear simulator.
43
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.3. Nonlinear Model Parameter Extraction
3.3.1. RF Performance o f N-M OSFET
Deep sub-micron n-MOSFET’s were fabricated on a low-resistivity (10 Q-cm)
substrate. Devices with different gate widths and number of fingers were fabricated using
National Semiconductor’s 0.25-p.m twin-well CMOS process on
8
inch wafers.
Fig. 3.2 shows the fabricated MOSFET and test pattern for S-parameter de­
embedding. After calibration of the network analyzer with an impedance standard
substrate , the S-parameters o f the various transistor test structures were measured at
different bias points. Due to increasing the frequency range o f CM OS, the test structures
were measured up to 10 GHz.
For nonlinear model development of the deep sub-micron devices, we chose 10
finger and 25-(im gate width n-MOSFETs with common source configuration and
substrate connected to source to disable back gate effects. The RF and noise performance
of this sample are summarized in Table 3.1. In order to achieve good RF performance, a
silicided poly gate was used to decrease the gate resistance. The cutoff and maximum
oscillation frequencies o f this device demonstrate the feasibility of silicon MOS
technologies for RF and microwave applications. The device noise performance was
characterized using an ATN NP5 system.
44
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 3.2
Fabricated Test Patterns and Deep sub-micron MOSFET device
45
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
DC bias condition
V ^ l-6 V . V ^ i V
x(GHz)
28
fm
ax(GHz)
24
Fm ui(dB)
0.54 at 4.4 GHz
R n ( f i)
31
Gass (dB )
13
F opt
0.734 Z43.20
f
Rd(Q)
5.1
Cdg (fF)
68
Rg(Q )
9.2
Cds (fF)
157
Rs (Q)
4.8
Cdd(fF)
175
Lg (pH)
72
Rdd(Q)
273
Ld (pH)
43
Cpgs (fF)
45.7
Ls (pH)
57
Rpgs(Q)
22
t (pS)
2.9
Cpds (fF)
48.7
gm (S)
0.137
Rpds(Q)
20
Rds (Q)
90
Cpdg (fF)
4.4
Cgs (fF)
356
Rpdg(Q)
398
Table 3.1. RF Performance and small signal circuit parameters o f the fabricated deep sub­
micron (0.25fim) n-MOSFET with 1 0 finger and 25 nm gate width.
46
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The values of high frequency noise parameters such as the minimum noise figure (Fmi„),
equivalent noise resistance (Rn), and the minimum noise input matching point
(ropt) are
also suitable for implementation of RF and microwave receiver front-ends.
3.3.2. Channel Current an d New Breakdown M odel Extraction
The drain current is measured using an on-wafer dual pulse I-V measurement
system with zero DC bias offset (Vgs = 0 V,
model
= 0 V) for the drain channel current
/
Vacuum
Thermal
controllable
Chamber
/
TEK AM503B
Current
Amplifier
/
0
n
n
TEK TDS420A 200MHz
Oscilloscope
TEK
A6312 100 MHz Current Probe
HP8114A 100V/2A
Drain Pulse
G enerator
HP81110A 330 MHz
Gate Pulse/Pattem
Generator
/
1
J
□n □□□
□□□□□
/
Tem perature Controller
Fig. 3.3
The on-wafer dual pulse I-V measurement setup with temperature
controllable thermal chamber.
47
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The bias trap effects on dynamic I-V curves have been well studied for M ESFET and
HEMT devices [35]. Based on the pulse I-V measurements, it was found that there were
no bias trap effects on dynamic I-V characteristics of the measured M OSFET’s. The
pulse measurement setup is shown in Fig. 3.3. A short pulse was used to measure I-V
characteristics. We used 400 ns pulse width for the gate side and 200 ns pulse width for
the drain side with less than 1 % of duty cycle. The pulse width is chosen to measure
isothermal current-voltage characteristic and the duty cycle is chosen to ensure the
thermal stability o f the sample device. Therefore, this pulse width is much shorter than
the nominal thermal time constant of M OSFET’s [36]
7
6
70
o
U
A
V-
I d .P u l s e (Vd * 3.2 V)
(Vd = 3 .4 V)
(Vd = 3 .6 V)
(Vd - 3 .8 V)
60
50
«
w
3
°-.
4
(A
r
0>
J2
_
Drain C u rren t
40
<
30
m
at
D rain P u ls e
3
Q.
<n
o>
>
1
G a te P u lse
0
-1
-10
0.2
0.4
0.6
0.8
Time (usee)
Fig. 3.4.
The actual pulse waveform used to measure pulse I-V with breakdown
current. The pulse width is 400 (is for the gate and 200 ps for the drain.
48
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 3.4 shows the actual pulse waveform that was used to measure the breakdown
effects. At a constant gate bias of 1.1 V, the drain bias is varied from 3.2 to 3.8 V in steps
of 0.2 V. The drain current waveform increases rapidly as the drain bias goes above the
bias point where breakdown begins.
A pulsed breakdown measurement technique for MESFETs has been presented
for nondestructive and isothermal breakdown m easurem ent in [37].
100
80
<
G
60
E
cn
*o
40
20
0
Fig. 3.5.
0.5
1
1.5
2
2.5
Vds (V)
3
3.5
4
The measured CW I-V and pulse I-V (Vgs : 0 .6 - 1. 8 V, Step : 0.2 V).
49
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Using on-wafer dual pulse I-V measurements, we have measured the dual pulse IV curves of the n-M O SFET’s including breakdown region, and have developed a new
continuous breakdown current model that incorporates the breakdown voltage turnover
behavior. The measured CW I-V and pulse I-V, including breakdown current, of this
device is shown in Fig. 3.5. The gate bias was varied from 0.6 V to 1.8 V and the drain
bias was varied from 0 V to 3.8 V, both with 0.2 V step.
For the CW I-V measurement, the drain bias was measured up to Vds = 2.8 V for
the measurement o f the saturation current components. The solid line represents the CW
I-V curves and the open square shows the pulsed I-V curves with breakdown current
trends. Due to the high thermal conductivity of the silicon substrate, the low voltage
operation and the medium sample device size, the saturation components of the pulsed IV agreed well with those o f static I-V curves. The closed squares in Fig. 3.5. also show
the starting points o f the breakdown current. The drain bias corresponding to the closed
squares First decreases and then increases as Vgs increases.
To develop an accurate breakdown model, we have separated the measured pulse
I-V into its saturation current and breakdown current components, which are shown in
Fig. 3.6. The breakdown components are extracted from a comparison between the pulse
I-V and the saturation components extrapolated beyond each o f the breakdown voltages.
The open circles and triangles represent the saturation current components and the closed
symbols denote the breakdown current components at two different gate voltages.
50
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80
—
--—
*—
*—
70
60
<
E
50
•
*<>
saturation comp, at Vgs=1.2 V
saturation comp, at Vgs=0.7 V
breakdown comp, at Vgs=1.2 V
breakdown comp, at Vgs=0.7 V -
2
30
20
10
0
0
Fig. 3.6.
0.5
1
1.5
2
2.5
Vds (V)
3
3.5
4
The extracted saturation and breakdown current components of the
measured Pulse I-V curves at two different Vgs.
Because this separation method prevents coupling of the parameters of the two
current components during model extraction, this approach makes it easier to extract the
total nonlinear channel current parameters. From Fig. 3.5, the drain bias point
corresponding to the starting point of the breakdown current is designated as VBon- This
Figure shows the breakdown voltage has a turnover trend as the gate voltage increases.
The dependence on the gate bias can be modeled as an empirical modeling approach.
51
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
I
♦
♦
Measured VBon
Modeled VBon
3.5
♦
o
>
. ..
...........................
m
♦
♦
2.5
I
0.5
Fig. 3.7.
Vgs (V)
1.5
The measured and modeled breakdown current turn-on voltage (VBon)
turnover trend with Vgs bias voltage.
The measured and modeled VBon are shown in Fig. 3.7 and the trend of this
voltage has a negative slope at low gate voltages but a positive slope at high gate
voltages. This breakdown voltage turnover was modeled using (3.5). All Fitting
parameters in (3.6) and (3.7) can be extracted using the measured pulse I-V curves after
extracting the parameters o f (3.5).
52
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The parameters of the saturation current component are summ arized in Table 3.2.
These parameters consist of the saturation current component for total channel current
model.
VTO
7
VST
t
ucnt
GMEXP
VOEXP
k
a
SATEXP
0.81
-0.066
0.07
0.1233
0.02
0.0011
1.1
0.0054
5.6075
0.055
Table 3.2.
Summary of the parameters o f saturation current com ponent o f the total
channel current.
Table 3.3 shows the parameters of the breakdown current com ponent in the total
nonlinear channel current.
\\
F Bnun.
u
‘^0
5.85
0.4
3E-5
0.8
Table 3.3.
0.025
4
4
4
0.94
0.75
0.15
13.2
4
4
1.4
1.7E-3
0.62
•49
^10
li
0.67
1.31
0.85
Summary of the parameters o f breakdown current com ponent o f the total
channel current.
53
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3.3.3 Nonlinear Substrate Coupling M odel Extraction
The bias dependent S-parameters o f deep sub-micron M OSFET’s were measured
using a HP8510C network analyzer with a bias source and a monitor. During parameter
extraction, parasitic resistances are assumed to be independent of the bias source. Using
the bias dependent S-parameters, including the zero bias measurement, the drain-tosubstrate capacitance is extracted at each bias point using the parasitic extraction method
presented in [38] and optimized for wide band tuning to fit measured S-parameters to the
equivalent circuit model from 0.1 GHz to 10 GHz. To describe the decrease of the output
resistance at RF and microwave frequencies, drain-to-substrate resistance and drain-tosubstrate coupling capacitance are incorporated in the equivalent circuit model.
B, S
II
Y
t
t
t
i T f ir n f o j j *
’ £ i ■ t r j i C * t f i C f m » Y » f ? »'*£■*?'iii'rm m ) f »T V : T i 1
■ * # V r rf * t f r r ' * f F r f fV » r * »
'U i\f
T V r »Y \ t f r V r T T i ' f ' fj'T V i'* 'T t
Fig. 3.8. Deep Sub-micron MOSFET layout
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 3.8 shows the deep sub-micron MOSFET layout which consists of gate, drain
and source connected ton the body terminal.
300
250
tr 200
TO
"O
O
150
100
50
measured Cdd
measured Cdd
measured Cdd
measured Cdd
measured Cdd
measured Cdd
modeled Cdd
0.5
at Vgs=0.8 V
at Vgs=1.0 V
at Vgs=1.2 V
at Vgs=1.4 V
at Vgs=1.6 V
at Vgs=1.8 V
1.5
2
Vds (V)
2.5
3.5
Fig. 3.9. Extracted and modeled nonlinear drain-to-substrate coupling
capacitance Cdd-
After getting small signal equivalent circuit parameters at a certain bias point, the
bias dependent parameters can be obtained by fitting procedures with multi-bias Sparameter using the values of the bias independent parameters. The starting value of the
equivalent circuit are determined by DC measurement and analytical expressions.
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
150
100
at
50
Vgs increases
0.5
0
1
1.5
2
Vds (V)
(a )
2.5
3
3.5
600
500
u.
%-
400
&
Ul 300
O
200
Vgs increases
100
0
0.5
1
1.5
2
Vds (V)
2.5
3
(b)
56
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.5
300
250
200
u<«-.
(0 150
■o
O
100
Vgs increases-
0.5
1.5
2
Vds (v)
(C)
2.5
3.5
Fig. 3.10. Extracted and modeled (a) Cdg, (b) Cgs, and (c)
The extracted drain-to-substrate coupling capacitance has bias dependence. The
plot o f the extracted and modeled coupling capacitance is shown in Fig. 3.9.
Using equation (3.10), this nonlinear trend has been modeled by a drain-tosubstrate nonlinear coupling capacitance as a function of drain bias. The modeled Cdd is
combined with substrate lossy resistance to build an output nonlinear coupling network as
shown in Fig. 3.1. The other nonlinear capacitances are modeled using equations (3.11),
(3.12) and (3.13). Fig. 3.10(a)-(c) show the extracted and modeled nonlinear capacitances
(—
du' Cgs and Cgs
57
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 3.11 shows the drain to source nonlinear resistance Rds in the small-signal
MOSFET modeling at each bias point. The total channel current Ids (Wat and IdsB) in the
large signal model in Fig. 3.1 can be equivalently modeled as a voltage dependent current
source (gmVgs) and drain-to-source nonlinear resistance RdS at small-signal conditions.
Therefore, the nonlinear behavior o f Rds is implicitly incorporated in the total channel
current Ids implemented using the symbolic defined model (SDD) in nonlinear simulators.
200
Vgs increases
150
?
—
(A
■o
K
100
50
0
0.5
1
1.5
2
2.5
Vd (V)
Fig. 3 .1 1 . Extracted nonlinear drain to source resistance Rds-
58
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3
3.4. Nonlinear Model Verification
The robustness o f the improved deep sub-micron M OSFET nonlinear model was
tested at various termination conditions, biases, and frequencies.
100
80
<
E
60
10
■o
40
20
0
0.5
1
1.5
2
2.5
3
3.5
4
Vds (V)
Fig. 3 .12. Measured (circle) and modeled (solid) pulse I-V including breakdown current
(Vgs: 0 .6 - 1.8 V, Step : 0.2 V). Mark denotes the breakdown current turn-on voltag
(VBon).
Fig. 3 .12 shows the modeled and measured pulse I-V curves including the
breakdown region. The open circle shows the measured pulse I-V and the solid line
represents the modeled curves. The closed squares denote the breakdown voltage
59
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
turnover trend in the pulse I -V. The breakdown voltage turnover trend is also well
described as the gate bias increases. This model shows good correlation with the
measured pulse I-V. even in the breakdown region. Small-signal operation o f the
developed nonlinear model is verified with the bias dependent S-parameters. The
measured and modeled S-param eters o f 10 (finger) x 25-|i.m n-M OSFET is shown in Fig.
3.13(a)-(b). All S-parameters are shown in the same figure for each bias point. S 11 and S 22
are plotted on the lower half o f the smith chart and S 21 and S 12 are plotted on the upper
half o f the polar plot.
-1
0
(a)
60
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1
(b)
Fig. 3.13. Comparison o f measured (cross) and modeled (solid line) S-parameters (a) at
Vgs = 0.8 V and VJs = 1 V and (b) at Vgs = 1 V and
= 2.5 V. f = 0.1 GHz ~ 10 GHz.
Load pull measurements, including IMD, using an ATN LP2 load-pull system are
performed. The measured and simulated fundamental power and harmonics are shown in
Fig. 3.14. The proposed nonlinear model incorporating a new breakdown model and
substrate coupling shows good agreement with the measured data. As a comparison, the
model without substrate coupling and the breakdown model has been simulated and
compared with the measured data. This comparison shows a maximum of 1.5 dB
61
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
difference in the fundamental output power, a 5 dB difference in the second harmonics
and a 15 dB difference in the third harmonics at 4.4-GHz. As the result have shown, the
breakdown current model and substrate coupling are critical for accurate prediction of
power characteristics o f deep sub-micron MOSFETs.
60
40
♦
m e a su re d P1
sim ulated P1 w/ le a c k a g e a n d BD m odel
------ sim ulated P1 w/o le a c k a g e a n d BO m odel
a
m e a su re d P2
sim ulated P2 w I le a c k a g e a n d BD m odel
■£-— sim ulated P2 w/o le a c k a g e a n d BD m odel
▼
m e asu red P3
sim ulated P3 w/ le a c k a g e a n d BD m odel
•v— sim ulated P 3 w/o le a c k a g e a n d BD m odel
-60
-15
-10
-5
Pin (dBm)
Fig. 3.14. Comparison of measured fundamental output power (P I), second (P2) and third
harmonics (P3) and simulated data with proposed breakdown and substrate coupling
model and without these models at Vgs = 1.3 V and
= 3 V, freq. = 4.4 GHz. input
termination 0.64Z800 and output termination 0.26Z1330.
62
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Load pull measurements including EMD are performed, using an ATN LP2 load-pull
system. Fig. 3.15(a)-(fc>) illustrate the com parison o f the power characteristics at 3.4-GHz
and 4.4 GHz respectively. These figures show that the measured and m odeled output
power, power added efficiency and power gain at the two different operating frequencies
and termination conditions are tuned for maximum output power with the conjugate input
termination.
60
50
15
A •
40
C
’<5
u
O
3°
? 10
CL
20
measured Pout
modeled Pout
measured Gain
modeled Gain
measured PAE
modeled PAE
5
10
0
-20
m
9
00
3
o
>
-15
-10
-5
0
5
Pin (dBm)
(a)
63
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
20
• M
CD 15
•o
■o
(0
O
?
ffi
3
O
Q.
>
10
m
■
5
•
a
0
-20
-15
measured Pout
modeled Pout measured Gain.
modeled Gain
measured PAE modeled PAE
0
-10
0
Pin (dBm)
(b)
Fig. 3.15. Pout, Gain, and PAE measured and simulated (a) at Vgs = 0.9 V and
= 2 V,
freq. = 3.4 GHz. input termination 0.64Z 55.50 and output termination 0.31 Z 9 6 0 and (h)
at VgS= 1 .3 V and Vds= 2 V, freq. = 4.4 GHz, input termination 0.66Z 75.9 0
and output term ination 0.28Z1320.
The 3.4-GHz measured and modeled Pout. Gain, and PAE at
= 0.9 V and Vds = 2 V is
shown in Fig. 3.15(a). The termination condition of this comparison is 0.64Z 55.50 at the
input and 0 .3 1Z96° at the output.
64
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 3.15(b) shows that the 4.4-GHz measured and modeled data at Vgs=1.3V and
Vds=2V. The termination condition is 0.66Z 75.90 at the input and 0.28Z 1320 at the
output. The model predicts the power output, gain, and efficiency from small-signal
operation to well past power compression. These comparisons show that the developed
model correlates well with the measured power characteristics at different termination
conditions, bias points and frequencies.
E
ffl
■o
*
-20
2
-40
3
O
Q_
modeled Pout
measured Pout
modeled IM3
measured IM3
modeled IM5
measured IM5
-60
-80
-20
-1 5
-10
-5
0
5
Pin (dBm)
(a)
65
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
20
_
0
E
ffl
▲A
■o
o -20
«
I
-40
3
O
Q.
0
-60
A
-80
-20
▼
modeled Pout
measured Pout
modeled IM3
measured IM3
modeled IM5
measured IM5
_ J __________
-15
-10
-5
Pin (dBm)
0
.
10
(b)
Fig. 3.16. Fundamental output power (Pout), IM3 and IM5 measured and simulated by
the proposed model (a) using 3.4 GHz and 3.401 GHz and (b) using 4.4 G H z and 4.401
GHz. Vgs = 0.9 V and Vds= 3 V. 50 £2 input and output termination, input power sweep
from -15 dBm to 5 dBm.
To verify the model prediction capability of the harmonics and intermodulation
distortions, we measured these two parameters using the ATN LP2 system. Fig. 3.16(a)(b) show the third-order and fifth-order intermodulation distortion measurements at 3.4GHz and 4.4-GHz with an input power sweep from -15-dBm to 5-dBm into 50-Q
66
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termination and a bias condition o f Vgs = 0.9 V and
= 3 V. The offset frequency for
the two-tone signals was 1-MHz. The developed model predicts accurately, the thirdorder and fifth-order intermodulation distortions at both frequencies
Fig. 3.17(a)-(b) show the m easured and modeled intermodulation distortions at
3.4-GHz and 4.4-GHz with different gate biases and a 0-dBm input pow er level. The
fundamental output power, third and fifth-order intermodulation distortions are measured
at 50-Q termination and 2.5 V drain bias.
20
10
E
0
ffl
T3
in
-10
eo
-20
3
O
-30
-40
modeled Pout measured P out.
modeled IM3
measured IM3 modeled IM5
measured IM5
-50
-60
0.5
*
Vgs (dBm)
1 5
(a)
67
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E
CQ
TJ
-10
-30
"7
A
A_
A
hl
3
O
-40
modeled Pout measured P out.
modeled IM3
measured IM3 modeled IM5
measured IM5
-50
-60
0.5
1
Vgs (dBm)
1.5
2
(b)
Fig. 3.17. Fundamental output power (Pout), IM3 and IM5 measured and simulated by
the proposed model (a) using 3.4 GHz and 3.401 GHz and (b) using 4.4 GHz and 4.401
GHz. Vgs sweep from 0.6 V to 2.0 V and Vds= 2 V, 50 Q input and output termination, 0
dBm input power condition.
The fundamental output power and third-order intermodulation distortion
correlate well with the measured data and the modeled fifth-order intermodulation
distortion corresponds reasonably with the measured data between Vgs = 0.6 V and Vgs =
68
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2 V. Fig 3.18(a)-(b) show the measured and modeled harmonics at 3.4-GHz and 4.4-GHz
with different gate biases and O-dBm input power level. The fundamental output power,
second and third harmonics are measured at 50-£2 termination condition and 2.5 V drain
bias voltage. The fundamental and second harmonics correlate well with the measured
data and the modeled third harmonics correspond reasonably with the measured data
between Vgs = 0.6 V and
= 2 V.
20
r>
r>
o
n
n
■
->
10
E
m
o
tj
n
▲
CLWk
M
Q.
-10
▼
A
A
* -
modeled P1
measured P1
modeled P2
measured P2
modeled P3
measured P3
-A
♦
-20
▼
.
T
i . ,
-30
0.5
1
|.
....
Vgs (V)
1*5
(a)
69
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
X
20
10
E
CD
~
■o
i
CO
0.
Mr -1 0
Q.
a
modeled P1
measured P1
modeled P2
measured P2
modeled P3
measured P3
-20
\
A\
-30
a
A
-40
0.5
1.5
Vgs (V)
(b)
Fig. 3.18. Fundamental output power (P I), second (P2) and third harmonics (P3)
measured and simulated by the proposed model (a) at 3.4 GHz and (b) at 4.4 GHz,
Vgs sweep from 0.6 V to 2.0 V and Vds = 2.5 V, 50 Q input and output termination.
0 dBm input power condition.
The modeled IMD results using I-M Hz offset and the modeled harmonics from
the developed nonlinear model also show good agreement with the measured data at
different termination conditions, bias points and frequencies.
70
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3.5. Conclusion
An improved deep sub-micron M OSFET RF nonlinear model, incorporating a
new breakdown current model and drain-to-substrate nonlinear coupling, has been
developed and investigated extensively using various measurements. For the first time,
the breakdown voltage turnover behavior has been incorporated in a continuously
differentiable channel current model to predict nonlinear operation accurately around the
soft breakdown region. Based on the philosophy of the separation o f saturation and
breakdown components of the nonlinear channel current, we decoupled the model
parameters of the two components to enable easy parameter extraction. Frequency
dependence o f the output admittance is accurately modeled by including a new drain-tosubstrate nonlinear coupling network. The robustness of the new nonlinear deep sub­
micron
MOSFET
model
has
been
comprehensively
verified
through
load-pull
measurements, including 1MD and harmonics at various termination conditions, biases,
and frequencies.
71
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CHAPTER IV
A 1.9-GHz DECT MOSFET POWER AMPLIFIER WITH
FULLY INTEGRATED MULTI-LAYER LTCC PASSIVES
4.1 Introduction
Reduction in size and full integration are key trends in current commercial RF
component production. Recently, two-chip or three-chip solutions for 1.9-GHz DECT
applications have been presented based on various technologies [39-41]. These chips
need to be integrated with off-chip Filters and discrete passive elements, such as chip
inductors and capacitors, to build a complete transceiver module. A single-chip solution
for a partial functional block is developed for DECT applications based on a commercial
BiCMOS technology [42]. However, it still requires integration with a power amplifier, a
low noise amplifier, a duplexer and various filters.
A major bottleneck hindering full integration onto a single chip is the fact that the
on-chip passives, such as inductors, capacitors and filter structures, require high-Q values.
72
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Multi-layer LTCC is one of the compact and cost-effective solutions to this problem. Fig.
4.1 shows a module of DECT applications. This figure shows the DECT module block
diagram, which consists of the IF digital part, the IF/RF interface, the RF front end.
numerous off-chip filters and a duplexer.To develop an integrated DECT transceiver
module, the LTCC technology may be a good candidate due to its high-Q multi-layer
passives. Using this technology, it’s efficient to build compact RF components, filters and
duplexers. We focused on the power am plifier using LTCC integral passives.
U2761B R F /F
Frortend
PLL/TX
Fig. 4 .1 A 1.9-GHz DECT module block diagram.
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It is attractive to implement a RF transceiver module based on a standard silicon
technology in conjunction with LTCC passives in order to replace low-Q passives on
silicon [43] with multi-layer high-Q passives such as inductors [13], filters [44] and
duplexers [45]. These facts demonstrate how the LTCC is a good candidate for systemon-package (SOP) solutions [46].
In this research, we show the first reported M OSFET PA with fully integrated
multi-layer LTCC passives, which is particularly suitable for modem communication
systems using constant envelope modulation schemes. W e developed the LTCC inductor
and capacitor library that allows high-Q passives and a higher level o f integration in
addition to lowering the cost incurred by the discrete off-chip components.
The passive library has been implemented in the LTCC technology. The inductor
components in the library were implemented using multi-level ground plane architecture
to allow a more compact implementation. The capacitors used for matching and RF
ground utilize the novel vertically interdigitated configuration (VIC) and the conventional
Metal-Insulator-Metal (MIM) topology. Multi-layer ceramic-based integrated passives
have been demonstrated as a feasible option [13-14] to realize high-Q passives. There are
two obvious advantages to incorporating integral passives into microwave integrated
circuit development. First, it eliminates the needs for discrete components, which
consequently reduces the cost. In addition, it also reduces the assembly time as well as the
turn around time. The inductor components in the library are implemented in the so-
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called multi-level ground plane architecture that allow for a compact realization. The
LTCC passives were simulated using an EM sim ulator such as SONNET [47]. In order to
design the high performance power am plifier, a custom non-linear M OSFET model [48]
has also been developed and incorporated.
For the active device nonlinear model, a new temperature dependent large-signal
model with self-heating and ambient tem perature effects for sub-micron (0.8-(im) power
M OSFETs was developed from on-wafer pulse-IV measurements at different ambient
temperatures. The simulation data from the new model with self-heating effects
demonstrates a good agreement with m easured S-parameters and power characteristics
including gain, efficiency, harmonic com ponents and intermodulation powers in class AB
operation. This modeling approach was used to develop a new CM OS-LTCC 1.9-GHz
high efficiency power amplifier. This is the first significant step toward a compact 1.9GHz DECT transceiver module using conventional MOSFETs and multi-layer LTCC
technology. Simulation and measured results of the power amplifier module have been
summarized.
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4.2 Digital Enhanced Cordless Telecommunications
4.2.1 D E C T standard
The DECT standard was initially conceived in the mid-1980s as a pan-European
standard for domestic cordless phones. The objective of the new standard proposed by
CEPT (the Council of European PTTs) was to use digital radio technology to improve the
performance o f cordless phones in three important areas - speech quality, security against
eavesdropping, and immunity from radio interference between nearby cordless phones.
By the time the DECT standard was finalized in 1992 and published by ETSI
(European Telecommunications Standards Institute, the successor to CEPT). the scope of
the standard had broadened beyond domestic cordless phones to include two additional
application areas. The first was the business cordless telephone (the so-called cordless
PBX or wireless PBX) and the second was a cordless access system for subscribers to
public telecom networks.
Since 1993. DECT has been a mandatory standard throughout the European
Union. M ember countries have set aside radio frequencies in the 1.88-1.9 GHz for DECT
systems. The DECT standard has also been adopted for use in countries outside the EU.
The latest information shows that DECT is regarded as a standard in 26 countries, making
it the most widely-used digital standard for cordless communications. For this reason, the
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name of the DECT standard has been revised. In the original form, the letter 'E' stood for
European’. Now, it denotes ’Enhanced’. So today, the acronym DECT m eans Digital
Enhanced Cordless Telecommunications.
DECT is a digital radio access standard for single- and multiple-cell cordless
communications. It is based on a multi-carrier TDMA (time division m ultiple access)
technology. This is the same technology used in main digital cellular standards, but the
central difference is that cellular systems were developed for wide-area coverage, whereas
the DECT standard was optimized for local coverage, with a high density o f users. The
standard specifies four layers of connectivity, plus other important functions. The four
layers correspond approximately to layers 1-3 o f the ISO Open Systems Interconnection
(OSI) model, as follows:
1. Physical layer: Radio parameters such as frequency, timing and pow er values,
bit and slot synchronization, and transm itter and receiver performance.
2. Medium Access Control layer: The establishment and release of connections
between portable and fixed parts o f the DECT system.
3. Data Link Control layer: Provides very reliable data links to the Network
layer, for signaling, speech transmission, and circuit- and packet-switched data
transmission.
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4. Network layer: The main signaling layer, specifying message exchanges
required for the establishment, maintenance and release of calls between
portable and fixed elements o f the network.
Other elements o f the DECT standard cover equipm ent identities and addressing, security
authentication procedures, speech coding and transmission. Public Access Profile and
cryptographic algorithms.
4.2.2 Applications f o r the DECT standard
The three applications for the DECT standard that have reached widespread
commercial deployment so far are for home cordless phones, business cordless systems,
and as a radio alternative to wired subscriber accesses in public fixed telecom networks,
known as W ireless Local Loop (WLL). In a DECT home cordless phone, a typical DECT
system consists o f a phone handset and a base unit that contains the radio base station.
In a DECT business cordless system, the core radio network is a num ber of radio
base stations, all connected to a PBX through a radio exchange. A DECT business
cordless system has an architecture that is sim ilar in concept to a cellular mobile phone
system, with a network o f radio base stations so that users can walk around the premises
while making and receiving calls. The cell structure in a DECT business cordless system
are much smaller (pico-cells) than those used in a cellular network, which allow much
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higher user densities. DECT permits the highest user densities of any cordless system, up
to 100.000 per square kilometer.
In a DECT WLL system, the radio base station is located somewhere in the
neighborhood, and each subscriber is equipped with a DECT transceiver unit into which a
standard telephone can be plugged. Group 3 fax machines and data modems can also be
used. A further development of this public network access concept is to equip subscribers
with DECT digital cordless phones, to provide a limited degree of mobility in a local
area. This solution is termed Cordless Terminal Mobility (CTM).
4.2.3 Strengths o f DECT standard
The DECT strengths have been summarized as follows:
1. High capacity: The digital TDM A radio technology used in the DECT standard.
with its low radio interference characteristics, allows business cordless
systems to handle up to 100,(XX) users per square kilometer. This allows even
the most densely-occupied office buildings and similar locations to be served.
2. High speech quality: Speech is digitally encoded before transmission, using 32
kbit/s ADPCM (Adaptive Differential Pulse Code Modulation) speech
encoding. The resulting speech quality is as good as with an ordinary wired
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phone. High security: The DECT standard uses encryption techniques so that
radio eavesdropping is virtually impossible.
3. Long battery life: The radio technology uses discontinuous transmission,
occupying only two out of the 16 timeslots, which reduces the load on the
battery in the cordless phone. Standby and talk times of 45 hours and nine
hours are commonly available in the latest DECT cordless phones.
4. Seamless handover of calls: In a DECT business cordless system, as the user
moves around from one pico-cell to another during a call, it is the phone rather
than the radio network that initiates handover from cell to cell. A ’makebefore-break’ handover principle ensures that the handover is undetectable to
the user.
5.
Data as well
as voice:
The
DECT standard permits
cordless data
communications as well as voice, creating the possibility of cordless LANs
(Local Area Networks) which could share capacity with cordless telephone
systems.
One of the most important profiles is the GAP (Generic Access Profile), which ensures
that all DECT products from different manufacturers will be compatible.
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4.3 Low Temperature Co-ffred Ceramic Technology
Passive components occupy a significant part of the total area in Monolithic
Microwave Integrated Circuits (MMIC). It is desirable to reduce the area and achieve
better performance by implementing passive elements. The LTCC process we used
utilizes screen-printing technology and low-loss stacked via processes as well as high
conductivity metalization for high frequency applications. The substrate material for the
20-layer LTCC is 951-AT ceramic and each layer is 3.6 mils thick. Fig. 4.2 shows the
flow chart o f LTCC fabrication.
Unreel Tape
f
Drill via holes
w
Repeat via drilling
and metal printing
on each layer
...
4
Press stacked tape
Fire stacked tape at 875PC
Print metalization
Fig. 4.2. LTCC process flow chart
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.3.1 LTCC Inductors
The inductor is one o f the key components that determ ine the performance of
RF/microwave circuits. Therefore, the design and use of com pact and high-Q inductors
with the desired inductance is important to ensure good circuit operation.
Lumped element inductor and capacitor components have been developed in a
multi-layer LTCC technology. The inductors are built based on the multi-level ground
plane concept as shown in Fig. 4.3. In a multi-level ground plane architecture, all the
footprints of the components are on the surface layer while the ground plane of each
component may be on different levels.
Moving the ground plane closer to the inductor footprint increases Cs, thereby
canceling part of the inductance. On the other hand, moving the ground plane farther from
the structure reduces Cs and increases L^ff. In the example shown in Fig. 4.3. the inductor
structure L in Fig. 4.3(a) has a closer gap to the ground plane than that in Fig. 4.3(b) (hi <
hi). Therefore, CS| is larger than Q i implying Lem is smaller than Leffi. Close proximity
of the ground plane to the inductor footprint reduces the effective inductance due to the
negative mutual coupling caused by the current flowing in the ground plane in the
opposite direction to the inductor current flow [49].
The three Figure of merits used to evaluate the inductor performance are the
quality (Q) factor, the effective inductance (L^ff) and the Self Resonant Frequency (SRF).
The effective inductance Lcff is the total inductance seen at the input port of the inductor
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and is obtained by taking the ratio of the imaginary part of the input impedance to the
angular frequency
The angular frequency _ is given by 2 _ f where f is the frequency.
The quality factor of passives in RF matching circuit and DC choke affects the total
efficiency due to the degradation of the output voltage swing.
The reduction in Lcff consequently reduces Q and Self Resonance Frequency (SRF).
However, we show experimentally that even though such phenomena took place, a
sufficiently high Q and SRF can still be achieved.
*-2
C slZ Z
h,
Ground plane
Ground plane
(a)
(b)
Fig. 4.3. The structure o f multi-level ground plane inductors
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The second advantage of keeping the inductor footprint on the surface layer is to
minimize the dielectric loss by maintaining a portion o f the field of the inductor
propagating in the air. M easured
and Q of multi-level ground plane inductors are
shown in Figs. 4.4 and 4.5.
This topology has two advantages. First, by moving the location of the ground
plane on different layers, different inductances can be realized without occupying larger
lateral real estate. The effective inductance of the structure can be varied by increasing or
reducing the shunt parasitic capacitance to ground.
3
9
a
z
■
8
X
c
6
Full Turn (W=10 mils)
Full Turn (W=20 mils)
Three Quarter Turn fW=10 mils
Three Quarter Turn (W=20 mils!
Halt Turn (W=10 mils)
Half Turn (W=20 mils)
-
10
15
h (Layers)
Fig. 4.4. The effective inductance of multi-level ground plane inductors
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160
5.4 nH
4.0 nH
3.8 nH
2.5 nH
1.4 nH
1.2 nH
140
120
2
Csl
Cs2
100
Ground
0
1
2
3
4
5
7
6
Frequency (GHz)
Fig. 4.5. The measured Q of multi-level ground plane inductors
4.3.2. LTCC Capacitors
The capacitors for matching purposes and RF ground utilize the conventional
Metal-Insulator-Metal
(MIM)
topology
and
the
novel
vertical
configuration (VIC) in Fig. 4.6.
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interdigitation
(a)Parallel Plate Capacitor
(b)Vertically Interdigitated Capacitor
Fig. 4.6. The structure o f capacitor topology
An alternative capacitor implementation to the conventional parallel plate MEM
[50] was proposed using the vertically interdigitated configuration (VIC). Fig. 4.6(b)
illustrates the concept o f VIC as compared to the conventional MIM structure shown in
Fig. 4.6(a). The VIC deploys these smaller plates with width w' vertically as depicted in
Fig. 4.6(b). The plate size can be made smaller as more plates are deployed on more
dielectric layers. The electric flux not only flows vertically between the pair o f the
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capacitor electrodes, but also laterally between via interconnect to the electrode. Such
mechanism allows further shrinkage of the VIC plates. The VIC is a suitable architecture
to realize compact capacitor. For testing, a 1.4-pF capacitor was fabricated in both VIC
and MIM configurations by incorporating the fringing fields. The plate size for the MIM
capacitors is 45 mil x 45 mil. The 1.4-pF VIC was fabricated using multi-layer plate
including the ground plane on five tape layers similar to those illustrated in Fig. 4.6(b).
One-port capacitor can be realized by connecting the bottom electrode of the MIM
structure to the ground or by using the ground as the bottom electrode. For the VIC, the
electrodes connected to one o f the ports in Fig. 4.6(b) were simply shorted to ground to
realize a one-port device. The capacitor Q was obtained by taking the ratio of the negative
of the imaginary to the real part of the input impedance o f one-port capacitor test
structures obtained from de-embedded S-parameter.
Fig. 4.7 show's the measured effective capacitance Ceff and Q as a function of
frequency superimposed with the simulation results using a commercial method of EM
simulator [47], The VIC capacitor shows comparable Q and SRF to their MIM
counterpart as predicted from the simulated results. M ultiple vias connecting the VIC
plates contribute to the slightly less SRF and Q. There are more inductive and resistive
parasitic components through multiple via connections to implement the VIC capacitor
plates. The comparison between MIM and VIC topology are summarized in Table 4.1.
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100
10
I
Measured MIM
-z — Measured VIC
80
8
Simulated Results
60
O
T3
~n
40
3
4
5
Frequency, GHz
Fig. 4.7. Measured and simulated results o f MIM and VIC capacitors.
Type
Plate size
(mil x mil)
VIC
18
324
5
5.5
1.4
MIM
45
2,025
2
6.8
1.4
VIC
47
2,209
5
2.4
MIM
101
10,201
2
3.1
6.2
6.2
Lateral Capacitor # of plates
Area (mil2>
SRF (GHz) Ceff> Pp
Table 4.1. Comparison between MIM capacitors and VIC capacitors.
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4.4 A New Temperature Dependent Power MOSFET RF
Nonlinear Model
To design this pow er amplifier, a new em pirical large signal model for power
MOSFETs. which has self-heating and am bient temperature effects, and continuity of
channel current equation in high order derivatives, has been developed. The modeled
channel current is based on on-wafer pulse IV (current-voltage) measurements at different
ambient temperatures. A table-based channel current model with pulsed IV has been
presented to model thermal effects of a power M O SFET [51]. However, the model only
accounts for self-heating, not ambient tem perature effects. A physically based BSIM3V3
[52] model has been linked to a commercial harm onic balance simulator [53], but this
SPICE model doesn’t include the self-heating effect and is complicated with more than
ninety parameters for the complete model. In addition to the effects of self-heating, a
continuously differentiable channel current model has been previously developed for a
LDMOS FET [54]. This model also has sim plicity and the capability to emulate
transconductance saturation.
In this work, a new channel current model based on [54] is introduced to
characterize the thermal phenomena of a pow er M OSFET, including self-heating. The
new temperature dependent large signal model with self-heating effects and continuity
reduces the number o f model parameters without compromising accuracy in DC and RE
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performance. The com plete large signal model is linked to a harmonic balance simulator.
To verify the accuracy and robustness of the model, the fundamental and its harmonics
and IM power measurements and simulations were performed. The measured and
modeled data are in good agreement for DC and RF operation. For the design o f the
power amplifier, this temperature dependent nonlinear model is linked to HP MDS.
which is one of the popular nonlinear circuit simulators using a user-defined model.
4.4.1. A New Temperature Dependent Nonlinear Current M odel
Common source N-MOSFET power devices were fabricated using National
Semiconductor’s 0.8-p.m ABIC5 BiCMOS process. The bulk has been connected to the
source to eliminate body bias effects. To extract a thermal model of channel current, onwafer drain pulse IV measurements were performed using a thermal chamber [55] at
different temperatures without self-heating (static EXT biasing: Vds = 0 V. Ids = 0 mA).
The pulse width is 600 ns and the duty cycle is 1%, which is much shorter than
the thermal time constant for MOSFET [56]. In the thermal chamber [55], the device
channel temperature can be assumed to be the same temperature as the chamber wafer
chuck at a thermal steady state. Based upon the channel current equation in [54], a
temperature dependent channel current model is proposed as follows:
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Vgst \ ty gs ,Vd s ) =
V
v g s - (VTO + y V d s )
(4.1)
<^gs • ^ds ) = VST In [exp( - M l ) + 1]
(4.2)
^ eff = ------------------(1 + p crn V s l GMEXP
U M tx^ )
(4 '3)
'dssat <vgs ■V'ds) = Peff < V >
ct V
0 + >■^ds > “‘" h < , SATEXP > <4'4)
''gst
^
(4.5)
^ th ^ciis +
(4.6)
P = Po + P T A 7 j
(4.7)
The temperature dependence of the channel current can be modeled using ft and y
which are expressed in equations (4.6) and (4.7) as first order functions of the increase in
channel temperature. Rth[°C/W] is the thermal resistance and P<jis is the DC power
consumption caused by IX! biasing voltage. A7] represents the increase in channel
temperature. 7^ is the ambient temperature at the operating condition while Ta* represents
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the ambient temperature at the time when the device is modeled. The nonlinear channel
current model can be improved to get generalized temperature dependence by adding
linear temperature dependent parameters: A, a, VTO, VBoa and extrinsic resistances.
However, a simple yet sufficiently accurate model for the operation temperature region of
interest can be achieved without including all these temperature dependent parameters.
4.4.2. DC and A C M odel Param eter Extraction
A static IV curve at 294°K and pulsed IV curves at three different ambient
temperatures are shown in Fig 4.8.
0.5
static IV at 294 K
pulsa IV jit 294 K
pulse IV:at 274 K
pulse IV at 254 K
■O -
0.4
0.3
<
to
■o
0.2
0.1
--«—
0
0.5
1
1.5
2
2.5
3
3.5
4
Vds (V)
Fig. 4.8. Pulsed IV curves at three ambient temperatures and a static IV curve at 294°K
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For each pulsed IV curve, the channel current parameters can be extracted using
equations (4.1-4.4). The thermal resistance of the sample can be easily extracted using
pulsed and static IV curves at the same ambient temperature (294°K) [48], Using
extracted parameters at each temperature and equations (4.5~4.7), Po,pT, yo and yT are
extracted. Table 4.2 shows all parameters.
po
0.2533
PT
-0.000265
yo
-0.02153
YT
0.000055
a
1.7104
k
9.2E-7
Rth[°C/W]
35
flcrit
0.0057
VTO
0.93
VST
0.1
VGEXP
1.3
GMEXP
0.2527
SATEXP
0.81
Table 4.2. Pulsed IV Channel Current and Temperature Parameters o f Power MOSFET.
93
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Using bias dependent S-parameters, linear elements and nonlinear capacitors are
extracted at one hundred bias points in the IV plane. For nonlinear capacitors, empirical
equations are used. The nonlinear channel current model with temperature effects and
nonlinear capacitor models are used to implement a large signal model in a harmonic
balance simulator. The drain pulse IV measurement and simulated data from the model
are shown in Fig. 4.9.
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
2.5
Vds (V)
3
3.5
4
Fig. 4.9. Measured and Simulated Dual Pulse IV curves with DC Offset
(Vds=3V,Vgs=2.1 V with Vgs:0.9V~2.5V, 0.4V step)
94
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The solid line is the simulated pulse IV with EXT offset bias and the triangular line
shows the measured pulse IV curves. This comparison shows the model can predict the
dynamic IV with DC bias self-heating accurately. The only thermal contribution in this
case are the self-heating effects due to the power dissipation of DC bias. This simulated
and measured I-V curves represent the dynamic I-V curves.
Fig. 4.10. M easured(circle) and Simulated (solid line) S-parameters
95
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Correlation between the measured small-signal S-parameters and simulation
results from the model are shown in Fig. 4.10 for frequencies between 1 and 8GHz.
20
15
30
- 25
■o
7 10
lo
Qy
15
10
m m u n d Gain j
m o d e led Gafn
m easu red PAE i
m odeled PAE I!
5
0
5
10
15
20
Pin (dBm)
Fig. 4.11. Measured and Simulated Power Gain and Power Added Efficiency at 1GHz.
Figs. 4.11 and 4.12 show that the developed model correlates very well with
measured power characteristics such as gain, efficiency and harmonics into a 50-ohm
matching condition in class AB operation. Fig. 4.11 shows that the model tracks the gain
and efficiency from small-signal operation to well past compression. Sim ulated and
measured fundamental and harmonic components are shown in Fig. 4.12.
96
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30
20
10
cr
o
Or
-30
maasurad P1 I
— modaiad P1
measured P 2 j
—- modaiadP2 ’ .
maasurad P3 — modalad P3 I
-40
50
5
0
5
10
15
20
Pin (dBm)
Fig. 4.12. Measured and Simulated Harmonic Power at 1GHz
97
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4.5 A New CMOS-LTCC 1.9 GHz High Efficiency Power Amplifier
4.5.1 High Efficiency Power Am plifier using LTCC integral passives
This work describes, for the first time, a power amplifier for the 1.9-GHz Digital
European Cordless Telephone (DECT) frequency band composed of a LTCC passives.
The Gaussian Frequency Shift Keying (GFSK) modulation format used in DECT is a
constant envelope signal enabling the use of non-linear amplification. The power output
at the antenna is constant and limited to 24 dBm. The classical approach utilizing class
AB and class B amplification can be used.
4.5.2 LTCC Passive Equivalent Circuit Modeling
The S-parameters of the LTCC passives were simulated using an EM simulator.
Based on these result, equivalent circuit models of passive inductors and capacitors were
obtained.
1 nH
0 j65 OIim
VA—
0.19pF
24K O hm |
Fig. 4.13. The equivalent circuit model of one port 1 nH inductor
98
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-1
Fig. 4.14. Simulated (+) and modeled (solid line) S-parameters o f one port 1 nH inductor
The 1-nH one-port inductor has been shown as an equivalent circuit with passive
elements in Fig. 4.13. The S-parameters were simulated from 1 to 2.5 GHz using an EM
simulator such as SONNET [47]. An equivalent circuit model o f the inductor was
extracted to fit the measured S-parameters over this range and the resulting comparison is
shown in Fig. 4.14.
1.9 p F
OJ04 O h m
o
Fig. 4.15. The equivalent circuit model of one port 1.9 pF capacitor
99
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1
Fig. 4.16. Simulated (+) and modeled (solid line) S-parameters o f 1.9 pF capacitor
The 1.9-pF one-port capacitor has been shown as an equivalent circuit with
passive elements in Fig. 4.15. An equivalent circuit model of capacitor was extracted by
fitting the measured S-parameters over this range. The comparison between the simulated
and modeled data is shown in Fig. 4.16.
4.5.3 High Efficiency Power A m plifier Design and Performance
The power amplifier was built using a combination of the twenty-layer LTCC
passive library and 0.8-pm power n-M OSFETs [48]. The LTCC inductor library was built
based on the multi-level ground plane concept that allows for a tremendous real-estate
100
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savings by maintaining the lateral size o f the inductor footprint while varying the values
of inductance.
The capacitor library was built using a new compact topology and the
conventional metal-insulator-metal (MIM) configuration. In the vertically interdigitated
capacitor (VIC) topology, the structure implements a capacitor by stacking and
intertwining electrodes in a multi-level dielectric system. Such a configuration is suitable
for realizing a big capacitor, such as the RF ground capacitor, in high frequency circuits.
Stacking and intertwining multiple electrodes is equivalent to establishing parallel
capacitor interconnects whose total capacitance is the sum of the individual capacitances
formed by a pair of electrodes. The VIC has demonstrated the reduction in the area by
almost an order o f magnitude as compared to the MIM counterpart for the same effective
capacitance with similar performance in terms o f Q-factor and SRF.
In addition to the passive library, a custom RF/microwave non-linear MOSFET
model for large signal applications has also been developed for the power amplifier
design and demonstrates compatibility with standard commercial wireless CAD tools. In
this model, a new temperature dependent channel current model is introduced to
characterize thermal phenomena of a power MOSFET including self-heating. The
temperature dependent large-signal model with self-heating effects and continuity reduces
the number of model parameters without compromising accuracy in DC and RF
101
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performance. The complete large-signal model was implemented in a harmonic balance
simulator and used for the power amplifier simulation.
A two-stage DECT power amplifier with second-harmonic tuning circuits using
silicon n-MOSFET active devices has been built utilizing passive components from the
LTCC library. Fig. 4.17 shows the circuit diagram of the LTCC power amplifier.
The inter-stage matching consists o f two inductors and capacitors to minimize the
return loss in the inter-stage. The second harmonic short circuits are implemented with
L3. C l, L6, C3, L9, C8. LI 1, and C l l to achieve high power added efficiency. To
decrease the size of RF ground capacitors. Vertically Interdigitated Capacitors (VIC)
topology is used for C2, C4. C9, and CIO. The series connection of inductor L12 and
capacitor C12 are used for the output matching circuit. Fig. 4.18 shows the layout
diagram of the I.9-GHz two-stage power amplifier using conventional MEM capacitors
for RF ground.
Fig. 4.19 shows the photograph of the fabricated LTCC power amplifier
occupying 0.78-in x 0.38-in board area. The two n-MOSFET devices fabricated in a 0.8pm National BiCMOS technology [48] were wire-bonded onto gold pads on the LTCC
board. The device size of the first and second stage is 2.5 mm and 5 mm respectively.
Half and quarter turn inductors were used as matching components while a full-tum
inductor was used as an RF choke. Parallel plate MIM capacitors were utilized as
matching components since their values and sizes are relatively small.
102
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Fig. 4.17. The circuit diagram of the LTCC power amplifier.
103
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Fig. 4.18. LTCC layout o f 1.9-GHz DECT High Efficiency Power Amplifier
N-MOSFET 2.5 mm
MIM Capacitor
VIC Capacitor
^
N-MOSFET 5 mm
Second Harmonic Tuning Circuit
Fig. 4.19. The photograph o f the LTCC power amplifier.
104
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3D inductor
The RF ground capacitors were implemented in the novel VIC topology since they
require large capacitance and area. Second-harmonic tuning elements were implemented
by a series LC resonator at 3.8 GHz as part of the second-harmonic trap network to
improve the efficiency.
Fig. 4.20 shows the measured gain. PAE and output power at 1.9 GHz
demonstrating a good correlation to the simulated result performed using the LTCC
passive library and the custom-developed M OSFET model.
30
60
25
50
Gain
m 20
40
< —
15
30
PAE
Pout
<
5
20
.
10
0
AAA*
-5
-20
-15
A A A + 4 *
-10
0
-5
0
Pin (dBm)
5
10
15
Fig. 4.20. The measured (* ..♦ .•) and simulated (solid line) gain, PAE and output
power at 1.9 GHz
105
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The power amplifier exhibits 48 °/c o f PAE, 26 dBm o f output power and I7-dB
power gain at 1.9 GHz with a 3.3-V drain supply voltage as indicated in Fig. 4.20. The
measured small-signal performance o f the power amplifier, showing a good agreement
with the simulation result incorporating the passive library and the active device non­
linear model, is plotted in Fig. 4.21. The slight discrepancy between the measured and
simulated results is attributed to additional parasitic and loss mechanisms caused by the
discontinuous ground plane deployed on different tape layers.
30
20
m
•o
T-
CM
CO
CM
CM
CO
CO
-10
S11_meas
--- S11_sim
S21_meas
- S21_sim
S22_meas
— S22_sim
-20
-30
1
1.5
2
2.5
3
Frequency (GHz)
Fig. 4 .2 1 The measured small signal performance of the power amplifier
106
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Table 4.3 provides a detailed summary on the measured and simulated power
amplifier performance. This summary shows the M OSFET pow er amplifier with high-Q
LTCC passives is an attractive implementation for 1.9-GHz DECT transceiver modules.
Specification
Simulation Data
Measured Data
Freqency Range
1.88 GHz to 1.9 GHz
1.88 GHz to 1.9 GHz
Supply Voltage
3.3 V
3.3 V
Maximum Pout
27 dBm
26 dBm
Input VSWR
<1.5:1
<1.5:1
Gam Variation In Band
<0.5 dB
<0.8 dB
Power Added Efficiency
51 %
48%
Power Gam
18 dB
17 dB
Table 4.3. Performance summary of the M OSFET-LTCC power amplifier
107
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4.6 Conclusion
A 1.9-GHz MOSFET power amplifier module with fully integrated high-Q LTCC
passives has been demonstrated. This highly integrated module, suitable for DECT
applications, was built based on multi-layer LTCC passives and does not use any discrete
off-chip components. A two-stage power amplifier has been designed utilizing
components from the LTCC passive library and a new temperature dependent power
MOSFET RF nonlinear model.
The inductor components in the library are implemented in the multi-level ground
plane architecture that allow com pact realization of microwave integrated circuit. For the
active device nonlinear model, a novel temperature dependent large-signal model with
self-heating and ambient temperature effects for power MOSFETs was developed from
on-wafer pulse IV measurements at different ambient temperatures.
This CMOS-LTCC power amplifier eliminates the needs for discrete components,
which consequently reduces the cost. This development is the first integrated PA using
LTCC and a significant step towards the realization of a highly integrated RF system
using LTCC multi-layer integral passives. This is a significant step toward a higher level
of integration for 1.9-GHz DECT transceiver module development based on a standard
MOSFET technology and high-Q LTCC passives.
108
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CHAPTER V
CONCLUSION
This thesis has presented a new deep sub-micron (0.25-pm) M OSFET R F large
signal model that incorporates a new breakdown current model and drain-to-substrate
nonlinear coupling in order to ensure the circuit performance for the required frequency
bands and also shorten the design cycle. Using this nonlinear modeling method, for the
first time, a 1.9-GHz MOSFET power am plifier module with fully integrated high-Q
LTCC passives is demonstrated. This highly integrated module, suitable for DECT
applications, was built based on multi-layer LTCC passives.
A novel deep sub-micron (0.25-pm) MOSFET RF large-signal model that
incorporates a new breakdown current model and drain-to-substrate nonlinear coupling
was developed and investigated using various experiments. An accurate breakdown
model is required for deep sub-micron M OSFET’s due to its relatively low breakdown
voltage. For the first time, the breakdown voltage turnover behavior has been
incorporated in a continuously differentiable channel current model to predict nonlinear
operation accurately around the soft breakdown region. Based on the philosophy o f the
separation of saturation and breakdown components of the nonlinear channel current, the
109
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model parameters o f the two current com ponents are decoupled to enable easy param eter
extraction. Frequency dependence o f the output admittance is accurately m odeled by
including a new drain-to-substrate nonlinear coupling network. The robustness o f the
model is verified with measured pulsed I-V, S-parameters. power characteristics and
intermodulation distortion (IMD) levels at different input and output termination
conditions, operating biases, and frequencies.
For the first time, we present a M OSFET power amplifier with fully integrated
multi-layer LTCC passives for 1.9-GHz DECT applications. The LTCC inductor and
capacitor library that allows high-Q passives and a higher level of integration is
developed. Using this LTCC passive library, the assembly time and cost incurred by the
discrete off-chip components can be eliminated.
The passive library has been implemented in Low Temperature Co-fired Ceramics
(LTCC) technology. The inductor components in the library were implemented using a
multi-level ground plane architecture to allow com pact realization. The capacitors used
for RF ground utilize the novel vertically interdigitated configuration (VIC) topology.
There are two obvious advantages to incorporating integral passives into the microwave
integrated circuit development. First, it eliminates the needs for discrete components,
which consequently reduces the cost. In addition, it also reduces the assembly time as
well as turn around time. The LTCC passives were simulated using an EM sim ulator such
as SONNET. In order to design the high performance power amplifier, a custom non­
linear M OSFET model has also been developed and incorporated.
110
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For the active device nonlinear model, a novel temperature dependent large signal
model with self-heating and am bient temperature effects for sub-micron (0.8-nm) power
M OSFETs was developed from on-wafer pulse IV measurements at different ambient
temperatures. The simulation data from the new model with self heating effects
demonstrates good agreement with measured S-parameters and power characteristics
including gain, efficiency, harmonic components and intermoduiation powers in class AB
operation.
The measured results show that an inductor Q-factor is as high as one hundred
with a self-resonant-frequency (SRF) as high as 8-GHz. The measured result of the power
amplifier showed a good agreement with the simulated results exhibiting 48-% power
added efficiency, 26-dBm output power at 1.9 GHz with a 3.3-V drain supply voltage.
This is the first significant step toward the compact 1.9-GHz DECT transceiver module
development using conventional MOSFETs and multi-layer LTCC technology.
This CMOS-LTCC pow er amplifier eliminates the needs for discrete components,
which consequently reduces the cost. This development is the first integrated power
amplifier utilizing LTCC technology. This work is a significant step toward a higher level
of integration for RF transceiver module development based on a standard MOSFET
technology and high-Q multi-layer LTCC passives.
Ill
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VITA
Deukhyoun Heo was bom on January 6, 1967 in Daegu, South Korea and received the
B.S.E.E. degree in electrical engineering from Kyoungpuk National University, Daegu.
South Korea, in 1989 and worked as a senior design engineer in LG information and
communications Ltd. for six years. He also worked one and a half year as a design
engineer for Electronics and Telecommunications Research Institute in Taejon, South
Korea during that period. In 1997, he received M .S.E.E. degree in electrical engineering
from Pohang University o f Science and Technology (POSTECH), Pohang, South Korea.
He came to Georgia Institute of Technology, A tlanta GA, in fall, 1997. He joined
Microwave Applications Group, headed by Dr. Joy Laskar, his Ph.D. advisor in winter.
1998. He worked as research assistant at Georgia Institute of Technology and as a senior
design engineer in National semiconductor as a Co-op program. He continued to work
part time at Georgia institute o f Technology tow ards Ph.D. degree in electrical
engineering, where he authored and co-authored sixteen journal and conference papers.
His research interest includes system simulation and optim ization techniques, and design
and characterization o f MMIC and MMIC-based m odules for wireless communication
applications based on CM OS, BiCMOS, SiGe, and G aAs technologies.
118
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