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Development of silicon germanium-based power heterojunction bipolar transistors and their application to microwave power amplification

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DEVELOPMENT OF SiGe-BASED POWER
HETEROJUNCTION BIPOLAR TRANSISTORS
AND THEIR APPLICATION TO
MICROWAVE POWER AMPLIFICATION
by
Zhenqiang M a
A dissertation submitted in partial fulfillment
of the requirements for the degree of
Doctor of Philosophy
(Electrical Engineering)
in The University of Michigan
2001
Doctoral Committee:
Professor Pallab Bhattacharya, Chair
Professor Erdogan Gulari
Professor Linda P. B. Katehi
Professor Dimitris Pavlidis
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UMI Number: 3016912
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Copyright 2001 by Bell & Howell Information and Learning Company.
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Zhenqiang Ma
All Rights Reserved
2001
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Dedicated to my parents Yuqin Fan and Xiuji Ma, my wife shaoqin Gong, my daughter
Alice Lily Ma, my brothers and sisters Zhenmei Ma, Zhengang Ma, Zhenming Ma and
Zhenling Ma (in my memory), and the Ma’s families all over the world
ii
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ACKNOW LEDGM ENTS
I would like to express my deepest gratitude and appreciation to my research
advisor Professor Pallab Bhattacharya, for his countless advice, continuous support and
guidance and sincere concern and encouragement. My past three and half years with
him, which are fruitful and full of wonderful memories, will benefit me for the rest of my
life. I specially thank Professor Linda P. B. Katehi for her kind interest, great assistance
and, specially, her countless encouragement for my research work.
I am also very
grateful to Professor Dimitris Pavlidis for his various help in the past years and Professor
Erdogan Gulari for taking out his valuable time to serve on my committee.
My special thanks should go to Dr. Jae-Sung Rieh for his mentoring on my initial
experimental research in the solid-state area. His exemplary attitude toward research and
his superior personality are always the goals that I have been pursuing.
I am very grateful to Dr. Saeed Mohammadi for his mentoring, encouragement
and great help on various things in my reseach. Without his help, the completion of this
thesis will not be possible.
I am also very grateful to Dr. Samuel Alterovitz and Dr. George Ponchak at
NASA-Glenn Research Center for their great assistance and numerous valuable
suggestions for my doctoral research. Without their direct help, the completion of this
thesis is also not possible. I thank Dr. Edward T. Croke at HRL Laboratories and Dr.
Karl M. Strohm and Dr. Johann-Friedrich Luy at Daimler-Chrysler Research Center for
their high-quality MBE materials.
iii
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I thank my colleagues and friends for their help, encouragement and concern:
they are Dr. Heather Trigg, Dr. Dennis Grimard, Dr. Omar Qasaimeh, Dr. Herte
Gebrersadik, Dr. Weidong Zhou, Dr. Sanjay Krishna, Dr. Guohong He, Dr. Donghai Zhu,
Dr. Wei Kong, Dr. Egor Alekseev, Dr. Cheng-Hui Lin, Dr. Andew Brown, Dr. Katherine
Herrick, Dr. Kevin Lu, Sameer Pradhan, Jayshri Sabarinathan, Siddhartha Ghosh, Jian
Xu, Boaz Kochman, Adrienne D Stiff, Carl H Fischer, Sasan Fathpour, Pei-chen Yu,
Xing Cheng, Yongming Cai, Arvind Salian, Jun Zheng, Shuo-hung Hsu, Kok Yan lee,
Jaehoon Park, Wan-Hsuan Yen and Tae-Young Choi, Patty Chiang-Chien, Ning Gulari,
Guan Leng Tan, Chunbo Zhang, Dimitrios Peroulis, James Becker, Seth Hubbard, Florea
C atalin
and all SSEL staff members.
iv
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TABLE OF CONTENTS
D E D IC A T IO N ................................................................................................................... ii
A C K N O W L E D G M E N T S ............................................................................................ iii
L IS T O F F IG U R E S ....................................................................................................... vii
CHAPTER
I.
IN T R O D U C T IO N ..................................................................................... 1
1.1 Foreword....................................................................................... 1
1.2 The Heterostructure and a Brief History of the SiGe
Alloy System.................................................................................3
1.3 Objective and Outline of This Thesis..........................................7
n.
D E S IG N A N D F A B R IC A T IO N O F X -B A N D (8.4
G H z) N P N S iG e/S i P O W E R H B T ’S ..............................................11
2.1 Introduction.................................................................................11
2.2 Device Design Consideration.....................................................13
2.2.1 Heterostructure design.............................................. 13
2.2.2 Layout design.............................................................25
2.3 Fabrication Process of Double-Mesa Type SiGe/Si HBT’s ....34
2.4 Summary.....................................................................................41
IH .
D C , S M A L L - A N D L A R G E -S IG N A L
C H A R A C T E R IS T IC S O F X -B A N D (8 .4 G H z) N P N
S iG e/S i P O W E R H B T ’S ......................................................................44
3.1 Introduction................................................................................ 44
3.2 DC Characteristics...................................................................... 45
3.3 Small-signal RF characteristics................................................. 52
3.4 Large-signal RF characteristics................................................. 57
3.5 Summary.....................................................................................64
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IV .
X -B A N D (8.4 G H z) S iG e/S i H B T -B A S E D
M O N O L IT H IC A L L Y IN T E G R A T E D P O W E R
A M P L I F I E R S ..........................................................................................67
4.1 Introduction.................................................................................67
4.2 Characteristics of SiGe/Si Multifinger HBT’s ......................... 68
4.3 Amplifier Design and Fabrication............................................. 71
4.3.1 Large-signal modeling of power HBT’s ..................71
4.3.2 Characterization and modeling of lumped
passive components...................................................77
4.3.3 Circuit design and fabrication...................................81
4.4 Power Amplifier Characteristics................................................81
4.5 Summary..................................................................................... 87
V.
D E V E L O P M E N T O F K u -B A N D (12.6 G H z) N P N
S iG e /S i P O W E R H B T ’S ___________________________________ 88
5.1 Introduction................................................................................. 88
5.2 Design Considerations for High-Frequency Power HBT’s
89
5.3 Heterostructure and Layout Design........................................... 91
5.3.1 Heterostructure design.............................................. 91
5.3.2 Layout design............................................................. 93
5.4 Process Development for Small Feature Fabrication and
Isotropic Dry etching.................................................................. 95
5.5 DC and Small-Signal RF Characteristics..................................98
5.6 Large-Signal RF Characteristics..............................................104
5.7 Summary................................................................................... 105
VI.
LONG-TERM RELIABILITY OF SIGE/SI HBT’S
UNDER ACCELERATED LIFETIME TESTING........... 107
6.1 Introduction............................................................................... 107
6.2 Accelerated Lifetime Testing Techniques...............................109
6.3 Reliability Testing Results and Analysis................................113
6.4 An Analytical Model for Recombination Enhanced
Impurity Diffusion (REID)......................................................118
6.5 Summary................................................................................... 124
VH.
C O N C L U S IO N S A N D S U G G E S T IO N S F O R
FUTURE RESEARCH.............................................................125
7.1 Conclusions............................................................................... 125
7.2 Suggestions for Future Research.............................................129
B IB L IO G R A P H Y .......................................................................................................... 131
vi
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LIST OF FIGURES
Figure
1.1
An avionics microsystem enabled by SOAC technology (Source: 7999
Annual Report, CISM, JPL/NASA, p.3)........................................................... 3
1.2
Schematic representation of the pseudomorphic growth of SiGe on top
of Si substrate. The SiGe layer is coherently strained due to the lattice
mismatch.............................................................................................................. 4
1.3
Band alignment of SiGe/Si heterostructure when SiGe is coherently
strained..................................................................................................................5
2.1
Epitaxial structure of the X-band power SiGe/Si HBTs: (a) HBT_1;
(b) HBT_2. All the values are designed values.............................................26
2.2
Measured SIMS profiles of the CVD grown X-band power SiGe/Si
HBTs : (a) HBT_1 showing the complete structure; (b) HBT_1 with a
detailed analysis of the emitter and base layers; (c) HBT_2 showing
the complete structure; (d) HBT_2 with a detailed analysis of the
emitter and base layers...................................................................................... 27
2.3 Layout considerations for SiGe power HBT design: (a) a compact
layout in which all emitter fingers are bound together. This layout
leads to high temperature rise in the center area; (b) significant
voltage drop for many finger devices due to the high spreading
collector resistance; (c) a non-compact layout with two emitter fingers
bound together in a subcell. Collector spreading resistance is reduced
and thermal effects are suppressed to an acceptable level............................. 31
2.4 Layout of a 6 -finger (each of size 2x30 pm2) common-base HBT
showing the distributed feature.........................................................................33
2.5 Fabrication flow of double-mesa type Si/SiGe/Si H B T s............................... 42
2.6 Photomicrographs of the fabricated 10-finger SiGe/Si power HBTs:
(a) Common-emitter configuration; (b) Common-base configuration......... 43
vii
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3.1
I-V characteristics
fabricated from
configuration; (b)
voltages are BV c b o
of 10-finger SiGe/Si HBTs (Ae = 780 pm2)
heterostructure HBT_2: (a) common-emitter
common-base configuration.
The breakdown
= 26 V and BVqeo = 23 V.............................................. 47
3.2
DC current gain P and differential current gain AP vs. collector current
Ic for a 10-finger SiGe/Si HBTs (Ae = 780 pm2) fabricated from
heterostructure HBT_2......................................................................................51
3.3
Forward (Island Ic,f) and reverse (Islan d Iej) Gummel Plots of a 10finger SiGe/Si HBTs (A e = 780 pm2) fabricated from heterostructure
HBT_2................................................................................................................51
3.4
Frequency response of 10-finger (Ae = 780 pm2) SiGe/Si HBTs
showing current gain and power gain, fr and fmax are extrapolated
based on the assumption of - 6 dB/octave roll-off: (a) CE HBT; (b) CB
HBT.................................................................................................................... 56
3-5 fmax versus collector current Ic for 10-finger (Ae = 780 pm2) SiGe/Si
HBTs fabricated from structure HBT_2..........................................................58
3.6
Meaured Poul, Gain, PAE and Ic of 10-finger (a) CE and (b) CB
SiGe/Si HBTs fabricated from structure HBT_2............................................61
3.7
Meaured Pout, Gain, PAE and Ic of 20-finger (a) CE and (b) CB
SiGe/Si HBTs fabricated from structure HBT_2............................................63
3.8
Meaured Pout, Gain, PAE and Ic of 4-finger (actual emitter area 240
pm2)CE SiGe/Si HBTs fabricated from structure HBT_2. At the
highest measured Pout, the RF power density is 0.96 mW/pm 2 with the
associated PAE of 27.4%..................................................................................65
4.1
Measured and modeled DC current-voltage characteristics of 10finger common-base SiGe/Si HBT fabricated from structure HBT_2,
with emitter area of Ae = 780 pm 2 ___________________
70
4.2
RF response of 10-finger common-base SiGe/Si HBT fabricated from
structure HBT_2, with emitter area of Ae = 780 pm 2 measured at Ie =
-77 mA and VCB = 7 V .................................................. 1..................................70
4.3
Measured output power Pout, gain, power added efficiency PAE and
collector efficiency rjcoii as a function of input power P;n at 8.4 GHz
biased for class AB operation (V eb = -1.176 V and V cb = 8.1 V) under
CW conditions of 10-finger common-base SiGe/Si HBT with emitter
area of A e = 780 pm2. The source (Ts = 0.64Z1780) and load (TL =
0.71Z850) matching are optimized for maximum output power. The
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output power is 24.2 dBm with concurrent gain of 6.9 dB and 28.1%
PAE. Maximum Pout is 26.3 dBm and maximum r|coii is 36.9%...................72
4.4
Complete Gummel-Poon model for 10-emitter fingers common-base
SiGe power HBT based on structure HBT_2 with values of the device
parameters and parasitics used in the model................................................... 74
4.5
Modeled and measured small-signal S-parameters of 10-finger
common-base Si/SiGe/Si HBT from structure HBT_2 at Ie = -77 mA
and V cb = 7 V from 2-26 GHz.........................................................................75
4.6
Predicted from Gummel-Poon model and measured output power of
10-finger common-base Si/SiGe/Si HBT (based on structure HBT_2)
as a function of input power under the same source (Ts = 0.64^178°)
and load (T l = 0.71Z850) matching and same bias conditions (V eb = 1.176 V and VCB = 8.1 V)................................................................................ 76
4.7
(a) Equivalent circuit of a 3.5-tum spiral inductor; (b) The S-parameter
fitting with the equivalent circuit of (a); (c) Inductance value change
with number of turns.........................................................................................79
4.8
(a) Equivalent circuit of a 4000-pm2 MIM (200 nm SiO insulated)
capacitor; (b) The S-parameter fitting with the equivalent circuit of (a);
(c) The capacitance value change with capacitor area. The unit-area
capacitance value is 0.2 fF/pm 2 ....................................................................... 80
4.9
(a) Schematic of single-stage MMIC power amplifier using commonbase (CB) SiGe/Si HBT and passive components; (b)
Photomicrograph of a fabricated MMIC power amplifer (chip size, 1 x
0.75 pm2)........................................................................................................... 82
4.10 Small-signal performance of MMIC power amplifier with 8.7 dB gain
at 8.4 GHz and input/output return loss of 7.1 dB and 4.9 dB,
respectively, at the same frequency................................................................. 83
4.11 (a) Power performance of the SiGe/Si HBT MMIC amplifier biased at
VEB = -1.3 V and VcB = 11.5 V. 22.9 dBm output power at peak
efficiency and 24.8 dBm in saturation were obtained, (b) Power
performance of the SiGe/Si HBT MMIC amplifier biased at V eb = 1.65 V and VCB = 7.0 V. Peak PAE of 16% was obtained............................85
5.1
Epitaxial structure of the Ku-band power SiGe/Si HBT: HBT_3. The
subcollector layer is grown by CVD and the rest is grown by MBE.
All the values are designed values...................................................................94
ix
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5.2
Measured SIMS profiles of the MBE grown Ku-band power SiGe/Si
HBTs : (a) HBTJ3 showing the complete structure; (b) HBT_3 with a
detailed analysis of the emitter and base layers...............................................94
5.3
SEM photomicrograph showing the air bridge structure made with
isotropic dry etching. The air bridges are encapsulated with 1-pm
PECVD S i0 2 ...................................................................................................... 99
5.4
Photomicrographs of fabricated 15-emitter finger (1-pm width)
common-base SiGe/Si HBTs: (a) without air bridges; (b) with air
bridges................................................................................................................. 99
5.5 I-V characteristics of 15-finger CB SiGe/Si HBTs ( A e = 672 pm2)
fabricated from heterostructure HBT_3. The breakdown voltages are
B V c b o = 2 0 V and B V c e o = 13 V................................................................... 1 0 0
5.6 DC current gain P and differential current gain Af3 vs. collector current
Ic for a 15-finger SiGe/Si HBTs (AE = 672 pm2) fabricated from
heterostructure HBTJ3.....................................................................................101
5.7
Forward (lB,f and Ic,f) and reverse (IB.r and IEj) Gummel Plots of a 15finger SiGe/Si HBTs (AE = 672 pm2) fabricated from heterostructure
HBT_3............................................................................................................... 101
5.8 Frequency response of 9-emitter finger (AE = 403 pm2) CB SiGe/Si
HBTs showing power gain, fmax of 100 GHz is extrapolated based on
the assumption of - 6 dB/octave roll-off.......................................................... 103
5.9 Frequency response of 15-emitter finger (AE = 672 pm2) CB SiGe/Si
HBTs showing power gain, fmax of 83 GHz is extrapolated based on
the assumption of - 6 dB/octave roll-off.......................................................... 103
5.10 Meaured Pout, Gain, PAE and Ic of 15-emitter finger CB SiGe/Si
HBTs fabricated from structure HBT_3......................................................... 105
6.1 Schematic of Si/SiGe HBT, in which the As-doped subcollector layer
is grown by CVD and the rest of the heterostructure is grown by M B E ... 110
6.2 Schematic cross-section of a double mesa self-aligned Si/SiGe HBT.........I l l
6.3 Layout of the tested double-mesa type single-finger Si/SiGe/Si HBTs
with emitter area of 5x20 pm 2 and no encapsulation layer on the top of
interconnection lines........................................................................................ I l l
6.4 Typical degradation behavior for a SiGe/Si HBT. The constant
collector current and step-like base current change with time is the
manifestation of feedback control...................................................................114
x
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6.5
6 .6
6.7
6 .8
6.9
Base-emitter and base-collector junction diode characteristics before
and after accelerated lifetime testing. Increased leakage current
develops at base-emitter junction in reverse and low forward bias
regimes. The reverse bias leakage current at base-collector junction is
reduced...............................................................................................................114
DC current gain versus base-collector bias voltage at different baseemitter biases after accelerated lifetime testing.............................................117
Gummel plots of a SiGe/Si HBT before and after accelerated lifetime
testing. Base-emitter tum-on voltage increased by 50 mV after the test... 117
Arrhenius plot for lifetime of the Si/SiGe/Si HBTs. MTTF(300K) =
1.9xl0 7 hours, <£ =0.77 eV.............................................................................. 120
Model for boron outdiffusion from base layers into adjacent emitter
and collector layers due to electrical-thermal stress...................................... 1 2 0
6.10 Measured (solid lines) and calculated (dashed lines) normalized
current gain of Si/SiGe/Si HBTs as a function of stress time for
different junction temperatures........................................................................1 2 2
xi
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CHAPTER I
INTRODUCTION
1.1
FOREWORD
The invention of semiconductor transistors, integrated circuits, heterojunctions and
lasers by Shockley, Bardeen, Brattain, Alferov, Kroemer and Kilby, has triggered an
explosive information revolution in our world. This epoch-making revolution has altered
our planet into a “village” via the wired and wireless communication tools. Fueled by the
demand of professional applications and personal handsets, the wireless communication
market has experienced a substantial and rapid growth over the past few years and this
growth is expected to continue in the foreseeable future. Future wireless communication
systems will require higher speed for faster data transmit rate, higher operation frequency
to accommodate more channels and users, more functionality, light weight, low power
consumption and low cost. One of the solutions to meet these requirements is embodied
in the concept of a complete wireless system on a chip.
Integrating the receiver,
transmitter and other processing circuits on a single chip can not only reduce the volume
and weight of a wireless communication unit significantly, but can also reap the cost
benefit from volume production.
To meet the high speed and high frequency
requirements with a high level of integration for such a system-on-a-chip, the material
system has to be suitably selected. Devices made from III-V materials, due to their
1
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2
superior carrier transport characteristics and the feasibility of bandgap engineering,
exhibit high-speed characteristics and are suitable for high frequency operation. The
availability o f semi-insulating substrates in IH-V materials also made the realization of
microwave monolithically integrated circuits (MMIC) feasible with these materials.
However, the high cost, low thermal conductivity and poor mechanical strength of these
materials have made them slightly inaccessible for high-level integration. On the other
hand, the conventional low-cost Si-based devices, in which the frequency response is
limited by intrinsic Si material properties, are not suitable for microwave applications.
Another obstacle that impeded the use of Si for microwave application for many years is
the lack of semi-insulating substrates. Fortunately, the major advances made with SiGebased devices and the low-cost growth of high-resistivity (104 Q-cm) Si substrates made
possible in recent years have reduced, or removed, the limitations posed by conventional
Si technology. W ith the realization of both fmax a n d / 7 - over 130 GHz [l]-[2], SiGe-based
devices have demonstrated their suitability for microwave and millimeter wave
applications. In addition, the SiGe-based material system, like Si, has the advantages of
low cost, maturity of process technology, superior thermal conductivity, compatibility
with CMOS technology, mechanical stability of substrate and ease of high-level
integration. In particular, compatibility with CMOS technology provides the opportunity
for integration of RF/microwave modules with low-frequency circuitry and hence offers
the feasibility of realization of a complete wireless system on a chip. A “system-on-achip” example of large-scale integration is shown in Figure 1.1.
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3
M ultiple Science Packages o f D istributed Sensors
(Attached to A rm . Sail, Deployable Structure, etc.)
C om m ercial Systern-O n-A -C ltip
(Logic + M em ory)
N onvolatile M em ory
■O p tical Interconnect to
Avionics M icrosystem
S O I w ith D ie A ttach to Flex
M icronavigator
A u /S n Eutectic Bonding
to S O I Substrate -----
R F C om
From
Pow er Bus
Flex o r R igid Substrate
S O I w ith D ie A ttach to Flex
M onolithic Power Chip
-D C -D C
Converter
w ith
Integrated
Passives
• Battery
C harging
Circuit
- T h in -F ilm
Battery
B ackup
Advanced T herm al C ontrol A ttached to Backside
o f Substrate (T herm oelectric Cooler. M EM S
M icropum p/M icrocooler. etc.)
Figure 1.1: An avionics microsystem enabled by SOAC technology (Source: 1999
Annual Report, CISM, JPL/NASA, p.3)
1.2
THE HETEROSTRUCTURE AND A BRIEF HISTORY OF THE SiGe/Si
ALLOY SYSTEM
The lattice constant of Si (5.431
mismatch.
A)
and Ge (5.646 A) are different, with a 4.18%
This considerable lattice mismatch sets an upper limit for the thickness of
Sii.xGex alloy that can be grown on a Si substrate without generating dislocations. In this
“pseudomorphic” regime (Figure 1.2), the SiGe layer is coherently strained, the degree of
which depends on the amount of misfit and to some extent on epitaxial growth
parameters. Detailed band structure studies have elucidated the major benefits for bipolar
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4
SiGe epitaxial layer
pseudomorphic
Si substrate
Figure 1.2: Schematic representation of the pseudomorphic growth of SiGe on top of Si
substrate. The SiGe layer is coherently strained due to the lattice mismatch.
transistor operation due to the strain present in the Sii_xGex layer. These benefits can be
summarized into the following categories: (a) the lifting of degeneracy in the conduction
band o f strained Sii.xGex lowers the energy of the conduction band minima and thus
causes bandgap shrinkage; (b) the out-of-plane effective mass of electrons, perpendicular
to the SiGe/Si heterointerface is reduced; (c) the lifting of degeneracy of the valence band
maxima causes a major bandgap shrinkage in strained Sii_xGex alloy (Figure 1.3); and (d)
the in-plane effective mass of holes is reduced due to the lifting of the valence band
degeneracy.
The superior hole transport favors a low base sheet resistance and the
reduced electron effective mass reduces the carrier transit delay time, both of which are
desirable for bipolar junction transistor (BJT) operation. The reduction in carrier mobility
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5
Figure 1.3: Band alignment of SiGe/Si heterostructure when SiGe is coherently strained.
due to alloying-scattering is outweighed by the above mentioned benefits due to the
coherent strain in the Sii.xGex alloy. More importantly, the large valence band offset
(Figure 1.3) provides a large current gain and thus eliminates the doping concentrationlimited electron injection efficiency for an NPN type BJT. The large current gain can be
realized in spite of a high doping concentration in the Sii-xGex base region, to obtain an
extremely low base resistance even with a very thin base layer thickness.
performance
heterojunction
bipolar
transistors,
with
high-frequency
High
response
characteristics comparable to devices made with DI-V materials, are now being realized.
Among the various thin film SiGe deposition techniques that appeared in the
1960’s are the solution technique by Miller et al [3] and by Donnelly et al [4], and the
vapor deposition technique by Riben et al [5]. Detailed material studies on SiGe thin
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6
films were made in the 1970’s by Vasilevskaya et al in Ukraine [6 ] [7], Cullis et al [8 ]
and Aharoni et al [9] in the United States. The demonstration of a SiGe/Si superlattice,
with UHV deposition, was done by Kasper et al in Germany in 1975 [10].
This
monumental achievement demonstrated maturity in the growth of coherently strained
SiGe thin film alloys on Si.
The study of the electronic properties of the strained SiGe thin film alloys was
pioneered by Bean and People et al [11] [12] in the 1980’s, along with the investigation
of modulation doped field effect transistors (MODFETs) [13]. The bandstructure and the
band alignment of the pseudomorphic SiGe/Si system were first studied by Lang, et al
[14] and by Temkin et al [15], respectively, at that time. These investigations triggered
the extensive research activities with SiGe-based devices.
The fist MBE-grown DC
Si/Sio.ssGeo.u/Si HBT was developed at IBM by Iyer et al [16] in 1987, which shows the
expected HBT operation and enhanced collector current level over a comparable Si BJT.
Considerable research has been made on SiGe-based HBTs thereafter, which has been
dominated by IBM and Daimler-Chrysler (former Daimler-Benz). The planar process,
which is adopted by IBM from the traditional Si process technology, provides the ease
and low cost for high-level integration with Si CMOS to form the SiGe-based BiCMOS
process. The success of the high-temperature planar process has made IBM the world’s
leading vendor o f SiGe-based devices, circuits and systems. The highest cut-off
frequency f r achieved by IBM is over 100 GHz [17]. The only shortcoming associated
with the high temperature planar process is the maximum tolerable Ge fraction in the
base region, as limited by the critical layer thickness.
The mesa-shaped SiGe-based
HBT, employed by Daimler-Chrysler, is a modified adoption of the traditional IH-V
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7
processing technology.
For this double-mesa structure, the whole manufacturing
procedure is free of high temperature processing. As a result, this “cold” process leaves
insufficiently passivated surfaces and thus causes a high leakage current at the baseemitter junction at low bias levels.
However, the “cold” process allows higher Ge
fraction in the strained SiGe base layer and thus produces better high-frequency
performance of the transistors than the planar process. The highest maximum oscillation
frequency fmax achieved by Daimler-Chrysler is 160 GHz [1], which has been the world’s
record for more than
6
years.
A number of reports, on the successful implementation of MMICs with SiGe/Si
HBTs as the active components, appeared in the 1990’s after the maturity of SiGe HBT
technology.
These include voltage-controlled oscillators (VCO’s) with oscillation
frequency of 26 and 40 GHz [18], X-band mixers [19] and narrow-band and wide-band
amplifiers at Ka- [20] and Ku-band [21], respectively. Small-signal narrow band X- and
Ku-band amplifiers, implemented with Si/SiGe HBTs and micromachined lumped
passive components, have also been reported [2 2 ].
The
superior
performance
of
SiGe-based
devices
and
the
successful
implementation of MMIC circuits with these devices, combined with the possibility of
further improvement in both device and the circuit performance, make this material
system a leading contender in the coming years for a “system-on-a-chip” solution of the
next generation communication systems.
1.3
OBJECTIVE AND OUTLINE OF THIS THESIS
A prevailing concern with the SiGe material system has been its potential to
realize efficient power amplifiers, which are crucial circuit components of RF/microwave
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8
transmitters. Compared to field effect transistors (FETS), bipolar junction transistors
(BJTs) have a higher current-handling capability and promise higher voltage operation
with better linearity.
In addition, HBTs usually exhibit high gain even at low bias
conditions, which is essential for class AB and class B operations. As a result, higher
efficiency power amplifiers can be realized with these devices.
However, since the
demonstration of the highest fmax in a SiGe HBT [1], the investigation and development
of SiGe microwave power HBTs have only received limited attention. Efforts on the
microwave power application of SiGe-based HBTs have so far been limited to L- [23]
[24], S- [25] [26], and C-band [27] operations. The demand for higher channel capacity
in wireless communication will naturally drive the wireless operation frequency to X- and
higher frequency bands and the reported performance characteristics of SiGe HBTs [28]
[29] operating in these bands are rather limited. The frequency response of large-area
devices, which are needed for high output power, is usually poorer than that of small-area
devices, mainly due to severe thermal effects in large-area devices. A drawback in the
development of X- and higher frequency band power SiGe HBTs, arising from the (at
least) -6 dB/octave power gain reduction for small-signal operation and additional gain
compression for large-signal operation, is that high output power can only be obtained at
the cost of low power gain [28] and vice versa [29]. Nonetheless, a high output power
with a concurrent high power gain (hence PAE at a certain class of operation) is always
required for the implementation of efficient power amplifiers. To achieve this goal, the
heterostructure and the device layout have to be well designed, with considerations of
thermal effects, breakdown voltage, fmax and output power.
Power amplifiers using
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9
SiGe/Si HBTs have only been demonstrated at C-band frequencies [27] and the
demonstration of a MMIC power amplifier has not been reported.
The main objective of the study presented in this thesis was to investigate the
operation of high power and high efficiency SiGe/Si HBTs in the X-band (8.4 GHz) and
Ku-band (12.6 GHz). Another objective of this study was to demonstrate MMIC-type
power amplifiers with SiGe-based HBTs in the X-band (8.4 GHz).
In addition, the
reliability and the degradation mechanisms of SiGe/Si HBTs were also investigated by
accelerated lifetime testing.
This thesis consists of seven chapters. The design and fabrication of X-band (8.4
GHz) power SiGe/Si HBTs is described in Chapter II.
Emphasis has been laid on
improving the high-frequency response characteristics, while maintaining the high power
handling capability of the HBTs through the design and the fabrication process. The DC,
RE and state-of-the-art large-signal power performance characteristics of the X-band
devices are presented in Chapter HI. The relationship between the measured DC, smallsignal and large-signal characteristics is discussed in detail in this chapter and the
difference in performance between the common-emitter and the common-base SiGe/Si
HBTs has been analyzed. In Chapter IV, the first demonstration of SiGe/Si HBT-based
MMIC power amplifies is reported. The large-signal modeling of SiGe/Si HBTs with the
conventional Gummel-Poon model is discussed, wherein the interplay of the Kirk effect
and the Early effect at high bias levels is addressed for the first time. The fabrication and
modeling of the lumped passive components is also discussed in this chapter along with
the design of the power amplifier circuit. The first Ku-band (12.6 GHz) power SiGe/Si
HBT development is discussed in Chapter V, focusing on the aggressive modifications of
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10
the device heterostructure design and of the layout, as well as the fabrication process for
small-feature sizes with optical lithography. DC, small-signal and larger signal power
performance characteristics of these Ku-band HBTs are then described and discussed.
The investigation of the long-term reliability of SiGe/Si HBTs is described in Chapter VI,
with a detailed analysis of the device degradation mechanism.
The recombination
enhanced impurity diffusion (REID) of the boron dopant atoms in SiGe/Si HBTs is
included in the analytical model that has been developed on the basis of the low-level
injection theory. Finally, important conclusions and suggestions for future research are
made in Chapter VII.
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CHAPTER H
DESIGN AND FABRICATION OF
X-BAND (8.4 GHz) NPN SiGe/Si POWER HBT’S
2.1
INTRODUCTION
The performance of the active devices largely dictates the overall performance of
a circuit. As a result, the development of high performance transistors is of crucial
importance over a wide range of applications. The performance parameters of transistors
include DC performance parameters, such as current gain, breakdown voltage, offset
voltage, maximum current density, etc., and RF performance parameters, such as cut-off
frequency, maximum frequency of oscillation, etc. Power transistors, which constitute
the power amplifier of a microwave transmitter, can be further characterized by such
performance parameters as output power, power gain, power-added efficiency, input and
output impedance, linearity, etc. In order to achieve the high performance of transistors,
the transistor design parameters have to be properly chosen. These design parameters
include vertical structure parameters, such as layer thickness and doping level/profile,
alloy composition, etc., and lateral geometrical dimensions. While both BJTs and FETs
can be used for microwave applications, for microwave power applications BJTs are
preferred over FETs owing to their better power handling capability and higher linearity.
In addition, BJTs have gain even at very low-bias levels and hence high-efficiency power
11
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12
amplifiers can be realized more easily with BJTs than FETs. In terms of the material
properties, IH-V-based power transistors have superior high-frequency characteristics
over Si-based devices and, as a result, modem microwave power transistors have been
dominated by IH-V materials. However, ffl-V materials suffer from their poor thermal
conductivity (0.46 W/cmK for GaAs at room temperature), high cost and poor
mechanical strength. The high power operation of IH-V power transistors require special
designs such as ballasting resistors, thermal shunts, wafer thinning, or extended finger
spacing for more effective heat sinking. On the other hand, due to their poor mechanical
and thermal properties, large-scale integration of these high-speed transistors on a single
chip has become very difficult. Silicon, on the other hand, has much better thermal
conductivity (1.41 W/cmK) and better mechanical strength than IH-V-based materials
and, as a consequence, many design constraints of Si-based transistors can be relaxed and
a compact layout and high density and high-level integration are thus possible.
In
addition, the incorporation of Ge in the thin base layer of Si-based bipolar transistors,
forming heterojunctions at both emitter and collector sides, has broken the frequency
response limitation of the conventional pure silicon-based BJTs and demonstrated the
promise of their applications in microwave power applications. A properly designed
SiGe/Si power HBT can deliver high output power with high gain and associated high
power-added efficiency when the device is operating at X-band microwave frequencies.
In this chapter, the design and fabrication of double-mesa type Si/SiGe/Si power HBTs
will be discussed in detail. Following the design considerations in Section 2.2, the actual
heterostructures and layout employed in this work will be discussed in Section 2.3. The
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13
fabrication process with the key technologies will be described in Section 2.4 followed by
a summary in Section 2.5.
2.2
DEVICE DESIGN CONSIDERATIONS
The design goal for a power HBT is to achieve high-frequency operation while
maintaining high power handling capability. Theoretically, a high output power (AC
current-voltage product) may be realized with either a high operation voltage combined
with a low current density or vice versa, implied by the fact that the device design
requirements for a high operation voltage and those for a high current density are
opposite with each other and thus cannot be both satisfied in a specific design. In reality,
both approaches are not suitable for achieving high output power in an efficient way as it
can be seen in the following discussions. The requirements for high-frequency operation
and high output power are inter-related with each other and an optimized compromise
sometimes has to be made.
2.2.1
Heterostructure Design
The heterostructure design is to properly select the layer thickness, composition
and doping concentration/profile for each epitaxial layer and the substrate.
The
considerations of selecting these parameters for achieving high-frequency operation are
first discussed. All the discussions are based on NPN-type Si/Sii-xGex/Si double HBTs.
Two figures of merit, the cut-off frequency fi- and the maximum oscillation frequency
fmax, are frequently used to represent the device RF characteristics. These two parameters
can be expressed, in terms of the device intrinsic parameters, as the following:
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14
where r EC represents the sum of all the delays (transition and charging) encountered by
the carriers as they flow from the emitter to the collector and can be further expressed as,
(2 .2 )
In this expression,
te
is emitter-charging delay, r B is base diffusion transit delay, rc is
the collector charging delay and t CSCL is the carrier transition delay in the collector space
charge layer, fi- is the frequency at which the short-circuit common-emitter current gain
o f a BJT extrapolates to unity and it represents the current gain characteristic of a BJT at
high frequencies. As a result, f r itself is not very useful when the device characteristics
are evaluated for power applications. For the common-base configuration, because there
is no current gain this parameter is even not defined, fmax is the frequency at which the
power gain extrapolates to unity and is the single most important parameter for
evaluating the device RF characteristics for power applications. It can be expressed as,
max
(2-3)
where RB is the base resistance and CBC is the base-collector junction capacitance. The
larger is this fmax value, the higher power gain has the device at a certain operating
frequency. Based on Eq. 2.1 to Eq. 2.3, in order to get a high value o f fmax RB > CBC and
all the time delay terms, te , r B, Tc and t CSCL have to be minimized during the device
design. However, these parameters are inter-related with each other and the optimization
of these parameters cannot be achieved in a straightforward manner. Fortunately, due to
the advancement of the computer technology in nowadays, the inter-related optimization
for device design has been eased by numerical simulation with the available CAD tools
such as MEDICI, DAVINCI, SELVACO, etc. Since these CAD tool venders frequently
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15
update their packages with the state-of-the-art research results from the literature, the
simulated results largely, sometimes very accurately, predict or verify the measurement
results. The disadvantage o f using these user-friendly and highly sophisticated tools is
the concealment of the underlying physics. On the other hand, analyzing the effects of
each design parameters on the device overall performance from a physical point of view
can give a clear picture and a right direction for the device optimization. This knowledge
can be applied to the numerical simulation with any o f the CAD tools for a faster and
reasonable solution.
With the term-by-term analysis of Eq. 2.1 to Eq. 2.3, the
considerations for the heterostructure design are given below.
The emitter-charging delay can be expressed as,
te
kT
= — - C be,
q ic
(2.4)
where I c is collector current and CBE is base-emitter depletion capacitance. To reduce
r E, I c needs to be maximized and CBE needs to be minimized. The maximum I c is
limited by the Kirk effect, which is further limited by collector doping concentration as
can be seen from the following expression:
I
k =
^ . ^ 1
+^
7%
qly c yvc
) “ 9V,JVC.
(2.5)
where vx is the carrier saturation velocity, VCB is the applied base-collector voltage, eSi
is the permittivity of Si, Wc and N c
concentration, respectively.
are the collector layer width and doping
At this stage of discussion, a high doping level in the
collector layer is favorable. To reduce CBE, the emitter doping concentration should be
low and the emitter layer width WE should be large. A low-level of emitter doping is
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16
favorable for suppressing tunneling current from the emitter-side valence band to the
base-side conduction band due to quantum mechanical tunneling effect. The emitter
doping concentration, however, should not be made too low, as the emitter injection
efficiency will be reduced too much.
The current gain, lowered by this effect and
enhanced by the valence band offset at the base-emitter heterojunction, should be kept at
a reasonable level. The emitter doping profile can be made uniform across the emitter
width. A thick emitter layer is favored for larger current gain and large open-collector
base-emitter breakdown voltage B V ^ q . However, the emitter layer width WE should
not exceed the maximum depletion thickness during large-signal operation, or
unnecessary emitter serial resistance can be resulted from the undepleted region of this
layer.
The base diffusion transit delay r s can be expressed as,
W2
(2 -6)
where WB is the neutral base region width, y is the field factor accounting for the effect
of the induced quasi-electric field in this region and DnB is the minority carrier
diffusivity. A smaller
t b
can be achieved with a narrower base region width WB . The
reduction of the base region width is more effective for the reduction of r B than other
parameters of Eq. 2.6 due to the square exponent of this parameter. This base region
width cannot be made too thin as this may bring in growth and fabrication difficulty and
result in large base sheet-resistance. For a uniformly doped base region, the field factor
y is 2. This factor can be increased by grading the Ge fraction with an up-sloped profile
from the base-emitter side toward the base-collector side (quasi-electric field
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17
I. fiV-i
E x = --------, Ei is the intrinsic Fermi level). However, a small Ge fraction near the baseq dx
emitter heterojunction reduces the valence band offset between the Si- emitter and SiGebase and thus reduces the current gain enhancement benefited from this band offset. A
small reduction of Ge fraction near the base-emitter heterojunction can decrease the
AEv
current gain exponentially ( P ° c e kT ) since the back-injection of the holes from base to
emitter decreases with the amount of the valence band offset exponentially. The current
gain reduction causes restrictions on the HBT design: in order to maintain a reasonable
value of current gain the highest base doping concentration is then limited. As can be
seen in the following discussion, a high base doping concentration is always favored for a
highfmax value. As a result, a graded Ge profile is favorable for a high f r but not for high
fmax■ From the process point of view (see Section 2.4), a low Ge fraction near the baseemitter junction results in low etching selectivity of SiGe over Si and the base layer can
be over etched resulting in a thinner base layer and higher base sheet resistance.
Fortunately, due to the presence of the Webster’s effect at high-level injection, the field
factor y in power HBTs is enhanced by a factor of 2 and becomes 4. As the power HBTs
are always operated at high-level injection, the speed benefits due to the Webster’s effect
are always present. Hence, without Ge grading in the base region, a smaller r B can still
be obtained for power HBTs. z B is usually a major fraction of the total time delay t EC
for low-power high-speed HBTs but not for a power HBT as can be seen in later
discussions.
For a uniform (box-type) Ge composition across the base region, the
fraction value x is another important parameter that needs to be well chosen. According
to Vegard’s Law, higher Ge fraction offers larger band offsets at the heterojunctions and,
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18
as a result, higher current gain can be obtained. With the increase of Ge fraction, the
carrier (both minority and majority) mobility is also enhanced due to strain-induced band
edge splitting. The enhancement of minority carrier mobility benefits the diffusivity
value Dn8 in Eq. 2.6 and the enhancement o f majority carrier mobility benefits the base
resistance R b- The maximum value of Ge fraction is nevertheless restricted by two
factors: the metastable SiGe layer thickness and the alloy scattering. The metastable
thickness is the upper limit that a SiGe layer can be grown without generating
dislocations in this layer. The higher is the Ge fraction, the lower is the metastable layer
thickness. In order to ensure a thin but easy-to-handle SiGe base layer (20-25 nm), the
Ge fraction has to be kept below 40%. Moreover, the alloy scattering becomes more
severe for Ge fraction of above 40%. Usually this fraction value is kept below 30%,
depending on specific growth facilities. Doping profile is another design parameter of
the base layer. Boron (B) is commonly used to dope SiGe base layer for the purpose o f a
very high doping concentration. The grading of this doping profile with a down-slope
from base-emitter side toward base-collector side can also generate a quasi-electric field
IcT 1 dl^
(quasi-electric field, Er = ------------ , P is boron dopant concentration) facilitating the
q P dx
minority carrier transit across the base region. A higher doping level near the baseemitter side is also favorable for a better p-type ohmic contact. However, due to the
extremely thinness of the base layer and the high diffusivity of the boron atoms, a sharply
graded doping profile is usually difficult to realize. The reduced total boron doping
concentration in the base region due to the grading will greatly increase the base-sheet
resistance.
As a result, a high-level uniformly doped (box-type) boron profile is
favorable for the device overall performance.
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19
The collector charging delay r c can be expressed as
IrT
r c = (—
q lc
IrT
+ R e + R c )C bc = (—
F
A
+ r e + r c )^L -K L ,
q lc
(2.7)
Wc
where R e and R c are the emitter and collector resistance, respectively.
Cbc is base-
collector junction capacitance, A bc is base-collector junction area and Wc is the depleted
thickness of collector layer. A small collector-charging delay t c can be achieved with a
high collector current Ic, small parasitic emitter and collector resistance R e and Rc as well
as a small base-collector junction capacitance Cbc• According to Eq. 2.7, a high collector
current is favored for high-speed operation (only favorable for fir). Smaller R e and Rc can
be realized with a thin and highly doped emitter cap layer since the current flows
vertically through this layer. A high doping concentration on the emitter surface also
benefits the ohmic contact. The higher is the doping concentration in this layer, the
smaller series resistance can be resulted and the upper limit usually depends on the
growth capability. For a self-aligned base-emitter contact, this emitter cap layer should
be made extra thick in order to avoid the possible electrical shorts between emitter metal
and base metal. For mesa-type SiGe HBT process, collector contacts are made on highly
doped subcollector layers. These collector contacts are usually made by the sides of the
base mesas resulting in lateral current transport from these contacts to the mesa area. As
a result, the subcollector layer has to be made reasonably thick to reduce the parasitic
collector resistance. If the subcollector layer is made too thick, the step coverage can be
a problem for a double-mesa type process. The reduction of the base-collector junction
capacitance will be discussed in the final discussion offmax.
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20
The last time delay term in r EC is
tcscl .
This term, assuming the collector layer
is fully depleted, which is usually the case for power HBT operation, can be expressed as:
^
c scl
~
Wc
2 v
s
(2 -8)
~ C
According to Eq. 2.8, if speed (mainly for a high fi- value) is the only consideration in
device design, a smaller collector width is always favorable since the carriers are always
made to drift at their saturation speed (~ lx l0 7 cm/s for electrons drifting in Si) across the
fully depleted collector region. For power HBTs,
major fraction of the total time delay
t ec .
t cscl
(-0.8 psec for 0.8 jim of Wc) is a
Since fmax (Eq. 2.3) is the most important
parameter for evaluating device speed characteristics for power applications, base
resistance R b and base-collector junction capacitance Cbc also have to be well considered.
R b can be most efficiently reduced by increasing the base doping concentration.
The mobility reduction resulted from the heavy base doping can be far more compensated
by increased carrier concentration. Hence, practically the highest doping level is always
preferred and it is usually determined by the growth capability. A high base doping
concentration can also prevent device from punch-through and improve the Early voltage.
Both improvements are advantageous for high power applications. With a high base
doping concentration, the base layer can be made very thin without resulting in too large
sheet resistivity and thus the base diffusion transit delay r B can be made very small (Eq.
2.6).
Due to the high diffusivity of boron atoms, boron outdiffusion is frequently
observed during epitaxial growth and high-temperature device fabrication.
To
accommodate the boron outdiffusion, a SiGe spacer layer is usually added on each side of
the highly doped base layer during device design. These two spacers are undoped during
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21
growth and should become part of the base region after the devices are out of the
fabrication facility. In double-mesa type SiGe/Si HBTs SiGe layer is usually used for an
etch-stop to expose the base layer. If an undoped or low-doped SiGe spacer layer is still
present after base exposure, a very high base resistance R b will be resulted from high
base contact resistance. From this inference slight boron outdiffusion at the base emitter
side is favorable for a good base ohmic contact based on the fact that a sharp boron edge
can never be obtained from any growth technologies. In the other extreme case, if severe
boron outdiffusion occurs near the base-emitter and/or base-collector heterojunctions
parasitic energy barriers will be formed and device performance will be substantially
degraded. As a consequence, the thickness of the two-spacer layers has to be very
carefully determined based on the base layer thickness, base doping concentration, the
adjacent emitter and collector doping concentrations and the growth temperature. Higher
base doping concentration and higher growth temperatures will result in longer
outdiffusion tails and the spacer layer thickness has to be made larger. The emitter
doping concentration is usually 2-3 orders higher than collector.
As a result, a
symmetrical boron outdiffusion will result unsymmetrical base widening on the two sides
o f the base region. However, the formation the parasitic energy barrier is mainly due to
the band gap difference between Si and SiGe alloy. To accommodate boron outdiffusion
on both sides of the base region, unsymmetrical spacer thickness is usually used in high
speed SiGe/Si HBTs. The definition of the Si/SiGe heterojunction interface have crucial
influence on the device RF characteristics, it is rather a growth fine-tuning issue than a
pure design issue.
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22
From the viewpoint of heterostructure design, Cbc can be reduced by increasing
the depleted collector thickness Wc (Eq. 2.7). Because the collector layer thickness is
chosen such that it is fully depleted under typical bias conditions, a larger Wc can only be
obtained with a lower doping concentration. This requirement is contradictory to the
requirement of a high collector current Ic, which is needed in Eq. 2.4 and Eq. 2.7, and is
also contradictory to Eq. 2.8, where a smaller Wc is preferred. To fully examine the
dependence of fmax on Wc, Eq. 2.1, 2.2, 2.4, 2.6, 2.7 and 2.8 are substituted into Eq. 2.3
and the following expression can be obtained:
f
= ( ---- — ---- ) 2
Jtm
8 tjR bC bc
BC
f
(
(2.9)
=v
(16jCzR bB£SiA
BC( ^+ Ts- + £ W
* ^2 ( ^ L + R E£ + R cc/) + - L ))"7
5, acv
From this formula, with a fixed collect current Ic, a thick and fully depleted collector is
favorable for a larger fmax. The experimental verification of this trend (fmax vs. Wc) can be
found in Ref. 1.
The considerations of heterostructure design for achieving high power handling
capability is now discussed. As mentioned above, high power delivery can be obtained
either with a high operation voltage combined with a low current density or vice versa. A
high current density can result in low breakdown voltage and cause thermal instability
problem. A common phenomenon observed in such devices is the collector current (or
DC current gain) crash at high bias levels. Since power HBTs are usually operated at
high bias levels for high power-added efficiency, the junction temperature can become
very high if the generated heat cannot be dissipated efficiently. As a result, good thermal
dissipation in power HBT design is an essential consideration for a high power-added
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23
efficiency.
Based on these considerations, heterostructure design with a low current
density operation (the extent is also affected by the layout as discussed in Section 2.2.2)
is favored for high-efficiency power HBTs. It also offers the advantage of better output
linearity. The high power needed from a single HBT can be obtained by increasing the
device area. The highest current density that an HBT can handle is mainly determined by
the onset of the Kirk effect (JK), which is further determined by the collector doping
concentration (Eq. 2.5). The power HBT design usually begins with an operation voltage
specification.
If this is the case, the open-base collector-emitter breakdown voltage
(BVceo) has to be 2-3 times larger than the specified operation voltage in order to
accommodate the voltage swing of large-signal operation. The breakdown voltage BV ceo
(sustaining voltage) can be expressed as,
BV ceo
(2 . 1 0 )
P~n
where /? is the DC current gain, n is an empirical parameter and BV cbo is the openemitter reverse breakdown voltage of the base-collector junction. This BV cbo value is
mainly determined by the collector doping concentration as it can be seen from the
following (assuming collector layer is fully depleted during operation),
b v cbo
qN cW2
= e cw c - V c— .
2 e*
where E c is the critical electrical field.
(2 -ID
Lower doping concentration offers higher
breakdown voltages and vice versa. The collector thickness is also determined by the
breakdown voltage requirement since lower doping concentration will result in larger
depletion width. Unnecessarily higher breakdown voltages should be avoided because
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24
larger collector thickness will be needed and larger
t cscl
will be caused. Overall, the
collector design has more profound influence on the HBT power performance than other
layers of the heterostructure,
hi practice, an optimization of the collector layer
parameters has to be made in order to achieve high performance for a power HBT.
Based on these considerations, several heterostructures have been investigated,
from some of which the state-of-the-art power performance of SiGe/Si HBTs has been
obtained. The two nominal structures with all the layer parameters are listed in Figure
2.1 and the measured SIMS profiles of these two structures are shown in Figure 2.2 (a)
and (c). Figure 2.2 (b) and (d) are the detailed base- and emitter- analysis profiles of the
HBT_1 and HBT_2, respectively. Both structures were grown in one step by CVD on 4”
high-resistivity wafers. The measured substrate resistivity is about ~104 Q-cm, which is
sufficiently high for the suppression of the dielectric loss in the monolithically-integrated
passive components and transmission lines for f < 10 GHz. HBT_1 has a thinner emitter
cap layer than HBT_2. Both the base doping concentration (Figure 2.2 (a) and (b),
2.5xl0 1 9 cm'3) and the Ge composition (21%) in the base layer o f HBT_1 are lower than
those of HBT_2 (Figure 2.2 (c) and (d), 8x10 1 9 cm ' 3 and 25%, respectively).
The
thickness of the SiGe layer of HBT_1 is 32.5 nm (FWHM) and that of HBT_2 is 21.5 nm
(FWHM). The average collector doping concentration of HBT_1 is about 4x10 1 6 cm ' 3
and that of HBT_2 is about 3xl0 1 6 cm'3. The collector thickness of HBT_2 is also
smaller than that of HBT_1. Most of these differences between these two structures
prophesy a better performance from HBT_2 than that from HBT_1, based on the above
considerations. During the study course, HBT_2 structure is a further modification of
HBT_1. The use of a thicker emitter cap layer in HBT_2 than HBT_1 is mainly for the
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25
purpose of the process yield. Both Figure 2.2 (b) and (d) show a long boron doping tail
near the base-collector junctions. This apparent “boron outdiffusion” is due to the SIMS
analysis ions, Cs. Because the mass of a Cs+ ion is too much heavier than that of boron
atoms, the boron doping profile has been tortured. Oxygen ions should be used to obtain
a more accurate boron profile. The up-slope profile in the collector layer toward the
subcollector layer is due to phosphor diffusion during growth. This profile will not have
adverse effects on the device performance. Another up-slope in the emitter layer toward
the base region is a growth artifact, which may reduce the base-emitter reverse
breakdown voltage of an HBT. Higher doping concentrations in the emitter cap layer and
the subcollector layer and higher Ge composition in the base region were desired before
the structure growth. However, all of them are limited by the CVD growth capability.
2.2.2
Layout Design
The power HBT performance also strongly depends on the layout design.
A
proper device layout can maintain high performance of RF characteristics while
delivering high output power with associated high power-added efficiency.
The design
of the layout is to properly choose the lateral dimensions in order to maximize both the
RF and the power performance. For a multi-finger power HBT, the layout parameters
include finger width, finger length, finger spacing and arrangement, the number of the
emitter fingers. The considerations of these performance-related parameters and other
layout parameters are discussed below.
Finger Width: Large emitter area is required for power HBTs to deliver high output
power and high-level injection is the power device operation state in most applications.
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26
Emitter cap
Si
n+
P
2 x l0 19cm'3
100 nm
Emitter
Si
n
P
lxlO I8cm'3
100 nm
Spacer
^*0.75^e0.25
i
Base
^*0.75^e0.25
P+
Spacer
S*0.75^e0.25
i
Collector
Si
n-
P
4 x l0 16cm-3
500 nm
Sub-collector
Si
n+
P
2 x l0 19cm'3
1000 nm
Si(100)
P-
lxlO I2cm'3
540 (im : =
- Substrate
5 nm
B
5xlOI9cm'3
20 nm
5 nm
(a)
Emitter cap
Si
n+
P
2 x l0 19cm'3
150 nm
Emitter
Si
n
P
lx l0 I8cm'3
100 nm
Spacer
S*0.75^*e0.25
i
Base
^*0.75^e0.25
P+
Spacer
Sio.7s^eoas
i
Collector
Si
n-
P
3x1016cm'3
500 nm
Sub-collector
Si
n+
P
2 x l0 19cm'3
1000 nm
Si(100)
P-
lxlOI2cm'3
540 pm :
s Substrate
5 nm
B
lx l0 2°cm'3
20 nm
5 nm
(b)
Figure 2.1: Epitaxial structure of the X-band power SiGe/Si HBTs: (a) HBT_1; (b)
HBT_2. All the values are designed values.
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27
3)
1020
Concentration (atoms/cm
20
15 .—.
E
o
10 16
0)
4x10 16- 5 O
0
in
E
.o
CO 1019
E
o
to 1018
co
to 1017
c
C
oD 1016
c
o
o
r
Depth (nm)
Concentration (atoms/cc)
(a)
400
(b)
1Q20
25
Ge
100 200 300
Depth (nm)
E
o
10 CD
o
1016
0
400 800 1200 1600
Depth (nm)
(c)
0
100 200 300
Depth (nm)
400
(d)
Figure 2.2: Measured SIMS profiles of the CVD grown X-band power SiGe/Si HBTs :
(a) HBT_1 showing the complete structure; (b) HBT_1 with a detailed
analysis o f the emitter and base layers; (c) HBT_2 showing the complete
structure; (d) HBT_2 with a detailed analysis of the emitter and base layers.
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28
At high-level injection, the voltage drop from the edge to the center of the emitter pad,
due to base sheet resistance, will reduce the voltage available to the center area of the
emitter and, hence, the overall emitter injection efficiency (or the effective emitter area)
will be substantially reduced. This phenomenon is called (lateral) emitter current
crowding effect.
The reduced emitter injection efficiency will reduce the available
collector current Ic and leave unnecessary large intrinsic base-collector junction area
(part of A bc in Eq. 2.7). Both of these two factors will adversely affect the device speed.
To reduce the emitter current crowding effect, the emitter width has to be reduced such
that the voltage drop from the edge to the center of the emitter stripe is below the thermal
kT
voltage ( — ~ 2 6 m V ). The power HBT’s requirement of a large emitter area is then
q
satisfied with multiple emitter stripes (fingers). The selection o f the emitter finger width
is determined by the base current level and the base layer sheet resistance. The smaller is
the width, the higher is the emitter injection efficiency and the smaller C bc- In most
cases, the smallest emitter finger width is limited by the photolithography resolution.
Finger Length: The longer is the emitter finger length, the higher power can a single
emitter finger deliver. However, the maximum length of the emitter fingers is limited by
the longitudinal current crowding effect, which is similar to the lateral current crowding
effect as mentioned above. This current crowding effect arises from the limited electrical
conductivity of the emitter metal stripes. The voltage drop along an emitter finger due to
the metal resistance causes lower available voltage at the end of the emitter finger than
that available at the current feeding point. Again the emitter injection efficiency will be
adversely affected in this case. As a rule of thumb, the voltage drop along an emitter
length should also be less than the thermal voltage, -26 mV, in order to maintain a
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29
comparable current density along the emitter. The finger length is determined by finger
width, current flow, emitter metal thickness and the metal conductivity.
Finger Spacing and Arrangement: In order to reduce base access resistance (part of R b),
self-aligned base metallization scheme has been used in modem mesa-type HBTs. For
these self-aligned base-emitter structures, the emitter finger spacing is essentially the base
metal width. Increasing the finger spacing will reduce the base resistance, but increase
the base-collector junction capacitance {C bc)- On the other hand, the finger spacing
should not be reduced such that it is less than two (base) transfer lengths (2 lt), which is
expressed as,
(2. 12)
where p c is the base contact resistance and pSh is the base layer sheet resistance. The
transfer length is a distance across which the base current density reduces to 1 /e of the
value at the base metal edge. pc and pSh are strongly dependent on the base doping
concentration and, hence, the selection of the finger spacing should be based on the
measured p c and base doping concentration. A finger spacing, which is smaller than 2/f,
will sacrifice the device performance.
Heat dissipation is another consideration for
layout design and this consideration is crucially important for high power HBTs, in which
substantial heat will be generated during operation.
Due to the heat generation, the
junction temperature in the center of the device is higher than that at the edges. The nonuniform temperature distribution deteriorates the power performance by rendering the
center part of the device useless for high power operation. The heat generation can be
reduced by using a lightly doped collector such that the current density is reduced, as
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30
discussed in Section 2.2.1. From the layout design point o f view, the heat dissipation
within the device can be improved with a distributed layout, i.e., physically increase the
device area. However, increasing finger spacing (base metal width) will result in larger
C bc- A compromise can be made by dividing all the emitter fingers into several subcells,
in each of which several fingers with narrow finger spacing (slightly larger than 2 lt) are
bound together and collector metal stripes are inserted in between two subcells. This
configuration can reduce thermal effects without increasing C bc, but with the extra
advantage of decreased collector spreading resistance. The number of emitter fingers that
can be bound in a subcell depends on the junction temperature requirement for the
device. Less severe heat accumulation within the device can allow more number of
emitter fingers to be bound together. The minimum width of the collector metal stripes
should be at least equal to two (collector) transfer lengths, which can be calculated with
Eq. 12 with the parameters of the collector layer. The maximum width can be determined
based to on the thermal dissipation requirement. This layout scheme is illustrated in
Figure 2.3.
The Num ber o f Emitter Fingers: The total number of emitter fingers determines the
highest output power that a device can deliver. However, it is not simply a “the more, the
better” situation. The maximum number of emitter fingers is limited by the device
maximum spreading width, above which microwave signal can be severely out of phase.
In addition, power HBTs require input and output matching circuits for desired power
performance when they are implemented in power amplifier circuits. Very large HBTs
have extremely low input and output impedance. Due to the difficulty of matching for
these HBTs, a high output power is still not available regardless the large size the HBTs.
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31
Collector
Base
Emitter
(a)
Emitter
Subcollector
CollectorBase
Emitter
(c)
Figure 2.3: Layout considerations for SiGe power HBT design: (a) a compact layout in
which all emitter fingers are bound together.
This layout leads to high
temperature rise in the center area; (b) significant voltage drop for many
finger devices due to the high spreading collector resistance;
(c) a non­
compact layout with two emitter fingers bound together in a subcell.
Collector spreading resistance is reduced and thermal effects are suppressed
to an acceptable level.
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Other Layout Parameters: To connect the active device with other components in a
circuit and for measurement purposes, interconnect thin film metal layers are required in
the device layout design. Proper connect technology (air bridge or vial hole) also has to
be well selected. Some design rules may be set in order to obtain a high process yield
and to ease the fabrication process. For example, in the process of a double-mesa type
high power HBT that has a thick collector layer, the step coverage of the interconnect
metal can be jeopardized unless this metal is made extremely thick (the amount and the
cost of gold can be too much, lift off can also be difficult). This process problem can be
easily solved at the design stage by making two etching masks of different size such that
two steps can be obtained after proper etching (e.g., base mesa and isolation etching).
Air-bridge connect technology offers low parasitic capacitance, which is favorable for
very high frequency operation, but with handling difficulty and poor yield. Via hole is
another connect option, which is more fabricative and of high yield but with more
parasitic inductance. If the via holes are made in the active device area, the overall
emitter injection efficiency can be reduced. The size of the via holes also affects the
device performance in addition to process yield.
Based on the considerations for the layout design, the layout of a typical high
performance X-band HBT (common-base configuration) is shown in Figure 2.4. Only
six fingers were drawn for a clear illustration of all the lateral dimensions. In this layout,
the emitter finger width is 2 |im, finger length is 30 |im, the finger spacing is 2 pm and
there are 2 fingers in each subcell. The two fingers are joined together at the end of the
fingers to form a 6 x 6 pm 2 square area, on which emitter via holes (2.5x2.5 pm2) are
made for the contacts. As a result, the actual emitter area in each subcell is 156 pm2.
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33
E m itte r
T
r
C o lle c to r
Figure 2.4: Layout of a 6 -finger (each of size 2x30 pm2) common-base HBT showing the
distributed feature.
The subcell spacing was designed to be 10 (xm, leading to a junction temperature increase
in the device center area within the acceptable range according to thermal calculation.
The width of the collector metal stripe is
8
pm and there is 1 pm distance between the
base mesa and the collector metal strip to tolerate the alignment error. The collector
metal forms an inter-digitated structure, at the joint end of which large contact via holes
are opened. Via holes are also opened on the base metal, which are connected together
by interconnect metallization.
The layout of the interconnect layer is designed to
minimize the parasitic capacitance.
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34
2.3 FABRICATION PROCESS OF DOUBLE-MESA TYPE SiGe/Si HBT’S
In this section, the fabrication process is described with emphasis on the key
techniques and experience. The initial process development has been detailed in Ref. 22.
This double-mesa type process is an adoption of the typical mesa-type HBT process for
m -V semiconductors, which is different from the SiGe planar BiCMOS process initiated
by IBM. The high-temperature process employed by IBM has some restrictions on the
device parameter change, e.g., the Ge composition in the base region has to be kept low
(around 10%) to avoid generating any dislocations. The double-mesa type SiGe/Si HBT
process used in this study offers plenty of room for experimentation and all process steps
can be accomplished in the Solid-State Electronics Laboratory at the University of
Michigan. The process consists of seven mask levels and nine steps. These process steps
are described below.
In order to achieve high processing success, the following
procedures (besides any procedures for each lab machine) were stricdy followed during
fabrication process: For every pattern transfer step both the edge removal mask and
device mask were thoroughly cleaned in order to extend the mask lifetime and to
maintain a high process yield. After spinning photoresist (PR), visual inspection of the
PR surface quality was performed.
For each of the following pattern transfer steps
discussed below, edge removal lithography was performed (30 sec UV light exposure @
20 mW/cm2) followed by 1 min developing. For all the processing steps involved, the
PR thickness, deposited metal thickness and etching depth were always tracked. This can
be accomplished with a Dektak profiler. A proper use of the profiler can keep a depth
resolution of up to 2-5 nm. A curve tracer and a probe station were frequently used to
track of the electrical characteristics of the test devices/patterns on the wafer and also
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35
were used to verify the etching depth with the assistance of the measured SIMS profiles.
A dummy-etching run was performed before any dry etching was performed on device
wafers. The time of the dummy run was set based on the estimated time for a real run
since the etching rate is not constant with etching depth.
1
min O2 plasma de-scumming
was followed after final developing. Oxide etching was always performed right before
the wafer was loaded into chamber for ohmic contact metal evaporation. Microscope
final inspection on PR patterns was performed before a wafer is loaded into vacuum
chamber for etching or deposition.
Hot PRS 2000 PR stripper was used for all lift-off,
PR removal steps. To compensate the lab condition changes, detailed notes were taken
for future reference and debugging process problems.
Emitter Metal (M ask #1)\ This is the first processing step. In this step, emitter metal is
deposited and all align key patterns used for later pattern transfer steps are also deposited.
After wafer cleaning (immersion in acetone and then IP A), oxide removal (30 sec of BHF
etching) and dehydration at 130 °C for 2 min, HMDS adhesion promoter and AZ 5314E
photoresist are spun at 4.5 krmp for 30 sec. After 1 min bake at 105 °C, edge removal is
performed. The alignment objective of this step is to align the grid lines of the mask with
the major direction of wafer at about 45 degree so that a vertical emitter profile can be
obtained during base exposure. The contact distance between the wafer and the mask
during alignment has to be even close for all four comers. It can be inspected from the
pattern formation of the Newton rings when the wafer is brought close enough to the
mask. If this situation cannot be achieved, elongated patterns across the wafer will be
resulted and the alignment of the following layers with this layer can become difficult.
The photolithography of this step is a standard image reversal process: Pre-exposure of
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36
3.5 sec @ 20 mW/cm2, followed by post bake o f lmin at 130 °C and 90 sec flood
exposure @ 20 mW/cm2. After developing in AZ 327 developer for 35 seconds, the PR
pattern is finished. In this photolithography, pre-exposure defines the pattern and its
timing is crucially important.
Longer pre-exposure time (4.5 sec is too long), more
diffraction will be resulted and after the image reversal, the pattern edges cannot be made
very sharp after lift-off. The evaporated emitter metal is Cr/Au (500/2500 A). Cr is used
for good adhesion and for good N-type ohmic contact. Since Cr is not melted during ebeam evaporation, refilling Cr source is always performed to obtain pure Cr thin films.
No RTA is needed since the doping concentration of the emitter cap layer is high enough
to induce carrier tunneling for a good ohmic contact.
Emitter M esa: This step and the next are the two most critical steps in the fabrication of
SiGe/Si HBT. The success of these two steps largely determines the success of the whole
process run. The purpose of this step is to fully expose the highly doped SiGe base
surface while maintaining minimum undercut beneath the emitter metal. Two etching
steps were employed to expose the base. Reactive ion etching (REE) was used to remove
2/3 or 3/4 of the total emitter thickness (including emitter cap and emitter in Figure 2.1).
The amount to be removed (2/3 or 3/4) in this RIE step depends on the total emitter
thickness. The rest portion to be removed by KOH etching should be around 70-75 nm.
This amount of Si remained is used to protect the SiGe base layer from RIE damage and
also used to monitor the KOH etching process.
This small amount of Si remained
ensures a small undercut beneath the emitter metal, hence, ensures a small base resistance
Rb. The RIE etching rate has to be WELL calibrated (using the method mentioned above,
0.1 min makes difference) to avoid hazardous over-etching of the emitter. The recipe for
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37
this RIE etching is: SF6 flow of 20 seem, O2 flow of 3 seem, 65 W RF power and change
pressure 20m torr->5 mtorr once plasma is started and RF power becomes steady. Due to
the low etching pressure, virtually no undercut should be resulted up to this step. After
the proper RIE etching, the SiGe base layer needs to be exposed with KOH wet selective
etching.
From the processing experience it is known that this base exposure step is
extremely sensitive to contaminations, which are frequently encountered in a multi-user
based processing lab. Precautions were taken in this step: a set of beakers, thermometers
and handling tools were used exclusively for this process from the very beginning o f this
study; new gloves, new BHF and KOH solution were used for each wet etching run and
DI water was made sure to be of high quality (resistivity -18.93 Mfl-cm). It is found that
the temperature of the KOH solution is the single most parameter for this step to be made
reliable, repeatable and controllable. KOH was made with 50 g of KOH pellets and 200
ml DI water in a 1000 ml beaker.
Heat will be generated when KOH pellets were
dissolving in water. The temperature can be monitored with a thermometer. During the
cooling time (from -58 -6 0 °C), a 30-sec BHF oxide etch can be performed followed by
DI rinsing. The best temperature of KOH solution was found to be 40-42 °C. In this
temperature range, no etching delay or SiGe over etching was ever observed. Before the
KOH solution reached this temperature range, the sample was kept in DI water to avoid
the growth of native oxide, or the wet etching process was not controllable. The cooling
process can be speeded up by stirring.
Once the KOH solution reached the desired
temperature range, the sample, while being covered with DI water, was quickly moved
into KOH solution and timing was started at the same time. Bubbling was observed
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38
coming from the backside of the wafer, indicating the reaction of KOH with Si. A close
watch was performed on the front surface of the wafer. During the etching, tiny bubbling
(most observable from the pattern grid lines) and/or color changing (thickness changing)
were observed depending on emitter growth condition.
In MBE- (CVD-) grown
structures, color change (bubbling) was usually observed.
The etching process was
stopped at the SiGe layer when no more bubbling or color changing from the wafer
surface. The etching rate at this temperature was estimated to be 85-90 nm/min. It took
about 60 sec to remove 70 nm Si after RIE etching. Another equal time (60 sec in this
case) was used to over etch SiGe layer.
It was found that for some of the SiGe/Si
heterostructures this over-etching step helped to improve base contact resistance. This
over etching also increases the undercut to a safer level. The undercut of up to 0.15-0.16
pm on each side the emitter metal can be reliably repeated using this process. For the
emitter metal width of 2 pm, the Si emitter width can be made ~ 84-85% of the emitter
metal width so that the base access resistance can be effectively reduced. The exposed
highly P-type doped SiGe layer was verified by measuring the surface conductivity and
two-isolated emitter metal pads. The surface should be very conductive and the back-toback diode characteristics should be steadily observed.
Base M etal (Mask #2): The objective of this step is to deposit base metal on the exposed
SiGe layer. A low contact resistance is absolutely required for high performance HBT.
The surface and the deposited base metal have to be free of any contamination.
The
indication of contamination is high base contact resistance. It can be tested with curve
tracer and needle probes.
In the contamination-free case, the electrical conductivity
between two base metal pads should be of very low resistance and a vast improvement
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39
over the conductivity when probing the bare SiGe surface. The test diode should show
very low resistance after tum-on.
In the contaminated case, no such improvement or
even degradation can be observed and RTA of any allowable time was not able to cure
the problem.
The mechanism responsible for this degradation could be due to the
contaminant induced band-bending change such that free holes for tunneling are lacking
at the SiGe surface. To avoid the possibility of contamination, base metal deposition on
dummy SiGe layer was made right before the deposition of base metal on real wafers.
The base metal used was Ti/Pt/Au with 100/200 A Ti/Pt and variable thickness of Au
depending upon the total Si emitter thickness. Half of this emitter thickness was used for
base metal thickness to minimize the chance of electrical shorts between the self-aligned
base-emitter metal structure. The recipe for base metal photolithography and evaporation
is the same as that for emitter metal. The adhesion of the base metal on SiGe layer is
much poorer than the emitter metal on Si. The surface of SiGe layer has to be free of any
PR residue.
Base Mesa (Mask #3): This step is to cover the base-emitter area with PR SC1827 while
etching down other area to the subcollector layer with RIE. Base mesa was intentionally
designed to be slightly smaller than base metal so that the base-collector junction area
(thus C bc) can be minimized. The photolithography recipe, after edge removal, is: spin
PR SC1827 @4.5 kprm for 30 sec, pre-bake @ 105 °C for 2 min, align and expose for 10
sec @20 mW/cm2, develop in MICROPOSIT:DI =1:5 solution for 40-45 sec depending
on the time during which PR on the wafer surface is completely dissolved from visual
inspection. An extended developing time of 10-12 sec after that time point gave the best
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40
developing result.
The RIE recipe is the same as that for emitter mesa.
After
subcollector layer is exposed, the surface becomes very conductive.
Collector M etal (Mask #4): This step is to evaporate collector metal, Ti/Pt/Au
(200/300/2000 A) on the subcollector layer. The recipe for this step is: spin PR 1813
twice @3.5 krpm for 30 sec, pre-bake @80 °C for 100 sec (extend to 120 sec for high
humidity environment), immersion into chlorobenzene for 5.5 min, edge removal and
develop, align and expose 6.5 sec @20 mW/cm2, develop in MICROPOSIT:DI =1:5
solution for 42 sec. Test device was then measured for I-V characteristics.
Device Isolation (Mask #5): In this step, active devices are isolated with deep RIE while
protecting the active device area with thick PR SC1827. The photolithography and RIE
recipes are the same as those for the base mesa step. Once the substrate is exposed, high
surface breakdown voltage should be measured.
Passivation: This step is to passivate the active device and form the insulating layer for
interconnect m e tallization.
Adhesion on metal surface is important to make reliable
insulation layer. After PR stripping in the last step, the surface was cleaned with O 2
plasma ashing @ 150 W for 3 min, in order to remove any organic residues on the sample
surface. 1 jim S i0 2 was then deposited using plasma-enhanced CVD system. The recipe
for this deposition is:
SLH 4
flow of 24 seem, NoO flow of 20 seem, RF power of 80 W,
pressure of 100 mtorr and the temperature if 200 °C. 60-62 minutes was needed to
deposit ~1 mm Si02.
Via Holes Opening (Mask #6): This step is to open via holes on the deposited S i0 2 film.
The photolithography for this step is the same as that for device isolation, except that the
PR dissolving process cannot be seen during developing since the PR that needs to be
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41
removed is little. 42 sec developing generated proper size of via hole openings. The
recipe for this RIE is: 25 seem flow for both CF4 and CHF3 . RF power of 183 W and
pressure of 40 mtorr. The etching rate is ~ 28 nm/min. An over etching time o f 5-8 min
was used to compensate the non-uniformity of SiOi film and to ensure full opening of all
the via holes. The full opening o f the via holes can be verified by probing the exposed
metal surface (showing electrical shorts) in the large opening areas and/or by measuring
the SiC>2 thickness (showing error if completely etched away) in the pre-designed test
area.
Interconnect Metallization (M ask #7)\ This is the final step which deposits the
interconnect metal and provides connection between electrodes and probing pads.
A
thick metal, Ti/Al/Ti/Au (500/14000/500/4000 A), is required to reduce the parasitic
resistance. The recipe for this step is: spin PR 1827 @3.25 krpm for 30 sec, pre-bake
@80 °C for 100 sec, immersion into chlorobenzene for 5.5 min, edge removal and
develop, align and expose 10 sec @20 mW/cm2, develop in MICROPOSIT:DI =1:5
solution for 42 sec.
With chlorobenzene treatment, overhang pattern edge profile was
successfully created and the lift-off process for this thick metal layer was greatly eased.
After the interconnect formation, the devices are ready for measurement and
characterization. The schematic of the process flow is shown in Figure 2.5 and the SEM
micrographs of finished 10-finger HBTs are shown in Figure 2.6.
2.4
SUMMARY
In this chapter, design considerations for both transistor heterostructure and layout
of SiGe/Si power HBTs are discussed in terms of high-speed operation and high-power
handling capability. It is concluded that a thick and lightly doped collector layer is
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42
1. Emitter contact
2. Emitter mesa
p+Si 1_xGex Base
Si Substrate
3. Base contact
4. Base mesa
7:' Y'
5. Collector contact
and isolation
x
:7:7-7 7:7:7: Am
6. SiCX,, via, and
interconnect
Interconnect
Figure 2.5: Fabrication flow of double-mesa type Si/SiGe/Si HBTs
favorable for both high-speed and high-power operation. Employing a high operating
voltage combined with a low current density is more beneficial than employing a low
operation voltage combined with a high current density. A distributed layout renders
lower junction temperature operation, which is required for high-efficiency power
amplification. Based on these considerations, two heterostructures were designed and
grown by one-step CVD and a distributed layout was resulted. The double-mesa type
SiGe/Si process was described with the emphasis on the techniques for achieving high
performance and high process yield.
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43
(b)
Figure 2.6: Photomicrographs of the fabricated 10-finger SiGe/Si power HBTs:
(a) Common-emitter configuration; (b) Common-base configuration.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER HI
DC, SMALL- AND LARGE-SIGNAL CHARACTERISTICS
OF X-BAND (8.4 GHz) NPN SiGe/Si POWER HBT’S
3.1
INTRODUCTION
A prevailing concern with the SiGe material system has been its potential to
realize efficient power amplifiers, which are crucial circuit components of RF/microwave
transmitters. The performance of the power SiGe/Si HBT is the most determinant factor
for an efficient power amplifier. However, since the demonstration of the highest fmax in
a SiGe HBT [1], the investigation and development of SiGe microwave power HBTs
have only received limited attention. Efforts on the microwave power application of
SiGe-based HBTs have so far been limited to L- [23] [24], S- [25] [26], and C-band [27]
operations. The demand for higher channel capacity in wireless communication will
naturally drive the wireless operation frequency to X-band and the reported performance
characteristics of SiGe HBTs [28] [29] operating in this band are rather limited.
Therefore, there is a need for more device characterization for SiGe-HBTs to be a
contender for X-band wireless communications. A drawback in the development of Xband power SiGe HBTs, arising from the -6dB/octave power gain reduction for smallsignal operation and additional gain compression for large-signal operation, is that high
output power can only be obtained at the cost of low power gain [28] and vice versa [29].
44
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
45
Nevertheless, a high output power with concurrent high power gain (hence PAE at a
certain class o f operation) is always required for the implementation of efficient power
amplifiers. To achieve this goal, the heterostructure and the device layout have to be well
designed with considerations of thermal effects, breakdown voltage, fnax and output
power, etc. These considerations have been discussed in Chapter II. Using the fabrication
technology described in Chapter n , double-mesa type NPN Si/Sio.7 5 Geoj>5 /Si power HBTs
were successfully fabricated with high process yield and good repeatability in the SolidState Electronics Laboratory at the University of Michigan.
In this chapter, the DC,
small- and large-signal characteristics of these power HBTs will be discussed.
The
individual power HBTs made from heterostructure HBT_1 and HBT_2 (Figure 2.1 and
Figure 2.2) demonstrated the state-of-the-art power performance among SiGe-based
HBTs. The device characteristics based on structure HBT_2 is presented in this chapter.
In what follows, the device DC characteristics will be discussed in Section 3.2, the smallsignal RF performance will be described in Section 3.3 and the large-signal performance
will be detailed in Section 3.4, followed by a summary in Section 3.5.
3.2
DC CHARACTERISTICS
Device DC characteristics are directly related to the RF characteristics.
The
analysis of DC characteristics can provide feedback to device design and help to predict
the limitations in RF performance. In this section, the DC characteristics of SiGe/Si
HBTs fabricated from structure HBT_2 will be described in detail. Their relationship
with RF performance will also be discussed.
The DC characteristics of the fabricated SiGe/Si HBTs were characterized with an
HP 4145 semiconductor parameter analzer. Figure 3.1 shows the current-voltage (I-V)
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
46
characteristics of 10-finger common-emitter (CE) and common-base (CB) SiGe/Si HBTs
Qayout shown in Fig. 2.6, emitter area A E = 780 (im2).
Higher current levels can be
achieved with these HBTs and the highest current level, 100 mA, as shown in Figure 3.1
is the upper limit of the HP 4145 semiconductor parameter analzer. The measured basecoUector breakdown voltage (BV cbo) is about 26 V and the open-base collector-emitter
breakdown voltage (BV ceo) is about 23 V (not shown in the curves). No punchthrough
was observed at these voltages. These are the highest breakdown voltages ever achieved
in SiGe-based HBTs. The high breakdown voltages result from the low collector doping
concentration and the high base doping concentration (Figure 2.2(c)), which allow high
applied operation voltages for power amplification and can accommodate large output
signal swing.
High power can then be obtained with large device area.
Another
advantage o f these high breakdown voltages is better linearity of output power.
The offset voltage (VcE,offset) of the CE configuration is measured to be 0.08 V,
which originates from the asymmetry between base-emitter and base-collector junction
diodes. The positive value of VcE,offset indicates that the tum-on voltage of the baseemitter juntion diode is larger than that of the base-collector junction diode. The tum-on
voltage difference comes from the possible band offset difference at the two junctions
and the difference between the emitter and the collector doping concentrations. The
offset voltage is small for the Si/SiGe/Si double heterojuntion structure and is an intrinsic
advantage in terms of the power added efficiency (PAE). The knee (saturation) voltage
(Vknee) o f the CE HBT is only 1.5 V comparing the 23 V of BV ceo, which is attributed to
the reduced collector access resistance from the heterostructure design (thick subcollector
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
47
120
BVcbo —26 V
BVceo = 23 V
100
80
<
e 60
o
40
20
knee
(a)
120
BVcbo = 26 V
BVceo = 23 V
100
Ae = 780 pm2
^E.step =
^ mA
80
60
40
20
0
X
J.
knee
(b)
Figure 3 .1 :1-V characteristics of 10-finger SiGe/Si HBTs (AE = 780 jim2) fabricated from
heterostructure HBTJ2: (a) common-emitter configuration; (b) common-base
configuration. The breakdown voltages are BV cbo = 26 V and BV ceo = 23 V.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
layer) and layout design (1 |±m separation between base mesa and collector metal). The
Kirk effect is apparent in Figure 3.1 (the dotted line), which is due to the low doping
concentration in the collector layer. This effect, which is also called high injection effect
or base push-out effect, mainly occurs at high base-emitter bias and low collector-emitter
bias regime. This is because, in this regime, too many electrons are injected from the
base region into the collector region and the base-collector voltage is too small to
accelerate the carriers to their saturation speed. The accumulated electrons decrease the
space charge density in the collector-side depletion region of the base-collector junction
and the actual base is then widened. The consequence of the Kirk effect is a reduced
collector current level and reduced DC current gain when Ib is high and Vce is low. The
onset of the Kirk effect limits the voltage swing for large-signal operation and then sets
the limitaion of output power and its linearity. No thermal effects were observed in the IV characteristics mainly because of the low doping concentration employed in the
collector region and the distributed layout. The lower current gain at low collector current
levels is due to the base-emitter leakage current in this region. The cause for this high
leakage current will be discussed later.
The offset voltage
( V cb ,offset)
0.6 V. The negtive value of
The magnitude of
V c b ,offset
of the CB configuration was measured to be about -
VcB.offset
is a direct consequence of the CB configuration.
is essentially the reflection of the tum-on voltage of the base-
emitter junction diode. As can be seen from Figure 3.1(b), due to the shift of the I-V
curve to the lower base-collector voltages, the knee voltage, which limits the AC signal
swing, has been further reduced (Vknee — -0.3 V). In addition, a higher Early voltage is
obtained in the CB configuration than in the CE configuration. All these characteristics
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
49
associated with the CB configuration indicate the advantages of employing it for power
applications. Although BV cbo is always larger than BV ceo and a higher Vcb seems to be
applicable, the overall allowable operation voltages (V cb and Veb) for CB HBTs is still
determined by the value of BV ceo■
Since a CB HBT does not have current gain, the common-emitter current gain
P and the differential current gain Afi versus collector current lc for a 10-finger SiGe/Si
HBT, biased at Vce = 7.5 V, were measured and the results are shown in Figure 3.2. Due
to the current limitation of the HOP 4145 Semiconductor Parameter Analyzer, the highest
current gain p and the roll-off of P at high Ic levels were not measured for this
1 0
-emitter
finger device. The largest P was estimated to be in the range of 25-30. The highest
differential current gain AP was, however, measured to be 38.3.
These values are
appropriate for RF applications. In addition, the measurements shown in Figure 3.2 offer
the easiest way to locate the optimum bias points for RF measurements. Although AP
shown in Figure 3.2, to be more precisely defined, is difference gain (AIc/AIb), the
differential limit of this parametric value is the AC current gain. The collector current
region in which the largest values of AP that can be measured is thus the optimum bias
region for RF responsse and this collector current region is the optimum bias region for
both CE and CB RF measurements. Another bias parameter for RF measurements is Vce,
which can be easily found with the measured breakdown voltage, BV ceo• Figure 3.2
shows a broad range (> 50mA), in which the value of AP does not change much. As a
consequence, the best RF resposnse of the device is also available within a large bias
range. Additionally, a relatively large value of AP is available even at very low bias
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50
levels. The availability of high gain at low bias levels signifies the main advantage of
BJT over FET, with which high efficiency power amplifier can be realized.
The forward and reverse Gummel plots are shown in Figure 3.3. The forward
Gummel plot {IB,fand 7c/) shows high base leakage current at low bias levels, which leads
to a forward base ideality factor nB,f o f 2.28. The high base leakage current is commonly
observed in double-mesa type SiGe/Si HBTs, which mainly arises from the non­
coincidence between base-em itter PN junction and Si/SiG e heterojunction and
insufficiently passivated surface states. Since it is usual to operate power HBTs at high
base-emitter bias levels, the non-ideal base current at low bias levels has negligible effect
on large-signal performance. The ideality factor of collector current Nc.f is 1.18. As seen
from the forward Gummel plot, due to the base leakage current at low bias levels high
current gain is only available at high bias levels from these HBTs. The reverse Gummel
plot shows better ideality factors than the forward Gummel plot, with base ideality factor
nBrr-1.18 and emitter ideality factor nBr~ l .2. The smaller nBrthan nB,f is ascribed to the
fact that the base contact is made on the top of the exposed base layer such that the
electron conducting path in the base-collector junction is vertical and the surface
conducting path is minimal compared to the base-emitter junction. Because of the much
lower injection efficiency from the collector, the base current is larger than the emitter
current for all bias levels. The coincidence of Zc/and /£>in Figure 3.3 indicates that the
tum-on voltage of the base-emitter junction diode and that of the base-collector junction
diode are almost equal. If 1 pA is used as the criterion for junctions to be turned on, the
tum-on voltages of these two junction diodes are less than 0.5 V. This small value of
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
51
50
40
ex
30
<
ex
20
20
0
40
60
80
100
lc (mA)
Figure 3.2: DC current gain fi and differential current gain A p vs. collector current Ic for
a 10-finger SiGe/Si HBTs (AE = 780 jim2) fabricated from heterostructure
HBT 2.
10
-!
forward Gummel plot
reverse Gummel plot
•B,r /
'C.f
o
10-5
0.0
B.f
'E,r
0.3
0.9
0.6
VBe & VBC (V)
1.2
1.5
Figure 3.3: Forward (IB.f and /c/) and reverse (/s.r and IE.r) Gummel Plots o f a 10-finger
SiGe/Si HBTs (Ae = 780 jim2) fabricated from heterostructure HBT_2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
52
tum-on voltages is a clear indication that the PN junction resides in the SiGe region since
SiGe has a smaller bandgap than Si.
3.3
SMALL-SIGNAL RF CHARACTERISTICS
In this section, the small-signal RF characteristics of double mesa-type NPN
Si/SiGe/Si power HBTs, fabricated from structure HBT_2, will be discussed in detail.
The small-signal RF performance of the SiGe/Si HBTs with different geometries were
characterized by small-signal S-parameters with an HP 85 IOC network analyzer. The
two figures of merit, f niax and f T (only for CE HBTs), and the stability factors were then
derived from the measured S-parameters. These two parameters were expressed in terms
of device parameters in Chap. 2 (Eq. 2.1 and 2.3).
From measurements, these two
parameters are defined as the frequencies where current gain and power gain,
respectively, reach unity. In the case that fi- and/or
exceed(s) the frequency limit of
the network analyzer (40 G H z),/r and f niax are obtained from the extrapolation of current
gain and power gain, respectively, to 0 dB based on the assumption of - 6 dB/octave roll­
off and one-pole approximation. The current gain can be expressed in terms of Sparameters as,
H 2l= ------------------( l - 5 ll)(l + S22) + 52I5 12
(3.1)
There are two power gain equations, which are frequently used. The Mason unilateral
gain can be expressed as,
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where
K
2|5I25 2[|
and
(3-3)
(3.4)
are two stability factors. The unditional stability condition is K> 1 and zl<l, otherwise the
transistor is potentially unstable. Another power gain is the maximum transducer gain
Gr.max, which can be splitted into the maximum stable gain (MSG),
, when K<1
(3.5a)
(K - V a: 2 - 1 ) , when K>1
(3.5b)
MSG
|S, 2
and the maximum available gain (MAG),
MAG
These two power gain equations (Eq. 3.2 and Eq. 3.5) may give different values of power
gain and thus result in different values offmax- Usually the larger one is cited to represent
the transistor RF performance and it is considered to be reasonable. The physical cause
o f the difference of the power gain values will be discussed later with the measurement
results.
Figure 3.4 shows the RF response of 10-finger CE and CB HBTs under the
optimum bias conditions with Vce = 7 V and I b = 4.9 mA. The CE HBT demonstrates fio f 29.5 GHz and fmax of 40 GHz based on - 6 dB/octave roll-off. Beyond 24 GHz, a —
12dB/octave roll-off is observed, which is due to the 2nd pole generated by large base-
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54
collector junction capacitance C bc- The large size of base-emitter junction area is relative
to the emitter area (intrinsic base-collector junction). The base-collector junction area
Abc for a 10-finger HBT with a distributed layout is larger than that for a compact layout
(all 10 fingers bound togerher) with the same number of emitter fingers.
The ratio
between the intrinsic base-collector junction area and the total junction area Abc is about
0.35 for the distributed layout and that for a 10-finger compact layout is about 0.45. The
MSG/MAG curve beyond 9 GHz does not strictly follow the roll-off of - 6 dB/octave,
which is also because of the 2nd pole generation. The power gain at 8.4 GHz is MSG =
12.4 dB and U = 13.0 dB.
It is noteworthy that the unilateral gain U is larger than
MSG/MAG for the CE HBT. In CE cinfiguration, the input port is base and the output
port is collector. The feedback path from the output port (collector) to the input port
(base) is the base-collector junction capacitance, C bc- Because of the large Cbc, the
power gain represented by U is “exaggerated” relative to that represented by MSG/MAG.
The relationship between the power gain and C bc will be further explained in the
discussion of CB HBT RE response.
The CB HBT demonstrates a higher fmax of 74 GHz based on the extrapolation of
- 6 dB/octave roll-off, which is much larger than that of CE HBT with the same active
area layout. Due to the 2nd pole generated by junction capacitance, the MSG/MAG curve
beyond 31 GHz follows a gain roll-off of -12dB/octave. The MSG below 5 GHz does
not follow -3dB/octave roll-off, which is influenced by the 1st pole, the The power gain
at 8.4 GHz is MAG = 18.9 dB and U = 14.1 dB. The MAG value at 8.4 GHz of CB HBT
is much larger than that of CE HBT, indicating a much better power performance for CB
HBT than CE HBT. Contrary to the RF response of CE HBT, the MSG/MAG values are
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
55
larger than the values of U for almost all the measured frequency range as seen in Figure
3.4(b). The reason which causes a difference in the RF characteristics between CE and
CB HBTs is now analyzed.
In a common-emitter HBT, the feedback path between the output port (collector)
and the input port (base) is Cbc• In CB HBT, the input port is the emitter and the ouput
port is the collector. The feedback path from the output port to the input port is C ec,
which is a series capacitance with C be and C bc■ Since C ec is always smaller than C bc,
the feedback from the output port (collector) to the input port (emitter) for the CB HBT is
smaller than that of the CE HBT. As a result, the MSG/MAG of the CB HBT is larger
than that of the CE HBT. The above reasoning can be easily justified from the cross
section of the fabricated double-mesa type HBT (Fig. 2.5). For CE HBT, the base (input
port) and the collector (output port) are next to each other and, for CB HBT, the the
emitter (input port) is separated by base layer from the collector (output port). Therefore,
the feedback extent is small in CB HBTs than in CE HBTs. In terms of the power gain,
CB HBT is more appropriate for the application of power amplification than CE HBT.
An extended conclusion from the above analysis can be drawn: by comparing the relative
values of MSG/MAG and U for two different devices, the extent of the feedback from the
output port to the input port can be compared. For a BJT, the feedback path is the
capacitance connecting the input port and the output port. Since a CB HBT does not
have current gain, the current gain shown in Figure 3.4(b) is less than 0 dB at low
frequencies. The current gain peak at high frequencies is due to the resonance caused by
the parasitic inductance of the output port and C bc■ The parasitic inductance mainly
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56
25
20
MSG/MAG
A"
15
m
T3
C
O
•6 dB/qctaye
CO
1
10
Frequency (GHz)
100
(a)
25
MSG/MAG
20
S ' 15
2
c
*c0
®
*
10
10
Frequency (GHz)
100
(b)
Figure 3.4: Frequency response of 10-finger (Ae = 780 Jim2) SiGe/Si HBTs showing
current gain and power gain, fi- and fmax are extrapolated based on the
assumption of - 6 dB/octave roll-off: (a) CE HBT; (b) CB HBT.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
57
arises from the interdigitated collector metal of the distributed layout. This phenomenon
has been described by a previous publication.
To determine the amplification characteristics o f the 10-finger CB HBT, the
collector dependence of fmax was measured. The results are shown in Figure 3.5. Due to
the influence of the 1 st pole and the 2 nd pole, the power gain curves do not strictly follow
the - 6 dB/octave roll-off. The values o f fmax shown in Figure 3.5 were calculated from the
power gain value (MAG) at 10 GHz based on - 6 dB/octave roll-off. It is obvious that
there is a large collector current range (over 50 mA) in which the CB HBT shows the best
RF response. The roll-off of fmax, which is due to the Kirk effect, was not measured for
the concern of the device bum-out. It should be pointed out that the the collector current
range, in which the best RF response performance is obtained, matches the one, in which
the largest difference gain is measured (Figure 3.2).
3.4
LARGE-SIGNAL RF CHARACTERISTICS
Small-signal RF characteristics describe the device frequency response at a
certain input power level (Pm), which is small enough to ensure the linear operation of the
device. The device characteristics (Pouf, power gain, efficieny and linearity change) as a
function of Pm, at a certain operation frequency, are the most important characteristics
associated with power devices. Since this type of devices is usually driven up to very
high Pi„ levels (large voltage/current swing) in order to obtain the best performance, these
RF characteristics are called large-signal RF characteristics. Good small-signal RF
characteristics are usually an indication of good large-signal performance. However,
with increasing signal swing, most RF characteristics will be changed and become more
complicated than small-signal characteristics. S-parameters at high input power levels
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
58
100
Ae = 780 pm2
common-base
80
— 40
20
0
50
1 00
150
200
lc (mA)
Figure 3.5: fmax versus collector current Ic for 10-finger (Ae = 780 |im2) SiGe/Si HBTs
fabricated from structure HBT_2.
are no longer useful parameters to characterize the device performance.
The input and
output matching points vary with input level as well as the bias conditions. In addition,
different bias conditions can give very different power performance. In order to find the
best power performance for a power device, the input/output matching, the bias
conditions and the input power level have to be well tuned. Special techniques have been
utilized for large signal characterization, one of which is the source/load pull
measurement technique.
In this measurement setup, two electrical-mechanical tuners
closely connecting the device input and output ports, with a Smith chart representing the
matching point of each tuner, provide a large range (/^o* ~ 0.95) of the input and output
matching.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
59
The multifinger CE and CB SiGe/Si HBTs with different geometries from
structure HBT_2 have been characterized with a Focus Microwave source/load pull
system.
The output power Pout, power gain and the power added efficiency PAE
P -P
( PAE = ——-----—) were measured on wafer as a function of input power Pin at 8.4 GHz
Pdc
under CW mode. No special heat dissipation technique or external ballast resistors were
involved in the measurements. Figure 3.6 shows the power performance of 10-finger CE
and CB HBTs along with the collector current under different bias conditions. When the
CE HBT was biased at Vce = 7 V and Vbe — 1.14 V (class A ) , the linear gain of
was obtained.
8 .8 8
dB
The matching points (JTs = 0.82Z1780 and 71 = 0.57Z1420) were
optimized for maximum Pout. The input matching is very close to the edge of the Smith
chart, indicating the small input impedance. The output power at 1 dB gain compression
point, P-idB is 22.8 dBm.
The peak PAE of 28.2% was achieved at 3.5 dB gain
compression point with a POM of 25.9 dBm. At the quiescent bias point, the collector
current is 62 mA and it was driven to 147 mA at the peak PAE. The power gain at the
peak PAE was measured to be 5.4 dB. The final saturation power was not measured
owing to the DC current limit, which was set to prevent the device from burning out. No
oscillation was observed during measurement.
Sligtly higher peak PAE (29%) was
obtained with the same input and output matching when Vbe was lowered to 1.07 V. The
Pout at the peak PAE is 25.7 dBm, which was obtained at 2.8 dB gain compression. The
collector current at the quiescent point is about 45 mA, which is close to a class AB
operation. Owing to the lower Vbe, a lower linear gain 8.06 dB was resulted. The above
performance features represent the typical behavior of SiGe/Si power HBTs, which can
be summarized as the following. High bias levels (fixed Vce and variable VBe) provide
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60
higher linear gain than low bias levels, but with an earlier gain compression as input
power is increased. However, higher PAE can be obtained at the low bias levels than the
high bias levels. The cause for these features are analyzed.
At the high bias levels (class A or higher), the collector current at the quiescent
point is close to the upper limit of the collector current Ic.max, which is set by the decrease
in the value o f j3 (Kirk effect). As Pin is driven to higher levels the swing o f the output
signal will be quickly limited by the maximum collector current, Ic.max- Because most of
the tuners in a load-pull system are single-tone tuners, a direct consequence of the high
bias levels is an early power gain compression and large output distorsion (not measured
in this work) with the increasing of the input power. Usually, the high bias levels are
used for small-signal (output signal swing is not limited by Ic.max) and high gain
operation, which can be seen in Figure 3.5. As the bias level is lowered, the output signal
swing will be less limited by the collector current and the output power can be driven to
higher level with the increase of the input power.
Therefore, a later power gain
compression with input power, or a flatter gain curve, can be resulted. The high PAE
which can be realized at the low bias levels is due to the low DC power dissipated (low Ic
or smaller conduction angle) while the output signal can reach a large and undistorted
swing.
The lower linear gain at the low bias levels is mainly due to that the smaller
collector current will result in a lower f ir (Eq. 2.1 and 2.3) and thus fmax (Figure 3.5). Since
at the low bias levels the peak PAE can be reached at a lower Pin level, the Pou, at the
peak PAE under the low bias levels is smaller than that under the high bias levels.
The 10-finger CB HBT shows better performance than CE HBT with the same
bias-dependent features. Under Vcb = 7 V and Veb = -1.21 V (class AB), the quiescent
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
61
35
- CE 10-finger on HBT_2
VCe = 7 V
30
I f = 8.4 GHz
CD
45
= 0.82<178°
40
r L = 0.57<142°
35
25
30
■i 20
a
25
PAE
out
Gain
PAE (%), lc (10 mA)
„
rs
15
10
6
8
10
12
14
16
18
20
22
Pin (dBm)
(a)
35
30
25
— ■“
T3
n , = 0.82<178°
r L= 0.67<112°
PAE
40
VEB = -1 .0 6 V
20
out
Gain
20
PAE (%), lc (10 mA)
m
50
CB 10-finger on HBT_2
VCB = 7 V
f = 8.4 GHz
— a — VEB = -1.21 V
10
4
12
8
16
Pin (dBm)
(b)
Figure 3.6: Meaured Pout, Gain, PAE and Ic of 10-finger (a) CE and (b) CB SiGe/Si
HBTs fabricated from structure HBT_2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
62
collector current is 49.4 mA. W ith the input/output matching (/$ = 0.82Z1780 and / I =
0.67Z1120) optimized for maximum output power, 25 dBm was obtained at the peak
PAE of 40.4%. Higher Pout at the peak PAE (will be lower) can be obtained if the bias
levels were set higher. A linear gain of 12 dB was measured and the peak PAE was
achieved at 3.4 dB power gain compression. The associated power gain at the peak PAE
is
8 .6
dB. The high power gain associated with CB HBT has been analyzed in Section
3.3. After Veb is lowered to —1.06 V, with the same matching a peak PAE of 42.1% was
achieved. The Pout at the peak PAE is 24.6 dBm with the associated power gain of 7.1 dB
(3.07 dB gain compression). A more slowly compressed power gain was measured for
Veb =
—1-06 V than for Veb = -1.21 V. It is interesting to note that the best input
matching point for CE HBT and that for CB HBT are the same with different output
matching points. This is because no matter for CE or CB configuration, the input port
and the ground are always base and emitter, which is not the case for the output port and
ground.
The power performance of 20-finger CE and CB HBTs with an identical layout,
based on structure HBT_2, were also characterized on wafer under CW mode at 8.4 GHz.
The input and output matching ( / J = 0.82Z1800 and 71 = 0.71Z1540) was optimized for
the maximum Pout. The Pout, Gain, PAE along with the collector current lc as a function
of Pin are illustrated in Figure 3.7. For the CE 20-finger HBT, under VCe = 7 V and VBe
= 1.08 V (close class AB), 27.4 dBm Pout was obtained at the peak PAE of 26.3%. The
linear power gain is 5.5 dB and it was compressed to 4 dB at the peak PAE. Higher PAE
can be achieved with lower bias levels. Again, much better power performance was
obtained from the 20-finger CB HBTs.
With the optimum input and output matching
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63
40
35
30
m
35
r , = 0.71 <154°
30
f = 8.4 GHz
25
2,
25
out
■§ 20
PAE
CD
20
15
PAE (%), lc (10 mA)
_
r s = 0 .8 2 <1 8 0 °
I CE 20-finger on HBT_2
1 VCE = 7 V
Gan
5
10
15
Pin (dBm)
25
20
(a)
36
50
r s = 0 .8 2 <1 8 0 °
r,=0.83<150°
m
S 24
c
*05
40
PAE
out
30
% 20
E
S 16
20
CD
H
o
CL
12
PAE (%), lc (10 mA)
- CB 20-finger on HBT_2
32 7 Vc e = 7 V
: VEB = -1.48 V
28 r f = 8.4 GHz
Gan
5
10
15
20
25
Pin (dBm)
(b)
Figure 3.7: Meaured Pout, Gain, PAE and lc of 20-finger (a) CE and (b) CB SiGe/Si
HBTs fabricated from structure HBT 2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
64
( r s = 0.82Z1800 and r L = 0.83Z1500) and under f e = 7 V and VBE = 1-48 V (class A),
Pout of 27.4 dBm (P ouurf = 550 mW) was realized at the peak PAE of 32% with the
associated power gain of 7 dB. These are the best RF power performance achieved with
SiGe/Si HBTs, till date. At the peak PAE, the initial linear power gain 10.9 dB was
compressed by 3.9 dB. After the fall-off o f the peak PAE to 25%, a Pout of28.45 dBm
(700 mW) was reached. With the consideration of the emitter undercut during KOH wet
etching (actual emitter area is about 1200 (im2), the power density in this device is 0.58
mW/|im2. Higher RF power density (0.96 mW/fim2) has been achieved from a samller
CE HBT (4-finger with the same type of layout) fabricated from the same wafer. The
power performance measurement results are shown in Figure 3.8. These parameters (for
both 4-figner CE, 10- and 20-finger CE and CB HBTs) represent the state-of-the-art
power performance of SiGe-based HBTs operating at X-band frequencies at the present
time. A lower RF power density for larger devices is resulted from the thermal effect
such that the power gain is reduced. The employment of a distributed layout and a low
level collector doping concentration in this study helps to reduce the thermal effects to a
minimum level.
Better power performance was not obtained from 30-finger HBTs,
mainly because of the severe thermal effects and the difficulty of output matching.
3.5
SUMMARY
In this chapter, the DC, small- and large-signal RF characteristics of SiGe/Si
power HBTs (fabricated from structure HBT_2) have been presented and analyzed. The
relationship between the DC and RF characteristics has been discussed in detail. Based
on the heterostructure design and distributed layout, state-of-the-art power HBT
performance has been achieved. Record breakdown voltages have been realized in large
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65
30 r— '— 1— '— '— l— '— 1—
- CE 4-finger on HBT_2
r s = 0.81 <175°
40
r u = 0.33<90o
0
0
0
5
10
P in (dBm)
15
20
Figure 3.8: Meaured Pou[, Gain, PAE and lc of 4-finger (actual emitter area 240 jim2)CE
SiGe/Si HBTs fabricated from structure HBT_2. At the highest measured Pom,
the RF power density is 0.96 mW/(im 2 with the associated PAE of 27.4%.
emitter area (780 fim2) SiGe-based HBTs, with 23 V BV ceo and 26 V BV cbo and
associated 40 GHz and 74 GHz oifmax for CE and CB HBTs, respectively. 25.9 dBm Pout
was obtained from 10-finger CE HBTs at a peak PAE of 28.2%. The associated power
gain at the peak PAE is 5.4 dB. 10-finger CB HBTs provide 25 dBm Pou, at a peak PAE
of 40.4% with associated power gain of 8 . 6 dB. A higher PAE of 42.1% was achieved at
slightly lower bias levels.
20-finger SiGe/Si HBTs demonstrated the highest Pou, at
thepeak PAE, 27.4 dBm (550 mW) for both CE and CB configurations. Peak PAE of
26.3% and 32% were measured for 20-finger CE and CB HBTs, respectively.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The
66
associated power gain at the peak PAE for CE and CB HBTs are 4 dB and 7 dB,
respectively. With 25% PAE, 20-finger HBTs are able to provide 28.45 dBm (700 mW)
P om, which is equivalent to a RF power density of 0.58 mW/jim2. The highest power
density was measured to be 0.96 mW/fim 2 from a 4-finger CE HBTs. These superior
SiGe/Si HBT power performance results from a very low base resistance, high device
breakdown voltages and good thermal stability of the device at very high power levels,
which are further ascribed to a combination of device heterostructure design and
optimized layout, good material quality and optimized processing techniques.
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CHAPTER IV
X-BAND (8.4 GHz) SiGe/Si HBT-BASED
MON OLITHIC ALL Y INTEGRATED
POWER AMPLIFIERS
4.1 INTRODUCTION
Monolithic microwave integrated circuits (MMIC) based on Si technology have
received considerable attention due to considerations of cost, compatibility with Si
CMOS technology, and the superior thermal and mechanical properties of Si.
Additionally, recent advances in SiGe-based devices and maturity in Si/SiGe epitaxial
growth have reduced or eliminated most of the limitations posed by conventional Si
technology. In particular, high-performance heterojunction bipolar transistors (HBTs)
made with SiGe/Si heterostructures have been reported.
For example, with the
realization of both fmax and f r over 100 GHz [1] [2], Si/SiGe HBTs have demonstrated
their suitability for microwave and millimeter wave applications.
There have been a number of reports on successful implementation of MMICs
with SiGe/Si HBTs as the active components.
These include voltage-controlled
oscillators (VCO’s) with oscillation frequency of 26 and 40 GHz [18], X-band mixers
[19] and narrow-band and wide-band amplifiers at Ka- [20] and Ku-band [21],
respectively. We have also recently reported X- and Ku-band amplifiers with Si/SiGe
67
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68
HBTs and micromachined lumped passive components [22]. However, power amplifiers
using SiGe/Si HBTs have only been demonstrated at C-band frequencies [23] and the
demonstration of a MMIC power amplifier has not been reported.
The successful
development of high-performance power amplifiers relies on the availability of highperformance SiGe/Si HBTs and high-Q factor on-chip passive components.
In this
chapter, the design, fabrication and characterization of an X-band high power amplifier
circuit using SiGe/Si HBT and lumped passive components will be discussed. In what
follows, the characteristics of discrete double-heterojunction HBTs fabricated from
structure HBT_1 are described in Section 4.2. Large-signal modeling of the power HBTs
and the modeling of the lumped passive components, together with circuit fabrication are
outlined in Section 4.3. The power amplifier performance characteristics are described in
Section 4.4. Concluding remarks are made in Section 4.5
4.2
CHARACTERISTICS OF SiGe/Si MULTIFINGER HBT’S
The realization of the power amplifiers was initiated with the device
heterostructure design and a proper device layout, taking into consideration the
requirements of high power handling capability, thermal stability and high-frequency
operation. These considerations have been documented in Chapter II. Discrete transistors
were fabricated by standard lift-off and etching techniques as described in Chapter II and
the DC and RF performance of the devices were evaluated.
DC and small-signal microwave characteristics of the discrete devices were
measured with a HP 4145B semiconductor parameter analyzer and a HP 85 IOC network
analyzer, respectively.
Devices in the common-base (CB) configuration show better
high-frequency performance than common-emitter (CE) devices with an identical active
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
area layout, mainly because the physical separation of the input port (emitter) and output
port (collector) for a CB configuration leads to a smaller value of Si 2 , than for the CE
configuration [22]. The characteristics difference between CE and CB HBTs have been
discussed in detail in chap. 3. The DC characteristics o f a 10-finger CB device are shown
in Figure 4.1, from which a DC current gain >5 of 31 is obtained at Vqe = 7 V if it is
configured in CE mode. The measured BVceo is 22.5 V and BVcbo is about 24 V. The
high-frequency response characteristics are shown in Figure 4.2. The device in the CB
mode exhibits a measured fmax of 37 GHz (it can be extrapolated to 62 GHz based on 6
dB/octave roll off). The —12dB/octave roll off beyond 27 GHz is due to a second pole
generated by the high base-collector junction capacitance, CBc- The ma xim um stable
gain (Graax) is 15.6 dB at 8.4 GHz.
Higher values of gain at this frequency can be
obtained with higher base-doping level and with reduction of emitter finger width and the
undercut during the etching.
The large-signal performance of the 10-finger CB SiGe HBT was tested on wafer
at 8.4 GHz using a single-tone Focus Microwave load-pull system under class AB
operation in CW mode. No special arrangement for heat dissipation was employed in
the measurements. The device was biased at Veb = -1.176 V and Vcb =
8 .1
V in order to
provide class AB operation and the source (/$ = 0.64Z1780) and load (71 = 0.71Z850)
matching were optimized for maximum output power. The measured output power Pout,
gain, power added efficiency PAE, and collector efficiency rjco[, are plotted as a function
of input power Pin in Figure 4.3. The measured linear gain is 10.9 dB. At 1 dB and 3
dB gain compression, the RF output power P.mb and Psbb are 21.5 dBm (140 mW) and
23.5 dBm (224 mW), respectively. The maximum PAE, 28.1%, is achieved at 4 dB gain
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
70
100
measurement
modeling
80
60
<
E.
-£? 40
20
0
2
4
6
8
VCB (V)
Figure 4.1: Measured and modeled DC current-voltage characteristics
of 10-finger
common-base SiGe/Si HBT fabricated from structure HBT_2, with emitter
area of A e = 780 (xm2.
25
20
MSG/MAG
15
^
10
• 62 GHz
1
10
Frequency (GHz)
100
Figure 4.2: RF response of 10-finger common-base SiGe/Si HBT fabricated from
structure HBT_2, with emitter area of AE = 780 fim2 measured at Is = -77
mA and Vqb = 7 V.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
71
compression with associated RF output power of 24.2 dBm (263 mW). The largest RF
output power (in saturation, gain drops to near unity) that the device can generate is as
high as 26.3 dBm (430 mW, 0.55 mW/jim 2 power density) and the maximum collector
efficiency is 36.9 % for Pin = 20.2 dBm.
Higher PAE could be obtained if the
measurement is optimized for highest PAE. No thermal or electrical instability was
observed under these operating conditions. The thermal stability is mainly ascribed to the
high thermal conductivity of the silicon substrate.
4.3 AMPLIFIER DESIGN AND FABRICATION
4.3.1
Large-Signal M odeling of Power HBTs
An accurate large-signal model is essential for the design of non-linear circuits,
such as high-power amplifiers and oscillators. The conventional Gummel-Poon model
serves as the basis of all modified versions, which may account for self-heating, collector
delay and breakdown.
Incorporating thermal effects into the large-signal model
significantly complicates the modeling procedure and the incorporation of thermal
circuits often results in a convergence problem during the harmonic balance analysis. On
the other hand, the conventional Gummel-Poon model is available in most commercial
software, such as EESof LIBRA, ADS and HSPICE. The suitability of this model for
SiGe HBT large-signal modeling can facilitate power amplifier design with SiGe HBTs.
Since Si has very good thermal conductivity, the thermal effects of SiGe HBTs can be
minimized with specially designed layout and heterostructure, as discussed in Section
2.2. Our attempt in using the conventional Gummel-Poon model, which accounts for the
Early effect and the Kirk effect but does not include thermal circuits, to model the 10-
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72
40
50
■ r S • 0.64<178 , r L: 0.71 <85
‘ f = 8.4 GHz
30
I V
pm
EB
= -1.176 V
a
30
out
20
•§
40
col
CB
PAE
20
Gain
s 10
O
CL
10
o
5
0
5
10
15
P (dBm)
in '
20
25
7
Figure 4.3: Measured output power Pout, gain, power added efficiency PAE and collector
efficiency rjcou as a function of input power Pin at 8.4 GHz biased for class
AB operation ( V e b = -1.176 V and
V cb
— 8.1 V) under CW conditions of 10-
finger common-base SiGe/Si HBT with emitter area o f Ae = 780 fim2. The
source (/$ = 0.64Z1780) and load ( / I = 0.71Z850) matching are optimized
for maximum output power. The output power is 24.2 dBm with concurrent
gain of 6.9 dB and 28.1% PAE. Maximum Pout is 26.3 dBm and maximum
Tjcou is 36.9%.
finger common-base power HBTs described in Section 4.2 has yielded good agreement
between simulated and measured DC characteristics and small-signal S-parameters. In
addition, the accuracy of the large-signal model has been validated with the measurement
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
73
of HBT power performance, which shows the possibility of using this model for power
amplifier designs.
For modeling purposes, the DC and small-signal S-parameters of the fabricated
10-finger CB HBTs were measured in a wide range of bias values. From the measured
forward and reverse Gummel plots, relevant DC model parameters (IS, ISE, ISC, IKF,
IKR, BF, BR, NF, NE, NR, NC, NKF, RE, RB, RC) were first extracted using the
optimization capabilities of HSPICE. The AC model parameters such as capacitances
and transit times were next extracted following the procedures described by Pehlke et al
[30]. The parasitic elements, such as Ls, L b, L c, were also taken into account. The value
of the capacitance of the interconnect pads was first extracted and this value was
confirmed by S-parameter measurements of a dummy pad frame. These parameters,
along with the DC model parameters, were further optimized in HP EESof LIBRA by
fitting the measured S-parameters at various biases and in a frequency range of 2-26
GHz. The Gummel-Poon model with the values of the model parameters are listed in
Figure 4.4. From the modeling, it was found that the Early effect and Kirk effect are
related to each other, particularly at high bias levels. For the HBT described in Section
4.2, a large Early voltage is expected from its high base doping level (2.4xl0 1 9 cm'3) and
low collector doping level (-4x10 1 6 cm'3) since the base width modulation by the
collector-base bias Vcb is very small. However, this point is only valid at low bias levels.
When the HBT is biased at higher levels, the base push-out due to Kirk effect will create
an extended base region. The width of this extended base region can be much larger than
the original SiGe base region, but the hole concentration in this region is very low and,
hence, the modulation of this extended base by the bias is significant. As a result, at very
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74
* C
E
,G-P
BJT
G um m el-Poon Large-Signal Model P aram eters
P ara­
m eter
IS
BF
NF
VAF
IKF
ISE
NE
BR
NR
ISC
NC
Value
2.06e-12 A
52
1.09
17 V
0.5 A
2.02e-5 A
6.53
7.3e-6
1.54
1.25e-9 A
3.91
P ara­
m eter
RB
RE
RC
CJE
VJE
MJE
TF
CJC
VJC
MJC
XCJC
Value
3n
n
3.5
4.7 Q
1e-12 F
0.75 V
0.33
5.9e-12 s
1.29e-12 F
0.4 V
0.5
0.35
P a ra ­
m eter
VJS
EG
XTI
FC
NK
TNOM
L„
L„
L„
c„
c„
Value
0.75 V
1.11 eV
3
0.5
0.5
300 K
8e-12 H
3e-11 H
3e-11 H
9e-14 F
3e-14 F
Figure 4.4: Complete Gummel-Poon model for 10-emitter fingers common-base SiGe
power HBT based on structure HBT_2 with values of the device parameters
and parasitics used in the model.
high bias levels, which are typical of high power operation, the Early voltage is
significantly reduced. The reduction of Early voltage occurs as long as the Kirk effect
takes place and the manifestation of the reduction is a steep rise of collector current at
high Vce bias values in a measured current-voltage curve in common-emitter
configuration. This steep rise of collector current is a phenomenon which is different
from the sudden increase of collector current due to breakdown. Considering the high
bias levels in large-signal operation of the device, the S-parameter fitting is particularly
optimized at relatively high bias points in this modeling. The modeled DC characteristics
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
75
1 . 0
'1 ?
-0
.
—5 . 0
2'
-0 . 5
'22
Frequency
-2
2.0
to
26.0
.
0
GHz
Figure 4.5: Modeled and measured small-signal S-parameters of 10-finger common-base
Si/SiGe/Si HBT from structure HBT_2 at Ie = -77 mA and Vcb = 7 V from
2-26 GHz.
are also plotted in Figure 4.1 along with the measured data for comparison.
The
agreement is good for almost the entire measurement range. The discrepancy between
the model and the measurement at the low Vcb and high l c region is due to the simplicity
of the Gummel-Poon model. Figure 4.5 shows the measured and simulated small-signal
S- parameters for the optimum operating point (Je = -77 mA, VCb = 7 V). Again, fairly
good agreement is observed and larger discrepancy for Su is still due to the simplicity of
the Gummel-Poon model. Since fir, fmax and stability factors are directly derived from S-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
76
30
predicted by G-P model
measured
25
E 20
CD
jO
H
o
15
10
5
-5
0
5
10
15
20
25
P tn (dBm)
Figure 4.6: Predicted from Gummel-Poon model and measured output power of 10-finger
common-base Si/SiGe/Si HBT (based on structure HBT_2) as a function of
input power under the same source ( / } = 0.64Z1780) and load ( / I =
0.71Z850) matching and same bias conditions (V eb = -1.176 V and Vcb = 8.1
V).
parameters, good agreements can also be expected for these parameters.
To further
validate the accuracy of the large-signal model, the power performance predicted by the
model was compared with the measured power data, under the same impedance matching
and bias conditions.
This is shown in Figure 4.6 and again excellent agreement is
achieved. Other power performance parameters, such as PAE and power gain, can also
be accurately predicted as they are directly related to output power, POM- The fair
accuracy and suitability of the conventional Gummel-poon model is mainly ascribed to
the device design, in which thermal effects are minimized with a non-compact layout and
a lightly-doped collector, and consideration of the Early and Kirk effects. A modified
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77
Gummel-Poon model should take into account other effects associated with these SiGebased HBTs.
4.3.2 Characterization and M odeling of Lumped Passive Components
The lumped passive components, including spiral inductors, MIM capacitors and
thin film resistors, are important circuit components along with the high performance
active devices. These components are widely used as matching elements, bias chokes
and filter com ponents, with the advantage of sm aller size than the distributed
transmission line components at X-band frequencies. The scalable design of these
passive components can ease circuit implementation with the active devices. One of the
approaches to this scalable design of the lumped passive components is to model their
high-frequency characteristics. Because of the associated parasitics, the quality factor
(Q) o f the passive components changes with frequency. The modeling of passive
components not only give the values of the parasitics, additionally they serve as an
indicator of techniques for improvement. In this study, the passive components were
modeled by fitting the measured S-parameter values with the corresponding equivalent
circuits for all available geometries. From such modeling, the inductance values of the
spiral inductor, the unit-area capacitance of the MIM capacitors and the sheet resistance
of the thin film resistors were obtained. Figure 4.7(a) shows the equivalent circuit of a
3.5-tum spiral inductor. Figure 4.7(b) shows the agreement between the measured and
modeled S-parameters for this element.
This equivalent circuit is accurate for modeling
the sp iral in d u cto rs up to ~26 GH z, w hich is su fficien t for X -band circu it
im plem entation. The change in inductance with num ber of turns is shown in
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78
0.005 pF
1.83 nH
5.56 £2
' /W V — lh
0.028 pF
0.028 pF
(a)
-
0
.
2’
—5 . 0
'12
-0 . 5
Frequency
-
0.5
to
25.5
2.0
GHz
(b)
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79
3.0
2.5
W/S = 14/6 urn
xc
<D
£§
o
T33
^
2.0
1 -5
-t n
0.5
0.0
0
1
3
2
5
4
Number of turns
(c)
Figure 4.7: (a) Equivalent circuit of a 3.5-tum spiral inductor; (b) the S-parameter fitting
with the equivalent circuit of (a); (c) inductance value change with number of
turns.
0.16 nH
I ------- 1—
0.8 pF
—
0.86 Q
| |-------- W V — f
0.028 pF
0.028 pF
(a)
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80
'12
-
>22
0 - 2'
-0 .5
-
Frequency
0.5
to
25.5
2.0
GHz
(b)
1.4
1.2
_
U.
SiO =200 nm
1.0
0.6
0.4
0.2
0.0
1000
2000
4000
3000
5000
6000
Area (pm2)
(c)
Figure 4.8: (a) Equivalent circuit of a 4000-jim2 MEM (200 nm SiO insulated) capacitor;
(b) the S-parameter fitting with the equivalent circuit of (a); (c) the
capacitance value change with capacitor area. The unit-area capacitance value
is 0.2 fF/pm2.
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81
Figure 4.7(c). Figure 4.8 shows the MIM capacitor results. A unit-area capacitance of
0.2 fF/jim 2 was obtained from the modeling. The quality factor Q was also calculated for
the lumped passive components.
Depending on the geometry and the size of these
lumped elements, the Q-factors of the fabricated spiral inductors and capacitors varied in
the range of 10-16 and 40-70, respectively, as a result of reduced parasitic from the
micromachined structure [2 2 ].
4.3.3
Circuit Design and Fabrication
After the characterization of the HBTs and passive components, the large-signal
model of the transistor and equivalent circuits of the passive components are used for
circuit design.
Circuit simulation and optimization were done with the help of HP
EESOF LIBRA. The stability of the circuit was analyzed before the circuit layout was
designed. Figure 4.9(a) shows the circuit diagram of the X-band power amplifier. The
circuits are fabricated with heterostructure HBT wafers identical to those used to
fabricate discrete devices and by using identical lithography, lift-off and etching
techniques. The detailed fabrication process of the MMIC circuits has been described by
Rieh et al [22]. The on-chip matching networks were realized with micromachined spiral
inductors and SiO MEM capacitors.
The input and output matching networks were
designed for high output power and both were matched to 50-ohm impedance. The
photomicrograph of the fabricated MMIC power amplifier is shown in Figure 4.9(b).
The small chip size of 1 x 0.75 mm 2 results from the use of lumped passive elements.
4.4 POWER AMPLIFIER CHARACTERISTICS
The fabricated power amplifier was tested on-wafer under continuous wave (CW)
operation (class A) at room temperature and no wafer thinning or extra heat sinking was
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
82
r
0.54 nH
0.54 nH
S Y Y \
/Y Y V
y
^
r
x
i
2.62 nH
0.54 nH
1.73 nH
0.75 pF
0.22 pF
1
1
(a)
(b)
Figure 4.9: (a) Schematic of single-stage MMIC power amplifier using common-base
(CB) SiGe/Si HBT and passive components; (b) photomicrograph of a
fabricated MMIC power amplifer (chip size, 1 x 0.75 pm2).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
83
12
I = -92 mA
CB
22
m
-4
-12
-16
-20
5
6
7
10
9
Frequency (GHz)
8
11
12
13
14
Figure 4.10: Small-signal performance of MMIC power amplifier with 8.7 dB gain at 8.4
GHz and input/output return loss of 7.1 dB and 4.9 dB, respectively, at the
same frequency.
employed. Figure 4.10 shows the measured small-signal gain and input/output return
losses of the power amplifier. At 8.4 GHz and with a bias of Ie = -92 mA and Vcb = 7 V,
the small-signal gain is 8.7 dB, with input and output return loss of 7.1 dB and 4.9 dB,
respectively. These values vary with bias and the goal of these measurements was to
optimize the maximum gain. The design goal of narrow band matching circuits is largely
reflected in this plot with the peak-gain frequency centered at 8.2 GHz, which is very
close to the desired center frequency 8.4 GHz, and a bandwidth of 4.1 GHz. The peak
gain is smaller than the designed value (-10 dB) and the bandwidth is larger than the
designed value (-2.5 GHz). The input return loss is also worse than the designed value.
A detailed investigation after the circuit characterization shows that the Q-factors of the
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
84
passive components, which were incorporated in the circuit, are lower than the desired
values. Both the spiral inductors and the MIM capacitors show higher serial parasitic
resistance, identified to be due to a processing related issue, resulting in a lower gain.
The larger bandwidth and the low input return loss are due to other parasitics associated
with inductors and MIM capacitors. The inductor values and the unit-area capacitance
value matched the desired values and thus the measured peak-gain frequency meets the
design goal. Figure 4.11(a) shows the output power, gain and power added efficiency
(PAE) as a function of input power, measured at 8.4 GHz, with the HBT biased at VEb = 1.3 V and Vcb = 11-5 V (class A) for maximum output power. This high operation
voltage is a consequence of the high-breakdown voltage achieved with a thick and lightly
doped collector layer. The peak efficiency, 12% at these bias conditions was achieved at
2.9 dB gain compression with a linear gain larger than
6
dB. The output power at the
peak value of PAE is 22.9 dBm (195 mW) and 24.8 dBm (302 mW) in its saturation.
These values, particularly the PAE, are also lower than the designed values for the same
reasons as outlined above for the small-signal characteristics. The major loss comes from
resistive loss associated with the spiral inductors. Although the design of the circuit was
optimized for maximum output power, higher PAE (16%) was observed when the circuit
was biased (V eb = -1.65 V and Vcb = 7.0 V) for optimum PAE, as shown in Figure
4.11(b). The maximum PAE was achieved at a 2.2 dB gain compression point with a
linear gain of 7.5 dB. The output power at the peak value of PAE is 21.1 dBm and
saturated at 23.1 dBm. Comparing Figure 4.11(a) and Figure 4.11 (b), high output power
can be obtained at the expense of low PAE and vice versa. A high output power can be
obtained at higher bias conditions and a high PAE can be obtained at low bias levels.
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85
30
20
25
15
out
§.
c
PAE
20
CO
E
CD
TO
CL
Gan
12
10
14
16
18
P (dBm)
20
22
24
in
(a)
30
30
V
25
EB
= -1.49 V
CB
out
20
PAE
CL
•5
o
Ga'n
10
12
14
16
18
20
22
24
P (dBm)
in v
'
(b)
Figure 4.11: (a) Power performance of the SiGe/Si HBT MMIC amplifier biased at V eb =
-1.3 V and Vcb = 11.5 V. 22.9 dBm output power at peak efficiency and
24.8 dBm in saturation were obtained, (b) Power performance of the
SiGe/Si HBT MMIC amplifier biased at VES = -1.65 V and VCB = 7.0 V.
Peak PAE of 16% was obtained.
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86
Usually, high-PAE power amplifiers can be realized with other classes of amplifier
operation.
The stability of the CB configuration, compared to that of the CE configuration,
has been of concern due to the higher unilateral gain in the former case. However, no
oscillation was observed at any bias points, indicating the successful design and
implementation of the matching circuits. The discrete HBTs, fabricated on the same
wafer, demonstrate good repeatability o f excellent DC and high frequency characteristics.
However, DC measurements on the HBTs which are embedded in the circuit show lower
current levels with the same applied bias, which is a direct consequence of resistive loss
in the spiral inductors.
Although the resistive loss in the spiral inductors and MIM
capacitors can be reduced, it is still a shortcoming of these lumped passive elements in
spite of their small area. By reducing the losses, the power amplifier efficiency can be
significantly increased. Due to the difficulty of developing high-Q spiral inductors with
currently available technology, the improvement of the performance of the active devices
is seen as a way to relax the requirements of the performance characteristics of lumped
passive components.
Our recent study has shown that there is room to improve the
performance of the SiGe/Si power HBTs in terms of gain, output power and PAE [31].
The demonstration of the Si-based MMIC power amplifier is an important step
toward the system-on-a-chip solution for the next generation communication applications
and, currently, it shows the feasibility of integrating Si-based microwave power
transistors with other passive components on a single chip. Based on this achievement, a
highly integrated microwave transmitter based on Si, with reduced volume and weight,
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87
seems feasible. Due to the low cost o f Si, the MMIC-type approach for this application
also means a low cost for mass production.
4.5 SUMMARY
The design, fabrication and characterization of a class A single-stage X-band
MMIC power amplifier incorporating a SiGe/Si HBT and lumped passive components is
described in this chapter. The double heterostructure power HBTs are characterized by a
breakdown voltage BV ceo of 22.5 V, power gain Gmax of 15.6 dB at 8.4 GHz and an
extrapolated fmax o f 62 GHz.
The amplifier design was initiated with large-signal
modeling of SiGe/Si power HBTs using the conventional Gummel-Poon model and the
equivalent circuit modeling of the spiral inductors and MIM capacitors. Good accuracy
has been achieved from this modeling process and the interplay of the Kirk effect and the
Early effect at high bias levels is addressed for the first time. At 8.4 GHz, the power
amplifier exhibits an output power of 23 dBm at peak PAE, 12%, and a saturation output
power of 25 dBm. Higher PAE (16%) was also observed when the circuit was biased for
this purpose. It was found that the resistive loss in the passive components accounts for
the major loss in the MMIC.
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CHAPTER V
DEVELOPMENT OF Ku-BAND (12.6 GHz) NPN
SiGe/Si POWER HBT’S
5.1 INTRODUCTION
Regardless of the fact that the highest fmax achieved with SiGe/Si HBTs is 160
GHz (based on the unilateral gain extrapolation), the highest reported large-signal
operation frequency till date is 8.4 GHz (X-band) [31,32], With the demand for higher
capacity of communication channels, higher operation frequencies are always desired.
Large-signal power amplification at the Ku-, Ka- and higher frequency bands has only
been demonstrated with high-speed IH-V devices.
The development of SiGe-based
MMIC power amplifiers has shown the promise of a system-on-a-chip with Si-based
semiconductors [33]. The realization of a system-on-a-chip will enable the reduction in
volume and weight of a communication unit and, furthermore, substantially reduce their
manufacturing cost for mass production.
Therefore, it is important to explore high-
frequency and high-power operation of SiGe/Si HBTs.
Small-signal amplifiers in the Ku-band, with SiGe-based HBTs, have been
reported [22]. However, large-signal power amplification with SiGe-based HBTs at Kuband has not been reported. The obstacle to realizing high-efficiency and high-power
amplification at high frequencies (Ku-band and higher) with SiGe/Si HBTs is the
88
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89
difficulty in achieving high power gain and high power output simultaneously at these
frequencies. The parameter of importance, which is often used to characterize the speed
o f a power HBT, is the maximum oscillation frequency, fmax- A high value of fmax can be
obtained in smaller devices, but with lower breakdown voltages and lower power level.
A n fmax of 120 GHz has been reported for a common-base SiGe/Si HBT with an emitter
area of 70-80 pm 2 [34]. The operating voltage and current for this HBT is only 4 V and
40 mA, respectively. The highest fmax (160 GHz, extrapolated from the unilateral gain)
__
<j
was reported for a common-emitter HBT with an emitter area of only 12.8 pm“ [1].
However, these state-of-the-art high speed HBTs are not quite useful for high power
applications due to their small emitter area, low operation voltage/current, and
consequent low power level. SiGe-based power HBTs, which have large emitter area
(>600 pm2) and high-breakdown voltages (BV ceo> 2 0 V) with concurrent fmax values
higher than 74 GHz [31] have never been reported. Efforts to develop high power SiGe
HBTs, aimed for operation at high frequencies (X-band) and beyond, have been launched
at the University of Michigan [32] and X-band power devices with excellent
characteristics were recently reported [31].
5.2
DESIGN CONSIDERATIONS FOR HIGH-FREQUENCY POWER HBT’S
For large-area SiGe/Si HBTs, the room to reduce base resistance Rb in order to
improve fmax (Eq. 2.3) is rather limited. On the other hand, the base-collector junction
capacitance C bc is proportionally increased with the device area.
Theoretically, the
RbCqc product remains constant with increasing of emitter area. However, due to the
thermal effects associated with large-area devices, particularly when these devices are
operated at high power levels, the increase in junction temperature of the devices will
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90
reduce the hole mobility (phonon-scattering limited) in the base region and, therefore, the
base resistance R b will not be inversely related to the Cbc• hi order to reduce the thermal
effects, a distributed layout was proposed and described in Chapter II (also in Ref. 32 )
and, as a result, a large
of 74 GHz was obtained for large-area (780 pm2) and high-
BV ceo (23 V) SiGe/Si HBTs.
These devices demonstrated large power gain and the
largest RF output power, achieved at the highest large-signal operation frequency (8.4
GHz) [31]. For double-mesa type SiGe/Si HBTs, further reduction of Rb can be achieved
with a smaller emitter finger width and a higher base doping concentration.
The base-collector junction capacitance C bc is another parameter that needs to be
reduced for the large-area SiGe/Si HBTs to be a candidate for high power applications at
very high frequencies (e.g., Ku-band). In a BJT or HBT, in which C bc is the dominant
limiting factor for the high frequency response, the power gain follows a roll-off o f 6
dB/octave with frequency. At some frequency, depending on the value of C bc, a 2 nd
pole will be generated.
This apparently creates a more rapid power gain roll-off (-
12dB/octave) and the useful frequency range is reduced (Fig. 3.4).
In this case, the
extrapolated fmax value, based on the assumption of single-pole approximation, becomes
erroneous. A smaller value of C bc can shift the frequency of the 2 nd pole to higher values
and thus the useful frequency range of the device can be extended.
In order to reduce the value of Cbc, the common-base configuration is often used
for power applications, in which case C ec (smaller than C bc) becomes the limiting factor
for the frequency response. The superiority of CB HBTs over CE HBTs, for power
applications, has been discussed in Chapter m . Various processing technologies have
been devised to reduce C bc of a BJT/HBT.
These include laterally etched undercut
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91
(LEU) [35], heavy base doping by ion implantation in the external base region, etc. From
the point of view of the layout design, a compact layout can reduce C bc', however, with
the price of increased thermal effects. As a result, the compact layout option is not a
good one for reducing C bc for high power applications.
In what follows, the device heterostructure design and layout design to improve
the RF performance characteristics is described in Section 5.3. The process development
for fabricating narrow emitter fingers (<
described in Section 5.4.
2
pm) and for reducing device parasitics is
The DC and small-signal characteristics of these Ku-band
SiGe/Si HBTs will be described and discussed in Section 5.5.
The large-signal
characteristics will be described and discussed in Section 5.6, followed by a summary in
Section 5.7.
5.3
HETEROSTRUCTURE AND LAYOUT DESIGN
The considerations for SiGe/Si heterostructure design and layout design have
been documented in Chapter H. Based on those considerations, further modifications
have been made to the heterostructure (HBT_2, Figure 2.1(b)) and on the distributed
layout, in order to obtain better RF performance characteristics. These modifications are
discussed in this section.
5.3.1 Heterostructure Design
It is well known that the solid-source MBE growth technology can offer sharper
interface definition than CVD growth and a well-defined SiGe/Si interface can maximize
the RF performance of SiGe/Si HBTs. For this purpose, solid-source MBE was used to
grow the heterostructures for this study.
The following modifications were made to
maximize the RF performance. The doping concentration in the emitter cap region is
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92
increased to 2 x l0 2 0 cm'3, which cannot be achieved by CVD growth.
With the high
doping concentration in the emitter region, the contact resistance of the emitter metal, as
well as the series resistance associated with the emitter cap, will be reduced to a
negligible level. Therefore, Re in Eq. 2.7 and 2.9 will become negligible. The thickness of
the emitter cap layer is increased to 250 nm with due considerations to the self-aligned
base-emitter metallization. The emitter layer is reduced to 50 nm, considering the sharp
transition of the doping concentration from the emitter cap region to the emitter region
that can be achieved with MBE growth. The doping concentration of the emitter region is
increased to 2 x l0 18 cm'3. A base doping concentration of lxlO 2 0 cm ' 3 is expected to be
achievable with MBE growth. As a result, the base resistance RB will be further reduced,
to enable the achievement of a higher f nmx. The thickness of the base region is increased
to 25 nm to further reduce the base sheet resistance. The Ge fraction in the SiGe base
region is increased to 30%, which is achievable with the MBE growth. A thicker (7 nm)
undoped SiGe spacer layer is incorporated at the collector side than at the emitter side (3
nm).
The reason for the different thickness has been discussed in Chapter II. The
thickness of the collector region is 500 nm, with a doping concentration of 2x10 1 6 cm'3.
The low doping concentration in the collector layer ensures a high breakdown voltage. A
thick and heavily doped subcollector region is desirable for fmax. However, because the
growth rate during MBE is very low, an extended growth time can cause the segregation
of the n-type dopant in the subcollector region. Therefore, this subcollector layer is either
made by ion implantation followed by a thermal annealing or grown by CVD before the
growth of the remainder of other heterostructure.
Ion implantation is sometimes
preferred since it can produce a much higher doping concentration (reduced Rc) than
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93
CVD growth.
In the present study, a 1 (im Si subcollector layer with a doping
concentration o f 2x10 1 9 cm " 3 was grown by CVD. The complete heterostructure, grown at
Daimler-Chrysler Research Center, is schematically shown in Figure 5.1 and the
measured SIMS profile is shown in Figure 5.2.
5 3 .2 Layout Design
The detailed considerations for the lateral layout design have been discussed in
Chapter II. Based on those considerations, more aggressive modifications have been
made to the layout, for achieving superior RF performance. In order to further reduce Rb,
devices with emitter finger width of 1 (im and 1.4-1.5 pm have been designed. At high
bias levels, the base access resistance should be reduced with these narrow emitter
fingers. In order to maintain a small C bc and ensure a small current flow in these narrow
emitter fingers, three emitter fingers are grouped together in a subcell. The emitter finger
lengths vary from 15-20 Jim for different emitter widths. Interdigitated collector metal
stripes are inserted in between the subcells to form a distributed layout for reducing the
thermal effects within the device active region. These collector metal stripes vary from 4
Jim to
8
jim in width. In order to reduce the parasitic capacitance, the layout is also
designed to isolate the active device area with the external contact area during the
fabrication process. For this purpose, all the electrode metals are connected to the outside
via air bridges, which is formed by isotropic RJE etching. The base metal is usually
made thin (1000-1500 A) for the self-aligned base-emitter metal structure. If this thin
base metal is used to form air bridges, it may become a concern of fabrication yield after
the metal is exposed to RIE etching. An extra mask layer was used to form a thicker
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94
Emitter cap
Si
n+
Sb
2
x l 0 2 0 cnr 3
250 nm
Emitter
Si
n
Sb
2
xlOI8 cm' 3
50 nm
Spacer
Si0 7 Ge0 3
i
Base
^*0.7^e0J
P+
Spacer
^*0.7^e0J
i
Collector
Si
n-
Sb
2
x l0
16
cm' 3
Sub-collector
Si
n+
As
2
x l0
19
cm' 3
Si(100)
P-
: Substrate
3 nm
lxlO2 0 cm*3
B
25 nm
7 nm
500 nm
1 0 0 0
nm
540 pm s
lxlO 12 cm*3
El
I I !
1 0 20
pb
|
1 I
I
I
|
i i
i
i
j
> i
I I
j_
Ge
B
30
25
___ ^ ___
1019
20 S2
F
15 o
03
1 0 18
10 CD
b
<D
1017
4 — 3x 1 0 1
1 0 1 6
0.0
0.5
1.0 1.5
Depth (pm)
2.0
0
1021
o
"cS 1020
e
o
13
ei
o
1018
2
cCD 101?
o
o
O 1016 S |
0
(a)
l l
l | l l l l j l l l
l | l l
I
CO
1 0 2 1
o
Concentration (atoms/cc)
Figure 5.1: Epitaxial structure of the Ku-band power SiGe/Si HBT: HBT_3. The
subcollector layer is grown by CVD and the rest is grown by MBE. All the
values are designed values.
10
IU
®
0
/w u l/l, . i . 'Xv
0.1 0.2 0.3 0.4 0.5
Depth (pm)
I I V Ml /![
(b)
Figure 5.2: Measured SIMS profiles of the MBE grown Ku-band power SiGe/Si HBTs :
(a) HBT_3 showing the complete structure; (b) HBT_3 with a detailed
analysis o f the emitter and base layers.
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95
portion of the base metal, which connects the thinner portion of the base metal in the
device active region with the contact region. The base metal air bridges are formed with
the thicker portion of the base metal. In addition, deep RIE etching will generate big
etching depth for the contact regions that are located outside of the device active area,
and thus will endanger the step coverage for the final interconnect metallization. Cares
are taken in the layout design to overcome this weakness.
5.4
PROCESS DEVELOPMENT FOR SMALL FEATURE FABRICATION AND
ISOTROPIC DRY ETCHING
The detailed fabrication procedures for double mesa type Si/SiGe/Si HBTs have
been described in Chapter II. However, this process has to be modified to meet the
requirements set by the feature size of 1 pm and the incorporation of the air bridges. The
processing techniques to satisfy these requirements are discussed in this section.
In order to reliably fabricate transistors with l-pm emitter size of without
resorting to X-ray or e-beam lithography, the pattern transfer using optical lithography
has to be done carefully. Either clear-field or dark-field contact mask can be used for the
pattern transfer, and the resolution of both is limited by the wavelength. The most critical
aspect in this step is to reduce undesired diffraction as much as possible. If a dark field
mask is used in this step, an exposure time of about 6.5 sec is generally used for PR 1813.
Because of the long exposure time, optical diffraction along the mask pattern edges will
enlarge the feature size after developing. Also, the resulting PR pattern profile does not
have the desired overhung and a sharp edge of the emitter metal cannot be obtained after
evaporation and lift-off. In addition, the use of a dark field mask is not as convenient as
the use of a clear field mask.
The latter involves an image reversal process.
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For
96
successful photolithography, the environmental humidity has to be below 40%-50%,
otherwise the pattern transfer is not possible. Second, the PR thickness has to be very
small (several tenths of 1 Jim) and the PR surface after spinning needs to be free of dried
PR particles in order to minimize optical diffraction. Third, a large portion of the wafer
edge has to be removed in the edge-removal step. Fourth, the stage of the aligner has to
be leveled with the mask and no more than two Newton rings should be seen when the
wafer is brought close to the mask. Last and not the least, the processed wafer cannot be
larger than 2x2 cm, which is mainly limited by the non-uniform hotplate baking. Each of
these conditions has a significant influence on the successful fabrication of l-(im emitter
sized transistors. The critical process parameters, that are modified from the standard
ones (Chapter II) for this steps are, spinning speed
6
krpm for 30 sec, pre-exposure time
of 3 sec @ 20 mW/cm 2 and developing time of 25-30 sec with fresh developer. The preexposure time is so critical that 0.5 sec makes a significant difference on the resulted
patterns.
A l-|±m emitter finger size (width) adds more difficulty to the control of the
selective base exposure with KOH wet etching. The over-etching, which is needed to
expose the heavily doped base region, and the lateral undercut of the emitter have to be
well balanced. An extended over-etching or a high etching rate may completely remove
the material underneath the 1-jim emitter metal. The procedures described in Section 2.3
needs to be perfected.
The new process adopted for base metal formation consists of two steps. The first
is identical to the standard base metal formation, as discussed in Chapter II. After the
thin base metal deposition and lift-off, the extra mask layer (BCML, Mask #3) is used to
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97
form the thick portion of the base metal. The recipe for this step is: spin PR 1813 twice
@4.5 krpm for 30 sec, pre-bake @80 °C for 100 sec, immersion into chlorobenzene for
5.5 min, edge removal and develop, align and expose 6.5 sec @20 mW/cm", develop in
MICROPOSITrDI =1:5 solution for 40 sec, evaporate Ti/Au (100/2500 A) and lift-off.
This thick portion of the base metal connects with the self-aligned thin portion and
provides strong mechanical support after the base metal air bridges are formed. Since the
adhesion on the SiGe layer is poorer than on Si, a thin layer of Ti is mainly used for this
purpose. Thicker Ti layer should be avoided for its low conductivity. A thick Au layer
should be avoided for stress considerations.
The procedure for the fabrication of the air bridges was also modified from the
standard process. The RIE step for the emitter mesa formation is unchanged, because a
vertical profile is desired in this step. The base mesa formation using RIE partially forms
the air bridges. An isotropic etching in this step also helps to reduce C bc by etching away
some material underneath the base metal.
The etching time for this step needs to be
calculated from the heterostructure SIMS profile. The procedure for this step is similar to
the standard process, except that a pressure of 20 mtorr and RF power of 50 W are used
for the etching. A large undercut is expected with this etching recipe. The etching rate is
not so stable at this pressure as at 5 mtorr and therefore the etching rate needs to be well
calibrated.
The air bridges for all the electrodes are formed in the device isolation step. The
etching recipe is a pressure of 40 mtorr and RF power of 40 W. The increased pressure
and reduced power will decrease the mean free path of the etching ions and result in a
more complete isotropic etching. Most of the material underneath the bridges will then
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98
be removed, while the active area is covered with thick patterned PR. The emitter air
bridge structure fabricated from this isotropic etching method is shown in Figure 5.3.
The bright portion in the picture is the interconnect metal, which is not covered by SiC>2 .
The dark portion is covered by PECVD S i0 2. The emitter air bridges look much thicker
than 250 nm, which is due to the encapsulation o f the S i02. The fully fabricated 15emitter finger common-base HBTs are shown in Figure 5.4.
5.5
DC AND SMALL-SIGNAL RF CHARACTERISTICS
The DC characteristics of the fabricated SiGe/Si HBTs were measured with a HP
4145 semiconductor parameter analyzer.
Figure 5.5 shows the current-voltage (I-V)
characteristics of 15-finger CB SiGe/Si HBTs (layout shown in Figure 5.4, emitter area
Ae = 672 Jim2). The measured base-collector breakdown voltage (BVcbo) is about 20 V
and the open-base collector-emitter breakdown voltage (BVceo) is about 16 V (not shown
in the curves). No punchthrough was observed at these voltages. The high breakdown
voltages result from the low collector doping concentration and the high base doping
concentration (Figure 5.2), which allow large operating voltages for power amplification
and can accommodate a large output signal swing.
The offset voltage
0.6
V .
( V C B , 0ffset)
in the CB configuration was measured to be about -
The common-emitter current gain (3 and the differential current gain A/3 versus
collector current Ic for a 15-finger SiGe/Si HBT, biased at Vce = 8.0
V ,
were measured
and the results are shown in Figure 5.6. Due to the current limitation of the HP 4145
Semiconductor Parameter Analyzer, the highest current gain (3 and the roll-off of f3 at
high Ic levels were not measured for this 15-emitter finger device. The largest (3 was
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99
interconnect
ll V
Mdyn
3 0 0 kV I0 3 3 5 x
m m m
Figure 5.3: SEM photomicrograph showing the air bridge structure made with isotropic
dry etching. The air bridges are encapsulated with 1-pm PECVD S i0 2.
(a)
(b)
Figure 5.4: Photomicrographs of fabricated 15-emitter finger (1-pm width) common-base
SiGe/Si HBTs: (a) without air bridges; (b) with air bridges.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
100
120
BVcbo = 2 0 V
BVCeo = 13 V
100
80
<r
1 60
o
40
20
r /
- ^
f
0
2
4
6
8
Figure 5 .5 :1-V characteristics of 15-finger CB SiGe/Si HBTs (Ae = 672 (im2) fabricated
from heterostructure HBT_3. The breakdown voltages are BV cbo = 20 V and
BV ceo = 13 V.
estimated to be around 18.6. The highest differential current gain Afi was, however,
measured to be 24.8. These values are appropriate for RF applications.
The forward and reverse Gummel plots are shown in Figure 5.7. The forward
Gummel plot (/Br/and 7c/) shows high base leakage current at low bias levels, which leads
to a forward base ideality factor
hbj,
of 3.88. The high base leakage current is
commonly observed in double-mesa type SiGe/Si HBTs, which mainly arises from a
physical separation between base-emitter PN junction and the Si/SiGe heterojunction and
from insufficiently passivated surface states. Since it is usual to operate power HBTs at
high base-emitter bias levels, the non-ideal base current at low bias levels has negligible
effect on large-signal performance. The ideality factor of collector current, Ncj, is 1.01.
As seen from the forward Gummel plot, due to the base leakage current at low bias levels
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101
30
25
20
10
40
20
0
60
80
100
lC (mA)
Figure 5.6: DC current gain (3 and differential current gain A(3 vs. collector current Ic for
a 15-finger SiGe/Si HBTs (A e = 672 pm2) fabricated from heterostructure
HBT_3.
10-1
_<.
10'3
c
10-4
o
10-5
£
forward Gummel plot
reverse Gummel plot
'B.r
'B.f
E,r
0.0
0.2
0.6
0.4
VBE& VBC (V)
0.8
1.0
Figure 5.7: Forward (Jbj and Icj) and reverse (IB.r and / £r) Gummel Plots of a 15-finger
SiGe/Si HBTs (Ac = 672 (im2) fabricated from heterostructure HBT_3.
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102
high current gain is only available at high bias levels from these HBTs. The reverse
Gummel plot shows better ideality factors than the forward Gummel plot, with base
ideality factor nB,r ~l-24 and emitter ideality factor «£r ~ 1.14. The smaller nB.r, compared
to nBj, is ascribed to the fact that the base contact is made on the top of the exposed base
layer such that the electron conducting path in the base-collector junction is vertical and
the surface conducting path is minimal compared to the base-emitter junction. Because
of the much lower injection efficiency from the collector, the base current is larger than
the emitter current for all bias levels. The coincidence of
and IEr in Figure 5.7
indicates that the turn-on voltage of the base-emitter junction diode and that of the basecollector junction diode are almost equal. If 1 pA is used as the criterion for junctions to
be turned on, the tum-on voltages of these two junction diodes are about 0.44 V. This
small value of tum-on voltages is a clear indication that the PN junction resides in the
SiGe region, since SiGe has a smaller bandgap than Si.
The small-signal RF performance of the SiGe/Si HBTs with different geometries
was characterized by measuring the sm all-signal S-parameters with an HP 8510C
network analyzer. Figure 5.8 shows the RF response of a 9-finger CB HBTs (AE = 403
Jim2) under the optimum bias conditions with Vcb = 6.5 V and IE = -69 mA.
The CB
device demonstrates an extrapolated fmax of 100 GHz based on a - 6 dB/octave roll-off.
The power gain at 12.6 GHz is MSG/MAG = 15.5 dB and U = 12.4 dB. The CB HBTs
always show higher MSG/MAG than U with an identical layout, as discussed in Chapter
HI.
The RF response of the 15-emitter finger HBTs with the same type of layout is
shown in Figure 5.9. A slightly lower power gain is obtained from these larger area
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103
25
20
K/ISG/MAG
S^o.
15
_c
CO
°
10
10
1 00
Frequency (GHz)
Figure 5.8: Frequency response of 9-emitter finger (As = 403 (im2) CB SiGe/Si HBTs
showing power gain, fmax of 100 GHz is extrapolated based on the
assumption of —6 dB/octave roll-off.
25
20
MSG/MAG
S 15
73.
c
’as
°
10
10
100
Frequency (GHz)
Figure 5.9: Frequency response of 15-emitter finger (As = 672 pm2) CB SiGe/Si HBTs
showing power gain, fmax of 83 GHz is extrapolated based on the assumption
of - 6 dB/octave roll-off.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
104
devices, with M SG/M AG = 14.8 dB and U = 11.5 dB at 12.6 GHz and for an fmax of 83
GHz.
5.6
LARGE-SIGNAL RF CHARACTERISTICS
The 15-emitter finger (Ae = 672 fim2) CB SiGe/Si HBTs have been characterized
with a Focus Microwave source/load pull system. The output power P out, power gain and
the power added efficiency PAE were measured on wafer as a function of input power P in
at 12.6 GHz under CW mode. No special heat dissipation technique or external ballast
resistors were incorporated.
Figure 5.10 shows the power performance of a typical
device, along with the collector current under different bias conditions (class AB). The
CB HBT was biased at Vcb = 6 V and 7 V and Veb = -0.668 V in order to provide class
AB operation. The matching points (7s = 0.71Z1760 and 71 = 0.66Z1210) were
optimized for maximum P ou[. The input matching is very close to the edge of the Smith
chart, indicating the small input impedance. The class AB operation can be seen from the
power gain change with the input power. Smaller power gain values at the low input
power levels are ascribed to the low collector current at the low bias. As the input power
level is increased, the collector current (DC and AC) is also increased and the maximum
power gain is then reached. After that point, the swing of the output signal will be
limited and the increase of the output power is slowed down with the input power.
Therefore, the power gain drops. The highest power gain of 7.88 dB at P,„ of 12.15 dBm
was measured when Vcb is bias at 6 V. The peak PAE of 22.8% was achieved at 0.51 dB
power gain compression. The output power P out at the peak PAE is 21.6 dBm and that at
thel dB gain compression point P-mb is 22.1 dBm. When Vcb is biased at 7 V, slightly
higher Pout 22.3 dBm at the peak PAE (21.5%) was measured with associated power gain
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
105
-|
30
25
§
i
■
i
.
[■
CB15-finger on HBT_3
VEB = -0.668 V
f = 12.6 GHz
n— '— '— >— 1 r
Ts = 0.71 <176°
35
TL= 0 .6 6 < 1 2 1 °
30
25
20
V cb = 6 V
20
CO
®
E
cn
"O
1
o
1 5 1
-
TJ
>
m
To
y
o-
15
io h
10
CL
5 -
o
3
>
5
» • »
10
15
Pin (dBm)
0
20
Figure 5.10: Meaured Pout, Gain, PAE and Ic of 15-emitter finger CB SiGe/Si HBTs
fabricated from structure HBT 3.
of 7 dB. The P-tdB is about 23 dBm (200 mW) and the maximum Pout was measured to be
24.4 dBm. At the quiescent bias point, the collector current is 14 mA and it was driven to
77 and 81 mA at the peak PAE, for Vcb of
6
and 7 V, respectively. The final saturation
power was not measured owing to the DC current limit, which was set to prevent the
device from burning out. No oscillation was observed during measurement. To the best
of the author’s knowledge, these are the first large-signal measurements made on SiGe/Si
HBTs in the Ku-band.
5.7 SUMMARY
In this chapter, the development of the first Ku-band (12.6 GHz) SiGe/Si power
HBTs has been described and discussed. The heterostructure design and device layout
lead to an. fmax of 100 GHz for a 9-emitter finger device with emitter area of 403 fim2. An
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106
fmax of 83 GHz is measured for a larger, 15-emitter finger device of emitter area 672 |im 2.
Under class AB operation and CW mode with Vcb =
6
V, an output power Pout = 21.6
dBm is achieved at a peak PAE of 22.8%, with associated power gain of 7.4 dB. The
output power at thel-dB gain compression point P-idB is 22.1 dBm. When the device is
biased at VCb = 7 V, Pou, of 22.3 dBm at the peak PAE (21.5%) was measured with
associated power gain of 7 dB. The P.mb is about 23 dBm (200 mW) and the maximum
Pout
was measured to be 24.4 dBm. These superior SiGe/Si HBT power performance
characteristics at the highest operation frequency of 12.6 GHz results from a combination
of optimized device heterostructure design and optimized layout, good material quality
and optimized processing techniques.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER VI
LONG-TERM RELIABILITY OF SiGe/Si HBT’S UNDER
ACCELERATED LIFETIME TESTING
6.1
INTRODUCTION
The rapid progress of Si/SiGe heterojunction bipolar transistor (HBT) technology
has made Si-based devices very attractive for microwave applications.
Among the
existing SiGe technologies, Si/SiGe/Si HBTs have been most widely studied [1] [2]
owing to the advantage in material characteristics, such as the near-zero conduction band
offset between Si and strained SiGe layers, which is preferred for npn HBT applications.
The use of a smaller bandgap SiGe alloy in the base of the HBT increases the efficiency
of minority carrier injection. This results in an increase of collector current and current
gain even though the base doping is high. The high base doping yields a smaller base
resistance, which in turn leads to high maximum oscillation frequency fmax, high Early
voltage and low noise figure. However, the p-n junctions in a HBT must be well defined
and coincident with the heterojunctions. Base dopant outdiffiision during epitaxy and/or
during device processing and operation shifts the location of p-n junctions, usually
resulting in the formation of parasitic energy barriers near the base-emitter and basecollector junctions, which can significantly reduce the current gain and cutoff frequency
[36], [37].
107
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108
Device performance is a function of time in general, since the device performance
parameters are liable to change, gradually or abruptly, as the operation time accumulates.
Therefore, excellent performance observed during the initial measurement on a device
does not necessarily guarantee long-term reliability. For the Si/SiGe HBT technology to
be a choice for commercial radio frequency integrated circuits the long-term reliability of
Si/SiGe HBTs has to be proven and, unfortunately, very limited report on this subject
exists in the literature. Neugroschel et al [38] have investigated the time-to-failure of
GeSi bipolar transistors with current-acceleration method in which base-emitter reversebias stress was applied at room temperature.
While this method can significantly
accelerate the degradation of devices and is effective for observing the device
degradation caused by hot carriers, it is not suitable for evaluating the device degradation
caused by atomic diffusion. Another investigation, on the effects of base-emitter reversebias stress on the cryogenic operation of SiGe HBTs, has been reported by Babcock et al
[39]. Specially tailored techniques are required to evaluate the long-term reliability of
devices since it takes impractically long times to observe any appreciable degradation in
the device performance under normal operating conditions. The long-term reliability can
be most effectively evaluated by accelerated lifetime testing (ALT), i.e., measuring the
device lifetime at elevated temperatures under normal bias conditions [40] [41]. Unlike
the current-acceleration method used by Neugroschel et al [38], this ALT method
resembles the real operating condition of HBTs. By extrapolating the HBT lifetimes at
high temperatures from the Arrhenius plot, the mean time to failure (MTTF) of the device
at room temperature can be estimated. The extrapolation is based on the assumption that
the degradation mechanism remains unchanged over the entire temperature range of
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109
testing and the same activation energy applies.
The common sources o f device
degradation are diffusion of dopants, dielectric breakdown, surface or interface ion
migration, metal contact degradation, electromigration of metal lines, etc. In particular,
boron outdiffusion is one of the major concerns in the context of thermal budget in the
fabrication and operation of SiGe/Si HBT, as it leads to the degradation of critical device
parameters as mentioned above [37]. The accelerated lifetime test can be used as an
effective tool to identify the source of degradation. Additionally, analysis of the failure
mechanism can offer valuable feedback on the design of device structures for long-term
reliability of the devices and circuits.
In this chapter, the reliability study of low power SiGe/Si HBTs under accelerated
lifetime testing will be described. It has been found that forward-bias electrical-thermal
stress can induce boron-outdiffusion and associated degradation for double-mesa
structure npn Si/SiGe HBTs. The degradation behavior has been quantitatively modeled,
to the first order of approximation. The device failure mechanism has been analyzed and
its impact on device heterostructure design for improvement of long-term reliability is
discussed.
In what follows, the experimental techniques are described in Section 6.2.
The experimental results will be presented and analyzed in Section 6.3. The REID model
based on low-level injection theory is presented in Section 6.4 and the important results
are summarized in Section 6.5.
6.2
ACCELERATED LIFETIME TESTING TECHNIQUES
The HBTs used in this testing are grown by solid-source MBE. The devices
(Figure 6.1) have a 30 nm boron doped Sio^Geoj base layer with two undoped Sio.7 Geo.3
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110
2 0 0
nm
1 0 0
nm
Emitter cap
Si
n+
Sb
5xl0I9 cnr 3
Emitter
Si
n
Sb
lx l 0
Spacer
Sii-xGex
i
Base
Sii-xGex
P+
Spacer
Sii-xGex
i
Si
n-
Sb
2
x 1 0 16 cm' 3
250 nm
Sub-collector Si
n+
As
2
x l0
cm' 3
1500 nm
lx l 0 l2 cm' 3
540 |im
Collector
= Substrate
Si(100)
P-
18
cm' 3
5 nm
B
6
x 1 0 19 cm' 3
30 nm
5 nm
19
sj
Figure 6.1: Schematic of Si/SiGe HBT, in which the As-doped subcollector layer is
grown by CVD and the rest of the heterostructure is grown by MBE.
spacers of thickness 5 nm on each side of it. Antimony was used to dope the emitter and
collector layers. The epitaxial heterostructures are fabricated into mesa type devices with
5x20 jim 2 emitter size, using standard photolithography and wet and dry etching
techniques. Details of these procedures have been described in Ref. 22. The schematic
cross-section of a finished HBT is shown in Figure 6.2 and the layout is shown in Figure
6.3. The measurement setup used for the lifetime test is briefly described. The device
under test (DUT) was placed on a temperature-controlled hotplate and biased with
collector-emitter voltage Vce and base current Ib in the common-emitter configuration.
Vce, supplied by a Keithley 230 voltage source, was fixed at 3 V, while Ib, supplied by a
Keithley 2 2 0 current source, was feedback-controlled by computer to maintain a constant
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Ill
Interconnect
Cr/Au
n+ Si
Pt/Au
n- Si
Pt/Au
p+ SiGe
i-SiG e
SiO
n- Si
n+ Si
High resistivity substrate
Figure 6.2: Schematic cross-section of a double mesa self-aligned Si/SiGe HBT.
Emitter
Collector
Base
Figure 6.3: Layout of the tested double-mesa type single-finger Si/SiGe/Si HBTs with
emitter area of 5x20 (im2 and no encapsulation layer on the top of
interconnection lines.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
112
collector current Ic of 13.5 mA, which corresponds to a current density Jc of 1.35 xlO 4
A/cm 2 and dissipated DC power Pdiss of 40.5 mW. It is necessary to maintain a constant
collector current level, which can vary with a fixed base current due to the possible
degradation of the current gain during the test, in order to keep a constant electrical stress
condition throughout the entire duration of each test run. A HP2378A multimeter was
included to monitor the collector current levels so that the base current could be adjusted
by feedback-control in case of deviation from the acceptable range. The multimeter was
also used to display the actual value of Vce applied to the devices.
The test was
performed without any interruption, the bias being applied to the devices continuously till
they stopped operating. Post-stress measurements were then made. Identical devices on
the same wafer, which were only subjected to thermal stress without any electrical stress
during each test run are classified as control devices and post-stress measurements were
also performed on these devices. The lifetime tests were performed for several different
hotplate temperatures, ranging from 175 °C to 275 °C.
The corresponding junction
temperatures, 7}, equal to 189.2 °C and 289.2 °C, respectively, and all temperatures in
between were calculated by the expression,
T j = P dissRth+ T amb
(6.1)
where Pdiss is the power dissipation, R,h is the thermal resistance, and Tomb is the ambient
temperature. The thermal resistance of the test device was extracted by the procedure
outlined in Ref. 42. After VBe is measured as a function of DC power dissipation with
increasing Vce and a fixed Ic at room temperature, Vbe is measured as a function of
temperature with both Vce and Ic fixed. The two plots are then combined and a relation
between the temperature and the DC power dissipation is obtained. The slope of this plot
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113
corresponds to the thermal resistance Rth, which was 350 °C/W in this case. It is assumed
in this calculation that the hotplate temperature is close to the junction temperature o f the
device, which is the case for the soft bias used in the measurements.
6.3
Reliability Testing Results and Analysis
It has been observed that the DC current gain, f$, increases initially with time,
which originates from the reduction of recombination in the base region due to the
elimination of interface states and the improvement of ohmic contacts by annealing [40],
[41]. After that /3 decreases continuously with stress time, with a faster reduction at the
initial and the final stages than in the intermediate stage. This behavior is analyzed and
discussed in Section 6.4. Figure 6.4 shows a typical degradation behavior for the tested
HBTs. The constant collector current and the step-like increase of base current are
m anifestations o f the feedback control.
The apparent failure o f the devices is
characterized by a zero P value at the end of the tests as a result of negligible collector
current after the test. The base-emitter and base-collector junction characteristics were
measured after the test and compared with those measured before. The measured results
for the Tj= 204.2 °C case are shown in Figure 6.5. The reverse-biased leakage current of
the base-emitter junction shows an increase after the stress test. The increase in current is
also observed in the low forward bias range (below 0.7 V). An increase in leakage
current across the base-emitter junction after electrical stress tests is commonly observed
in both Si BJTs [43]-[44] and GaAs/AlGaAs HBTs[45]. It is believed to be caused by
interface states created by hot electrons [39], [43] [44] at the base-emitter junction
sidewall. Furthermore, an extra leakage component can be present if the diode ideality
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114
1.2
90
45
T. =
75
0.6
224 °C
0.4
CD
J = 13.5 kA/cm
0.2
—
0.8
COL
03
"§
312
45
o
316
Time (hr)
320
0.6 1
“
0.4
30
0.2
0
120
60
180
300
240
360
Time (hr)
Figure 6.4: Typical degradation behavior for a SiGe/Si HBT. The constant collector
current and step-like base current change with time is the manifestation of
feedback control.
-3
-2.5
-2
-1.5
-1
-0.5
Junction Voltage (V)
0
0.5
1
Figure 6.5: Base-emitter and base-collector junction diode characteristics before and after
accelerated lifetime testing.
Increased leakage current develops at base-
emitter junction in reverse and low forward bias regimes. The reverse bias
leakage current at base-collector junction is reduced.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
115
factor is greater than 2. This originates from hot-electron damage at and tunneling
through the dielectric layer separating the base and emitter contact regions [39]. The
ideality factor of the base-emitter junction in the devices were indeed greater than
2
after
the stress, and therefore the additional tunneling component is expected to contribute to
the total base-emitter leakage current. The reverse leakage current for the base-collector
junction, on the other hand, showed a decrease after the stress was applied. This decrease
is attributed to the reduction in generation current in the base-collector space charge
region as a result of thermal annealing during the stress test [45]. The S-parameters were
also measured before and after the test. While the device exhibited high/ 7 - and/mo* values
before the test, these parameters could not be measured after the test, indicating that fiand fmax were decreased to lower than 2 GHz, the lower frequency limit o f the test
equipment. The rapidly decreasing values of the measured /? near the end of each testing
cycle are a manifestation of the measurement technique. As described in Section 6.2, we
have used the common-emitter biasing mode for the lifetime tests. With a decrease of
DC current gain, the feedback control will increase the base current by increasing the
base-emitter bias voltage VBe in order to keep the collector current constant.
The
increase of Vbe will accordingly decrease the reverse bias voltage VCb available to the
base-collector junction, since the collector-emitter bias Vce is fixed at 3 V. Decrease of
Vcb will expedite further decrease of the current gain. As a consequence,
VBe will be
shifted to even higher values and it finally reaches the pre-set limit of 2 V (measured by
Keithley 230 voltage source). At this point, the base current will not be changed and the
degradation of DC current gain will cause the continual decrease of collector current, till
it reaches a negligible value. At a higher base-collector bias, there should still be some
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116
current gain.
In order to verify this measurement artifact near the end of the tests,
measurements were made on the devices after the test, wherein the HBTs was biased in
common-base mode, such that the base-emitter and base-collector biases can be varied
independently. Figure
6 .6
shows the DC current gain versus collector-base voltage of a
typical device at different base-emitter bias conditions. It can be seen from this figure
that if the base-emitter bias is very small, the collector current is always negligible,
regardless of the base-collector bias, Vcb- Also, the /? values are very small even at
higher values of VbeThe gradual decrease of j5 seen in Figure 6.4 is considered to be the result of boron
outdiffusion and the associated formation of parasitic energy barriers [36], [37]. As
boron outdiffuses from the Sii_xGex base layer into the Si emitter and collector layers, the
p-n junctions move from the Si/SiGe heterojunctions into the Si layers, which broadens
the actual base width.
Since Si has a wider bandgap and lower intrinsic carrier
concentration than Sii_xGex, parasitic energy barriers will be formed near the base-emitter
junction and tum-on voltage of the diode should be increased [39]. Figure 6.7 shows the
forward Gummel plots of an HBT before and after a stress test at 7} = 204.2 °C. In
addition to the development of a base leakage current after the test, the collector current
Ic profile is shifted to higher Vbe values, indicating the increase of device base-emitter
tum-on voltage. The shift of Vbe was measured to be 50 mV at a collector current of
1
(lA. The low current value avoids the effect of series resistances [39]. Similar results
were obtained from the reverse Gummel plots (emitter current Ie shifted to higher Vbc
values). The increase of the tum-on voltages can only be caused by boron outdiffudion.
The Gummel plots measured on the control devices, which are only subjected to thermal
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117
T = 224 °C
BE
CO .
BE
4
V
0
1
BE
= 0.5 V
4
3
2
5
6
VcbM
Figure
6
.6 : DC current gain versus base-collector bias voltage at different base-emitter
biases after accelerated lifetime testing.
T. = 204 °C
CD
1 10-6
Before stress
After stress
c/
1 0 '8
I 50 mV
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Figure 6.7: Gummel plots of a SiGe/Si HBT before and after accelerated lifetime testing.
Base-emitter tum-on voltage increased by 50 mV after the test.
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118
stress without electrical stress, do not show the increase of tum-on voltage. The testing
termperatures (up to 289 °C) are too low to induce thermally activated boron diffusion.
The current gain measured on the control device for each test mn shov/s negligible
change after prolonged thermal stressing. It has been reported that electromigration (EM)
induced compressive stress on the top of the emitter can degrade the dc current gain (3 for
current densities of lxlO 5 A/cm 2 or higher [46]. In this study, the interconnect metal is
not encapsulated (Figure 6.3) and the current density is about two orders of magnitude
lower than the reported values [46]. In addition, the /? degradation behavior observed in
this experiment (Figure 6.4) is different from that caused by compressive stress in the
reported Si-based devices [46].
The distinct behavior observed in EM induced J3
degradation is a double minimum in the value of (3 with increasing stress (or time) [46].
However, this trend was not observed in this study, in spite of data being recorded at time
intervals of 30 minutes. We therefore believe that the EM induced (3 degradation
mechanism is not operative in these devices.
Defining 50% j3 degradation as the failure criteria, the MTTF was found to be
1.9xl0 7 hours with an activation energy of 0.77 eV. The Arrhenius plot of the lifetimes
versus reciprocal of test temperatures is shown in Figure 6 .8 .
6.4
An Analytical Model for Recombination-Enhanced Impurity Diffusion (REID)
Since boron outdiffusion occurs during the testing, a further step was taken to
analyze the outdiffusion-related gradual degradation behavior with a simple diffusion
model as outlined below. All the analysis is based on low-level injection theory, since
the base-emitter bias dining the gradual P degradation is about 0.6-0.7 V.
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119
In an npn SiGe HBT, the collector current density Jc, assuming absence of hotelectron effects, can be expressed as [47]:
J c —q
Jo n?(x)Dn(x)
e “■,
(6 .2 )
where Wb is the neutral base width, Vbe is the base-emitter voltage, p(x) is the base
doping, Dn(x) is the minority carrier diffusion coefficient and nrfx) is the intrinsic carrier
concentration of SiGe base, respectively. Assuming that the base current is generated
Me
only by hole injection from base into emitter, it is modeled as [48] J B = J BQe kT and the
analytical current gain takes the form:
,8
=i c =_gJ> . / M
&
J B J bo Jo n?(x)Dn(x)
(6.3)
Vox simplicity, it is assumed that the germanium and boron profiles in the base region are
box-like, as shown in Figure 6.9. Therefore, expanding the integral in Eq. 6.3 to include
the out-diffused regions, we get,
q (f
J BO
pm
J-Aivv
\n
- ^ n n^2x( )r D
A + rI 'r 'l
n(x)
Jo
rt 2 f y \ n f
nf2{x)Dn(x)
dx
Jw„
^ (x )D „ (x )
,
(6-4)
where AWE and AWC are outdiffused region widths, as shown in Figure 6.9. In this
analysis it is assumed that the dopant atoms are fully ionized, i.e., p(x) = NA, over the
base and out-diffused regions and the diffusion coefficient Dn(x) is also constant over this
region. If the parasitic energy barriers caused by the boron atom outdiffusion from base
to both emitter and collector regions are AE ‘b and AE cb , respectively, Eq. 6.3 can be
rewritten as:
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120
10'
1 0
g
'
10
1 0
'
1.8
2
2.2
2.4
2.6
2.8
3
3.2
1000/T (1/K)
Figure 6 .8 : Arrhenius plot for lifetime of the Si/SiGe/Si HBTs. M7TF(300K) = 1.9xl0 7
hours, <P=0.77 eV.
Emitter
(n-doped)
Collector
(n-doped)
Base
e
Outdiffused
boron
_o
*—
*
53
u,
C
4O>
c
Boron
o
U
ac
c
'S.
o
Q
w B+AWc
-AWc
Depth
Figure 6.9: Model for boron outdiffusion from base layers into adjacent emitter and
collector layers due to electrical-thermal stress.
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121
— ^
p _ qDnn f (SiGe) f 1 + ^AW
2 L e ^*r + ^AW
! I c <s*r
W
J N
WB
yY B J B 0 I y A
(6.5)
Assuming that no boron outdiffusion has occurred at the onset of accelerated lifetime
j-y
testing, then /? =
/? 0
=
^2
/
£
at t = 0 , and therefore the normalized current gain
W BJ bqN A
degradation due to outdiffusion-induced base width broadening can be expressed as
A
f
H
Po
AW£
AWC
—e kT H
—e kT
WB
Ws
( 6 .6 )
This equation is used to analyze the measured degradation of current gain /? with stress
time. In this work it is assumed that AW s= AWc = AL = ^ D st , where Ds is the effective
boron diffusion constant and t is the stress time.
Thus the desired (3(t) relation is
obtained. Ds can be expressed as [49]
ea
where D;»(°)’ and D;
n = D-0) + D (+) V
,
(6.7)
ni
are the diffusion coefficients of boron-neutral-point-defect pairs
and of boron-positively-charged-point-defect pairs, respectively. EA is a bandgap and
doping related activation energy.
Originally, values of Dj0) and D\+) at the above
testing temperatures were extrapolated from those obtained in the literature [50] in this
analysis. However, it is noted here that the diffusion coefficient, Dj+), is enhanced by a
factor of 106 under bias conditions. Similar results were reported in the reliability tests of
Be doped GaAs Esaki tunnel diodes [51]. The values of AE eb and AE cb are computed
from the changes in Fermi levels produced by the boron outdiffusion. The decrease in
the Sii.xGex bandgap, AEg, with composition is calculated from [52], [53], AEg =0.85x.
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122
experiment
1.0
calculation
0.9
\
T. = 189 °C
CO .
*
N
75
I
:z
0.8
0.7
T = 204 °C
:
T. = 224 °C
0.6
0.6
0
200
400
600
800
1000
Time (hr)
Figure 6.10: Measured (solid lines) and calculated (dashed lines) normalized current gain
of Si/SiGe/Si HBTs as a function of stress time for different junction
temperatures.
Finally, it is important to note that the heavy doping level in the base and out-diffused
regions will cause bandgap narrowing, which can be approximately expressed by the
empirical equation [54], [55], AE d = E0 In' X
'1
, where E0 =18 meV and iVj=101 7 cm'3.
The calculated variation of current gain with stress time is shown in Figure 6.10
alongside measured data for several stress temperatures. The agreement of the calculated
results at the initial and the intermediate stages of each test run is fairly good, indicating
that the device degradation at each testing temperature is due to boron outdiffusion. As
mentioned before, the failure at the end of a test run is defined by different processes.
In formulating the diffusion model described above and utilizing it to analyze the
experimental data, it was found that the diffusion coefficient of boron-positively-charged-
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123
point-defect pairs
( P i +>)
was enhanced by
6
orders under bias conditions.
This
anomalous behavior of the boron dopant is attributed to recombination-enhanced
impurity diffusion (REID), which is reported in Be-doped GaAs [51]. For boron-doped
npn Si/Sii_xGex/Si HBTs under forward active bias, electrons are injected from the
emitter into the base. A fraction of the injected electrons will be captured by traps and
recombination centers. The excess energy of the electrons is released non-radiatively and
transferred to boron atoms, thereby enhancing their vibration and diffusivity. Because of
the high efficiency of the non-radiative energy transfer, the enhancement of boron
diffusivity should be more significant than thermally activated diffusion. This explains
why a control device, under the same thermal stress but without electrical stress, shows
negligible DC current gain degradation. Similar results were reported from reliability
tests on Be-doped GaAs/AlGaAs HBTs [45]. However, this low-level injection based
model is the first analytical REID model for this diffusion process. From the analysis and
the modeling process, it is appropriate to expect a more rapid degradation of SiGe/Si
HBTs at higher stress current levels.
The reliability study offers valuable feedback to device heterostructure design. In
practical applications, devices are usually driven at high current density for the purpose
of obtaining high speed or high power.
In order to minimize Si/Sii_xGex/Si HBT
degradation under such operating conditions, it is imperative to reduce or eliminate
recombination-enhanced dopant outdiffusion from the base. In this context, a SiGeC
base region in npn Si/Sii_xGex/Si HBTs might perform better since it has been reported
that carbon can successfully reduce boron outdiffusion at elevated temperatures [56]. A
self-aligned mesa structure can reduce the parasitic base resistance.
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However, if the
124
separation between emitter and base contact regions is too small, the dielectric
passivation in between may be cause for concern. In reality, a trade-off exists between
HBT performance and long-term reliability issues.
6.5
Summary
A detailed study of forward-bias electrical-thermal stress induced degradation of
Sii-xGex/Si HBTs is presented. From the extrapolation of the Arrhenius plots of device
lifetime versus reciprocal temperature the mean time to failure (MTTF) of these devices
at room temperature, under 1.35 xlO4 A/cm 2 current density operation, is estimated to be
1.9xl0 7 hours with activation energy of 0.77 eV.
In these devices the gradual
degradation is mainly caused by recombination enhanced boron outdiffusion from the
base layer. An analytical REID model was formulated based on the low-level injection
theory. Good agreement of the gradual degradation behavior is obtained with calculated
results based on this model which takes into account base dopant outdiffusion and the
associated formation of parasitic energy barriers.
A SiGeC base layer design will
probably reduce boron outdiffusion and improve the long-term reliability of these
devices.
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CHAPTER VH
CONCLUSIONS AND
SUGGESTIONS FOR FUTURE RESEARCH
7.1 CONCLUSIONS
The work outlined in this thesis was aimed at the development of high power SiGebased HBTs for microwave power amplification at high frequency bands (X- and Kuband), the realization of MMIC power amplifiers with high power SiGe/Si HBTs at Xband frequency and the investigation the long-term reliability and degradation
mechanisms of SiGe/Si HBTs.
In order to achieve high power operation of SiGe/Si HBTs at microwave
frequencies, the device heterostructure and layout have to be well designed with the
simultaneous consideration of high-speed operation and high-power handling capability.
From the present study, it is concluded that a thick and lightly doped collector layer is
favorable for both high-speed and high-power operation. Furthermore, employing a high
operating voltage combined with a low current density is more beneficial than employing
a low operation voltage combined with a high current density. The thermal effects
associated with high power operation can be efficiently minimized with a distributed
layout, which is required for high-efficiency power amplification.
A double-mesa
process developed for the SiGe/Si HBTs has been described, together with the critical
125
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126
processing techniques that ensure reliable fabrication with high performance and high
process yield. Two heterostructures were designed and grown by one-step CVD and a
distributed layout was utilized. The fabricated large-area power SiGe/Si HBTs show
breakdown voltages of 23 V BV ceo and 26 V BV cbo and associated 40 GHz and 74 GHz
offmax for CE and CB HBTs, respectively. State-of-the-art power performance at X-band
(8.4 GHz) was achieved from the fabricated SiGe/Si HBTs. 25.9 dBm Pout was obtained
from 10-finger (Ae = 780 pm2) CE HBTs at a peak PAE of 28.2% with the associated
power gain of 5.4 dB. 10-finger CB HBTs provide 25 dBm Pout at a peak PAE of 40.4%
with associated power gain of
8 .6
dB.
The highest PAE of 42.1% was achieved at
slightly lower bias levels. 20-finger SiGe/Si HBTs (AE = 1560 pm2) demonstrated the
highest Pout at the peak PAE, 27.4 dBm (550 mW) for both CE and CB configurations.
Peak PAE of 26.3% and 32% were measured for 20-finger CE and CB HBTs,
respectively. The associated power gain at the peak PAE for CE and CB HBTs are 4 dB
and 7 dB, respectively. With 25% PAE, 20-finger HBTs are able to provide 28.45 dBm
(700 mW) Poul, which is equivalent to a RF power density of 0.58 mW/p.m2. The highest
power density was measured to be 0.96 mW/pm 2 from a 4-finger CE HBTs.
The
superior SiGe/Si HBT power performance results from a very low base resistance, high
device breakdown voltages and good thermal stability of the device at very high power
levels, which are further ascribed to a combination of device heterostructure design and
optimized layout, good material quality.
The relationship between the DC and RF
characteristics has been discussed.
The first implementation of SiGe HBT-based X-band MMIC single-stage power
amplifier under class A operation with the incorporation of on-chip lumped passive
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127
components has been described. The amplifier design was initiated with large-signal
modeling of SiGe/Si power HBTs using the conventional Gummel-Poon model and the
equivalent circuit modeling of the spiral inductors and MIM capacitors. Good accuracy
has been achieved from this modeling process and the interplay of the Kirk effect and the
Early effect at high bias levels is addressed for the first time.
The MMIC power
amplifier was successfully fabricated with 11 mask levels. At 8.4 GHz, the MMIC power
amplifier exhibits an output power of 23 dBm at peak PAE, 12%, and a saturation output
power of 25 dBm. Higher PAE (16%) was also observed when the circuit was biased for
this purpose. The analysis of the power amplifier circuit shows that the resistive loss in
the passive components accounts for the major loss in the MMIC.
In further development of Ku-band (12.6 GHz) high power SiGe/Si HBTs, the
HBT heterostructure, layout and process were modified in order to provide high power
gain with large-area devices at the desired operation frequency. Suitable modification of
the device heterostructure and the use of MBE growth, which enabled higher doping
concentrations in the emitter and base regions, variable thicknesses of the two undoped
spacer layers and more abrupt interfaces between layers have been immensely helpful.
Emitter finger widths of 1 pm and 1.4-1.5 pm were adopted in the layout design for the
purpose of reducing base resistance. In order to isolate the device active area from the
contact area, for reducing parasitics, reliable air bridges were designed in the layout for
all three-electrode connections. A new fabrication process was developed for the reliable
fabrication of HBTs with 1 pm feature emitter size, with the reduction of the emitter
undercut by isotropic dry etching. The new process reduces the base resistance, the base-
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128
collector junction capacitance and the parasitics and, therefore, enabling high frequency
performance of the SiGe/Si power HBTs.
A n fmax of 100 GHz was obtained for a 9-emitter finger device with emitter area of
403 (im2. This is the highest
for a large area (Ae > 1 0 0 jim2) SiGe/Si HBT till date.
An fmax of 83 GHz is measured for an even larger (672 (im2), 15-emitter finger device.
The large-signal measurements made at 12.6 GHz on these devices demonstrated the
realization of the first Ku-band SiGe/Si power HBT. Under class AB operation and CW
mode with Vcb =
6
V, 21.6 dBm Pout is achieved at the peak PAE of 22.8%, with
associated power gain of 7.4 dB.
The output power at thel-dB gain compression point
P.idB is 22.1 dBm. When the device is biased at Vcb = 7 V, Pou[ of 22.3 dBm at the peak
PAE (21.5%) was measured with associated power gain of 7 dB. The P-ub is about 23
dBm (200 mW) and the maximum Pout was measured to be 24.4 dBm. These superior
power performance characteristics at the operation frequency of 12.6 GHz results from a
combination of device heterostructure design and optimized layout and optimized
processing techniques.
Since long-term reliability is of concern for practical applications of SiGe/Si
HBTs, a detailed study of forward-bias electrical-thermal stress induced degradation of
Sii.xGex/Si HBTs has been conducted. From the extrapolation of the Arrhenius plots of
device lifetime versus reciprocal temperature (environmental temperature: 175 —275 °C)
the mean time to failure (MTTF) of these devices at room temperature, under 1.35 xlO4
A/cm 2 current density operation, is estimated to be 1.9xl0 7 hours with activation energy
of 0.77 eV. It was found that the gradual degradation is mainly caused by recombination
enhanced impurity diffusion (REID) of the boron atoms from the base layer into the
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129
adjacent emitter and collector layers. An analytical REID model was formulated, for the
first time, based on the low-level injection theory.
Good agreement of the gradual
degradation behavior is obtained with calculated results based on this model, which takes
into account base dopant outdiffusion and the associated formation of parasitic energy
barriers.
In summary, large-area high power SiGe/Si HBTs operating at X-band (8.4 GHz)
with state-of-the-art power performance have been designed, fabricated and characterized
associated with high fabrication yield and repeatability. The first Ku-band (12.6 GHz)
SiGe/Si power HBT has been brought into reality with high performance characteristics.
The first X-band (8.4 GHz) SiGe HBT-based MMIC power amplifier has been realized
with on-chip lumped passive components as the passive devices.
The degradation
mechanism of SiGe/Si HBTs under accelerated lifetime testing has been analyzed, with
the first discovery of the REID process in SiGe-based HBTs. The first analytical model
on the basis of the low-level injection theory has been developed for the REID process.
7.2
SUGGESTIONS FO R FUTURE RESEARCH
Although the SiGe/Si HBTs developed in this study demonstrate state-of-the-art
performance characteristics, there is room for improvement. For example, the thermal
effects can be further reduced for larger area devices by optimizing the extent of the
layout distribution and the number of emitter fingers that are grouped in a subcell. These
efforts are particularly important for very large device areas. The option of wafer backthinning or incorporation of a thermal shunt with thick and larger-area interconnect metal
on top of the active device region is also worth trying. By reducing the thermal effects,
the RF response o f large area devices will approach that of smaller devices.
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130
In the development of power amplifier circuits new circuit topologies should be
considered to improve performance beyond what has been achieved here. The Q-factor
o f the lumped passive components can be improved by improving processing. Highefficiency power amplification is of great importance in wireless communication, which
will require higher class of amplification with the active devices and new circuit design
techniques. The large-signal modeling of SiGe/Si HBTs with the conventional GummelPoon model is applicable only for class A operation and its validity for higher classes of
operation has not been demonstrated in this study. Other large-signal models may help to
solve this problem. Power combining is one of the ways to increase the output power of
a power amplifier circuit. With the increase of device area, the matching circuit design
becomes more difficult and power combining for these large devices needs to studied and
implemented.
The reliability of the SiGe/Si HBTs was investigated on small devices in this
study. High power applications may induce a different degradation mechanism in the
multi-finger SiGe/Si HBTs. It is important to test the SiGe/Si HBT reliability at high bias
levels and analyze the degradation/failure mechanism.
The REID degradation
mechanism may be reduced with a SiGeC base layer, since it has been proven that carbon
incorporation in the base region reduces boron outdiffusion at elevated temperatures [56].
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131
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