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Novel RF and microwave components employing ferroelectric and solid -state tunable capacitors for multi-functional wireless communication systems

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NOVEL RF AND MICROWAVE COMPONENTS EMPLOYING
FERROELECTRIC AND SOLID-STATE TUNABLE CAPACITORS FOR
MULTI-FUNCTIONAL WIRELESS COMMUNICATION SYSTEMS
by
Ali Tombak
A dissertation submitted in partial fulfillment
of the requirements for the degree of
Doctor o f Philosophy
(Electrical Engineering)
in The University o f Michigan
2004
Doctoral Committee:
Associate Professor Amir Mortazawi, Chair
Professor Anthony W. England
Professor Kamal Sarabandi
Professor Wayne E. Stark
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UMI Number: 3150111
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©
Ali Tombak
-----------------------------
All Rights Reserved
2004
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DEDICATION
This thesis is dedicated to my wife, Pakize Kuaybe Tombak, for her undying love,
support and encouragement.
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ACKNOWLEDGMENTS
I would like to first express my deepest appreciation to my advisor, Professor Amir
Mortazawi, for his relentless support, encouragement, and guidance during my graduate
study. I have certainly learnt a great deal o f experience from him both professionally and
socially, which will benefit me throughout my future career and life. I also would like to
thank Professor Anthony W. England, Professor Kamal Sarabandi and Professor Wayne
E. Stark for their valuable support, advise and time by being on my committee.
I would like to thank Professor Angus I. Kingon, Professor Jon-Paul Maria, Dr.
Francisco Tito Ayguavives, Dr. Gregory T. Stauf, Dr. Zhang Jin, and Dr. Michael Brand
for their support, assistance and valuable discussions in the Frequency Agile Materials
for Electronics (FAME) program.
I would like to acknowledge Defense Advanced Research Project Agency (DARPA),
Army Research Labs (ARL), National Science Foundation (NSF), and the University of
Michigan for proving me with the financial support throughout my graduate study. I also
want to acknowledge Rogers Corporation, Metelics Inc., MACOM Inc., and Dielectric
Laboratories Inc. for sending me free samples o f their products that I used in my circuits.
I hope that the friendships I have made during the course of this study will stay for
years. I wish them all the best o f luck in their lives. I would like to thank Ibrahim Sahin,
Steve Lipa, Bryan McChesney, Mete Ozkar, Ayman Al-Zayed, Xin Jiang, Hakan
Yazarel, my cousin Mehmet Ozdemir, A rif Kurt, Sean Ortiz, Mustafa Dagtekin, Rizwan
iii
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Bashirullah, Yolkan Ozdemir, Muharrem Asar, Ugur Mertyurek, Adam Martin, Eray
Yasan, Adib Nashashibi, Adem Saglik, Mohamed Abdel-Moneum, Reza Azadegan,
Navin Gupta, Jonghoon Choi, Lora Schulwitz, Jia-Shiang Fu, Alfred Zhu, Farshid
Aryanfar, Abbas Abbaspour-Tamijani, Lee Harle, Kevin Buell, Nader Behdad,
Christopher Galbraith, Jad Rizk, Kamran Entesari, Mark Casciato, Timothy Hancock,
and many others. Many thanks are due to the RADLAB and department staff for their
support and help over the years, Beth Stalnaker, Karen Kirchner, Mary Eyler, and Susan
Chamley.
Finally, I would like to thank my parents, Zeynep and Osman, parent-in-laws, Yuksel
and Muzaffer, my sister, Belkis, and other family members who are far away from here.
They have patiently supported me to achieve this important goal in my life, which will
make them proud. Most importantly, my beloved wife, Pakize Kuaybe Tombak. She has
been the source o f relentless love, happiness and relief. She has shared my joys and
sorrows during these difficult times. Without her support, understanding and
encouragement, my life would have been much more difficult and stressful.
Ali Tombak
September 16, 2004
Ann Arbor, Michigan USA
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TABLE OF CONTENTS
DEDICATION.......................................................................................................................................................ii
ACKNOWLEDGMENTS...................................................................................................................................iii
LIST OF TABLES............................................................................................................................................. vii
LIST OF FIGURES.......................................................................................................................................... viii
LIST OF APPENDICES...................................................................................................................................xiv
CHAPTERS
1
INTRODUCTION................................................................................................................................ 1
1.1. A n O verview
of
V aractor T echnologies ............................................................................5
1.1.1. Varactor D iodes...................................................................................................................5
1.1.2. MOS Varactors.................................................................................................................... 8
1.1.3. MEMS Varactors.............................................................................................................. 10
1.1.4. Ferroelectric Varactors....................................................................................................11
1.2. C ontributions
2
and
Thesis O v e r v ie w ................................................................................... 16
TUNABLE RF/MICROWAVE FILTERS USING
BARIUM STRONTIUM
TITANATE BASED TUNABLE CAPACITORS.........................................................................18
2.1. In t r o d u c tio n .................................................................................................................................. 18
2.2. F abrication of BST V a r a c t o r s ..............................................................................................19
2.3. M easurem ents
and
M odeling
of
BST V a r a c t o r s .........................................................23
2.3.1. Large Signal Measurements o f BST Varactors....................................................... 28
2.4. T una ble L um ped Element VHF F il t e r s ..............................................................................37
2.4.1. Tunable Lumped Element Lowpass Filters.............................................................. 37
2.4.2. Tunable Lumped Element Bandpass F ilter.............................................................. 40
2.4.3. Intermodulation Distortion Characterization o f the Tunable F ilter................... 46
2.5. C o n c lusion s .................................................................................................................................... 48
3
EXTENDED RESONANCE PHASED ARRAYS EMPLOYING VARACTORS............... 50
3.1. In t r o d u c tio n .................................................................................................................................. 50
3.2. T h e o r y ............................................................................................................................................... 52
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3.2.1. Maximum Achievable Scan R a n g e.............................................................................58
3.2.2. Effect o f Varactor Quality Factor on the Phased Array E fficien cy....................61
3.3. D esign
of a
T wo GH z Phased A r r a y ....................................................................................63
3.3.1. Microstrip Antenna D e sig n ........................................................................................... 64
3.4. D esign of L arger E xtended R esonance P hased A r r a y s ............................................71
3.4.1. Array Factor Simulation................................................................................................. 84
3.4.2. Symmetrically Fed Tapered Extended Resonance Phased A rrays.....................87
3.4.3. Maximum Array S iz e ......................................................................................................92
3.4.4. Other Topologies for Matching N etworks.................................................................96
3.4.5. D esign with Reduced Number o f Varactors............................................................. 96
3.4.6. Bandw idth..........................................................................................................................97
3.5. D esign
of a
T en GH z P hased A r r a y ................................................................................... 101
3.6. C o n c lusion s ...................................................................................................................................104
4
P O W E R A M P L IFIE R L IN E A R IZ A T IO N U SIN G A V A R A C T O R ...........................................105
4.1. In t r o d u c tio n ................................................................................................................................ 105
4.2. A n O verview
of
P ower A mplifier L inearization T echniq ues ................................ 107
4.2.1. Feedforward Linearization.......................................................................................... 107
4.2.2. Feedback Linearization................................................................................................ 108
4.2.3. Predistortion Linearization.......................................................................................... 110
4.3. D esign of a V aractor B ased P redistortion L inearizer ...........................................113
4.3.1. Effect o f Large RF Signal on Varactor Capacitance............................................113
4.3.2. Operation o f the Varactor Based Predistortion Linearizer................................. 118
4.3.3. Intermodulation Distortion and Adjacent Channel Power Ratio
Simulation Results..........................................................................................................124
4.4. M easurem ent Re su lt s .............................................................................................................. 132
4.5. C o n c lu sio n s .................................................................................................................................. 137
5
C O N C L U SIO N S A N D FU TU R E W O R K ...............................................................................................139
5.1. C o n c lusion s ...................................................................................................................................139
5.2. F uture W ork D ir ec tio n s .........................................................................................................141
5.2.1. Tunable RF/Microwave Filters Based on Ferroelectric Varactors...................141
5.2.2. Extended Resonance Phased A rrays........................................................................ 142
5.2.3. Tunable Resonator Based Predistortion Linearizers............................................. 142
A P P E N D IC E S .....................................................................................................................................................................143
B IB L IO G R A P H Y ..............................................................................................................................................................148
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LIST OF TABLES
Table 1.1:
A brief overview o f varactor technologies............................................................................................. 16
Table 3.1:
Varactor C-V values and Q factor at 2 GHz with via holes and bond w ires................................ 64
Table 3.2:
The measured performance o f the phased array................................................................................... 69
Table 3.3:
Basic design parameters for the phased array....................................................................................... 86
Table 3.4:
Resulting component values for the phased array................................................................................86
Table 3.5:
Basic design parameters for the phased array in Figure 3.33........................................................... 91
Table 3.6:
Resulting component values for the phased array in Figure 3.3 3 ....................................................92
Table 3.7:
The design values for a 30 antenna extended resonance phased array with various
amplitude tapers (half design parameters are given, the second half o f the phased
array is designed symmetrically)............................................................................................................. 94
Table 3.8:
The design values for a 40 antenna extended resonance phased array with various
amplitude tapers (half design parameters are given, the second half o f the phased
array is designed symmetrically)............................................................................................................. 95
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LIST OF FIGURES
Figure 1.1:
(a) Unbiased pn-junction (b) reverse biased pn-junction (c) forward biased pnjunction..............................................................................................................................................................7
Figure 1.2:
Typical capacitance vs. voltage (C-V) curve for a commercially available varactor
diode (M GV125-20, M etelics Inc.)...........................................................................................................7
Figure 1.3:
A typical pMOS capacitor............................................................................................................................ 9
Figure 1.4:
Typical tuning characteristics for a pMOS capacitor.......................................................................... 10
Figure 1.5:
A typical MEMS varactor...........................................................................................................................11
Figure 1.6:
A B 0 3 perovskite unit cell (not to scale)..................................................................................................14
Figure 1.7:
(a) Ferroelectric phase (below Tc), (b) Paraelectric phase (above Tc) ........................................... 15
Figure 1.8:
The C-V curve for a typical BST capacitor............................................................................................15
Figure 2.1:
Schematic illustration o f the parallel plate BST capacitors............................................................... 21
Figure 2.2:
The description o f the multilayer ground plane BST capacitor........................................................22
Figure 2.3:
Small signal measurement setup............................................................................................................... 23
Figure 2.4:
A typical probe contact for the BST capacitors.................................................................................... 24
Figure 2.5:
The equivalent circuit model for the BST capacitor............................................................................25
Figure 2.6:
Relative permittivity vs. applied DC voltage for BST between 45 and 500 MHz
(The BST thickness is 700 A and the top electrode size is 50x50 pm 2) ....................................... 27
Figure 2.7.
The quality factors, Qtotai(measured)s Q bst? Qcomiucior, Qtotai(modei) for a BST capacitor at 0
V DC bias.......................................................................................................................................................28
Figure 2.8:
Large signal measurement set-up............................................................................................................. 29
Figure 2.9:
Measured C-V curve for large RF signal amplitudes (f=50 MHz, the BST thickness
is 700 A, and the top electrode size 50x50 pm2) .................................................................................31
Figure 2.10: Measured and m odeled C-V curve for the BST varactor used in Figure 2 .9 ................................34
Figure 2.11: Time domain current flowing through the BST varactor for various RF signal
amplitudes......................................................................................................................................................34
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Figure 2.12:
Time domain voltage across the BST varactor for various RF signal amplitudes.................... 35
Figure 2.13:
Current through the BST varactor at harmonic frequencies as a function o f total RF
voltage across the BST varactor.............................................................................................................. 35
Figure 2.14:
Voltage across the BST varactor at harmonic frequencies as a function o f total RF
voltage across the BST varactor.............................................................................................................. 36
Figure 2.15:
Simulated C-V curve for large RF signal amplitudes for the BST varactor shown in
Figure 2.9 (f=50 M H z)............................................................................................................................... 36
Figure 2.16:
0 V DC capacitance as a function o f the RF voltage amplitude for the BST varactor
shown in Figure 2 .9..................................................................................................................................... 37
Figure 2.17:
A prototype 3rd order tunable lowpass filter........................................................................................ 39
Figure 2.18:
The measured insertion loss and the return loss o f the 3rd order lowpass filter with
changing the DC bias voltage................................................................................................................... 39
Figure 2.19:
The 5th order tunable lowpass filter........................................................................................................39
Figure 2.20:
The measured insertion loss and the return loss o f the 5th order lowpass filter with
changing the DC bias voltage...................................................................................................................40
Figure 2.21:
A 3rd order tunable bandpass filter prototype...................................................................................... 42
Figure 2.22:
Inversion o f series LC to parallel LC using impedance inverters..................................................42
Figure 2.23:
The complete circuit o f the tunable bandpass filter (The quality factors o f the
inductors are given at 200 M H z)............................................................................................................. 43
Figure 2.24:
A photograph o f the constructed filter.................................................................................................. 43
Figure 2.25:
(a) The insertion loss and (b) the return loss o f the new bandpass filter with the
higher Q BST capacitors and inductors................................................................................................. 45
Figure 2.26:
Measurement setup for the intermodulation distortion.....................................................................47
Figure 2.27:
Spectrum observed in the spectrum analyzer...................................................................................... 47
Figure 3.1:
Conventional phased array concept........................................................................................................52
Figure 3.2:
Extended resonance concept incorporating N-ports.......................................................................... 53
Figure 3.3:
The extended resonance based phased array concept........................................................................53
Figure 3.4:
A more realizable extended resonance based phased array............................................................. 56
Figure 3.5:
Simulated array factor for a 4-antenna extended resonance phased array (antennas
are X/2 apart, varactor tunability is 4:1, the circuit is assumed to be lossless)............................56
Figure 3.6:
Extended resonance phased array for two dimensional scanning.................................................. 57
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Figure 3.7:
The achievable phase shift between successive power divider ports for various
varactor tunabilities..................................................................................................................................... 60
Figure 3.8:
Maximum achievable phase shift and scan range versus varactor tunability.............................60
Figure 3.9:
Cascaded extended resonance phased array for higher scan range............................................... 61
Figure 3.10:
Equivalent circuit model for the varactor............................................................................................. 62
Figure 3.11:
Simulated array feed efficiency versus varactor quality factor for N =4 antennas.....................63
Figure 3.12:
Microstrip patch antenna layout and dimensions...............................................................................66
Figure 3.13:
A photo o f the phased array (array dimensions are 15.4x9.8 inch2) ............................................. 67
Figure 3.14:
Measured H-plane pattern for various diode voltages (measured gain at 30 V is 8.7
dB )....................................................................................................................................................................69
Figure 3.15:
Measured scan angle and array feed efficiency versus the diode voltage (varactor
tunability is 3.2:1 from 3 V to 30 V )...................................................................................................... 70
Figure 3.16:
Measured return loss for various diode voltages................................................................................ 70
Figure 3.17:
Normalized inductor value as a function o f x (tmax=4) ..................................................................... 74
Figure 3.18:
Inductor tunability vs. varactor tunability............................................................................................ 74
Figure 3.19:
Extended resonance section incorporating a fixed inductor............................................................ 75
Figure 3.20:
Real and imaginary parts o f the input admittance in Figure 3.19 compared with the
first stage’s capacitance and antenna input conductance as a function o f x ................................ 75
Figure 3.21:
Magnitude and phase o f the voltage ratio between the 2nd and 1st nodes as a function
o f x ................................................................................................................................................................... 76
Figure 3.22:
Extended resonance section after the 2nd antenna is added..............................................................78
Figure 3.23:
Real part o f the input admittance in Figure 3.22 compared with the first stage’s
antenna input conductance as a function o f x ...................................................................................... 78
Figure 3.24:
LC-matching network transforming the admittance to the first antenna admittance............... 79
Figure 3.25:
Real and imaginary parts o f the input admittance in Figure 3.24 compared with the
first stage’s capacitance and antenna input conductance as a function o f x ................................ 79
Figure 3.26:
The extended resonance phased array concept utilizing a single value varactor
throughout the w hole design..................................................................................................................... 82
Figure 3.27:
Real and imaginary parts o f the input admittance for N =20 antenna phased array.................. 82
Figure 3.28:
The ratio o f the powers delivered to adjacent antennas as a function o f x (N=20
antennas).........................................................................................................................................................83
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Figure 3.29:
Phase o f the voltage ratio between adjacent nodes as a function o f x (N=20
antennas).........................................................................................................................................................83
Figure 3.30:
Simulated array factor for a 20 antenna phased array....................................................................... 85
Figure 3.31:
Simulated array factor for a 20 antenna phased array with ideal amplitude and phase
distribution.....................................................................................................................................................85
Figure 3.32:
The symmetrically fed extended resonance phased arrays.............................................................. 88
Figure 3.33:
Simulated array factor for a 20 antenna phased array with 40 dB Chebyshev taper................ 91
Figure 3.34:
Extended resonance phased array design with reduced number o f varactors.............................97
Figure 3.35:
Simulated return loss for various scan angles..................................................................................... 99
Figure 3.36:
Simulated 0 degree array factors at various frequencies.................................................................. 99
Figure 3.37:
Simulated -6 degree array factors at various frequencies...............................................................100
Figure 3.38:
Simulated -12 degree array factors at various frequencies............................................................ 100
Figure 3.39:
10 GHz microstrip patch antenna layout and dimensions.............................................................. 102
Figure 3.40:
A photograph o f the 10 GHz 8 antenna extended resonance phased array............................... 103
Figure 3.41:
Measured H-plane pattern o f the 10 GHz 8-antenna phased array..............................................103
Figure 4.1:
(a) Gain and (b) phase vs. input power relationship for a typical power amplifier.................106
Figure 4.2:
Feedforward linearization concept....................................................................................................... 108
Figure 4.3:
Indirect feedback linearization concept.............................................................................................. 109
Figure 4.4:
Cartesian feedback linearization concept........................................................................................... 110
Figure 4.5:
Predistortion linearization concept.......................................................................................................111
Figure 4.6:
Small signal C-V curve for a typical varactor diode (Cj0= l 32 pF, Vo=0.84 V ).......................116
Figure 4.7:
Instantaneous capacitance for the varactor in Figure 4.6 for an applied reverse bias
RF voltage o f V(t)=VDC+A*sin(cot) (V DC=5 V , A=5 V, f=50 M H z)...........................................116
Figure 4.8:
Current through the varactor in Figure 4.6 and through a BST capacitor for various
RF signal amplitudes (V RF=2, 3 ,4 , 5 V) (f=50 MHz, V DC=5 V, C BSt ( 0 V )=50 pF)............... 117
Figure 4.9:
Capacitance as a function o f the RF voltage amplitude for the varactor diode shown
in Figure 4.6 (V dc= 5 V )........................................................................................................................... 117
Figure 4.10:
Schematic illustration o f the varactor based predistortion linearizer.......................................... 118
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Figure 4.11:
Magnitude o f S2] vs. frequency for a varactor diode based predistortion linearizer at
two different input RF power levels (R=34 G, L=18 nH, Z0= 50 f l, Cj0= l pF,
V o=0.84 V, V dc= -3 .6 V ).......................................................................................................................... 121
Figure 4.12:
Phase o f S2i vs. frequency for a varactor diode based predistortion linearizer at two
different input RF power levels (R=34 Q, L=18 nH, Z0=50 f2, Cj0= l pF, V 0=0.84 V,
V DC= -3.6 V ).................................................................................................................................................122
Figure 4.13:
Magnitude o f S2] vs. input RF power level for the varactor diode based predistortion
linearizer shown in Figure 4.11 and Figure 4.12 (£=1.8 GHz)...................................................... 122
Figure 4.14:
Phase o f S2| vs. input RF power level for the varactor diode based predistortion
linearizer shown in Figure 4.11 and Figure 4.12 (£=1.8 GHz)...................................................... 123
Figure 4.15:
The power amplifier linearization concept using the varactor based predistortion
circuit.............................................................................................................................................................123
Figure 4.16:
Magnitude o f S2i vs. input RF power level for the nonlinear power amplifier that
w ill be linearized (£=1.8 GHz)................................................................................................................126
Figure 4.17:
Phase o f S2] vs. input RF power level for the nonlinear power amplifier that w ill be
linearized (f= l .8 GHz)..............................................................................................................................126
Figure 4.18: Gain deviation vs. output RF power level for the ideal and designed predistortion
linearizer to linearize the power amplifier given in Figure 4.16 and Figure 4.17
(£=1.8 GHz)................................................................................................................................................. 127
Figure 4.19: Phase deviation vs. output RF power level for the ideal and designed predistortion
linearizer to linearize the power amplifier given in Figure 4.16 and Figure 4.17
(£=1.8 GHz)................................................................................................................................................. 127
Figure 4.20:
Gain vs. input RF power level for the original power amplifier and the linearized
power amplifier (£=1.8 GHz).................................................................................................................. 128
Figure 4.21:
Phase deviation vs. input RF power level for the original power amplifier and the
linearized power amplifier (£=1.8 G H z).............................................................................................. 128
Figure 4.22:
Carrier to 3rd order intermodulation product ratio for the original power amplifier
and the linearized power amplifier as a function o f the output power level (f0=1.8
GHz, A£=2 M H z)........................................................................................................................................130
Figure 4.23: Lower channel ACPR for the original and linearized power amplifiers as a function
o f the mean output power level (The modulation standard is IS-95 reverse link
(narrowband CDMA) at 1.8 GHz).........................................................................................................130
Figure 4.24: Upper channel ACPR for the original and linearized power amplifiers as a function
o f the mean output power level (The modulation standard is IS-95 reverse link
(narrowband CDM A) at 1.8 GHz).........................................................................................................131
Figure 4.25:
Improvement in the power added efficiency and the mean output power as a
function o f adjacent channel power ratio.............................................................................................131
Figure 4.26:
A photograph o f the predistortion linearizer (left) and the power amplifier (right)................134
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Figure 4.27:
Measured gain deviation o f the predistortion linearizer vs. output power level for
various varactor reverse bias voltages (f= l .8 G H z)......................................................................... 134
Figure 4.28:
Measured phase deviation o f the predistortion linearizer vs. output power level for
various varactor reverse bias voltages (f=1.8 G H z)......................................................................... 135
Figure 4.29:
Measured gain vs. input power for the original power amplifier and linearized
power amplifiers at various varactor reverse bias voltages............................................................ 135
Figure 4.30:
Measured phase deviation vs. input power for the original power amplifier and
linearized power amplifiers at various varactor reverse bias voltages........................................ 136
Figure 4.31:
Measured adjacent channel power ratio (upper channel) vs. output power for the
original power amplifier and linearized power amplifiers at various varactor reverse
bias voltages................................................................................................................................................ 136
Figure 4.32:
Improvement in the power added efficiency (PAE) for various varactor reverse bias
voltages as a function o f the adjacent channel power ratio (ACPR)............................................137
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LIST OF APPENDICES
A P PE N D IX
A.
BST CAPACITOR M O DELER .......................................................................................................... 144
B.
M ATLAB CURVE FITTING PROGRAM ...................................................................................... 145
C.
LARGE SIGNAL C-V CURVE SIM U LA TO R.............................................................................. 146
D.
EXTENDED RESONANCE PHASED ARRAY SIM ULATO R............................................... 147
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CHAPTER 1
INTRODUCTION
The recent advancement in wireless communications demands an ever increasing
improvement in the system performance and functionality with a reduced size and cost.
For example, with the cellular and cordless phones operating in the 900 MHz / 1.8 GHz
band, the Global Positioning System (GPS) in the 1.5 GHz band, and the wireless local
area networks (WLAN) in the 2.4 GHz band, it is desirable to combine two or more
standards into a single wireless unit. Dual-band transceivers have recently been
introduced to increase the functionality of wireless communication systems by switching
between two different bands [l]-[4]. Using conventional design techniques, this is
achieved by building multiple independent components for each band such as filters,
amplifiers, oscillators, synthesizers (and therefore antennas) at the expense o f an
undesirable increase in the complexity, size, cost, and power dissipation. While there
have been efforts to minimize the number o f additional components used for dual/multi­
band applications to reduce the complexity, footprint and cost, researchers in industry and
academia are also considering tunable RF/microwave components, which can address
these
challenges by designing
electronically tunable
subsystems
[5]-[20].
The
components can therefore function optimally as conditions change (such as the frequency
of operation). Depending on the specific circuit where such tunable components are used,
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the result may be a savings in cost, reduction in size, improvement in battery life, better
performance, or increased functionality.
Another example which demonstrates the need for tunable
RF/microwave
components is the scenario where the mobile device is moving within a service area. In
modem wireless systems, the mobile device must reduce its output power level as the
user approaches the base station. This is done to assure that the base station receives the
same power level from all users within its reach and the signal from the nearby user does
not drown out the weaker signals from more distant users. As the amplifier’s output
power is adjusted from its maximum rated output power, there is also a change in the
amplifier’s impedance and the optimum impedance that should be presented to the
amplifier’s output so that the battery power is efficiently transferred to the antenna. When
the impedance is not properly matched, the power is reflected backward and wasted.
Fixed impedance matching networks can only provide optimum power transfer at one
power level. Using tunable matching circuits, efficient transfer o f battery power can be
achieved for varying amplifier output power levels, thereby increasing the amplifier’s
efficiency and battery life.
One other example is the use o f adaptive antennas in base stations to improve the
capacity o f the base station. Among multiple access techniques used today, TimeDivision Multiple Access (TDMA) and Code-Division Multiple Access (CDMA) are
most prominent. In TDMA, users communicate at the same frequency, but at different
times (time-sharing). In CDMA, users communicate using the same frequency, but each
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one has a unique spreading code so that the information is recovered using the same code.
The performance o f these systems is mostly limited by signal fading and interference
from other users occupying the same frequency and time slots [21]-[22]. Both o f these
effects can be reduced by the use o f multiple antennas with proper signal combining of
the received signals. Adaptive antennas provide path diversity against multipath fading
and permit the use o f the spatial dimension so that multiple users can occupy the same
channel [22]-[24]. An adaptive antenna system consists o f a group o f antennas (similar to
phased arrays), where the directional pattern can be adjusted electronically by changing
the phase and power of the signal received by the antenna elements. With the proper
selection of the power and phase of the antenna elements, sidelobes can be eliminated or
nulls can be steered towards the sources o f interference. Similar to commercial
communication systems, the highly dispersed and mobile nature o f future battles will also
require large, complex military wireless communication systems, which will be highly
distributed and dynamic. The resulting networks must be interference and intercept
resistant, interoperative, and reconfigurable to minimize the effects o f noise, jamming,
multipath, fading, signal intercept, failures, and other losses by adaptively adjusting their
power, frequency, polarization and beam direction [25]-[36]. Therefore, it is imperative
to pursue innovative design approaches and technologies that maximize the system
performance, functionality and reliability while reducing the size and cost o f the
communication system.
The required RF/microwave components for constructing these reconfigurable
systems (e.g. multi-band transceivers, adaptive antenna systems, etc.) include tunable
3
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filters, tunable antennas, adaptive antennas (phased arrays or beam-agile antennas),
multibeam antennas, polarization agile antennas, tunable amplifiers, tunable matching
networks,
linearizers, phase
shifters, voltage
controlled oscillators,
etc.
These
components can be designed using various techniques such as techniques relying on
mechanical movement, electrical tuning (varactors), magnetic tuning (ferrites), etc.
Among these techniques, electrical tuning is the simplest and most common choice for
making tunable circuits. Tunable capacitors (capacitors whose capacitance can be
changed by an applied DC voltage) are utilized in electrical tuning. When the value of a
capacitor in a circuit is changed, the impedance and phase relationships in the circuit are
affected in predictable ways. Therefore, these parameter changes can be exploited to
design RF/microwave components with greater functionality, higher performance, and
reduced size and cost. Tunable capacitors (varactors) are characterized by a number of
performance measures:
a) Tunability: the ratio o f the maximum capacitance to the minimum
capacitance,
( C m ax /C m m ) .
b) Quality factor (Q): the ratio of the imaginary part o f the impedance to the real
part o f the impedance o f a varactor.
c) Control voltage: the required bias voltage to achieve certain tunability.
d) Power handling capability.
e) Tuning speed: the time it takes the varactor to adjust its capacitance to a
change in the applied bias voltage.
4
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A high performance varactor has a high quality factor (Q), high tunability, high
power handling capability, low control voltage, and fast tuning speed. There are various
technologies that can be used to fabricate varactors at RF/microwave frequencies. A brief
overview of these technologies is given next.
1.1. AN OVERVIEW OF VARACTOR TECHNOLOGIES
1.1.1. Varactor Diodes
A varactor diode is a pn-junction diode, whose depletion-area capacitance can be
changed by changing the reverse-bias voltage across the diode. In Figure 1.1a, p- and ntype materials are brought together to form a pn-junction diode. The different energy
levels in the two materials cause a diffusion of the holes and electrons through both
materials which tends to balance their energy levels. When this diffusion process stops,
the diode is left with a small area on either side o f the junction, called the depletion area,
which contains no free electrons or holes. The movement o f electrons through the
materials creates an electric field across the depletion area that is described as a barrier
potential and has the electrical characteristics o f a charged capacitor. External bias,
applied in either the reverse or forward direction, as shown in Figure 1.1b and Figure
1.1c, affects the magnitude, barrier potential, and width of the depletion area. Enough
forward bias will overcome the barrier potential and cause current to flow through the
diode. The width of the depletion region can be controlled by keeping the bias voltage at
levels that do not allow current to flow. Since the depletion area acts as a capacitor, the
diode will perform as a variable capacitor that changes with the applied bias voltage. The
capacitance vs. voltage relationship for a typical pn-junction diode is given by:
5
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where Vb is the applied bias voltage (positive for forward bias, negative for reverse bias),
Vo is the barrier potential across the junction and Cj0 is the junction capacitance at V b=0.
A typical capacitance vs. voltage (C-V) relationship for a commercially available
varactor diode is plotted in Figure 1.2 [37].
©©
©©
©©
©©
©@
^1
nn
■
HI
fiHte
oo
o©
oo
oo
oo
n
D ep letio n region
(a)
(b)
6
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(C)
Figure 1.1: (a) Unbiased pn-junction (b) reverse biased pn-junction (c) forward biased pnjunction.
0.4
0.2
25
R everse Bias Voltage, V
Figure 1.2: Typical capacitance vs. voltage (C-V) curve for a commercially available varactor
diode (MGV125-20, Metelics Inc.).
Varactor diode technology is well mature today and varactors are readily available.
Varactor diodes have high tunabilities (typically 3-5:1) and low control voltages (5-30 V)
with fast tuning speeds. However, the quality factor (Q) of varactor diodes becomes very
low as the frequency is increased beyond 2-4 GHz. They also suffer from low power
7
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handling capability since varactor diodes must be reverse biased by at least the peak
value of the RF voltage amplitude to avoid forward biasing the diode.
1.1.2. MOS Varactors
It is well known that a MOS transistor with drain, source, and bulk (D, S, B)
connected together realizes a MOS capacitor with capacitance value dependent on the
voltage between the bulk (B) and gate (G). In the case o f a pMOS capacitor (see Figure
1.3), an inversion channel with mobile holes builds up for
Vbg
> \ V t \, where | V t \ is the
threshold voltage of the transistor. This condition operate the MOS capacitor in the strong
inversion region where the MOS device shows the well-known transistor behavior. On
the other hand, for Vg > Vb, the MOS device enters the accumulation region, where the
voltage at the interface between gate oxide and semiconductor is positive and high
enough to allow electrons to move freely. Thus, in both strong inversion and
accumulation regions, the value o f the MOS capacitance is equal to the oxide
capacitance, Cox = e A / t , where A and t are the transistor channel area and the oxide
thickness, respectively. Three more regions can be defined for intermediate values o f Vg'.
moderate inversion, weak inversion, and depletion. In these regions, there are very few
mobile charge carriers at the gate oxide interface, which cause a decrease in the
capacitance o f the MOS device (the MOS capacitor is modeled as a series combination of
Cox and the depletion region capacitance under the gate, which varies with voltage similar
to reverse biased varactor diodes). A typical MOS capacitance, Cmos, versus Vbg is shown
in Figure 1.4 [38]-[39]. It should be noted that Figure 1.4 is valid for a very small signal
superimposed on the bias voltage, Vbg• If the signal at the gate o f the transistor is large,
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the instantaneous value o f the MOS capacitor will change throughout the signal period,
impairing the tuning capability. One solution to overcome this undesired phenomenon is
to remove the connection between D-S and B, and to connect B to the highest potential,
( V d d )-
In this topology (inversion mode MOS, I-MOS), the transistor never goes into
accumulation, so a wider input signal range can be achieved [39]-[40], A better solution
is the use o f the MOS device in the depletion and accumulation regions only
(accumulation mode MOS, A-MOS). This is accomplished by removing the D-S regions
completely, and making bulk contacts on either side o f the channel [39]-[40]. Although
this approach allows for a larger input signal range, this type of process is not supported
by silicon foundries. Therefore, the designer must optimize the design by trial and error
[39]. MOS varactors are extensively used in integrated voltage controlled oscillator
(VCO) applications since they are readily available in a CMOS process [39]-[43].
Typical durabilities o f 1.6:1-2:1 are achievable. However, the quality factor o f MOS
varactors is low at RF/microwave frequencies due to their high series resistance [39].
Figure 1.3: A typical pMOS capacitor.
9
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mos
ox
Strong
Inversion
Accumulation
Depletion
W eak and Moderate Inversion
Figure 1.4: Typical tuning characteristics for a pMOS capacitor.
1.1.3. MEMS Varactors
Micro-electro-mechanical systems (MEMS) represent one o f today’s most active
areas o f research and development. MEMS fabrication is based on an extension of the
photolithographic techniques used in electronic integrated circuits, but with an emphasis
on physical construction rather than electrical functions. The majority o f today’s
RF/microwave MEMS products include four types o f components: switches [44]-[50],
varactors [51]- [56], inductors [57]-[58] and resonators [59]-[60]. A typical MEMS
varactor is shown in Figure 1.5. By applying a voltage between the bridge and the signal
path, the bridge gap can be reduced to one third o f its original value, and therefore
tunable capacitor behavior can be achieved. Further increase o f the voltage between the
plates will cause the pull-in effect, where the bridge collapses on the dielectric. Although
this effect does not significantly impair the switching operation, it limits the tunability of
MEMS varactors. In an analog MEMS varactor, a typical tunability o f 1.5:1 is achievable
with the application of 20-80 V DC bias. Digital MEMS varactors can also be built by
10
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connecting several capacitors together and switching between one capacitor to another
using MEMS switches [55]-[56]. Although very high tunabilities are achievable using
switched structures, this approach has a bandwidth limitation due to the interconnects
between switches. MEMS varactors result in superior quality factors, and they do not
suffer from intermodulation distortion due to the absence of electrical nonlinearity on the
varactor. However, the power handling capability o f MEMS varactors is limited due to
the fact that high power may cause undesired pull-in effects and failures in the bridge.
Also, due to mechanical movement, MEMS varactors are much slower compared to
varactors based on solid-state and ferroelectric technologies.
Dielectric
Anchor
Ground
Substrate
Figure 1.5: A typical MEMS varactor.
1.1.4. Ferroelectric Varactors
Ferroelectric materials are a class o f dipolar dielectric materials characterized over
some range of temperature by a large electrical polarization. The polarization, which
occurs in any dielectric as a result o f an applied electric field, is enhanced in ferroelectric
materials because of a lack o f symmetry in the crystallographic structure o f the unit cell
and the ability o f an electric field to switch the direction o f internal electric dipoles.
11
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Ferroelectricity is most commonly observed in ABO 3 perovskite structures as shown
in Figure 1.6. The A and B atoms represent +2 and +4 ions, respectively, while the O
atom is the Oxygen (-2) ion. This ABO 3 structure in a general sense can be thought o f as
face centered cubic (FCC) lattice with A atoms at the comers and the O atoms on the
faces. The B atom completes the picture and is located at the center o f the lattice. The A
atom is the largest of the atoms and consequently increases the overall size o f the ABO 3
(FCC) structure. As a result, there are minimum energy positions off centered from the
original octahedron that can be occupied by the B atom. Shifting o f this atom due to the
applied electric field causes the structure to be altered, creating electric dipoles [61]-[62].
Therefore, a ferroelectric material exhibits, over some range o f temperatures, a
spontaneous electric polarization that can be reoriented by the application o f electric field
as shown in Figure 1.7a. Although these features o f a ferroelectric material could be used
in a wide range o f applications, the primary focus o f the recent research is directed
towards the development o f non volatile random access memories [63]. When an external
voltage is applied to a ferroelectric capacitor, there is a net ionic displacement in the unit
cells of the ferroelectric material. The individual unit cells interact constmctively with
their neighbors to produce domains within the material. As the voltage is removed,
majority of the domains will remain in the direction of the previously applied field,
requiring compensating charge to remain on the plates o f the capacitor. At zero applied
field, there are two states o f polarization, which are equally stable. Either o f these two
states could be encoded as “ 1 ” or “ 0 ”, and since no external field is required to maintain
these states, the memory device is non volatile.
12
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Ferroelectrics have a characteristic structural phase transition temperature called the
Curie temperature, Tc■ The Curie temperature is the temperature above which a
ferroelectric loses its ferroelectric ability to possess a spontaneous polarization in the
absence o f an external electric field. At temperatures below the Curie point, dipole
moments are partially aligned in the ferroelectric material. As the Curie point is
approached, thermal fluctuations increasingly destroy this alignment until the net
polarization becomes zero at and above the Curie point. Above the Curie point, the
material becomes a paraelectric with a cubic lattice. At the paraelectric phase, the
spontaneous polarization is zero, however the relative dielectric constant, £n still remains
large and becomes a nonlinear function o f the applied electric field as shown in Figure
1.7b. This enables the fabrication o f electronically tunable capacitors with typical
tunabilities greater than 50 % at DC bias levels as low as 2-5 Volts [64]-[69].
Strontium titanate, SrTiC>3, (STO) and barium strontium titanate, (Bax,Sri_x)Ti0 3 ,
(BST) are two o f the most popular ferroelectric films currently being studied for tunable
RF/microwave applications [10]-[12], [65]-[69]. STO presents high tunability at
significantly low temperatures (~77K), thus allowing the incorporation o f high
temperature superconductors (HTS) for very low loss. However, systems based on STO
can be very expensive due to cryogenic cooling requirements [11]-[12], [70],
Furthermore, since STO thin films exhibit very little tunability at room temperature (STO
is an incipient ferroelectric with an extrapolated curie temperature below absolute zero),
they are not suitable for integration in systems operating at room temperature. BST thin
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films can overcome these difficulties. Depending upon the specific composition, BST can
be made tunable at room temperature. The capacitance variation with the applied DC
voltage for a BST capacitor is shown in Figure 1.8. Other advantages o f BST based
capacitors include ease of integration with active devices such as MMICs, low cost
simultaneous fabrication o f multiple parts, low losses in high quality films, and high
power handling capability [6 6 ], [71]. In addition, due to the high dielectric constant o f
BST thin films (typically around 300), capacitors with very small footprints can be
fabricated on appropriately buffered substrates.
• •
A
B
O
Figure 1.6: AB0 3 perovskite unit cell (not to scale).
14
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Polarization
Polarization
Electric Field
Electric Field
(a)
(b)
Figure 1.7: (a) Ferroelectric phase (below Tc), (b) Paraelectric phase (above Tc).
35
30
Ph
a 25
4)
0 20
1
15
& 10
u
5
0
-12
8
4
0
4
8
12
DC Voltage (V)
Figure 1.8: The C-V curve for a typical BST capacitor.
The four aforementioned technologies constitute the main varactor technologies at
RF/microwave frequencies. Each technology has its own pros and cons, but depending on
the specific application, one technology will perform better than the other. For example,
15
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for high power applications, ferroelectric varactors are very attractive due to their higher
breakdown field strengths and the ability to improve the power handling capability by
simply adjusting the thickness of the dielectric. If a very low loss is required in the
application, MEMS based varactors seem to be better than others due to their high quality
factors. Also, for fast tuning responses, ferroelectric and solid-state varactors are better
than others. Table 1.1 summarizes the advantages and disadvantages o f the individual
technologies at RF/microwave frequencies [72]-[74].
Varactor
Diodes
MOS
Varactors
MEMS
Varactors
Ferroelectric
Varactors
Tunability
High
(2-4:1 typ.)
Medium
(1.6:1 typ.)
Low
(1.5:1 typ.)
High
(2-4:1 typ.)
RF Loss (Q)
Moderate
(Q - 6 0 typ.)
Low
Excellent
( Q -2 0 0 typ.)
Moderate
(Q - 6 0 typ.)
Control Voltage
5-30 V
(unipolar)
Low
20-90 V
(bipolar)
5-30 V (bipolar)
(thickness dep.)
Tuning Speed
Fast
Fast
Slow
Fast
Power Handling
Low
Low
Low
High
Intermodulation
Distortion (IMD)
Poor
Poor
Excellent
Trades with control
voltage
Reliability
Excellent
Excellent
Getting better
Good, needs to be
quantified
Cost
Moderate to High
Low to Moderate
Low?
Low?
Table 1.1:
A brief overview of varactor technologies.
1.2. CONTRIBUTIONS AND THESIS OVERVIEW
There are two main parts in this thesis. The first part (chapter 2) studies the
ferroelectric varactor technology for the design o f tunable RF/microwave components. In
this chapter, the measurement and modeling results for thin film barium strontium
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titanate based parallel plate tunable capacitors at VHF frequencies are discussed first. The
results presented here are new for this recently emerging technology. In addition, several
tunable lumped element lowpass and bandpass filters are presented. These filters are also
the first demonstration o f lumped element tunable filters based on the ferroelectric
technology. The second part (chapter 3 and chapter 4) of the thesis will concentrate on
novel RF/microwave circuits employing tunable capacitors. While any varactor
technology can be used in the design o f these circuits, the demonstrated components
utilize semiconductor varactor diodes. In chapter 3, a novel beam-steering technique
using tunable capacitors for low-cost phased array design is presented. In contrast to
conventional systems, phased arrays based on this technique eliminate the need for a
separate power splitter and phase shifters, resulting in a substantial reduction in the
circuit complexity and cost. In chapter 4, a novel power amplifier linearization technique
using a varactor based tunable R-L-C resonator is presented. This approach requires very
few circuit elements, and therefore has simple circuitry and low-cost. The circuits and
techniques introduced in this thesis may be utilized towards the development o f
reconfigurable RF/microwave components as mentioned before. Finally, the last chapter
concludes the thesis and outlines the main achievements and the directions for future
work.
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CHAPTER 2
TUNABLE RF/MICROWAVE FILTERS USING BARIUM
STRONTIUM TITANATE BASED TUNABLE CAPACITORS
2.1. INTRODUCTION
Tunable RF and microwave filters have wide applications in many types of
communication systems, such as receiver pre-selection, IF and transmit filtering. Most of
today’s tunable filters rely on either mechanical tuning, or electronic tuning using
varactor diodes or bank o f switchable capacitors. Mechanically tunable filters have high
power handling capability with a low insertion loss. The main disadvantages o f these
filters are low tuning speed, large size and mass [19]. Varactor diode based tunable filters
are much faster, but they suffer from poor power handling and high losses at RF and
microwave frequencies due to the low quality factor of varactor diodes at these
frequencies [19]. Switched capacitor filter banks are more common, but they do not have
a continuous tuning range and are not usually small. Recently, new technologies such as
MEMS [13]-[18] and ferroelectric thin films [8]-[12], [75] have been exploited for the
development o f low loss and miniature tunable filters. MEMS based tunable filters
employ either MEMS switches or MEMS varactors. A good example o f a MEMS based
tunable bandpass filter at VHF has been presented in [76] with an insertion loss o f
approximately 4 dB. With the advances in MEMS technology, lower insertion loss filters
are expected. However, MEMS have stringent packaging requirements and complicated
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biasing schemes [77]. Most o f the current research activities concentrate on improving
the power handling capability and reliability o f the MEMS based structures [78]-[79]. On
the other hand, ferroelectric varactor technology is a newly emerging technology for the
design o f tunable RF/microwave components. Unlike MEMS, BST based varactors
(Barium Strontium Titanate, (Bax,Sri.x)Ti 0 3 ) offer high tunability, high power handling
capability, fast tuning speeds and low control voltages [65]-[69].
In this chapter, fabrication, measurements and modeling o f parallel plate tunable
capacitors based on BST thin films will be discussed, and tunable lowpass and bandpass
filters based on these capacitors will be presented.
2.2. FABRICATION OF BST VARACTORS
The parallel plate BST capacitors were fabricated by ATMI Inc., Danbury, CT and
North Carolina State University (NCSU), Material Science Department, Raleigh, NC on
500 pm thick silicon wafers covered with approximately 500 A o f thermal SiC>2 and
1000-3000 A of Pt (this Pt layer acts as the device ground plane). Metal-organic chemical
vapor deposition (MOCVD) technique was used to grow
700-3000 A thick
(Bao.7Sro.3)Ti0 3 films. MOCVD provides excellent composition control, large area
coverage, and the potential for areal homogeneity and conformal coating o f complicated
topography [80]-[81]. In this work, all BST films were uniformly deposited on 150 mm
wafers, thus indicating the suitability for commercial mass production. Either sputtering
or electron-beam evaporation techniques were used to deposit the 3000 A thick top
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electrodes
completing
the
parallel
plate
capacitor
structures.
Using
standard
photolithographic methods and reactive ion etching, the top platinum surface was
patterned. Figure 2.1 shows the schematic illustration o f the parallel plate BST capacitors
fabricated. To achieve the best electrical properties, it was necessary to anneal the top
electrodes after deposition at 550 °C for 30 minutes in air [69]. This annealing process
results in reduced loss tangents and reduced dielectric dispersion. If samples are re­
exposed to atmosphere for extended periods after this annealing step, in order to maintain
reliable electrical properties, this step must be repeated. It is believed that atmospheric
moisture will in some way influence the film/electrode interface over time and degrade
the interfacial electrical properties. This implies that BST components in real circuits
must be capped with isolation layers providing moisture barrier. These capacitors were
used to fabricate a bandpass filter, which resulted in an insertion loss o f 7 dB [8 ]. To
reduce this insertion loss, higher quality factor BST capacitors were needed. The main
source o f the total loss for the BST capacitors is the conductor loss [6 6 ]. It is certainly
possible to reduce the conductor loss by increasing the electrodes’ thickness and reducing
the total resistance. To improve the quality factor o f the BST capacitors, efforts were
directed to improving the ground plane metallization [82], However, there are some
challenges associated with this approach.
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Top Electrode
W
m
J K
B ST
■PT Ground Plane
Silicon Substrate
Figure 2.1: Schematic illustration of the parallel plate BST capacitors.
The bottom electrode must survive the BST deposition process remaining smooth,
flat, and adherent to the substrate. Typically, BST is deposited between 650 °C and 700
°C in an atmosphere composed o f chemical precursors, which can be particularly
aggressive. This environment, especially the high temperatures, can facilitate bottom
electrode degradation. Specifically, the thermal expansion mismatch between the silicon
wafer and the Pt electrodes results in appreciable residual strains upon cooldown to room
temperature. The potential outcome o f large residual stresses includes bottom electrode
peeling and hillocking. These conditions are worsened by increasing the metal thickness;
as the thickness is increased, the amount of residual stress increases as well. Thus
increasing the thickness to reduce the total resistance can result in mechanically unstable
bottom electrode layers, which are obviously undesirable for high quality devices.
To avoid these problems, the adhesion between the platinum electrodes and the Si0 2
substrate surfaces must be improved - this can be difficult to accomplish. This was
addressed by developing hybrid composite electrodes fabricated from interleaved layers
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o f Pt and &O2 [83]. IrCh is a metallic oxide, which can promote Pt adhesion and
mechanical stability. The composite electrodes consisted of alternating layers o f 250 A
IrC>2 and 2000 A Pt as shown in Figure 2.2. This stacking was continued until a total
thickness of 1.3 pm was reached. This metallic stack was able to survive the BST
deposition process without mechanically failing, and the resistance is reduced as expected
by the thickness increase. High frequency measurements were performed on the BST
deposited on these thick electrodes to determine if the quality was similar to samples
deposited on the traditionally thin Pt layers. The loss tangent o f the BST material on these
thick layers was measured to be 0.008 between 45 and 500 MHz, which is similar to the
values obtained from thin platinum bottom electrode BST capacitors [65], [83]. The total
quality factor (device Q) o f a 65 pF BST capacitor having multilayer ground plane was
measured to be 63 at 45 MHz, a factor of two improvement compared to previously
fabricated BST capacitors with thin bottom electrodes.
Pt top electrode
BST dielectric layer
Pt bottom electrode layers ~ 2000 A
Ir02 adhesion layers - 250A
|S i substrate
S i0 2o
///////////////////////a
F igu re 2.2:
T he d escrip tion o f the m u ltila y er ground p lan e B S T capacitor.
22
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2.3. MEASUREMENTS AND MODELING OF BST VARACTORS
An HP8510C vector network analyzer and a Cascade Microtech probe station was
used to measure the parallel plate BST capacitors. A schematic illustration o f the
measurement setup is shown in Figure 2.3. GGB Industries’ Model 10 and Model 40A
type high frequency probes were used to contact the BST capacitors. Figure 2.4 shows a
picture o f the BST capacitors contacted with a Model 10 probe. Access to the ground
plane was achieved through etching the BST layer. Cascade Microtech’s calibration
standards were used to make a one-port short-open-load (SOL) calibration at the network
analyzer. BST capacitors having typical dimensions o f 50 pm x 50 pm were measured at
a frequency range between 45 MHz and 500 MHz. The upper frequency limit was set by
the high dielectric constant (so high capacitance) o f the BST material (-200). DC bias
was applied to the capacitors through the internal bias-tee o f the network analyzer.
DC Power
Supply
Computer
HP-IB
HP8510C
Network
Analyzer
F igu re 2.3:
High
frequency
probes
BST
Capacitors
S m all sig n a l m easu rem ent setup.
23
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Figure 2.4: A typical probe contact for the BST capacitors.
The BST capacitors are modeled in terms o f an equivalent circuit as shown in Figure
2.5. In this model, Rs accounts for the conductor losses due to the top and bottom
electrodes o f the parallel plate capacitor, and Rp accounts for the BST dielectric losses.
Since the conductor thickness deposited in the fabrication of the BST capacitors is much
smaller than the skin depth at the frequencies o f interest, Rs is assumed to be frequency
independent. The loss tangent of the BST is also assumed to be constant over this
frequency range [84], [85]. The element values o f the equivalent circuit model were
optimized using Agilent-ADS (Advanced Design System) simulation tool such that the
modeled and measured S-parameters (magnitude and phase) fit each other over the
measured frequency range. The details of the simulation setup is given in Appendix A.
From these simulations, Rs, Rp, and C values are obtained. Depending on the quality o f
the BST capacitor, resulting Rs and Rp values are in the range o f 0.5-5 Q and 1-10 kQ,
24
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respectively. The relative dielectric constant (relative permittivity, er) and the loss tangent
of the BST thin films were then calculated using the following relations:
C -d
£0A
=
tan S =
(2 .1)
(2.2)
a)RpC
where C is the capacitance, A is the top plate area of the BST capacitor and d is the
thickness o f the BST.
R c
Rt
F igu re 2.5:
*
C
T h e eq u ivalen t circuit m o d e l for the B S T capacitor.
Figure 2.6 shows a typical plot for the relative dielectric constant as a function o f the
applied DC voltage across a parallel-plate BST capacitor between 45 MHz and 500 MHz.
Approximate tunabilities o f 71% (3.4:1) with the application o f 0 V to 9 V DC were
obtained from BST capacitors. The loss tangent values were typically in the range of
0.003 - 0.009 over this frequency range. The total (device) quality factor (Qtotai) of the
25
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measured BST capacitors was extracted from the measured data using the following
relation:
_ _ imag{Z)
,0,al
real(Z)
where Z is the impedance measured by the network analyzer. The device Q includes
losses due to the BST (Q bst) and the conductor losses (Qconductor) which are related by:
1
1
Q total
Q
1
+ - -------b ST
(2-4)
^conductor
where Qbst and Qconductor are obtained from:
Q bst
= ® RpC =
Qconductor
Using
n
(t)Kv C
(2 -5)
(2 -6 )
(2.4) - (2.6), the quality factors due to the BST dielectric losses and the
conductor losses were extracted from the total quality factor, respectively. Figure 2.7
shows the measured and modeled device Q vs. frequency plot as well as the modeled Q
factors due to the BST dielectric loss and the conductor loss for a typical BST capacitor
measured in this work with C = 65 pF at 0 V DC bias. The measured device Q o f the BST
capacitor is approximately 60 at 50 MHz, which is comparable with the Q factors for
commercially available semiconductor based varactor diodes with similar capacitance
values (Typical 65 pF commercial varactor diodes have Q factors in the range 40-80 at 50
MHz). It should be noted that the maximum accurate quality factor measurable using this
26
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
technique is approximately 70-80 due to the uncertainties in the reflection coefficient
measurement [8 6 ]. It can also be concluded from Figure 2.7 that at lower frequencies,
both Qbst and
increased,
Q c o n d u c to r
Q to ta i
contribute to the device
is dominated by
Q c o n d u c to r,
Q
(Q to ta i),
whereas as the frequency is
which is inversely proportional to the
frequency. It can be clearly seen from Figure 2.7 that the dielectric losses o f the BST
itself (tanS = Qbst"1 = 0.008) has little impact on
Q to ta i
at frequencies above 300 MHz.
Conversely, it can be stated that at higher frequencies, a substantial improvement in
device quality factor can be expected if the conductor losses are reduced. One
straightforward solution is to use a metallization with higher conductivity or to increase
the capacitor electrode thickness. For example, the thickness can be increased up to
approximately 5-6 pm at 1 GHz, above which the skin effect becomes dominant.
^
250
200
150
100
50
0
10
5
0
5
10
DC Voltage (V)
F igure 2.6:
R ela tiv e p erm ittivity v s. ap plied D C v o lta g e for B S T b e tw e e n 4 5 and 5 0 0 M H z
(T h e B S T th ick n ess is 7 0 0
A and
the top electro d e siz e is 5 0 x 5 0 p m 2).
27
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
160
140
120
Qtotal(meas.)
O 100
-
OS
Qconductor
|
80
§
O'
60 -
Q bst
Qtotal(modeI)
0
100
200
300
400
500
Frequency (MHz)
F igure 2.7;
T h e q uality fUCtOfS,
V D C bias.
Q total(measured)) Q b S T , Q conductor) Qtotal(m odel)
fcr d B S T CUpUCitOr at 0
2.3.1. Large Signal Measurements of BST Varactors
Possible applications o f BST based capacitors are tunable filters in transmitters,
tunable matching networks at the output o f power amplifiers, and high efficiency DC-DC
converters, where the BST capacitors are exposed to large AC signal amplitudes. In
addition, the nonlinear C-V curve o f the BST varactors can be exploited for the design o f
frequency
multipliers
and
parametric
amplifiers.
These
applications
require
understanding the effect of large AC signal on the C-V curve o f the BST capacitors. The
set-up in Figure 2.8 was used to obtain the large signal C-V curve for BST capacitors. In
this set-up, an HP70820A microwave transition analyzer is used to measure the large
signal S-parameters o f the BST capacitors. The signal generated from the source o f the
transition analyzer is fed into a power amplifier, and the amplified signal is fed to the
28
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
directional coupler. The directional coupler couples -20 dB o f the input power to the 2nd
port o f the transition analyzer as a reference. However, most o f the power is applied to
the device under test. The measurement frequency was 50 MHz. An external bias-tee was
used to apply the DC bias voltage. The reflected signal from the BST capacitor is coupled
to the reverse port of the transition analyzer. An SOL (short-open-load) calibration
procedure was applied to correctly measure the reflection coefficient at large RF signals.
A GGB Model 34A-4-35 high impedance active probe with a tungsten tip was used to
measure the actual RF signal amplitude across the capacitors. The probe was connected
to the top plate of the capacitors while being excited with the large RF signal. The
voltage waveforms were observed on a high frequency oscilloscope, and the rms values
of the waveforms were recorded at various RF power levels. Similar to the procedure
explained in 2.3, the capacitance (hence relative permittivity) o f the BST varactors were
determined at the measured RF signal amplitudes and DC voltages.
HP 70820A
Transition
Analyzer
Amplifier Research
10W1000C
RF Power Amplifier
DC Power
Supply
reverse
forward
input
output
Picosecond
5530A Bias T
Mini Circuits ZFD C -20-1H
Directional Coupler
Oscilloscope
High Frequency
Active Probe
BST
Capacitor
Figure 2.8: Large signal measurement set-up.
29
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 2.9 shows the plots o f the capacitance as a function of the applied DC voltage
(C-V) for various RF signal amplitudes. The breakdown voltage o f 8 V for this particular
sample limited the application o f higher DC voltages, while high RF voltage levels were
applied. It can be seen that the capacitance near 0 V DC bias decreases with increasing
the RF signal amplitude, resulting in reduced tunabilities. The reason for this drop is that
when a large RF signal is applied to the BST varactor, its capacitance is modulated and
the current passing through the capacitor contains the harmonics o f the fundamental
frequency due to the nonlinearity of the C-V curve [87]-[89]. The measured capacitance
is therefore the capacitance determined by the magnitude of the current and voltage at the
fundamental frequency, which therefore results in reduced capacitance due to the high
nonlinearity o f the C-V curve around 0 V DC bias. Using the small signal C-V
relationship o f the varactor, the reduction in the capacitance can be analytically predicted
using the current and voltage at the fundamental frequency [87] such that:
reduced
r m s ( l( t) ) \ f0
f
(2.7)
f sll
where C,reduced is the reduced capacitance, rms{l(t)) | / 0 and rms — — | f 0 are the root
V dt
mean square (rms) values for the fundamental frequency components o f the current
flowing through the BST varactor and the voltage across the BST varactor, respectively.
Knowing the amplitude and frequency of the voltage across the capacitor and the small
signal C-V relationship, the current flowing through the BST capacitor can be calculated
using:
30
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
<M)
j C(v<f))-v(t)
dt
(2 .8)
dt
where Q(t) is the instantaneous charge.
70
60
a
O
O
50
40
l
£ 30
&
- b- R IM ).69 Vrms
-* -R F = 1 .3 8 Vrms
-* -R F = 2 .5 8 Vrms
20
10
0
6
•4
0
■2
2
4
6
DC Voltage (Volt)
Figure 2.9: Measured C-V curve for large RF signal amplitudes (f=50 MHz, the BST thickness
is 700 A, and the top electrode size 50x50 pm2).
Let us now estimate the reduction in the permittivity for the BST capacitor shown in
Figure 2.9. In order to obtain the C-V relationship, the measured small signal C-V curve
of the BST capacitor was fit into a polynomial based nonlinear capacitor model using a
MATLAB curve fitting code as given in Appendix B. The resulting C-V relation is:
193 + 5.24• V - 23.6• F 2 -1 .5 7 -F 3 + 3.58-F4 + 0 .2 2 -F 5 -0 .3 2 -F 6\
C(V) = C0 -1.57-10 "2 - V 1 +1.63-10'2 -Vs +5.92-10"4 -V9 -4.65-10"4 -V'0
-1 .1 2 -10-5 -Vn +6.91-10"6 -F 12 +8.33-10 "8 -F 13 -4 .1 7 -1 0 '8 -F 14
31
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(2.9)
where Co is 0.333 pF (the term inside the parenthesis represents the relative permittivity
vs. voltage). The measured small signal C-V curve and the C-V relation from (2.9) for
this BST varactor are plotted in Figure 2.10. It turns out that the small signal C-V curve is
well estimated with a 14th order polynomial based nonlinear capacitor model for the
measured voltages. Based on the polynomial based nonlinear capacitor model, a
harmonic balance simulation was performed in Agilent-ADS to observe the current and
voltage waveforms. The details of the simulation setup are shown in Appendix C. The
resulting time domain currents flowing through the varactor and the voltages across the
varactor for various RF signal amplitudes are shown in Figure 2.11 and Figure 2.12,
respectively. The harmonic content o f the time domain currents and voltages as a
function o f the rms value of the total voltage across the BST varactor are also shown in
Figure 2.13 and Figure 2.14, respectively. It turns out that as the RF voltage amplitude
across the BST varactor increases, higher harmonic levels are generated. Using (2.7), the
C-V curves o f the BST varactor for various RF signal amplitudes were calculated as
shown in Figure 2.15. Similar capacitance decrease (hence reduced tunability) with the
applied RF signal amplitude was observed. Therefore, the small signal C-V curve is
sufficient to predict the capacitance drop at large RF signal amplitudes. The simulated 0
V DC bias capacitance o f the BST varactor as a function of the RF signal amplitude (CV
rf)
is also shown in Figure 2.16. It turns out that with the application o f an RF signal
with 3.3 Vrms amplitude, the 0 V DC bias capacitance for this particular BST varactor is
reduced from 65 pF to 50 pF (tunability o f 1.3:1). It should be noted that the reduction in
the capacitance depends very much on the nonlinearity o f the small signal C-V curve. For
example, it was simulated that more reduction in the capacitance is obtained if the C-V
32
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
curve is steeper (i.e. same tunability at lower control voltages) or the BST capacitor has
more tunability (i.e. more tunability with the same control voltages).
The reduction in the BST varactor capacitance at large RF signal amplitudes must be
taken into consideration for applications where circuit linearity is important. In order to
reduce/eliminate this reduction, the BST varactor can be operated at a more linear region
(i.e. at a DC offset where C-V curve is linear). It should also be mentioned that tunability
and power handling capability o f varactor diodes degrade dramatically due to the
application o f high RF voltages. This is because for proper operation, varactor diodes
must be reverse biased by at least the peak value of the RF voltage amplitude to prevent
forward biasing. However, this requirement is not present in BST based capacitors,
making them attractive for the design of high power and tunable RF and microwave
circuits. In addition, this reduction can be exploited for useful purposes, such as design of
predistortion linearizers as mentioned in chapter 4, frequency multipliers and parametric
amplifiers [89],
33
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
70
—
o
Polynom ial Model
M e a su red
60
q.50
<2 45
Q.
40
-6
DC V oltage, V
Figure 2.10: Measured and modeled C-V curve for the BST varactor used in Figure 2.9.
<
E
c
£u.
=3
o
0
5
10
15
20
25
30
35
40
Time, nsec
Figure 2.11: Time domain current flowing through the BST varactor for various RF signal
amplitudes.
34
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
6
4
2
0)
o> 0
C
O»
H
—
£
■2
-4
■6
0
10
5
20
15
25
30
35
40
Time, nsec
Figure 2.12: Time domain voltage across the BST varactor for various RF signal amplitudes.
-20
-30
■Fundamental
-40
/ - “-v
/—\
I
-5°
S
O
©
<N
-60
2 nd
harmonic
D - 3rd harmonic
O 4th harmonic
-70
-X —5th harmonic
-80
—I— 6 th harmonic
-90
-100
0.25
0.75
1.25
1.75
2.25
2.75
3.25
Magnitude of RF Voltage, Vrms
Figure 2.13: Current through the BST varactor at harmonic frequencies as a function of total RF
voltage across the BST varactor.
35
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fundamental
2 nd
o
£
harmonic
3rd harmonic
&
-© —4th harmonic
bo
o
o(N
-X —5th harmonic
—I— 6 th harmonic
-100
0.25
0.75
1.25
1.75
2.25
2.75
3.25
Magnitude of RF Voltage, Vrms
Figure 2.14: Voltage across the BST varactor at harmonic frequencies as a function of total RF
voltage across the BST varactor.
70
Capacitance, pF
60
50
40
Small Signal
30
R F =0.69 Vrms
20
R F=1.38 Vrms
10
R F=2.58 Vrms
0
-6
-4
-2
0
2
DC Voltage (Volt)
4
6
Figure 2.15: Simulated C-V curve for large RF signal amplitudes for the BST varactor shown in
Figure 2.9 (f=50 MHz).
36
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
70
60
50
40
30
20
10
0
0
2
1
3
4
Magnitude o f RF Voltage, V rms
Figure 2.16: 0 V DC capacitance as a function of the RF voltage amplitude for the BST varactor
shown in Figure 2.9.
2.4.
TUNABLE LUM PED ELEM ENT VHF FILTERS
2.4.1. Tunable Lumped Element Lowpass Filters
A tunable lowpass filter (LPF) can be designed using a Chebyshev or Butterworth
lowpass filter prototype. In Figure 2.17, a 3rd order lowpass filter prototype is shown. For
a given ripple in the passband, the component values can be calculated using:
C =
gl
R0 -coc
L = gl '
Q)c
37
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(2.10)
(2.11)
where gi and g2 are the prototype element values from the design table, Ro is
characteristic impedance of the 1st and 2nd ports, which is usually 50 Q, and coc is the cut­
off frequency o f the filter [90], A lumped element tunable lowpass filter based on the 3rd
order 0.5 dB ripple Chebyshev prototype was designed with component values L=56 nH
and C=32 pF at 0 V. The DC bias voltage to the BST capacitors was applied through the
ports o f the filter using a bias-tee. The BST layer was etched away using hydrofluoric
acid (HF), and the access to the ground plane was obtained. The ground plane of the BST
capacitors was then connected to the circuit using silver epoxy. Coilcraft 603CS type chip
inductors were used in the fabrication o f the lowpass filter. The top electrode of the
parallel plate BST capacitors were connected to the circuit using bond wires. An HP8510C network analyzer was used to measure the filter. The lowpass filter exhibited an
insertion loss o f 0.8 dB and a tunability of 30% (120-170 MHz), defined as the
percentage change of the 3 dB cut-off frequency when the filter is tuned, with the
application o f 0-9 V DC as shown in Figure 2.18. The return loss o f the filter within the
passband was higher than 10 dB for all biasing conditions. A 5 order tunable lowpass
filter was also fabricated as shown in Figure 2.19. The design of this filter was
approximate since the exact combination o f BST capacitors and inductors were not
available. This filter had an insertion loss o f approximately 2 dB and a return loss of
better than 7 dB with a 40 % tunability by the application o f 0 to 9 V DC bias as shown
in Figure 2.20.
38
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
a
-o
*
Figure 2.17: A prototype 3rd order tunable lowpass filter.
RL at 0
-10
-15
9V
9V
IL at 0 V
-25
-30
0
300
200
100
400
500
Frequency (M H z)
Figure 2.18: The measured insertion loss and the return loss of the 3rd order lowpass filter with
changing the DC bias voltage.
Ll=110nH
o
-n n m
—
Ll=110nH
L2=165 nH
-^nnp
^ T T I P --------- -o
—
C l=32 pF
C l=32 pF
Figure 2.19: The 5th order tunable lowpass filter.
39
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
0
® -20
at-OV
c«
CO
O
-40 - IL at :0 V
100
200
300
400
Frequency (M H z)
Figure 2.20: The measured insertion loss and the return loss of the 5th order lowpass filter with
changing the DC bias voltage.
2.4.2. Tunable Lumped Element Bandpass Filter
A 3rd order bandpass filter prototype is shown in Figure 2.21. The components values
are found using the following relations [91]:
T - AZ«
®ogi
CI =
C2 =
(2 .12)
gi
Ao)0Z 0
(2.13)
§2^0
Acon
(2.14)
(2.15)
^0§2^0
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where gi and g2 are the lowpass prototype element values depending on the desired
passband ripple and stopband suppression, Zo is the impedance o f the ports which is
usually 50 Q, co0 and A are the center frequency and fractional bandwidth o f the
bandpass filter that are given by:
(2.16)
A=
where
cdx
and
a>2
(02 - CO]
(2.17)
are the angular cut-off frequencies. However, fabrication of this
topology is practically very difficult. Because, connecting a BST capacitor in series
requires access to the ground plane, and results in the utilization o f only one capacitor on
the wafer and accommodation problems for the die (refer to Figure 2.4). However, the
series LC circuit in Figure 2.21 can be transformed to a parallel LC circuit by using
admittance inverters [90], resulting in a circuit configuration which is easier to fabricate.
An admittance inverter can be realized using the circuit of Figure 2.22. The effect o f the
negative inductors is compensated by changing Li and L 3 on each side. The admittance
inverter parameter for this inverter circuit will be:
Therefore, the new shunt components values can be calculated using:
(2.19)
41
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
C3 = J 2L 2
(2.20)
To prevent the shunt inductors to short out the DC bias voltage, decoupling capacitors
were used in series with the inductors. However, series decoupling capacitors should also
be added at the input and output o f the filter to block low frequency signals. A bandpass
filter was designed, fabricated and tested following the outlined design procedure. The
admittance inverter parameter was chosen such that it results in the same tunable
capacitor value so that the same BST Capacitor wafer (die) can be used to facilitate the
fabrication process. The complete circuit schematics o f the tunable bandpass filter is
shown in Figure 2.23 and a photograph of the bandpass filter is shown in Figure 2.24.
The DC bias voltage to the BST capacitors was again applied through the ports o f the
filter using a bias-tee.
L2
C2
Cl
Cl
Figure 2.21: A 3rd order tunable bandpass filter p rototype.
Impedance inverter
L
:
L2
(YYWl
C2
^
O
L
(YXVY)
L3
C3
-O
F igu re 2.22: In version o f series L C to parallel LC u sin g im p ed a n ce inverters.
42
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
:
44 nH
44 nH
Q =97
Q =97
m® Lr
3.3 nF
14 nH
Q =72
3.3 nF
3.3 nF
65 pF
20 nH
Q =76
65 pF
14 nH;
Q = 72
65 pF
F igure 2.23: T he co m p lete circuit o f the tunable bandpass filter (T h e q uality factors o f the
inductors are g iv e n at 2 0 0 M H z).
F igure 2.24: A photograph o f the con stru cted filter.
43
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The measurement result for the bandpass filter is presented in Figure 2.25. The center
frequency of the filter was tuned from 176 MHz to 276 MHz, resulting in 57 % tunability
with the application o f 0 to 6 V DC. The BST capacitor tunability was 2.5:1 (60%) with
the applied DC bias. The insertion loss within the passband was 3 dB for all bias values.
The return loss of the filter was measured to be better than 7 dB. By comparing the
measured and the simulated responses o f the bandpass filter, it was concluded that 1.5 dB
of the 3 dB insertion loss is directly attributable to the BST capacitors. The remainder o f
the insertion loss (1.5 dB) is mostly due to the finite quality factor o f the inductors and
the bond wires used. The insertion loss performance achieved from this bandpass filter is
comparable to the commercially available varactor diode based tunable filters and
switched capacitor filter banks (Available 2nd order tunable bandpass filters based on
varactor diodes and switched capacitor filter banks with similar center frequency and
bandwidth have insertion loss o f approximately 1 dB [92]). The shape factor o f the
bandpass filter (defined as the ratio o f the 30 dB bandwidth to the 3 dB bandwidth) was
2.85, which is also comparable to the commercial tunable bandpass filters. With the
recent advances in BST film deposition and processing, lower insertion loss BST based
tunable filters are expected.
44
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
PQ
3
-1 0
£ -15
0
^ -20
1
- 25
I -30
* -35
0 Volt\ 3j V o lt\6 Voll
-40
0
100
200
300
400
500
400
500
Frequency (M H z)
(a)
S -io
^
-15
2
-20
e
-25
I
-30
0 Volt
3 Volt:
-35
-40
0
100
200
300
Frequency (M H z)
(b)
F igu re 2.25: (a) T h e in sertion lo ss and (b) the return lo s s o f the n e w band pass filter w ith the
h igh er Q B S T capacitors and inductors.
45
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
2.4.3. Intermodulation Distortion Characterization of the Tunable Filter
Intermodulation distortion (IMD) is a measure o f the linearity o f a two port nonlinear
circuit. When two closely spaced signals at frequencies fr and f2 are injected to a
nonlinear two port circuit (such as a nonlinear filter), harmonics o f the fundamental
signals and their cross products are generated. O f particular interest are the 3rd order
products at 2fi-f2 and 2 f2-fi, which fall within the band of interest and cause signal
distortion. This is a troublesome effect in RF systems. If a weak signal accompanied by a
strong interferer experiences third order nonlinearity, then the IMD products distort the
desired signal component. The distortion due to the 3rd order products o f two nearby
signals is so common and so critical that a performance metric has been defined to
characterize this behavior. Called the 3rd order intercept point (IP3), this parameter can be
measured by a two-tone test as in Figure 2.26. A spectrum similar to Figure 2.27 is
observed in the spectrum analyzer. In this spectrum, increasing the input power raises the
fundamental signal’s power by one time, whereas it increases the 3rd order product’s
power by three times. IP3 is theoretically defined as the level o f the output power (or
input power) at which the fundamental signal’s power and the 3rd order product’s power
are equal to each other, and can be calculated using the formula below (power units are in
dB):
O uput m
+ P* ’“ ~ P™
=
46
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(2.21)
S ig n a l G enerator
at f + 8 f
P o w e r C o m b in er
T u nab le F ilter
H P8563E
S pectru m
A n a ly zer
S ig n a l G enerator
(n o n lin ea r tw o port)
at f - 5 f
F igure 2.26: M easu rem ent setup for the in term odu lation distortion.
▲
Ik
_____ 1p
ik
J fundamental
1
ik
^3rd
------------------------- ►
f-3 8 f f-5 f
f+ 5 f
f+ 3 8 f
Frequency
F igure 2.27: Spectrum o b serv ed in the spectrum analyzer.
The output IP3 point of the bandpass filter was measured to be 19 dBm with the
application o f two tones at 169.5 and 170.5 MHz. This IP3 point is comparable to the IP3
points of varactor diode based tunable bandpass filters (Varactor diode based tunable
filters have IP3 points of approximately +10 dBm [92]). Much higher IP3 points (30 to
50 dBm) are achievable from switched capacitor filter banks due to the absence of
nonlinear elements for tuning. Several approaches can be followed to improve the IP3
point of the bandpass filter. Based on Agilent-ADS simulations, it was concluded that the
major source o f the intermodulation distortion is the high nonlinearity o f the capacitance
vs. voltage (C-V) curve around 0 V DC bias as shown in Figure 2.6. Therefore, by
applying a small DC bias to the BST capacitors, they can operate at a more linear region,
47
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
hence the IP3 point is improved. However, this o f course reduces the tunability. Another
approach is to increase the BST thickness or to connect the capacitors in series at the
expense of requiring higher tuning voltages, which reduces the RF electric field across
the capacitors, thereby improving the IP3. Furthermore, the design o f the bandpass filter
can be optimized for the best IP3 performance without altering the filter response by
simply adjusting the J-inverter parameter in the filter. BST based tunable filters can be
used in multi-band transceivers as a pre-selector or as a transmit filter. If used as a
transmit filter, the IP3 point of the filter must be carefully designed to satisfy the linearity
requirement o f the communication system.
2.5. CONCLUSIONS
In this chapter, the fabrication, measurement and modeling results for Barium
Strontium Titanate (BST) based varactors have been presented, and tunable lowpass and
bandpass filters employing BST varactors have been demonstrated. MOCVD grown
parallel plate BST capacitors resulted in approximate tuning range o f 3.4:1 (71%) with
the application o f 5 V to 10 V DC bias. The measured loss tangent values were in the
range 0.003 - 0.009 at VHF frequencies. The total quality factor for the BST capacitors
was discriminated into components due to the BST loss and the conductor loss. It was
determined that at frequencies below 100 MHz, both conductor loss and BST dielectric
loss contributed to the total quality factor, whereas at frequencies above 100 MHz, the
total loss is dominated by the conductor loss. The measured total Q for BST varactors is
comparable with the total Q o f commercially available varactor diodes having similar
48
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
capacitance. Furthermore, the effect o f large RF signal amplitudes on the capacitance vs.
voltage (C-V) curve was investigated. The capacitance near 0 V DC bias (hence the
tunability) decreases as the RF voltage amplitude across the BST varactor increases. This
effect must be taken into consideration for applications where circuit linearity is
important. The measurement and modeling results presented in this chapter are new for
this recently emerging technology. In addition, tunable lumped element lowpass and
bandpass filters based on parallel plate BST capacitors were presented. The lowpass filter
achieved 40 % tunability with the application o f 0 to 9 V DC bias. The bandpass filter
showed 57 % tunability with an applied DC bias o f 0 to 6 V. The passband insertion loss
of the bandpass filter was measured to be 3 dB, which is a promising result compared to
the commercially available varactor diode based tunable filters and switched capacitor
filter banks. These filters are also the first demonstration o f lumped element tunable
filters based on ferroelectric technology.
49
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER 3
EXTENDED RESONANCE PHASED ARRAYS
EMPLOYING VARACTORS
3.1. INTRODUCTION
A phased array is a group of antennas in which the relative phases o f the respective
signals feeding the antennas are varied electronically in such a way that the effective
radiation pattern o f the array is reinforced in a desired direction and suppressed in
undesired directions. In a conventional phased array system, the signal is divided into
many branches using a power splitter and each branch is then fed into a phase shifter and
followed by an antenna as shown in Figure 3.1. These systems are discussed in detail in
[93]-[95]. Phased arrays can steer the radiation pattern at a fast rate due to the absence of
mechanical movement, however they require a complex integration o f many circuits and
suffer from high loss and mass. Phase shifters are considered to be the most sensitive and
expensive part o f a phased array. It has been estimated that almost half o f the cost o f a
phased array is due to the cost of the phase shifters used [96]. Furthermore, the
complexities in the feed network, the bias network for the phase shifters, and the coupling
between array elements make the design o f phased arrays very difficult and expensive.
Therefore, phased arrays have been used only in a few sophisticated military applications
and space systems such as satellite communications, multipoint communications, radar
systems, early warning and missile defense systems. These applications usually have
50
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
stringent requirements on the sidelobe levels, scan range and beamwidth of the phased
arrays. On the other hand, phased arrays are also being considered for emerging
commercial applications, such as automotive collision avoidance radars and intelligent
cruise control systems [97]-[98], automotive blind spot indicators, adaptive antenna
systems for wireless local area networks and base stations [22]-[24], [99], mobile
multimedia broadcasting [100]-[101], and traffic control radars [102], In these systems,
accurate beam control and wide scan angles are not required. Instead, low cost, small
size, and ease of manufacturability are the driving criteria. For example, for mobile
multimedia broadcasting, the receiver unit must be able to track the satellite while the
vehicle is in motion with scan ranges 20-30 degrees [100]-[101], Also, for automotive
collision avoidance radars, the required scan ranges are 10-20 degrees [97]-[98].
Therefore, new techniques that reduce the cost o f phased arrays must be developed for
these applications. The phased array cost can be reduced by reducing the number of
phase shifters [102] or eliminating them [103]-[105],
In this chapter, the theory and measurement results for a new phased array technique
based on the extended resonance power dividing method is presented. The extended
resonance is a power dividing / combining technique, which results in a very compact
and highly efficient (> 90%) circuit structure [106]. This approach eliminates the need for
separate power splitter and phase shifters in a conventional phased array system, and
achieves power dividing and phase shifting using the same circuitry, resulting in
significant amount o f reduction in the circuit complexity and cost.
51
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Phase
Shifters
V
V w w w V
Antennas
FEED N ETW O RK
B e a m T e rm in a l
F igu re 3.1:
C o n v en tio n a l p h ased array con cept.
3.2. THEORY
An N-port extended resonance power divider circuit is shown in Figure 3.2. The
admittance connected to the nth port for n<N is G+(2n-l)jB, whereas the admittance
connected to the last port is G+(N-l)jB. The length o f the first transmission line, l\, is
chosen such that the admittance at the first port is transformed to its conjugate, G-jB. The
admittance seen at the second port is 2(G+jB). Similarly, the length o f the second
transmission line, h, is chosen to transform 2(G+jB) to its conjugate, 2(G-jB), hence the
admittance seen at the third port is 3(G+jB). This process is performed (N -l) times, and
at the last stage, the admittance seen at the plane of the (N -l)th transmission line will be
(N-l)(G-jB) and the admittance seen at the N*h port will be NG, which is matched to the
source impedance using a quarter-wave transformer. The analysis of this structure shows
that the voltages at each port are equal in magnitude (equal power division), but not in
phase. This feature has been exploited for the design o f power amplifiers at microwave
and millimeter wave frequencies [106]-[110].
52
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(N -2)(G -jB )
(N -l)(G -jB )
NG
(N -l)(G + jB )
2(G+jB) G -jB
G+jB
L L
L
^
X/4
I
transformer
? port # N -
l
^
port
V
Port ^
N -l
G + ( N - l) j B
JU
G + (2 N -3 )jB
JU
F igu re 3.2:
antenna # 3
v ant3
vantN
J /
N -l
\ / 2 apart
----
4>offset2
^3C
(N -l)C
(N -l)G an+ (N -l)jO )C
V,
^antl
^ o ffse t 1
'1
1
c
G ant+jcoC
3 G ant+3j(OC
NG ant
F igu re 3.3:
antenna # 1
v2
VN
A/4
transformer
antenna # 2
v ant2
*^offset3
^ o ffse t I
Rs
Jr.
E xten d ed reson an ce co n cep t incorporating N -p orts.
antenna # N
V.
G+jB
G+3jB
_r_
2G ant + 2j COC
T h e ex ten d ed reson an ce b a sed p hased array con cept.
The concept of a phased array based on the extended resonance technique is depicted
in Figure 3.3. The power divider ports are connected to an antenna (G=Gant) in shunt with
a tunable capacitor (varactor) (B=coC). Instead o f a transmission line, a tunable inductor
is used to transform the admittance to its complex conjugate as the shunt varactors are
tuned. The required inductance to transform the admittance, nGant+nj(oC, to its complex
conjugate, nGanrnjcoC, is:
L =-
2C
nG lant + nco2C 2
53
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.1)
Using the inductor value found in (3.1), the ratio o f the voltages between successive
ports is:
(g ^ + i o c y
V,
(3.2)
G 2„,+ffl2C 2
Therefore, the magnitude o f the voltage ratio is
v»+i
'
(3-3)
and the phase difference between successive ports is
Vn
=
@ n+ i,»
'
~ tan-1-I
~ T r* i
\ G ant\ - c o AC '
^
(3 -4 >
Equation 3.4 can be further simplified as:
-il «jC
0 ^ = 2 . tan"1
(3.5)
ant
Note that successive power divider ports have the same phase difference given by
(3.5) regardless o f the port number in the circuit. It should be mentioned that in a uniform
amplitude phased array, all the antennas are excited with the same amplitude, and the
phase difference between the adjacent antennas must be the same. Therefore, by tuning
the varactors as well as inductors given by (3.1), one can obtain equal power division
among antennas as given in (3.3) and the same phase shift between successive power
divider ports as given in (3.5). Thus, a phased array system with one-dimensional
scanning capability can be designed. Due to the initial phase offsets between the power
54
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
divider ports, constant phase delays
(<&0ffs e ti,
& o ffse t 2,
—
$ offsetN )
are used as shown in
Figure 3.3 to set the initial phases at the antenna nodes equal to each other. From then on,
the beam is steered around the boreside of the antennas by tuning the varactors. Since
realizing tunable inductors is not easy, the circuit o f Figure 3.3 can be further modified.
Artificial tunable inductors can be realized using an impedance inverter consisting o f two
quarter-wave transformers with a shunt varactor in between [90]. This will both ease the
realization of the tunable inductors and provide approximately }J2 spacing for the
antennas. The modified extended resonance based phased array circuit is shown in Figure
3.4. Based on the theory outlined so far, simulated array factor for a 4-antenna extended
resonance phased array for various normalized capacitive susceptances is shown in
Figure 3.5 (antennas are X/2 apart). The simulated scan range is 24 degrees for a varactor
tunability of 4:1. Extended resonance beam-steering technique can also be used to design
phased arrays with two dimensional scanning capability as shown in Figure 3.6. Multiple
1-dimensional horizontal scanning arrays are fed using a vertically scanning extended
resonance circuit to achieve 2-dimensional beam-steering capability. It should also be
noted that extended resonance phased arrays can be designed for non-uniform power
distribution among antennas (array taper) to achieve low side lobes. In extended
resonance circuits, since the magnitude of the voltage at each node is equal to each other,
the real part o f the port admittance can be chosen so that the required power distribution
is achieved. Then, the imaginary part can be chosen such that equal phase shift is
achieved between successive antennas.
55
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
a n te n n a # 1
a n te n n a # 2
a n te n n a # 3
V
V
z0,m
V
a p a rt
^offset 2
’{’offset 3
z 0 , A/4
X q/2
z 0 , W4
V2
Z 0 , A/4
^offset 1
Z 0 , A/4
r V|
if:3C
tra n s fo rm e r
? 'C
■ N -l
3 G „ ,+ 3JCCC
F igu re 3.4:
o
x
+
*
□
2 G „ t +2j(0C
A m ore realizab le exten d ed reso n a n ce b a sed p h ased array.
(oC/Gant=0.5
coC/G =0.7
ant
©C/Gant=1
©C/G =1.4
©C/G =2
Angle, degrees
F igure 3.5:
S im u lated array factor for a 4-an ten n a ex ten d ed reson an ce p h ased array (antennas
are X /2 apart, varactor tun ability is 4 :1, the circuit is a ssu m ed to b e lo ssle ss).
56
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
antenna #(N ,1)
antenna # (N,2)
antenna # (N,N)
offset 2
o ffset 1
(N .1)
(N ,2)
in p u t N
antenna #(2,1)
antenna # (2,2)
antenna # (2,N)
o ffset 1
o ffset 2
o ffset N
(2 ,2)
(2,N )
3C:,
input 2
z
(2 , 1)
(N -l)C
x , a/4
antenna# (1,1)
antenna# (1,2)
antenna# (1,N)
'in —1
Zj
,
am
offset 2
o ffset 1
(1,2)
in p u t 1
Rs
A/4
transformer
F igu re 3.6:
E xten d ed reson an ce p h ased array for tw o d im en sio n a l scann ing.
57
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(i,i)
3.2.1. Maximum Achievable Scan Range
The maximum achievable phase shift for a given varactor tunability is studied next.
The achievable phase shift between power divider ports when the varactors are tuned is:
A 0 = 0 ,.ll, ( C ) - ( U 1(C /< )= 2 -ta n G an,
j
1
G an,
j
(3.6)
where t is the tunability o f the varactor (the ratio of the maximum capacitance to the
minimum capacitance). Note that varactors at various ports have different values, but
they have the same tunability, t. A plot o f the achievable phase shift, A # , versus the
normalized capacitive susceptance, coC/Gant, for various varactor tunabilities is shown in
Figure 3.7. The plot indicates that depending on the tunability o f the varactor, there exists
an optimum normalized capacitive susceptance, which results in the maximum phase
shift between power divider ports, or maximum scan angle for the phased array. The
optimum normalized capacitive susceptance is also found analytically by finding the
roots o f the derivative o f the achievable phase shift, A d , with respect to the normalized
capacitive susceptances as given below:
d( A d)
r
V
coC
ant J
2 -t
_____2
„ \
coCopt
1+
\
\2
ojC,opt
\
ant J
\2
=
0
(3.7)
ant J
Therefore, the optimum normalized capacitive susceptance is:
opt
(3.8)
58
Reproduced with permission o f the copyright owner. Further reproduction prohibited without permission.
The resulting maximum achievable phase shift between power divider ports is
therefore:
A plot of the maximum achievable phase shift and resulting scan range for a phased
array with half wavelength antenna spacing versus the varactor tunability is shown in
Figure 3.8. Varactors are usually fabricated using solid-state, ferroelectric [64]-[69], and
MEMS [51]- [56] technologies. As mentioned in chapter 1, solid-state based varactors are
well-mature and are commercially available, presenting the most economic choice.
MEMS and ferroelectric based varactors have better performance; however, they are not
mature enough yet. Depending on the technology utilized, varactors can either be tuned
continuously by changing the applied DC voltage or be tuned discretely by switching
capacitors or transmission lines using p-i-n diodes, FET or MEMS switches. Examples of
varactors with continuous timing include solid-state varactor diodes or ferroelectric
varactors. They can achieve typical tunabilities in the range o f 3:1 to 6:1, whereas
varactors with discrete tuning can achieve very high tunabilities [55]. Therefore, using
solid-state varactor diodes or ferroelectric varactors, phase shifts in the range of 60-90
degrees can be achieved from extended resonance based phased arrays, which
corresponds to 20-30 degrees of scan range in a phased array with half wavelength
antenna spacing. For switchable length transmission lines, the achievable phase shift
approaches 180 degrees, or 60 degrees o f scan range in the phased array. More phase
shift can be obtained by cascading several extended resonance phase shifters as shown in
59
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.9. In this case, the phase shift can be multiplied by the num ber o f stages at the
expense o f using more varactors.
£ 120
2 100
Q.
40
Tunability=3:1
Tunability=5:1
Tunability=7:1
T unability=10:1
T unability=15:1
20
N orm alized c ap a citiv e s u s c e p ta n c e
Figure 3.7:
T h e a ch ievab le p h ase sh ift b etw e en s u c c e s siv e p o w er d ivid er ports for various
varactor tunabilities.
140
45
120
40
V)
CD
CD
35
100
30
25
.c
CO
20
CD
</5
CO
■C
15
10
CL
w
J:
L.
O
)
(D
T3
CD~
O
)
C
QC
c
CO
o
CO
5
0
0
5
15
10
Varactor Tunability
F igu re 3.8:
20
25
( C m a x /C ,™ )
M axim u m a ch iev a b le p h ase sh ift and scan range versu s varactor tunability.
60
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
antenna # 1
antenna # 2
V
A.q/2
?
apart
^ offset 1
offset 2
Z0 , A/4
V2 Z 0 , A/4
Z 0 , A/4
V,
i f : 3C
T
2(G ant+jOJC)
Figure 3.9:
2C
CL
Ll
^
?kc
CL,
® ant+J®^
® ant+j®^
C ascad ed ex ten d ed reson an ce p h ased array for h igh er scan range.
3.2.2. Effect of Varactor Quality Factor on the Phased Array Efficiency
The theory given in the previous section did not consider any circuit loss. The effect
o f finite varactor quality factor (Q) on the efficiency o f the extended resonance array feed
is studied in this section. The equivalent circuit model for the varactor is shown in Figure
3.10 and its associated quality factor is given in (3.10).
(3.10)
Gr
Therefore, at the power divider ports, some portion of the divided power is radiated
through the antenna with input conductance o f Gant, and the rest is dissipated within the
varactors through their shunt conductances. Assuming all the varactors in the circuit have
the same quality factor, the efficiency of the extended resonance phased array feed can be
calculated as given in (3.11) by taking the ratio o f the total radiated power from the
antennas to the sum o f the total radiated power and the power lost within the varactors:
61
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.10: Equivalent circuit model for the varactor.
^ ant
.-------Efficiency = ----------- ^
N-Gm +2(N-\)N-G,
(3-11)
where N is the number of antennas (N>1). Equation 3.11 can be further simplified using
(3.10) as:
Efficiency = ---------- —-----—T
Q+2(N
(3.12)
ant
A plot o f the efficiency versus varactor quality factor for a 4-antenna phased array is
shown in Figure 3.11. Solid state-based varactors usually achieve quality factors in the
range o f 20 to 80. Therefore, it is possible to realize efficiencies higher than 75 % using
commercially available solid-state varactors. Higher efficiencies can be achieved using
switched sections of transmission lines as tuning elements due to their higher quality
factors.
62
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
100
oc>.
a)
'o
it
LU
Capacitor quality factor
Figure 3.11: Simulated array feed efficiency versus varactor quality factor for N=4 antennas.
3.3. DESIGN OF A TWO GHZ PHASED ARRAY
To demonstrate the utility o f the extended resonance phased array concept, a 2 GHz
extended resonance based phased array consisting o f four edge coupled microstrip patch
antennas placed half wavelength apart was designed, fabricated and tested [111]-[113]. A
31 mil thick RT/duroid 5880 substrate from Rogers Corporation with a dielectric constant
of 2.2 and MSV34 series chip varactor diodes from Metelics Inc. were used to fabricate
the phased array. Since via holes and bond wires must be utilized to connect the chip
varactors to the circuit, the overall C-V curve and quality factor of the varactors were
estimated using Agilent-ADS based on the C-V curve and quality factor for the chip
varactors, bond wires and substrate parameters as given in Table 3.2. The tunability of
63
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the varactors was 3.2:1 with the application o f 3 V to 30 V reverse bias. The required
antenna impedance was determined to be 67 Cl.
Capacitance
(pF)
2.736
2.251
1.619
1.453
1.33
1.235
1.093
1.039
0.992
0.952
0.884
0.855
V dc
(V)
3
4
8
10
12
14
18
20
22
24
28
30
Table 3.1:
Q at 2
GHz
24.4
29.2
45.5
51.7
58.1
63.8
72.8
75.8
78.7
83.7
90.1
94.1
Varactor C-V values and Q factor at 2 GHz with via holes and bond wires.
3.3.1. Microstrip Antenna Design
The procedure in [114] was followed to make a preliminary microstrip patch antenna
design. The width o f the antenna was calculated using:
W =— J - 2 —
2 /o lk + l
(3.13)
where c is the speed o f light, fo is the resonant frequency of the microstrip patch antenna,
and s r is the dielectric constant o f the substrate. The effective dielectric constant o f the
microstrip antenna was determined using:
64
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
where h is the substrate thickness. Once W and s r_eff is calculated, the extension length
of the microstrip patch due to the fringing effects can be calculated using:
( < W + 0 . 3 ) { 2 . + 0.264
AL = /?• 0.412------------------ ^ ---------- (■
(3.15)
( e ^ . - 0 . 2 5 8 ) - ^ + 0.8
Therefore, the length of the microstrip patch is given by:
L=
j
- -2 A L
2 / 0y j £ r - e /f
(3.16)
Using these equations and the substrate parameters, a 2 GHz microstrip patch antenna
was designed, and also the dimensions were optimized using Agilent-ADS Momentum
simulation software to achieve the correct resonant frequency. The final microstrip patch
antenna dimensions were determined to be 5.87x4.98 cm2. The input impedance o f the
microstrip patch was designed as 67 Cl by recessing the feed point by 1.62 cm as shown
in Figure 3.12.
65
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 3.12: Microstrip patch antenna layout and dimensions.
Due to the initial phase offsets, constant phase delays must be used for the phased
array to scan the broadside. This has been achieved by using meandered microstrip lines
to give the desired phase delay for a given spacing between the antennas and the
varactors. Meandered microstrip lines were designed using Agilent-ADS layout engine,
and momentum simulations were performed to accurately determine the designed phase
delay. Tunable inductors have been realized using impedance inverters with two quarter
wave transformers with a shunt tunable capacitor in between. The microstrip line
impedances were all chosen to be 67 £2 (width=0.162 cm). A quarter wave transformer
with a characteristic impedance o f 25 Q (width=0.614 cm) was also used at the input to
transform the impedance seen at the last port to the source impedance. A photograph of
66
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the phased array is shown in Figure 3.13. The DC bias to the varactors was applied using
a bias-tee at the input, and the DC bias to the varactors for artificial tunable inductors was
applied through separate bias networks as shown in Figure 3.13. The overall size o f the
phased array is 39x25 cm2.
Figure 3.13: A photo of the phased array (array dimensions are 15.4x9.8 inch2).
The radiation pattern and gain of the phased array was measured in an anechoic
chamber. In addition, the magnitude and phase o f the signal at each antenna node was
measured using a vector network analyzer by replacing the microstrip antennas with
microstrip launchers. Using the measured scattering parameters from the input o f the
phased array to each antenna port, the resulting array factors were computed. The array
feed efficiency was determined using (3.17) by comparing the maximum value o f the
67
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
array factor to the ideal maximum array factor o f an extended resonance array feed (ideal
power/phase distribution, no loss).
(
4
max
77 =
jkd cos(0)
n
'\
e
\ i =1
•100
(3.17)
where Su is the complex s-parameter from the input o f the phased array to the ith output
port, k is the free space wave number ( k = 2jz I A ), d is the spacing between antennas
(<7=A/2) and 0 is the angle from the bore side o f the array. Measured H-plane patterns of
the phased array for various diode voltages are shown in Figure 3.14. The summary of
the array performance is given in Table 3.2. The measured scan angle and array feed
efficiency versus the diode voltage is also plotted in Figure 3.15. The phased array can
steer the beam by +/- 10 degrees with the application o f 3 V to 30 V reverse bias to the
varactor diodes, which compares well with the simulated scan range. The measured side
lobe level was better than -9 dB and the average 3-dB beam width was 25 degrees. The
measured array feed efficiency was approximately 80 % (corresponds to 1 dB insertion
loss). The array feed efficiency decreased to 59 % (2.3 dB insertion loss) as the diode
voltage is reduced to 3 V due to the increased loss o f the varactors at low reverse bias
voltages. It should be noted that other tunable capacitors with lower loss, such as
ferroelectric [64]-[69] or MEMS based tunable capacitors [51]-[56], switched capacitors
or transmission lines using p-i-n diodes or MEMS switches are expected to provide a
better performance. The measured return loss o f the phased array was better than 10 dB
for all the diode voltages tested as shown in Figure 3.16 and cross-polarization was lower
than -23 dB.
68
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3 Volt
4 Volt
8 Volt
12 Volt
18 Volt
30 Volt
-2
-4
TJ
-6
Q.
O.-10
m -1 2
-1 4
-1 6
-1 8
-4 0
-20
Angle, degrees
Figure 3.14: Measured H-plane pattern for various diode voltages (measured gain at 30 V is 8.7
dB).
Diode
Voltage, V
Scan Angle,
degrees
3 dB Beamwidth,
degrees
Side Lobe
Level, dB
Gain,
dB
Array Feed
Efficiency, %
3
4
8
10
12
18
24
30
10
6
2
0
-2
-4
-6
-10
24
24
26
24
24
26
26
28
-9.1
-12
-14
-13.5
-12.5
-11
-11
-9
6.9
7.5
8.1
8.4
8.4
8.6
8.7
8.7
59
67
80
82
82
83
82
80
Table 3.2:
The measured performance of the phased array.
69
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15
90
80
<o
CD
CD
t_
10
O)
CD
"O
Jif
O)
c
5
c
CD
O
-5
<
C/3
70
60 ^
50
$
40
I
0
30 S
20
-10
10
-15
0
0
5
10
15
20
25
30
35
Diode Voltage, V
Figure 3.15: Measured scan angle and array feed efficiency versus the diode voltage (varactor
tunability is 3.2:1 from 3 V to 30 V).
-1 0
- e - 3 Volt
4 Volt
- A - 8 Volt
- I - 12 Volt
18 Volt
30 Volt
Return Loss, dB
-12
—14’
-e-e-e-
-16
-18
-20
-2 2
-24
Frequency, GHz
Figure 3.16: Measured return loss for various diode voltages.
70
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3.4. DESIGN OF LARGER EXTENDED RESONANCE PHASED
ARRAYS
The extended resonance phased array circuit presented in Figure 3.3 requires the
value o f the tunable capacitors to increase progressively as odd multiple o f the first
varactor capacitance and the value o f the tunable inductors to decrease progressively.
This may place a limit on the order o f the array due to the lack o f availability o f arbitrary
varactor values. In addition, tunable inductors were previously realized using impedance
inverters consisting o f two quarter-wave transformers and a shunt varactor. However, this
approach limits the bandwidth due to the quarter-wave transformers used and increases
the complexity o f extended resonance phased arrays due to the added biasing networks.
In this section, the design methodology for an extended resonance based phased array,
which utilizes fixed inductors and single value varactors throughout the entire design, is
presented. Thus, the circuit complexity is significantly reduced and the fabrication of
higher order phased arrays is facilitated.
The required tunable inductor value as the varactor capacitance changes can be
calculated using (3.1) and (3.8) as:
L„=—4 -------- P ^ - =L0- f
nco Cmax x + t max
x +?max
(3. 18)
where (O is the angular frequency, Cmax is the maximum varactor capacitance, tmax is the
tunability o f varactors, and x, varactor tuning parameter, represents the instantaneous
value o f the varactor such that Cinstantcmeous=Cmax/x (hence, x ranges from 1 to tmax). A plot
o f L„/Lo as a function o f the varactor tuning parameter is shown in Figure 3.17. The
71
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
maximum value o f the required inductor can be found by finding the root o f the first
derivative of (3.18) as a function o f x and calculating L n as given below:
max
77
(3.19)
-max
Since the minimum value o f L„ occurs at the extreme values o f x (x= l or x=tmax), the
required inductor tunability as a function of tmax can be calculated as follows:
max
/7-max
max
(3.20)
max
max
where ti is the required inductor tunability. A plot o f ti as a function of tmax is shown in
Figure 3.18. It turns out that the required inductor tunability is considerably smaller than
the varactor tunability.
Let us now observe the effect o f a fixed inductor, whose value is chosen to be the
minimum value shown in Figure 3.17 (L, - Ln_min = L 0 -tmiX/(\ + tmm)), on the input
admittance (Yin) and voltage ratio (V 2/V 1) between the two adjacent nodes as shown in
Figure 3.19. The resulting real and imaginary parts of the input admittance as the varactor
is tuned are plotted in Figure 3.20 (It is assumed that Gj=Gant=l/50Q, tmax=4, and f= 10
GHz, Cmax is calculated using (3.8)). The analysis shows that the admittance seen at the
1st port is transformed to its exact conjugate for the maximum and minimum values o f the
varactor capacitance. Therefore, the real part of the admittance is 0.02 mhos (50Q) and
the imaginary part is 0 mhos. Since the inductor value is kept constant, there will be
72
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
errors in the impedance transformation and consequently in the amplitude and phase of
the voltage ratio as the varactor capacitance changes between its maximum and minimum
values. The resulting magnitude and phase o f the voltage ratio between 2nd and 1st node
as a function o f the varactor tuning parameter, x, is shown in Figure 3.21. The magnitude
of the voltage ratio is 1 (0 dB, no error) for maximum and minimum values o f the
varactor. However, because o f using a fixed value inductor, up to 2 dB o f error in the
magnitude of the voltage ratio is created as the varactor capacitance is tuned. It should be
noted that by designing the impedance presented at the 2nd node using (3.21), the power
delivered to the 2nd antenna can be adjusted such that the power division error is ±1 dB
(instead o f 0 to -2 dB) as the varactor capacitance is tuned. This can be realized either by
designing the antenna input impedances and offset lines given by (3.21) or by designing a
matching network between the 2nd node and the offset line. However, the latter solution is
easier to achieve since the same antenna design can be used for the entire phased array. It
should also be noted that the achievable phase shift between 2nd and 1st node is not
affected due to the fixed value inductor.
° 2
~ max(| V2 / Vj |)- min(| V2 / V{ |)
73
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
° 2l)
0.98
0.96
0.94
0.92
0.9
0.88
0.86
0.84
0.82
0.8
3.5
2.5
x
Figure 3.17: Normalized inductor value as a function of x (tmax=4).
2.5
V aractor tunability (t
)
Figure 3.18: Inductor tunability vs. varactor tunability.
74
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
antenna # 1
Figure 3.19: Extended resonance section incorporating a fixed inductor.
0.04
0.035
E 0.03
0.025
0.015
0.01
3.5
2.5
0.04:
o
imag(Y )
« 0.03
0.02
<x«**xxx*xxxxxxx*xx
1 0.01
CCCXXXX»OOOCX)OCOOOOOOOOOOOOO(>
-
0.01
2.5
3.5
X
Figure 3.20: R eal and im aginary parts o f the input adm ittance in F igure 3 .1 9 com p ared w ith the
first sta g e ’s cap acitan ce and antenna input con d u ctan ce as a fu n ctio n o f x.
75
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
-0.5
-1.5
1.5
2.5
3.5
2.5
3.5
140
x
Figure 3.21: Magnitude and phase of the voltage ratio between the 2nd and 1st nodes as a function
of x.
Using (3.21), the admittance that needs to be presented to the 2nd node is calculated as
G2=l/40 mhos for tmax=4 and G i= l/50 mhos as shown in Figure 3.22. The real part o f the
resulting input admittance is shown in Figure 3.23, which increases due to the addition of
G2 . Previously, the 2nd varactor value was chosen to be three times larger than the 1st
varactor value in order to satisfy (3.8) and to achieve the same phase shift between nodes
3-2 and 2-1. This has two drawbacks. Firstly, the increasing real and imaginary parts of
the admittances towards the source side makes the design o f large arrays very difficult
due to the difficulty of matching very low impedances. Secondly, arbitrary varactor
capacitances may not be available commercially. In order to avoid these issues, the input
admittance seen in Figure 3.22 is transformed back to the first conductance, Gi=Gant,
76
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
using an LC-matching network as shown in Figure 3.24. The series inductor,
shunt capacitor,
C match2 ,
L malch2 ,
and
are designed as given in (3.22) and (3.23) such that the input
admittance is transformed to
Gy
for the maximum and minimum values o f the varactor
capacitance.
G ,n-ana ( x = 1)
•1
Gam
match!
(3.22)
' G in-antl ( X ~
f
’
match2
—
n-3 \
^~,malch2G in-ant2^.X
, ,
9 r2
^ 2
/
i\
1 + co L match2G jn_ant2 ( x - 1)
where Gi„.ant2 is the real part o f the input admittance, Yin.ant2 . Let us now observe the real
and imaginary part of the input admittance after the LC-matching section,
Y in.maich2 ,
as
shown in Figure 3.25. The real part o f the admittance varies between 0.0184 mhos (54 Q)
to 0.0206 mhos (48.5 Q) as the varactor capacitance changes, which is in the close
vicinity of Gy. The imaginary part also varies in the close vicinity o f 0 mhos. Therefore,
using a fixed LC-matching section, the input admittance seen at the second stage is
transformed back to
G y.
It should be noted that at microwave frequencies, fixed inductors
and capacitors can be realized either through short high and low impedance transmission
lines, or by open or short circuited stubs. If the design frequency is not very high, lumped
element inductors and capacitors can also be used.
77
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
antenna # 1
antenna # 2
Y
Y
• ^antl
^ant2
°
Vo
^offset2
^offset 1
f
L
G2
-rw w -
G,
-V
?Fc
Y in-ant2
^ in-ant2 ~ ^ ant + J^
Figure 3.22: Extended resonance section after the 2nd antenna is added.
0.06
o real(Y.
v in-ant2'’
x* Gant
0.055
0.05
!0000o° o o c c o o o <)
<8 0.04!
g
0.04
<? 0.035
0.03
0.025
0 . 02 :
3.5
Figure 3.23: Real part of the input admittance in Figure 3.22 compared with the first stage’s
antenna input conductance as a function of x.
78
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
antenna # 2
antenna # 1
t
^ a n t2
Matching Network
^match2
V
Yantl
^offset 1
f
Pi
Ll
Pmatch2
^ in-m atch2
^ in-an t2
^ in -an t 1 —^ ant + J^
Figure 3.24: LC-matching network transforming the admittance to the first antenna admittance
0.021
0.0205
g 0.0195
8
■§
o
xx
0.019
0.0185
0.018
real(Y.in-match2'
G ant '
2.5
0.04:
3.5
o
imag(Y
S 0.03
0.02
X X X X X X X X X X X X X X X H
tj30cjCDC^ ^
-
0.01
2.5
)
3.5
X
Figure 3.25: Real and imaginary parts of the input admittance in Figure 3.24 compared with the
first stage’s capacitance and antenna input conductance as a function of x.
79
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
After the LC-matching section, an extended resonance circuit with the same varactor
and fixed inductor value is designed to achieve phase shifting between the 3rd and 2nd
nodes, and the 3rd node is terminated with G3 as shown in Figure 3.26. It should be noted
that the 3rd varactor is in parallel with the matching capacitor, Cmatch2 ■ Therefore, the
value of the matching capacitor can be added to the value o f the varactor. Similar to the
procedure performed after the 2nd node (i.e. LC-matching, extended resonance circuit,
and antenna connection), the same procedure is performed to make an N-antenna phased
array. The circuit parameters to be able to connect N stages are given below:
Gin-ant(n)
j
Gam
^m atch(n)
_
~
(3.24)
® ' Gtn-ant(n) i X ~ 0
0
^ Jmatch(n)G m -ant(n)^.X
i
2r2
,
1^
W
7^2
match(n)
in-ant(n)
,
in
v
V)
Gn+1 —
/, T/ /t/ |\ ■ (\ j/ it/ |\
max(| Vn+t IVn I)-mind Vn+I/ Vn |)
'
>
(3.26)
where Gin.ant(n) is the real part o f the input admittance seen at the terminal of the nth node,
Lmatch(n) and Cmatch(n) are the inductance and capacitance o f the matching section for the nth
stage, and Gn is the conductance terminating the nth node. At the end, the input
admittance can be matched to the source impedance using a matching section, such as a
quarter wave transformer or a single stub tuner. Let us now observe the real and
imaginary parts of the admittances after the LC-matching sections as a function o f the
varactor tuning parameter, x, for a 20 antenna phased array as shown in Figure 3.27. The
80
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
real part o f the admittance varies between 0.018 mhos (56 Q) and 0.027 mhos (37 Q) and
the imaginary part varies between 0 mhos (°° Q) and 0.007 mhos (143 Q) as the varactors
are tuned. The ratio o f the powers delivered to adjacent antennas and phase o f the voltage
ratio between adjacent nodes as the varactor capacitance changes are also shown in
Figure 3.28 and Figure 3.29, respectively. The highest power division error is ± 1 dB,
which occurs between the first and second nodes, and the error decreases towards the
input. The achievable phase shift between adjacent nodes are all equal to each other,
however as the varactors are tuned, there exists an error of up to 10 degrees in the phase
of the voltage ratios.
In this section, a power dividing and phase shifting scheme was introduced using
single value varactors, and fixed inductors throughout the entire extended resonance
phased array design. Therefore, the complexity due to the increasing varactor values,
tunable inductors and the biasing networks were eliminated. It is concluded that the input
power is divided among antennas with an error of less than ± 1 dB as the varactors are
tuned. Also, there exists an error o f less than 10 degrees in the phase shifts between
adjacent antennas as the varactors are tuned. However, the effect o f these errors on the
phased array performance must also be studied as presented next.
81
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antenna # 1
antenna # 2
antenna # 3
Matching Network
N Stages
connected similarly
Figure 3.26: The extended resonance phased array concept utilizing a single value varactor
throughout the whole design.
0.03
real(Y.
’
' in-match n)‘
Gant.
0.028
E 0.026
<D
g 0.024
(0
1 0.022
■O
0 . 02 :
<
0.018
o#e*coa5ooo<xx>o<xxxxxxxxxxxxxxxxxxxxx
2.5
3.5
X
0.04:
imag(Y
«
in-match(n)'
0.03
n
E
o
0.02
|
0.01
5
0
o
:xxx x x x x x x x x x x x x x x X.x.xxx xx xx-):
E
-
0.01
2.5
3.5
X
Figure 3.27: Real and imaginary parts of the input admittance for N=20 antenna phased array.
82
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0.8
0.6
0.4
0.2
q_c-0.4
-
0.6
-
0.8
2.5
3.5
x
Figure 3.28: The ratio of the powers delivered to adjacent antennas as a function of x (N=20
antennas).
70
0)50
•o
2.5
3.5
x
Figure 3.29: Phase of the voltage ratio between adjacent nodes as a function of x (N=20
antennas).
83
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
3.4.1. A rray F actor Sim ulation
A 20 antenna phased array is designed based on the theory in the previous section and
the array factors are simulated. The details o f the simulation setup is shown in AppendixD. The phase offsets between the power divider ports and antennas are calculated using:
offset(n+1)
r offset{n)
I^
/
mm
V
r
V
Vn+x A
+ max
Vn
(3.27)
where the first offset can be chosen arbitrarily. Also, integer multiples o f 360 degrees can
be subtracted from the phase offset if it is higher than 360 degrees. The array factor (AF)
o f the phased array is calculated using the following relation:
A F = Y deJ**-dMe)S niU
n-
(3.28)
1
where k is the free space wave number, d is the antenna spacing (usually d=A/2), 6 is the
angle from the boreside o f the antenna, and Snj i is the complex S-parameter from the
input o f the phased array to the nth antenna (input port number is 21 as shown in
Appendix-D). The simulated array factors for various varactor capacitance values are
shown in Figure 3.30. As a comparison, the array factors for a 20 antenna phased array
with ideal amplitude (uniform) and phase distribution are also plotted in Figure 3.31. The
performances o f the two arrays are very similar to each other, showing that utilization of
fixed inductors and fixed matching sections does not severely degrade the performance of
the phased array. The maximum array factor o f the extended resonance phased array is
approximately 0.5 dB lower than that o f a phased array with ideal amplitude and phase
distribution, and the side lobe levels are better than 12 dB.
84
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15
-30
-20
-10
0
10
20
30
Angle, degrees
F igu re 3.30: S im u lated array factor for a 2 0 antenna p h a sed array.
Q
o
to
u.
>.
g
<
-5 -
g -10 -
-20
-30
-20
-10
0
10
20
30
Angle, degrees
F igure 3.31: S im u lated array factor for a 2 0 antenna p h ased array w ith id ea l am plitu de and p hase
distribution.
85
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Therefore, one can design a phased array with near ideal performance by using single
value varactors and fixed inductors throughout the entire phased array. The required
component values for a 10-GHz 20-antenna phased array based on the outlined theory are
given in Table 3.3 and Table 3.4. The design results in feasible values for inductor and
capacitor values, however as the order o f the array increases, the required impedances
(1/Gn) that must be presented at the power divider ports increase dramatically, which in
effect limits the maximum practical array size for this specific structure to approximately
7-10 antennas. In the next section, an improved topology is introduced, which enables the
design o f larger arrays.
f
(GHz)
10
Table 3.3:
1/Gi
(A)
50
Tunability
(tmax)
4
rv-/max
(pF)
0.64
Li
(nH)
0.64
Basic design parameters for the phased array.
11
1/G„
(ft)
413
f inatch
(nH)
0.247
Gmatch
(pF)
0.111
0.356
12
456
0.238
0.105
0.389
0.258
13
498
0.229
0.101
121
0.362
0.205
14
538
0.222
0.097
5
170
0.333
0.173
15
580
0.215
0.094
6
212
0.313
0.154
16
623
0.209
0.090
7
247
0.298
0.143
17
663
0.203
0.087
8
288
0.283
0.133
18
704
0.198
0.085
9
333
0.268
0.123
19
746
0.193
0.082
10
374
0.257
0.116
20
787
Stage
Tinatch
(nH)
1
1/Gn
(ft)
50
2
40
0.395
3
76
4
Table 3.4:
Stage
Gmatch
(PF)
Resulting component values for the phased array.
86
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3.4.2. Symmetrically Fed Tapered Extended Resonance Phased Arrays
In the previous section, it was shown that the impedances that must be presented at
the power divider ports (1/G„) increase towards the source side. Hence, the maximum
practical array size is determined by how large these impedances can be fabricated at the
last port. In this section, a modified approach to design larger phased arrays based on the
extended resonance technique is presented. Phased arrays are usually designed for nonuniform power distribution among antennas (array tapering) to achieve low side lobe
levels or no side lobes at all. This, however, increases the overall beamwidth of the
phased array. Binomial and Chebyshev tapers are two o f the most commonly used array
tapers [115]. In Binomial and Chebyshev arrays, the antennas in the array are excited by
Binomial or Chebyshev coefficients (i.e. the power radiated from each antennas is
proportional to these coefficients). These coefficients are symmetric, and their values are
the highest at the center antennas, which decrease towards the side antennas in the array.
Consider the structure in Figure 3.32, where two extended resonance phased arrays
are connected at the input. The two phased arrays are identical to each other such that:
'match(i)
'm a tc h (2 N -i)
m a tc h (2 N -i)
match(i)
a n tenna(2N -i)
antennaii)
87
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(3.29)
(3.30)
(3.31)
—IfcH"
F igure 3.32: T he sym m etrica lly fed exten d ed reso n a n ce p h ased arrays.
88
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
They also utilize the same varactors, however the varactors on the left and right phased
arrays are tuned differently so that equal phase shifts between adjacent antennas are
achieved throughout the entire phased array. This is required since the left phased array is
a mirror of the right phased array. If, for example, the phase shifts between the adjacent
antennas in the right phased array has an increasing trend as the varactors are tuned, the
phase shifts between adjacent antennas in the left phased array must have a decreasing
trend so that when the left phased array is mirrored, the overall phased array has an
increasing phase shift trend as the varactors are tuned. The required tuning values for the
varactors in the left and right phased arrays are derived next. The voltage ratio between
the adjacent nodes o f an extended resonance section with a fixed inductor as shown in
Figure 3.19 can be found as:
£
= 1 + jcoLx -{G + j(oC)
(3.32)
Equation 3.32 can be further simplified using (3.8) as:
The phase shift between the 2nd and the 1st node is therefore:
/
(3.34)
Z — = ta n '1
Vx
1
^max
2 t max / X
Equation 3.34 gives the phase shift between the 2nd and the 1st nodes as a function of
the tunability of varactors and the instantaneous varactor value {Cinstantaneous= Cmax/x). For
89
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
the left and right phased arrays to achieve the same phase shift trend as the varactors are
tuned, the following equation must be satisfied.
ta n '1
2A
+ tan'
1 + ^m ax
1+
2 ? m a x / X Iej-t j
= 180°
(3.35)
^ m a x I ^ right y
where xieft and xright are the varactor tuning parameters at the left and right phased arrays,
respectively. Equation 3.35 can be further simplified and the relationship between the
tuning parameters o f the left and right phased arrays can be obtained as:
1+
X Ieft ~
\
1
1
t max
X right J
-
(3.36)
Using (3.36), the required varactor values to result in correct phase shift trends in the left
and right phased arrays can be found. Finally, the phase offsets before antennas can be
determined based on the absolute phases at the antenna nodes and the input impedance
can be matched to the source impedance using a matching network.
A 20 antenna phased array with 40 dB Chebyshev array taper is simulated using
Agilent-ADS to demonstrate the utility o f this approach. The resulting array factors for
various varactor values are shown in Figure 3.33, and the design parameters for this
phased array is given in Table 3.5 and Table 3.6. The side lobe level o f the array factor is
lower than -25 dB. The higher side lobe levels compared to the design value o f -40 dB
are due to the amplitude and phase errors created by the fixed inductors. The required
impedances that need to be connected to the power divider ports vary between 20 Q and
139 Q, which is more practical than the phased array presented in the previous section.
90
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The values for the fixed inductors and capacitors are also feasible at the design frequency
of 10 GHz.
GO
■o
x=1.26
§
(0
x=1.6
x - x = 2.53
b
-30
-20
-10
0
10
20
-
x
= 4
30
Angle, degrees
Figure 3.33: Simulated array factor for a 20 antenna phased array with 40 dB Chebyshev taper.
f
(GHz)
10
Table 3.5:
1/Gi
(Si)
50
Tunability
(tmax)
4
Cmax
(pF)
0.64
L,
(nH)
0.64
Basic design parameters for the phased array in Figure 3.33.
91
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
11
1/G„
(«)
139
0.500
12
106
0.371
0.218
0.369
0.470
13
82
0.386
0.249
29
0.384
0.415
14
63
0.395
0.283
5
38
0.394
0.364
15
49
0.397
0.321
6
49
0.397
0.321
16
38
0.394
0.364
7
63
0.395
0.283
17
29
0.384
0.415
8
82
0.386
0.249
18
23
0.369
0.470
9
106
0.371
0.218
19
20
0.360
0.500
10
139
0.351
0.191
20
50
1
1/G„
(A)
50
2
20
0.360
3
23
4
Stage
Table 3.6:
L m a tc h
C m a tc h
(nH)
(pF)
Stage
L m a tc h
C m a tc h
(nH)
(pF)
0.351
0.191
Resulting component values for the phased array in Figure 3.33.
3.4.3. M axim um A rray Size
In the previous section, a 20 antenna phased array with 40 dB Chebyshev taper was
presented to demonstrate the utility o f extended resonance phased array technique to
design large phased arrays. In this section, extended resonance phased arrays with various
size and amplitude distributions will be studied to evaluate the maximum array size that
can be practically fabricated. The criteria in this investigation is the practicality o f the
impedances that must be presented at the power divider ports as shown in Figure 3.32.
The design values for 30 and 40-antenna extended resonance phased arrays with
Chebyshev array tapers o f 20 to 50 dB are given in Table 3.7 and Table 3.8. The ratio of
the maximum impedance to the minimum impedance that must be presented to the power
divider ports to design an extended resonance phased array varies from 5.55 (30
antennas, 30 dB side lobe level) to 6.65 (40 antennas, 40 dB side lobe level). It should be
noted that microstrip lines are the most commonly used transmission lines in RF &
92
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
microwave circuits. Using a microstrip transmission line, characteristic impedances in the
range o f 20 to 120 Q can be fabricated, which corresponds to a maximum to minimum
impedance ratio o f 6 [116]. The upper limit is set by the production tolerances, whereas
the lower limit is set by the appearance o f the higher order modes. Therefore, extended
resonance phased arrays can be theoretically fabricated with array sizes up to 30 to 40
antennas using microstrip transmission lines. However, it has been concluded from
simulations that the maximum practical array size is not more than 20-25 antennas due to
the component tolerances and errors in the power division and phase shifting. In other
words, constructing larger arrays will not make a significant reduction in the 3 dB
beamwidth o f the phased array. The minimum achievable 3 dB beamwidth is limited to
approximately 5-7 degrees, which can be obtained using a 20 antenna phased array as
shown in Figure 3.33.
93
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Chebyshev (20 dB)
Stage
Chebyshev (30 dB)
(nH)
C m atch
(pF)
1/G„
m
20
Chebyshev (40 dB)
1
1/Gn
(«)
20
2
170
0.098
0.273
47
0.146
0.522
27
0.238
0.563
3
166
0.099
0.276
41
0.150
0.557
24
0.237
0.594
4
141
0.105
0.300
39
0.151
0.568
26
0.238
0.569
5
125
0.110
0.318
38
0.151
0.578
30
0.239
0.527
6
122
0.111
0.322
39
0.151
0.570
36
0.238
0.487
7
116
0.113
0.331
42
0.149
0.548
42
0.236
0.449
8
115
0.113
0.333
46
0.146
0.523
49
0.232
0.415
9
117
0.112
0.329
52
0.143
0.495
57
0.227
0.385
10
119
0.112
0.326
58
0.139
0.468
66
0.221
0.358
11
124
0.110
0.319
65
0.135
0.440
77
0.215
0.332
12
132
0.108
0.310
74
0.130
0.414
89
0.208
0.308
13
140
0.105
0.300
84
0.125
0.388
103
0.199
0.286
14
152
0.102
0.289
96
0.120
0.363
121
0.191
0.264
15
165
0.099
0.277
111
0.115
0.339
142
0.181
0.244
Table 3.7:
L m a tc h
L m a tc h
C m a tc h
(nH)
(pF)
1/G„
(A)
30
L m a tc h
C m a tc h
(nH)
(pF)
The design values for a 30 antenna extended resonance phased array with various
amplitude tapers (half design parameters are given, the second half of the phased
array is designed symmetrically).
94
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Chebyshev (30 dB)
Stage
Chebyshev (40 dB)
1/G„
(ft)
Chebyshev (50 dB)
1/G„
(ft)
1
1/G„
(ft)
20
2
84
0.126
0.389
32
0.155
0.633
22
0.236
0.621
3
76
0.129
0.409
27
0.157
0.684
20
0.234
0.651
4
67
0.134
0.435
27
0.158
0.689
22
0.236
0.619
5
59
0.138
0.463
27
0.157
0.681
26
0.238
0.575
6
58
0.139
0.468
29
0.156
0.659
30
0.239
0.533
7
58
0.139
0.467
32
0.155
0.628
34
0.238
0.495
8
59
0.138
0.464
36
0.153
0.594
40
0.236
0.461
9
61
0.137
0.455
40
0.15
0.563
45
0.234
0.431
10
65
0.135
0.443
44
0.147
0.534
52
0.23
0.404
11
69
0.133
0.43
49
0.144
0.506
58
0.226
0.381
12
73
0.131
0.415
55
0.141
0.48
66
0.222
0.359
13
79
0.128
0.399
61
0.137
0.456
74
0.217
0.339
14
86
0.124
0.383
68
0.134
0.432
83
0.211
0.319
15
94
0.121
0.367
75
0.13
0.41
93
0.205
0.301
16
103
0.118
0.351
84
0.126
0.389
105
0.199
0.284
17
112
0.114
0.336
94
0.121
0.368
118
0.192
0.267
18
124
0.11
0.32
105
0.117
0.348
134
0.185
0.251
19
136
0.106
0.305
118
0.112
0.328
153
0.177
0.235
20
151
0.102
0.29
133
0.107
0.309
175
0.169
0.22
Table 3.8:
L m a tc h
C m a tc h
(nH)
(pF)
L m a tc h
C m a tc h
(nH)
(pF)
20
L m a tc h
C m a tc h
(nH)
(pF)
30
The design values for a 40 antenna extended resonance phased array with various
amplitude tapers (half design parameters are given, the second half of the phased
array is designed symmetrically).
95
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3.4.4. Other Topologies for Matching Networks
The extended resonance phased arrays presented in Figure 3.26 and Figure 3.32
utilized LC-matching networks to transform the input admittances seen at the plane o f the
power divider ports to the first port’s admittance,
G y.
Other topologies, such as quarter
wave transformers or single stub tuners, can also be used to design the matching
networks. These topologies have the advantage o f simple fabrication with the rest o f the
circuitry and having accurate responses. However, simulation results show that the
extended resonance phased arrays with these matching networks result in higher power
division and phase shifting errors, which limits the maximum phased array size to
approximately 10 antennas.
3.4.5. Design with Reduced Number of Varactors
The topology in Figure
3 .3 2
was introduced to design a phased array with single
value varactors throughout the entire design. This was achieved by transforming the
admittances seen at the plane o f the ports to the first port’s admittance,
matching sections as shown in Figure
3 .2 4 .
G y,
using
LC-
This approach requires 2N-2 varactors to
design an N antenna extended resonance phased array. However, if varactors with
different values for a few o f stages are available, the required number o f varactors will
further reduce. For example, an extended resonance phased array structure utilizing two
different varactors
(C , 3 C )
is shown in Figure
3 .3 4 .
At the second node, a varactor o f 3C
is connected and a fixed inductor o f L\/2 is used to achieve phase shifting. Then, the input
admittance is transformed back to the first port’s admittance
(G y )
and phase shifting can
be achieved using Lj. By cascading many stages together, an extended resonance phased
96
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array with reduced number of varactors can be designed. The resulting number of
varactors for the phased array shown in Figure 3.34 is 3 N / 2 - 1 (N:even). Therefore, for
a 20 antenna phased array, 29 varactors, instead o f 38 varactors, are needed. If more
varactor values are available, the required number o f varactors will be further reduced.
This part is repeated to connect N antennas
antenna # 4
antenna # 3
antenna # 2
antenna # 1
M atching Network
3C
3C
Figure 3.34: Extended resonance phased array design with reduced number of varactors.
3.4.6. Bandwidth
So far, the design equations and resulting simulation results for the extended
resonance phased arrays were presented assuming a single frequency o f operation.
However, in real systems, modulated signals spanning a certain bandwidth around the
operating frequency are transmitted and received. Thus, it is important to characterize the
bandwidth o f extended resonance phased arrays. Two definitions for the bandwidth can
be made. The first one is the return loss bandwidth, which determines how much o f the
incident energy at the input is reflected back. While this bandwidth definition is
important to have a rough estimate o f the usable frequency range o f the phased array, it is
97
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not sufficient to determine if the scan angle and gain varies with frequency or not. For a
phased array, bandwidth is usually defined such that at the band edges, the main beam
has moved through half the beamwidth, that is, the gain has dropped by 3 dB [94]. The
simulated return loss bandwidth o f the 20 antenna phased array presented in Figure 3.33
is shown in Figure 3.35, which shows that the return loss is better than -10 dB between 9
and 11 GHz. In addition, the simulated array factors at -12, -6 and 0 degree scan angles
for various operating frequencies are shown in Figure 3.36-Figure 3.38. As the operating
frequency deviates from the design frequency, the beam quality degrades and the side
lobe levels increase. The -12 degree beam is affected most from the operating frequency
change. The 3 dB beamwidth of the -12 degree beam widens from 7.8 degrees to 9.4
degrees with a frequency change from 10 GHz to 10.5 GHz as shown in Figure 3.38.
Also, the magnitude o f the array factor drops from 11.5 dB to 8.5 dB when the frequency
changes from 10 GHz to 9.4 GHz. Therefore, based on the definition o f the bandwidth
given in [94], the bandwidth of extended resonance phased arrays is approximately 10 %.
However, it should be noted that this conclusion is based on the assumption that the
antenna bandwidth is at least 10 %. If a narrow band antenna (such as a microstrip patch
antenna) is used, the overall bandwidth o f the phased array will be determined by the
antenna bandwidth.
98
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-10
-15
CD
-o
- a - -12 degrees
«
O
—i— -6 degrees
: -20
(0
c1—
0 degrees
-25
6 degrees
ZJ»
-I—
0 -30
CL
- e - 12 degrees
-35
-40
9.5
10
11
10.5
Angle, degrees
Figure 3.35: Simulated return loss for various scan angles.
15
* -f= 9 .5 0 GHz
— f=10.0 GHz
* -f= 1 0 .5 GHz
-30
-20
-10
0
10
20
30
Angle, degrees
Figure 3.36: Simulated 0 degree array factors at various frequencies.
99
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15
* -f= 9 .5 0 GHz
— f=10.0 GHz
* -f= 1 0 .5 GHz
-30
-20
-10
0
10
20
30
Angle, degrees
Figure 3.37: Simulated -6 degree array factors at various frequencies.
CD
T3
*-f= 9 .5 0 GHz
— f=10.0 GHz
*-f= 1 0 .5 GHz
B
o
m
LL
£
<
-30
-20
-10
0
10
20
30
Angle, degrees
Figure 3.38: Simulated -12 degree array factors at various frequencies.
100
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3.5. DESIGN OF A TEN GHZ PHASED ARRAY
A 10-GHz 8-antenna extended resonance phased array has been designed, fabricated
and tested to demonstrate the utility o f the technique presented in 3.4. A 15 mil thick
TMM3 substrate (8r=3.27) from Rogers Corporation was used to construct the phased
array. Edge coupled microstrip patch antennas with half wavelength separation in
between were designed, whose layout and dimensions are shown in Figure 3.39. The feed
point of the patch antennas was recessed by 0.262 cm to yield an input impedance o f 65
ST. A photograph o f the fabricated phased array is shown in Figure 3.40. The phased array
was designed based on the 20 dB side lobe level Chebyshev array taper. Using quarter
wave transformers, the antenna impedances were transformed to the required impedances
at the extended resonance power divider ports. Quarter wave transformers were also used
as matching networks to transform the admittances seen at the plane o f the power divider
ports to the admittance presented at the first port (G/). MA46580 series beam lead
varactor diodes from MACOM Inc. were used as tunable capacitors. In this design, open
circuited quarter wave radial stubs were used to achieve floating ground planes for the
varactor diodes. The overall size o f the phased array was 11.4x3 cm (except for the bias
lines and the input feed line). The measured H-plane pattern o f the phased array for
various diode voltages is shown in Figure 3.41. The measurement results show that the
phased array can steer the beam 18 degrees with the application o f 2.25 V to 10.2 V
reverse bias to the varactor diodes (the applied bias voltages are for the varactors on the
left phased array, the required varactor capacitances in the right phased array (hence bias
voltages) was determined using (3.36)). The measured side lobe level was lower than -10
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dB and the average 3 dB beamwidth o f the patterns were 14 degrees. It can be seen from
Figure 3.41 that the gain of the phased array decreases by 2.8 dB as the diode voltage is
reduced to 2.25 V. This is due to the low quality factor o f the varactor diodes at this
voltage resulting in non-symmetrical power division at the input extended resonance
network. A fully symmetric structure at the input should result in a symmetric radiation
pattern.
W= 1.021 cm
W=0.58 mm
Figure 3.39: 10 GHz microstrip patch antenna layout and dimensions.
102
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Figure 3.40: A photograph of the 10 GHz 8 antenna extended resonance phased array.
CD
"O
-a —
Vd=2.25 V
h—
Vd—3.85 V
CD
*3
CO
a.
— Vd=5.35 V
CD
C
TO
Vd=10.2 V
CL
I
X
-60
-40
-20
0
20
40
60
Angle, degrees
Figure 3.41: Measured H-plane pattern of the 10 GHz 8-antenna phased array.
103
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3.6. CONCLUSIONS
In this chapter, a new beam-steering technique based on the extended resonance
power dividing method has been presented. Phased arrays based on this technique do not
need separate power splitter and phase shifters compared to conventional systems.
Instead, the power division and phase shifting circuits are merged into a single circuit,
which utilizes tunable capacitors. This results in a substantial reduction in the phased
array cost and circuit complexity. Extended resonance phased arrays can be employed in
automotive collision avoidance systems, cruise control systems, mobile multimedia
services, etc. A comprehensive theory has been presented, which addresses the design
procedure, maximum scan angle, maximum practical array size, bandwidth, effect of
varactor losses on the phased array performance, and ways to reduce the required number
o f varactors. As a proof of principle, a 2-GHz 4-antenna and a 10-GHz 8-antenna
extended resonance phased arrays using varactor diodes and microstrip patch antennas
have been designed, fabricated and tested. The measured scan range for the 2 GHz
phased array was 20 degrees with the application o f 3 V to 30 V reverse bias to the
varactors. The measured efficiency o f the extended resonance phased array feed was
typically 80 % (1 dB insertion loss). The side lobe level o f the measured patterns was
lower than -9 dB and the average 3 dB beamwidth was 25 degrees. The measured scan
range for the 10 GHz phased array was 18 degrees with the application o f 2.25 to 10.2 V
reverse bias to the varactors. The side lobe level was lower than -10 dB and the average 3
dB beamwidth o f the measured patterns were 14 degrees.
104
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CHAPTER 4
POWER AMPLIFIER LINEARIZATION USING A VARACTOR
4.1. INTRODUCTION
Many wireless communication systems, such as cellular phones, wireless modems,
wireless personal digital assistants (PDA), require RF power amplifiers to boost the
signals before transmission through the antenna. The power amplifier (PA) is the highest
power consuming part o f the transceiver. The output power and efficiency o f the PA
determines the battery life and size. Therefore, a highly efficient PA is the key to design
small, lightweight mobile units. In addition, if the PA is not very efficient, considerable
amount o f power is spent within the PA that requires a big heat sink or a cooling fan,
which increases the cost and size. In order to obtain high efficiency from a power
amplifier, the PA must be driven close to its saturation. However, this results in gain and
phase deviations as a function o f the input power level as shown in Figure 4.1 due to the
nonlinearities in the PA. When a modulated signal is fed into a microwave PA, the
nonlinearities result in signal distortion, which manifest itself in the form o f spectral re­
growth (unwanted power leakage to nearby channels). Adjacent channel power ratio
(ACPR) is a common figure o f merit to quantify this distortion. On the other hand, the
emphasis on higher date rates has put stringent linearity requirements on the power
amplifiers [117]-[118]. If the power amplifier cannot meet these requirements, the PA
must either be operated at a power back-off, which results in reduced efficiency, hence
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shorter battery life, or it must be linearized using additional circuitry. Linearizers are
incorporated into power amplifiers and transmitters for the purposes o f simultaneously
improving the linearity and allowing the operation with less power back-off, resulting in
higher efficiency and output power [117]-[120]. In this chapter, an overview o f power
amplifier linearization techniques is given and a new predistortion linearizer, which
utilizes a varactor based tunable R-L-C resonator, is introduced. Linearizers based on this
technique offer low-cost and simple circuitry.
co
■o
o-
.£
6-
V
.
ra
'
Input Power, dBm
(a)
co
CD
C
LD
_
™ 85O)
-
CD
;
Q_ 8 0 <d
:
«
“ 75Q.
;
70-
Input Power, dBm
F igure 4.1:
(b)
(a) G ain and (b) p h ase v s. input p o w e r relation ship for a ty p ica l p o w e r am plifier.
106
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4.2. AN OVERVIEW OF POW ER AM PLIFIER LINEARIZATION
TECHNIQUES
Linearization is a systematic procedure for reducing an amplifier’s distortion. There
are many different ways of linearizing an amplifier. Linearization allows a power
amplifier to produce more output power (hence higher efficiency) for a given distortion
level, or it allows the PA to operate with less distortion at a given output power level
[117]. Feedforward, feedback and predistortion are the most common forms of
linearization. A brief overview of these techniques will be presented next.
4.2.1. Feedforward Linearization
A feedforward power amplifier consists o f two amplifiers (the main and error
amplifiers), directional couplers, delay lines, tunable attenuators, phase shifters, and loop
control networks as shown in Figure 4.2. The operation of the feedforward amplifier can
be explained as follows. The input signal is first split into two paths using directional
couplers, with one going to the main high power amplifier while the other signal path
goes to a tunable attenuator and a delay line, which are controlled by the first control
network. The output signal from the PA contains both the desired signal and the
distortion components. In the first loop, the first control network adjusts the attenuation
and phase shift so that the desired signal component is cancelled at the output o f the first
power combiner. The combined power, which contains only the distortion component, is
then amplified using a low-power high-linearity error amplifier. In the second loop, the
attenuator and phase shifter is adjusted so that when the error signal and the amplified
signal from the PA are combined, a distortion free signal is obtained at the output.
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Successful isolation o f the error signal and the removal o f distortion components depend
on precise signal cancellation over a band o f frequencies. In practical systems, distortion
cancellation o f 20-40 dB can be achieved [117], [121]. The feedforward linearization
technique
offers
ultra-linear broadband power amplifier performance,
however
feedforward amplifiers are rather costly and inefficient due to the need for many extra
components. The overall average efficiency o f a feedforward amplifier is limited to 10-15
% [117], [121].
M ain PA
Delav Line
Pow er Combiner
Input
Output
LOOP
Phase Shifter
LOOP 2
Error A m plifier
Control
N etw ork 2
Control
N etw ork 1
Figure 4.2: Feedforward linearization concept.
4.2.2. Feedback Linearization
Feedback techniques can also be used for the linearization o f power amplifiers. They
can be divided into several branches such as indirect feedback or cartesian feedback. For
example, a PA linearizer based on the indirect feedback technique is shown in Figure 4.3.
In this approach, a power amplifier’s input and output signals are detected, lowpass
filtered, and the resulting baseband signals are compared. The error signal is then used to
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control the gain and phase of the PA by means o f a tunable attenuator and a phase shifter.
The error signal can also be used to change the bias point o f the amplifier. In cartesian
feedback, the input and output signals are separated into in-phase (I) and quadrature (Q)
components as shown in Figure 4.4. This eliminates the need for phase shifting elements,
but still allows the gain and phase correction by adjusting the amplitudes o f the I and Q
components. Cartesian feedback is most often used with quadrature phase-shift keyed
(QPSK) modulation. In this case, the output demodulated I and Q components are
directly subtracted from the respective input I and Q modulating signals. Therefore, this
eliminates the need to demodulate in the input side. Very high linearity can be achieved
using the feedback techniques. They are also self correcting for changes due to
environmental and aging effects. However, feedback’s main limitation is the stability
issues and inability to handle wideband signals due to the low speed o f the feedback
networks [117], [121].
Phase Shifter
Power Amplifier
Attenuator
Input
Output
Phase
Detector
Figure 4.3: Indirect feedback linearization concept.
109
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I-Q Modulator
Output
Power
Amplifier
LO
out
out
Attenuator
I-Q De-modulator
Figure 4.4: Cartesian feedback linearization concept.
4.2.3. Predistortion Linearization
Predistortion is the most commonly used technique for the linearization of power
amplifiers due to their relatively simple circuitry, small size, and ability to be added as a
stand-alone unit to existing power amplifiers. Predistortion (PD) linearizers generate a
nonlinear transfer characteristics that can be thought o f as the inverse o f the power
amplifier’s transfer characteristics in both magnitude and phase as shown in Figure 4.5 so
that when combined with the PA, a linear power amplifier response is achieved. Unlike
feedback techniques, predistortion is an open-loop technique, hence it achieves wider
bandwidths and does not suffer from stability issues. PD linearizers tend to be less
expensive than other linearizers, making them an attractive candidate for cellular/mobile
applications [117], [121],
110
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PREDISTORTION
HPA
OUTPUT
LINEARIZER
Figure 4.5: Predistortion linearization concept.
In a predistortion linearizer, the distortion products will cancel if the distortion
components produced by the PD linearizer are made equal in magnitude and 180 degrees
out of phase. This condition occurs when the gain and phase o f the linearized power
amplifier remain constant with change in power level. In decibels (dB), the gain of the
linearizer
(G £ )
must increase by the same amount the power amplifier’s gain
( G a)
decreases as given below:
Gt ( n „ - I ) - G 1_ss = - ( G A P ^ ) - 0 ^ ss) \ P , ^ = P „ . ,
where
G ls s
and
G
a -ss
(4.1)
are the small gains of the linearizer and the PA, respectively and
GL(Pout-i) and GA(Pin-A) are these gains as a function o f the linearizer output and amplifier
input power levels, respectively. A similar relationship for the phase can also be achieved
as follows:
L (P fm t-L
) — ^
L~SS
=
A i^ in -A
) _
^ /1 -X S 1)
I^ o u t- L
= ^ 'in - A
111
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(4 -2 )
Equations 4.1 and 4.2 can be rewritten, and the linearizer’s transfer characteristics can
be obtained as follows:
Gl (P»-l ) = <?*_* +
- G , (P„.L + Gl (P„_l ))
(4.3)
- * A ^ l + G 1(/> .-J)
(4.4)
Equation 4.3 and 4.4 can be solved iteratively for the ideal linearizer response to
linearize a given PA. When the power amplifier approaches saturation, the rate of gain
and phase change of the linearizer becomes infinite, which however cannot be achieved
in practice and limits the PD linearizers’ useful operating region. Another limitation with
PD linearizers is their limited distortion cancellation compared to the feedback and
feedforward linearizers [117], [121].
In summary, all linearization techniques have some advantages and disadvantages.
Feedback techniques can improve the linearity significantly, however they suffer from
stability issues and inability to handle wideband signals. Feedforward is a very powerful
technique, offers significant linearity improvement, and does not suffer from stability or
bandwidth issues. This, however, comes at a high cost. On the other hand, predistortion is
a relatively simple and inexpensive technique with no stability concerns. PD linearizers
also potentially handle wide band signals, however they typically cannot achieve the
same level of correction the feedforward and feedback can.
112
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4.3. DESIGN OF A VARACTOR BASED PREDISTORTION
LINEARIZER
In this section, the design procedure and simulation results for a new predistortion
linearization technique using a varactor based tunable R-L-C resonator are presented. The
linearizers based on this technique offer low-cost and simple circuitry. The design o f the
new predistortion linearizer depends very much on the effect o f large RF signal
amplitudes on the capacitance o f varactors. Therefore, this effect is presented first, and
the new linearization concept is discussed thereafter.
4.3.1. Effect of Large RF Signal on Varactor Capacitance
It was mentioned in detail in 2.3.1 that an increasing RF signal amplitude across a
BST varactor decreases its capacitance near 0 V DC bias as shown in Figure 2.9, Figure
2.15, and Figure 2.16. Therefore, instead o f controlling the DC voltage across the BST
varactor, the RF signal amplitude can be controlled to tune its capacitance. The RF signal
amplitude can also be controlled to tune the capacitance o f varactor diodes. However,
unlike BST varactors, an increasing RF signal amplitude across a varactor diode
increases its capacitance, which will be explained next.
Varactor diodes must be reverse biased at all times to provide the useful tunable
capacitor behavior. As discussed in chapter 1, the C-V relationship for a typical varactor
diode is given by:
c{v,) =- i k
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(4.5)
where Vb is the applied bias voltage (negative for reverse bias), Vo is the barrier potential
across the junction and Cjo is the junction capacitance at V b=0. The C-V curve for a
varactor diode with Cjo=132 pF and Vo=0.84 V is shown in Figure 4.6. It is apparent from
Figure 4.6 that the C-V curve becomes more nonlinear as the reverse bias voltage
approaches 0 V. Therefore, if a large RF signal is applied to the varactor diode around a
certain DC bias point, the capacitance will be modulated and the current flowing through
the varactor diode will contain higher order harmonics similar to BST varactors. It should
be mentioned that when a sinusoidal voltage is applied across a BST varactor, its
capacitance varies instantaneously between its maximum value (0 V DC bias value) and
the value determined by the signal amplitude. Since the current is the derivative of the
charge with respect to time as given in (4.6), the maximum value o f the current is
determined when the signal has the highest derivative, which occurs when V(t)=0.
Therefore, the maximum current through a BST varactor depends on the 0 V DC bias
capacitance (maximum capacitance), the amplitude and frequency o f the RF signal as
given below:
/ =
dt
=d
dt
V{t) + C { V ( t ) ) ^ & , V{t) = Asm {(ot)
dt
(4.6)
7ma, = C mm-A-Q)
(4.7)
On the other hand, in varactor diodes, the instantaneous capacitance both increase and
decrease around the DC bias point as shown in Figure 4.7. The varactor capacitance
increases sharply as the sinusoidal voltage across the varactor goes into the negative
cycle. Therefore, there exists a portion o f time that the magnitude o f the current is higher
114
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
than the current determined using (4.7) as shown in Figure 4.8. This also results in a
higher current component at the fundamental frequency, hence increased capacitance.
The capacitance as a function o f RF signal amplitude for the varactor in Figure 4.6 is
shown in Figure 4.9. It turns out that with the application o f an RF signal with a 5 V (3.5
Vrms) amplitude, the capacitance of the varactor diode can be tuned from 50 pF to 55 pF,
resulting in 1.1:1 tunability. It should be noted that the increase in the capacitance
depends on the nonlinearity o f the C-V curve. If the varactor diode is biased at a more
nonlinear operating point to result in a higher current, the increase in the capacitance will
be higher.
In this section, the effect o f large RF signal amplitudes on the capacitance o f solidstate and BST varactors was discussed. An increasing RF signal amplitude decreases the
capacitance of BST varactors and increases the capacitance of varactor diodes. It should
also be mentioned that an increasing capacitance with increasing RF signal amplitude can
be achieved using a BST varactor by simply operating it at an offset DC bias similar to
varactor diodes.
115
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140
120
% 100
<D
g
80
'a 6o
&
u
40
0
1
2
3
4
5
6
7
8
9
10
Reverse Bias Voltage, V
Figure 4.6: Small signal C-V curve for a typical varactor diode (Cjo=l 32 pF, V q=0.84 V).
140
120
100
Time, nsec
Figure 4.7: Instantaneous capacitance for the varactor in Figure 4.6 for an applied reverse bias
RF voltage of V(t)=VDC+A*sin(cot) (VDC=5 V, A=5 V, f=50 MHz).
116
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
x: varactor diode o: BST varactor
<
E
c
CD
U.
&_
D
o
-100
rm
10
15
20
rm
25
rm
30
i i m
35
40
Time, nsec
F igure 4.8:
Current through the varactor in F igure 4 .6 and through a B S T cap acitor for various
RF sig n a l am plitu des (V rf= 2 , 3 , 4 , 5 V ) (f= 5 0 M H z, V DC= 5 V , C BSt (0 V )= 5 0 pF).
58
57
(Jh
56
55
od) 54
c
53
52
& 51
o
50
49
48
0
2
1
3
4
RF Voltage Amplitude, Vr,
F igu re 4.9:
C apacitance as a fu n ctio n o f the RF v o lta g e am plitu de for the varactor d io d e sh o w n
in F igu re 4 .6 (V d c= 5 V ).
117
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
4.3.2. Operation of the Varactor Based Predistortion Linearizer
In this section, a predistortion linearization technique based on the tunability of
varactors using large RF signal amplitudes as discussed in the previous section is
presented. The schematic illustration o f the new predistortion (PD) linearizer circuit is
shown in Figure 4.10. It consists o f a varactor based tunable R-L-C resonator in shunt
configuration. The insertion loss (S 21) o f this circuit is:
(l - a ) 2LC)+ j • (RcoC)
(4.8)
where Zo is the reference impedance o f the system. Therefore, the magnitude and phase
o f the insertion loss are:
(4.9)
Z S 2i = tan 1
(ORC
\ _
1 - q) 2R C )
, r (2 R + Z 0)a)C'
an y i - ( \ - ( 0 2RC );
In
Figure 4.10: Schematic illustration of the varactor based predistortion linearizer.
118
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(4.10)
This circuit has a resonant frequency at:
f =l^fLC
(4'U )
At the resonant frequency, the magnitude o f S21 will be minimum given by (4.9), and the
phase o f S21 will be zero degrees given by (4.10). If a signal at the resonant frequency is
injected at the input, it will be attenuated most. However, if the magnitude o f the input
signal is increased beyond a certain value (determined by the varactor C-V curve and the
voltage across the varactor), the varactor capacitance will start changing as explained in
the previous section. Therefore, the circuit will operate at a new resonant frequency.
Hence, at the frequency of the input signal, the magnitude o f S21 will increase and the
phase o f S21 will increase or decrease depending on the direction o f change in the
varactor capacitance. In order to summarize its operation, consider a varactor diode based
R-L-C resonator with R=34 Q, L=18 nH, Zo=50 Q. The varactor diode has Cj0= l pF, and
Vo=0.84 V and is biased at -3.6 V (reverse biased). The magnitude and phase o f S21 for
this R-L-C resonator at two different input RF power levels are shown in Figure 4.11 and
Figure 4.12, respectively. The resonant frequency shifts from 1.8 GHz to 1.64 GHz,
which results in a 1.33 dB increase in the magnitude o f S21 and 13.6 degrees increase in
the phase o f S21 at 1.8 GHz. It should be noted that if a BST varactor is used in the
resonator, the magnitude o f S21 will still increase, however its phase will decrease due to
the capacitance decrease. In order to observe the variation in S21 more clearly, the
magnitude and phase of S21 at 1.8 GHz is plotted as a function o f the input RF power
level as shown in Figure 4.13 and Figure 4.14, respectively. The magnitude o f S21 can be
119
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
increased from -4.7 dB to -2.6 dB (2.1 dB o f expansion) and the phase o f S21 can be
increased from 0 degrees to 16 degrees (16 degrees of expansion) as the input RF power
level changes from -5 dBm to 20 dBm. Therefore, this circuit can be utilized to achieve
gain and phase expansion (phase compression if using BST varactor) as a function o f the
input RF power level, and can be used to predistort a power amplifier as shown in Figure
4.15. The input matching network in Figure 4.15 is used to improve the return loss o f the
linearizer by matching the input impedance o f the linearizer (with the power amplifier) to
the source impedance at the resonant frequency.
It should be noted that the predistortion circuit introduces a variable loss to the power
amplifier, not gain, which reduces the overall gain o f the system. However, the actual
benefit obtained from the predistortion linearizer is to achieve a linear power input vs.
power output relationship at increased output RF power levels of the power amplifier so
that the overall efficiency o f the system is improved. This benefit is usually quantified in
terms o f the power added efficiency (PAE) o f the overall system given by:
PAE = P°ul ~ Pin
^ dc
(4.12)
where P;n and Pout are the input and output RF power levels, and P dc is the DC power
consumed by the power amplifier. Power added efficiency quantifies how much o f the
DC power is converted to RF power using the power amplifier. Using a predistortion
linearizer, higher output power is obtained from the power amplifier at a given distortion
level, hence a higher efficiency is expected from the linearized amplifier. It should be
120
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
noted that, given a resonant frequency, there are infinite number o f solutions for L and C
values to design the predistortion circuit. However, depending on the power amplifier’s
characteristics, and bandwidth and tunability considerations, these values must be chosen
carefully. The resistor value, R, must also be chosen to minimize the magnitude of S21- If
the insertion loss of the designed predistortion linearizer is high, a low-power highefficiency buffer amplifier [122] can be used to compensate this loss, which also
improves the isolation between the linearizer and the power amplifier. However, the DC
power consumption for this buffer amplifier should be accounted for in (4.12).
□: Pin=5 dBm
o: Pin=17 dBm
c/3
o
M—
'c
o>
CO
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
Frequency, GHz
Figure 4.11: Magnitude of S2i vs. frequency for a varactor diode based predistortion linearizer at
two different input RF power levels (R=34 Q, L=18 nH, Z0=50 Q, Cj0=l pF,
V0=0.84 V, Vdc=-3.6 V).
121
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
□: Pin=5 dBm
o: Pin=17 dBm
O)
CM
-10
-20
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
Frequency, GHz
Figure 4.12: Phase of S21 vs. frequency for a varactor diode based predistortion linearizer at two
different input RF power levels (R=34 Q, L=18 nH, Zo=50 Q, Cj0=l pF, V0=0.84 V,
Vdc=-3.6 V).
-2.5
CD
-o
-3.0
CM
w
-3.5
-5.0
■5
0
5
10
15
20
Input Power, dBm
Figure 4.13: Magnitude of S21 vs. input RF power level for the varactor diode based predistortion
linearizer shown in Figure 4.11 and Figure 4.12 (f=1.8 GHz).
122
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
20
-5
0
5
10
15
20
Input Power, dBm
Figure 4.14: Phase of S21 vs. input RF power level for the varactor diode based predistortion
linearizer shown in Figure 4.11 and Figure 4.12 (f=1.8 GHz).
Pow er A m plifier
In
Input Matching
Network
Linearizer
F igure 4.15: T he p o w e r am p lifier lin earization co n cep t u sin g the varactor b a sed predistortion
circuit.
123
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4.3.3. Intermodulation Distortion and Adjacent Channel Power Ratio Simulation
Results
The basic operating principle of the new predistortion linearization technique was
discussed in the previous section. In order to demonstrate the utility o f this technique, a
linearizer is designed to linearize a nonlinear power amplifier, and the simulation results
for the improvement in linearity and efficiency o f the linearized power amplifier is
presented. The linearity o f the linearized power amplifier is quantified in terms o f both
the 3rd order intermodulation distortion (IMD) and the adjacent channel power ratio
(ACPR) levels. A detailed discussion o f IMD was given in 2.4.3. ACPR, on the other
hand, is the most commonly used figure-of-merit to characterize the linearity o f the
power amplifiers for modem modulation techniques, and is defined as the ratio o f the
power in the adjacent channels to the power in the main channel for a given modulation
standard [124] such as code-division-multiple-access (CDMA).
The magnitude and phase o f S21 for the nonlinear power amplifier that will be
linearized using the introduced technique is given in Figure 4.16 and Figure 4.17,
respectively. The gain and phase characteristics o f an ideal predistortion linearizer to
linearize the given power amplifier were derived using (4.1) and (4.2), and a varactor
diode based predistortion linearizer was designed with R=34 Q,, L=18 nH, Z0=50 Q,
CJ0=1 pF, V 0=0.84 V, and V Dc=-3.6 V using the introduced technique in the previous
section. A quarter wave transformer with a characteristic impedance o f 32 Q was also
used to match the input impedance o f the linearizer to the source impedance at the
resonant frequency of 1.8 GHz. The gain and phase deviations as a function o f the output
124
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
RF power level for the ideal linearizer found from (4.1) and (4.2), and for the designed
linearizer are shown in Figure 4.18 and Figure 4.19, respectively. The linearizer achieves
2 dB gain and 11 degrees o f phase expansion as the output power level changes from 5
dBm to 22 dBm. The insertion loss of the linearizer at the small signal region (the region
where the gain deviation is constant with output RF power level) was simulated as -3.9
dB. In order to observe the effect o f the linearizer on the power amplifier, the gain and
phase o f the original power amplifier and the linearized power amplifier as a function of
the input RF power level is plotted in Figure 4.20 and Figure 4.21, respectively. The
linearized amplifier has a more linear gain and phase vs. input power relationship
compared to the original power amplifier. Due to the 3.9 dB loss o f the linearizer, the
gain o f the linearized power amplifier decreases from 9.2 dB to 5.3 dB. Overall, the
output 1 dB compression point (defined as the output power level where the gain drops
by 1 dB) o f the original amplifier is improved from 20.4 dBm to 23 dBm (2.6 dB
improvement), resulting in a power added
efficiency (PAE) improvement o f 36 %
(defined as the percentage improvement from the PAE o f the original power amplifier to
the linearized power amplifier). In order to observe the effect o f the linearizer on the
linearity more clearly, 3rd order intermodulation distortion (IMD) and adjacent channel
power ratio (ACPR) simulation results for the original power amplifier and the linearized
power amplifier are presented next.
125
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CD
~o
9 -'
CN
CO
4—
O
0
■O
rs
+~*
'c
D)
CO
■5
0
10
5
15
20
Input Power, dBm
F igure 4 .1 6 : M agn itu d e o f S 2[ vs. input R F p o w er le v e l for the n on lin ear p o w e r am p lifier that
w ill b e lin earized (£=1.8 G H z).
50
0
<U
2
O)
0
40
T3
CM
CO
30
0
0
0
20
10
■5
0
10
5
15
20
Input Power, dBm
F igure 4.17: P hase o f S 2i vs. input RF p o w e r le v e l for the n onlinear p o w e r am p lifier that w ill be
lin earized (f= 1.8 G H z).
126
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
x: Ideal linearizer o: Designed linearizer
10
00
■o
c
o
*-4—*
g
>
0
Q
8
6
4
03
0
2
0
(pOpOpapOMp^ ^
Output Power, dBm
F igure 4.18: G ain d eviation vs. output R F p o w e r le v e l for the id eal and d esig n ed predistortion
lin earizer to lin earize the p o w er am p lifier g iv e n in F igu re 4 .1 6 and F igu re 4 .1 7
(f= 1 .8 G H z).
x: Ideal linearizer o: Designed linearizer
C/3
40
0
0i—
O)
0
■o
C
O
g
>
0
Q
K90 0 0 C
0
C/3
0
sz
0_
Output Power, dBm
F igure 4.19: P hase d ev ia tio n v s. output R F p o w er le v e l for the id eal and d esig n ed predistortion
lin earizer to lin earize the p o w e r am plifier g iv e n in F igu re 4 .1 6 and F igu re 4 .1 7
(f= 1.8 G H z).
127
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o: Original power amplifier
x: Linearized power amplifier
jieoocxxcoooooi
8
-
CO
T3
2&0<X>00<X>C>00<>C><K><>00<>0
C
'CD
O
■5
0
5
10
15
20
25
Input Power, dBm
Figure 4.20: Gain vs. input RF power level for the original power amplifier and the linearized
power amplifier (f=1.8 GHz).
o: Original power amplifier
x: Linearized power amplifier
i030000000000000<Xj
CO
0
£
-4—'
eg
>
0
Q
0
co
ro
.c
-30
-40-
Input Power, dBm
Figure 4.21: Phase deviation vs. input RF power level for the original power amplifier and the
linearized power amplifier (f=1.8 GHz).
128
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Third order intermodulation distortion characterization was performed to observe the
effect of the linearizer on the distortion components. The carrier to 3rd order IMD product
ratio (ratio o f the power at the fundamental frequencies to the power at the 3rd order
products) is shown in Figure 4.22. The linearizer improves the carrier to 3rd order
intermodulation product ratio by 5 to 10 dB between the output power levels o f 5 dBm
and 16 dBm. Therefore, there is a range o f output power levels that this linearizer can be
used to effectively improve the 3rd order distortion components. In addition to the
intermodulation distortion simulations, the adjacent channel power ratio (ACPR)
simulations for both the original power amplifier and the linearized power amplifier were
performed. A narrowband CDMA standard (IS-95 reverse link) was used to simulate the
ACPR of the original power amplifier and the linearized power amplifier. The lower and
upper channel ACPR’s for the original and linearized power amplifier as a function of the
mean output power level from the amplifiers are shown in Figure 4.23 and Figure 4.24,
respectively. Using the linearizer, the lower and upper channel ACPR’s o f the power
amplifier are improved by 5 to 11 dB between the mean output power levels o f 5 dBm
and 17 dBm. Therefore, the new predistortion linearizer successfully reduces the
distortion for a constant mean output power level from the power amplifier. In addition,
the linearizer also allows the power amplifier to operate at a higher mean output power
level for a given ACPR level, resulting in improved power added efficiency. The
improvement in PAE and the mean output power as a function o f the ACPR level is
shown in Figure 4.25. The mean output power is improved between 1 dB and 4.7 dB, and
the power added efficiency is improved between 0 % and 126 % in the ACPR range o f 70 to -40 dB. It is clear from Figure 4.25 that there is an optimum range o f ACPR levels
129
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CO
u
o: Original power amplifier x: Linearized power amplifier
o"
'•4—» 60
2
o
"O
A—l
2Q.
Q
o
■2
o
■s
CO
o»
-t—
50
40
30
20
10
92
5
u.
15
10
20
CD
o
Output Power, dBm
Figure 4.22: Carrier to 3rd order intermodulation product ratio for the original power amplifier
and the linearized power amplifier as a function of the output power level (fo=1.8
GHz, Af=2 MHz).
o: Original power amplifier x: Linearized power amplifier
-35
00
-a
CL
O
-45
®
-55
<
c
CO
^
(U
-65
<S
o
_l
-75
5
15
10
20
Mean Output Power, dBm
Figure 4.23: Lower channel ACPR for the original and linearized power amplifiers as a function
of the mean output power level (The modulation standard is IS-95 reverse link
(narrowband CDMA) at 1.8 GHz).
130
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
o: Original power amplifier x: Linearized power amplifier
-35
00
■O
CL
-45
O
<
g
c
-55
CD
SI
O
-65
<D
Q.
Q.
D
-75
20
15
10
5
Mean Output Power, dBm
Figure 4.24: Upper channel ACPR for the original and linearized power amplifiers as a function
of the mean output power level (The modulation standard is IS-95 reverse link
(narrowband CDMA) at 1.8 GHz).
140
4.5
120
100
a<0
a<D
o
s<D
>
2.5 2
O
>
s
hI*
—
I
O
£
§<L>
PAE Improvement
Pout Improvement
%
P -i
h
0.5
-20
-70
-65
-60
-55
-50
-45
-40
Adjacent Channel Power Ratio, dB
Figure 4.25: Improvement in the power added efficiency and the mean output power as a function
of adjacent channel power ratio.
131
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
that this linearizer can be used to effectively improve the mean output power and the
power added efficiency.
4.4. M EASUREM ENT RESULTS
In the previous section, a new predistortion linearization technique using a varactor
based tunable R-L-C resonator was introduced, and simulated results for the efficiency
and linearity improvement of a nonlinear power amplifier linearized using this technique
were presented. In order to show the utility o f this technique, a predistortion linearizer to
linearize a 1.8 GHz power amplifier was designed, fabricated and tested [124]-[125].
Measured results for the original and linearized power amplifiers are presented in this
section.
The original power amplifier uses a Infineon CLY5 GaAs MESFET and achieves a
small signal gain o f 9 dB, and output 1-dB compression point o f 21 dBm. A 60 mil thick
RT/Duroid 6002 substrate from Rogers Corporation and MSV 34 series chip varactor
diodes from Metelics Inc. were used to fabricate the predistortion linearizer. A picture of
the linearizer and the power amplifier are shown in Figure 4.26. The measured gain and
phase deviations for the predistortion linearizer at 1.8 GHz are shown in Figure 4.27 and
Figure 4.28, respectively. The varactor reverse bias voltage was tuned from -2.6 V to -3.4
V to match the gain and phase deviations o f the linearizer to that of the power amplifier.
The insertion loss o f the linearizer varies between 3.2 dB to 3.5 dB as the varactor reverse
bias voltage changes from -2.6 V to -3.4 V. The linearizer achieves up to 1.4 dB gain and
10 degrees of phase expansion as the linearizer output power changes from 0 dBm to 17.5
132
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
dBm. The linearizer was then connected to the power amplifier. The measured gain and
phase of the original and linearized power amplifiers as a function o f the input RF power
level is plotted in Figure 4.29 and Figure 4.30, respectively. The linearized power
amplifier has a flatter gain-phase vs. input power relationship compared to the original
power amplifier. The output 1-dB compression point o f the original power amplifier is
improved from 21 dBm to 22.8 dBm. A standard North American Digital Cellular
(NADC) test signal at a carrier frequency o f 1.8 GHz was used for the adjacent channel
power ratio measurements. ACPR was measured at 12.5 kHz bandwidth at 30 kHz offset
from the carrier frequency. The measured ACPR for various varactor reverse bias
voltages vs. output RF power level is shown in Figure 4.31. There is an optimum range
(15-21 dBm) o f output RF power levels where ACPR is improved, which is attributed to
the extensive flatness in the gain and phase for the linearized power amplifier at these
output power levels. The improvement in ACPR reaches a maximum o f 11 dB at 17.5
dBm output power when the varactor diode is biased at -3 V. In addition, the linearizer
increases the maximum output power from the power amplifier for a given ACPR level,
hence the efficiency is improved. The improvement in PAE for various varactor reverse
bias voltages is also plotted in Figure 4.32 as a function o f the ACPR level. The PAE
improvement reaches a maximum o f 42 % for the ACPR level o f -42 dBc. It was also
determined that the varactor reverse bias voltage o f -3 V results in the optimum
performance for the linearized power amplifier.
133
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 4.26: A photograph of the predistortion linearizer (left) and the power amplifier (right).
1.4
VDC—2.6V
— VDC=-3.0V
-*-V D C =-3.4V
0.8
0.6
0.4
0.2
0
5
10
15
20
Output Power, dBm
Figure 4.27: Measured gain deviation of the predistortion linearizer vs. output power level for
various varactor reverse bias voltages (f=1.8 GHz).
134
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
12
- a- VDC=-2.6V
w
<0 10
<L>
tH
W
<
D)
T3 8
a
o
6
'E
Q 4
<
u
a)
ai
J=1
CU 2
— V D O -3.0V
-x - V D O -3.4V
0
5
15
10
20
Output Power, dBm
Figure 4.28: Measured phase deviation of the predistortion linearizer vs. output power level for
various varactor reverse bias voltages (f=1.8 GHz).
10.00
9.00
Original PA
.00
- -
9 7.00
ta
P D + P A , V n r—-2 .6 V
a 6.oo
5 .0 0 -
4.00 ”
P D + P A , V n r—- 3 .4 V
3.00
0.00
5.00
10.00
Input Power, dBm
15.00
20.00
Figure 4.29: Measured gain vs. input power for the original power amplifier and linearized power
amplifiers at various varactor reverse bias voltages.
135
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
§-10
2 -15 "
Original PA
PD+PA
Vdc=-2.6 V
-25
-30
0
5
15
10
20
Input Power, dBm
Figure 4.30: Measured phase deviation vs. input power for the original power amplifier and
linearized power amplifiers at various varactor reverse bias voltages.
-20
Original PA
PD+PA, VDC—2.6 V
PD+PA, VDC=-3.0 V
PD+PA, V D O -3.4 V
-25
O -30
^ -3 5
Pd
b
-40
* -45
-50
-55
10
12
14
16
18
20
22
24
Output Power, dBm
Figure 4.31: Measured adjacent channel power ratio (upper channel) vs. output power for the
original power amplifier and linearized power amplifiers at various varactor reverse
bias voltages.
136
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
- A - P D +PA , V D C = -2.6 V
P D +PA , V D C = -3.0 V
^ 40
- X - P D +PA , V D C = -3.4 V
f 35
-45
-40
-35
-30
-25
ACPR, dBc
Figure 4.32: Improvement in the power added efficiency (PAE) for various varactor reverse bias
voltages as a function of the adjacent channel power ratio (ACPR).
4.5. CONCLUSIONS
In this chapter, a new predistortion linearizer for the linearization o f RF/microwave
power amplifiers has been introduced. The core o f this predistortion linearizer is a
varactor based tunable R-L-C resonator in shunt configuration. The operation o f this
linearizer is based on the tunability o f varactors with large RF signal amplitudes. This
linearizer can achieve gain expansion and phase expansion (or compression) as the input
power to the linearizer is increased. Due to the small number o f circuit elements required,
linearizers based on this technique offer low-cost and simple circuitry, hence can be
utilized in handheld and cellular applications. As a proof of principle, a 1.8 GHz power
amplifier with 9 dB gain and output 1-dB compression point o f 21 dBm was linearized
137
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using this technique. The linearizer improved the output 1-dB compression point o f the
power amplifier from 21 dBm to 22.8 dBm. Adjacent channel power ratio (ACPR)
measurements were also performed using a standard North American Digital Cellular
(NADC) test signal. ACPR was improved about 11 dB at an output power level o f 17.5
dBm. In addition, the improvement in the power added efficiency was determined for a
given ACPR level. The improvement in power added efficiency reaches a maximum of
42 % for the ACPR level o f -42 dBc.
138
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CHAPTER 5
CONCLUSIONS AND FUTURE WORK
5.1. CONCLUSIONS
This thesis has demonstrated novel RF and microwave components based on
ferroelectric and solid-state based tunable capacitor (varactor) technologies for the design
of low-cost, small-size and multi-functional wireless communication systems. These
include tunable lumped element VHF filters based on ferroelectric varactors, phased
arrays which, unlike conventional systems, do not require separate power dividers and
phase shifters, and a predistortion linearization technique that uses a varactor based
tunable R-L-C resonator.
The demonstrated tunable filters were based on the newly emerging ferroelectric
(Barium Strontium Titanate - BST) varactor technology. The BST varactors in this study
achieved typical durabilities o f 4.2:1 (76 %) with the application o f 5 V to 10 V DC bias
voltage. The measured loss tangent values were in the range of 0.003 and 0.009 at VHF
frequencies. The effect of large RF signal amplitudes on the C-V curve was also
investigated. Large RF signal amplitudes reduce the BST varactor capacitance near 0 V
DC bias, hence results in reduced tunabilities. Tunable lumped element lowpass and
bandpass VHF filters based on BST varactors were demonstrated. The lowpass filter
achieved 40 % tunability with the application o f 0 to 9 V DC bias to the BST varactors.
139
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The bandpass filter showed 57 % tunability with an applied DC bias o f 0 to 6 V. The
passband insertion loss o f the bandpass filter was 3 dB, which compares favorably with
MEMS tunable filters and commercially available tunable filters based on varactor diodes
and switched capacitors.
The demonstrated phased arrays were based on the extended resonance power
dividing technique. Phased arrays based on this technique do not require separate power
divider and phase shifters. Instead, the power division and phase shifting circuits are
combined into a single circuit, which utilizes tunable capacitors. This results in a
substantial reduction in the circuit complexity and cost. Phased arrays based on this
technique can be employed in applications where small-size and low-cost are important
such as automotive collision avoidance radars, mobile multimedia services, automotive
cruise control systems. As a proof o f principle, a 2 GHz 4 antenna and a 10 GHz 8
antenna extended resonance phased arrays were demonstrated with scan ranges o f 20
degrees and 18 degrees, respectively.
In the last part of the thesis, a new predistortion linearizer for the linearization of
RF/microwave power amplifiers was presented. It consists o f a varactor based tunable RL-C resonator in shunt configuration. Due to the small number of circuit elements
required, linearizers based on this technique offer low-cost and simple circuitry, hence
can be utilized in handheld and cellular applications. A 1.8 GHz power amplifier with 9
dB gain and output 1-dB compression point o f 21 dBm was linearized using this
technique. The linearizer improved the output 1-dB compression point o f the power
140
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amplifier from 21 dBm to 22.8 dBm. Adjacent channel power ratio (ACPR) was
improved about 11 dB at an output power level o f 17.5 dBm. The improvement in the
power added efficiency was also determined for a given ACPR level.
The circuits and techniques introduced in this thesis may be utilized towards the
development o f various components for multi-functional wireless communication
systems as mentioned in the first chapter. However, their major commonality is the
utilization o f a tunable capacitor. The next section will outline some ideas for future
research.
5.2. FUTURE W O RK DIRECTIONS
Based on the achievements o f this thesis, the possible future work directions are
outlined as follows:
5.2.1. Tunable RF/Microwave Filters Based on Ferroelectric Varactors
The high dielectric constant of the BST material (er=:~200) resulted in parallel plate
capacitor values in the range o f 10 pF to 100 pF, which therefore limited the upper
frequency range to characterize the BST properties to approximately 500 MHz due to the
small capacitive reactance values at this frequency. Alternative ways o f achieving smaller
capacitor values, such as interdigital BST varactors or BST varactors connected in series,
can be explored, and characterization o f BST properties can be made at microwave and
millimeterwave frequencies. In addition, other measurement techniques such as the two
port measurements discussed in [86] can be utilized to characterize BST properties more
141
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accurately. Design and fabrication of integrated tunable filters at microwave and
millimeterwave frequencies can be made. Other applications that uses BST varactors
such as tunable matching networks, linearizers, frequency multipliers, parametric
amplifiers can also be studied.
5.2.2. Extended Resonance Phased Arrays
Extended resonance phased array technique was demonstrated as a potential solution
for mobile multimedia services and automotive collision avoidance radars. Future work
may include designing an extended resonance phased array for collision avoidance
systems operating at 24 GHz or 77 GHz. Due to the increased frequencies, a fully
integrated extended resonance phased array fabrication can also be explored.
5.2.3. Tunable Resonator Based Predistortion Linearizers
The operation and design procedure for the tunable resonator based predistortion
linearizer was presented quantitatively. However, given the characteristics o f an arbitrary
power amplifier, the possibility o f an analytical closed form solution for a tunable
resonator based predistortion linearizer can be studied. Therefore, the required R, L, C
values, and the capacitance vs. voltage (C-V) curve are easily obtained. In addition, other
topologies such as cascade o f two R-L-C resonators or an R-L-C resonator operating
slightly off-resonance can be explored to increase the flexibility of the design and to
achieve better performance.
142
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APPENDICES
143
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APPENDIX A
BST CAPACITOR MODELER
The Agilent-ADS simulation setup below extracts the equivalent circuit model
parameters from the measured reflection coefficient data of the BST capacitors.
1
v68_0V
-'W V -
E I slci
Cc = E r * 3 8 5 4 2 E ! 2 * ( 1 5 0
Qc = 5 . 6 0 0 6 1 4 e + - 0 0 1
opt)
£ r = b 3 MJ S 3 l e * - 0 CU
opt)
Rb - 5 S 2 9 0 8 2e - 001
opt)
Hi p"
-)h
3 7 * 1 5 0 . 37ft 12 ) / ( 7 0 0 E - i C )
I to 500 I
1 to 200 )
0 . 0 1 1o 1 0 j
ESTr
m d - ( m o g ( S ( t . 1 ) ]. - ma g [ S ( 2 ■2 ) ) ) / m a g < S ( 1 . i ) )
o d ~ ( p hq e o ( S { 1 , i ) ) ■ p h o B n ( 5 { 2 , 2 ) ) ) / { » f t 0 B o ( 5 ( l
NOMIN AL
OPTIMIZATION
Opti tTI'
Op I i mTy p QnsR gr i d om
[ r r o r f <) f f'v—L2
Ma x i l o o " - 1 5 6
P»
Des f f e d E f r a >=0
S t o t o s L e v e l =°
S o t B « S ’t V o I U85"' J' CE
Sou<J-
]
[
Cp*imOoai'
Exp r = ;ln d "
S i mt n a I o n e a Noma —
M
oex'gh
=01=1 0
W
Ron ge Vc r [ 1 ] =
Sa n q c j M' n [ 1 ] —
Ro n q a Wu x[ s
coN am o- " S P 1"
We i h t =
RcngeVar[1 ]=
R c r g o M l n[ 1 ]->•
R <j ny«M a* [ 1 ] —
S a v a S o n s “■y a s
S o v c O p I irnV □ r s = n o
Sci v e O o a I s = n e
Goo i Nome ■ 1 ] " " O p i i m G c a 12"
G a n I Nomo ' 7 ] m " Dp t | r n d a a I 1 "
144
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APPENDIX B
MATLAB CURVE FITTING PROGRAM
The MATLAB program below fits the measured relative permittivity vs. voltage
A
curve o f a BST capacitor to a 14 degree polynomial based nonlinear capacitor.
clear all;
form at long g;
v -[ -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 -0.4 0 0.4 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
6 6.5 7]’;
Er=[82 85 89 94 102 109 116 125 137 151 164 184 188 197 192 188 172 159 143 131
121 113 106 102 95 91 87 84 8 1 ]’;
degree=14;
coeff-polyfit(v,Er, degree);
coeff
datal = ";
fo r i=l:degree+l
data=sprintf('%s%e*Eo,',datal,coeff(degree+2-i));
datal =data;
end
data
x=linspace(-6,6,1400);
plot(x,polyval(coeffx));
grid;
145
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APPENDIX C
LARGE SIGNAL C-V CURVE SIMULATOR
The Agilent-ADS simulation setup below is used to simulate the effect o f large RF
signal amplitudes on the dielectric constant of the BST capacitors.
|
LSSP
|
|
HARMON I C
BALANCE
[
i o = B . R 5 4 2 C -1 2 * 0 . O . ^ s s a f i f l i H 7 3 8 0 4
hB2
MB '
F r e q M j - f r c q i i c n c . y MHz
O r d e < ' 1 |=1
I S S P _ . F r e q A t Pf t r t [ 1 ] = f r c q u e n c y
w e s p Vo' • = " f i o v o I t o q f t "
F r b q [ ‘ “ f r o q ij e n c y MHz
Order f 1]= 1
S w o e p V o r = ■’ r j ov o I t a g o “
Stor1=0
SrorUJ
^
S t op“ 0
S tep =
S top =7
S to p -.1
VAR2
powe r = - 2 0
d cv ol t o ge-Q
frequency-SD
-A A /v
PORT1
9
Nun=l
2 = 5 0 Oh w
o r(d n m tcw (p q *cr) , 0)
F r e a ^ t r e q u e n e y MHz
V d c - d c v oI i o g e
T
Ea-;;r,
EE
EH...
n=z i n { S 1 ! . F o r I Z l )
v t ( V I r. , 0 , D , 5 0 n s c c , 1 0 CO)
o u r . v c - v t ( V c , G , 0 , 5 0 n s c c . 1 000)
146
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APPENDIX D
EXTENDED RESONANCE PHASED ARRAY SIMULATOR
The Agilent-ADS simulation setup below is used to simulate the array factor o f the
extended resonance based phased arrays utilizing fixed inductors to transform the
admittance to its conjugate and fixed LC-matching sections to step up the impedance to
the first antenna impedance.
E;,
E,\
Ei
B,
g&
B,
lz-4S0lu
] |» | 5-PARAM
ETERS"| Q;
where each block represents the following:
P3
N um = 3
TL.1N
O
<I>
P o rt
C2
L=Lind H
C=CJ F
R=
C3
C = C _t F
L=l_m atch nH
R=
P2
N um = 2
147
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BIBLIOGRAPHY
148
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