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Analysis and design of microwave HEMT mixers for low noise, high conversion gain, and low intermodulation

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ANALYSIS AND DESIGN OF MICROWAVE HEMT MIXERS
FOR LOW NOISE, HIGH CONVERSION GAIN, AND LOW INTERMODULATION
A Dissertation Submitted to the
Division o f Graduate Studies and Research
of University of Cincinnati
in partial fulfillment of the
requirements for the degree of
DOCTOR OF PHILOSOPHY
in the Department o f Electrical and Computer Engineering
o f the College o f Engineering
1996
by
Guanghua Huang
BS, Fuzhou University, the People’s Republic of China, 1983
MS, South-East University, the People’s Republic o f China, 1986
Committee Chair:
Dr. Altan M. Ferendeci
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UMI Number: 9734587
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UNIVERSITY OF CINCINNATI
December 3
m
,19
96
Guanghua Huang
hereby submit this as part of the
requirements for the degree of:
Doctor of Philosophy
Electrical and Computer Engineering
I /I ■■
■-
it is entitled .
Analysis and Design of Microwave
HEMT M i x e r s — for Low Noise, High Conversion
Gain,
and Low Intermodulation
Approved by
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Abstract
In this work, the design o f a new drain mixer was carried out with the following novel
features: A double-tuned microstrip band pass filter(DTMBPF), a new model for the I-V
characteristics o f a HEMT/FET,
a modified model for determining the harmonic
coefficients of a FET, a quasi-static large signal (QSLS) equivalent circuit for a mixer, a
model for predicting conversion gain of a mixer by a microwave linear simulation
program, a model for predicting third harmonics o f a FET mixer based on the first order
output, a theory for the stability of a FET mixer, and the theoretical and experimental
investigation of HEMT mixers.
A double-tuned microstrip band pass filter(DTMBPF) without loaded lumped
capacitors based on the low frequency double-tuned resonant circuit is presented. The
design guidelines for determining taping points, coupling distance, and length o f the
resonators are provided.
A modified I-V characteristics for a HEMT/FET is developed. The control-randomsearch is used for the optimization and parameter extraction. The new model offers better
accuracy over the conventional models o f Materka, Curtice, Angelov, etc., especially in
the ohmic region.
An experimental model is developed to determine the harmonic coefficients o f the
Volterra-Series analysis o f gate (base)
I-V characteristics of a transistor at low RF
ii
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frequency band. The gate signal voltage and first-order output voltage were measured
directly by a scope instead o f measuring the input and output power levels by a spectrum
analyzer. Comparison between the measured and modeled was carried out.
FET characterization for the gate mixer and drain mixer is developed. Frequency
conversion of the gate mixer is analyzed. The mixing transconductance o f the gate mixer
is calculated. At some dc gate bias points, zero frequency conversion is observed. The
quasi-static large signal equivalent circuit is developed to predict conversion gain and to
design matching networks.
Frequency conversion o f a novel drain mixer is analyzed using transistors with both
symmetrical and asymmetrical I-V characteristics. The mixing transconductance o f a
drain mixer peaks at zero dc drain bias and with a finite dc gate bias.
An experimental determination of the pumped drain shunt resistance and drain dc
offset is developed. A quasi-static large signal equivalent circuit o f the drain mixer was
extracted.
The stability o f the gate mixer and drain mixer is theoretically analyzed based on the
developed large-signal S-parameters. The pumped S-parameters related to the stability at
the RF frequency components o f both gate and drain mixers were simulated. The stability
o f the drain mixer is found to be better than that o f the gate mixer.
A 12 GHz drain mixer was designed based on the developed QSLS model.
Experimental measurements gave a noise figure o f 3 dB with a conversion gain o f 10 dB
at an LO power o f 10 dBm at a center frequency o f 12 GHz over a 500 MHz bandwidth.
A simple and effective method is developed so that a microwave linear program such
as Touchstone can be used for predicting conversion gain. A simple and effective method
iii
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is developed for prediction o f the third order harmonic product of any FET mixers. The
intermodulation products are calculated based on the known pumped third order
coefficient a3p , mixing transconductance, and first order output power level. Min im u m
third harmonic product with high conversion gain is thus identified theoretically and
experimentally at the dc gate bias around -0.6V when a NE33284A HEMT is used.
A 12 GHz HEMT gate mixer is designed based on the developed QSLS equivalent
circuit. Typical conversion gain o f more than 8 dB with a noise figure of 5.5 to 7 dB are
obtained. The “zero” frequency conversion gain is identified theoretically and
experimentally. Calculated third order harmonic products of the gate mixer are also
compared with the experimentally measured results.
The experimental setups of conversion gain, intermodulation and noise figure
measurements are given in detail.
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Acknowledgment
I would like to thank specially my dear advisor, the committee chair, Dr. Altan M.
Ferendeci, from Department of Electrical and Computer Engineering, who has been given
me such the guidance, suggestion, help, and constant encouragement. His support through
out this work could not be concluded simply in several words.
I would like to thank the following people to be my dissertation committee, Dr. Howard
E. Jackson, from Department of Physics, Dr. Peter B. Kosel, from Department of
Electrical and Computer Engineering, Dr. Kenneth P. Roenker, from Department of
Electrical and Computer Engineering, Dr. Marc M. Cahay, from Department o f Electrical
and Computer Engineering, University o f Cincinnati. I also would like to thank Dr. ShiLin Lu and Mr. Qidong Guo for their useful assistance and discussion.
The support o f this work from OVERHOFF Technology Corporation is appreciated.
I would like to specially thank my dear wife, Ying Wang, and my family, for their
dedication o f patience, understanding, and support of this work.
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Contents
Contents
List of Figures
Principal Symbols
I
4
12
Chapter 1
Introduction
18
Chapter 2
2.1
2.2
Double-Tuned Microstrip Bandpass Filter
Structure
Theory
Coupling Space s Between the Two Parallel
Resonators
Determination of the Tapped Position /,
Design Examples
Multi-Tuned MicrostripBand Pass Filter (MTMBPF)
Conclusions
38
38
40
41
2.2.1
2.2.2
2.3
2.4
2.5
Chapter 3
A New I-V Characteristics Microwave Nonlinear
Model for HEMTs and MESFETs
A New Microwave Nonlinear FET Model
Curve fitting o f I-V characteristics
Conclusions
3.1
3.2
3.3
Chapter 4
4.1
4.2
4.3
4.4
4.5
Chapter 5
5.1
5.2
5.2.1
5.2.2
5.3
46
49
55
57
58
58
68
78
The Volterra-Series Analysis And Measurement Of
FET Gate I-V Characteristics For Intermodulation
Prediction
Introduction
Theoretical prediction of ax, a 2, a3, ...
Description o f the Measurement Technique
Experimental Results
Conclusions
79
81
83
86
93
FET Characterization
Introduction
Small signal equivalent circuit parameters
R „ R g,R d
Ls, L g ,a n d L d
QSLS equivalent circuit for a gate mixer
94
94
95
96
97
99
79
l
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5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.2
5.5
5.6
Chapter 6
6.1
6.2
6.3
6.4
Chapter 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Chapter 8
“Hot” small signal equivalent circuit
Non-linear elements Cgs and C„,
gd
Frequency conversion in a gate mixer
QSLS equivalent circuit for the new drain mixer (DM)
Frequency conversion in the new drain mixer
Symmetrical FET I-V characteristics
FET with asymmetrical I-V characteristics
The pumped gate-to drain capacitance Cgd
Theoretical analysis o f the stability o f the mixers
Conclusions
100
101
103
113
115
115
121
127
129
134
Design of a FET gate mixer
Introduction
Matching networks and conversion gain
Noise-Figure, Conversion Gain, And Intermodulation
Measurements
Conclusions
136
136
137
144
148
Design And Performances OF The Drain Mixer
Introduction
Design O f Drain Mixer For Maximum Conversion Gain
Design o f The Matching Networks And Prediction O f
The Conversion Gain By Touchstone
Predicting Third Order Intermodulation Products Based
On Conversion Gain
Measurement Of Conversion Gain And Noise Figure By
HP 8970A Noise Figure Meter
Measurement Of Intermodulation And Conversion Gain
Using A Spectrum Analyzer
Conclusions
171
174
Conclusions
175
Bibliography
149
149
150
153
161
168
182
Appendix
A2-1
The Touchstone program fo r simulation o f 11.50-12.00
DTMBPF
A3-1
The CRS Program fo r Curve Fitting I/V Characteristics
ofNE33284A HEMT at Vd >0
A4-1
The Programs for Determination o f harmonic
coefficients a u a2, and a3
1. Theoretical prediction o f a x, a2, and a3 using the new I/V
model
192
192
193
196
196
2
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2.
Experimental predictions
A5-I
1.
The Touchstone program fo r extraction o f the parasitic
elements from measured "cold" S-parameters.
2. The Touchstone program fo r extraction o f the parasitic
elements from measured "hot" S-parameters.
A5-2
A5-3
A5-4
A5-5
A 7-1
A 7-2
A 7-3
The calculation o f gate mixer mixing transconductance
using Mathcad
The extraction o f the small signal equivalent circuit fo r
the drain mixer
The measured average large signal drain shunt
resistance
The calculation o f drain mixer mixing transconductance
using Mathcad
The Touchstone program for prediction o f conversion
gain o f D M
The measured specifications o f the drain mixer #1
The measured specifications o f the drain mixer #2
196
199
199
199
201
201
203
204
206
208
211
222
3
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List of the Figures
Figure No.
Descriptions
Pages
Figure 1.1
The small signal model of the gate mixer.
20
Figure 1.2
The equivalent circuit o f the Maas’ gate mixer.
22
Figure 1.3
The dc bias point of a typical FET gate mixer.
23
Figure 1.4
The dc bias point of a typical FET resistive mixer.
23
Figure 1.5
The Begemann’s theoretical conversion gain o f a drain mixer.
24
Figure 1.6
The bias point o f a DM.
25
Figure 1.7
The equivalent circuit o f a FET at low radio frequency band.
34
Figure 1.8
A conventional taped combline filter.
35
Figure 1.9
A coplanar microstrip combline filter.
36
Figure 2.1a
The physical structure of a double-tuned microstrip band pass filter.
39
Figure 2.1b
The equivalent circuit o f double-tuned microstrip band pass filter.
39
Figure 2.2
A “coupled microstriplines” configuration and break-up ...
44
Figure 2.3
The effective coupling length o f the resonators.
45
Figure 2.4
The frequency response of a typical double-tuned resonant circuit.
45
Figure 2.5
The flow diagram o f design a double-tuned microstrip band pass
filter.
48
Figure 2.6
The Touchstone simulation model o f DTMBPF.
49
Figure 2.7
The experimental and the simulation results o f the 11.50-12.30 GHz
double-tuned microstrip band pass filter.
52
4
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Figure 2.8
The comparison o f the simulation results to the experimental result
of the 10.73 GHz double-tuned microstrip band pass filter.
Figure 2.9
The comparison o f the simulation result to the experimental result
of the 11.70-12.20 GHz double-tuned microstrip band pass filter
Figure 2.10
54
The structure and the simulation model of the multi-tuned microstrip
band pass filter.
Figure 2.14
54
The simulation frequency responses of the double-tuned microstrip
band pass filter varies with the tapped positions Sa.
Figure 2.12
53
The simulation frequency response of the double-tuned microstrip
band pass filter varies with the coupling gap s.
Figure 2.11
53
56
The simulation result o f the 1.85-1.87 GHz multi-tuned microstrip
band pass filter.
57
Figure 3.1
Large signal equivalent circuit of a FET.
60
Figure 3.2
The typical “bell” shaped structure of transconductance o f a HEMT.
63
Figure3.3
Measured I-V characteristics o f NE33284AHEMT for both Vd<0
and Vd >0.
67
Figure 3.4
A FET works in
>0 and
<0
Figure 3.5
The energy band diagram o f an n-AlGaAs/GaAs heterostructure
67
system.
68
Figure 3.6
The flow diagram o f CRS.
70
Figure 3.7
The curve fitting result o f the new model.
72
Figure 3.8
The comparison o f new model to the Angelov’s model.
74
5
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vs. V at different V^.
Figure 3.9
Comparison o f the measured and modeled
Figure 3.10
The comparison o f the Meterka’s model and the new model in the
ohmic region.
Figure 3.11
76
The comparison o f measured and modeled I-V characteristics o f
NE33284A.
Figure 3.12
75
77
The comparison o f measured and modeled I-V characteristics o f
NE71084.
78
Figure 4.1
The equivalent circuit o f a FET valid at VHF frequencies.
80
Figure 4.2
The setup used to perform low-frequency measurements o f RF
harmonics.
87
Figure 4-3
VIPP, Pla, P2a, Pia vs- the gate biases at F^0=0.5 V.
88
Figure 4.4
Vlpp, Pla, P2a, P2a vs. the gate biases at ^ = 0 . 8 V.
88
Figure 4.5
Vlpp, Pla, P2a, P2a vs. the gate biases at VM =\ V.
89
Figure 4.6
VIpp, Pla, P2a, P2a vs. the gate biases at Vlb0=2 V.
89
Figure 4.7
The VAM modeled and from I-V modeled results of a, vs. dc gate
biases.
Figure 4.8
The VAM modeled and from I-V modeled results of a2 vs. dc gate
biases.
Figure 4.9
91
The VAM modeled and from I-V modeled results of a2 vs. dc gate
biases.
Figure 4.10
90
91
The VAM modeled and from I-V modeled results of ax vs. dc gate
6
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biases.
Figure 4.11
92
The VAM modeled and from I-V modeled results of a2 vs. dc gate
biases.
Figure 4.12
92
The VAM modeled and from I-V modeled results of a3 vs. dc gate
biases.
93
Figure 5.1
The small signal equivalent circuit of a FET.
96
Figure 5.2
The “cold” equivalent circuit of a FET.
98
Figure 5.3
The measured and modeled “cold” S-parameters of NE33284A.
99
Figure 5.4
The pumped gate total voltage(PGTV) at the LO signal amplitudes
o f 0.5V and 2.0V
102
Figure 5.5
The calculation results o f the average o f Cp and C ^.
103
Figure 5.6
An ideal mixer
104
Figure 5.7
A simplified FET I-V characteristics
104
Figure 5.8
The drain current waveform o f the gate mixer at the local oscillation
signal amplitude of 0.5 V.
108
Figure 5.9
The mixing transconductance of NE33284A HEMT.
109
Figure 5.10
The waveform of the pumped transconductance gm(t).
110
Figure 5.11
The final quasi static large-signal equivalent circuit o f the gate mixer
for matching network design and prediction of conversion gain.
Figure 5.12
The calculated g Qversus the amplitudes of the LO signal at the
biases of P^ 0=-0.8 V and F*„=2.0 V.
Figure 5.13
112
The measured input reflection coefficient
112
of a typical drain mixer
7
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( NE33284A HEM T).
114
Figure 5.14
The g t varies with VffQ and ViQ.
118
Figure 5.15
Comparison of g, vs. V&Q for both the Materka’s and new models.
119
Figure 5.16
The mixing transconductance g, varies with the dc gate bias V 0 and
the local oscillation signal amplitude V0.
Figure 5.17
The mixing transconductance g, vs. the dc drain bias
120
and local
oscillation signal amplitude VQ.
120
Figure 5.18
The typical pumped drain voltage and currentconfigurations.
Figure 5.19
The set up for measuring
Figure 5.20
The mixing transconductance of NE33284A.
125
Figure 5.21
The average transconductance o f NE33284A.
126
Figure 5.22
The calculated results o f Cgd versus the gate dc bias.
127
Figure 5.23
The comparison o f the mixing transconductance versus the gate dc
and Rd (t ).
bias of the gate mixer and the drain mixer.
Figure 5.24
130
131
The modeled quasi static large-signal S-parameters of the drain
mixer.
Figure 5.27
128
The stability circles o f the gate mixer in the source and load
reflection coefficient planes, simulated by the Touchstone software.
Figure 5.26
124
The modeled quasi static large-signal S-parameters o f the gate
mixer.
Figure 5.25
122
132
The stability circles in the source and load reflection coefficient
planes o f the drain mixer.
133
8
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Figure 6.1
The schematic o f the gate mixer.
138
Figure 6.2
The measured and calculated conversion gain frequency response of
the gate mixer.
Figure 6.3
139
The calculated and measured conversion gain of the gate mixer
versus gate dc biases at RF frequency o f 12 GHz.
140
Figure 6.4
The typical noise figure performance o f the gate mixer.
141
Figure 6.5
The typical intermodulation performance o f the gate mixer.
142
Figure 6.6
Measured and the calculated IM3 output based on experimentally
measured a 3 at the dc bias o f
=-0.8 V and FdiO=2.0V.
143
Figure 6.7
The measured IM3 output versus the LO power levels.
144
Figure 6.8
The calculated a3p versus local oscillation signal amplitude.
144
Figure 6.9
The setup o f measurement o f noise figure of the gate mixer.
145
Figure 6.10
The input network of the gate mixer.
146
Figure 6.11
The measured insertion loss o f the input network for measuring the
gate mixer.
147
Figure 6.12
The setup for measuring the intermodulation of the gate mixer.
148
Figure 7.1
The schematic of the drain mixer.
151
Figure 7.2
The quasi-static large signal equivalent circuit of the drain mixer.
152
Figure 7.3
The Touchstone simulation model for designing the input and drain
networks o f the drain mixer.
153
Figure 7.4
The mechanical drawing o f the test fixture for 12 GHz drain mixer.
155
Figure 7.5
The circuit board layout o f 12 GHz drain mixer.
156
9
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Figure 7.6
The measured and predicted input reflection coefficients o f drain
mixer.
156
Figure 7.7
The measured and simulated Sx, at local oscillation port.
157
Figure 7.8
The measured and simulated S n at intermediate frequency output
port.
158
Figure 7.9
The measured and simulated conversion gain o f the drain mixer.
158
Figure 7.10
The measured and calculated conversion gain,
versus local
oscillation signal power levels.
160
Figure 7.11
The measured and calculated conversion gain versus drain dc bias.
161
Figure 7.12
The modified drain mixer circuit for prediction IM3 products.
162
Figure 7.13
The measured and calculated pumped aJp o f the drain mixer.
164
Figure 7.14
The measured and calculated third order intermodulation o f the drain
mixer.
Figure 7.15
The measured and calculated third harmonics outputs versus the dc
gate bias.
Figure 7.16
166
166
The third order intermodulation output power level P2rd as a function
of the local oscillation signal power level at the dc gate bias of
P^q—0.6 V and the dc drain bias of ^ o=0V for the second drain
mixer.
Figure 7.17
Figure 7.18
167
The spectrum distribution o f the image, RF, and local oscillation
signals.
168
The setup of the measurement of noise figure and conversion gain.
170
10
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Figure 7.19
The insertion loss o f the input image rejection network.
Figure 7.20
The setup o f intermodulation products and conversion
171
gain
measurements.
172
Figure 7.21
The layout o f the drain mixer for the minimum IM3 design.
173
Figure 7.22
The measured noise figure and conversion gain of the drain mixer.
173
Figure 7.23
The measured IM3 o f the drain mixer.
174
Figure 8.1
Experimental measurement o f mixing transconductance o f a drain
Figure 8.2
mixer at low VHF frequencies.
180
The schematic diagram of a balance drain mixer.
18 1
11
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List of Symbols
ai/>’ a2p’ °i/.’•••
pumped i th-order coefficients o f drain current versus gate
axt
/ th-order coefficients of drain current versus gate voltage
^3 »•
•^1 * ^2 ’
* •
^lr 9^ k parameters o f the new I-V characteristics model o f a FET
BW
bandwidth
K
expansion coefficient o f gm(t)
ck
expansion coefficient o f gm(t)
cP
equivalent resonant capacitance of a DTMBPF
cm
capacitance between two metals
cr
fringe capacitance
c lF
IF output matching capacitance
Ccd
coupling capacitance through the dielectric o f a substrate
Cca
coupling capacitance through the air of a substrate
Cn
c*
gate-to-source capacitance
Cgd
gate-to-drain capacitance
pumped gate-to-drain capacitance
C*
gate capacitance under no dc gate bias
c
light speed in free space
Cc
coupling capacitance between two parallel microstrip lines
CRS
controlled random search
DTMBPF
double-tuned microstrip bandpass filter
dc
directed voltage/current
DM
drain mixer
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d
thickness of a substrate
E 0,
amplitude of a standing wave
E0
voltage amplitude o f equivalent LO signal
Et
source voltage
FET
field effect transistor
E\ »
f;
ideal filter to the RF signal frequency
F0, F ’
ideal filter to the LO signal frequency
f 2, f 2
ideal filter to the image signal frequency
f >, f ;
ideal filter to the IF signal frequency
mixing conversion gain
G jt)
pumped drain-to-source conductance
Sk
pumped coefficient o f transconductance
Si
mixing transconductance
mixing transconductance in Vd>0
S ir
mixing transconductance in Vd<0
So
small signal or dc transconductance
g m(‘)
pumped transconductance
HEMT
high electron mobility transistor
IF
intermediate frequency
^0
dc drain bias current
I dim
parameter of a transistor of Meterka’s model
1*
parameter of a transistor of the new model
Id.th
modeled drain current
Id .a
measured drain current
Id
intrinsic drain dc current
Id M
pumped intrinsic drain current
IM3
third order intermodulation
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/„ , /„
equivalent currents o f LO signal
/,, / 4
equivalent currents o f RF signal
I 2, I s
equivalent currents o f image signal
/ 3, / 6
equivalent currents o f IF signal
/„
equivalent currents of harmonics
£0
propagation constant in air
k
coupling coefficient
le
effective coupling length
/,
distance between the tapped point to the effective ground in a
DTMBPF
equivalent resonant inductance of a DTMBPF
L
P
Lx
tapped inductance
LO
local oscillation
I,
total length of a resonator o f a DTMBPF
Nl
tapped coefficient
N,
total number o f sampling point, N ,= m x n
PCS
Personal Communication Systems
PGTV
pumped gate total voltage
Pai
power reading o f a spectrum analyzer
power consumed on a load
Q-point
dc bias point o f a transistor
QSLS
quasi-static large signal
Ql
loaded quality factor
Qy
unloaded quality factor
Rsf
surface resistivity
Rs
source resistance o f a FET
Rp
equivalent resonant resistance of a DTMBPF
R
channel resistance o f a “cold” equivalent circuit of a FET
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RF
radio frequency
X*
drain resistance
R*
drain shunt resistance
Rl
load resistance
Rg
gate metal resistance
R,
gate ohmic contact resistance
V
Ru
-V
------ , a parameter of Fukui measurement
j
V
R22
—V
------ , a parameter of Fukui measurement
j
s
coupling gap between two parallel microstrip transmission lines
Sa
distance between the open-circuited terminal to the edge o f the tapped
transmission line
ta n S
tangential loss of a substrate
TEM
transverse electromagnetic
MTMBPF
multi-tuned microstrip bandpass filter
VAM
The Volterra-Series Analysis And Measurement
v+
the gate dc bias voltage at the maximum transconductance
v,
threshold voltage of a FET in positive region
r Po
threshold voltage of a FET in negative region,
y*
dc gate bias
r*
drain voltage
vd
intrinsic drain voltage
Vao
intrinsic dc drain bias voltage
pumped dc drain offset voltage
dc drain bias voltage
gate voltage
Vp(0
gate input voltage
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Vg
the intrinsic gate voltage
Vg0
the intrinsic dc gate bias voltage
V^o
dc gate bias voltage
gate-to-drain and source voltage when the drain and source are
connected together
gate-to-source voltage with the opened drain
Vgdf
gate-to-drain voltage with the opened source
K
amplitude ofLO
r.d)
output voltage o f a ideal mixer
Vs it)
total pumped gate voltage
K
voltage o f the first order output
V>PP
peak-to-peak voltage o f the first order output
K
amplitude of RF signal
v**
drain knee voltage o f a FET
w
width of a microstrip circuit transmission line
Zo
characteristic impedance
z*
.
input impedance
Zt
source impedance
^OLO
the output impedance of the LO port at the drain o f the FET
ZoiF
the output impedance o f the IF port at the drain o f the FET
a
a parameter o f a FET
<*r
a parameter o f a FET
<*a
total attenuation constant o f a substrate
dielectric attenuation constant o f a substrate
<*c
conductor attenuation constant o f a microstrip circuit
X
a parameter of a FET
K
effective wavelength in a substrate
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CO
angular frequency
RF signal angular frequency
(°RF0
center angular frequency of the RF signal
^IRFO
center angular frequency o f the IF signal
resonant frequency, local oscillating frequency
fix
propagation constant in a circuit
P
constant of early I-V model
r
ripple coefficient
<p
building potential voltage
<Pa
a parameter of Angelov’s I-V model
effective dielectric constant o f a microstrip circuit
er
8
dielectric constant of substrate
P iL -
P ia
input reflection coefficient
r opf( M )
optimum source reflection coefficient for minimum
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Chapter 1
Introduction
Early FET mixers had disappointing noise figures even though they had conversion
gain. The noise figure of these mixers were even worse than that o f a diode mixer.
Because diodes were more convenient to use in balanced-mixer circuits and were less
expensive, most designers were slow in accepting the FET mixers.
Recent developments have demonstrated that well-designed FET mixers[l][2][3] have
noise figures comparable to the diode mixers and with conversion gain at frequencies
extending well into the millimeter wavelength range[4]. Other performances of a FET
mixer such as distortion level, bandwidth, and stability are comparable to those o f a diode
mixer. The most remarkable aspect is that the FET mixers are more easily fabricated in
microwave MMIC circuits compared to the diode mixers.
Basically, there are two types o f FET mixers; dual-gate FET mixers and single-gate
FET mixers. Dual-gate FET mixers, where the radio frequency (RF) signal and local
oscillation (LO) signal are applied to the separate gates o f the FET have the distinct
advantage o f good separation between the RF and the LO ports. The single-gate FET
mixer can be designed in a variety of mixing modes. The RF signal is usually injected
into the gate and the LO signal can be fed into the source, the drain or the gate. The gate
mixer with both the RF and LO signals applied to the gate o f the FET has been found to
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have the best overall performance historically. Other operating modes can also have
certain advantages - particularly in MMICs where simplicity is very important.
A single gate FET mixer still does not have the same noise performance as that o f an
amplifier if the same FET is used for the both circuits. A well-designed MESFET gate
mixer has a noise figure in the order of 5 dB with a conversion gain in the order o f 6 dB
at X-band. In addition to the higher noise figure, it is not an easy task to design a gate
mixer accurately due to the operation in the strong nonlinear region and in large signal
mode.
Early GaAs MESFET gate mixers were developed theoretically and experimentally by
Robert A. Pucel at el. [5] in 1976. Both RF and LO signals were applied to the gate o f the
FET with the dc gate bias close to the pinch-ofif region and dc drain bias in the saturation
region. This work pointed out the difficulty o f the analysis o f the gate mixers due to the
large signal operational mode. The small signal equivalent mode was used and the
transconductance gm{t) is considered as a time-varying function o f the LO signal. In
Fig. 1.1, the small signal model of the gate mixer is given. The transconductance gm(t) is
time-varying with a period equal to that o f the LO signal:
&.(o=£&«'“w
(i d
where tq, is the angular frequency of the LO signal.
In Fig. 1.1, Rd = R0 is a time-averaged component o f the drain resistance. All the
other parameters o f the FET are assumed not to change with the LO signal. By
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considering only three frequency-components IF, RF, and LO in the input and output of
the mixer, the
z.
z;
F.
<«, ( L O )
, (LO)
!iB r„
z ;
F,
z.*
f;
w (RF)
■w Omogt)
•
■£®"1
Figure 1.1 The small signal model o f the gate mixer.
following conversion gain is obtained:
l/.l’ R c f c ]
*
"
(12)
where I 6 and Z6 are the current and impedance at the output IF port. £, and Z, are the
source voltage and source impedance of the RF signal at the input port of the mixer.
Theoretical and experimental results show that in a gate mixer the FET must work in a
strong nonlinear region and the dc gate bias Vp0 must almost be equal to the pinch off
voltage V in order to have higher conversion gain. The experimental results at 7.8 GHz
show that this type o f a mixer has a typical 6 dB conversion gain and a noise figure of
7.4 dB which are in agreement with the theoretically predicted values[5]. In this study,
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the transconductance g m is considered as a nonlinear component for predicting the
conversion gain. The noise performance and matching networks are not discussed in
detail.
A more complete and accurate model for the design and analysis o f a FET gate
mixer is given by S.A. Maas [6][7]. Here, a large signal model is used and harmonic
influence o f LO to the mixer is considered as shown in Fig. 1.2. Three nonlinear elements
are included in the analysis. Those are the drain current, gate to drain capacitance, and the
gate to source capacitance. In this design, typical noise figure o f a FET mixer is in the
order o f 5 dB with a conversion gain o f 6 dB at 8 GHz.
From the previous works in the design o f a single gate FET mixer with a maximum
conversion gain and better noise figure, the following rales can be summarized:
Condition 1:
Maximize the fundamental LO frequency component o f the
transconductance g m(t) , and minimize the time-variation o f other circuit elements,
especially the drain-to-source conductance G ^ t ) . These will minimize the noise figure
and maximize the gain o f the mixer.
Condition 2: From condition 1, drain-to-source voltage must be kept constant and
maximized in order to have good gain and noise performances. Thus as the FET is
pumped by the LO, it is imperative that the total drain voltage V& is not allowed to
decrease substantially from its dc bias value during any part o f the LO cycle. This means
that the LO signal can only be applied to the gate rather than to the drain of the FET.
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Condition 3: In order to have maximum gn (t), the dc gate bias must be set close to
the pinch-off voltage o f the FET. In other words, the FET works in the strong nonlinear
region, as shown in Fig. 1.3.
Condition 4: LO signal must be shorted at the drain. Failing to do so decreases g m(t)
and increases G ^it) which decreases the conversion gain and increases the noise figure
o f the mixer.
,(ti
V,LO
00
Figure 1.2 The equivalent circuit o f the Maas ’gate mixer.
For special applications such as low intermodulation products[8][9][10][ll], other
mixing modes of the FET mixer can be used. In this case, another mode o f the FET mixer
- resistive FET mixer[12][13][14][15][16] is proposed. The LO signal is applied to the
gate o f the FET based on the condition 2 and the RF signal is injected into the drain of the
FET with no dc drain bias. The dc operating bias point Q is selected as shown in Fig. 1.4.
As a matter o f fact, the FET works in the ohmic region. Under these conditions, the
channel resistance o f the unbiased FET is only very weekly nonlinear. The unbiased
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channel operates as a simple resistor where resistance can be varied by changing the gate
voltage. This type o f mixer has very low intermodulation products with - 6.5 dB
conversion loss and 6.6 dB noise figure.
Id
VdsO
Figure 1.3 The dc bias point o f a typical FET gate mixer.
Id
Figure 1.4 The dc bias point o f a typical FET resistive mixer.
Instead o f operating in the very strong nonlinear region o f a FET, operation in the
ohmic region has the following properties:
a)
Frequency mixing occurs;
b)
Noise figure, and intermodulation are comparable to the gate mixer or
may be further reduced.
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In 1979, G. Begemann theoretically analyzed the gain properties o f a FET drain mixer
[17]. LO and RF signals are applied to the drain and the gate o f the FET respectively. A
FET model similar to that o f [5] is proposed except both nonlinearities of gm and Rd are
considered due to large LO signal injected into the drain. The results of these calculation
are shown in Fig. 1.5. From Fig. 1.5, several conclusions can be obtained:
1) Gm increases with increasing dc drain bias
in a certain range of V^;
2) Gm increases with increasing V&\
3) Gm=0 when F*0 = 0;
4) the calculated conversion gain GM can be more than 15 dB.
«r
0-2 v
o-a
05
Figure 1.5 The Begemann’s theoretical conversion gain o f the drain mixer.
Here, the transconductance g m(t) is assumed to change with the LO signal similar to
the gate mixer. It will be shown later that, as a matter o f fact, the mixing
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transconductance g x becomes very small in the saturation region. Obviously Begemann’s
theoretical results were not practical especially after the 4 criteria are established by Maas
at. el.
After Begemann’s work, a few works[18][19] were published in the area of ‘FET
drain mixer’ as a result o f the four mixing criteria even though many FET mixers were
both developed theoretically and experimentally [20][21].
In this research, another type drain mixer (DM) is developed. Basically LO signal is
injected into the drain o f a FET with no external dc drain bias, and RF signal is injected
Id
Figure 1.6 The bias point o f a drain mixer.
into the gate o f the FET with the dc gate bias
away from the pinch-off region. The
main principle o f DM is that the Q point is selected at the origin, as shown in Fig. 1.6.
The mixing phenomenon due to the gain o f a FET is a time-varying function o f the LO
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signal since the drain current is the time-varying function o f the LO signal. Since the LO
signal is applied to the drain with no dc drain bias, the region o f Vd <0 also participates in
the operation o f the DM. The negative cycle of the LO signal swings into this region. The
gate bias can be chosen so that the mixer has minimum noise figure, maximum
conversion gain, or minimum intermodulation products.
In this work, the complete mechanism of DM
is presented. The mixing
transconductance is calculated at various dc bias points and LO power levels. It is found
that the conversion gain reaches a maximum at zero dc drain bias and decreases with
increasing dc drain bias. A model for predicting the conversion gain is developed so that
the multi-port o f the mixer can be analyzed using a linear simulation program such as
Touchstone. A model for predicting the third order intermodulation products based on the
first order output or conversion gain is also developed. The third order products are found
to decrease with increasing LO power level. The complete measurements o f the
conversion gain, intermodulation products, and noise figure are discussed.
The quasi-static large signal (QSLS) equivalent circuit for designing a FET mixer is
developed. In QSLS, the parasitic elements are assumed to be the same as that o f the
small signal elements. The nonlinear elements are modeled by a modified I-V
characteristics model under the LO pumped signal. The higher harmonic effects are
ignored since the pumped first order transconductance dominates the frequency
conversion. In other words, only the pumped mixing transconductance is based on the
first order frequency o f the LO signal. This assumption certainly introduces error since
the higher order harmonics o f the pumped transconductance also contribute to the
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frequency conversion. The calculated conversion gain is thus slightly lower than that of
the measured value. Under this assumption, QSLS equivalent circuit contains three ports.
Only three frequency components are taken into account in the QSLS equivalent circuit.
These are the RF signal frequency, the LO signal frequency, and the IF frequency.
The stability model o f a mixer is also developed.
The average pumped
transconductance is believed to be responsible for the stability. Based on the developed
QSLS equivalent circuit, the stability circles of the input impedance and output
impedance are investigated. The results show that the new drain mixer is very stable at
selecting source impedance. The gate mixer compared to the drain mixer is in very strict
conditional stable condition.
With the DM design, a mixing conversion gain of ~10 dB and a noise figure of ~3 dB
within the 500 MHz bandwidth at 12 GHz are obtained using a commercial HEMT
(NE33284A) with a dc gate bias of -0.5 V, no external dc drain bias, and a LO power of
lOdBm. The performance is believed better than these of a gate mixer when the same
transistor is used.
The optimum operation for the best intermodulation products o f the mixer is
identified when a HEMT (NE33284A) is used. It is found that the mixer with the dc gate
bias o f -0.6V provides the lowest third order output with the higher conversion gain and
lower noise figure.
Besides having much better performance, DM can be designed more accurately
because the dc gate bias is not set near the pinch-off region and the gate operates in the
small-signal mode. Note that dc gate bias of a gate mixer is close to V which is difficult
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to model accurately because o f the strong non-linearity. This is very important in the
application o f FET mixers in MMICs.
A gate mixer is also designed based on the developed models here. Calculation o f
conversion gain and third order intermodulation products are carried out. Zero mixing
phenomenon is observed theoretically and experimentally at a dc gate bias of -0.3 V
when a NE33284A is used. The physical mechanism for this effect is found to be due to
the 180° phase difference o f the pumped mixing IF currents at both sides of Vgs0= 0.3V. The conversion gain o f 9 dB with the noise figure of 6 dB were obtained. Due to
the complexity o f the gate mixer, the noise figure is higher than it should be no matter
how the matching circuit is timed. The reason for this is still not clear. May be a HEMT is
not suitable for a gate mixer.
In order to accurately design a mixer, drain current model of a FET is essential.
Analytical or real ‘physical’ FET models have been only partly successful because o f the
complexity o f the
FET, especially in the case o f large signal and strong nonlinear
operation such as a mixer. Although two-dimensional analysis o f the FET’s channel [22]
may be a highly accurate way to model a real FET, it is too slow and complex for use in
computer-aided design. Empirical models are more practical and successful. In other
words, the drain current related to the gate and drain voltages is modeled mathematically.
At present, as is well known, the most widely used models are those of Curtice,
Materka, Statz, and Rodriguez. Those models are originally developed for silicon based
FETs. The dependency of drain current on the gate voltage is described according to the
square law. This is not good enough to describe the GaAs based MESFET or HEMT.
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Especially the derivatives of the drain current of those models may have considerable
error.
Angelove’s model [23] is a typical successful model for a HEMT. The drain current is
modeled based on the observation o f the first derivative of the drain current or the
transconductance to be a “bell” shaped curve. This means the drain current versus gate
voltage does not follow the square law. The phenomenon is also observed in the ohmic
region (low drain voltage) for a MESFET. This is also the reason for failure of the most
models describing the I-V characteristics of a FET in the ohmic region [24].
The reason for the “bell” shaped curve o f the transconductance is that the rate of
increase in drain current with increasing dc gate bias declines significantly at a bias level
above -0.3V[25]. This corresponds to the onset o f conduction via the parasitic MESFET
within the HEMT structure. In other words, if the gate applied bias is not sufficient to
deplete the AlGaAs layer completely, then a conduction path (parasitic channel) between
the source and drain is developed through this layer.
In the ohmic region o f a MESFET, the rate of increasing in the drain current with
increasing gate voltage also decreases. This is due to the fact that the electrons do not
travel with the saturated speed in the channel. In other words, the speed o f the electrons is
limited by the drain-to-source voltage in spite o f the increasing gate voltage. The bell
shaped transconductance is also observed.
The hyperbolic tangent function describes the “bell” shaped curve and its derivatives
very well. The drain current model in [23] is given by:
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h = ! Pk t1 + tanh{<Pa)](! + kVd) tan h (a^ ,)
(1.3)
where I pk is the drain current at which maximum transconductance occurs. The drain
voltage dependency in (1.3) is the same as those in the Statz and Curtice models. In
general, <pa can be represented by a power series function centered at Vpk with V as a
variable i.e.
d-4)
k
Here Vpk is the gate voltage for maximum transconductance and Ak is the coefficient of
the expansion.
There are some limits in (1.3). First o f all, maximum drain current is only two times
that of I pk. For most HEMTs, the maximum drain current could be more than 2 1pk.
Second, the I-V characteristics at Vd > 0 is only modeled. Third, the drain current
dependency o f the drain voltage can be described better if the arc-tangent function is used
instead o f the hyperbolic function.
An improved nonlinear model is presented in this work for describing better I-V
characteristics o f a HEMT or a MESFET.
(lia rc ta n fa ^ )
Vd >0
7J = / i„ ta ilh [ > f „ ( ^ - ( ',0 - /l( ') ] a rc ta n ( a r( ')
Vd < 0
(1.5)
where I pk and Vpk have the same meaning as those in (1.3). VpQ is the pinch-off voltage
at ^ 0 = 0 V. Again, At and A2 are the parameters o f the transistor. The A2 is introduced
in (1.5) to describe the ratio o f the maximum drain current to I pk .
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I pk,V pk, Al t Atr, A 2, l , a, and a r can be determined by curve fitting the measured IV characteristics o f a FET at different gate and drain biases. The I-V characteristics of the
FET can be measured by a curve tracer or a semi-conductor device analyzer. The goal of
curve fitting the theoretical I-V characteristics to the measured data is to adjust the
parameters I pk, Ax, A2, and a or 1 ^ , A,r, I , and a r in (1.5) so that the following
objective function is minimized:
(1.6)
where I d th and I dex are the curve fitted and the measured drain currents at m gate bias
points and n drain bias points, respectively. N = m \ n is the total number of sampling
points. This objective function is subject to the constrains,
I pk>0, Ax>0, A2>Q, Vpk <0, anda> 0
and
/* > 0 , Alr>0, k>0, Vp0 < 0 ,and a >0
(1.7)
Controlled random search (CRS) method[26] is an excellent optimization method for
global optimization with n-space unknown variables. The Q-basic CRS program is
written for the optimization. Several HEMTs (NE33284A) and GaAs MESFETs
(NE71084) were used for the modeling. As an example o f the improvement over the
conventional models, the drain current o f NE33284A in Vd >0 was modeled using the
new model, Meterka’s model, and Angelov’s model. The new model provides E 0 of
0.093, the Meterka’s model of 0.257, and Angelov’s model o f 0.123. The improvement is
obvious.
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The intermodulation performance o f a mixer is important. Volterra-series analysis is
the most efficient and practical tool for determining the intermodulation performance in
small signal and quasi-small signal FET circuits. Thus, this tool can be used to analysis of
a mixer intermodulation performance.
The I-V characteristics o f a FET can be characterized by Taylor-series expansions in
the vicinity o f the dc gate bias points. The drain current I d (Vg) can be expressed as
W ) = a , ( F g - P ; o) + a2( yt -yto)2+a3(VB-yg0)i+-
(1.8)
where a, is equivalent to the linear transconductance, a2 is related to the second order
intermodulation component, az is related to the third order intermodulation component
and so on. Vg0 is the intrinsic dc gate bias.
Many theoretical and experimental models have been proposed to predict and measure
the coefficients in (1.8). The low-frequency RF measurement method is a typical one[27].
In the low RF frequency band, parasitic elements o f a FET such as parasitic inductances
and capacitances can be ignored while the measured coefficients are the needed practical
parameters in the microwave frequency bands. The reason for this is that these measured
parameters will be constants above 100 kHz. In other words, the parameters measured at
dc level or at frequencies below 100 kHz will vary compared to that at RF frequencies.
This is traditionally referred to as frequency dispersion effect. The frequency dispersion
tend to disappear above 100 kHz for GaAs based FETs.
In this work, a more accurate model is demonstrated based on the low RF frequency
measurements[27]. The gate voltage and the first order output are measured directly to
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eliminate the error in predicting a x in (1.8). A method for accurately measuring the power
levels o f the output harmonics is also developed.
The equivalent circuit o f the FET at low RF frequencies is similar to the traditional
one, as shown in Fig. 1.7. RL is selected to be small enough so that the drain current
passing through
The rms value
can be neglected. A highly precise resistor RL o f 3.9 ohms is used.
o f the input RF signal applied to the gate and the rms. value Vx of the
first order output signal are measured directly by a scope. Thus, the voltage Vg and the
first order coefficient a, can be determined very accurately. Also the power levels o f the
harmonic components on
RL can be obtained according to the measured Vx and the
readings at different harmonic frequencies from a spectrum analyzer connected across at
the 3.9 ohm load. Note that the measured power level across the load resistance RL is
different from the real harmonic power across RL. The measured power level Pai is the
power across the input impedance of the analyzer (50 Ohms). However, the real harmonic
power level can be determined by the known Vx and Pai since
RL and the input
impedance o f the analyzer are known.
A theoretical model is developed based on the method described above. A RF
frequency o f 4.5 MHz is used for the measurements since 4.5 MHz ceramic filters are
available commercially. The harmonics of the 4.5 MHz source itself has to be filtered out
in order to measure the harmonics generated by the transistor only. The theoretical
calculation o f the coefficients based on the developed I-V characteristics is also carried
out. As an example, a NE33284A HEMT is used to verify the model.
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Ed
y'qs
±
S
Figure 1.7 The equivalent circuit o f a FET at low radio frequency band.
For the design and implementation o f a DM, a simple but well-designed filter
becomes an advantage. For these purpose, double-tuned microstrip band pass filter is
developed. Combline filter is one o f the widely used bandpass filters in many application
areas extending well into the millimeter frequency range[28]. As shown in Fig. 1.8, a
conventional tapped combline filter consists o f a set o f parallel metal bars loaded by
lumped capacitors made o f timing screws, chips or beam lead capacitors. To design the
conventional combline filter, certain approximations have to be made due to the fact that
the exact theory o f the combline filter synthesis only works for commensurate lengths
propagating TEM-modes. A typical printed microstrip combline filter with parallel
comblines loaded with beam-lead capacitors is shown in Fig. 1.9 [29]. More complicated
theory for the design o f these filters is needed because o f the existence of multiple quasiTEM modes associated with the parallel microstrip lines.
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The conventional combline filters whether they are parallel metal bars or printed
microstrip structures have capacitor loads. In a typical circuit, the number o f the parallel
units are more than three. Every unit of those parallel bars or printed circuits do not
resonate at the design frequency. Each unit with the loaded capacitor contribute to the
required performances of the filter.
M etal B ars
O utput
Tuning S re w s
Figure 1.8 A conventional taped combline filter.
In this work, a practical microstrip filter based on the lumped double-tuned resonant
circuit concept is investigated. The filter consists o f two microstrip resonators coupled to
each other similar to a double-tuned circuit. This structure is much easier to design than
that o f the conventional combline filter. The filter uses less area and introduces less loss
since no capacitive loads are used. The low frequency double-timed filter theory can be
used to analyze and design of filters at the microwave frequencies. Touchstone
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B eam -L ead C a p a c ito rs
G round
Input
O utput
Figure 1.9 A coplanar microstrip combline filter.
program is used for fine tuning and simulations. Several DTMBPFs were fabricated at Xband and Ku-band based on the Touchstone simulation results. The differences between
the simulations and the experiments o f the typical DTMBPFs are under 3%. A 7-pole
filter at Personal Communication Systems (PCS) frequency band is simulated. The more
details about this filter are presented in chapter 2.
The dissertation is organized in the following sequence: In Chapter 2, the DTMBPF is
investigated theoretically and experimentally. In chapter 3, an improved model for I-V
characteristics o f a FET is developed and verified. Chapter 4 describes the low RF
frequency method to determine the harmonic coefficients o f a FET. In chapter 5, the FET
characterization and QSLS equivalent circuit for the design o f a mixer are investigated.
The frequency conversion o f the new FET drain mixer is presented in detail. Chapter 6
described the design of the gate mixer using QSLS equivalent circuit. Conversion gain,
36
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noise figure, and intermodulation performances are measured and discussed. In chapter 7,
the design o f matching networks for the drain mixer, the simulations for predicting the
conversion gain, and the third harmonics are investigated. The measurements of
conversion gain, noise figure, and intermodulation products are presented in detail. The
stability model o f a mixer is also presented. The stability circles o f the input (gate) and
output (drain) are created. Chapter 8 is the conclusions and recommendations for future
works.
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Chapter 2
Double-Tuned Microstrip Bandpass filter
Combline filter [28] [29] [30] [31] [32] is one of the widely used bandpass filter in many
application areas. To design the conventional combline filter as mentioned in the first
chapter, certain approximations have to be made due to the fact that the exact theory o f
the combline filter synthesis only works for commensurate lengths propagating TEMmodes. Complicated theoretical design is involved[33][34][35][36]. In this chapter,
double-tuned microstrip filter is investigated based on the double-tuned resonant circuit
design technique and Touchstone simulation.
2.1 Structure:
Fig. 2.1(a) shows a physical structure of a double-tuned microstrip band pass filter
(DTMBPF) which is developed based on the low frequency double-tuned resonant circuit
concept. It is assumed that the widths of all the microstrip transmission lines are designed
so that the characteristic impedances are 50 ohms. The filter is also designed so that the
physical structure o f the input and output of the DTMBPF is symmetrical.
The filter consists o f two parallel half-wavelength microstrip resonators with opencircuits at both terminals. These two resonators are used as the double-tuned resonant
circuits. Two parallel quarter- wavelength resonators with one side grounded can also be
38
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used. Thus, the resonators can be half-wavelength or quarter-wavelength. It depends on
the specific application. The input and output transmission lines are tapped to the
resonators in order to maintain the high loaded Q o f the resonators.
(a) The physical structure o f a double-tuned microstrip band pass filter.
(b) The equivalent circuit o f double-tuned microstrip band pass filter.
Figure 2.1 The physical structure and the equivalent circuit o f a
double-tuned microstrip band pass filter
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The length of the two parallel half-wavelength microstrip resonators is I, . The distance
between the tapped connection point o f the input transmission line and the equivalent
ground is /,. Sa, as shown in Fig. 2.1 (a), is the distance between the input transmission
line and the open circuit terminal of the resonator, or, /, = 5 a - X J 4 + w /2 , where A, is
the effective wavelength of the signal in the substrate. The equivalent circuit of the filter
is shown in Fig. 2.1 (b), where Cc is the equivalent coupling capacitance, Lp and Cp are
the equivalent resonant capacitors and inductors of the circuit, and R is the equivalent
resistance due to the total loss of the resonators.
2.2 Theory
To design a DTMBPF, the following parameters of the DTMBPF must be determined
according to a given frequency band and a substrate: the width
w of all microstrip
transmission lines, the length /, o f the parallel resonators, the tapped connection point
position /, or Sa, and the coupling distance s between the two parallel resonators.
The width w and the I, can be determined in a straight forward way when the
characteristics impedance Z0 = 50Q and the design frequency are given for a known
substrate [37]. Here, /, is the effective half-wavelength on the substrate when half­
wavelength resonators are used. The characteristics impedances of those resonators do
not have to be 50 O. Other values may be selected according to the overall performances
o f the filter.
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2.2.1 Coupling gap s between the two parallel resonators
The equivalent lumped elements of an ideal single half-wavelength microstrip
resonator at resonant frequency o f co are given by[37]:
(2. 1)
where Xe is the effective wavelength on the substrate, and a a is the total attenuation
constant due to the dielectric and the conductors. a a is given by
K sX et -l)tan < ?
Rsf
*zy
2k
°"v
The surface resistivity R!f and unloaded quality factor
(2.2)
are given by
(2.3)
In these equations,a d, a c are the respective attenuation constants due to the loss o f
the dielectric and the conductors o f the substrate, 8 is the tangential loss factor of the
substrate, a is conductivity o f the conductors. er and s e are the dielectric constant and
effective dielectric constant o f the substrate respectively.
For coupled parallel resonators, the overall resonant capacitance Cp or the
resonant inductance Lp is different from that of a single resonator because of the coupling
between the two resonators. The resonant capacitance Cp and coupling capacitance Cc
however can be calculated accurately. As shown in Fig. 2.2, the electromagnetic field
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between the two coupled transmission lines can be divided into two modes: even mode
and odd mode. Only the odd mode o f the fields has coupling between the two resonators.
The equivalent unit length capacitances o f the two resonators in Fig. 2.2 are: the
capacitance between the transmission line and the substrate Cm, the fringe capacitance
Cf , and the coupling capacitances Cca and Ccd between the two resonators through the air
and the dielectric. These unit length capacitance are given by [38]
Cm = s 0erw / d, £0 = 8.854x 10-'2 / / m
Cf = 0 5
cZ
(~’m
, c = 3x 10 m is
Afc*) , x =
C- ~ * ‘ K(x)
s + 2w
,x a
0 .0 2 ^ 7
+ l-£
s/d
K(x)
-In
n ri-V 7
1 , r l+ v ri
-2
0 < x < 0.7
(2-4)
0.7 < x < 1
r i- v d
where w and d are the width o f the transmission lines and the thickness o f the substrate,
s e is the effective dielectric constant o f the substrate.
To calculate the total coupling capacitance Cc and the equivalent resonant capacitance
Cp, the effective coupling length le (rather than the half-wavelength) must be used
because o f the standing waves on the resonators. Thus, the total coupling capacitance is
equal to the unit coupling capacitance time the effective coupling length le which the
uniform field distribution is assumed. As shown in Fig. 2.3, obviously
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^ jt/2
/e£ 0 j = - j E 03 cosOdO,
l,= XJ2
here Em is the amplitude o f the standing wave as shown in Fig. 2.3.
then
(2.5)
h= -lt
n
The total coupling capacitance of the half-wavelength is given by
c , = l.C a = I,
(2.6)
12
The resonant capacitance of DTMBPF is determined by
C, =(C. +C/ ) ~ + 2C1.- ( c . +C/ + i ^ ) i -
(2.7)
The resonant inductance Lp and the resistance Rp of the circuit are then determined
by (2.1).
From the lumped double-tuned resonant circuit theory [39], the relationship between
the resonant capacitance and the coupling capacitance is given by
Cc =kCp
where k is the coupling coefficient. Substituting it into (2.7), the coupling capacitor
becomes
43
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zz
4i
zz
Magnetic wall
Cf
Cp
Cf
Electric wall
Cca
Cm
Ccd
Figure 2.2. A “coupled microstrip lines ” configuration and break-up
o f capacitance fo r the even and odd modes.
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i c m+cr)-f
Cc =
(2.8)
1 -2 k
'Os
Figure 2.3. The effective coupling length o f the resonators
Fig. 2.4 shows the frequency response of the double-tuned resonant circuit filter based
on the equivalent circuit shown in Fig. 2.1(b). The bandwidth B W is given by[39]:
BW = f 2 - f[
(2.9)
Ac
Figure 2.4. Thefrequency response o f a typical
double-tuned resonant circuit
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The loaded quality factor QL relates to the ripple coefficient y by
kQL= z + V
z r -T
(2.10)
and
(2 . 11)
where f c is the center frequency of the filter, and
The parameters f e, / , , f 2, / , ’, f 2, Ap, Ac o f the filter are defined as shown in Fig. 2.4.
In summary, for a given bandwidth BW and ripple coefficient y, the coupling
coefficient k and the QL are determined from (2.10), and (2.11). Then, the unit coupling
capacitance CI2 are obtained from (2.8), (2.5), and (2.4). Thus the coupling separation
distance s can be determined from (2.4).
2.2.2 Determination of the tapped position /,
From the lumped double-tuned resonant circuit theory, the loaded and unloaded Q's
are
Q l ~ a*t)CpRtL, Qq —eo0CpRp
(2. 12)
where RtL is the loaded resonant resistance,
RlL= R p / / ( N 2Z0)
(2.13)
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N is the tapped coefficient of the double-tuned resonant circuit,
L
(2-14)
and Lx is the inductance o f the circuit from the tapped point to the effective ground.
Substituting (2.13) into (2.12), we have
N = q* - q l ~ t
(2‘15)
Substituting (2.14) into (2.15) and using the transmission line theory
2 TV
jcoLx = jZ 0 tan(/?/,), P = ~ ~
(2.16)
results in
(2,7)
Then /, is given by
l = — ta n '1
'
2*
&&
(2.18)
1
;
A computer program is developed for calculation o f the parameters
and Ql based on the equations (2.1) through (2.18) once a substrate is chosen and the
performance o f the filter is specified. The flow diagram for this program is given in Fig.
2.5.
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Input er,Z Q,h,\m {5)
Calculation o f
Calculation o f
Qo >Ql »Y' h >^
Figure 2.5 The flo w diagram o f design a double-tuned microstrip band pass filter.
The DTMBPF is also simulated using a Touchstone program. Fig. 2.6 shows the
model used in these simulations. The Touchstone file for simulation o f the 11.5-12.0 GHz
can be found in Appendix A2-1. Two microstrip coupled lines and two tees are
considered. The starting values of the parameters w, d, lt, s, and /, o f DTMBPF for the
simulation are taken from the calculated results o f equations (2.1) to (2.18).
The ideal open line is used in the simulation model in Fig. 2.6 instead o f using the
open line with the edge effect because o f the difficulty to consider the coupling line and
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the edge effect open line together for the Touchstone program. If the edge effects of the
open lines are not considered the experimental equivalent lengths o f the resonators are
n b ( 12;
Figure 2.6 The Touchstone simulation model o f a double-tuned
microstrip band pass filter.
about 1.7% longer than those o f the Touchstone simulation at a given frequency. Failure
to take into account o f this in the simulation of the filter results in the center frequency of
the experimental band pass filter to be down-shifted about 1.7% compared to that of the
simulation result.
2.3 Design Examples:
Three sample filters were built to verify the design guidelines presented above.
The center frequency o f the first filter is at 10.73 GHz with the bandwidth of 200 MHz.
The second and third filters have center frequencies at 11.75 GHz with bandwidth o f 500
MHz and 11.95 GHz with bandwidth of 700 MHz, respectively.
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RT/Duroid 5880 substrate having the following properties is used
tan( 8 ) = 0.0009
er=2.2
t=0.7 mils
d=I0mils
roughness = 0.012 mils <x=5.813 x 107 / Clm (copper)
w = 31.26 mils
^= 1 .8 7
t is the thickness o f the conductor foil, w is thetransmission line width
where
corresponds to a characteristics impedance o f 50 Q at 10 GHz.
The parameters of the filters according to both the calculation based on the
double-tuned filter theory and Touchstone simulation are listed in the Table 2.1.
The half-wavelength resonators are preferred for practical applications. This
structure has an inherent dc isolation between the input and the output o f DTMBPF.
This eliminates dc isolating capacitors when the dc biases may be required for the active
devices.
The simulation lengths Sa and /, from Table 2.1 are longer than those of the
double-tuned theoretical calculations since the lumped element calculations do not
accurately model the T-junction between the resonant circuit and the input transmission
line. In other words, the input transmission line has a certain width which will cause the
effective lengths Sa and /, to be longer than those o f the lumped calculations.
Fig. 2.7 shows the experimental and simulated frequency response o f the 11.50 12.00 G Hz bandpass filter. The dotted-line represents the simulation results and solidline is the experimental result using HP8510 network analyzer. The agreement between
the simulation and the experiment is very good, within 3%.
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Table 2.1 The structure sizes o f the double-tuned microstrip band pass filters
Freq. (GHz)
Double-tuned calculation results
Touchstone simulation results
11.50-12.00
A e= 734.70 mils
A ~ 734.70 mils
/,=11.75
lt = 367.35 mils
I, =382 mils
S a =181.21 mils
S a =200 mils
/, = \2&4 mils, s=10mils
s=10mils
0 o = 4 3 8 , Ql =8.96
10.63-10.83
A e=804.55 mils
Zo-10.73
1 = 402.3 mils
lt =410 mils
S a =191.43 mils
Sa =220 mils
/, =5.91 mils, s=30 mils
s=20 mils
A = 804.55 mils
Qo=358.4, Qe = 20*
11.60-12.30
A»e=719.40 mils
/ c=11.95
1= 359.7 mils
lt =368 mils ~
S a =176.52 mils
S a =200 mils
/, =12.30 mils, s - 6 mils
s=5 mils
-
A e= 719.40 mils
'-■*
Qo=439, Q l =9.2
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‘ ......’ simulation, ‘ — ’ experiment
Figure 2.7
The experimental and the simulation results o f the
11.50-12.30 GHz double-tuned microstrip band pass filter.
Fig. 2.8 shows the simulation result and the experimental result o f the second filter
j^=10.73 GHz DTMBPF. This filter is used as a local oscillation filter in the drain mixer
in the following chapters.
Fig. 2.9 shows the comparison of the Touchstone simulation and the experimental
results o f the third filter operating at 11.60-12.30 GHz.
The decreased agreement
between theoretical and experimental results in the upper band may be caused by the
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‘......’ simulation
‘ — ’ experiment
Figure 2.8 The comparison o f the simulation result
to the experimental result o f the 10.73 GHz
double-tuned microstrip band pass filter.
* 2 1
REF t . t
1
dm
l o g MAO
i t . • dm/
d9_____
V
V
MAR <ER 1
2 . 4 > GH Z
N
\N
\
\
S .
V
V
A
-
w
/
STAFT
a rty
t .t t t t t t t t t
x s .tttttttM
94*
oh*
‘.......’ simulation
‘ — ’ experiment
Figure 2.9
The comparison o f the simulation result to the experimental result
o f the 11.70-12.20 GHz double-tuned microstrip band pass filter.
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. oataau
■writ
0 .0 0 0 0
st.oo
1S.00
I) —s = 1 mil, 2) -- s = 3 mils, 3) —s = 10 mils
Figure 2.10 The simulation frequency response o f the double-tuned
microstrip band pass filter varies with the coupling gap s.
. OOCSftJ
it.oo
IS.00
1) — Sa—190 mils, 2) Sa = 200 mils, 3) Sa = 210 mils
Figure 2.11 The simulation frequency responses o f the double-tuned
microstrip band pass filter varies with the tapped positions Sa.
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complicated coupling between the two resonators when coupling gap s is small for a
wider bandwidth.
Fig. 2.10 shows the simulated frequency response o f the third filter for various
coupling gap distances. The curves obviously show that the coupling gap distance
determine mostly the bandwidth of the filter. The most important thing is that the
bandwidth is not sensitive to the gap distances. More tolerance is allowed in the
prediction and fabrication of the coupling gap.
Fig. 2.11 shows the frequency responses o f the same filter varying with various tapped
position Sa. It is clear that the tapped positions have marked affects on the attenuation of
the stop- band and the ripple in the pass band. The shorter the Sa, the higher QL and the
larger attenuation in the stop band. The higher ripple is also resulted because of the
shorter Sa if the coupling coefficient k is not changed.
2.4 Multi-Tuned Microstrip Band Pass Filter (MTMBPF)
In order to have a better attenuation in the stop band, multi-tuned microstrip band pass
filter can be developed. This is achieved by inserting additional resonator elements
between the two resonators. O f course, it is very difficult to realize a filter like this
because o f the multiple resonators and narrow bandwidth. The other difficulty is that the
quality factor o f the filter is not high enough. Thus the insertion loss in the pass band is
pretty large. High-Tc superconducting surface can be used to improve the insertion
loss[40].
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Fig. 2.12 shows the filter structure and the Touchstone simulation model. The
simulation results o f a 7-pole MTMBPF at frequency 1.8 GHz band is shown in Fig.
2.13. The improved stop band attenuation is resulted.
a) The structure o f a multi-tuned microstrip band pass filter.
fsi*| |S2i Itr V -r sT l
ten
Isii
b) Simulation model o f multi-tuned microstrip band pass filter.
Figure 2.12 The structure and the simulation model o f the multi-tuned
microstrip band pass filter.
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'j'j
n
u
Figure 2.14 The simulation result o f the 1.85-1.87 GHz
multi-tuned microstrip band pass filter.
2.5 Conclusions
The microstrip filter without loaded lumped capacitors based on the double-tuned
resonant circuit has been presented. Instead o f working on the tedious multi-mode design
method, one can use simple equations developed in this work and several minutes
Touchstone simulation to design a narrow band pass filter accurately.
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Chapter 3
A Modified I-V Characteristics Microwave
Nonlinear Model for HEMTs and MESFETs
3.1 A New Microwave Nonlinear FET Model
Analytical or real ‘physical’ FET models have only been partly successful because of
the complexity of the FET, especially in the large signal and strong nonlinear operation
such as a mixer. Although two-dimensional analysis of the FET’s channel [22][41]and
charge control model[42] are the most accurate way to model a real FET, it is too slow
and complex for use in computer-aided design. Empirical models have been more
practical and successful.
The earliest models of GaAs MESFETs were developed to improve the general
understanding of the operation o f these devices. Eventually, the goal o f developing
models for use in circuit simulation became an important concern, and FET models were
developed first for use in the well-known circuit simulator, SPICE. The limitations of
these early models became evident, and much work was devoted to their improvement.
At present, the most widely used models are those of Curtice[43], Materka, Statz, and
Rodriguez. Those models were originally developed for silicon based FET. The
dependency o f drain current on the gate voltage is described according to the square law.
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This is not good enough to describe the GaAs based MESFET or HEMT. Especially the
derivatives o f the drain current of these models may have considerable error.
Among many models[44][45][46][47], Angelove’s model [23] is a typical successful
model for HEMTs. The drain current is modeled based on the observation of the first
derivative o f the drain current or the transconductance structure being in “bell” shape.
There is, in one sense, not much difference among the those FET models: all use the
same or almost the same circuit topology, and all attempt to produce the same set of I-V
and C-V parameters. Fig. 3.1 shows the circuit topology used in these models. The
equivalent circuit has five nonlinear elements: 0 ^ , 0 ^ , Id that are controlled by
and
V , and two diodes. The transconductance gm(/) is a time-varying function o f the LO
signal in a mixer. Rt and Rd are primarily ohmic-contact resistances in the source and
drain o f the FET. Rg is the metallic contact resistance of the FET at the gate and /?, is the
resistance o f the channel between the gate depletion region and the source o f the FET.
The diodes Dx andZ)2, representing the gate to channel Schottky junctions, have little
effect as long as the voltages across either o f these diodes do not exceed their threshold
voltages (about 0.5 V). Indeed, when one speaks o f a FET ‘model’, it usually refers not to
the equivalent-circuit topology, but to the mathematical expression that models the FET’s
I-V characteristics.
The merits o f different FET models are probably the most contentious subject in the
area o f nonlinear circuit analysis[48][49][50]. Yet, in spite of very strong opinions about
the advantages o f various models, almost all seem to work at least acceptably well for
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certain applications. For instance, all the models can be used to predict a mixer’s basic
parameters o f conversion loss (gain), and port impedance with certain accuracy. The
Oqd
Cqd
Cd —
Oqd
2
Figure 3.1 Large signal equivalent circuit o f a FET.
reason for this paradoxical situation is that in well-designed active FET mixers, the
fundamental-frequency component of the pumped FET’s transconductance is by far the
dominant factor affecting conversion gain. Virtually all other elements in the FET’s
equivalent circuit can be acceptably approximated as single-valued, linear ones.
The merits o f the four models in the ohmic and saturation regions were compared by
[24]. The conclusions derived from the comparison of the four nonlinear MESFET
models developed by Materka, Statz, Curtice, and Rodriguez can be summarized as
following.
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a).The errors are significant for all the models when the gate bias V&0 is near the pinch
off voltage at large drain bias.
b).The errors are smallest for all the models when the gate bias is near V I 2.
c). In the ohmic (linear) region, the advantage is retained by the Meterka’s model. The
Statz’s model produces the lowest accuracy. This is followed by the Curtice’s model that
is on the average 40% more accurate than Statz. The Rodriguez’s model is slightly better,
producing a 50 % increase in accuracy over Statz. The Meterka’s model produces the best
results showing on average a 62% improvement in accuracy over Statz.
Condition a) results in significant error for designing a gate mixer because the mixer is
biased at high drain voltage and near gate pinch off voltage. Thus the difficulty of
modeling o f the gate mixer is limited in MMIC applications where the simplicity and
production volume are required.
No matter which one of the four models is used, the relationship between drain current
I d and the gate intrinsic voltage Vg is always described by the well known quadratic law
(3.1)
where Vp is the pinch off voltage o f a FET. The gate intrinsic voltage V
is the voltage
across the gate capacitance. The square law is only basically suitable for a silicon FET. It
is still reasonably accurate for a MESFET in the saturation region. When (3.1) is
compared with the experimental I-V characteristics o f GaAs MESFET and a HEMT,
however, the behavior o f I d as a function o f Vg is only poorly represented by (3.1). In
fact, quadratic law (3.1) is not satisfied in the ohmic region and as well as all regions of a
HEMT. Even the most fancy, complicated model[51] still gives considerable error in the
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ohmic region. The behavior o f I d as a function o f Vp follows a hyperbolic tangent
function. Thus the transconductance is in a “bell” shape.
The reason for the “bell” shaped transconductance is that the rate of increase in drain
to source current with increasing dc gate bias for a HEMT declines significantly at a bias
level above -0.3V[25]. This corresponds to the onset o f conduction via the parasitic
MESFET within the HEMT structure. In other words, if the applied bias to the gate is not
sufficient to deplete the AlGaAs layer completely[52], a conduction path between the
source and drain is developed through this layer.
In the ohmic region o f a MESFET, the rate o f increase in drain current decrease with
increasing gate voltage. This is due to the electron speed not being at the saturation speed
in the channel. Thus the current is limited by the potential difference between the drain
and source. Therefore, the transconductance is again the “bell” shaped.
To predict some o f the important performances o f a HEMT such as intermodulation
products o f a mixer, in addition to the dc I-V characteristics, their first and higher
derivatives have to be modeled correctly. The four models obviously are only based on
modeling the I-V characteristics o f a FET itself. The modeling of the derivatives becomes
very poor especially for a MESFET or a HEMT because the square law is not applicable
for GaAs based devices.
The “bell” shaped behavior o f the first derivative o f the I-V characteristics o f a
HEMT was observed by [23]. The hyperbolic tangent function for the drain current
describes the gate voltage dependencies and its derivatives well. The drain current is
given by[23]:
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Jd = l Pk [1 + tanh(tpa)](! + XVd) tanh(«^rf)
(3.2)
where, subtracting the contribution from the output conductance, I pk is the drain current
at which the maximum transconductance occurs. The drain voltage dependency in (3.2) is
the same as those in the Statz and Curtice models. <pa is a power series function centered
at Vpk with Vg as a variable i.e.
(3.3)
k
where
is the gate voltage for maximum transconductance. Ak’s are the coefficients of
the expansion.
Fig. 3.2 shows the plot of the transconductance resulted from (3.2). The starting point
o f (3.2) is modeling of the first derivative of the drain current o f a HEMT instead of
modeling drain current directly.
Transconductance vs. gate dc bias
_ 100
3
-1
-0.5
0
Gate d c bias (V)
Figure 3.2 The typical “bell" shaped structure o f
transconductance o f a HEMT.
63
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There are some limitations in (3.2). First of all, the maximum drain current is only two
times o f I pk. For some HEMTs, the maximum drain current could be more than twice
I pk. Second, I-V characteristics of a HEMT was only modeled by [23] forVd > 0.
In this work, a new nonlinear model which better describesthe I-V characteristics of a
HEMT or a MESFET is presented. The new equations are written as:
= r Pk
tanh[4lr(Ff -
Id = I
where I pk and
at
il + A 2 tan h [^,(rg - ^ ) ] } a r c t a n ( a r j
V pk
V p0
- XVd)] arctan(arFrf)
Vd > 0
Vd< 0
(3.4)
have the same meaning as those in (3.2). Vp0 is the pinch-off voltage
V. Again, Ax and A2 are parameters that depend on the transistor.
The
transistor parameter A2 is introduced in (3.4) to describe the ratio of the maximum drain
current to I pk .
The gate to source and gate to drain capacitances Cp and
can be modeled by [23]
Cg, = C ^ l + t a n h ^ - 0 .0 4 8 ^ ) ] [ l + tanh(0.4^)]
C f - C m l 1- tanh(055F(&)][l + ta n h ^ A S ^ )]
where CpQ and
(3.5), Cg,,, or
(3.5)
are the gate and drain capacitance at zero voltages. According to
o can be determined by the measured S-parameters at a given bias.
In Vd < 0, only hyperbolic tangent is used to describe the dependence o f the drain
current to the gate voltage. X is introduced also for most FET/HEMTs. Vp then decreases
with decreasing Vd when Vd < 0. In other words, the I-V characteristics
symmetrical for the two regions, Vd < 0 and Vd > 0.
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are not
Arctan(aVd) represents the dependence o f the drain current on the drain voltage. This
introduces several advantages: better fitting o f the drain current versus drain voltage
without introduction o f the slope term l + AVd; The drain resistance R& that used to be
difficult to determine theoretically is now easier and more accurate to predict.
A<-> 4 2, X, a, and a r can be determined by fitting the measured I-V
characteristics o f a FET at different gate and drain biases. A good calibrated curve tracer
or a semiconductor parameter analyzer is essential for measuring the I-V characteristic of
a transistor. Also the performance o f a transistor test fixture must also be taken into
consideration. For example, lead resistance may introduce an intolerable measurement
error for a large-size device. Instability and/or relatively low-frequency oscillations that
often take place in a high performance device, are quite often occurring, especially at
higher drain voltages. These oscillations cause the drain current to decrease with
increasing drain voltage. In other words, the measured I-V characteristics displays
negative resistance.
In this work, HP85041-80015 microwave test fixture and HP 4145A Semiconductor
Parameter Analyzer are used to measure the I-V curves of a HEMT.
Fig. 3.3 shows the measured I-V characteristics o f a NE33284A HEMT for both Vd<0
and Vd >0. In the region of Vd <0, there is a parasitic MESFET due to Vp varying with Vd.
Fig. 3.4 shows the charge distribution for a FET operating in Vd >0 and Vd <0 regions.
For Vd >0, at very low drain-to-source voltages (Fig. 3.4(a)), channel electrons move at a
velocity proportional to electric field strength. The gate depletion region is nearly
symmetrical and the drain current is proportional to the thickness of the channel. As the
65
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drain voltage is increased, the potential between the gate and channel becomes greater at
the drain than near the source end, and the depletion region therefore becomes wider near
the drain than near the gate (Fig. 3.4(b)). At higher reverse gate voltages and higher
drain-to-source voltages, the depletion region is relative wide and the channel thickness is
narrow, the pinch-off occurs at the channel near the drain (Fig. 3.4(c)). The electrons
move at saturated velocity. As drain voltage is increased further, the electric field
becomes stronger throughout the channel, the depletion becomes more distorted, and the
point where electrons reach saturated drift velocity moves toward the source. Eventually
all the electrons move in saturated velocity throughout the channel. For Vd <0, the
depletion region is greatly reduced near the drain end (Fig. 3.4 (d)). The drain current
increases since the channel thickness increases. The channel pinch-off voltage is also
determined by drain-to-source voltage. Higher reverse gate-to-source voltage is needed to
“pinch-off’ the channel. This pinch-off voltage decreases with decreasing drain-to-source
voltage. Fig. 3.5 shows the energy band diagram o f a conventional n-AlGaAs/GaAs
HEMT. Similar to a MESFET, a depletion region is developed in the AlGaAs layer. The
difference here is that for a normal operation of the HEMT, there is no channel in the
AlGaAs layer. Instead, the sheet carrier concentration n, in the 2-D electron gas layer is
controlled by the application o f a potential at the gate. For Vd <0, the depletion region is
greatly reduced and the drain to source current increase significantly and even there is a
parasitic channel created in the AlGaAs layer. The pinch-off voltage thus is also
determined by the drain-to-source voltage.
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GRAPHICS
PLOT
ID
<m A )
so. oofZI
-flO. OQ
- 1. 300
.
1 000
VOS
Figure 3.3 Measured I- V characteristics o f NE33284A HEMTfor both Vd<0
and Vd >0.
Vds*Q
Vds-0.5V
Vgs
itn
""BuHeT"
Substrate
Substrate
(a)
(b)
Vds-3V
Vds<0
Vgs
£
i.
Buffer
Butfer
Substrate
Substrate
(C)
Figure 3.4 A FET works in
(d)
>0 and
<0.
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n-AlGaAs
GaAs (Undoped)
Doped
Depleted
Undoped
Figure 3.5 The energy band diagram o f an n-AlGaAs/GaAs heterostructure system.
The rest of the parameters in (3.4) can be determined by fitting the I-V characteristics
o f the HEMT using the measured data. They are discussed in the next section.
3.2 Curve fitting of I-V characteristics
The measured I-V characteristics obviously contain the parasitic drain and source
resistances. However, those resistances are not includes in (3.4). Those parasitic
resistances Rs and Rd can be measured at dc levels[53]. So the effect of parasitic
resistances Rs and Rd has to be eliminated from the measured I-V characteristics first.
The following I-V characteristics is based on a NE33284A HEMT. The measured
pinch-off voltage is -0.8V. The measured I-V characteristics is shown in Fig. 3.3.
68
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Obviously, the measured drain current versus drain-source voltage shown in Fig. 3.3
includes the parasitic resistances. The effects of the parasitic resistance on the drain
current and drain voltage are taken into account by the following equations:
K=rd,-id(*d+Rs)
where Vg, Vd are the intrinsic gate and drain voltages, Vp ,
are the gate and drain
voltages which include the parasitic resistance effects. Rs and Rd can be obtained from
the measured S-parameters o f the FET and Fukui method[53].
The goal o f fitting the theoretical I-V characteristics to the measured one is to adjust
the parameters I pk, Ax, A2, and a or 1 ^ , Alr, X, and a r in (3.4) so that the following
objective function is minimized:
(3.6)
where I d lh and I d ex are the theoretical and the measured drain currents at m gate bias
points and n drain bias points, respectively. N,=m x n is the total number o f sampling
points. This objective function is subject to the constrains,
I pk>0, Ax>0, A2>0, Vpt <0, and a>0
and
Air>0, X>0, Vp0 <0, and a rX)
(3.7)
69
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Start
Input: w-number o f variables, Af-the number o f points to be stored,
the boundaries o f the variables, and then defining the initial domain V.
Chose N points randomly at V, consistent with the constraints, and
evaluate function value at each point. Store the coordinates and
function values in an N x (n+1) array A.
Determine the stored point, M, which has the greatest function value, fin
Chose randomly any n+1 distinct points R l, R2
Rn+1, from the
set Af, o f the stored points. Determine the centroid G o f the n points,
R l, R2, ... , Rn+1. Then make the next trial point P such that P=2GRn+1
Is the position o f P consistent
with the constraints?
Evaluate the value o f the function P, fp
Is fp<fm?
Replace the coordinates and function value o f
M by those o f P in A
Does the total evaluation times exceed the specified ?
Print the minimum function values
and coordinates
Stop
Figure 3.6 Flow diagram o f CRS
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and I pk are
The upper boundaries o f those parameters can be estimated. Generally,
in the range of tens mA for a small signal transistor.
Many optimization methods can be used to perform the optimization o f (3.6). These
are generally based on two methods. The gradient method, such as that o f Powell method,
involves the evaluation of the function and its derivatives at each iteration. This method
usually converges very fast but quite often is only effective for the local minimum. On
the other hand, direct methods, involving only function evaluations, are generally less
efficient than the gradient method but because they do not require the calculation of
derivatives are simpler and applicable to the optimization of non-differentiable functions.
Typical direct methods are those of Hooke’s and Jeeves’s random search, etc.
Controlled random search (CRS) method[26] is also an excellent optimization tool
for global optimization with n-space unknown variables. This method is used in the
curve fitting o f the I-V characteristic of a HEMT. Fig. 3.6 shows the flow diagram o f this
method.
An initial search domain V is defined by specifying limits to the domain o f each o f the
n variables and predetermined number N o f trial points are chosen at random over V
consistent with the constraints. The function is evaluated at each trial and the position and
the function value corresponding to each point are stored in an array A. At each iteration
a new trial point, P, randomly is selected from a set of possible trial points whose
positions are related to the configuration o f the N points currently held in store. The
selected point P satisfies
P = 2 G - Rn+l
(3.8)
71
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where G is the centroid o f
out o f /?, ,...R„+lrandomly selected points from N.
CRS is intended to find the global minimum instead o f convergence speed. It
guarantees to find the global minimum by trading of the convergence speed. The speed of
a modem computer is so fantastic so that one forgets the converging time issue.
The CRS program for curve fitting o f the NE33284A I-V characteristics for Vd >0 can
be found in Appendix A3-1.
I-V characteristics of NE33284A
70 -
60 50 i
0
— Meterka
New
- Experimei
0.2
0.4
0.6
0.8
1
Vds (V)
Figure 3.7 The curve fitting result o f the new model.
Fig. 3.7 shows the result of the new model after 20,000 CRS function evaluations with
E0 o f 0.093. The figure also shows the results of Meterka’s model after 20,000 CRS
function evaluations with E0 o f 0.257. It can be seen that the agreement between the
fitted curve and the experiment for the new model is not only good in the saturation
region but also very good in the ohmic region. The corresponding parameters o f the new
model in (3.4) are
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/p* =24.53 mA, 4=4.00, 4=1.088, a=9.954, KM=-0.301V
(3.9)
The drain current o f the Meterka’s model is given by
h -
tanh(^ _ ay ‘_ yVd ) U + W
(3.10)
The parameters for the Meterka’s model after 20,000 CRS function evaluations are
/* m=70.10 mA, a =4.369, ^ = -0 .7 7 0 V, y = 0.035, >.=0.242
(3.11)
The E 0 o f the Angelov’s model [23] is 0.123 after 20,000 function evaluations. The
parameters o f the Angelov’s model are:
7^=28.941 mA, 4=4.69, a=7.431, F,t =-0.304V, X =274
(3.12)
Fig. 3.8 shows the comparison of new model to the Angelov’s model. The E 0 is 0.119
if arctan(aFrf) instead o f tanh(aFrf)(l+ XVd) in Angelov’s model.
The arctan(af^) is better than tanh(aVd)(l + AVd ) for describing the drain current
versus drain voltage. In addition to having one parameter less, arctm(aVd) offers better
modeling in lower drain dc bias region.
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I-V characteristics of NE33284A
.NEW
•Angelov
Measured
70
60
Vgs=0V
50
-0.2V
<
40
E.
-0.3V
<0 30
•Q
20
10
0
0
0.2
0.4
0.6
0.8
1
Vds (V)
Figure 3.8 The comparison o f new model to the Angelov’s model.
Fig. 3.9 shows the comparison between the measured and new model o f drain currents
versus the gate bias at different drain biases. The dashed lines are for the new model and
the solid lines are the measured values. The agreement between the measured and
modeled characteristics is very good.
Fig. 3.10 shows the comparison o f the Meterka’s model and the new model in the
ohmic region. The solid lines are the measured I-V characteristics. The dashed lines are
the Meterka’s model after 20,000 function evaluations with the E 0 of 0.203. The dots are
74
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The drain current vs. the gate voltage
Ids (mA)
80 '
60 -
— Modeled
— Measured
Vds0=0.8V
^
VdsO=0.5V
Vds0=0.3V
Vds0=0.1V
-
0.8
-
0.6
-0.4
-
0
0.2
Vg* (V)
Figure 3.9
Comparison o f the measured and
modeled 1^ vs.
at different
for the new model after 20,000 function evaluations with E0 o f 0.048. The Angelov’s
model provides E0 o f 0.120 after 20,000 function evaluations. Significant improvement
o f the new model over the Materka and Angelov models in ohmic region is observed.
The parameters o f the transistor in the ohmic region are:
7^=25.46 mA, 4=3.47, 4 = 1 .2 0 , a=8.995, Vpk=-0.3QQV
(3.13)
Fig. 3.11 shows the measured and modeled I-V characteristics of NE33284A in full
region. The agreement between the measured and modeled I-V characteristics is very
good.
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I-V characteristics of NE33284A in linear region
60 '
— Meterka
New
Measured
Vgs=-0.1V
40 -
-0.2 V
<
E 30 .
■too
~
20
-0.3 V
*
0
0.1
0.3
0.4
0.5
Vds (V)
Figure 3.10 The comparison o f the Meterka’s model and
the new model in the ohmic region.
The corresponding parameters are:
I pk=24.531 mA, 4=4.00, 4 = 1 .0 8 8 , a=9.954, ^ ^ 0 .3 0 1 V
Vd > 0
(3.14)
7^=74.251 mA, 4,=1.518, a r=9.346, Vp0=-Q.556V, A-=1.00
^ < 0
(3.15)
The parameters given by(3.13) in the ohmic region are a slightly different from that of
(3.14) in the full region even though the same transistor is used. This is reasonable
because the CRS process minimizes the total £ 0 by adjusting these parameters. Besides,
the model is an empirical expression any way. But it does describe the dependency of the
drain current on the gate and drain voltages accurately.
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Comparision of the modeled and measured I-V characteristics
FET: NE33284A
Modeled
Measured
-120 1
Figure 3.11 The comparison o f measured and modeled I-V
characteristics o f the NE33284A..
Fig. 3.12 shows the comparison of the modeled and measured I-V characteristics of
NE71084 GaAs MESFET with the following modeled device parameters:
I pk=23.45 mA, 4 = 2 .0 0 , 4 = 1.08, a=5.04, Fpi=-0.28V
Vd >0
(3.16)
7^=257.2 mA, 4 r=0.36, a r=2.51, Fp0=-0.81V, X=0.73
^< 0
(3.17)
The agreement between the modeled and measured results is again very good.
77
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The measured and modeled I-V characteristics of NE71084
Vgs=0V
-0.2V
-0.4V
-1.5
0.5
1.5
2.5
Vds(V)
-60 -
-100
Modeled
Measued
-
Figure 3.12 The comparison o f measured and modeled I- V
characteristics ofNE71084.
3.3 Conclusions
In this chapter, a new I-V characteristics for a HEMT is presented. When Meterka’s,
Angelov’s and the new models are compared in low Vd (ohmic)region, the Meterka’s
model produces the lowest accuracy with the least square error E0 o f 0.203. This is
followed by the Angelov’s model with £ 0=0.120. The new model developed here offers
the best accuracy with E0=0.048. For
Vd>0 o f the saturation region, £ 0=0.257 for
Materka’s model, E0=0.123 for the Angelov’s model, and £ o=0.093 for the new model
are resulted. Moreover, the new model is also suitable for modeling I-V characteristics of
a GaAs MESFETs. The first order derivative is better represented by the new model.
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Chapter 4
The Volterra-Series Analysis And Measurement(VAM) Of FET
Gate I-V Characteristics For Intermodulation Prediction
4.1 Introduction
Volterra-series analysis [65][66][67]is the most efficient and practical tool for
determining the intermodulation products in small signal and quasi-small signal FET
circuits. The I/V characteristics o f a FET mixer can be characterized by a Taylor-series
expansion in the vicinity o f the dc bias points. The drain current I d (Vg) can be expressed
as
f A r g)=al(rg - V gQ) + a2(Vg - V g0) 2 + a3(Vg - V g0) i + -
(4.1)
where a, is equivalent to the linear transconductance, a2 is related to the second order
intermodulation component, a 3 is related to the third order intermodulation component
and so on. Vg0 is the intrinsic gate dc bias.
A lot o f theoretical and experimental models have been proposed to predict and
measure the coefficients in (4.1). Low-frequency RE measurement method is generally
used[27].
Fig. 4.1 is the equivalent circuit of a FET at low frequencies in the VHF band used by
[27]. However, the determination o f the input RF signal power in [27] is questionable.
79
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The measured input power level is not really the available power of the source which will
be delivered to the FET because o f the differences in the impedances between the
spectrum analyzer and the input impedance o f the FET at low frequencies. The spectrum
analyzer impedance is generally 50 ohms and the impedance o f the FET is pretty high at a
frequency o f 50 MHz. Also, the harmonics power levels at the output load R L have to be
determined accurately because the reading o f the spectrum analyzer is not the real power
on
R L. The accuracy of the measurements and calculations in [27] are also very
approximate.
Rds
RL
Rs
_L S
Figure 4.1 The equivalent circuit o f a FET valid at VHFfrequencies.
In this thesis, a more accurate measurement model is developed. The equivalent circuit
o f the FET at low RF frequency is the same as in Fig. 4.1. R L is selected to be small
80
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enough so that the drain current passing through R& can be neglected. A high precision
value resistor RL o f 3.9 ohms is used. The main idea is that the rms. V
of input RF
signal and the rms. Fj o f the first order output signal are measured directly by a scope.
Thus, the voltage Vg and the first order coefficient a, can be determined very accurately.
Also the power levels o f the harmonic components on R L can be obtained according to
the measured Fj and readings o f the analyzer at different harmonic frequencies.
4.2 Theoretical prediction of a „ a 2, a „ ...
Before the description o f the measurement, the theoretical prediction of a„ a2, a 3,
can also be made from the new model developed in chapter 3. For Vd > 0, using (3.4)
= I Pk A
(4.2)
{1- tanh2K (Vg0 - Vpk)]} arctan(aF„)
° 2 2 dVl
= - I pkA?A, tanh[A,(Fg0- F ^ H l - t a n h 2^ , ^
- F />t)]}arctan(aF</)
(4.3)
6 cv:
= - 7 l pkA lA 2 { l- ta n h 2[ 4 ( F g0 - Fpt)]}{1-3tanh2[^ ,(F g0- F ^ a r c t a n ^ F , )
81
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(4.4)
for V. < 0,
Q .r=
£ i
y,=y„
= [dssAn { l-ta n h 2[ ^ r ( ^ 0 -^po - ^ ) ] } a r c t a n ( a r^ )
1
° 2r 2 * F 2
(4.5)
= - I ^ A l tanh[Alr(Vg0- V p0- X V d)]
■{l~tanh2[Alr(Vg0- V pQ- AVd)]}aictan(aVd)
(4.6)
° 3r 6 dVl
=- g
0-~ t e h 2[AXr(yg0 - Vp0 - XVd)]}
•{1 —3 tanh2[AIr(Vg0- V p0 - /l^ ) ] } a r c ta n ( a r^ )
(4.7)
The parameters o f NE33284A HEMT are
I pk=24.531 mA, 4=4.00, 4= 1.088, a =9.954, Vpt=-0.300V,
Vd > 0
I to =74.251mA, 4 r=l .518, a r=9.346, F,0=-0.556V, A=1 .00,
VA < 0
All the a ,, a 2, a 3, ... can be calculated by substituting the parameters in to (4.2)~(4.7).
82
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4.3 Description of the Measurement Technique
Fig. 4.1 shows the equivalent FET circuit when the RF frequency is low. The
measurement set-up is shown in Fig. 4.2 that a fundamental frequency o f 4.5 MHz is
used. The drain is terminated in the resistance R L with R L« R ds. Thus the currents in
RA can be reduced to the point where its effects are negligible. On the other hand, the
value o f R l should be as small as possible while still allowing harmonic output
components to be observable on a spectrum analyzer. The RF signal as pointed out in
[68] must have very low harmonic itself, 90 dB or more below the desired level. Three
4.5 MHz ceramic filters are used to accomplish this task. This is the main reason why
frequency o f 4.5 MHz is chosen. The second advantage o f this frequency is that the cable
losses are negligible. The RF performance of the HEMT can still be measured at 4.5 MHz
because 4.5 MHz is far above the frequency dispersion off-set point [69][70][71]. The
frequency
dispersion
is
the
device
characteristics
include
output
resistance,
transconductance, and output capacitances shift as the frequency increasing above the
dc[72] [73] [74] [75] [76] [77].
The main principle o f the measurement is that the rms. Vv o f the input signal
Vgj (0 = V2 V&cos(<0,0
(4.8)
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and the rms. Vx o f the first order output are measured directly by a scope. Vx here includes
the distortion harmonic components. However, the power levels o f the 2nd and higher
harmonic products are usually much lower than that o f the first order. It is safe to assume
that the measured output voltage is the rms. Vx of the output first order signal.
With the harmonic power level measured by the spectrum analyzer and the known Vt
and Vx, every harmonic component current can be determined.
According to Fig. 4.1, the voltage Vg across the gate capacitance
V ^V ^I^R ,
is
(4.9)
and the first three harmonics of the drain current I vX_} are
a xK
Ivx=7rfr
( 4 -1 0 )
(4U)
-& S &
(4i2>
Substituting
/
JL
(4.13)
rl
into (4.10) gives a , :
K
(414)
As shown in Fig. 4.2, the spectrum analyzer is connected across the load R L to monitor
the output harmonics (The spectrum analyzer has to be disconnected when measuring the
84
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Vx in order to eliminate the current division by the analyzer). However, the spectrum
analyzer’s reading
is not the power
consumed on the load, i=l,2,3,.... The
relationship between the P^ and PM is fixed regardless o f the different dc biases or the
harmonic components because the analyzer actually is a pure resistive load shunting to
the R l at 4.5, 9.0, 13.5, ... MHz.
The 5 =PiL-PUt can be determined from the measured amplitude of the first order
output Vx, PXa, and R L:
(4.15)
The power levels o f every harmonic on RL without connecting the spectrum analyzer
can then be obtained from
(4.16)
The every harmonic current is then
(4.17)
Substituting (4.16), (4.17), and (4.14) into (4.11) and (4.12) gives
(4.18)
(4.19)
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The computer program for modeling a ,, a 2, and a} based on (4.1) to (4.4) and
experimental determination o f those parameters based on (4.9) to (4.19) are given in
Appendix A4-1.
4.4 Experimental Results
This method was used to determine the harmonic coefficients o f a packaged
NE33284A HEMT at all gate and drain biases. The dc I-V characteristics that were
developed in chapter 3 are used to model the theoretical harmonic coefficients. The small
signal “cold” equivalent circuit parameters were determined by adjusting the circuit
elements values until good agreement between calculated and measured “cold” Sparameters ( f ^ 0=0) was obtained. Thus, the source parasitic resistance Rs was
determined. The transistor was installed in a HP 85041-8005 test fixture with the
shunting resistance RL o f 3.9 ohms. Three 4.5 MHz ceramic band-pass filters were
connected in series with the input o f the FET in order to filter out the harmonics o f the
4.5 MHz source. The peak-to-peak amplitude of the input signal was set at 70 mV.
Fig. 4.3 ~ 4.6 show the measured peak-to-peak amplitude VXpp (Vlpp has to be
measured by disconnecting the analyzer) of the output first order and the harmonic power
level readings on spectrum analyzer. Those readings, as described in (4.16), are related to
the harmonic power levels on R L. (4.18) and (4.19) do not indicate whether a 2 and a 3 are
positive or negative.
However, the sign of a2 can be obtained from the observation of
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the derivative o f curve P2a in Fig. 4.3. The minimum o f P2a (a2=0) was observed at
around ^ = - 0 . 3 V. Thus, a 2<0 at
and a 2>0 at F ^ c-O JV . Similarly, the sign
HP 6281A
PWR Supply
VgsO
SMA-7mm
Adaptor
7mm-SMA
Adaptor
Test
PC Board
HP 85041
-8005 .
Test Feature ^
HP 3314A
Function
Generator
HP54601A
Scope
Ro=47 Ohms
R= 3.9 Ohms
Co=1uF
1%
C1= 1uF
HP 8593A
Spectrum
Analyzer
C2=47uF
C3=0.01uF
Figure 4.2 The setup used to perform low-frequency
measurements o f RF harmonics.
of n 3 can be obtained from the observation of the derivative of a2 curve. P3a reaches its
minimal (a 3=0) at around VaO=-0AV and -0.58V. Thus, a 3<0 for -0.58<Fgj0<-0.1V and
a 3>0 for ^ < - 0 .5 8 V and >-0. IV.
87
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Outputs
V1pp(mV)
-20 _ (dBm)
PI a (dBm)
P2a (dbm)
P3a (dBm)
V1pp(rW)
100
-
Vfl*0(V)
Figure 4.3 VXpp, PXa, P2a, P3a vs. the gate biases at Vjsq-0 .5 V.
Outputs
V lppm V )
Pla(dBm) |
PZa (dbm) j
P3a (dBm) |
Vlpp(trV) j
I
VgsO(V)
Figure 4.4 Vlpp, PXa, P2a, P^ vs. the gate biases at
=0.8 V.
88
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Outputs(dBm)
V1pp (mV)
- 35
- 30
-10
0
-50 _
r
25
-
20
-
10
-70 .
-90 .
-PIa (dBm)
- P2a (dbm)
-P3a (dBm)
-V1pp (mV)
-110
-
0.8
-
0.6
-0.4
-
0.2
0
VgsO (V)
Figure 4.5 Vlpp, PXa, P2a, P2a vs. the gate biases at VM = / V.
Outputs
V1pp (mV)
- 35
.P Ia (dBm)
. P2a (dbm)
-P3a (dBm)
.V1pp (mV)
100 I
-120.Q..8
Figure 4.6 V
G0
VgsO (V)
P». P:, • Pu vs. the gate biases at K * “2 V
Fig. 4.7-4.9 show a x, a2, and a3 modeled by (4.1)~(4.4) and VAM modeled results at
F^o=0.5V. The theoretical a, is the transconductance at DC and the VAM modeled a, is
89
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at the RF frequency. Thus, the frequency dispersion of a, is not obvious at low drain dc
bias.
a1
First Order Coefficient a1
(mA/V)
150 .
v
100 _
Vdso=0.S V
e
--
V
\
•
50 .
0 ------------
-0.8
-0.6
-0.4
. . . x - . - from l-Vmodeled
-0.2
m
0
VgsO (V)
VAM modeled
Figure 4.7 The VAM modeled and from I-V modeled
results o f a, vs. dc gate biases.
The agreements between the I-V modeled and VAM modeled results o f a2 and a 3 are
not tod perfect. The main reason of the error is believed to be the I-V characteristics
model itself. It is always difficult to model higher derivative of the I-V characteristics
accurately.
Fig. 4.10-4.12 show a x, a2, and a 3 modeled by (4.1)~(4.4) and VAM modeled results
based on (4.9)~(4.19) at V ^ =2V. Surprisingly, the frequency dispersion is not evident for
the NE33284A HEMT.
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2nd Order Coefficient a2
a2
(mA/VA2)
|
300 .
Vdso=0.5 V
200 _
.x - - . v
100 .
VgsO (V)
-100-Q..8
-0.6
-0.4
#
\-& .2
-200 .
-300 -
g
y . . x ,-'x
. . . X- - - from
9
I-V Modeled
VAM modeled
Figure 4.8 The VAM modeled andfrom I-V modeled
results o f a2 vs. dc gate biases.
.*?x- - - from I-V modeled
(mA/V*3)
200 _
0
-q.8
-200 -400 _
#
a
VAM modeled
VdsO=0.5 V
-0.6
-.0.4
*
X
-0.2 a
_
V g#0 ^
I
Jf
'‘X'’’
3rd Order Coefficient a3
Figure 4.9 The VAM modeled andfrom I-V modeled
results o f a 3 vs. dc gate biases.
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ai
Flrst 0rder Coefficient a1
(mA/V)
200 -
Vdso=2.0 V
150 m
t
-
50 -
0;
,
m .'* '
-0.8
-0.6
.
•’
y
•
* VgsO(V)
_____
-0.4
-0.2
. .-x --- FRMI-Vmodeled
0
s
VAMmodeled
Figure 4.10 The VAM modeled and from I-V modeled
results o f a, vs. dc gate biases.
a2
2nd Order Coefficient a2
(m A/VA2
800 200 -
Vdso=2.0 V
* - '* '* > ,
1°o
-100.&8
{'
|
* • y
-0.6
-0.4
. . . x - . . from l-V modeled
Vg8° (V)
'>,-0.2 •
a
9
I
VAM modeled j
Figure 4.11 The VAM modeled andfrom I-V modeled
results o f a 2 vs. dc gate biases.
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a3
(mA/VA3
3rd Order Coefficient a3
Vdso=2.0 V
240 _
o
-
-200
0.8
-
0.6
*
0
VgsO (V)
-400 -600 -
. . . x- - - from I-V modeled
m
VAM modeled
Figure 4.12 The VAM modeled andfrom I-V modeled
results o f a3 vs. dc gate biases.
4.5 Conclusions
In this chapter, an experimental model was developed to measure the harmonic
coefficients o f the Volterra-Series analysis o f gate (base)
I/V characteristics of a
transistor at low RF frequency band. The harmonic coefficients are determined by the
VAM method for the first time through the all gate and drain dc biases. The gate and
first-order output voltages were measured directly instead o f measuring the input power.
The frequency dispersion was found to be not evident for a NE33284A HEMT.
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Chapter 5
FET Characterization
5.1 Introductions
Many traditional methods for nonlinear analysis o f mixers demonstrated accuracy.
These are harmonic balance technique[60][78][79][80] and quasi-static large signal
model, etc. In this chapter, FET characterization for mixers using quasi-static large
signal(QSLS) model [5][7][17][24][54][56][81] is discussed. To develop a QSLS circuit
for a mixer, the small signal equivalent circuit of the FET is determined first based on the
measured S-parameters. Then the QSLS circuit is obtained by replacing nonlinear
elements o f the equivalent circuit with large signal values under the pumped LO signal.
In small signal equivalent circuit shown in Fig. 5.1, the elements R ^ , C ^ ,
, and
g m or the drain current Id{t) are assumed to be nonlinear when the pumped LO signal is
applied at drain or at gate. Those nonlinear elements are then replaced by their large
signal values. The rest o f the elements are assumed to be the same as those in the small
signal equivalent circuit.
Frequency conversion in a gate mixer is discussed by examination o f the
transconductance g m(t) presented by the LO signal at the gate. Even “Zero” mixing
transconductance is observed at a certain gate dc bias levels for a HEMT.
Frequency conversion for the new drain mixer is for the first time analyzed by
examination o f the g m(t) based on the I-V characteristics model developed in chapter 3.
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The mixing transconductance of the new drain mixer has a maximum value at the zero dc
drain bias.
Theoretical stability o f a gate mixer and a drain mixer are analyzed based on the
average transconductance g0 of the pumped g m(t).
5.2 Small signal equivalent circuit parameters
To obtain the QSLS equivalent circuit o f a mixer, a conventional small signal
equivalent circuit is first determined based on the measured S-parameters at given biases.
Fig. 5.1 is a conventional small signal equivalent circuit of a FET. Rs and Rd are
primarily ohmic-contact resistances in the source and drain o f the FET. Rg is the ohmic
(metal) resistance of the FET gate and R( is the resistance o f the ohmic part o f the channel
between the gate depletion region and the source of the FET. Lg, Ls, Ld, Cg, and Cd are
basically the parasitic inductances and capacitances of the FET. Cp is the gate
capacitance which mainly affect the performance o f the FET.
is the capacitance
between the gate and the drain. Q is the capacitance between the channel in the drain
and the source. R ^ is the drain shunt resistance. The controlled current source I d (t) is
determined by the voltage across the gate capacitance Cp .
Many methods were developed to extract those elements of the equivalent circuit.
These are based on the dc I-V. characteristics measurement and S-parameter
measurements. It is not an easy task to predict those elements precisely because any
combination o f those elements would give the same S-parameters.
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Various methods have been developed to determine some of the elements. Fukui
approach[53] is a good starting point to estimate the gate, source and drain resistances
Rg, Rs and Rd. The parasitic elements Ls, Lg, and Ld can be extracted by the measured
“cold” S-parameters. The rest o f the elements can be extracted from the measured Sparameters at a given dc bias.
Cqd
Vc
Figure 5.1 The small signal equivalent circuit o f a FET.
5.2.1 Rs, R g,R d
The first good estimation o f the parameters Rs, Rg, Rd can be determined by Fukui
approach [53] on the dc level measurement as follows:
The forward biased I-V characteristic o f the gate-to-source junction is measured with
the drain open-circuited. The deviation in the I-V characteristic from a straight line at
high currents is caused by the voltage drop across the series resistance Rs+Rg , which can
be determined by the measured deviations o f the voltage and the current.
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This can be written as
R s + R g = - v? «L .
The voltage
current
{5A )
the gate-to-source voltage with the open drain, and the corresponding
at which the series resistance is determined is also recorded. With the source
open-circuited, the gate-drain junction is biased to the same current / y . The voltage Vgdf
is then recorded. With the drain and source connected together, The junction between
gate and channel is biased to the same current /y and the voltage, Vpd is recorded.
Then
—
+
Rd —/?22 + V^u-^22
(5-2)
R! =^f--R,Ri /(R,+RJ)
j
where
*n =
V
-V
Rn = - f——-gS—
j
(5.3)
From the measured data, /?,=!. 13 Ohms, and Rd=3.00 Ohms for NE33284A.
5.2.2 Ls, Lg , and Ld
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External inductance Ls, Lg , and Ld that do not affect the DC I-V characteristic are
extracted from the measured S-parameters at zero drain-to-source voltage ( ‘cold’ FET Sparameters)[54]. The equivalent circuit of the FET, as shown in Fig. 5.2, is much simpler.
It is more accurate to extract these elements from the “cold” S-parameters. The values of
the parasitic inductances are supposed not to vary more than one percent even with
widely varying values o f dc biases [54].
T
C|3
C-iRd
Ld
Cds
Cd
Rs
Figure 5.2
The "cold” equivalent circuit o f a FET.
Table 5.1 shows the Touch-Stone extraction results of the parasitic elements of
NE33284A transistor from the measured “cold” S-parameters at biases
—0.5V and
^o= 0-0 V.
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Figure 5.3 shows the measured and modeled “cold” S-parameters o f NE33284A. Fig.
5.4(b) is the reduced range o f the Smith chart. The agreement between the modeled and
the measured S-parameters is very good.
Table 5.1 Parasitic parameters ofNE33284A
Lg=0.4465 nH
fly=0.015 Ohms
Cr =0.11l6pf
Ld=0.5904 nH
/?rf=3.000 Ohms
Crf=0.1386 pf
£,=0.1109 nH
/?,=!. 130 Ohms
Measured S21
Measured Si 1
.5
Modeled S 11
Modeled S22
Measured S 12
.75
(a) S u ,
1
Modeled S21, S12
(b) Sl2, S2I
Figure 5.3 The measured and modeled “cold ’’ S-parameters o f NE33284A.
5.3 QSLS equivalent circuit for a gate mixer
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It is difficult to extract QSLS equivalent circuit accurately for a gate mixer since the
gate dc bias is selected near pinch-off voltage and the drain bias is in saturation region in
order to get a good conversion gain and low noise figure. Even the extraction of the
elements for the small signal equivalent circuit even has accuracy problem because of the
gate dc bias selection. The gate, drain and source contact resistance Rg, Rd, and Rs
probably change more or less when the FET works in the strong non-linear region. The
drain shunt resistance R^ also becomes very sensitive to the gate dc bias. Any change of
the gate dc bias will cause R^ change a lot. The nonlinear elements in the Fig. 5.1
becomes even more complicated when the LO large signal is applied to the gate.
5.3.1 “Hot” small signal equivalent circuit
Regardless o f the problem o f the element extraction for a gate mixer, the QSLS
equivalent circuit is still used here., After the parasitic inductances Lg, Ld, Ls in Fig. 5.1
are determined by the measured “cold” S-parameters data and the resistances Rs and Rd
by Fukui method, the “hot” small signal equivalent circuit elements can be determined by
the measured S-parameters at the desired dc bias. At this point, Lg, Ld, Ls, Rs, and Rd
remain unchanged in the “hot” equivalent circuit and the rest o f the elements are
optimized to fit the measured S-parameters. Table 5.2 shows the elements o f the “hot”
small signal equivalent circuit when the dc biases are set at F^q—0.8 V and ^<,=2.0 V.
The related Touchstone program is listed in appendix A5-1.
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Table 5.2 ‘‘Hot ” small signal equivalent circuit elements o f NE 33284A at V 0=-0.8 V
and ^ 0=2.0 V, Units: Ohms, nH, pf
£,*0.4465
Rg=0.015
4 , =3243
C,=0.0
^ = 0 .1 5 1 3
Ld=0.5904
4 , =3.000
4=0.1150
Crf=0.0023
Q = 0.1438
4=0.1109
4 = 1.130
g»= 0.010
Cgd=0.02834
5.3.2 Non-linear elements C&■and Cgd
To obtain QSLS equivalent circuit elements o f the gate mixer, several nonlinear
elements o f the “hot” small signal equivalent circuit need to be replaced under the pump
o f the large LO signal at the gate. Shorting of the LO signal and harmonics at the drain
can improve the noise figure and conversion gain[7]. The assumption that the only
nonlinear elements are
, C ^ , and gm(t) is thus reasonable.
Cg, , Cgd can be modeled by (3.5), i.e.
= C ^ l + t a n h ^ - 0 .0 4 8 ^ ) ] [ l + tanh(0.4^)]
C * = C * 0[1 ~ ta n h (0 i5 ^ )][l + tanh(0.48^)]
where
^o = 2 -0 V
^ o ~ 0-8 + Vo c o s K O
(5.3)
Fig. 5.4 shows the pumped gate total voltage(PGTV) at the LO signal peak amplitudes
o f 0.5V and 2.0V. The gate-to-source junction diode will conduct when PGTV exceed
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0.5V. This is the situation o f the LO signal amplitude of 2V, as shown in Fig. 5.4. The
PGTV remains in the form o f (5.3) after PGTV is below the pinch-off voltage Vp even
though the drain current is cutoff.
Vgs(t) (V)
,Vo=2V
o=0.5V
cot
0
10
20
Figure 5.4 The pumped gate total voltage(PGTV) at the
LO signal amplitudes o f 0.5 V and 2.0 V.
Fig. 5.5 is the results o f the calculated average of Cp and Cgd. The “average” means
the first component of the Fourier series expansion of the pumped capacitance. The
harmonics o f the capacitances will be shorted at the gate or are very small compared to
the “average” values.
Fig. 5.5 shows that
does not change too much by the presence o f the LO signal.
=0.026-0.027 p f is obtained compared to the original small signal value of 0.028 p f
even though the LO signal amplitude varies from 0 V to 2 V. Thus, the small signal value
o f Cgj will provides a good enough accuracy for the QSLS equivalent circuit. On the
other hand, Cp varies from the original small signal value of 0.1513 p f to 0.306 p f when
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the LO signal amplitude varies from 0 V to 2 V. In other word, Cp
increases with
increasing LO power levels.
0.4
Cgs
0.3
D.2
0.1
0
Vo (V )
0
0.5
Figure 5.5 The calculation results o f the average o f
and C ^.
5.3.3 Frequency conversion in a gate mixer
An ideal mixer is a multiplier, as shown in Fig. 5.6. The RF signal is a small signal of
Vs cos(a>st). The LO signal is a large signal of V0 cos(a>0t). The IF signal is usually a low
frequency single-side band signal of with a Vs cos(eos -a>0)t component. The ideal mixer
follows the multiplying principle:
K ( 0 = VSVQcos(a)st)cos(co0t)
1
= 2 ^ /o tc o s K - <y0)? + cos(6j, + 6>0)r]
(5.4)
where Vs, and V0 are the amplitudes of the RF and LO signals; cos, and to0 are the angular
frequencies of the RF and LO signals.
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V o(t)
Low P a s s
RF
IF
Rlter
LO
Figure 5.6
An ideal mixer.
Fig. 5.7 shows a simplified I-V characteristics o f a FET. The curves are divided into
two regions: linear and saturation. In early SPICE FET model, the drain current versus
gate and drain voltages are simplified traditionally as:
P iV g - V p) 2
(a) In saturation region
(5.5)
J V '- V '- V * !
(b) In linear region
Vd
Figure 5.7 A simplified FET I-V characteristics.
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By careful analysis o f (5.5) based on the “multiplying” principle o f (5.4) for a FET
mixer, one can see that in the saturation region mixing could only happen when both the
RF signal and LO signals are applied to the gate. The gate total voltage is
Vg = y* + V*c°s(a>,0 + vacos(<v)
(5-6)
Substituting (5.6) into (5.5), only (5.5a) has product term o f RF and LO signals. On the
other hand, there will be no frequency conversion in the linear region. This are the reason
for selecting the pertinent dc biases for a gate FET mixer.
With the injection o f a LO signal into drain instead o f the gate, the gate and drain
voltages o f a drain mixer can be expressed as:
(a)
V9 = Vff0 + Vs cos(<y,0
(b)
Vds=Vd]0+V0 cos(a0t)
where V ^ , and
(5.7)
are the dc biases respectively.
Substituting (5.7) into (5.5), only (5.5b) has a product term of RF and LO signals. On
the other hand, there will be no frequency conversion in the saturation region if the
amplitude of the LO signal V0 is not large enough to reach the linear region. However,
[17] predicted that the conversion gain would increase with increasing o f the drain dc bias
V^ q. This contradicts the above analysis. Later theoretical and experimental results
demonstrated that the mixing transconductance does decrease with the increase o f the
drain bias. From historical experimental results, probably based on [7], it was concluded
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that a drain mixer had not clearly better performance over a gate mixer and the gate mixer
was believed to be the best FET mixer with a high conversion gain and low noise figure.
From the product term o f RF and LO signal in (5.5b) it is obvious that the frequency
conversion will happen if the drain dc bias is selected in the linear region, since
(5.8)
l d - PVsVqcos(£u,Ocos(fiy)
This is the basic principle o f the new drain FET mixer (DM). More theoretical
investigation o f a DM can be initiated by analyzing the transconductance under the
pumped LO signal applied at the drain of the FET.
As shown in Fig. 5.1 from the small signal equivalent circuit o f FET, the controlled
drain current will vary at a periodic rate by a large local oscillator signal injected into the
drain if the biases o f the FET are properly selected.
The traditional definition o f the transconductance is
const, biaes
However, the transconductance can be extended to “extensive” definition by
(5.9)
Q-point
Here, the definition o f the transconductance differs from the conventional one in that the
Q-point is not fixed. The Q-point in (5.9) is an “extensive” bias condition which could
include RF large signal besides the dc biases (if any).
Different models of drain current can be substituted into (5.9).
(5.9) can be
expended as following under the application o f the pumped LO signal,
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& A0
8A 0 - ' - -
where
1
nQ - p o int
ao ^
=T co + Z t c* cos(ko)0t) + bk sin(tauQt)]
2
*»
ck = — f g m(r)cos(& v)</(<v)
7t -*
k=0,1,2,3,...
bk = ~ f g m{t)sin(kcD0t)d(o)0t)
k=l,2,3,...
7t
~x
(5.10)
The first order coefficient o f ck is related to the mixing transconductance g ,. From
the later expansion analysis, one could see that g m(t)=
is always an even
Q - p o in t
function o f co0t no matter which I/V characteristics model is selected. Thus
bk ~ ~ ? g m(t)sm(kco0t)d(Q}ot)=O
it
-x
(5.11)
The single side band (SSB) conversion transconductance g-, then is given by
f T£mWcos(<y0/)rf(< v)
(5.12)
The general pumped transconductance g m(t), according to (3-4), is given by
g m(f)
- / p* A ^ { l - t a n h 2[ ^ ( F s - ^ J D a r c t a n W ) ! ^ ^
(5.13)
With the application o f the RF and LO signals at the gate o f a FET,
vs (0 = Vgo + K cos(as() + V0 cos(<o0t)
(5.14)
Substituting (5.13) and (5.14) into (5.12), the mixing transconductance g x can be
obtained.
Fig. 5.8 shows calculated drain current waveform o f the gate mixer using NE33284A
HEMT using a LO peak amplitude of 0.5 V. Obviously, the drain current is cut o ff in
parts o f the LO cycle. The “cut o ff’ here means that the pumped drain current is equal to
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zero when the PGTV is lower than the pinch-off voltage o f the FET. This effect has to be
taken into account in the analysis of the mixing transconductance. The other
consideration is that if Vg(t) exceeds 0.5 V, it will cause the conduction o f the junction
diode between the gate and the source. Here, 0.5 V is an approximate number to turn on
the gate-source junction.
id(t) (mA)
ioo
0
(Dot
2
4
6
8
10
Figure 5.8 The drain current waveform o f the gate mixer at the
local oscillation signal amplitude o f 0.5 V.
As a matter o f fact, from Fig. 5.8, one could see that the analysis of the gate mixer can
be simplified by assuming that the pumped LO signal at the gate is a square wave if the
amplitude o f the continuous LO signal is large enough. The amplitude o f the square wave
can be taken as 0.5-Vp .
Fig. 5.9 shows the mixing transconductance o f NE33284A HEMT as a function of
the gate dc bias at different LO peak amplitudes (the LO power levels). The drain dc
voltage is set at 2V.
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gi(m A /V )
Vgs0(V)
1
-0.75
0.5
0.25
0
Figure 5.9 The mixing transconductance
ofNE33284A HEMT
Here, g l ; 2, g ly4 ,and gly 6 are the mixing transconductance correspond to the LO
amplitudes o f 0.2 V, 0.4 V, and 0.6 V, respectively. Several observations can be made:
the mixing transconductance g,
increases with the decrease of the gate dc bias. The
optimum gate dc bias for maximum g, is in the pinch o ff region. Similar conclusions
have been made before historically, g, increases with increasing LO signal amplitude but
tends to saturate at certain levels. The optimum gate dc bias for maximum g, tends to
move to the positive side with decreasing LO power level.
The most interesting conclusion drawn from Fig. 5.9 is that, for a HEMT, “zero”
mixing transconductance where g, is equal to zero is obtained when the gate dc bias is
around -0.30V (dead region), g, tend to become negative when the gate dc bias is higher
than this “dead region”. What does “negative” g, means? The answer is straight forward
from the definition o f the transconductance (5.9). The “negative” g, indicates that there is
a 180° phase shift in the IF current in the time domain.
109
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Fig. 5.10 shows the pumped waveform o f the transconductance g m(r) at different gate
dc biases. The lower curve is the gate RF signal waveform. gan gbn and gct are the
normalized (divided by a factor of 100 in order to plot the gate voltage in the same chart)
mixing transconductances at the gate dc biases o f 0 V, -0.3V, and -0.8 V respectively.
The LO signal amplitude is selected to be 0.4V. g m(t) has the same phase as that of the
input RF signal at a gate bias o f -0.8V. The phase o f g m(t) has almost 180° phase
difference between the input RF signal and g m(t) at a gate bias of 0V. The frequency of
g m(t) is almost doubled when the
gm(t) (mA/V)
,.j
O'
Vgs0=-0.3V
Vgs0=-0.8V
0
2
4
6
8
10
Figure 5.10 The waveform o f the pumped transconductance g m(t).
gate bias is -0.3V. This “frequency-doubled” g„{t) gives zero first order coefficient g ,.
On the other hand, the second order component would be relatively high at this “dead
region”.
Fig. 5.11 shows final quasi static large-signal equivalent circuit o f the gate mixer.
Table 5.3 lists the element values at biases o f ^ = - 0 . 8 V and ^ = 2 . 0 V. Again, the
parasitic elements here are the same as these in the small signal equivalent circuit. This is
an approximation. As recently reported[83], there is a notable decrease in the magnitude
110
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o f £ , as the frequency varies from 1 to 30 GHz due to the fact that the contact resistivity
is shunted by 2DEG depletion capacitance at high frequency.
Table 5.3 The quasi static large-signal equivalent circuit elements o f NE33284A at
**=3243
Ld= 0 .5 9 0 4
£ ,= 3 .0 0 0
£,.=0.1150
Cd=0.0023
g 0= 0 .0 3 6 -0 .0 5 2
£ ,= 0 .1 1 0 9
£ ,= 1 .1 3 0
II
O*
Cgd= 0 .02834
g , = 0.042
oo
^ = 0 .0 1 5
©
Lg = 0.4465
ll
©
o
VpQ=-0.8 V and Vdl0=2.0 V. Units: Ohms, nH, p f , A/VA2
<^,=0.1513-41.306
To predict the conversion gain and to design the necessary matching networks, the
equivalent circuit can be simplified as a three port network with the RF port at input, RF
port at drain, and the IF port at output. In the equivalent circuit, g 0 is the average
transconductance o f the pumped g„(t). The mixer may oscillate since g 0 is not a small
value. [82] theoretically investigated the stability o f the gate mixer based on the
conversion gain approaching infinity. Unfortunately, the instability of the mixer is caused
by g Qinstead o f g x. In other word, the network between the RF input port and RF port at
drain determines the stability o f the mixer instead o f the network between the input and
IF output. Fig. 5.12 shows the calculated g0 versus the amplitudes o f the LO signal at
biases o f ^ = - 0 . 8 V and ^ = 2 . 0 V.
Large-signal S-parameters can be extracted from the network between the RF input
and the RF port at drain. Then the stability circles can be drawn and analyzed. The details
are given in Section 5.5.
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Cgd
vc ^
oVe
9
da
give
Cd
da
Figure 5.11 The fin a l quasi static large-signal equivalent circuit o f the gate
mixer fo r matching network design and prediction o f conversion gain.
go(mA/V)
48
36
4
12
0
Figure 5.12
0
0.2
0.4
0.6
0.8
V o(V)
The calculated g 0 versus the amplitudes o f the local oscillation signal
at the dc gate bias
=-0.8 V and the dc drain bias
=2.0 V.
112
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5.4 QSLS equivalent circuit for the drain mixer (DM)
To develop an equivalent circuit for a drain mixer, the small signal equivalent circuit of
the FET is determined based on the measured S-parameters at the desired dc bias level.
Among the small signal equivalent circuit elements shown in Fig. 5.1, it is reasonable to
assume that there are only three elements, R ^, C ^, and gm being the nonlinear elements
since the pumped LO signal is applied only at drain and shorted to ground at the gate or
has very small power levels at the gate. Fig. 5.13 shows the measured input reflection
coefficients r /n o f a typical DM using a NE33284A HEMT. There are two traces in Fig.
5.13. One is without pumped LO signal and the other is with the LO signal at power
levels o f 10 dBm. The frequency band between Marker 3 and 4 is the designed RF
frequency range o f 11.70 ~ 12.20 GHz. Marker 5 is the center frequency o f the image
signal band when the LO frequency is set at 10.730 GHz. It can be seen that I~n does not
vary significantly from 9 GHz to 14 GHz with and without pumped LO signal. Thus, to
develop the QSLS equivalent circuit, the three elements, R ^, C ^, and gm are replaced by
the pumped nonlinear elements /?*(?)»
( 0 , and gm(t) and the rest of the elements are
the same as those o f the small signal equivalent circuit.
The parasitic elements Lg, Ld, Ls, Cg, Cd, Rg, Rs, Rd have been extracted from the
“cold” S-parameters. The drain dc bias o f the new drain mixer is selected to be zero volts.
Note that again the small signal equivalent circuit is used even though the S-parameters
are the “cold” S-parameters. These elements are listed in Table 5.4.
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S u
la ,
W IG
r s r e . a dB
£
t a . a * 3/
* -i.eGsa dB
Hp
■—
1
MAR <E R 5
c . 4 GH z
'
:
J
. with LO sig.
|
*
'! - ------
T
r ~
'i
i
i
i
r
A
-----
j
I
i .
i
without LO sig.
. -
|
I
s ta r t
STOP
9.0 0 0 0 0 0 0 0 0
I d .300000080
c h i
GHi
Figure 5.13 The measured input reflection coefficient IT,
o f a typical drain mixer ( NE33284A HEMT).
Table 5.4 The small signal equivalent circuit elements o f NE33284A at V ^^-O .S V
and V^q- 0 V. Units: ohms, nH, p f , mA/V
4= 0.4465
Rg =0.015
**=10.08
C?=0.1116
£4=0.1591
Ld=0.5904
Rd=3.000
*,.= 1.00
Cd=0.1386
g o=0.00
4=0.1109
*,=1.130
C*= 0.012
Cgd=0.1455
In the following section, pumped g j f ) and its first order coefficient (the mixing
transconductance) g, are analyzed and modeled based on the new IN characteristics
equations developed in Chapter 3. The frequency conversion o f DM will be demonstrated
at zero drain dc bias and in the ohmic region as well. The pumped value of * * (t) will be
discussed and determined. Due to the frequency dispersion [69][70] characteristics of
* * (/) and the complexity o f deriving it from I/V model, an experimental measurement
11 4
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technique is developed to determine R&it). Finally, the pumped
Cgd(t) is calculated
and the QSLS equivalent circuit for DM is completed.
5.4.1 Frequency conversion in the new drain mixer
As is analyzed in section 5.3.3 based on the simplified l/V characteristics o f a FET
and an ideal mixer, frequency conversion tend to occur if the LO signal is applied at drain
when the FET works in linear region or even without drain dc bias.
5.4.1.1 Symmetrical FET I-V characteristics
The “Symmetrical” I-V characteristics assumed here means that the same equation
with the same parameters are used for the drain current in both Vd >0 (forward region)
and Vd<0 (reverse region). Obviously, this kind o f FET does not exist. The most available
commercial FETs are more or less symmetrical in the channel structure between the
source and the drain. The I-V characteristics then is not symmetrical according to the
analysis o f the drain currents in Chapter 3 for both Vd >0 and Vd<0. In other words, the
pinch-off voltage decreases with the decreasing drain-to-source voltage in Vd<0. It is,
however, instructive to assume the symmetrical I-V characteristics for analysis of the
mixing phenomenon of the new drain mixer.
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Meterka’s model is used as a comparison to the new model since Meterka’s model
provides the best accuracy among the conventional models in the linear region. From the
well known Meterka’s model, the drain current is modeled by
and can be reduced to the following expression in the linear region,
I
aV
f d = - f r ( v g - v p ) 2 t™ h(
d
(5.15)
)
According to the definition of the transconductance of (5.10) and (5.15), the
corresponding transconductance is
1-
s
tanh
aV,
pQ - p o int
(5.16)
According to the new model (3.4), the transconductance
is given by (5.13), or
«.(<) - / . . ^ { l - t a n h ’K C r ,
(5.17)
with the gate and drain voltages
v i = Vdo + v o c o « W )
(5-18)
Vg - V ^ - I dRs
where Ko is the intrinsic drain dc bias which is related to drain dc bias
by
Vm = Vm - I d(Rd + R s)
and Rd , Rs are drain and source resistances, respectively.
116
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In (5.18),
V0
is assumed to be a constant regardless of the gate and drain dc biases.
The drain shunt resistance and rests o f the elements (thus the reflection coefficient) is a
function o f the dc biases if the LO power level is kept constant. Then
VQis not a constant
at different biases. In order to simplify the analysis here, LO power level is adjusted to
keep V0 constant.
A HEMT with having the parameters the same as those of NE33284A transistor in the
forward region is used to investigate the frequency conversion using both Meterka’s
model and the new model. Again, symmetrical I-V characteristics is assumed here
without loss o f generality. In this case, the parameters are,
New model: /,*=24.53 mA, A, =4.0, 4 2=1.088, a=9.954, ^*=-0.300V
Meterka: /* m=70.10mA, y=0.035, Vp=-Q.770V, a =4.369, A =0.242
Fig. 5.14 shows the plot o f the calculation of g, for both models assuming the peak
amplitude o f LO signal is 0.5V. 0.5 V is picked up here because the mixing
transconductance g, tends to saturate beyond 0.5 V which will be explained in the
subsequent sections. Several significant conclusions can be drawn
from these plots.
Frequency conversion does occur in the new type drain mixer and g, is not a small value.
Both models predict maximum frequency conversion occurs at drain bias close to 0 V and
conversion gain goes down with increasing drain dc bias. The new model predicts that the
maximumg, occurs at gate bias around -0.2~ -0.4V while for the Meterka’s model it
occurs at V' 0 =0V. Experimental results that will be discussed later show that the
maximum conversion gain does not happen at Vp0 =0V. Instead, the new model predicts
the characteristics o f the mixing transconductance g, versus
much better. Fig. 5.15
117
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is a special case o f Fig. 5.14. The drain dc bias is set at zero volt and the amplitude of the
LO signal is 0.5V.
87.437
A ,<\
V djO
(a) New model
‘ l 60.341
pO
(b) Materka’s model
Figure 5.14 The g, varies with V^0 and Vd0.
From the analysis o f the mixing transconductance above, one can see that a welldeveloped model should not only fit the I-V characteristic good but should also predict
the higher order derivatives of I-V characteristics. These should be reflected as a good
agreement between the measured and modeled data. The Meterka’s model has problems
118
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in modeling the transconductance even though the drain current modeling is in good
agreement with the measured data.
Fig. 5.16 shows the variation o f g, with gate dc bias and LO amplitude. Here, the drain
gl(mA)/V
100
New model /
Meterka’s
-
0.8
-
0.6
-0.4
-
0.2
0
Vgso(V)
Figure 5.15 Comparison o f the mixing transconductance g, vs. the dc
gate bias
fo r both the Meterka's and new models.
dc bias is set at zero volt. It can be concluded that the mixing transconductance increases
with the increase o f the LO amplitude. The mixing transconductance tend to saturate after
the LO peak amplitude is more than 0.3~0.5V. The mixing transconductance reaches a
maximum in -0.2~-0.4 V of the gate dc bias and decreases with the rest o f gate dc bias.
Figure 5.17 shows g, vs.
and LO signal peak amplitude V0. Here, the gate bias is
set to -0.5 V. It can be concluded that at the zero drain dc bias, the mixing
transconductance will reach close to its maximum value only at 0.5 V o f the LO signal
peak amplitude. At this LO amplitude o f 0.5 V, the mixing transconductance is less than
10 mA/V when the drain dc bias is set above 0.6V. In other words, the higher the drain dc
bias is, the greater amplitude o f the LO signal is needed to get the higher mixing
119
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Vo (V )
64.4 48.3 32.2
o.eo.s-
80.5 I
0 .3 0. 2 "
o.i-
(a)
(b)
Figure 5.16 The mixing transconductance g x varies with the dc gate
bias
and the local oscillation signal amplitude V0.
VdsO(V)
9.5
gi(mA/V)
18.9
28.4
37.8
gi (mA/V)
47.3
Vo(V)
Vdjo(V)
o.s-
0.5
(a)
Figure 5.17
1
I.S
VtfV)
(b)
The mixing transconductance g x vs. the dc drain bias
and local oscillation signal amplitude V0.
transconductance. The mixing transconductance does not reach higher values after
is
great than 1.5V. Fig. 5.17(b) also shows that g t will reach 47 mA/V if drain bias is set
120
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between 0~1 V with the LO amplitude up to 2V. V0 can not be increased arbitrarily in
order to increase g t. As a matter of fact, V0 is limited by
^ » < ^ o - ^ o + 0-5V
(5.19)
because the conduction o f the p-n junction diode Ddg between gate and drain. Ddg will
conduct when (5.19) is not satisfied. For example, F0< 1.5 V if the gate bias is set to
-0.5V and the drain bias is 0.5V.
Fig. 5.17 also shows a “valley” along Vd * V0. g i tends to change rapidly along
this “valley”. Thus the selection o f the dc bias and V0 values is avoided along this
“valley”.
5.4.1.2 FET with asymmetrical I-V characteristics
Most available commercial FETs more or less are symmetrical between the source and
drain. Their I-V characteristics are asymmetrical between
> 0 and V^< 0regions
because of the pinch-off voltages are different in these two regions . The different
equations must be used to model the drain current in the two regions. The I-V equations
are rewritten here for the NE33284A as developed in Chapter 3:
h = I pk (1+ ^2 t a n h [ ^ ( ^ - Vpk)]} a rc ta n fa ^ )
Vd >0
l d = 1 ^ tanh[A,r(vg - Vp0 - AF,)]arctan(arF j
Vd < 0
with the following parameters,
I pk =24.53 mA, Ax=4.0, ^ = 1 .0 8 8 , a=9.953, Fpt=-0.300V
Vd > 0
(5.20)
121
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=74.251 mA, 4 r=1.518, a r=9.346, r pO=-0.556V, AM.00
^< 0
(5.21)
The asymmetrical I-V characteristics will cause drain dc bias level and drain resistance
to be effected when a large amplitude ac signal is applied to the drain since the pumped
drain currents at
Vd > 0 and
Vd < 0 are different. Fig. 5.18 shows at equilibrium a
typical modeled pumped drain current of NE33284A at ^ = 0 with LO power o f 10 mw.
The drain current wave form is not symmetrical. The average drain current is -3.5mA.
The amplitude of drain current in the region Vd < 0 is larger than that in the region
Vd > 0 . However, the drain resistance is smaller in the region Vd < 0 than that in the
region Vd > 0. Thus the total average drain voltage will shift to a certain positive level Vdt
at equilibrium.
(V)
vd(t)
average o f id(t i
0.5
Vd.
-40
0
10
0)ot
20
-60
COot
10
0
(a)
20
(b)
Figure 5.18 The typical pumped drain voltage and current configurations.
The pumped LO signal voltage can be written as
KtCO^K* + F 0 co s(cy )
(5.22)
here, Vdt is the total drain dc voltage which includes the applied dc bias (if any) and
pumped dc offset. Obviously, Vdl is equal to K u o if I-V characteristics is symmetrical or
the drain dc bias is selected so that the LO voltage does not reach to
< 0 region.
122
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It is quite tedious to determine theoretically Vdl, the average drain shunt resistance
Rd{t) and g m(t) in a closed form at a given gate and drain dc biases V 0 and
at a
certain LO power level P0. Fortunately, Vdt and Rd(t) at different dc biases and LO
power levels can be measured very easily and accurately according to the set up o f Fig.
5.19. Here,
can be measured directly by a high impedance meter from the drain dc
bias T (TP1) after LO signal is applied to the DM. For these measurements, the LO
frequency is chosen to be 10.730 GHz.
Rd(t) is measured directly from the IF port of the DM. The ideal measuring frequency
is at the RF frequency band at 12 GHz or at the LO frequency of 10.730 GHz. The
parasitic inductance’s and capacitance’s will affect the output impedance a lot at higher
frequencies. However, the output impedance dispersion tend to stop above 100 kHz
[69][70]. 50 MHz frequency is high enough that the measured output resistance will be
the same as that in 12 GHz band. The parasitic inductance and capacitance still can be
neglected at 50 MHz and this frequency is also in the frequency range of the HP 8510A
analyzer. Full l-port[ 86] is used to calibrate the system. The measured Vdl and Rd (t) at
different dc biases and LO power levels can be found in appendix A5-4.
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TP!
HP S510A
VdsO
ANALYZIER
IF
HP8JS0B
LO
SEEP
HP
DM
OSCILLATOR
50 OHM
BlAS-T
LOAD
GATE
a
HP436A
A
POWER
METER
VgjO
A
Figure 5.19 The set up fo r measuring the drain pumped dc
offset Vdl and Rd(t).
Fig. 5.20 shows the theoretical calculation of the mixing transconductance o f the
NE33284A transistor. Fig. 5.20(a) shows the mixing transconductance versus the drain dc
biases at V&0~ 0 .5 V . g lf and g lr are the mixing transconductance in Vd(t) >0 and
Vd(t)<0 regions, g, is the total mixing transconductance, g, tends to decrease with the
increasing drain dc bias. The maximum o f g, is located at ^ = 0 V.
g lf and g lr are only mathematically divided from g,. As a matter of fact, g, is
calculated by considering the total pumped mixing transconductance from (5.12).
However, the split o f g, into g lf and g lr does help understanding the contribution o f the
forward and reverse regions o f the drain voltages to the mixing transconductance.
Fig. 5.20(b) shows the mixing transconductance as a function o f the gate dc biases at
LO power level o f 10 mw with drain dc bias at 0 V. The maximum o f g, is in -0.2 and 0.4 V range. As mentioned in chapter 3, a parasitic MESFET will happen at a gate dc
124
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g1(mA/V)
60 -
_*_g1f(nVW )
50
0
VdsO(V)
0
0.5
1
Transconductances vs. VdsO
(a)
g1(mA/V)
P0=10rrWV
Vds0=0V
80 :
_*_g1f{mWV)
_ g _glr(nVW)
60 i
i
0
-
0.8
-
0.6
-0.4
-
0.2
0 VgsO(V)
Transconductances vs. VgsO
(b)
_*_g1f(nVW )
, 40 i
i 30 i
I
I
I
|
I
20 I
0
10
5
Transconductances vs. LO paw er levels
(C)
Figure 5.20 The mixing transconductance o f NE33284A .
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bias above -0.3V which will degrade the performance of the transistor. The gate dc bias is
suggested to be in the range o f -0.4V to -0.6V. In this region, low noise with high
conversion gain can be obtained. Moreover, the output drain resistance is usually around
50 ohm in this bias region, thus it is easier to design IF matching network.
Fig. 5.20 (c) shows the mixing transconductance as a function o f LO power, g, increases
with the increasing LO power level. The interesting observation is that the “reverse”
transconductance increases continuously with the increasing LO power levels.
gi(mA/V)
ioo
VgsofV)
-0.8
"0.6
"0.4
-0.2
0
Figure S.21 The average transconductance ofNE33284A.
The “forward” transconductance tends to saturate above 1.6 mw (2 dBm).
Fig. 5.21 shows the average of the pumped transconductance g 0. The I/V characteristics
in Vd > 0 contributes positive g 0 which has maximum value at gate dc bias V 0 around 0.30 V. The negative side o f the I/V characteristics contributes negative value to g 0
which decrease with the decreasing gate dc bias. The total g Qis close to zero at the gate
dc bias o f -0.6 V. It means that unconditional stable condition can be obtained if the gate
dc bias is set at -0.6V. The oscillation condition for an active network is that the feedback
from the output to the input is large enough with the same phase at certain frequency
126
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point. High gain is always relates to this oscillation condition. Only g 0 is related to the
gain with the same frequency component at the input and output of the network
(mixer). For V ^ —0.5 V, at which g 0 o f 31.24 mA/V, gives a pretty high mixing
transconductance. Thus, this is a good point to select the dc gate bias.
The mixing transconductance g t at Vp0 = -0.5 V,
= 0 V, and LO power level of
10 dBm is 54.38 mA/V. The drain shunt resistance is 34.53 ohms.
5.4.2 The pumped gate-to drain capacitance Cgd
Cgd given by (3.5) can be modeled using the drain total voltage,
^ ( 0 = ^ o + ^ o cosK O
Note that Vd0 and V0 are functions of the pumped LO power level and the gate dc bias.
Fig. 5.22 shows the calculated results o f Cgd versus the gate dc bias when the drain dc
0.2
0.IS
CgdO
<
o.t
0.05
-
0.8
-
0.6
-0.4
0
v8SOj
Figure 5.22 The calculated results o f
versus the dc gate bias.
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bias and the LO power are set at zero volt and 10 mw, respectively. From these
calculations, the average o f pumped Cgd is 0.115 p f at a gate dc bias of -0.5 V and LO
power o f 10 mw. This is not far o ff the small signal value o f 0.1455 pf.
The complete elements o f a quasi static large-signal equivalent circuit of a DM at V 0
=-0.5 V,
= 0 V, and LO power level of 10 dBm are listed in table 5.5. The equivalent
circuit is similar to Fig. 5.11.
Table 5.5 The elements o f quasi static large-signal equivalent circuit o f NE33284A at
Vpo— O.SV, V^q=0 V, and LO power level o f 10 mw. Units: ohms, nH, p f , mA/V
Lg=0.4465
4= 0.015
(4=0.1591
<4=0.1116
^ = 3 4 .5 3
4 = 0 .5 9 0 4
Rd=3.000
4 = 1.00
Crf=0.1386
go=3123
^=0.1109
4= 1.130
C*=0.1438
Cgd=0.115
=53.14
g1(rrVW)
80 ,
i
DM VdsO=OV
F0=10rrt/V
GM Vds0=2.0Vt
V0=0.6V
a
-<r.8
-0.6
—#
Figure 5.23
-0.4
DM . . . q
vgs0(V)
-0.2
GM
The comparison o f the mixing transconductance versus
the dc gate bias o f the gate mixer and the drain mixer.
128
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Fig. 5.23 shows the comparison o f the mixing transconductance versus the gate dc
bias of the gate mixer and the drain mixer. The mixing transconductance o f the drain
mixer is higher than that o f the gate mixer. The most advantage is that the peak g, of the
gate bias for the drain mixer is in the range o f -0.2 - -0.4 V instead o f in the pinch-off
region. The noise performance will be much improved when the gate dc bias is not at the
pinch-off region. Moreover, the circuit element modeling will be more accurate when the
gate dc bias is selected in the range of -0.2 ~ -0.4 V.
5.5 Theoretical analysis of the stability of the mixers
In the last section, both the QSLS equivalent circuits for the gate mixer and the drain
mixer are developed. The average of the pumped transconductance g 0 is believed to be
responsible for the stability o f the mixers since only g0 is related to the RF input port and
the RF port at the drain with the same frequency component. According to the stability
theory o f the two port network based on the S-parameters, stability circles o f the gate
mixer and the drain mixer can be analyzed and determined.
Fig. 5.24 shows the modeled QSLS S-parameters of the network between the gate and
the drain at the RF frequency component when the gate and drain dc biases are selected at
-0.8 V and 2.0 V , respectively, for the gate mixer. The peak amplitude o f the LO signal
is selected at 0.5V. One can see that S2l is pretty large. Fig. 5.25 shows the stability
circles on the source and load reflection coefficient planes, simulated by the Touchstone
software. The frequencies related to those stability circles are from 3 GHz to 16 GHz. The
129
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gate mixer is thus conditionally stable. To design a stable gate mixer, the capacitive load
at drain is preferred, from Fig. 5.25 (b). This contradicts the requirement o f shorting the
LO signal at drain because the quarter-wavelength open line may be an inductive load to
the RF frequency if the LO frequency is lower than the RF frequency. Thus, for a gate
mixer using HE33284A HEMT, higher LO frequency compared to the
zz~Z:
-
r2^ Z ~ S Z i r. e
-
A^g 30 52 '5
£2
’.5 9 6 - 5VN5G0
S21
o
X
Sn
16GHz
Frequency increasi
direction
/S 22
3GHz
3 0C00C
5.
n
0
1
.1
'.5. 3000
Figure 5.24 The modeled quasi static large-signal
S-parameters o f the gate mixer.
RF frequency is preferred so that for the RF frequency a capacitive load can be presented.
For example, the LO frequency o f 13.27 GHz is preferred instead of 10.730 GHz so that a
shorting stub, which is a quarter wavelength open line, acts as a capacitive load to the RF
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• -v . -u'; 30 2 2 19
!395 ■ GWiGGO
3GHz
Unstable
Region
15GHz
(a) Source plane
EEsof - 'cucnscone - Fr- iua 30 22: 38:23 ’.996 - SMN3G0
3GHz
Unstable Regibi
15GHz
ible
2
ton
1
:r
(b) Load plane
Figure 5.25 The stability circles o f the gate mixer in the source and load reflection
coefficient planes, simulated by the Touchstone software.
131
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frequency in the band o f 11.70 ~ 12.20 GHz. From Fig. 5.25 (a), capacitive source
impedance is safe for the stability o f the gate mixer also. For the drain mixer Fig. 5.26
shows the modeled QSLS S-parameters of the network at the RF frequency component
when the gate and drain dc biases are selected to be -0.5 V and 0 V with the LO power
level o f 10 dBm. Comparing to the gate mixer, Szl is much smaller. Thus, comparing to
the gate mixer, the higher stability of the drain mixer is expected.
E E scf - 'a i i C ^ s t o - e • r " . -u q 30 22 4 9 0 4 *.995 - :mn3GC
S22
S 11
Frequency increasi
direction
3GHz
S 12
M 3.00000
f 2: ! 5. 0000
Figure 5.26 The modeled quasi static large-signal
S-parameters o f the drain mixer.
This is understandable because of the zero drain dc bias. Fig. 5.27 shows the stability
circles in the source and load reflection coefficient planes, simulated by the Touchstone
132
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i , ♦ 3GHz
15GHz
(a) Source plane
EEscf - 'a u c n stc n e - Cf": Auc 30 23:08:03 ’.396 - 2MN3G0
3GHz
SS2
15GHz
2
2
r
(b) Load plane
Figure 5.27 The stability circles in the source and load planes o f the drain mixer.
133
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software. The frequencies related to those stability circles are from 3 GHz to 16 GHz. The
source stability circles in Fig. 5.27 (a) are almost out o f the standard Smith chart. Thus
we could say that the drain mixer has a lot room to select the source impedance. In Fig.
5.27 (b) of the load stability circles, capacitive load or larger inductive load with higher
resistance (>50 ohms) is preferred. The stable range for selection the load is, obviously,
larger than that o f the gate mixer.
5.6 Conclusions
In this chapter, FET characterization for the gate mixer and drain mixer was developed.
Frequency conversion o f the gate mixer was analyzed. The mixing transconductance of
the gate mixer was calculated. The mixing transconductance o f the gate mixer tends to
saturate after the amplitude o f the LO signal exceeds 0.4V. Pumped gate-to-source and
gate-to-drain capacitance’s were calculated. The quasi static large-signal equivalent
circuit was developed for predicting the conversion gain and design of matching
networks.
Frequency conversion o f the drain mixer was analyzed for assumed transistor with
symmetrical I-V characteristics and also real transistor with asymmetrical I-V
characteristics. The maximum mixing transconductance o f the drain mixer was found at
zero drain dc bias and -0.2V to -0.4 V of the gate dc bias. The mixing transconductance
decreases with increasing drain dc bias and goes to zero eventually. The least LO power
is needed at the zero drain dc bias for the maximum mixing transconductance. The
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mixing transconductance o f the drain mixer was found to be larger than that o f the gate
mixer.
The pumped drain shunt resistance and gate-to-drain capacitance were assumed to be
the nonlinear elements for the quasi static large-signal equivalent circuit. The pumped
gate-to-drain capacitance was modeled. Experimental determination of the pumped drain
shunt resistance and drain dc offset
was developed.
The quasi static large-signal
equivalent circuit o f the drain mixer was extracted.
The stability o f the gate mixer and drain mixer was theoretically analyzed based on the
pumped average o f the transconductance g 0. The pumped S-parameters at the RF
frequency component o f both gate and drain mixers were simulated. The stability of the
drain mixer was better than that of the gate mixer. The capacitive load at drain for the
gate mixer is preferred for the gate mixer.
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Chapter 6
Design of a FET gate mixer
6.1 Introduction
In chapter 5, the quasi-static large signal(QSLS) equivalent circuit of a gate mixer is
presented. The stability o f the gate mixer is also analyzed. In this chapter, a complete gate
mixer at 12 GHz band with a LO frequency o f 10.730 GHz is designed based on the
developed QSLS equivalent circuit. The analysis and prediction o f the conversion gain is
carried out. The theory developed in Chapter 7 for predicting the IM3 products based on
the first order output is verified.
As mentioned in chapter 5, a gate mixer consists of input matching network to the RF
and LO signals and the IF port matching network to the IF frequency. The input and drain
matching networks have to be designed very carefully so that the RF signal is transferred
to the FET effectively without any instability at any frequencies. Moreover, the matching
network at drain should short the LO signal to the ground to keep the amplitude o f the LO
signal at the drain as small as possible. This can be done by inserting an open quarterwavelength line at LO frequency. However, as shown in chapter 5, this line is an
inductive load to the RF signal and may cause instability o f the mixer when the LO
frequency is set below the RF frequency. Thus, a trade off between the stability and
shorting the LO signal may have to be considered.
The IF port matching network is designed so that the intermediate frequency
component can be transferred to the load effectively. Thus, the conjugate matching
136
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between the output o f the transistor and the input of the matching network is desirable in
the IF frequency band and for the given transistor this has been achieved.
6.2 Matching networks and conversion gain
Fig. 6.1 shows the schematic o f the microstrip gate mixer. The shunt stubs are used for
the input matching network. The trade off o f matching has to be considered between the
RF signal and the LO signal at the input matching network. It is preferred that this
network is designed so as it matches to the RF signal in the stable condition with
minimum transmission loss of the RF power. A quarter-wavelength open-line is used in
the drain. This open microstrip line shorts the LO signal or reduces the LO amplitude at
drain as small as possible to keep the total drain voltage above the knee voltage.
However, the quarter wavelength open line appears to be an inductive load to the RF
signal which may cause instability o f the mixer. Thus, the open-line must be carefully
chosen. Some trade-off may be necessarily between the shorting the LO signal at drain
and the stability o f the mixer. In other words, the line selection with stability
consideration may result the total drain voltage to be LO signal dependent. As is well
known, this will degrade the conversion gain.
Three inductors and one capacitor are used in the IF output port. The network is
conjugate-matched at the IF frequency.
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Substrate:
UL2000,
ER=2.45,
h=20mils
132
Lo=80
Wa=17.33
130
130
IF Output
—O —C3=RF+LO siqnols
Figure 6.1 The schematic o f the gate mixer.
Fig. 6.2 shows the measured and calculated conversion gain as a function o f
frequency at Vp0 —0.8V, V ^ - I V , and LO power level o f 4 dBm. The calculation of the
conversion gain is based on the developed QSLS equivalent circuit of the gate mixer at
the given dc biases and LO power level. The accuracy o f the calculations depend on the
measured S-parameters, the calculation of the pumped mixing transconductance, the
prediction or measurement o f the pumped drain shunt resistance, and so on. The
difference between the experimentally measured and calculated gain also depend on the
following several areas, the implementation o f the matching networks exactly based on
the calculated results, shorting the LO signal at the drain to assure the calculated mixing
transconductance will be produced, and the process and method of the measurement. Any
o f those procedures could create errors and these errors may accumulate.
138
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Ga(dB)
Va t0 =-O.8V
Vdio =2.0V
12
P0=4dBm
10
-
8
6
o
4
2
Measured
. . . . . . . Calculated
0
800
1000
1200
1400
1600
Figure 6.2 The measured and calculated conversion gain
frequency response o f the gate mixer.
By careful analysis o f the difference between the measured and calculated conversion
gain in Fig. 6.2, one can see that QSLS equivalent circuit developed in chapter 3 is
accurate enough and so is the prediction o f the mixing transconductance. The calculated
conversion gain is higher in certain frequency range and the bandwidth is narrower
compared to those o f the experimental results. It is believed that the implementation of
the circuit is not quite exactly the same as the simulated conditions. For instance, the
ground o f the substrate, connectors, soldering points, parasitic, and even case cover could
effect the results. These extra factors cause lower gain and wider bandwidth than those
predicted. The agreement between the calculated and measured results is good overall in
terms o f the above arguments.
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Fig. 6.3 shows the calculated and measured conversion gain o f the gate mixer versus
gate dc biases at RF frequency o f 12 GHz. The experimental results did show the “zero”
conversion gain phenomenon as discussed in chapter 5. This notch appears around at
Ga(dB)
10
-
o
„ Measured
-■
calculated
Vg*0(V)
-
-1 0
0.8
-
0.6
-0.4
-
-20 1
Figure 6.3 The calculated and measured conversion gain
o f the gate mixer versus gate dc biases at RF
frequency o f 12 GHz.
FgiO=-0.3 V for the NE33284A HEMT. The IF current at both sides o f the notch have a
180° phase difference. Those currents cancel each other at FpO=-0.3 V and cause very
low conversion gain. The poor agreement after V ^ - 0 .3 V is due to the possible
inaccuracy in the calculation o f the mixing transconductance and the parasitic MESFET
in the AlGaAs layer. Similar disadvantages are also observed in the drain mixer.
Fig. 6.4 shows typical noise figure performance o f the gate mixer. The better noise
figure is in the range o f 6 to 8 dB no mater how the LO power level, dc biases, etc. were
optimized. As will be shown in the next chapter the drain mixer offers much better noise
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performance which is in the rage o f 3 to 3.5 dB. Besides, drain mixer has slightly higher
conversion gain.
— a — Ga(Ro=4dBm) - -A- -NF(Ro=4dBm)
6a (dB)
NF(dB)
10 -
- 16
8 -__
- 14
6
- 12
CJ . 1°
4-
W 8
6
A
.0 i
800
1000
1200
1400
1600
IF fre q u e n cies (MHz)
Figure 6.4 The typical noise figure performance o f the gate mixer.
Fig. 6.5 shows typical intermodulation performance o f the gate mixer. The third IM
output can be predicted according to (7.9) in next chapter. Using F ^ —0.8 V, Faio=2.0 V,
and the LO power level of 4 dBm, (7.9) can be reduced to:
fl3P
P3rd (dBm)=33.22+201og[-^H+3 PUt(dBm)
(6.1)
P „ (dBm)= - 64.17+20log(lfl3P|)+ 3 /,£rt(dBm)
(6.2)
or
Errors in predicting the theoretical pumped a3p apply to all models because o f three
reasons: first is the third order derivative of the I-V characteristics could generate large
errors; Second, the frequency dispersion may become effective since the drain is biased in
141
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the saturation region( 2V) where the effect is considerable; Third, the shorting o f the LO
signal at the drain may not be perfect. Thus the determination of
a 3p from the
experimental method would be better and more accurate. Fig. 6.6 shows the measured
IM3 output compared to the calculation using the measured a 3.
The Outputs vs. the Input Signal Power
Levels
-10 i.
?
-20 i,
5.
-30 i
CO
1
■___ P lst
M'
g
-30
-25
-20
-15
P3rd
-10
-5
0
Pin (dB)
Figure 6.5 The typical intermodulation performance o f the gate mixer.
Note that a3p is different from ay One is pumped IM3 coefficient and the other is not.
Restrictedly, a3p should be used in (6.2) for predicting the IM3 product. Here, a 3 is used
due to the difficulty o f measuring a3p directly. The well agreement between the measured
and calculated results is still obtained.
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P3rd(dBm )
0r
10 *
Gate mixer
Va*o=-0.8V
-20 _
-30 -40 -50 -60 -70 1
-80
-30
Measured
Calculated
Pin(dBm)
-20
-10
0
Figure 6.6 Measured and the calculated IM3 output based on
experimentally measured a z at the dc bias o f
Vg,0 ~~0.8 V and VdsO=2.0V.
Fig. 6.7 shows the measured IM3 output versus the LO power level. The first order
output, o f course, increases with the LO power level until the gate-to-source pn-junction
conducts. The gain increases with the increasing the LO power level. However, the IM3
output decreases with increasing LO power. This can be explained from (6.1). The
increase o f 3 PUl basically can be canceled by the decrease of the 20 log(—7-) . Provided
a lp decreases with the increasing the LO power level. Fig. 6.8 shows the calculated aip
versus LO signal amplitudes (thus power level). The a3p does decrease with increasing
LO power. More study is needed for modeling the IM3 output versus LO power level
because the elements such as c *
c „ , 11^, and a3p
are to be determined more
accurately.
143
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P 1 st (dBm)
-10
,
-20 ,
-30 -40 .
-50 -
P3rd(dBm)
-70 ______________ _______________ _
-15
-10
-5
0
5
Po (dBm)
10
Figure 6.7 The measured IM3 output versus the local oscillation signal power levels.
a3p(mA/VA3)
100
-
-100 i
Figure 6.8
The calculated a2p versus local oscillation signal amplitude.
6.3 Noise Figure, Conversion Gain, And Intermodulation Measurements
The setup for measurement o f noise figure o f the gate mixer is shown in Fig. 6.9. The
input netw ork, which combines the LO signal, RF signal and the gate dc bias, is shown
in Fig. 6.10.
144
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H P 89 7 0 A N oise F igure M e^er
= 0 _________________ Q =
H P 8350B O scillator
IF
RF+La
N oise S o u rc e
G ate Mixer ^
Input
vletworl
Calibration
>■
o
V i HP J
11612A B ias T
VgsO
)
<±> VdsO
Figure 6.9 The setup o f measurement o f noise figure o f the gate mixer.
The input network introduces certain loss to the whole measuring system. The loss
can be measured by the network analyzer at the desired frequency. The Mode 34.2 special
function can be used to exclude the loss when noise figure o f the gate mixer is measured.
As shown in Fig. 6.9 and 6.10, the input network combines the RF signal, LO signal,
and the gate dc bias. The network also filters out the image signal and the IF signal in
order to measure the noise figure and conversion gain accurately, as is described in last
chapter. Two HP P281C waveguide to coaxial adapters are used to filter out the image
signal and IF frequency component at the input port o f the gate mixer.
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Fig. 6.10 shows the measured frequency response of the input network from 6 GHz to
18 GHz. The cutoff frequency o f the network is at about 9.8 GHz which is above the
image signal frequencies (Marker 1 and Marker 5). The IF frequency component is far
r
50 o h m s
load
3 Vgsi
To g a te
m ix er input
(1), (2) HP P281C Waveguide to cgaxial adapters
(3)
NEC 88414B isolator
^
(4)
HP 11612Abias
Figure 6.10 The input network o f the gate mixer.
below the cutoff frequency and thus also filtered out. Marker 3 and Marker 4 are the
lower and upper boundary o f the RF signal band. There is no resonant frequency within
the RF frequency band.
Fig. 6.11 shows the measured insertion loss o f the network in the frequency band of
11 GHz to 13 GHz. The frequency band between Marker 1 and Marker 2 is the RF
frequency band o f the signal, 11.7 GHz to 12.2 GHz. The insertion loss is 4.55 dB.
146
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I
I«g
REF 0 . 0 d e
£
1 0 .0 dB/
* - 7 . 7 5 2 4 . JB
mac
I’P
MAF < e r ‘ 2 ~
5 . 2 t Ch
------ —
----- ------
------ ------
------ ------
—
■
A3 A
2
-N & -
'
\ —
r
1
L
i
/
f
START
STOP
6 .0 0 0 0 0 0 0 0 0
1 8 .0 0 0 0 0 0 0 0 0
GHz
GH z
Figure 6.11 The measured insertion loss o f the input
networkfo r measuring the gate mixer.
Fig. 6.12 is the setup for measuring the intermodulation o f the gate mixer. Two 12
GHz sources with 20 MHz frequency difference with equal amplitudes are combined
together and sent to the variable attenuator. The LO signal is also combined with the RF
signal and sent to the mixer. The long cable with 15 dB loss is used between the output
and the input o f the spectrum analyzer to keep the input signal being always small signal
to the analyzer.
During the calibration, a through is connected between the output o f the input bias T
and the input o f the long cable (with 15 dB loss) to identify the power levels o f the two
combined RF signals and LO signals. Then, the gate mixer is inserted between where the
calibration through ports, as shown in Fig. 6.12. The first order and higher order
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harmonics at different dc biases and the input RF signal and LO signal can be measured
directly.
10.73 GHz LO
HP 8350B
Oscillator
attenuator
✓ S.
VdsO
HP
I1612A
3iasT
NEC
NEC
38414A
solator
38414A
solator
.ab-buiit
12 GHz
Oscillator
HP 626A
Dsdllator
f1 (GHz)
f2 (GHz)
12.000
12.020
VgsO
HP
I1612A
BiasT
HP
Spectrum
Analyzer
Calibration
15dB atte
Gate Mixer
able
Figure 6.12 The setup fo r measuring the intermodulation o f the gate mixer.
6.4 Conclusions
In this chapter, 12 GHz band HEMT gate mixer was designed based on the developed
QSLS equivalent circuit. Typical conversion gain of more than 8 dB with a noise figure
o f 5.5 to 7 dB were obtained. The “zero” conversion gain was observed and analyzed
experimentally and theoretically. Using the developed theory for predicting the IM3, the
third order harmonics o f the gate mixer was compared experimentally and theoretically.
The complete
setups for measuring the noise figure, conversion gain, and
intermodulation products o f the gate mixer were described. Decrease o f the IM3 products
with increasing LO power was observed and explained.
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Chapter 7
Design and performances of the Drain Mixer
7.1 Introduction
In this chapter, the design of a 12 GHz band drain mixer is carried out. The input RF
signal matching network, IF matching network, and the band pass filter network o f the
LO signal at drain are developed based on the QSLS model developed in chapter 5.
In the stability analysis o f the drain mixer in chapter 5, it was shown that for the
source impedance plane the unstable regions were near the outer prophecy o f the Smith
chart. Thus, the input network can be designed conjugately for maximum RF power
transferring to the FET for maximum conversion gain.
The drain matching network should have bandpass characteristics to the LO signal and
provide the required load to the RF signal at the drain port. This load should keep the
drain mixer out o f the unstable region. Moreover, the Sl2 or
pretty large due to the
zero drain dc bias. The selection o f the load will affect the input impedance o f the mixer
significantly. A low Q load to the RF frequency at drain is preferred in order to overcome
the LO power affecting the input impedance. The drain shunt resistor and the gate-todrain capacitance are functions o f the LO power. Any variation of the LO power will
cause the change o f the values of these two elements, and thus the input impedance. The
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low Q design also offers the advantage o f increasing the tolerance o f the QSLS equivalent
circuit model since the equivalent circuit is developed by replacing the pumped nonlinear
elements in the drain only. Here, low Q means any short-circuit or open-circuit to the RF
signal at drain is avoided.
An analysis o f the conversion gain is developed based on the developed QSLS
equivalent circuit even though many methods may be available. This method is unique
because that a linear microwave circuit simulation software such as Touchstone can be
used to predict the conversion gain o f the mixers.
A simple and effective method is developed for predicting the third order harmonics
o f the mixer instead of using traditional methods. The third order harmonics can be
predicted based on the known pumped third order coefficient a2p and the conversion gain
o f the mixer. a3p is modeled as shown in Chapter 4.
The measurement of conversion gain, noise figure, and intermodulation products of
the drain mixer are also discussed in this chapter. The comparison o f the predicted
conversion gain and third order intermodulation product to the experimental results are
carried out.
7.2 Design O f Drain Mixer For Maximum Conversion Gain
Fig. 7.1 shows the schematic o f the drain mixer. The cross shunt stub is used in the
input matching network. The position, lengths, and the width o f the stub are selected so
that the RF signal is conjugately matched and at the same time the LO signal at the gate is
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shorted. It is difficult to meet those two requirements. The key point is to match the RF
signal and then keep the amplitude of the LO signal as small as possible which leaks from
the drain. The DTMBPF filter in the drain provides a very narrow pass band to the LO
signal which also blocks any IF signal leakage to the LO port. The distance between the
DTMBPF and the drain has to be selected so that the drain load to the RF frequency
component has low Q. This means that no short-circuited or open-circuited elements to
the RF frequency is desired at the drain.
Figure 7.1
The schematic o f the drain mixer.
The IF network consists o f a required length o f high characteristics impedance
transmission line and a shunt capacitor C/F as a low pass filter for the matching purpose.
The network is conjugately matched at the IF frequency band for the maximum
conversion gain.
Fig. 7.2 is the QSLS equivalent circuit developed in chapter 5 at a gate bias o f -0.5
V, with zero drain dc bias and 10 dBm of LO power level. The related elements o f the
equivalent circuit are listed in Table 5.5, (units: ohms, nH, pf, mA/V) i.e.:
151
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Table 5.5 The QSLS equivalent circuit elements o f the drain mixer
^ = 0 .0 1 5
/?d=3.000
£,=1.130
6^=0.1591
^= 0 .1 1 1 6
Crf=0.1386
Cgd=0.117
©
©
II
of
£g=0.4465
Ld=0.5904
£,=0.1109
C*= 0.1438
£*=34.53
^0=24.5
53.1
Fig. 7.3 is the Touchstone simulation circuit for designing the input and drain port
networks. The numbers in dotted circles are the simulation nodes. The goal o f the design
is to select the lengths £,, Lu, Ld0, Wd, and L 2 so that the conjugate input matching at
the input o f the FET. i.e.:
z,=z;
(7.1)
where Z, and Z a are the impedance as shown in Fig. 6.3. The Lx, Lu, Lio, Wd, and L 2
Rd
Cqd
ioVc
Rd
« « ©
4 a,
Figure 7.2 The quasi-static large signal equivalent circuit o f the drain mixer.
' 152
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are the physical sizes o f the transmission lines as shown in Fig. 6.3. For instance, W J Lu
stands for the width and length o f the upper cross stub.
7.3 Design Of The Matching Networks And Prediction O f The Conversion Gain By
Touchstone
As is shown in Fig. 7.2 of the QSLS equivalent circuit, it is relatively easy to analyze
the impedance in each port and thus design of the matching networks. The difficulty here
is the calculation of the conversion gain at different frequencies between the RF port and
the IF port, i.e. the RF frequency band at the input and the IF frequency band at the IF
output port. There is no way to do multi-frequency analysis by Touchstone unless some
modifications and assumptions are made.
Zin
Z.
Wd/Lu
W/Lo
RF
W/Lo
Wb/Lb
Wd/Ldo
W/Sa
Cif
IF
Figure 7.3 The Touchstone simulation modelfo r designing the
input and drain networks o f the drain mixer.
153
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The following assumptions are made for the effective analysis of the conversion gain:
a) the frequencies in the IF port are the same as those in the RF port, b) the values o f the
parasitic elements Ls,L d, CA, and Cd in the IF port are then reduced by a factor o f a>m
/coRF0 in order to keep the same characteristics of the IF port. Here colF0 and coRFQ are
center angular frequencies o f the IF band and the RF band, respectively. It is easy to see
from Fig. 6.2 that the IF output impedance is dominated by the
+ Rd + Rs. This can be
seen from Touchstone simulations of the output reflection coefficient or the impedance in
the IF port. Obviously, the output impedance o f the IF port will be the same when the RF
frequency is used for the assumptions.
Fig. 7.4 is the mechanical drawing of the test fixture. There are two sections that are
isolated from each other by a thin wall. There is an open slot in the wall where the FET is
mounted. The source leads are pressed and grounded to the wall by a upper cover o f the
wall. The gate and drain leads are connected to the substrates in the two sections. Fig. 7.5
shows the circuit layout o f the drain mixer. The substrate is DUROID UL2000 with
£r=2.45, thickness = 20 mils.
Using the dimensions derived from Touchstone simulations, circuit shown in Fig. 7.5
is proposed and S-parameters are measured under the operating conditions. Fig. 7.6
shows the measured and simulated RF port input reflection coefficients, S u . The RF
signal frequency band is from 11.7 to 12.2 GHz. The measurement is made under the
pumped LO signal o f 10 dBm. Fig. 7.7 shows the measured and simulated Sn at LO
port. The
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0 250 “
0.125'
0.140'
0.140'
0 . 110”
0.700'
0.080'
0.600'
0.775
0 .210 '
;0 . U 0
0.400'
0.700“
Figure 7.4 The mechanical drawing o f the test fixture
fo r 12 GHz drain mixer.
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
UNIT :f1ILS
GATE PORT
DRAIN PORT
Figure 7.5 The circuit board layout o f 12 GHz drain mixer.
5 u
10 9
PtBF 0 . 0
£
HAS
dB
ie .0 ts /
- ▼ .8 5 3
-8
GHz
START
sto p
1 1 .0 8 0 0 0 8 6 8 0
i3 .e e a « e 0 e « e
OM«
gm*
Figure 7.6 The measured and predicted input reflection
coefficients o f drain mixer.
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return loss is very small since the reflection coefficient is less than -20 dB. That means
most o f the LO power is delivered to the FET. Fig. 6.8 shows the 5,, at IF port. The band
width is much wider than that in RF port or LO port because the output resistance is
dominated by the drain shunt resistance and the parasitic resistance.
The agreements between the simulated and experimental results are good. This is not
easy task to complete because the design of the matching networks is related to so many
precautions such as the frequency, large signal operation, measured device S-parameters,
measured I-V characteristics, the QSLS model, measured drain shunt resistance,
fabrication of the circuit, and the final performance measurements. Any error made or
accumulated in those processes will causes significant inaccuracy o f the design.
S -n
I 0 9 HAG
R EF 0 . 0 dB
1
1 0 .e d B /
V - 2 0 . 2 3 dB
3 . 7 (3 5
C HZ
START
STO P
1 0 .0 0 0 0 0 0 0 0 0
L I .3 0 0 0 0 0 0 0 0
GH z
GH z
Figure 7.7 The measured and simulated Su at local oscillation port.
157
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S u
R E P
' * 9
2
0 . 8
*
- 1 5 . 6 6 5
M * C
d B
te.e oB/
d B
■Simaiated
S T A R T
S T O P
0 . 5 0 0 0 0 0 0 0 0
. 0 0 0 0 0 0 0 0 0
2
G H z
C X z
Figure 7.8 The measured and simulated S u at intermediate frequency output port.
The conversion gain can now be predicted since the input matching network and IF
output matching network have the same frequencies band under the assumption that the
values o f the parasitic elements Ls,L d, C^, and Cd in the IF port are reduced by a
I Gain (dB)
I
!
15 T
-Measurd
q. . .
Modeled
800 900 1000 1100 1200 1300 1400 1500
Figure 7.9 The measured and simulated conversion gain o f the drain mixer.
158
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factor of o)IFQ / o ) ^ . Fig. 7.9 shows the measured and simulated frequency response of
the conversion gain under the following conditions,
/ 0=10.730 GHz
P0 =10.0 dBm
KJlO=-0.50V
^ 0 =OV
The agreement between the theoretical prediction and experiment is not perfect,
especially off the center frequency. The center frequency is at 12 GHz where the IF is
1270MHz. The error can be anything from measurement o f I-V characteristics, I-V
model, small signal S-parameter measurements, the extraction o f the elements o f the
small signal equivalent circuit, the determination of the drain shunt resistance, the
prediction o f the mixing transconductance, the manufacture o f the circuit, and the
measurement, etc. It is believed that the difference in Fig. 7.9 are caused by the input
matching network. The input matching network has to be designed in the high- Q region
since the amplitude o f Su o f the transistor is greater than 0.7 at 12 GHz band. Any error
o f the PC-board fabrication, mounting, and even soldering could cause the problem. The
measured, conversion gain is higher than that o f predicted. Thus the real mixing
transconductance is higher than the calculated value. It is believed that the I-V model
could have higher errors for predicting the first-order derivative o f the I-V characteristics
when the drain dc bias is zero volt. In this calculations, the harmonics of the mixing
process are also neglected. For instance, even the RF signal with the fundamental
frequency f s is amplified and transferred to the drain due to the pumped average
transconductance. The frequency conversion occurs at the drain when this amplified RF
signal is applied across the pumped drain shunt resistance with the same IF frequency o f
f s- f 0. This can be seen from,
159
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*rf(0 ~ g 'V 'R * cosa>stcosa)0t
where R ^ is the first order coefficient o f the pumped drain shunt resistance.
Ga(dB)
15 10
.
Vgso=-0.5V
Vdso=OV
fo=10.73GHz
6=12 GHz
5 ^
0
Measured
.
-5 -
-q . . . Calculated
Po (dBm)
-10
10
Figure 7.10 The measured and calculated conversion gain.
versus local oscillation signal power levels.
Fig. 7.10 shows the measured and calculated conversion gain versus the LO power
levels. The bias condition is at V ^ —0.5 V, ^ = 0 V. The agreement between the
measured and calculated results is quite well. Obviously, the conversion gain increases
with the increase o f the LO power level.
Fig. 7.11 shows the conversion gain versus the drain dc bias at a fixed LO power level
o f 10 mw. Both calculated and measured results show that the gain decreases with the
increase o f the drain dc bias. The main reason, as explained before, is that the effect of
the drain current variation with the pumped LO signal decreases in the saturation region.
Thus the pumped mixing transconductance decreases with the increase of the drain DC
bias. The difference between the measured and calculated results are believed to be due to
160
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the equivalent circuit o f the drain mixer. The S-parameters at ^<,=0 V were only used to
determine the small-signal elements o f the QSLS equivalent circuit o f the DM. As a
Vgso=-0.5V
Po=10dBm
fo=10.73GHz
fs=12.0GHz
Ga(dB)
12 _
11
-
8*
7 _
6.
5 4
0
Measured
Calculated
VdsO(V)
0.5
Figure 7.11 The measured and calculated conversion
gain versus drain dc bias.
matter o f fact, the gate capacitance
and gate-to-channel resistance Rt changes with
the drain dc bias. This is one o f the major contributions to the error.
More measured specification o f the drain mixer refers to the appendix A7-2.
7.4 Predicting Third Order Intermodulation Products Based On Conversion Gain
In this section, a simple but effective way for predicting third order intermodulation
products of a mixer is described based on the known conversion gain or output power
level o f the first order. As shown in Fig. 7.12 of modified DM circuit, the following
assumptions are always valid for the mixer when intermodulation products are
considered. The amplitude o f the two signals across the gate capacitance C& are equal
161
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Rg=50 ohms
Source 1
Source 2
Rds
Figure 7.12 The modified drain mixer circuit fo r prediction IM3 products.
because the signals are adjusted to have the same power level at the input. All the
networks have the same characteristics to those two signals since the frequencies are very
close to each other. The parasitic inductance and capacitance can be ignored at the IF
frequency band. There are only 2 /, - / 2 and 2/ 2 - / , third intennodulation products
since all the harmonics are filtered out by the EF port filter, where / , and f 2 are the
frequencies o f the two input signals. The IF port is designed for conjugate matching for
maximum conversion gain. Thus, the modified circuit as shown in Fig. 7.12 is developed.
According to the definition o f the harmonic currents, the first and third order currents
are given by
Iuf=^p vtX
(7.2)
(7.3)
Since only 2 f x - f 2 or l f 2 - f is considered, then I ip reduced to
162
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V “ 3 a ,, W *
P-4)
Then the ratio o f the third order power to the first order power is given by
IMR,= 9
K fi ■
V',
(7.5)
\ a \p /
where a lp and a3p are pumped harmonic coefficients which are related to the harmonic
coefficients a, and a 3 by
so
(0 = % +
i =1, 3
c o sK O ,
(7.6)
y'-i
According to the IF port equivalent circuit in Fig. 7.12, it is not difficult to get the
following expression
.
D2
R , + R + Rd . G 2P-n
^.=c 1+- - *V
*
) 7a iP/ct
^
(?-7)
Substituting (7.7) into (7.5), we have
IM R i= 9 ( \ +
R , + R , + R d . a]„G3P*
—1--- 4)4
*
-
(78)
a \pP~L
or the third harmonic output is given by
PZrd(dBW)=39.542+401og(l +
R + /?+/?
pJ
-)
R ds
'
a] (mA2 I V2)
+ 10,og[< ( ^ T O
l ( ^ 1+3G(dB>+3P*(dBm)
or
/>3rrf (</5m)=69.542+40log(l +
dj
163
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+20 ,O8 [< S
7
^
5 5
i+3G<dB>+3^<‘<8'”)
<7-9>
The third intermodulation output, from (7.9), decreases with increasing drain shunt
resistance R& as well as with the increasing mixing transconductance. Proper selection of
and reduction in alp thus the third
the gate bias could lead to an increase in
intermodulation output can be minimized. The third intermodulation output will also
decrease with the increasing LO power since alp increases with the increase of the LO
power. Fig. 7.13 shows the calculated and measured pumped a 3p. Obviously, the good
chose for the gate dc bias for lower IM3 products is in the range of -0.5V to -0.65V where
the R^ is higher with higher mixing transconductance and lower a3p
a3p(mAA3/VA3)
250 T
. . . . . . . Calculated
— ■— Measured
150 j
50 i
i
-504.8
!
-150 i
-250
Figure 7.13
O—■
«\
-0.6\
'CC
_
, - » - f V8*0(V)
/
i
\-0.4
-a i
/ n
1
\i , V'
_
_
i
The measured and calculated pumped a3p o f the drain mixer.
The measurement o f a3p is similar to the way of measuring a3 as mentioned in chapter 4
o f Fig. 4.2. The only difference is that the FET test fixture is a drain mixer test fixture
164
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which has an additional port available for injection o f the LO signal. The LO signal is set
at 10 dBm power level at the frequency of 10.73 GHz. Third harmonic(13.5MHz) power
level is observed with the fundamental VHF signal o f 4.5 MHz at the input. Thus aJp can
be determined.
For the drain mixer with the following working conditions,
Pg,o~0.5V , ^ 0=OV,/> 0=10mw
and with the following pumped first and third order coefficients,
a lp= 54.84 mA/V, alp= -159.35 mA3/ V 3
and measured drain shunt resistance of ^ = 3 4 .5 3 ohms, third order intermodulation
output can be predicted based on (7.9).
Fig. 7.14 shows the calculated and measured third order intermodulation products of
the drain mixer as a function o f the RF power level. The theoretical results are in good
agreement with the experimental data. The measured third order intermodulation output
collapses at input power level o f about -13 dBm due to the conduction o f the junction
diode between the gate-to-source or gate-to-drain. Even with this conduction, good
agreement between the measurement and calculation was still achieved at higher input
power levels.
Fig. 7.15 shows the measured and calculated third harmonic output versus gate dc bias
at zero drain dc bias and at LO power level of 10 mw. The poorer agreement o f
0.3 V is believed to be the calculation error o f the pumped first order a lp This can be seen
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PsrdfdBm)
-20 _
-30 -40 -
Measured
Calculated
-50 -60 -70 _
-35 -30 -25 -20 -15 -10
Figure 7.14
Pln(dBm)
-5
0
The measured and calculated third order intermodulation
o f the drain mixer.
in Fig. 4.7 o f the chapter 4. In the range of -0.0V to -0.3V, the drain shunt resistance is
also very low and thus the parasitic elements can not be neglected when developing (7.7).
The measured minimum third order intermodulation at around V 0 —0.56V was not
P3rd(dB)
10 r
j
*
Measured
-10
Calculated
-30 i
-50 \__ *
-
0.8
-■---------------------- 1 VflsO(V) i
-
0.6
-0.4
-0.2
0
i
Figure 7.15 The measured and calculated third harmonics outputs
versus the dc gate bias.
166
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observed. This is contradicting to the theoretical prediction. The reason is still unclear.
More effort is needed in making better measurements around this critical range.
Fig. 7.16 shows the measured third order IM products versus LO power at ^<,=-0.6 V
and VM =0V for a second DM. Surprisingly,
the third IM product decreases with
increasing LO power level before the conduction o f the drain-to-gate junction diode. The
reason is that, as shown in (7.9), P3rd decreases by 6 dB with the 1 dB increase o f a lp. At
the same time, P3rd only increases 3 dB with 1 dB increase o f the gain. Then the total Pird
decreases 3 dB if ldb increase-of alp causes 1 dB increase o f the gain. This phenomenon
is not observed in other type mixers.
P3rd(dB
m
V8*os - 0.6V
Vd,o*O.OV
DM:#2
•50
-55 .---------5
0
Figure 7.16
PO(dBm)
5
10
15
The third order intermodulation output power level Pird as a function o f
the local oscillation signal power level at the dc gate bias o f
and the dc drain bias o f
=-0.6 V
=0V fo r the second drain mixer.
167
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7.5 Measurement Of Conversion Gain And Noise Figure Using A Noise Figure
Meter
The measurement o f the conversion gain and noise figure o f a mixer by a noise figure
meter has to be carried out carefully because of the characteristics of the mixer and the
noise figure meter. First o f all, the image signal has to be filtered out at the input o f the
mixer. Otherwise, the measured noise figure will decrease 3 dB if the mixer has the same
frequency response at both the signal and image bands. Fig. 7.17 illustrates the spectrum
distribution o f the two signals. The noise power spectrum at the image frequency band
will be converted to the same EF frequency output . Thus the signal-to-noise ratio will
increase 2 times if the gain o f mixer is the same at both frequency bands. The worse thing
is that the different frequency response at the signal and image frequencies makes the
gain at image measured noise figure to be between the true noise figure and that minus 3
dB. Thus the
frequency band is at least 15 dB
A
below the gain at signal frequency
P(dBm)
band.
f(Hz)
fint
fo
fs
Figure 7.17 The spectrum distribution o f the
image, RF, and local oscillation signals.
The second consideration o f the measurement is that the HP 8970 noise figure meter
could only directly measure noise figure up to 1600 MHz frequency range[94]. For any
higher frequency band measurement, frequency conversion is carried out so that the
168
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measured frequency is converted to below 1600 MHz. For instance, the RF frequency of
12 GHz is converted to 1270 MHz if the LO frequency is set at 10.73 GHz. Any other
signal spectrum o f 1.270 GHz come from the noise source directly will increase the
signal-to-noise ratio o f the system. The signal spectrum of 1.270 GHz which is converted
from 12 GHz is only allowed at the input of the mixer. Therefore, a filter is needed at the
input of the mixer to filter out any signal coming out from the noise source below the
frequency o f 1600 MHz.
Fig. 7.18 shows the noise figure measurement setup. The input network is designed
to filter out the EF frequency and image frequency signals coming out from the noise
source. Two HP P281C waveguide-to-coaxial adapters are used as the filter. These
adapters have the cutoff frequency above the image frequency. The input network that
combines the adapters and a HP bias-T provides the gate bias path for the mixer. The
second bias-T is for the drain dc bias. The LO frequency is set at 10.73 GHz. The RF
frequency is varied from 11.70 GHz to 12.20 GHz. The resulting IF frequency is from
970 MHz to 1470 MHz.
Fig. 7.19 shows the insertion loss o f the input network at the RF frequency band. The
loss is eliminated using the special mode 34.1 and 34.2 of the noise figure meter. The loss
is 1±0.1 dB at 11.70~12.20 GHz band. This insertion loss o f the input network can be
measured very accurately by an analyzer.
The calibration and measurement process o f the noise and conversion gain are given
in the noise figure’s manual [94].
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H P 8 9 7 0 A N oise F igure M eter
= f l _________________ Q = -
H P 8350B O scillator
i
IF
R F+LQ .
> - Drain M ix e f^
N oise S o u rc e
Metworl
C alibration
>
o
\JH P L J
1 1 6 1 2 \B ia s T
>
VgsO
(a)
(2 )
(1), (2) HP P281C waveguide
to coaxial adapters
(3)
HP 11612Abias T
(3 ) 3
rr
VgsO
. . .
q
T o m ixer input
(b)
Figure 7.18 The setup o f the measurement o f noise figure and conversion gain.
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S 2 i
REF 0 .0
1
lip
»
j
t a
9
M A C
'
rrr~
*-♦***
dB
h
0 . 5
d B /
- I . 1 8 2 0
d B
1
1M A R < E R
s 1
1
2 . 3 1
G H z J
MARKER2
11.70 GHz
MARKER3
12.20 GHz
!
I
L
.
. !
!
I
I
1
*
i
i
I
t
f
2
^
"i
r v - ^ i
i
I
ST A R T
STOP
1 1 .0 0 0 0 0 0 0 0 0
1 3 .0 0 0 0 0 0 0 0 0
CHx
CHx
Figure 7.19 The insertion loss o f the input image rejection network.
7.6
Measurement O f Intermodulation And Conversion Gain Using A Spectrum
Analyzer
Fig. 7.20 illustrates the setup o f the intermodulation and conversion gain
measurements by a spectrum analyzer. Two 12 GHz sources of 20 MHz frequency
difference are connected to the power combiner before the attenuator. Two isolators are
used for elimination o f the interaction between the two sources. The same amplitude or
power level can be obtained at the input of the mixer by adjusting the power level o f the
two sources. The attenuator following the power combiner is for the controlling the
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power level o f the combined input signal to the mixer. The output network is connected
10.73 GHzLO
HP 8350B
Osdllatar
ttenuator
NEC
NEC
38414A
solators
38414A
solator
I1612A
aiasT
HP
Spectrum
Analyzer
VdsO
*
1
-ab-built
12 GHz
Dsdllator
HP 626A
Dstillator
f1 (GHz)
f2 (GHz)
12.000
12.020
> ■ Drain Mixer
>-
>
Calibration
HP
I1612A
3ias T
10dB
atten.
Output network
Figure 6.20 The setup o f intermodulation products and
conversion gain measurements.
to the drain dc bias-T following by a 10 dB attenuation cable. This cable assures that the
input signal to the spectrum analyzer is still relative small to prevent internally generated
harmonics by the spectrum analyzer.
The calibration is made by connecting the output network directly to the output of the
input bias T. The combined two signals can be set to the same power level at the desired
starting power levels. The measurement can then be carried out by insertion o f the mixer
between the output network and the input bias-T.
The second drain mixer is designed based on the following conditions for the minimum
third order harmonics at:
F’„ 0M ). 6 V,
^ o=0V, P0=10mw, / o=10.73GHz, f = l 1.7~12.2GHz
172
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with the substrate: DUROED 6010 £,=9.8 h=25 mils
Fig. 7.21 shows the layout o f the drain mixer. The circuit is divided into two parts, the
input gate matching network and drain matching networks.
Fig. 7.22 shows the measured noise figure and conversion gain o f the mixer.
Fig. 7.23 shows the measured IM3 o f the drain mixer.
70
♦IILO
22
I*
Figure 7.21 The layout o f the drain mixerfo r the minimum noise design.
Ga(dB)
4
Ga(dB)
□ NRdB)
0.^
800
1000
_
1200
1400
1600
IF(MHc)
Figure 7.22 The measured noise figure and conversion gain o f the mixer.
173
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Output
(dBm)
20 _
0 i
Pin (dBm)
-80
-30
-20
— Plst(dbm)
-10
_
0
P3rd(dbm)
Figure 7.23 The measured IM3 o f the drain mixer.
7.7 Conclusions
In this chapter, 12 GHz drain mixers were designed based on the QSLS model. The
method for predicting of conversion gain was developed so that the simulation software
such as Touchstone can be used to do realize the design o f the mixers. A simple and
effective method was developed for predicting the third order harmonic product of the
mixer. The intermodulation can be calculated based on the known pumped third order
coefficient aJp , mixing transconductance, and first order output power level. The
minimum third order harmonic product with higher conversion gain was identified at the
gate dc bias around -0.6V when NE33284A HEMT was used. The third order
intermodulation products decrease with the increasing LO power levels.
In addition to design a DM for maximum conversion gain, design o f a drain mixer for
the minimum IM3 was carried out.
The setup for measuring conversion gain and noise figure were illustrated in detail.
Every precaution was demonstrated and explained for the measurement accuracy.
174
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Chapter 8
Conclusions
In this thesis, design o f a new drain mixer was carried out with novel features. Double­
tuned microwave band pass filter, a new I-V characteristics for a HEMT/FET, a model
for determining harmonic coefficients of a FET, a quasi-static large signal equivalent
circuit for a mixer, a model for predicting conversion gain o f a mixer, a model for
predicting the third harmonic o f a FET mixer based on the first order output, the theory
for the stability analysis o f a FET mixer, investigation o f zero conversion gain for a gate
HEMT mixer, and the operating mechanism of the new FET drain mixer.
Double-tuned microstrip band pass filter was proposed. The microstrip filter without
loaded lumped capacitors based on the double-tuned resonant circuit has been presented.
Instead of working on tedious multi-mode design methods, one can use simple equations
developed in this work and several minutes Touchstone simulations to accurately design
a narrow band pass filter. Several DTMBPFs were built and tested at 10 GHz and 12 GHz
bands. The experimental results were in very good agreement with the theoretical
predictions. The multi-tuned microstrip band pass filter was proposed and simulated. The
Personal Communication System frequency band of 2 GHz MTMBPF was simulated.
A new I-V characteristics for a HEMT/FET was developed based on the assumption
that the drain current depends on the drain voltage through an arc-tangent function and
the drain current versus gate voltage through a hyperbolic-tangent function. When
175
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compared with Meterka’s and Angelov’s models, the new models in low Vd regions, the
Meterka’s model produces the lowest accuracy. This is followed by the Angelov’s model
which is on the average of 40.8 % more accuracy than Meterka’s model. The new model
offers an accuracy o f 76.35 % over the Meterka’s model. For all Frf>0, the Angelov’s
model is 52.1 % more accurate than Meterka’s model. The new model offers 63.8 %
more accuracy over the Meterka’s model. The new model is also suitable for modeling IV characteristics o f a GaAs MESFETs. The first order derivative is better represented by
the new model.
An experimental model was developed to measure the harmonic coefficients o f the
Volterra-Series analysis o f the gate (base) IN characteristics o f a transistor at low RF
frequency band. The coefficients were measured through various gate and drain dc biases.
The gate and first-order output voltage were measured directly instead o f measuring the
input power. Calculations related to the experimental results were developed and
comparison between the measured and modeled results were carried out.
A FET characterization procedure for a gate mixer and a drain mixer was developed.
Frequency conversion o f the gate mixer was analyzed. The mixing transconductance of
the gate mixer was calculated. The zero conversion gain was identified for certain gate
voltage. The IF currents at both sides o f this zero conversion gain have 180° phase
difference which causes this phenomenon. The mixing transconductance o f the gate
mixer tend to saturate when the amplitude o f the LO signal exceeds 0.4V. Pumped gateto-source and gate-to-drain capacitances were calculated. The quasi-static large-signal
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equivalent circuit was developed for predicting the conversion gain and for designing of
the matching networks.
Frequency conversion o f the drain mixer was analyzed for transistors assumed
symmetrical and asymmetrical I-V characteristics. The mixing transconductance o f the
drain mixer was found to have a peak value at zero dc drain bias and within the range of
-0.2V to -0.4 V of the dc gate bias. The mixing transconductance decreases with
increasing dc drain bias and becomes very small eventually. If zero dc drain bias is
selected, the least LO power is required for maximum mixing transconductance. The
mixing transconductance o f the drain mixer was found to be larger than that of the gate
mixer.
The pumped drain shunt resistance and gate-to-drain capacitance were assumed to be
the nonlinear elements for the quasi-static large-signal equivalent circuit. The pumped
gate-to-drain capacitance was modeled. The experimental determination of the pumped
drain shunt resistance and drain dc offset was developed. The quasi-static large-signal
equivalent circuit of the drain mixer was extracted.
The stability o f the gate mixer and drain mixer was theoretically analyzed based on the
pumped average transconductance. The pumped S-parameters at the RF frequency of
both the gate and the drain mixers were simulated. The stability o f the drain mixer was
relatively better than that o f the gate mixer. The capacitive load at the drain is preferred
for the gate mixer.
The drain mixer has a noise figure performance better than that of a gate mixer.
Typical noise figure o f 3 dB and conversion gain of 10 dB at LO power o f 10 dBm were
obtained in a 500 MHz bandwidth at 12 GHz. Theoretical and experimental results
177
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presented here showed that the historical conclusion “the gate mixer has an advantage
over a drain mixer” is not true.
An 12 GHz band HEMT gate mixer was designed based on the developed QSLS
equivalent circuit. The typical conversion gain of more than 8 dB with noise figure of 5.5
to 7 dB were obtained. The “zero” conversion gain was discovered and analyzed
experimentally and theoretically. Using the developed theory for prediction of IM3, the
third harmonics o f the gate mixer was compared experimentally and theoretically. The
completed setups for measuring noise figure, conversion gain, and intermodulation of the
gate mixer were described. The IM3 product decrease versus the increasing LO power
was observed and explained.
A 12 GHz drain mixer was designed based on the developed QSLS model. The
method for predicting conversion gain was developed so that simulation program such as
Touchstone can be used to do the job. A simple and effective method was developed for
predicting the third order harmonic products of any FET mixer. The intermodulation
products can be calculated based on the known pumped third order coefficient aJp ,
mixing transconductance g,, and first order output power levels. The minimum third
order intermodulation products with higher conversion gain was identified at a gate dc
bias around -0.6V when a NE33284A HEMT was used. The third order intermodulation
products decrease with the increasing LO power level.
Besides designing a DM for the maximum conversion gain, the design o f a drain
mixer with a minimum IM3 was developed.
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The setups for conversion gain and noise figure measurements were illustrated in
detail. Every precaution was demonstrated and explained for the measurement accuracy.
In this thesis, the following aspects need to be improved and to be done. In double­
tuned microstrip band pass filter, the experimental realization o f multi-tuned band pass
filter is difficult because o f high-Q of the resonators and multiple sections. The
simulation results could be off compared to experimental results. On the other hand,
higher specifications o f a filter in communication areas are required. For example, -0.5
dB insertion loss in pass band of a Personal Communication System transmitting filter is
essential with a very good stop band attenuation. Much higher quality factor is required
for the filter. Thus multi-tuned suspended striplines bandpass filter structure and multi­
tuned microstrip bandpass filter super conductor structure probably are the next step to
goThe I-V characteristics model at low temperature needs to be investigated. This is
significant because that a HEMT has a tremendous performances at very low temperature,
such as gain and noise figure.
In the prediction o f mixing transconductance o f a drain mixer, harmonics influence
needs
to
take
into
account.
The experimental determination of the mixing
transconductance o f the drain mixer could be done as shown in Fig. 8.1 at low VHF
frequencies. The 4.5 MHz signal is sent to the FET after 4.5 MHz filters. 10.5 MHz LO
signal is applied to the drain of the FET. 6 MHz IF signal is monitored by a spectrum
analyzer at the output o f the 6 MHz band pass filter. The LO power level is increased
until the IF output power level is just saturated. Then the mixing transconductance can be
determined.
179
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Gate Bias-
X
I 4.5 MHz
! Source
4.5 MHz
Filters
LO Band
Pass Filter
Gate Bias-
MHz
Band Pass
Filter
6
Spectrum
Analyzer
LO Source
(10.5 MHz)
Figure 8.1 Experimental measurement o f mixing transconductance o f a
drain mixer at low VHFfrequencies.
In the determination o f the pumped drain dc off-set and the pumped drain shunt
resistance, more theoretical effort needs to be done. In this thesis, only experimental
methods were presented.
Balance FET drain mixer will provide better gain and noise figure since the balance
structure provides better input and output return loss. The other advantage is that the
source impedance can be designed for the minimum noise figure without degrading the
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input and output return loss. Fig. 8.2 shows the suggested schematic of the balance drain
mixer.
DM
RF
Divider
90 Degree
LPF
Combiner
90 Degree
180
Degree
DM
LO
LPF
LO Band
Pass
Filter
Figure 8.2 The schematic diagram o f a balance drain mixer.
The experimental and theoretical design of a minimum noise figure of a drain mixer
needs to be investigated. The equivalent circuit for the noise analysis of a FET needs to
be determined. The analysis o f the noise parameters o f a FET such as the optimum noise
impedance needs to be derived from the equivalent circuit. The theoretical prediction
needed to be verified.
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Appendix A2-1
The Touchstone program for simulation of 11.50-12.00 DTMBPF
! * The DTMBPF of 11.50-12.00 GHz, Lt=.5 wavelength
! * File name: BPF12.ckt
! * Date:
10-18/95
! * Substrate: Duriod 5880, Er=2.2, h=l0 mils
Dim
freq ghz
res oh
ind nh
cap pf
tag mil
time ps
cond /oh
ang deg
var
wa=31.26
! 50 Ohms line width
c#3 10 15
! coupling gap
sa= 2 0 0
! tapping position
lt#350 382 400
! resonator length
16=200
eqn
lc=(It-wa-sa)* 1.018
! edge effect
sc=sa* 1.018
! edge effect
ckt
msub er=2.20 h=10 t=.7 rho= . 8 rgh=0.012
mlin 1 5
w'Hva 1A16
mlin 11 2
w^wa 1A16
maclin 4 3 6 7 w lAwa w2Awa sAc lAlc
maclin 9 8 1 0 1 2 wl'hva w2 Awa sAc lAsc
maclin 7 6 8 9 w l^ a w2Awa sAc I'Va
mtee 8 5 6 w l ^ a w2 Awa w 3^a
mtee 9 11 7 w lAwa w2 Awa wS^wa
open 3
open 4
open 10
open 12
de£2 p 1 2
freq
sweep 9 15 0.02
out
b db[sll]grl
b db[s2 1 ] grl
grid
range 9 15 0.5
grl -40 0 10
opt
range 11.496 12.05
b db[sll] < - 2 0
b db[s2 1 ]>-0 .0 1
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
Appendix A3-1
The CRS Program for Curve Fitting I/V Characteristics
of NE33284A HEMT at Vd >0
The bold areas in the program can be changed if the bias condition o f the transistor is
different. Also these area needed to be modified if the program is used for other
optimization applications.
700 PRINT "7-15/96, File Name: newne3f.bas"
800 PRINT "The F-H model with CRS optimization, VD>0"
900 PRINT " The numbers of the drain sampling voltages, o=l 1"
910 PRINT ” The gate sampling voltages,p=8 "
920 PRINT " Input the variable numbers, N="
930 INPUT n
940 PRINT "Input the trail numbers, M "
950 INPUT M
1000 0 = 11: p = 8
1010 DIM ie(o, p), it(o, p), vd(o, p), vg(o, p), a(M, n + 1), c(n), vd0(o, p)
1015 DIM d(o, p), p(n + 1, n), ct(n + 1), bu(n), bd(n), vg0(o, p)
1020 FOR i = 1 TO o
1030 FOR j = 1 TO p
1040 READ ie(i, j)
1045 vg0(i, j) = -.1 *j + .l
1050 NEXT j
1060 NEXT i
1070 DATA 0,0,0,0,0,0,0,0,16,14.85,13.20,11,7.8,4.42,1.54,.13
1071 DATA 30.26,27.52,24,19,12.67,6.33,1.64,.258
1072 DATA 41.67,37.38,31.66,24.29,15.89,7.76,1.9,0J9
1073 DATA 50.13,44,36.48,27,17.56,7.87,1.92,.52
1074 DATA 5538,48.1238.9138.42,18,8,2.23, .65
! Measured I-V data
1075 DATA 583930.4,40.77,29.62,1839,7.69,23,.77
1076 DATA 60.26,5134,4135,30.51,18.59,7.63,2.56,.903
1077 DATA 60.96,52.56,423 30.89,18.59,7.123.60,1.22
1078 DATA 61.63,53.07,42.9531.67,18.85,7.443.08,1.28
1079 DATA 62.6933.84,43.9531.96,18.97,7.53.59,1.29
1082 FOR i = 1 TO o
193
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1084 FORj = 1 TO p
1085 vd0(i, j) = i * .1 - .1
1090 vd(i, j) = vd0(i, j) - ie(i, j) * .00413 ! parasitic resistance effect on drain voltage
1120 NEXT j
1125 NEXT i
1130 FOR i = 1 TO o
1132 FORj = 1 TOp
1134 vg(i, j) = vg0(i, j) - ie(i, j) * .00113 ! parasitic resistance effect on gate voltage
1137 NEXT j: NEXT i
1150 PRINT "input the bounds of the varibles,xlL,xlU,x2L,x2U,..."
1160 FOR i = 1 TO n
1170 INPUT bd(i), bu(i)
1180 NEXT i
1190 PRINT "Input the maximum calculation number, TN"
1200 INPUT TN
2000 FOR i = 1 TO n
2020 FORj = 1 TO M
2025 RANDOMIZE TIMER
2030 a0, i) = RND * (bu(i) - bd(i)) + bd(i)
2040 NEXTj
2050 NEXT i
3000 FOR i = 1 TO M
3020 hi = a(i, 1): h2 = a(i, 2): h3 = a(i, 3)
3025 vpk = a(i, 4): a2 = a(i, 5)
3030 GOSUB 5000
3040a(i,n+l) = e0
3060 NEXT i
3070 d2 = 0: FOR i = 1 TO M
3080 IF a(i, n + 1) < d2 THEN 3100
3090 iO= i: d2 = a(i, n + 1)
3100 NEXT i: PRINT : PRINT d2;
3120 FOR i = 1 TO n + 1: tl = tl + I
3130 RANDOMIZE TIMER
3140 jO = INT(RND * M) + 1
3142 FORj = 1 TO n: p(i, j) = aQO, j)
3145 NEXTj: NEXT i
3150 FORj = 1 TO n
3152su = 0: FORi = 1 TOn
3154 su = p(i, j) + su: NEXT i
3156 c(j) = 2 * su / n - p(n + I, j): NEXTj
3158 FOR i = I TO n
3160 IF c(i) < bd(i) THEN 3120: IF c(i) > bu(i) THEN 3120
3162 NEXT i
3165 hi = c(l): h2 = c(2): h3 = c(3): vpk = c(4): a2 = c(5)
3170 GOSUB 5000
194
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3175 IF e0>d2 THEN 3120
3180 a(i0, n + 1) = eO: d2 = eO
3185 FOR i= 1 TOn
3190 a(iO, i) = c(i)
3200 NEXT i
3215 PRINT tl;
3218 IF tl >= TN THEN 3230
3220 GOTO 3070
3230 FOR i = I TO M
3240 IF a(i, n + 1) > d2 THEN 3260
3250 d2 = a(i, n + 1): iO= i
3260 NEXT i
3270 PRINT : PRINT " Idss"; " al"; "
Alpha”;
3275 PRINT"
vpk";" a2";"
e0"
3280 FOR i = 1 TO n
3290 PRINT a(i0,i);
3300 NEXT i: PRINT d2 / (o * p): PRINT
3302 hi = a(i0,1): h2 = a(i0,2): h3 = a(i0,3): vpk = a(i0,4): a2 = a(i0,5)
3304 GOSUB 5000
3305 FOR i = I TO o: FORj = 1 TO p
3306 PRINT it(i, j); ie(i, j);
3308 NEXTj: NEXT i
3310 END
5000 dO = 0: FOR g = 1 TO o
5010 FOR h = I TO p
5020 x = h2 * (vg(g, h) - vpk): GOSUB 7000: yl = a2 * y +1
5025 x = h3 * vd(g, h): y = ATN(x)
5026 it(g, h) = hi * yl * y
5030 d(g, h) = ABS(it(g, h) - ie(g, h))
5035 dO = d(g, h) A 2 + dO
5036 NEXT h: NEXT g
5039 eO = SQR(dO)
5080 RETURN
! I-V model
7000 y = (EXP(x) - EXP(-x)) / (EXP(x) + EXP(-x)): RETURN
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Appendix A4-1
The Programs for Determination of harmonic coefficients a,, a2, and a3
1. Theoretical prediction of a„ a2, and a 3 using the new I/V model
The bold areas in the program can be changed if the bias condition of the transistor is
different or for different transistors. The name of the program: Volterra.bas
1000 PRINT "Program for calculation of Volterra coefficients"
1005 DIM a(3,9), vgs(9)
1006 PRINT "input the drain dc bias in Volts"
1007 Vds = . 5
1010 READ al, a2, Ipk, al, vpk
1020 DATA 3.48,1.1,24.12,10.86,-.27
L025 cl = Ipk * al * a2 * ATN(al * Vds)
1027 PRINT" al"," a2", " a3"
1030 FOR i = 1 TO 9
1035 vgs(i) = -.1 * i + .1
1050 x = al * (vgs(i) - vpk)
1060 GOSUB 5000
1070 c2 = y
1080 a(l, i) = cl * (I - c2 A2 )
1090 a(2, i) = -al * cl * c2 * (1 - c2 A2)
1100 a(3, i) = -al A2 * cl * (1 - c2 A2) * (1 -3 * c2 A2) / 6
1110 PRiNT : PRINT a(l, i), a(2, i), a(3, i)
1120 NEXT i
1130 END
5000 y = (EXP(x) - EXP(-x)) / (EXP(x) + EXP(-x))
5060 RETURN
2. Experim ental predictions
As shown in chapter 4, the amplitude o f the first order can be measured directly for a
given load o f low value resistor at the drain o f the transistor. However, the spectrum
analyzer’s reading P^is not the power PL consumed on the load. The relationship
between the PL and Pu is fixed with regardless o f different dc bias.
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The PL and 8 =PL-Pu can be determined from the measured amplitude o f the first
order output V, , R L, and Pu by the following program:
The name o f the program: Vltra-pI.Bas
1000 PRINT "Program for calculation of PI from measured VI"
1005 PRINT "RL—test drain lord resistor (3.9 Ohms)"
1010 PRINT "VI(i)—measured first-order output"
1020 PRINT ”pl(i)—analyzer reading of the first-order component across the RL"
1030 PRINT: PRINT
1040 PRINT "input RL (Ohms)": PRINT
1045 INPUT RL
1048 N = 8
1050 DIM p(N), pl(N), vl(N)
1060 FOR i = 1 TO N
1070 READ vl(i)
1080 NEXT i
1090 FOR i = I TO N
1100 READ pl(i)
1110 NEXT i
1120 FOR i = 1 TO N
1130 p(i) = -39.031 + 20 * LOG(vl(i)) / LOG(IO) - 10 * LOG(RL) / LOG(IO)
1150 PRINT "PL(i)="; p(i)
1160 NEXT i: PRINT
1170 FOR i = 1 TO N
1180 d(i) = p(i) - pl(i)
1190 PRINT ”d(i)=";d(i)
1200 NEXT i: PRINT
1210 DATA 21,26,29,30-5,28,20.5,11.2,3.6
1220 DATA -31.46,-28.19,-27.26,-27.33,-29.43,-3U 5,-37.2,-46.92
1230 END
The experimental harmonic coefficients a,, a2, and a 3 then can be determined by
the following program:
Name o f the program: Vltrahmo.Bas
5 PRINT "**********•***************************************•*********************
10 PRINT "The program for determination al, a2, and a3 "
20 PRINT " from measured VI ,p 1a,p2a,and p3a"
30 PRINT "VI-measured first order peak-to-peak amplitude(mV)"
197
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40 PRINT "Pla, p2a, and p3a-tneasured harmonic power levels from s-analyzer(dBm)"
45 PRINT "Vgs-the input 1 MHz signal peak-to-peak amplitude (mV)"
46 PRINT "RL—the test drain load (3.9 Ohms)"
48 PRINT "Rs—the source parasitic resistance (Ohms)"
50 PRINT "dl—the cal factor: the difference between the measured and practical power on RL"
55 PRINT
60 PRINT: PRINT: PRINT "input RL, Rs (Ohms)": PRINT
65 INPUT r, rs
70 PRINT: PRINT "input power cal. factor dl(dB)": PRINT
80 INPUT dl
85 N = 8
90 PRINT: PRINT "input the Vgs (mV)": PRINT
95 INPUT vgs: vgs = vgs / 2.828
96 PRINT: PRINT : PRINT "The final results are:": PRINT
98 PRINT "_______________________________________________________________ "
100 DIM a(N), p(N), vl(N), p2(N), p3(N), kl(N)
105 PRINT "al:": PRINT
110 FOR i = 1 TO N
120 READ vl(i): vl(i) = vl(i) / 2.828
130 al(i) = 1000 * vl(i) / (vgs * r - vl(i) * rs)
140 PRINT al(i); " ";
150 NEXT i: PRINT : PRINT
1000 V0 = .001 * vgs
1020 PRINT "a2:"
1026 FO R i=l TON
1028 kl(i) = 1 0 0 0 * r/ (vgs * r - vl(i) * rs)
1040 READ p2(i)
1050 p(i) = p2(i): GOSUB 5000
1060 PRINT b(i) * (kl(i)) A2;" ";: NEXT i
1062 PRINT : PRINT : PRINT "a3:"
1066 FOR i = 1 TO N
1070 READ p3(i)
1080 p(i) = p3(i): GOSUB 5000
1090 PRINT b(i) * (kl(i))A3;"";
1100 NEXT i
1108 PRINT: PRINT "_______________ :___________________________________ "
1110 DATA 21,26,29,30.5,28,20.5,11.2,3.6
! VI - The first order output voltage
1200 DATA -63.61,-62.5,-69.16,-95.28,-66.6,-59.83,-59.27,-64.2 ! Power of the 2nd order output
1220 DATA -104,-94.04,-90.44,-89.17,-884,-91.02,-96.22,-87.77 ! Power of the 3rd order output
1230 END
5000 b(i) = 1000 * SQR(10 A((p(i) + dl) / 10) / (1000 * r)): RETURN
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Appendix A5-1
1. The Touchstone program for extraction of the parasitic elements from measured
“cold” S-parameters.
! fet "cold" equivalent circuit 3-27/96
! file name: clne3tro.ckt
! FET: NE33284A with Vds=0, Vgs0=-0.50 V
DIM
FREQ GHz
RES OH
INDNH
CAP PF
LNG MIL
TIME PS
COND /OH
ANGDEG
VAR
K0\0.07600 ! THE CHANNEL CAPACITANCE
S0\3.87738 ! THE CHANNEL RESISTANCE
CKT
SRL 1 9 R#0.01 0.01505 5 L#0.01 0.44653 1 ! Rg, Lg
CAP 10C#0.001 0.11157 1 ! Cg
CAP 3 7 C#0.00001 0.00004 1 ! Cds
CAP 9 3 CAK0
CAP 9 4 CAK0
CAP 9 5 CAK0
CAP 9 7 CAK0
SRL 7 6 R#1 3.00 5
L#0.01 0.59035 1 !Rd,Ld
SRL 3 0 R=1.13
L#0.01 0.11094 1 !Rs,Ls
RES 3 4 RAS0
RES 4 5 RAS0
RES 5 7 RAS0
CAP 6 0C#0.001 0.13857 1
DEF2P 1 6 A ! A IS THE CIRCUIT MODEL OF THE fet
S2PA 1 2 0 ne3trmco S-PARAMETERS MEASURED
DEF2P 1 2 B ! B IS THE ACTUAL FET
FREQ
SWEEP 3 16 .5
! SWEEP 3 16 1! USE THIS AS A DISPLAY
OUT
IDISPLAY SI 1, S22, S21, S12 ON SC2
asll
bsll
a s2 2
199
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b s2 2
OPT
A MODEL B ! OPTIMISATION OF FET MODEL A AS CLOSE AS MODEL B
2. The Touchstone program for extraction of the parasitic elements from measured
“hot” S-parameters.
! fet gm equivalent circuit 4-4/96
! file name: ne3hogmr.ckt
! FET: #1 NE33284A with Vds=2.0V, Vgs0=-.80 V
DIM
FREQ GHZ
RES OH
INDNH
CAP PF
LNG MIL
TIME PS
COND /OH
ANGDEG
CKT
SRL 1 2 R=0.0I5
L=.4465
! Rg, Lg
CAP 10 C#0
5.403e-06
1
! Cg
CAP 2 3 C#0.01
0.02834 1
!Cgd
cap 2 4 c#0.01
0.15130 1
!Cgs
CAP 3 5 C#0.01
0.14382 0.9
!Cds
res 4 5 r#0.1
0.11470 10
!Ri
SRL 3 6 R =3
L=.5904
!Rd£d
SRL 5 0 R= 1.13
L=0.1109
!Rs,Ls
CAP 6 0 C#0 0.00227 I
VCCS 2 3 4 5 m#0 0.00997 1 A=0 rl=le + 6 r2\3.243e+03 f=8.4E101=2
DEF2P 1 6 A ! A IS THE CIRCUIT MODEL OF THE fet
S2PA 1 2 0 ne33gmxr ! S-PARAMETERS MEASURED
DEF2P 1 2 B ! B IS THE ACTUAL FET
FREQ
SWEEP 11 13 .1
! SWEEP 11 13 .5 ! USE THIS AS A DISPLAY
OUT
1DISPLAY SI 1, S22, S21, S12 ON SC3
ASll
bSll
A s22
b S22
OPT
A MODEL B ! OPTIMISATION OF FET MODEL A AS CLOSE AS MODEL B
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Appendix A5-2
The calculation o f gate mixer mixing transconductance using Mathcad
File Name: gm33gm.mcd
T he NE33284A p aram eters with new model
9.954 Ipk
a
24.53 vpk - .30 A 1 =4.0
A2 =1.088
The g a te and drain b ia s e s are:
g ate:
j =0..8
drain:
vdO
vgsO^ - 0 .1-j
2
T he LO signal am plitudes in volts:
k -1.. 10
v0 =k-0.l
k
T he angular frequency tim es time of the LO signal:
i =1.. 100
a t. =0. t-i
T he pum ped gate total voltage:
><vgsO,vO,cot) =v0 cos(tut) - vgsO vgSj =xl'vgs00,v02,o)t.j
xKvgsO.vO.ojt) = <D(-(j<vgsO,vO,oit) - 0.5))-<vgs0,v0,(at) r <t>(<vgsO,vO,cot) - 0.5)-0.5
T he drain current:
id(vgs0,v0,(Bt) = Ipk-( I r A2-tanh(Al-(xl(vgsO,vO,oit) - vpk)))-atan(a-vd0)
id. = id(vgsO,,v05,o)t.)
T he transconductance:
g(vgs0,v0,G)t) = Ipk-AI-A2-[l - (tanh(Al(xI(vgsO ,vO .cot) - vpk))) J-atan(a-vdO)
T he mixing transconductance is:
f*
g(vgsO,vO.Mt)
HXvgsO.vO) = I
«-R
2*
gOk =ro(-.8,vOk)
g(vgsO.vO.mt)
f(vgs0,v0) =
gOOj =ro( vgsO.,0.6)
cos (cot) dot
J-,
glj 4 =f(vgs0.,v04)
i
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
■
i.*
-32.416
-37.814
-26.431
- 1 .9.
-44.112
- 34.365
-18.216
-2.99510 " -8.05410 12
26.431
18.216
37.814
3 4 J6 5
32.416
44.112
- 0 .1
20.65
42.717
-0.8
11.058
31.769
glj 6 =f(vgs0r v06'
g>LS..
-28.466
18.532
9.023
-1.72810''
9.023
18.532
28.542
37.698
42.396
"0 75
-0.5
-0 25
0
*S»0.
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The average of the pumped transconductance:
v°k
S°k
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
13.14(
18.55<
28.302
41.25^
52.362
55.825
51.73*
44.582
37.71'
32.20*
60
48
36
24
12
0
0.S
0
vO,
The pumped transconductance wave form (normalized to 100 mA/VA2) at different gate dc biases:
g|Vgs00,v04,o)t.!
Sa;
100
g:'vgs03,v04,a)t.i
g! vgs0g,v04,«Dt)
gb-
gc.
1
100
1
100
v g s.
-0.5
0
4
2
6
10
8
Otj
100
id.i
-20
-so
0
2
4
6
8
10
Otf
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Appendix A5-3
The extraction of the small signal equivalent circuit for the drain mixer
! fet DM equivalent circuit 5-15/96
! file name: hotn3trm.ckt
! FET: #1 NE33284A with Vds=0.0V, Vgs0=-.50 V
DIM
FREQ GHZ
RES OH
IND NH
CAP PF
LNG MIL
TIME PS
COND /OH
ANG DEG
var
Rg=
0.015
Ri#0.1
1.00239
10
Rs=
1.13
Rd=
3
Rdst=
14.21
Lg=
0.4465
Ls=
0.1109
Ld=
0.5904
Cg=
0.1116
Cgd#0.0l
0.14545
1
Cgs#0.01
0.15913
1
Cds#0.01
0.01195
1
Cd=
0.1386
eqn
Rds=rdst-Rd-Rs
CKT
SRL 1 2 RARg LALg
CAP 1 0 CACg
CAP 2 3 CACgd
cap 2 4 c*C gs
CAP 3 5 CACds
res 4 5 ^Ri
SRL 3 6 R ARd LALd
SRL 5 0 R ARs LALs
CAP 6 0 CACd
VCCS 2 3 4 5 m=0.0
A=0 rl=Ie+6 r2ARds
£=10E10t=2
DEF2P I 6 A ! A IS THE CIRCUIT MODEL OF THE fet
S2PA I 2 0 ne3trmco ! S-PARAMETERS MEASURED
DEF2P 1 2 B ! B IS THE ACTUAL FET
FREQ
SWEEP 3 16.2
! SWEEP 3 16 1 ! USE THIS AS A DISPLAY
OUT
!DISPLAY SI 1, S22, S21, S12 0N SC3
AS11
b SI 1
A S22
b S22
OPT
A MODEL B ! OPTIMISATION OF FET MODEL A AS CLOSE AS MODEL B
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Appendix A5-4
The measured average large signal drain shunt resistance RA
The measurement setup refers to Fig. 5.19 o f chapter 5. Here, RdsO and K3s are the
small signal and pumped values o f R ^ . VdO is the drain pumped voltage offset.
Po=10 dBm, fo=10.730GHz.
(Rdso/RWVdo)
VdsO\VgsO(V)
0
-.1
-.2
-.3
-.4
-.5
-.6
-.7
0
5.027/7.
39/0.035
5.36/9.7
1/.06
7.46/16.
08/.449
5.89/13.
66/0.119
9.35/19.
40/.52
6.98/17.
87/.204
13.36/22
.59/.520
33.18/33
.14/0.82
9.03/24.
25/.316
22.28/28
.30/.52
51/36.2/
0.727
80.23/44
.08/0.88
96.21/52
.12/1.00
103/61.5
/ l . 121
14.21/38
.66/.426
46.24/38
.83/.451
81.9/42.
23/.636
106.6/50
121.67/5
9.5/0.92
127.5/75
.55/1.05
32.26/51
.0/.547
118.98/5
2.28/.57
157.71/5
2.43/.57
176.41/6
0.34/0.7
190.24/7
3.9/0.84
196/99.4
3/0.974
167.62/7
6.50/.66
455.83/7
8.07/.69
470/80.7
1/0.71
460/79.5
6/0.713
459.69/8
7.4/0.75
451/126/
0.96
.2
.4
.6
.8
1.0
Po=8dBm, fo=l0.730GHz.
10.116
(R dso/R ds/V do)
VdsoWgsO (V)
0
-.1
-.2
-.3
-.4
-.5
-.6
-.7
0
5.027/6.
09/0.01
5.36/7.8
4/0.03
7.46/14.
67/0.37
5.89/10.
19/0.1
9.35/19./
0.415
6.98/15.
02/0.12
13.36/21
.54/0.44
33.18/34
.2/0.73
9.03/20.
39/0.21
22.28/26
.54/0.43
51/38.40
/0.621
80.23/50
/0.771
96.21/64
.35/0.92
103/82.6
7/1.075
14.21/34
.66/0.31
46.24/34
.38/0.40
81.9/43.
8/0.561
106.6/56
.9/0.705
121.67/7
9.3/0.87
127.5/10
8.1/1.02
32.26/50
/0.418
118.98/4
9.5/0.44
157.71/5
2.4/0.47
176.41/6
9.2/0.65
190.24/1
00/0.795
196/176.
19/0.96
167.6/77
.38/0.53
455.83/8
1.4/0.56
470/83/0
.574
460/87.3
4/0.60
459.7/13
8.2/0.78
451/—
/0.937
.2
.4
.6
.8
1.0
204
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
Po=6.0dBm, fo=10.730GHz.
(Rdso/kjs/Vdo)
VdsoWgso(V)
0
-.1
-.2
-.3
-.4
-.5
-.6
-.7
0
5.027/5.
48/0.007
5.36/6.2
9/0.012
7.46/13.
07/0.293
5.89/7.9
9/0.025
9.35/16.
35/0.34
6.98/12.
57/0.065
13.36/20
.23/0.37
33.18/33
.53/0.64
9.03/19.
12/0.13
22.28/25
.39/0.37
51/37.83
/0.575
80.23/52
.16/0.73
96.21/71
.92/0.89
103/89.7
/ l . 056
14.21/28
.69/0.22
46.24/34
.65/0.35
81.9/46.
71/0.50
106.6/67
.0/0.66
121.7/10
0.5/0.83
127.5/12
4/1.017
32.26/47
.1/0.312
118.98/4
8.0/0.33
157.71/6
1.3/0.46
176.41/9
0.7/0.61
190.24/1
70/0.78
196/229.
34/0.98
167.6/80
.54/0.41
455.83/8
6.9/0.45
470/90.2
3/0.46
460/144.
7/0.62
459.69/2
66/0.773
451/—
/0.947
.2
.4
.6
.8
1.0
Po=3.0dBm, fo=10.730GHz.
(Riso/ftW Y do)
VdsoWgsO (V)
0
-.1
-.2
-.3
-.4
-.5
-.6
-.7
0
5.027/5.
25/0.003
5.36/5.7
2/0.005
7.46/9.6
7/0.24
5.89/6.7
2/0.01
9.35/13.
86/0.27
6.98/9.1
5/0.024
13.36/18
.85/0.29
33.18/33
.75/0.54
9.03/14.
93/0.055
22.28/24
.93/0.30
51/40.72
/0.50
80.23/61
.3/0.67
96.21/83
.34/0.84
103/100/
1.034
14.21/25
.53/0.12
46.24/35
.43/0.29
81.9/55.
72/0.45
106.6/89
.14/0.63
121.7/11
5.7/0.82
127.5/13
0/1.018
32.26/45
.4/0.20
118.98/4
9.3/0.23
157.71/8
3.4/0.42
176.41/1
64.2/0.6
190.24/2
09.7/0.8
196/217/
0.994
167.6/89
.76/0.29
455.83/9
6.2/0.31
470/133.
64/0.40
460/400/
0.62
459.7/51
0.9/0.78
451/504/
0.982
.2
.4
.6
.8
1.0
Po=6.0dBm, fo=10.730GHz.
(R dso/Rds/Vdo)
VdsO\VgsO(V)
0
-.1
-.2
-.3
-.4
-.5
-.6
-.7
0
5.027/5.
06/0.001
5.36/5.4
5/0.002
7.46/8.3
7/0.215
5.89/6.2
5/0.004
9.35/11.
24/0.23
6.98/7.8/
0.01
13.36/16
.8/0.25
33.18/34
.2/0.48
9.03/11.
52/0.022
22.28/24
.26/0.26
51/44.5/
0.45
80.23/70
.21/0.64
96.21/90
.8/0.82
103/102.
9/10.32
14.21/22
.07/0.06
46.24/38
.6/0.25
81.9/67.
6/0.44
106.6/10
1.9/0.62
121.67/1
20.8/0.8
127.5/13
3/1.033
32.26/44
.38/0.12
118.98/6
2.3/0.22
157.71/1
26.9/0.4
176.41/1
92/0.6
190.24/2
04.7/0.8
196/214.
7/1.00
167.62/1
03.4/0.2
455.8/12
2.7/0.24
470/354/
0.412
460/508/
0.622
459.69/4
96/0.79
451/503/
0.995
.2
.4
.6
.8
1.0
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
Appendix A5-5
The calculation of drain mixer mixing transconductance using Mathcad
g1 vs. VgsO
The parameters of the N E33284A :
a -9.953
ipk -24.53 vpk " .3
is "74.251
Air " 1.518
j
" 1.. 8
A l "4.00
ar "9.346
A2
vp "-.556
1.088
Im = 1.00
vgsOj = . l j - . I
The power levels of the LO signal
pO "0. 01
The measured drain dc offset and resistance:
x "vgsO.-0 .0 2
j
j
vdO,I =.035
vdO,2 =.06
vd0? =.547
vd0g =.665
vdO,3 =.119 vdO,4 =.204
rd.I =7.39
rd,2 =9.71rd, = I3.66rd,
=17.87
3
4
rd7 =51
rdg =76.32
vdO,5 =.316
rdc =24.25
5
vdO6 =.426
rdf =38.66
6
The amplitute of the drain LO signal:
pl ( rd)
=! I — j ——
L
| p0
vl ( rd) = V 2 p l(r d )r d
v 0 (r d ) = — — ^ - ^ v l ( r d )
\ rd -s- 34.66/ j
rd
where 4.13 is Rd+Rs
The drain total voltage:
vd(t,rd,vd0) = vdO +■vO(rd)cos(t)
The mixing transconductance:
Let:
sl(t,rd ,v d 0 ) =avd(t,rd ,vd0)
s(t,rd,vd0) =sl(t,rd,vd0)-<t>(sl(t,rd,vd0))
The mixing transconductance contribute by IN characteristics in Vd>0:
ff r d ,v d O ,x ,n ) = i
j
gf. =f(rd.,vd0j , x , l )
^
i -1 - ta n h (A l ( x - v p k ) ) 2 J atan_( s ( t ,r d ,v d O ) ) ^
^
n) ±
t-2
gfO. = fi rd., vdO^x.O)
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The mixing transconductance contribute by l/V characteristics in Vd<0:
s2(t,rd,vd0) =arvd(t,rd,vdO)<D ( - vd(t,rd,vd0))
a ta n ^ tt.rd .v d O lJA lr-i 1 -
tan h i A ir- x - v p - l m
ar
k(rd,vdO,x,n)
gr.
e J
J
J
grO. -k/rd.,vd0.,x,0'
/
6
1
\
The total mixing transconductance:
vgsO,- gfj
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
gr-
8.291
19.141
34.685
44.596
40.591
28.305
15.521
7.724
8.214
12.65*
16.35
18.841
21.03
24.83:
26-71
28.93:
gli .
16.505
31.8
51.035
63.446
61.621
53.13'
42.231
36.65'
-2
--is-cos(t-n) dt
it -2
k rd., vdO.,x, 0
J
s2 (t,rd ,v d 0 )
3
J
.
Blj =gf-8r.
rd.
vdO.
7.39
9.71
13.6(
17.87
24.25
38.6(
51
76.37
0.035
0.06
_L
3
_L
0.111
0.204
0.316
0.426
0.547
0.665
40
-
0.8
-
-0.4
0.6
-
0.2
0
vgsOj
The average of the pumped transconductance:
g0. = gfO. - grO.
vgsO.
i
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
gO
___...
2.279
13.971
38.306
60.855
59.882
31.194
5.305
-14.245
gfO.
J
12.171
29.397
58.027
82.841
83.767
59.815
35.39:
18.217
grO.
j
-9.9
-15.427
-19.727
-21.994
-23.871
-28.621
-30.087
-32.462
100
gffl
so
» ° i 25
go.
-25
-50
-
0.8
-
0.6
-0.4
-
0.2
0
vgsO.
207
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Appendix A7-1
The Touchstone program for prediction of conversion gain of DM
! fet DM
i
5-22796
* *** * * * * * * * * * *
! file name: * dm0596t.ckt *
i
* * * * * * * * * * * * * *
! FET: #1 NE33284A
DIM
FREQ GHZ
RES OH
IN D N H
CAP PF
LNG MIL
TIME PS
COND /OH
ANG DEG
var
wa=
55
wb=
10
lb=
200
lt=
392
! lt#385 392 450
sc=
212
! sc# 180 212 250
c=
60
! width o f the 50 ohms lines
! width o f the IF output lines
! length o f the IF output line
!! length o f the LO filter resonators
! taping points o f the DTMBPF
! coupling gap o f the DTMBPF
!wd#55 61.29772 65
! width o f the shunt stubs
wd=60
12#3 10
50
! distance between drain and the LO DTMBPF
! 12=20
11#250 285
300
! distance between gate and the shunt
! 11=275
! lu=
70
! length o f the shunt stub
lu#55 70 85
195
ldo#130
250
! length o f the shunt stub
! ldo=200
Cif=
1
! IF port matching capacitor
i
Rg=
Ri=
Rs=
Rd=
Lg=
Ls=
Ld=
Cg=
Cd =
Cds=
0.015
1
1.13
3
0.4465
0.1109
0.5904
0.1116
0.1386
0.012
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! The following three elements' values are changed with the bias, power levels
Rdst=
Cgd=
Cgs=
38.66
0.118
0.159
eqn
Rds=rdst-Rd-Rs
sa=sc*1.018
la=lt-sc-wa
10=580-ll-wd
CKT
msub er=2.45 h=20 t=l rho=l rgh=.012
1UL2000
mlin 1 3 wAw a 1AI0
mcros2 3 4 5 6 w l Awa w2Awd w3Awa w4Awd
m lef 4 w 'V d lAlu
m lef 6 w^wd lAldo
mlin 5 10 w'Nva 1A11
def2p 1 10 input
mlin 1 7 w Awa IA12
mtee 8 7 9 w l Awa w2Awa w3Awa
maclin 17 16 8 18 w l Awa w2Awa sAc lAla
maclin 19 9 23 20 w l'V a w2Awa sAc lAsa
maclin 18 8 9 19 w l'V a w2Awa sAc l^wa
mtee 18 21 19 w l'V a w2Awa wS'Va
mlin 21 22 w ^ va IA10
m lef 8 w 'V a lAla
m lef 18 w ^ a lAla
m lef 19 wAwa lAsa
m lef 9 w V a lAsa
def2p 1 22 LO
input 1 10
SRL 10 11 RARg LALg
CAP 10 0 C * C g
CAP 11 14 C 'C g d
cap 11 12 t^Cgs
CAP 14 13 C 'C ds
res 12 13 r'Tli
SRL 14 15 R ARd LALd
SRL 13 0 R ARs LALs
CAP 15 0 CACd
VCCS 11 14 12 13 m= .02475 A=0 r l= le + 6 r2ARds f=10E10t=2
VCCS 11 24 12 25 m =0.0532 A=0 r l= le+ 6 r2ARds f=10E10 t=2
LO 15 16
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match 16
sr!25 Oi^rs 1=0.0117
srl 24 26 r^rd 1=0.0629
mlin 26 2 w*wb 1=21.16
cap 2 0 c=0.106
DEF2P 1 2 DM
i* * * * * * * * * * * * * * * * * * * * *
FREQ
sweep 11.7 12.2 0.05
!sweep 10 11.5 0.01
[sweep .5 2 0.01
OUT
d m d b [sll] grl
dm db[s21] grl
dm db[s22] grl
dmre[z2] gr2
dm im[z2] gr2
d m im [zl] gr2
dm re[zl] gr2
! LO d b [sll] grl
! LO db[s21] grl
grid
range 11.7 12.2 0.1
[range 10 11.5 0.15
[range .5 2 .15
grl -50 50 10
gr2 -100 100 20
OPT
range 11.80 11.83 1
dm db[s21]=12
d m d b [sll]< -8
range 11.7 11.8
dm db[s21]=8
2
range 12.0 12.2
dm db[s21]=8
2
! range 10.72 10.74
! LO db[s21]>-0.1
1
! LO d b [sll]< -20
2
! range 10 10.70
! LO d b [sll]> -0.5
3
! LO db[s21]<-5
3
! range 10.76 11.5
! LO d b [sll]> -0.5
3
! LO db[s21]<-5
3
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Appendix A7-2
T he m easured specifications of the drain mixer #1
1. By H P 8970A Noise Figure M eter
File Name:
5-24/96 .xls
Vgso - Gate dc bias
Vdso • Drain dc bias
Vdo - Drain dc component due to LO
fo - LO frequency
Date: 5-24/96
FET: NE33284 #2.
Po - LO power
G - Conversion gain
NF - N oise figure
1. Gain and NF vs. Frequencies
Bias conditions: V gso=-0.5 V, Vdsos 0V
LO
conditions:
3 Hz)
11.53
11.55
11.57
11.59
11.61
11.63
11.65
11.67
11.69
11.71
11.73
11.75
11.77
11.79
11.81
11.83
11.85
11.87
11.89
11.91
11.93
11.95
11.97
fo =
G1-Plo
G2-Plo
=13dBm =10dBm
10.730
GHz
G3-Plo
=0dBm
IF(MHz) G1
NF1
G2
NF2
G3
800
9.16
3.41
8.8
3.37
9.07
3.43
8.78
820
3.4
9.06
3.47
8.8
3.44
840
9.12
3.48
8.76
3.46
860
880
9.18
3.46
8.82
3.42
900
9.58
3.43
8.88 ' 3.38
9.37
10.2
920
3.26
3.21
10.56
3.16
9.82
3.09
940
3.07
10.27
960
11.08
3.02
11.54
2.95
10.83
980
2.91
11.34
11.92
2.96
1000
2.92
2.95
11.72
1020
12.41
2,92
13.23
2.99
12.16
1040
2.96
1060
13.45
3.02
12.87
2.99
13.76
3.07
1080
12.98
3.03
13.52
3.05
13.12
1100
3.02
12.64
1120
12.85
3.02
3.05
12.42
1140
3.02
12.07
2.99
12.54
3.13
1160
11.67
3.13
1180
12.55
3.19
11.59
3.05
11.7
3.14
1200
11.46
3.03
11.73
1220
3.11
10.56
3.08
11.27
1240
2.99
3.11
10.47
NF3
3.18
3.62
3.55
3.18
3.3
3.25
4.03
4.39
3.94
4.52
4.73
5.09
5.32
4.96
5.01
4.61
4.56
3.84
3.87
3.82
3.62
3.61
3.88
4.22
4.37
4.4
4.45
4.48
4.34
4.12
4.09
3.9
3.96
3.96
3.84
3.87
3.87
4.23
4.52
4.69
4.61
4.56
4.3
4.36
4.33
4.22
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
11.99
12.01
12.03
12.05
12.07
12.09
12.11
12.13
12.15
12.17
12.19
12.21
12.23
12.25
12.27
12.29
12.31
12.33
1260
1280
1300
1320
1340
1360
1380
1400
1420
1440
1460
1480
1500
1520
1540
1560
1580
1600
11.25
10.99
10.52
10.52
10.92
10.85
10.34
9.98
9.93
9.92
10.29
10.44
10.23
10.54
10.56
9.69
9.79 9.38
2.91
2.81
2.92
2.99
3.1
3
3.05
3.28
3.29
3.19
3.22
3.24
2.99
3.06
3.2
3.11
3.27
3.6
10.4
10.37
10.09
9.95
10.15
10.03
9.63
9.32
9.14
9.16
9.62
10.08
9.99
9.91
9.34
8.63
8.7
8.35
3.2
2.88
2.98
3.05
3.15
3
3.07
3.3
3.26
3.15
3.22
3.22
2.98
3.11
3.27
3.14
3.32
3.68
3.64
4.02
3.73
4.09
3.89
3.45
3.86
3.5
3.42
3.5
3.69
3.09
2.67
3.52
2.61
2.85
2.99
2.58
4.07
4.01
4.03
4.15
3.9
3.54
4.08
3.93
3.58
3.75
4.3
3.82
3.23
4.33
4.09
3.8
4.01
4.67
Bias conditions: Vg*o=-0.3 V, Vdso= OV
LO conditions: fo = 10.730 GHz
3Hz)
11.53
11.55
11.57
11.59
11.61
11.63
11.65
11.67
11.69
11.71
11.73
11.75
11.77
11.79
11.81
11.83
11.85
11.87
11.89
11.91
IF(MHz) G1
800
820
840
860
880
900
920
940
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
NF1
8.81
9.05
9.19
9
8.96
8.74
9.71
10.51
10.31
10.93
11.59
12.42
12.83
13.25
13.6
13.63
13.64
12.9
12.5
12.3
G2
3.54
3.58
3.57
3.58
3.59
3.5
3.27
3.09
3
2.96
2.91
2.86
2.88
2.88
2.93
3.08
3.04
3.09
3.04
3.08
NF2
8.27
8.6
8.8
8.55
8.48
8.24
9.36
10.19
9.82
10.47
11.17
12.03
12.37
12.64
12.92
12.84
12.85
12.6
12.12
11.85
G3
3.62
3.68
3.64
3.66
3.7
3.6
3.33
3.14
3.07
3.05
2.98
2.92
2.94
2.96
3.04
3.07
3.02
3.02
3.09
3.04
NF3
-7.44
-6.79
-7.12
-7.38
-7.13
-7.59
-6.72
-6.17
-7.27
-6.55
-6.44
-5.7
-5.42
-6.38
-5.99
-6.91
-6.49
-6.41
-7.26
-6.37
9.01
9.14
9.08
8.19
8.94
8.45
8.95
8.68
8.75
8.79
8.61
8.45
8.22
8.3
8.57
8.55
8.35
8.76
8.67
8.64
212
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
11.93
11.95
11.97
11.99
12.01
12.03
12.05
12.07
12.09
12.11
12.13
12.15
12.17
12.19
12.21
12.23
12.25
12.27
12.29
12.31
12.33
2.
1200
1220
1240
1260
1280
1300
1320
1340
1360
1380
1400
1420
1440
1460
1480
1500
1520
1540
1560
1580
1600
12.51
11.89
11.41
11.36
11.91
11.34
11.3
11.16
10.81
10.84
10.46
10.26
10.25
10.48
10.54
10.2
11.14
10.38
9.94
10.1
9.57
3.04
3.1
2.94
2.8
2.75
2.82
2.89
2.92
2.86
2.95
3.04
3.02
3.05
3.14
3.03
2.84
2.97
3.04
3.02
3.16
3.43
11.56
11.1
10.79
10.64
11.19
10.69
10.76
10.53
10.15
10.3
9.92
9.74
9.93
9.91
9.76
9.42
10.43
9.59
9.32
9.46
8.93
3.01
3.02
3.06
2.89
2.84
2.89
2.95
2.95
2.87
2.99
3.04
3
3.17
3.17
3
2.83
3.03
3.08
3.05
3.18
3.48
-7.32
-7.08
-6.03
-6.89
-6.25
-6.56
-5.6
-6.44
-6.96
-5.89
-6.39
-6.48
-6.13
-6.02
-7.35
-7.24
-6.39
-7.68
-6.47
-6.51
-7.55
8.52
8.19
8.72
8.5
8.35
8.69
8.54
8.66
8.83
8.56
8.92
8.04
8.13
8.44
8.38
8.35
8.82
8.44
8.57
9.53
10.43
Gain and N F vs. LO power
Bias conditions: Vg*o= -.5 0 V, Vd*o=OV
LO conditions: fo=10.730 GHz. IF= 1270 MHz
)
-7
-5
-3
0
1
3
5
6
8
10
11
13
15
G(dB)
-5.9
-2.82
0.16
3.76
4.74
6.44
7.89
8.56
9.8
10.44
11
11.2
10.7
Vdo(V)
NF(dB)
6.64
0.01
0.03
5.36
4.54
0.043
3.9
0.077
0.095
3.76
0.137
3.52
0.193
3.3
0.225
3.2
3
0.31
2.88
0.421
0.485
2.83
2.8
0.615
2.9
0.78
213
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
Bias conditions: Vgso= -.6 0 V, Vdso=OV
LO conditions: fo=10.730 GHz, IF= 1270 MHz
)
-7
-5
-3
0
1
3
5
6
8
10
11
13
15
G(dB)
NF(dB)
Vdo(V)
-1.23
6.52
0.049
0.15
6
0.067
1.4
5.56
0.091
3.2
4.98
0.146
3.81
4.79
0.169
5
4.43
0.227
6.11
4.12
0.294
6.68
3.96
0.334
7.7
3.72
0.432
8.58
3.5
0.557
8.97
3.41
0.624
9.79
3.25
0.748
9.59
3.62
0.887
Bias conditions: Vg«o= -.3 0 V, Vdso=0V
LO conditions: fo=10.730 GHz, IF= 1270 MHz
G(dB)
Vdo(V)
NF(dB)
-18.9
-7
15.2
0.012
-5
-16.1
12.9
0.013
-12.6
-3
10.1
0.017
-5.983
0
6
0.029
1
-3.38
4.98
0.036
1.45
3.84
3
0.059
5
5.15
3.37
0.094
6.68
6
3.23
0.12
9.26
8
2.96
0.19
11.1
10
2.73
0.286
11
11.81
2.64
0.344
13
12.22
2.7
0.481
11
15
3
0.6
)
214
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
3. Gain and NF vs. gate dc bias
Bias conditions: Vd*o=0V, Po=10.OdBm
LO conditions: fo=10.730GHz, IF=1270MHz
)
G(dB)
NF(dB)
Vdo(V)
7.32
0.188
0.195
5.9
2.87
0.226
0.289
2.73
0.359
2.74
0.449
2.9
0.556
3.5
0.672
4.71
6.74
0.781
11.64
0.857
-8.02
1.2
5.11
10.31
11.09
11.21
10.55
8.6
4.87
l
o
C*i
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
Bias conditions:
Vdso=OV,
P0=13.0dBm
LO conditions: fb=10.730GHz, IF=1270MHz
)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
G(dB)
9.47
10.71
11.88
12.27
12.21
11.31
9.76
7.27
4.02
-0.1
Vd0(V)
NF(dB)
0.327
4.37
0.368
5.08
0.407
2.95
2.7
0.482
0.55
2.7
0.639
2.9
3.27
0.748
0.87
3.98
1.01
5.05
1.134
6.7
Bias conditions: Vd»o=OV, Po=O.OdBm
LO conditions: fo=10.730GHz, IF=1270MHz
215
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
)
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
G(dB)
-27
-20.1
-13.6
-6
1.11
4.31
3.21
-3.13
-14.5
NF(dB)
21.8
15.7
10.6
6.04
4.13
4
4.98
8.46
17.37
Vd0(V)
0.012
0.014
0.018
0.029
0.051
0.09
0.145
0.205
0.242
4. Gain and N F vs. drain bias
Bias conditions: Vgso= -0.3V , Po=O.OdBm
LO conditions: fo=10.73GHz, IF= 1270 MHz
Vds(V)
Vdso(V)
0.021
0.122
0.222
0.319
0.413
0.509
0.607
0.702
0.802
0.903
1.002
1.201
1.5
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
G(dB)
NF(dB)
-6.57
6.44
0.7
4.45
4.25
4.35
6.04
4.64
6.47
5.22
5.83
6.21
4.48
7.65
2.56
9.6
-0.27
12.46
-3.87
16.15
-7.23
19.69
-11.6
24.25
-14.9
27.74
-16.2
29.35
Bias conditions: Vg*o= -0.5V, Po=O.OdBm
LO conditions: tb=10.73GHz, IF= 1270 MHz
Vds(V)
0.073
0.147
G(dB)
Vdso (V )
0
0.1
3.81
4.7
NF(dB)
4.08
4.32
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
0.231
0.315
0.41
0.506
0.606
0.703
0.805
0.904
1
1.2
1.5
2
4.77
3.95
1.88
-0.92
-3.69
-6.38
-9.6
-13
-16.1
-19
4.96
6.07
8.09
10.92
13-89
16.82
20.22
23.75
27.2
29.75
Bias conditions: Vg*o= -0.5V, Po=10.0dBm
LO conditions: fo=10.73GHz, IF= 1270 MHz
Vds (V )
Vdso (V )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
0.428
0.431
0.437
0.468
0.521
0.59
0.666
0.749
0.833
0.921
1.015
1.195
1.482
1.97
G(dB)
NF(dB)
10.71
2.89
10.71
2.89
10.71
2.89
10.62
2.93
10.4
3
3.14
9.96
9.37
3.38
8.61
3.79
7.78
4.33
5.04
6.85
5.74
5.92
2.61
8.56
14.4
-3.1
23.18
-11.1
Bias conditions: Vb*o= -0.3V, Po=10.0dBm
LO conditions: fb=10.73GHz, IF= 1270 MHz
Vds (V )
0.278
0.3
0.359
0.432
Vdso(V)
0
0.1
0.2
0.3
G(dB)
NF(dB)
10.97
2.82
11.02
2.83
11.02
2.9
10.88
3.05
217
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
0.507
0.59
0.671
0.757
0.843
0.932
1.023
1.206
1.492
1.986
10.78
10.57
10.39
10.2
9.98
9.72
9.37
8.43
6.07
-1.53
3.18
3.42
3.65
3.89
4.15
4.42
4.73
5.52
7.55
15
Bias conditions: Vg«o- -0.3V, Po=13.0dBm
LO conditions: fo=10.73GHz, IF= 1270 MHz
Vds(V)
Vdso (V )
0.473
0.473
0.485
0.525
0.584
0.654
0.732
0.808
0.889
0.974
1.057
1.232
1.507
1.987
G (d B )
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
12.09
12.1
12.2
12.5
12.4
12.13
11.73
11.32
10.97
10.74
10.59
10.34
9.83
7.43
N F (d B )
2.79
2.79
2.78
2.78
2.71
2.79
2.9
3.1
3.35
3.6
3.82
4.21
4.85
7.04
Bias conditions: Vg*o= -0.5V, Po=13.0dBm
LO conditions: fb=10.73GHz, IF= 1270 MHz
Vds (V )
0.61
0.607
0.607
Vdso(V)
0
0.1
0.2
G(dB)
NF(dB)
11.47
2.91
11.46
2.91
11.46
2.91
218
R ep ro d u ced with p erm ission of the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
0.611
0.633
0.665
0.723
0.793
0.869
0.95
1.036
1.211
1.484
1.966
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
11.46
11.46
11.46
11.22
10.98
10.65
10.22
9.65
8.46
6.81
1.74
2.91
2.91
2.91
2.93
2.97
3.04
3.18
3.41
4.17
5.64
10.41
2. By HP8593A Spectrum Analyzer:
File Name: 5-27
Date: 05-27/96
1. Calibration of the LO power Levels at drain of the DM
HP8350B HP8593A
-4.8
-7
-2.7
-5 Note: HP8593A's reading is the actual LO power delivered to the DM
-0.7
2.4
5.3
7.5
8.5
10.7
12.7
13.7
15.6
17.3
-3
0
3
5
6
8
10
11
13
15
HP 8593A
Spectrum
Analyzer
HP 8350B
Sweep
Oscillator
2. Calibration of the RF input level
HP X382A HP 8593A
Attenuator (dBm)
-26.2
-30
-21.2
-25
-18.2
-22
-16.2
-20
-14.2
-18
-11.2
-15
8.2
-12
-
219
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout p erm ission .
6.2
-3.4
-1.4
-
-10
-7
-5
3. Outputs vs. input RF signal power levels
f1=12.000GHz
f2=12.020GHz
fo=10.730GHz
Po=10dBm
Vdso=OV
V g so = -0 .5 V
Pin(dBm) P1st(dBm) P3rd(dBm)
-30
-19.1
-61.5
-25
-14.4
-47.15
-22
-11.76
-39.6
-20
-10
-35.1
-18
-8.72
-31
-15
-7.17
-25.7
-12
-6.92
-29
-10
-6.48
-28.5
-5
-5.15
-21.5
f1=12.000GHz
f2=12.020GHz
fo=10.730GHz
Po=13dBm
Vdso=OV
Vgso— 0.5V
Pin(dBm) P1st
P3rd
-30
-18.1
-63.8
-25
-13.53
-49.5
-22
-10.91
-41.8
-20
-9.42
-37.8
-18
-8.2
-33.1
-15
-6.4
-28
-12
-5.64
-29
-10
-5.1
-29.1
-5
-3.28
-22.7
f1=12.000GHz
f2=12.020GHz
fb=10.730GHz
Pa=0dBm
Vdso=OV
V g so = -0 .5 V
Pin(dBm) P1st
P3rd
-30
-25.39
-63
-25
-21
-50
-22
-18.46
-42.83
-20
-17.09
-38.54
-18
-16
-35
220
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
-15
-12
-10
-5
-14.68
-13.93
-15.03
-15
-30.5
-29.54
-40.85
-33.54
i ro
(
ro
CO 00
i>
N
<o
m) P1st-0
Pin(dBm)
P3rd-0
P1 st-10
P3rd-10 P1 st-13
P3rd-13
-30
-25.39
-63
-19.1
-61.5
-18.1
-63.8
-25
-21
-50
-14.4
-47.15
-13.53
-49.5
-22
-18.46
-11.76
-42.83
-39.6
-10.91
-41.8
-20
-17.09
-38.54
-10.27
-35.1
-9.42
-37.8
-18
-16
-35
-8.92
-31
-33.1
-8.2
-15
-14.68
-30.5
-7.27
-25.7
-6.4
-12
-13.93
-29.54
-6.92
-5.64
-10
-15.03
-40.85
-6.48
-28.5
-5.1
-29.1
-5
-15
-33.54
-5.15
-21.5
-3.28
-22.7
4. The outputs vs. drain biases
f1=12.000GHz
f2=12.020GHz
fo=10.730GHz
Pin=-20dBm
P1st-0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.2
1.5
2
-18
-17.34
-17.32
-16.88
-17.06
-19
-20.68
-21.9
-22.69
-24.1
-25.7
-28.69
. -31
-36.05
Vgso=-0.5V
P3rd-0
P1 st-10
P3rd-10 P1st-13
P3rd-13
-39.89
-10.34
-9.42
-34.88
-36.08
-38.68
-10.36
-34.84
-9.42
-36.2
-38.52
-10.38
-34.72
-9.42
-36.75
-37.11
-10.41
-9.44
-34.65
-36
-10.57
-36.95
-9.44
-36.04
-34.65
-40.45
-10.72
-35.97
-34.65
-9.5
-45.88
-11.05
-34.81
-9.6
-36
-45.1
-11.24
-9.76
-35.23
-36.1
-43.99
-11.64
-35.77
-9.97
-36.49
-42.5
-12.14
-36.2
-10.32
-36.84
-41.68
-12.62
-36.68
-10.6
-37.2
-14.4
-41.68
-39.96
-11.39
-38
-41.6
-18.46
-40.38
-12.76
-39.59
-49
-22.35
-38.23
-15.35
-40.7
5. The outputs vs. gate biases
f1 =12.000GHz
f2=12.020GHz
Vgso (V )
0
fo=10.730GHz
Pin=-20dBm
Vds0=0V
P1st-0
P3rd-0
P1st-10
P3rd-10 P1st-13
P3rd-13
-41.31
-66.7
-16.35
-45.59
-10.77
-37.51
221
R ep ro d u ced with p erm ission of th e copyright ow ner. Further reproduction prohibited w ithout p erm ission .
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-36.67
-31.48
-26.08
-21.42
-18.7
-16.44
-16.4
-18.05
-22
-59.72
-52.21
-47.94
-50
-37.21
-38.07
-36.45
-40.43
-51.27
-13.46
-11
-9.8
-9.67
-9.6
-11.41
-13.7
-17.43
-22.2
-39.45
-38.21
-36.9
-35.4
-35.9
-35.85
-40.43
-48.34
-55.32
-9.3
-8.12
-7.85
-7.8
-8.88
-9.81
-11.53
-14.34
-17.94
-37
-36.2
-35.8
-35.3
-35.4
-36.59
-39.82
-46.3
-53.15
6. Port isolations
V g s o - 0 .5 0 V , Vdso=OV, P o = 1 0 d B m , fo = 1 0 .7 3 0 G H z , fs = 1 2 G H z , P in = -2 0 d B m
LO signal:
RF port (dBm)
- 8.2
IF port (dBm)
-7.48
LO port (dBm)
IF port (dBm)
RF signal
Appendix A7-3
The m easured specifications of the drain m ixer #2
1. By HP 8970A Noise Figure M eter
File Name:ne33-2.xls
Date:i 1- 12/95
FET: NE33284 #2. Vp—1V, Nf0=0.75db, Ga=10.5db @12GHz
Bias conditions: Vdso=OV, VgsO=-0.6V, optimum bias for minimum third order
intermodulation.
LO conditions: fb=10.73GHz, Po=9dbm (exclude the cable loss)
Gf, NFf- gain and n oise figure with the input waveguide filter, GO, NFO-without the
filter
Note: @10.73GHz, cable loss—1.6db.
1. Gain and NF vs. Frequencies
222
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
RF(GHz)
11.53
11.55
11.57
11.59
11.61
11.63
11.65
11.67
11.69
11.71
11.73
11.75
11.77
11.79
11.81
11.83
11.85
11.87
11.89
11.91
11.93
11.95
11.97
11.99
12.01
12.03
12.05
12.07
12.09
12.11
12.13
12.15
12.17
12.19
12.21
12.23
12.25
12.27
12.29
12.31
12.33
IF(MHz) NFO(dB)
800
820
840
860
880
900
920
940
960
980
1000
1020
1040
1060
1080
1100
1120
1140
1160
1180
1200
1220
1240
1260
1280
1300
1320
1340
1360
1380
1400
1420
1440
1460
1480
1500
1520
1540
1560
1580
1600
3.09
3.07
3.2
3.16
3
2.9
2.81
2.75
2.73
2.79
2.68
2.55
2.56
2.54
2.59
2.47
2.6
2.6
2.57
2.57
2.61
2.85
2.6
2.84
2.9
2.81
2.68
3.18
3.07
2.65
3.32
3.29
2.87
3.43
3.66
2.73
3.92
3.81
3.4
3.65
4.18
GO(dB)
5.26
5.53
5.23
5.27
5.8
5.87
6.21
6.41
6.4
6.58
6.77
7.36
7.47
7.49
7.95
7.95
8.34
8.17
8.54
8.54
8.36
8.96
7.96
7.9
8.4
8.24
7.13
7.48
7.18
6.23
6.84
6.32
5.83
6.25
5.7
4.43
5.47
4.12
4.38
4.94
3.95
NFf(dB)
Gf(dB)
3.32
3.26
3.57
3.56
3.4
3.28
3.21
3.29
3.32
3.56
3.66
4.05
6.44
6.84
4.24
3.57
3.66
3.58
3.83
4.27
4.31
4.11
3.69
3.72
3.61
3.5
3.39
3.94
3.83
3.35
4.09
4.15
3.79
4.42
4.81
3.93
5.29
5.34
4.98
5.3
6.1
5.15
5.48
4.74
4.75
5.2
5.56
6.07
6.41
6.34
6.18
6.58
7.27
7.22
6.54
6.66
6.48
6.6
6.39
6.57
6.78
7.18
8.16
7.12
7.13
7.83
7.78
6.51
6.52
6.38
5.33
5.78
5.15
4.48
4.82
4.36
2.95
3.79
2.31
2.49
2.89
1.73
FET: NE33284. Vp-1V, Nf0=0.75db, Ga=10.5db @12GHz
Bias conditions: V g so= -0.6V , Vdso=OV
LO conditions: fb=10.73GHz, Po=9dbm (exclude the cable loss)
There is waveguide filter in the input
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
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Note: @ 10.73GHz, cable loss=-1.6db.
with permission
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2. Gain and N F vs. LO power (with die input waveguide filter)
Bias conditions: V g so= -0.6V , Vdso=OV
LO conditions: fo=10.73GHz, IF=1300MHz
Po (dBm) Po(mw)
Gf(dB)
NFf(dB) GO (dB)
NFO(dB)
5.14
0.5
0.39
0.82
-3
4.45
1
2.78
4.43
3.12
0
3.8
4.25
3.91
1
1.259
3.55
3.6
1.585
4.31
4.08
4.61
3.47
2
3.96
2
5
5.28
3.35
3
4
2.512
5.61
3.82
5.88
3.21
3.7
3.162
6.17
6.45
5
3.1
3.981
3.63
6.97
2.95
6
6.68
7.47
3.56
7
5.012
7.15
2.9
3.51
7.88
6.31
7.53
2.82
8
8.26
7.943
7.83
3.48
2.79
9
3.47
8.55
10
8.02
2.79
10
3.5
8.73
12.589
8.11
2.78
11
15.849
8.85
8.14
3.59
2.81
12
8.95
3.68
2.89
19.953
8.16
13
Gain and N F vs. LO power (without the input waveguide filter)
Bias conditions: V g so = -0 .6 V , Vdso=OV
LO conditions: fo=10.73GHz, IF=1300MHz
Po (dBm) Po (mw)
GO (dB)
NFO (dB)
0.5
0.82
4.45
-3
1
3.12
3.8
0
3.6
1
1.259
3.91
3.47
1.585
4.61
2
2
3.35
5.28
3
4
2.512
5.88
3.21
3.1
3.162
6.45
5
6.97
2.95
3.981
6
7.47
5.012
2.9
7
2.82
7.88
6.31
8
7.943
8.26
2.79
9
2.79
10
8.55
10
2.78
12.589
8.73
11
15.849
8.85
2.81
12
2.89
19.953
8.95
13
3.
Gain and N F vs. gate bias
Bias conditions: Vdso=OV, Po=9.0dBm
LO conditions: fo=10.73GHz, IF=1300MHz
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
Gf (dB)
VgsO (V)
0
-0.2
-0.3
-0.4
-0.5
•0.6
-0.7
-0.8
-0.9
-1
-4.93
2.3
4
5.35
6.85
7.99
7.23
6.05
4.24
1.09
NFf(dB)
9.72
5.91
5.07
4.43
3.86
3.4
4.25
5.62
5.14
5.36
GO (dB)
-0.83
4.21
5.48
6.47
7.47
8.26
7.55
3.76
-3.35
-15
NFO (dB)
5.79
4.17
3.77
3.4
3.11
2.83
2.79
3.25
4.99
11.54
4. Gain and N F vs. drain bias
Bias conditions: Vgso=-0.60V, Po=9.0dBm
LO conditions: fo=10.73GHz, IF=1300MHz
Vdso(V)
Gf (dB)
NFf(dB)
-0.534
-1.17
8.8
-0.334
3.73
4.99
-0.134
6.84
3.7
0
8
3.4
0.216
6.97
3.68
0.3
1.9
8.46
5. LO Signal Isolation Between LO Port to RF Port, and to IF Port
Bias conditions: Vdso=OV, Po=9.0dBm
LO conditions: fo=10.73GHz, IF=1300MHz
f)
-0.4
-0.5
•0.6
-0.7
-0.8
IRF (dB) IIF (dB)
16.12
9.61
18.18
9.56
20.51
9.51
22.85
9.31
23.63
9.13
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
2. Measurement of the conversion gain and intermodulation by the spectrum
analyzer
f1=12.0493GHz
f1'=12.0358Ghz
f1st=1.3135GHz
fisf=1.3275GHz
f2=12.0633Ghz
V gso=-0.60V
V dso=0V
f2'=12.0773GHz
fo=10.74GHz
f3rd=1.300GHz
f5th=1.2860GHz
Po=10dbm
Atten.(dB)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin(dBm)
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
P1st(dBm)
-6
-6.57
-7.3
-7.9
-8.65
-9.6
-10.62
-11.7
-12.8
-13.8
-14.8
-15.8
-16.8
-17.8
-18.8
-19.8
P3rd(dBm)
-26.4
-28.49
-31.02
-33.4
-36.1
-38.8
-40.6
-42.6
-44.5
-46.3
-48.4
-50.2
-52
-54
-56
-58.5
Po=7dbm
Atten.(dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin(dBm)
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
P1st(dBm)
-7.65
-8.11
-8.6
-9.22
-9.8
-10.65
-11.7
-12.7
-13.78
-14.78
-15.78
-16.78
-17.78
-18.78
-19.78
-20.78
P3rd(dBm) P5th(dBm)
-26.4
-39.5
-27.94
-42.5
-29.47
-45
-31.2
-49.3
-33.12
-53.7
-35.4
-57
-37.94
-40.4
-42.7
-45
-47.3
-49.8
-52
-54.2
-56.7
-59
0
-45.24
-50.04
-57
227
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
f1=12.050GHz
f2=12.0625Ghz
fo=10.73GHz
V gso=-0.60V
V dso=0V
Atten.(dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
Po=6.0dbm
Pin(dBm)
P1st(dBm)
-12.4
-8.2
-13.4
-8.7
-14.4
-9.2
-15.4
-9.7
-16.4
-10.25
-17.4
-10.98
-18.4
-11.98
-19.4
-13
-20.4
-14.01
-21.4
-15
-22.4
-16
-23.4
-17
-24.4
-18
P3rd(dBm) P5th(dBm)
-26.72
-39
-27.98
-41.68
-29.34
-44.6
-30.94
-47.5
-32.7
-50.8
-34.7
-54.82
-37
-57
-39.7
-42.45
-44.8
-47.2
-49.5
-52
Lo Cable loss:-3.22dB atfo=10.74GHz
Po=3 dBm
Atten.(dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin(dBm)
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
-28.4
-29.4
-30.4
P1st(dBm)
-10.37
-10.98
-11.3
-11.8
-12.3
-12.95
-13.65
-14.66
-15.65
-16.65
-17.65
-18.65
-19.65
-20.65
-21.65
-22.65
-23.65
-24.65
-25.65
P3rd(dBm) P5th(dBm)
-28.27
-40
-42.5
-29.5
-44.4
-30.8
-32.3
-46.5
-34
-49
-51.97
-35.8
-54.5
-37.92
-40.6
-42.9
-45.4
-47.6
-50.3
-52.4
-54.6
-57
-59
Po=0 dBm
Atten.(dB)
Pin(dBm)
P1st(dBm)
P3rd(dBm) P5th(dBm)
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
-28.4
-12.84
-13.18
-13.59
-14
-14.5
-15.05
-15.7
-16.3
-17.15
-18.15
-19.15
-20.15
-21.15
-22.15
-23.15
-24.15
-25.15
-29.7
-30.9
-32.2
-33.5
-35.1
-37.14
-39
-40
-43.1
-45.4
-48.1
-50.4
-52.5
-55
-41.2
-43.2
-45.3
-47.9
-50
-52.67
-55.78
f1=12.050GHz
f2=12.060GHz
fo=10.74GHz
Po=10dbm
V g so = -0 .6 V
VdsO (V )
0
0.2
0.4
0.6
0.8
1
1.2
1.5
Pin=-24.7dbm
Ga(dB)
P1st(dBm)
7.3
-17.4
7.3
-17.4
7.3
-17.4
7.3
-17.4
3.96
-20.74
-0.15
-24.85
-3.3
-28
-5.57
-30.27
P3rd(dBm)
-60
-60
-59
-59.5
-59
Vs. VgsO:
Po=10dbm,
Vdso=OV,
VgsO(V)
P1st(dBm)
-32.7
-21.77
-19.4
-19.5
-18.42
-17.78
-17.1
0
-0.2
-0.3
-0.4
-0.5
-0.56
-0.597
Pin=-24.7dBm
P3rd(dl
P5th(dBm)
-61
-61
-61
-58
-58
-60
229
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout p erm ission.
-0.634
-0.698
- 0.8
-0.936
-17.2
-18.49
- 21.88
-25.94
-61
-61
Po=10dBm,
VdsO=0V,
Pin=-20.7dBm
VgsO(V)
P1st(dBm)
-27.72
-17.7
-15.38
-15.5
-14.35
-13.5
-13.05
-13.5
-14.67
P3rd(dBm)
-56.5
-55.5
-53.8
-54
-50.2
-50.2
<
Pin*-20.7dB,
Po(dBm)
P1st(dBm)
-19.4
-3
0
-17.28
1
-15.57
-16.07
2
-15.6
3
4
-15.24
6
-14.35
8
-13.7
-13.4
9
10
-13.3
12
-13.07
Conversion Gain
Ga
1.3
3.42
4.13
4.63
5.1
5.46
6.35
1
cn
ro
P5th(dBm)
-52
-53
-61
1
Ol
00
-17.73
-19.92
£
I
0
-0.2
-0.3
-0.4
-0.5
-0.563
-0.603
-0.644
-0.702
-0.774
-0.801
-0.864
1
0>
00
VS. VgsO:
-54
Vg.O=-0.6V
P3rd(dBm)
-45.8
-46
-46.5
-46.7
-47
-47
-48
-49.8
-50
-52.2
-54
P5th(dBm)
-65.02
Po(dBm)
0.5
1
1.26
1.58
2
2.51
3.98
Po(dBm)
-3
0
1
2
3
4
6
-70
P3rd(dBm)
-45.8
-46
-46.5
-46.7
-47
-47
-48
230
R ep ro d u ced with p erm ission o f th e copyright ow ner. Further reproduction prohibited w ithout perm ission.
7
7.3
7.4
7.63
6.31
7.94
10
15.85
8
9
10
12
-49.8
-50.5
-52.2
-54
Pin(dBm)
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
-28.4
-29.4
10 (dBm)
-6
-6.57
-7.3
-7.9
-8.65
-9.6
-10.62
-11.7
-12.8
-13.8
-14.8
-15.8
-16.8
-17.8
-18.8
-19.8
7 (dBm)
-7.65
-8.11
-8.6
-9.22
-9.8
-10.65
-11.7
-12.7
-13.78
-14.78
-15.78
-16.78
-17.78
-18.78
-19.78
-20.78
6 (dBm)
-8.2
-8.7
-9.2
-9.7
-10.25
-10.98
-11.98
-13
-14.01
-15
-16
-17
-18
3 (dBm)
-10.37
-10.98
-11.3
-11.8
-12.3
-12.95
-13.65
-14.66
-15.65
-16.65
-17.65
-18.65
-19.65
-20.65
-21.65
-22.65
-23.65
-24.65
-25.65
0 (dBm)
-12.84
-13.18
-13.59
-14
-14.5
-15.05
-15.7
-16.3
-17.15
-18.15
-19.15
-20.15
-21.15
-22.15
-23.15
-24.15
-25.15
Pin(dBm)
-12.4
-13.4
-14.4
-15.4
-16.4
-17.4
-18.4
-19.4
-20.4
-21.4
-22.4
-23.4
-24.4
-25.4
-26.4
-27.4
-28.4
-29.4
10 (dBm)
-26.4
-28.49
-31.02
-33.4
-36.1
-38.8
-40.6
-42.6
-44.5
-46.3
-48.4
-50.2
-52
-54
-56
-58.5
7 (dBm)
-26.4
-27.94
-29.47
-31.2
-33.12
-35.4
-37.94
-40.4
-42.7
-45
-47.3
-49.8
-52
-54.2
-56.7
-59
6 (dBm)
-26.72
-27.98
-29.34
-30.94
-32.7
-34.7
-37
-39.7
-42.45
-44.8
-47.2
-49.5
-52
3 (dBm)
-29.7
-30.9
-32.2
-33.5
-35.1
-37.14
-39
-40
-43.1
-45.4
-48.1
-50.4
-52.5
-55
0 (dBm)
-29.7
-30.9
-32.2
-33.5
-35.1
-37.14
-39
-40
-43.1
-45.4
-48.1
-50.4
-52.5
-55
R ep ro d u ced with p erm ission o f the copyright ow ner. Further reproduction prohibited w ithout perm ission.
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