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Molecular beam epitaxial growth and fabrication of microwave and photonic devices for hybrid integration on alternative substrates

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O rder N um ber 932S574
M olecular beam epitaxial grow th and fabrication o f m icrowave
and ph otonic devices for hybrid integration on alternative
su bstrates
Tsao, Alwin James, Ph.D.
The University of Texas at Austin, 1993
C opyright © 1993 by T sao, A lw in Jam es. A ll righ ts reserved.
UMI
300N.ZeebRd.
Ann Aibor, MI 48106
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MOLECULAR BEAM EPITAXIAL GROWTH AND FABRICATION OF
MICROWAVE AND PHOTONIC DEVICES FOR HYBRID
INTEGRATION ON ALTERNATIVE SUBSTRATES
by
ALWIN JAMES TSAO, B.S.E.E., M.S.E.E.
DISSERTATION
Presented to the Faculty of the Graduate School of
The University of Texas at Austin
in Partial Fulfillment
of the Requirements
for the Degree of
DOCTOR OF PHILOSOPHY
THE UNIVERSITY OF TEXAS AT AUSTIN
May 1993
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MOLECULAR BEAM EPITAXIAL GROWTH AND FABRICATION OF
MICROWAVE AND PHOTONIC DEVICES FOR HYBRID
INTEGRATION ON ALTERNATIVE SUBSTRATES
APPROVED BY
DISSERTATION COMMITTEE:
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Copyright
by
Alwin James Tsao
1993
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This work is dedicated to my father, James Jhy-Yuan Tsao, my mother, Vicki Ishien Wei Tsao, my brother Allen Tsao, my sister, Debbie Tsao and my wife,
Jenn Fen Liu Tsao
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ACKNOWLEDGEMENTS
I would like to first thank my advisor, Professor Dean P. Neikirk, whose
guidance, support, patience, "gee-whiz" ideas , and friendship have allowed me to
finish this work. To Professors Ben G. Streetman and Joe C. Campbell, I owe a
great deal of thanks for their interest in this work and use of their facilities. I would
also like to thank the other members of my committee, Professors Willis Adcock
and Mike Downer, for their time and effort. To Terry Mattord, I would like to
express my appreciation for his time and help on equipment related issues. In
addition, I would like to thank Professor Alex DeLozanne for use of his scanning
electron microscope used to obtain all the SEM micrographs shown in this study.
I have been very fortunate to work with many outstanding graduate students
in the Microelectronics Research Center (MRC). I would like to thank Stu
Wentworth for his help in the area of fabrication and equipment related issues. To
my "ENS 405 brothers", Douglas Miller, Vijay Reddy and Kiran Gullapalli, I would
like to extend a heartfelt thanks for their friendship, for the many discussions we've
had, and the help they have given to me over the years. I would also like to thank
Saiful Islam for many useful discussions related to processing and CPWs. In
addition, I would like to thank the members of the MBE group for the pleasure of
working with them and learning from them: Ananth Dodabalapur, Tom Block,
Tommy Rogers, Kayvan Sadra, Albert Shih, Anand Srinivasan, Alex Anselm, Chad
Hansing, and Andy Tang. To Carl "Goobaby" Kyono, Kevin Klein, and Marty
Agnostinelli, I thank them for the profit and the fun I had in the high-stakes tennis
matches we played. I would also like to thank Ravi "Truck" Kuchibhotla for useful
discussions on LEDs, lasers, and his opinions on everything. For the other
members of "Team Neikirk", I would like to express my sincere appreciation for
their assistance in many lab related issues. In addition, I would like to thank
Bernice Wooton for her help in taking care of many administrative tasks.
Finally, I would like to acknowledge the sources of financial support for this
research: Texas Advanced Technology Program, Joint Services Electronics
Program and the VLSI Fabrication Lab at the University of Texas at Austin.
v
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MOLECULAR BEAM EPITAXIAL GROWTH AND FABRICATION OF
MICROWAVE AND PHOTONIC DEVICES FOR HYBRID
INTEGRATION ON ALTERNATIVE SUBSTRATES
Publication No._____________
Alwin James Tsao, Ph.D.
The University of Texas at Austin, 1993
Supervisor. Dean P. Neikirk
In recent years, there has been considerable work on improving the high
frequency and output power properties of double barrier resonant tunneling diodes
(DBRTDs) which exhibit negative differential resistance (NDR) in their DC
current-voltage (DC-IV) characteristics. Structural device parameters such as
quantum well, barrier, and spacer layer thicknesses significantly impact the peak-tovalley current ratio (PVCR), the peak current density (Jp), the difference between
the peak voltage and the valley voltage (AV), and the difference between the peak
current density and the valley current density (AJ). Furthermore, variations in the
dopant profiles, thickness of the spacer layers, and the contact resistance can
significantly alter device characteristics. Optimization of the ohmic contacts to the
DBRTDs was investigated. The impact of barrier asymmetries in AlAs/GaAs and
AlAs/AlGaAs/GaAs DBRTD structures were studied. Through the use of an
AlGaAs/AlAs "chair" barrier or composite barrier, a PVCR of 6.3 was measured.
The impact of intentional small barrier thickness asymmetries on the DC-IV
characteristics of AlAs/GaAs high current density DBRTDs was also examined.
The thickness of the asymmetric barrier is adjusted nominally in increments of a
half-monolayer based on growth rates using Reflection High Energy Electron
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Diffraction (RHEED) intensity oscillations. From this study, an AlAs/GaAs
DBRTD was produced with a PVCR of 5.6. These PVCRs remain the highest
reported to date for their respective material systems.
The typical current densities of AlAs/GaAs DBRTDs are in the range of 20
kA/cm2 - 100 kA/cm2. As a result of the significant device heating that can occur,
the Epitaxial Lift Off (ELO) technique was used to remove the DBRTDs from their
original substrates for subsequent hybrid integration to hybrid substrates of higher
thermal conductivity. The ELO technique was used to create optically controlled
Schottky contacted coplanar waveguide (CPW) phase shifters which are bonded to
transparent substrates. In a similar fashion, ELO light emitting diodes (LED) such
as AlGaAs/GaAs double heterostructure and multi-quantum well LEDs have been
grown and hybrid bonded to transparent and pre-pattemed substrates.
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Table of Contents
Chapter 1 Introduction...................................................................................1
1.1 Statement of Purpose....................................................................... 1
Chapter 2 Molecular Beam E pitaxy..............................................................4
2.1 Introduction...................................................................................... 4
2.2 Description of the Varian Gen IIMBE System................................ 7
2.3 Substrate Preparation Before Epitaxial Growth............................... 9
2.4 Growth Kinetics.............................................................................. 9
2.5 Reflection High Energy Electron Diffraction (RHEED)...................12
2.6 GaAs on Si MBE Growth................................................................ 16
Chapter 3 Hybrid Integration using the Epitaxial Lift Off Method.............18
3.1 Introduction......................................................................................18
3.2 General Description of the ELO Method.......................................... 18
3.3 Sample Preparation for Epitaxial Lift O ff........................................22
3.4 Epitaxial Lift Off and Manipulation of ELO Films.......................... 26
3.5 Issues Regarding Bonding of ELO films..........................................29
3.6 Van der Waals (VDW) Bonding of ELO Films............................... 29
3.7 Adhesive and Metal/Alloy Based Bonds to Alternative
Substrates............................................................................................... 33
3.8 Hybrid substrates used in ELO........................................................ 40
3.9 Epitaxial Lift Off of Strained Layer Films.......................................41
3.10 Epitaxial Lift Off of Silicon on Insulator (SOI)............................. 42
3.11 Alternative Processes other than the ELO Process......................... 43
Chapter 4 AlAs/GaAs Double Barrier Resonant Tunneling Diodes............ 45
4.1 Introduction..................................................................................... 45
4.2 Background Discussion for the AlAs/GaAs DBRTD...................... 46
4.3 Simulations Used for Analyzing the DBRTD.................................. 50
4.4 Coherent vs. Sequential Tunneling and Inelastic Tunneling............ 52
4.5 The QW1TT diode and the use of depleted spacer layers................. 54
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4.6 Temperature Dependence of AlAs/GaAs DBRTDs and
QWITTs.................................................................................................59
4.7 MBE Growth of AlAs/GaAs DBRTDs and QWITTs...................... 61
4.8 Formation of Ohmic Contacts and Fabrication Issues...................... 63
4.9 MBE Growth of AlAs/GaAs DBRTDs with As2 and AS4 ............... 72
4.10 Growth, Fabrication, and Testing of Depletion-Edge
Modulation AlAs/GaAs QWITTS.........................................................73
Chapter 5 Intuitional Barrier Asymmetries in AlAs/GaAs
Double Barrier Resonant Tunneling Diodes.................................................78
5.1 Introduction....................................................................................78
5.2 Half-monolayer scale barrier asymmetries in AlAs/GaAs
DBRTDs.............................................................................................. 80
5.3 Asymmetric Barriers Utilizing AlGaAs/ALAs/GaAs "Chair"
Barriers................................................................................................. 89
5.4 Use of an AlGaAs/AlAs/GaAs "Chair" Barrier in a QWITT
Diode..................................................................................................... 93
Chapter 6 Application of the ELO Technique to
Microwave and Photonic Devices...................................................................96
6.1 Introduction..................................................................................... 96
6.2 Epitaxial Lift Off of AlAs/GaAs DBRTDs and Integration with
Alternative Substrates using In-based Bonds..........................................96
6.3 Epitaxial Lift Off of AlAs/GaAs QWITTs and Integration with
Alternative Substrates using Pd-based Bonds......................................... 105
6.4 Process Problems Associated with ELO DBRTDs and QWITTs 114
6.5 Epitaxial Lift Off of an Optically Controlled Schottky Contacted
Coplanar Waveguide (CPW) Phase Shifter and Bonds to Transparent
Substrates...............................................................................................119
6 . 6 Future Work Involving Hybrid Integration of ELO Devices............126
Chapter 7 Summary and Conclusion............................................................ 129
Appendix 1 Parametric Summary of All DBRTD and QWITT Devices
131
Appendix 2 AZ5214E Photolithographic Process using
the HTG System 3 Aligner...............................................................................140
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Appendix 3 General Epitaxial Lift Off Procedure........................................ 142
References......................................................................................................... 145
VITA.................................................................................................................159
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List of Figures
Figure 2.1
Illustration showing a typical growth chamber. After M.B. Panish [Ohr92]
5
Figure 2.2
Cutaway view of the Varian Gen II MBE System. Illustration taken from
the Varian Gen II Users Manual........................................................................ 6
Figure 2 3
Illustration showing the growth of GaAs from Ga and As2 - Taken from a
reproduction of the work of C.T. Foxon in The Technology and Phvsics of
Molecular Beam Epitaxy. E.H.C. Parker, editor................................................11
Figure 2.4
Illustration showing the growth of GaAs from Ga and AS4 . Taken from a
reproduction of the work of C.T. Foxon in The Technology and Phvsics of
Molecular Beam Epitaxy. E.H.C. Parker, editor............................................... 11
Figure 2.5
2 x 4 diffraction pattern, (0 °), for GaAs in As-stabilized growth mode............. 13
Figure 2.6
4 x 2 diffraction pattern, (0 °), for GaAs in Ga-stabilized growth mode.............13
Figure 2.7
Illustration depicting nucleation and island growth that occurs on the
surface, diffraction of the electron beam, and the corresponding RHEED
intensity oscillations taken from the specular spot Taken from The
Materials Science of Thin Films. M. Ohring [Ohr92]........................................14
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Figure 3.1
Illustration (not drawn to scale) of the ELO technique as an epitaxial film is
being separated from its original growth substrate. The tension in the
Apiezon W black wax induces a radius of curvature, R, of several
centimeters in the epitaxial film which promotes removal of etch by­
products from the etch front [YaG87]..............................................................20
Figure 3 2
Illustration showing typical cross-section of ELO layer structure for twoterminal mesa isolated device that can be tested both before ELO and after
ELO. Note that mesa etch must be controlled such that the etch does not
penetrate the AlAs release layer....................................................................... 22
Figure 33
Illustration of the application of Apiezon W black wax to mesa isolated
AlGaAs/GaAs heterojunction device. To make sure that good step
coverage of the black wax over the mesas occurs, a teflon press is used to
press the softened wax over the edges of the mesas. The wax can be
softened either by raised temperature or through the use of solvents such as
TCA and toluene...............................................................................................25
Figure 3.4
Illustration of dome-shape in black wax carrier on mesa isolated
AlGaAs/GaAs heterostructures. The AlAs release layer is exposed at all
edges before inserting the sample into the 10% HF etch................................... 26
Figure 35
Illustration showing the edges of a mesa isolated AlGaAs/GaAs
heterostructure (i.e. AlAs/GaAs double barrier resonant tunneling diodes,
AlGaAs/GaAs double heterostructure LEDs) being peeled back by the
tension in the Apiezon W black wax as the AlAs release layer is being
etched out by 10% HF...................................................................................... 27
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Figure 3.6
Illustration showing the suspension of an ELO sample in the 10% HF. Upon
complete separation, the substrate drops away from the ELO film.................... 28
Figure 3.7
Illustration of uniform pressure applied by vacuum bag to wax carrier as
ELO film is pressed together with an alternative substrate for a VDW bond.
A lint free Kim-wipe is placed between the wax carrier and vacuum bag to
prevent pinching off of the vacuum.................................................................. 31
Figure 3.8
SEM micrograph showing the complete mesa isolation of an 3 pm thick
ELO film into * 4pm by 4pm islands. The "mushroom" cap on top of the
GaAs island is the remaining photoresist after the mesa etch.............................34
Figure 3.9
SEM micrograph showing an ELO film that has been bonded to P-20 silver
polyimide. Note that the size of the silver flakes appear to be on the order of
the ELO film thickness and does not provide a smooth flat bond line................35
Figure 3.10
SEM micrograph of an ELO device bonded to an In/AuCr coated glass
substrate. The specific contact resistivity of the ohmic contacts was
indirectly extracted and found to be 8 x 10-6 Q-cm2. The mechanical
contact and bond strength were poor. Note the roughness of the In at the
edges of the ELO film...................................................................................... 38
Figure 3.11
SEM micrograph of an ELO device bonded to a Pd/AuCr coated Si
substrate. The best possible backside specific contact resistivity was
indirectly extracted and found to be = 1 x 10-5 Q-cm2. The mechanical
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contact and bond strength were very good. Note the smooth morphology of
the Pd surface and the excellent bond at the edges of the film........................... 39
Figure 3.12
Cross-sectional schematic of a silicon-on-insulator (SOI) sample used in the
ELO process. A standard 49% HF solution was used to etch out the oxide as
the Si overlayer was held to a Apiezon W black wax carrier.............................42
Figure 4.1
Illustration of the T-T conduction band profile of a typical AlAs/GaAs
DBRTD, similar to those grown by MBE in this work. The conduction band
offset between Ta ia s and TGaAs is ® 1.04 eV................................................... 46
Figure 4.2
Plots of the transmission coefficient versus electron energy for an
AlAs/GaAs single barrier structure and a double barrier structure. The
barriers are 17A and the quantum well of the DBRTD is 50A. Plot courtesy
of K.K. Gullapalli............................................................................................. 47
Figure 4 3
Figure 4.3: (a) Illustration depicting the operation of an AlGaAs/GaAs
DBRTD as a voltage is applied to the device. Taken from Sollner,
et.al. [SoG83]. (b) J-V characteristics of an AlAs/GaAs DBRTD with
specific parameters of interest highlighted: Peak voltage (Vp), Valley
voltage (Vv), Peak current density (Jp), Valley current density (Jv), AV = Vv
- Vp, and AJ —Jp - Jv.........................................................................................49
Figure 4.4
Conduction band profiles of both the T-point and X-point minima for an
AlAs/GaAs DBRTD. The offset values were taken from Liu [Liu87 ]............. 54
xiv
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Figure 4.5
Illustration depicting the cross-sectional layer structure and conduction band
profile of a typical AlAs/GaAs QWITT. (Not drawn to scale.)....................... 55
Figure 4.6
Measured J-V characteristics for an AlAs/GaAs DBRTD and an AlAs/GaAs
QWITT with the same quantum well structure. The quantum well consists
of 17A AlAs barriers, a 50A GaAs well and an ainj.= 0.3 (1/Q-cm)................. 57
Figure 4.7
Variation of valley current and PVCR versus temperature for AlGaAs/GaAs
DBRTDs. Taken from [VaL89\........................................................................61
Figure 4.8
Cross-sectional layer structure for a "baseline” AlAs/GaAs DBRTD and the
growth interrupts associated with the MBE growth of the device......................63
Figure 4.9
Impact of series resistance on the I-V characteristics of an AlAs/GaAs
QWITT diode with additional series resistances of 10£1, 20£2 and 30Q
added to the I-V curves. Note that AV decreases with increasing series
resistance.......................................................................................................... 64
Figure 4.10
SEM micrograph showing an alloyed Ni/AuGe/Ni ohmic contact on top of a
mesa isolated AlAs/GaAs DBRTD. This contact was made using a
metallization lift off process where AZ1350J-SF photoresist is used to
define and lift off the contact pattern. Note the metal flags at the edge of the
metallization due to the lift off procedure......................................................... 68
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Figure 4.11
Schematic drawing of Cox-Strack structures used to extract the specific
contact resistivity of the ohmic contact metallization....................................... 69
Figure 4.12
Cross-sectional layer schematic for a spacer layer/doping spike/spacer layer
combination placed downstream (on the anode side) of an asymmetric
AlAs/GaAs/AlAs quantum well. The current density is therefore reduced in
such a structure, but the AV should be increased. The purpose of the AlAs
release layer will be discussed in Chapter 6, section 6.3....................................75
Figure 4.13
J-V characteristics of an AlAs/GaAs DEM-QWITT with a spacer
layer/doping spike/spacer layer combination placed downstream (on the
cathode side) of an asymmetric AlAs/GaAs/AlAs (8ML/18ML/6ML)
quantum well. Note that two measurements were taken as a result of the
amount of hysteresis observed in the J-V characteristics.................................. 76
Figure 5.1
Measured J-V characteristics for a baseline, nominally symmetric
AlAs/GaAs DBRTD. Slight asymmetries in the J-V characteristics are
observed where the Jp is higher, the Vp is higher, and the PVCR is lower, all
in the forward bias mode (Forward bias here implies the electron traverses
the bottom AlAs banier first.)..........................................................................79
Figure 5.2
Illustration showing the cross-sectional layer structure of the AlAs/GaAs
DBRTDs used to examine the impact of intentional barrier thickness
asymmetries on the DC-IV characteristics. Note reverse bias implies
electron injection through the top AlAs barrier first, whereas forward bias
implies electron injection through the bottom AlAs barrier first The top
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AlAs banier thickness, T, was altered to produce nominal layer thicknesses
of 5.0,5.5,6.0, 6.5,7.0, and 8.0 ML................................................................. 81
Figure S3
Peak current density vs. top AlAs barrier thickness for both simulation and
experimental results.......................................................................................... 83
Figure 5.4
Peak current density vs. top AlAs barrier thickness for both simulation and
experimental results.......................................................................................... 84
Figure 53
Peak voltage vs. top AlAs barrier thickness for both simulation and
experimental results.......................................................................................... 85
Figure 5.6
Peak to valley current ratio vs. top AlAs barrier thickness for experimental
results............................................................................................................... 86
Figure 5.7
Ratio of the forward and reverse bias DC-IV parameters versus the top AlAs
barrier thickness. This graph displays the asymmetry in DC-IV parameters
as top AlAs banier thickness is varied. The device with a 5.5 ML top AlAs
barrier is shown to be most symmetric..............................................................87
t
Figure 5.8
Cross-sectional diagram of the Alo.2 Gao.8 As/AlAs/GaAs "chair" barrier
DBRTD used in this study. The AlGaAs "chair" was placed on the top AlAs
barrier based on the higher PVCRs obtained when the "baseline" DBRTDs
were reverse biased. Note that minor conections have been made in the
doping profiles and layer thicknesses in this cross-sectional diagram...............90
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Figure 5.9
Conduction band profiles of both the T-point and the X-point minimums for
the Alo.2 Gao.8 As/AlAs/GaAs "chair" barrier DBRTD. All energies shown
are in reference to the T-point of GaAs. The offset values for GaAs/AlAs
are from Liu [Liu87] and Alo.2Gao.8 from Adachi [ Ada85\............................. 91
Figure 5.10
Measured J-V curves for a standard "baseline" AlAs/GaAs DBRTD and the
AlGaAs/AlAs/GaAs "chair" banier DBRTD, taken by this author. Note that
in the reverse bias mode, the "chair" barrier DBRTD has a slightly smaller
Jp than the standard DBRTD.............................................................................93
Figure 5.11
Cross-sectional diagram of the Alo.3 0 Gao.7 0 As/AlAs/GaAs "chair" banier
QWITT discussed in this section. Here both the AlAs and Alo.3 Gao.7 As
portions of the chair barrier were thinned by one monolayer to examine the
impact on the measured Jp and PVCR............................................................... 94
Figure 6.1
Cross-sectional diagram of the layer structure for the first ELO AlAs/GaAs
DBRTD (MBE Run# 1043) grown in this study. Note that this sample was
grown on a semi-insulating substrate and therefore could not be tested
before ELO. Subsequent DBRTDs (MBE Run#1376) and QWTTTs (MBE
Runs# 1437 and 2028) were grown on n+ GaAs substrates with heavily n+
doped AlAs release layers.................................................................................98
Figure 6.2
Typical forward bias J-V characteristics for the ELO DBRTD and a baseline
DBRTD. The closed circles are the measurements taken for a baseline
AlAs/GaAs DBRTD and the open circles are the measurements taken for an
ELO AlAs/GaAs DBRTD. Note in the J-V characteristic of the ELO
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DBRTD on In/AuCr/glass that the valley current rises faster and the PVCR
and the AV are reduced......................................................................................101
Figure 63
SEM micrograph of an ELO device bonded to an In/AuCr coated glass
substrate after an anneal at 350°C. Note the roughness of the In at the edges
of the ELO film. This type of bond did not survive a "Scotch" tape t e s t..........102
Figure 6.4
Illustration showing a mesa isolated ELO DBRTD or QWITT bonded to a
Pd/AuCr coated silicon substrate. This bond is initially created using a
vacuum bag/oven combination which provides the proper
pressure/temperature combination to cause a solid phase reaction between
the GaAs and Pd to form PcUGaAs.................................................................... 107
Figure 63
SEM micrograph of an ELO DEM-QWITT bonded to a Pd/AuCr coated n+
silicon substrate after an overnight bond in a vacuum bag. Note the smooth
surface with no gaps, bumps or defects at the edges of the ELO film. This
bond is much improved over the In based bonds in terms of bond strength
and reduced defects............................................................................................108
Figure 6.6
Illustration showing a mesa isolated ELO DBRTD or QWITT bonded to a
typical Pd/Ge/Pd coated silicon substrate. This bond is created using a
vacuum bag/oven combination, discussed in Chapter 3, which provides the
proper pressure/temperature combination to cause a solid phase reaction
between the GaAs and Pd to form P&jGaAs. Subsequently, the ELO
film/Pd/Ge/Pd combination are alloyed at 300°C for 5 minutes in order to
form an ohmic contact....................................................................................... 1 1 0
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Figure 6.7
Characteristic J-V data for the ELO Chair barrier QWITT before and after
ELO. Note that the PVCR in both bias directions improved slightly with the
only significant degradation in device characteristics occurring in the AV
due to a higher backside contact resistance after ELO....................................... 112
Figure 6.8
SEM micrograph of particles on the order of 1pm preventing a reliable bond
at the edge of an ELO QWITT layer and its alternative silicon substrate........... 115
Figure 6.9
Photograph showing regions where there were very small bubbles that burst
or broke upon rapid thermal annealing the backside ohmic contacts.................. 116
Figure 6.10
SEM micrograph of a crack that formed in an ELO DEM-QWITT and its
subsequent release from the surrogate substrate................................................ 117
Figure 6.11
SEM micrograph showing the peeling up of the top half of an AlAs/GaAs
DBRTD, above the quantum well, which was not covered properly with
Apiezon W black wax during the lift off in 10% HF......................................... 118
Figure 6.12
Illustration depicting a typical Schottky contacted CPW phase shifter before
ELO. The device processing and testing were performed by M. Saiful
Islam. The ELO processing of this device was performed by this author..........120
Figure 6.13
Illustration showing the ELO CPW bonded to a clear fused quartz slide
using either cyanoacrylates or VDW bonds.......................................................122
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Figure 6.14
Hybrid back-to-back bonding of an ELO CPW and an ELO double
heterostructure LED or multi-quantum well (MQW) LED. Both the ELO
CPW and ELO LED are bonded to the sunogate quartz substrate with
cyanoacrylate.................................................................................................... 124
Figure 6.15
Illustration showing a typical MQW LED type structure designed for
emission of light with a wavelength of = 750nm using software written by
T.R. Block.........................................................................................................125
Figure 6.16
Illustration showing the planarized ELO DBRTD or QWITT utilizing an air­
bridge for device isolation and an LT-GaAs layer for backside isolation
127
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List of Tables
Table 3.1
Physical Properties of Apiezon W Waxes (from [Bid81])................................ 23
Table 4.1
Table of specific DC-IV parameters for a standard AlAs/GaAs DBRTD
grown using the As2 cell and the AlAs/GaAs DBRTD using the As4 cell.
Note that all the layer thicknesses including those in the quantum well are
the same for both devices, as shown in Figure 4.8............................................73
Table 4.2
Characteristic J-V data for the AlAs/GaAs DEM-QWITT with an
asymmetric quantum well and a spacer layer/doping spike/spacer layer
combination placed downstream from the quantum well..................................77
Table 5.1
Comparison of J-V data for a "baseline" AlAs/GaAs DBRTD and the
AlGaAs/AlAs/GaAs "chair" barrier DBRTD. Note that the "chair" barrier
DBRTD obtained a PVCR of 6.3 at room temperature, which remains the
highest PVCR to date for an AlGaAs/GaAs DBRTD. Both of the above
devices were grown by MBE, processed, and DC-IV tested by this author. .... 92
Table 5.2
Characteristic J-V data for a "chair" barrier QWITT structure..........................95
Table 6.1
Characteristic J-V data for the ELO DBRTD (MBE Run# 1043) and a
standard baseline DBRTD. Note the higher peak voltage, lower AV, lower
AJ, and lower PVCR of the ELO DBRTD....................................................... 100
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Table 6.2
Characteristic J-V data for an AlAs/GaAs DBRTD (MBE Run# 1376) both
before and after ELO. Again note the higher peak voltage, lower AV, lower
AJ, and lower PVCR of the ELO DBRTD. Although the device was bonded
to Si, a reduction in the valley current density was not seen. As shown in
Figure 6.3, it is believed that the mechanical and thermal contact to the
backside of the ELO DBRTD did not provide an improvement over the
original substrate............................................................................................... 104
Table 6.3
Characteristic J-V data for an AlAs/GaAs DEM-QWITT (MBE Run# 2028)
both before and after ELO. Note that the PVCR is actually higher and the
valley current lower after ELO, in both bias modes. The AV has decreased
after ELO, indicating that the backside ohmic contact has an overall higher
series resistance................................................................................................. 106
Table 6.4
Characteristic J-V data for an Alo3 Gao.7 As/AlAs/GaAs QWITT (MBE
Run# 1437) both before and after ELO. Note that the PVCR is actually
higher and the valley current lower after ELO, in both bias modes. The AV
has decreased after ELO, indicating that the backside ohmic contact has an
overall higher series resistance.......................................................................... I l l
Table 6.5
Thermal conductivities for various materials. Taken from B.S. Perlman
[Col76\............................................................................................................. 113
Table 6.6
Measurement taken on an ELO CPW before and after ELO. The
measurements were taken by M. S. Islam [IsT91].............................................123
xxiii
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Chapter 1
Introduction
1.1 Statement of Purpose
The initial goals of this research are to investigate the fabrication and
molecular beam epitaxial (MBE) growth related problems associated with the
AlAs/GaAs double barrier iesonant tunneling diode (DBRTD) and the quantum well
injection transit diode (QWITT). The AlAs/GaAs DBRTD, initially investigated by
Tsu and Esaki [TsE73], has been a device of much interest in recent years due to the
transport physics involved and the possible microwave and switching applications of
the device. The DBRTD basically consists of a lower bandgap material (GaAs)
confined by a larger bandgap material (AlGaAs or AlAs) on either side to form a
quantum well. If the larger bandgap material or the barriers are sufficiently thin, then
the electrons can resonantly tunnel through them at specific values of device bias.
Inside the quantum well, there exists discrete quasi-bound states. The QWITT is
basically an extension of the DBRTD where a depleted spacer layer downstream is
added in series to the DBRTD [KeN87]. In-depth discussions of these devices will
be provided in Chapters 4 and 5. There has been considerable work in recent years
on improving the high frequency and output power capabilities of DBRTDs and
QWITTs in oscillator applications. These majority carrier devices are interesting from
the viewpoint that they exhibit negative differential resistance (NDR) in their DC
current-voltage characteristics as a result of quantum interference effects. To operate
as useful oscillators, it is imperative that the lowest specific resistance contacts be
made with repeatability to these devices. Furthermore, doping profiles must be
characterized much more accurately since the spacer layers outside of the quantum
well have a strong influence on the characteristics of the DBRTD and QWITT. Many
MBE related issues concerning asymmetries in the quantum wells also required
investigation. Symmetrically grown DBRTDs tend to exhibit slight asymmetries that
appear to indicate that the top barrier is somewhat thicker than the bottom barrier. In
this research, one of the goals is to determine how much asymmetry exists in these
devices and how these asymmetries effect the resultant DC-IV characteristics.
Initially, efforts in this study centered around the development of an optimum ohmic
1
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2
contact metallization to n+ GaAs. Furthermore, many additional MBE runs were
made to obtain accurate doping setpoints, using capacitance-voltage (C-V)
measurements, pertinent to the DBRTDs and QWITTs. Once these initial problems
were solved and a baseline MBE growth and fabrication process was developed,
efforts to develop new DBRTD and QWITT structures could begin. Such
optimization efforts include the use of composite AlGaAs/AlAs "chair" barriers,
different spacer layer schemes for the QWITTs, and the use of novel fabrication
processes which include the use of image reversal photoresists.
One of the fabrication processes that has been used is the epitaxial lift gff
(ELO) technique [YaG87]. This process, which is described in detail in Chapters 3
and 6 , provides a method to obtain totally substrateless devices whose thin films may
be as thin as 100A. This method is useful due to the fact that an Apiezon W black
wax carrier is used to provide mechanical support to these thin films, thus allowing
easy manipulation and transfer of thin epitaxial films from their original growth
substrates to alternative or hybrid substrates. Although not truly a monolithic
integration process, this method provides a way to place AlGaAs/GaAs thin films on
alternative substrates in a hybrid like fashion and process these films in a monolithic
fashion. Thus this procedure is a form of "hybrid integration". One of the goals
utilizing this method is to separate the high current density AlAs/GaAs DBRTDs and
QWTTTs from their original growth substrates and bond them to substrates of higher
thermal conductivity. As well as ensuring a good mechanical and thermal contact to
the hybrid substrates, a good electrical ohmic contact to the backside of the ELO
DBRTD or ELO QWITT is also required. The materials and processes used to obtain
ohmic contacts to the back of ELO devices are investigated in this work. Hybrid
integration of ELO DBRTDs or QWITTs to silicon substrates will be presented in this
work. Specific issues related to the bonding of ELO films to alternative substrates are
investigated. In addition, the use of adhesive bonds and metal/alloy bonds will also
be presented in Chapter 3.
The ELO method was not only applied to DBRTDs and QWITTs, but to other
microwave and photonic devices of interest to our group. For the optically controlled
Schottky-contacted coplanar waveguide (CPW) structures studied [IsL93], the ELO
method allows optical contact to the backside of the fully depleted epi-layers of the
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3
CPW. Thus, a goal of this research is to grow by MBE the desired epi-layers
required for the CPW structures, perform ELO on these large area devices, and bond
them to transparent substrates such as quartz and glass. Furthermore, the application
of ELO to various light-emitdng devices will be presented as possible integrated
optical sources to other light sensitive ELO devices such as the ELO CPW.
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Chapter 2
Molecular Beam Epitaxy
2.1 Introduction
Molecular Beam Epitaxy (MBE) was developed by A.Y. Cho and J.R. Arthur
in the early 1970's. MBE is the growth of crystals on a host crystalline substrate by
heating a series of elements to a certain vapor pressure in an ultra high vacuum
(UHV), which forms a series of "molecular" beams, and depositing them onto the
host crystalline substrate. Computer controlled evaporation shutters are placed in
front of these evaporation sources, thereby determining which elements strike the
host crystalline substrate at certain pre-chosen instances. The difference between this
technique and a simple evaporation of any element onto any arbitrary substrate is the
fact that film growth by MBE is epitaxial or usually single crystalline. The flux of
elements or molecules striking the surface of the host crystalline substrate can be
controlled individually by adjusting the temperature of each evaporation source, most
commonly referred to as an effusion cell. Since the crystal growth occurs in UHV
(typically < 1 0 -9 torr), the purity of the epitaxial films are primarily a function of the
purity of the elemental source. In addition, the UHV environment allows the use of
in-situ analytical tools such as residual gas analysis (RGA), reflection high energy
electron diffraction (RHEED) and reflection mass spectroscopy (REMS). The
growth rates of the epitaxial films can be controlled very accurately to sub­
monolayer/second resolution, thus allowing precise layer thickness manipulation. In
m-V compound semiconductor MBE growth, some of the elemental sources are
doping sources and therefore allows the precise control of doping profile from layer
to layer. Furthermore, MBE systems have also been used to metallize substrates and
deposit dielectrics in a non-epitaxial manner, which extends its capabilities although
somewhat contradicting the true definition of its name.
The research performed here relies heavily upon the use of MBE to grow
many of the EH-V compound semiconductor device structures studied. In Figure 2.1,
a typical diagram of an MBE growth chamber for HI-V compound semiconductors
configuration is shown. As a result, a basic description of the MBE system used in
4
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5
U L T R A H IG H -U C
/
M ASS
SPECTROM ETER
ELECTRON
GUN
CHAMBER
SURSTRATE
- WAFER
_
LIQUID'
NITROGEN-COOLED
CRYOPANEL
HEATER
EFFUSION
OVEN
RHEEO
SCREEN
\ SHUTTER
DOPANT
Figure 2.1 Illustration showing a typical growth chamber. After M.B. Panish
[Ohr92].
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
A U X ILIA R Y PORT
BEAM FLUX MONITOR
M AIN SH U TTER
T R A N SFER ROD NOSEPIECE
• PREPARATIO N /A NA LY SIS CHAMBER
2 " CONTINU O USLY ROTATABLE
W AFER HOLDER
SUBSTRATE CRYOSHROUD
FU RN A CE/SH U TTER CRYOSHROUD
-A U G E R ELECTRON SPECTROM ETER
VACUUM INTERLOCK
’ M ULTIPLE W AFER LO A DIN G CHAMBER
T R A N SF E R RODS
TITANIUM SUBLIM ATION PUMP
2 0 0 L IT E R /S E C V aclon* PUMP
BA KEOU T IN TERFA CE BO NN ET
SOURCE FLA N G E ASSEM BLY
$
H IGH TEM P. FURN A CES
RECESSED SH U TTERS
•-G U N
GAS HANDLING M AN IFOLD
VACUUM CO N TRO L CABINET
V«cSortfm PUMPS
V tc lo n * PUMP ISOLATION V ALVE
4 0 0 LITER/SEC V ttt o n * PUMP
Figure 2.2 Cutaway view of the Varian Gen II MBE System. Illustration taken from
the Varian Gen II User's Manual.
On
7
this research will be presented as well as some of the MBE related issues specific to
this research.
2.2 Description of the Varian Gen II MBE System
The MBE system used at the Microelectronics Research Center (MRC) is a
Varian Gen II that utilizes as its elemental column HI metal sources: one A1 source,
two Ga sources, and one In source. There are two column V elemental As sources,
one n-type Si dopant source and one p-type Be dopant source. These elemental
sources are placed in effusion cells. These effusion cells basically consist of a
pyrolytic boron nitride (PBN) crucible which holds the source material, heater,
shrouding, thermocouple feedthroughs, and power feedthroughs. For As2 , an
arsenic cracking cell can be used. A cutaway view of the Varian Gen II system that
is used in the MRC is shown in Figure 2.2 with some minor variations. The Gen II
consists of three chambers designated as the load lock (LL), the prep chamber, and
the growth chamber (GC). The load lock is used to load samples from outside
vacuum. The entry point to the load lock is accessed through a pneumatically
controlled gate valve. The load lock is vented with N2 through the manifold which
runs underneath the load lock. Inside the LL are six sample holders attached to a
rotatable carousel. One of these sample holders is a heated station that allows the user
to heat the sample to drive off any moisture once the LL is at vacuum. After all
samples have been loaded, the LL is initially pumped down through the manifold
with a LN2 cooled soiption pump to < 60mTorr. Once at this pressure the manifold
is switched over to a Balzers turbo pump under which the LL is usually pumped on
overnight. In addition, the LL chamber is also heated overnight with heater tape to
aid in driving off any moisture on the chamber walls. Once under adequate vacuum
(< 5x1 O' 5 torr), the carousel allows rotating the samples around so that a specific
sample may be moved with the magnetic transfer rod and the samples can be
outgassed on the heated station. After pumping on the LL overnight, it can usually
achieve pressures in the low-10*7 torr range. At this point, the samples are ready to
be transferred to the prep chamber, which typically is at a baseline pressure of the
low-10*9 torr. The procedure just described helps maintain vacuum integrity when
transferring samples from the LL to the prep chamber.
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8
Upon transferring the samples from the LL to the prep chamber, pumping of
the LL is first switched from the Balzers turbo pump to an ion beam assisted pump
which typically brings the LL pressure down to the lo w - 1 0 -8 torr. Upon opening the
gate valve between the LL and the prep chamber, the LL ionization gauge may
monitor a pressure in the high-10*9 torr range. The original purpose of the prep
chamber was not only an intermediary docking position between the GC and the prep
chamber, but also as an analytical chamber where Auger analysis and other analytical
tools could be used. In our Varian, it is currently used as a location to perform a final
outgass of the sample and its sample block in order to drive off any residual moisture.
The prep chamber is pumped on by an ion beam assisted pump. The prep chamber
also has a titanium sublimation pump which is useful for gettering specific
impurities/gases.
The baseline pressure of the GC when it is in the standby mode is typically in
the mid-10" 10 torr range. In the growth mode, where all the cells are up to their
required setpoints, the pressure may rise as high as the high-10 *9 to the low-10*8 torr
range. The GC is the UHV environment under which all epitaxial layers are grown.
The primary pumps for the growth chamber are two liquid He cryopumps which
typically operate around 15K. These pumps are separated from the growth chamber
by pneumatically controlled gate valves that are closed when the cryopumps undergo
regeneration due to problems with excessive water buildup, As, etc.. In addition,
secondary pumping occurs near the sample through the use of a LN2 cryopanel.
Furthermore, in order to prevent thermal crosstalk between the various effusion cells,
a cryoshroud which separates each of the effusion cells with an isopropyl alcohol
(IPA)-water mixture that is cooled to approximately -12°C is used.
The growth chamber contains a UTI100C mass analyzer that allows one to
perform a residual gas analysis (RGA) everyday to make sure that the system is clean
and that no contamination of the UHV environment has occurred. The growth
chamber also contains an electron gun that is at an angle of approximately 5 ° to the
growth substrate. The beam is directed at a phosphor screen. This in-situ analytical
tool is referred to as reflection high energy electron diffraction (RHEED) and is an
extremely powerful tool for determining growth rates, examining surface growth
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9
kinetics and oxide desorption. A representative drawing of the GC is shown in
Figure 2.1.
The sample is finally transferred from the prep chamber to the GC using the
magnetic transfer rod. The sample block is placed onto a mechanism that can heat the
sample, rotate the sample continuously in the azimuthal direction, and turn the sample
such that it points upward, toward the effusion cells, downward, or toward the prep
chamber. This mechanism is referred to as the continuous azimuthal rotation (CAR).
The CAR can be heated up to 800°C without any special precautions. The CAR can
also rotate the sample at very high speeds, where uniformity is desired, but typical
speeds usually range from 5 rpm to 1 0 rpm and not any higher due to possible
problems with carbon generation [FaC87\ . The issues concerning growth of
epitaxial layers and substrate preparation will be discussed in the following chapters.
23
Substrate Preparation Before Epitaxial Growth
The substrates used in this research were primarily n+ GaAs substrates and/or
semi-insulating GaAs substrates. The specifications on these substrates were 2 inch
substrates with a front etch pit density of less than 500 cm*2. The n+ GaAs
substrates were doped with silicon from 2xl0 18 cm*3 to 4xl0 18 cm*3. Since these
were epi-ready wafers, they were usually cleaved to their desired size, rinsed with
DI-H2 O to remove any GaAs dust and possibly remove some arsenic and gallium
oxides [HiS91] , blown dry with N2 gas, and then mounted on molybdenum (Mo)
blocks with indium. The indium holds the substrate to the Mo block due to surface
tension, provides good thermal transfer between the Mo block and the substrate, and
subsequently provides a very good ohmic contact to the back of the n+ GaAs
substrates. After the substrate is mounted to the Mo block, any excess In is scraped
off the block. Once the samples are loaded in the MBE system, they are typically
outgassed at 450°C for 15 minutes in the LL and one hour in the prep chamber before
being transferred to the GC.
2.4
Growth Kinetics
The m -V compound semiconductor films and heterostructure devices grown
by MBE in this research are primarily in the AlxGai-xAs system (0 < x < 1), as will
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10
be discussed in later chapters. Much has been written on the mechanism of MBE
growth of GaAs and the specific variables which impact the ability to grow device
quality material [Par85] . Specific variables, which must be taken into account in the
growth of GaAs and/or AlGaAs, are the substrate temperature during growth, the
growth rates, and V/HE (As/Ga) incorporation ratio. Since the mechanisms of MBE
growth of GaAs have been widely studied [.FoJ75] [FoJ77] [Joy90] [MoD82\ , a
brief discussion of those mechanisms will be presented here.
The temperature of the substrate during the growth of GaAs was determined
empirically, driven by the results of optical photoluminescent measurements,
electrical Hall measurements, and device related results. Ideally, one would like to
grow single crystalline GaAs at as low a temperature as possible and in fact it has
been shown that GaAs could be grown single crystalline on a GaAs substrate at a
temperature as low as 94°C [NeJ78A] [NeJ78B] . The problem with these low
temperature GaAs layers are that they become highly resistive due to defects and As
precipitates. At these low temperatures, the kinetics are such that the Ga atoms strike
and stick to the substrate and a sufficient amount of As molecules react at the surface
forming stoichiometric GaAs. Since device related requirements forced the substrate
temperatures to be raised, congruent sublimation of As and re-evaporation of Ga from
the growth substrate became an issue [Gra85] . The standard model for growth of
GaAs by MBE is based on the work of Foxon and Joyce [FoJ75] [FoJ77] . This
model examines the growth of GaAs as a function of the As molecule produced
through the sublimation of the elemental As source. This As molecule can either be
dimeric, As2 , or tetrameric, AS4 . The growth of GaAs from AS2 occurs through the
process of "dissociative chemisorption" with a sticking coefficient of < 1 as shown in
Figure 2-3 [Gra85]. Chemisorption, in this context, implies that the molecule loses
its structure through ionic or covalent bonding with the substrate atoms. The growth
of GaAs from AS4 is a more complex process involving the reaction of pairs of AS4
molecules on adjacent Ga sites with a sticking coefficient of < 0.S as shown in Figure
2.4.
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11
Asj incident flux
Surface migration
Dissociative
chemisorption
t
ASj sticking coefficient«1
Go-stabilized GaAs surface
Figure 2.3: Illustration showing the growth of GaAs from Ga and As2 - Taken from
a reproduction of the work of C.T. Foxon in The Technology and Phvsics of
Molecular Beam Epitaxy. E.H.C. Parker, editor
AS/ incident flux
Precursor
state
Migration
E ^ -0 2 5 e V \% *
Chemisorbed state
2nd order reaction
As sticking coefficient <0-5
Go-stabilized Ga As surface
Figure 2.4: Illustration showing the growth of GaAs from Ga and AS4 . Taken from
a reproduction of the work of C.T. Foxon in The Technology and Phvsics of
Molecular Beam Epitaxy. E.H.C. Parker, editor
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12
Therefore, from a practical point of view, in growing a certain layer thickness of
GaAs, one can save up to twice as much elemental As using the cracked dimer over
the tetramer. In actual practice, the As cracker that is used to grow the epi-layers used
in this research is typically set such that not all of the As is cracked.
The typical temperatures for MBE growth of GaAs are usually around 580°C
to 650°C. For growth of the ternary AlGaAs the typical growth temperatures are
usually higher, 600°C to 720°C, due to considerations of surface morphology. It is
well known from RHEED studies, to be discussed in the next section, that Ga atoms
are able to migrate along the surface of the semiconductor during growth whereas A1
atoms tend to react much faster and incorporate themselves into the lattice structure of
the crystal at the same temperatures. Therefore the surface morphologies of AlGaAs
tend to be rougher and generally require growth at higher substrate temperatures to
improve the surface morphology. Furthermore, the growth rates and V/III
incorporation ratio, as determined by RHEED, are extremely important in the growth
of extremely thin layer structures as well as the growth of different A1 mole fraction
AlGaAs layers and an optimized growth surface, respectively. These issues related to
RHEED will be discussed in the next chapter.
2.5
Reflection High Energy Electron Diffraction (RHEED)
RHEED is an extremely important in-situ analytical tool used in the area of
growth and surface studies which allow determination of surface morphology,
accurate determination of growth rates and alloy compositions, determination of the
V/m incorporation ratio, and examination of surface dynamics. RHEED utilizes an
electron beam which is placed at a shallow angle (—1° - 5°) with respect to the growth
substrate and an energy from 1 keV-10 keV. The electron beam emitted from the
electron gun is diffracted off the growth substrate and subsequently creates a
diffraction pattern on a phosphor screen. This diffraction pattern, in the form of a
certain pattern and intensity, is used as a real time monitor of the surface dynamics
and structure on the growth substrate.
The growth substrate surface, in our case GaAs, is typically "As stabilized".
Here As stabilized implies that the GaAs growth surface has an excess of As
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13
molecules which can be ensured by controlling the flux of the As source. Similarly,
Ga stabilized implies that the GaAs growth surface has an excess of Ga atoms.
During actual growth, an As stabilized or As rich condition is maintained. Growth in
Ga rich conditions usually result in non-stoichiometric growth [Gra85] possibly due
to formation of Ga droplets. Different surface reconstructions are observed under As
stabilized or Ga stabilized conditions. Here surface reconstruction is defined as the
different periodicity or arrangement of the atoms at the surface as compared to those
of the bulk due to the incomplete bonds seen at the surface [Woo64] . The surface
structure for a GaAs (001) surface can be designated as (001)-(m x n) which implies
that the unit mesh size at the surface is m times larger in one direction and n times
larger in the other crystal direction. The surface reconstruction for an As stabilized
surface is 2 x 4 and the surface reconstruction for a Ga stabilized surface is 4 x 2, as
shown in Figure 2.5 and Figure 2.6, respectively.
Figure 2.5: 2 x 4 diffraction pattern, (0 °), for GaAs in As-stabilized growth mode.
Figure 2.6: 4 x 2 diffraction pattern, (0 °), for GaAs in Ga-stabilized growth mode.
Therefore, the surface reconstruction can give the structure of the surface whereas the
intensity oscillations are related to the surface roughness during actual growth.
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RHEED intensity oscillations basically represent the nucleadon and island growth that
occurs on the surface, as shown in Figure 2.7.
MONOLAYER GROWTH
ELECTRON BEAM
RHEED SIGNAL
Figure 2.7: Illustration depicting nucleation and island growth that occurs on the
surface, diffraction of the electron beam, and the corresponding RHEED intensity
oscillations taken from the specular spot Taken from The Materials Science of Thin
Films. M. Ohring [Ohr92].
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15
Note that one period of the intensity oscillation is taken to be exactly one monolayer
or atomic/molecular layer. Therefore from the RHEED intensity oscillations, one can
determine the growth rates. For GaAs, one monolayer is 2.83A. Here, the
discussion will be limited to the specific equipment and methods used to determine
growth rates, alloy compositions, and the As/Ga incorporation ratio in this research.
The RHEED setup used in the MRC MBE lab consists of an electron beam
gun with energies up to 10 keV, a phosphor screen attached to the inner edge of a 6
inch viewport and a CCD camera which is fed to a 386 based personal computer with
an imaging card and software that allows digital storage of the diffraction pattern
structure and intensity [MBE91] . From the RHEED intensity oscillations, the
growth rates can be determined very accurately. In addition, alloy compositions of
AlxGai_xAs can be easily determined. Typically, the growth rate of GaAs is
determined and subsequently, the AlxGai-xAs growth rate is measured. By taking
the difference in growth rate of the GaAs and the AlxGai-xAs, the A1 and Ga mole
fractions of the AlxGai.xAs can be precisely determined.
_ Rate(AlxGai_xAs)-Rate(GaAs)
X
RateiAlfia^^As)
.
Growth rates of AlAs can also be taken, but it should be noted that the RHEED
intensity oscillations of AlAs have a tendency to damp out much quicker than GaAs
due to the fact that A1 is much more reactive, tending to stick to the growth substrate
and not migrate as readily as Ga along the surface. For growth of some of the
structures in this research, such as double barrief resonant tunneling diodes, AlAs
growth rates are typically taken since the barrier thicknesses on these devices are
around 17A. Oxide desorption can also be observed by RHEED. As the oxide is
desorbed from the surface of the substrate, the RHEED pattern is seen to change from
a hazy and somewhat spotty 2 x 4 pattern to a much brighter and still spotty 2 x 4
pattern. As growth is initiated and the surface becomes smoother, the RHEED
pattern is observed to change from a spotty appearance to a streaky appearance in the
same 2 x 4 pattern. The importance of the As/Ga incorporation ratio lies in the fact
that the As overpressure plays an important role in the resultant surface morphology
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16
of the sample as well as the electronic quality of the material. If the sample is allowed
to become Ga rich during growth, the sample may lose its stoichiometry and if the
sample is allowed to become too As rich, the onset of deep levels in the material may
occur [Gra85]. The As overpressure used in the growth chamber is typically not
based on the flux rates as sometimes used by other groups since the measurement is
based on the beam equivalent pressures (BEP) ratios as measured by an ionization
gauge. This type of measurement can be strongly affected by initial conditions before
taking the measurement such as base pressure in the growth chamber and transients in
the measurement setup with fairly long decay times as well as system dependent
conditions. The method used in our lab to monitor the As overpressure is referred to
as the As/Ga incorporation ratio, or more generally V/in incorporation ratio. This
method begins with a GaAs wafer in an As stabilized 2 x 4 growth mode .
Subsequently, the As shutter is closed for a specified amount of time, T ^ , selected
by the user of the MBE system. During this time frame the As stabilized surface
converts to a Ga stabilized surface and exhibits a 4 x 2 RHEED pattern. After the
specified amount of time has passed, the As shutter is opened again and the time,
T2 x4 >that it takes the Ga stabilized surface to recover to a 2 x 4 As stabilized surface
is measured. The As/Ga incorporation ratio is then defined as:
Ratio = T?-*2
(2 .2 )
^2x4
2.6 GaAs on SI MBE Growth
The idea and practice of GaAs on Si MBE growth has been around for quite
awhile and while it has not been performed in this research it is important to discuss
the motivations, problems, and alternatives for this kind of research to justify some of
the research that is performed in this work. The motivations for GaAs on Si growth
are that it allows the integration of GaAs devices (photonic and electronic) with the
advanced technology and high integration densities of Si devices which is very
important in making optoelectronic integrated circuits (OEIC) a viable technology in
the future. Furthermore, by growing GaAs on Si, one is placing the active device
epi-layer on a Si substrate with significantly higher thermal conductivity
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17
(approximately 3 times higher) than GaAs. Therefore, heat sinking of structures such
as various heterojunction lasers, IMPATT and other microwave diodes which
generate significant heat can be improved if the active epi-layer and therefore the
junction of the device is placed close to a Si substrate. Furthermore Si substrates are
much more rugged than GaAs substrates and cost much less.
The problems associated with GaAs on Si growth are both growth and
machine related. Initialization of GaAs on Si growth is impeded since the growth of a
polar semiconductor on a nonpolar semiconductor results in antiphase disorder
formation [ChF87] . In addition, there is a 4% lattice mismatch between Si and GaAs
which results in a very large density of misfit dislocations. Furthermore, there is a
difference in thermal expansion coefficient between GaAs and Si that can result in
significant strain, cracking for thick GaAs layers, and even wafer bowing [GoM91].
The machine limitations lie in the fact that the Si substrates cannot be mounted to the
molybdenum blocks with In since the Si will not wet to the In and therefore the Si
substrate must be clipped to the molybdenum block. With this mounting method, the
quality of the thermal contact to the molybdenum block comes into question. Also,
desorbing oxide from the Si requires substrate temperatures of about 800 °C and
some MBE systems are not equipped to handle such high substrate temperatures and
still maintain substrate rotation. Furthermore, since the first micron or so of GaAs on
Si is full of misfits dislocations, very thick buffer layers are usually grown before
device quality GaAs can be grown.
One alternative to GaAs on Si growth is the Epitaxial Lift Q ff (ELO)
technique. This method not only provides the ability to combine GaAs and Si
devices, but also allows integration of GaAs devices with other alternative substrates
of better optical, electronic and thermal properties. The ELO technique is introduced
in the next chapter.
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Chapter 3
Hybrid Integration using the Epitaxial Lift Off Method
3.1
Introduction
The epitaxial lift gff (ELO) technique finds its roots in the earlier works of
Konagai, Sugimoto, and Takahashi where they worked on a "peeled film" technology
for solar cells in 1978 [KoS7S\ and Wu, Coldren, and Merz where they examined the
etch rates of AlxGai-xAs films as the A1 mole fraction was varied from x=0 to x=0.4
[WuC85] . It was only until 1987 that Yablonovitch and co-workers popularized the
ELO method and made it a viable alternative to some of the other monolithic/hybrid
thin film integration methods [YaG87] . Although the other methods, described in
section 3.11, are capable of integrating extremely thin layers of GaAs with Si, the
ELO technique has proven to be one of the most versatile in allowing GaAs
integration with almost any substrate, including nonplanar and transparent substrates.
3.2 General Description of the ELO Method
The epitaxial lift off method, as its name implies, is the complete separation of
large area epitaxially grown AlGaAs films from their growth substrates and
subsequently bonding these films to various other substrates [YaG87]. This
technique utilizes a thin AlAs layer between the epi-layers of interest and the GaAs
substrate. The high etch selectivity of AlAs over GaAs (~ 107 - 108) or low A1 mole
fraction AlGaAs in 10% hydrofluoric acid is used to completely undercut the films of
interest, thus separating them from the GaAs substrate. Since AlAs is extremely
reactive and has been observed to decompose upon exposure to air, it is expected that
an acid such as 10% HF will attack AlAs quite vigorously. The approximate etch rate
of AlAs in 10% HF is 50 pm/min to 60 pm/min [DeP90] whereas the upper limit for
GaAs appears to be no greater than 1 A/hour [YaG87], Through the use of Apiezon
W “black” wax as an HF resistant carrier, the selective etching of these extremely thin
films can be facilitated as well as allowing them to be easily manipulated and bonded
to alternative substrates without any damage. Upon application of the Apiezon W
wax to the sample and insertion into 10% HF, the tension in the Apiezon W wax lifts
up the edges of the epi-layers, thus allowing the by-products of the etch to exit the
18
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19
etch front and allow new etch to enter, as shown in Figure 3.1. The methods of
applying the wax to the sample will be discussed in section 3.2. The main by­
product of the etch is H2 , but other gases may form including ASH 3 . In fact, the
mixture of H2 O and AlAs can result in the formation of ASH 3 . (As a note, since this
process utilizes HF and can cause the possible formation of ASH 3 , however small the
amount may be, the etch should always be performed in a fume hood.) To avoid
cracking of the film and excessive bubble formation, the 10% HF etch environment is
kept at 0°C. The importance of tension in the black wax and its ability to induce a
radius of curvature of several centimeters in the epitaxial film was first investigated
and understood by Yablonovitch and co-workers. The radius of curvature translates
to lifting the epitaxial film up at the edges, thus changing the etch dynamics. Without
taking into account the curvature in the film, the etch flux is equated to the diffusion
flux of the by-products of the etch as follows:
vt3N = —Dt—
dz
(3.1)
where v is the etch rate, n is the molar volume of the dissolved by-products (primarily
H2 ), N is the molar concentration of the AlAs release layer, t is the thickness of the
AlAs, and D is the diffusion constant of H2 \YaG87]. The above equation assumes 3
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20
GaAs!AlGaAs epi-layer
—
3Ntv
AlAs
\
Semi-insulating or n+ GaAs Substrate
Figure 3.1 Illustration (not drawn to scale) of the ELO technique as an epitaxial film
is being separated from its original growth substrate. The tension in the Apiezon W
black wax induces a radius of curvature, R, of several centimeters in the epitaxial film
which promotes removal of etch by-products from the etch front. As expressed by
Yablonovitch, the etch flux is vt3N and the diffusion flux is -Dt dnldz when not
taking into account the curvature[YaGS7]. L is the length of the AlAs channel that
needs to be etched out and t is the thickness of the AlAs release layer.
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21
moles of H2 is produced for every mole of AlAs. If one integrates the above equation
over the total length of the channel, L, and integrates over the total molar
concentration of H2 that can be produced, the maximum speed that the AlAs is
removed can be expressed as [YaG87]:
Note that the total length along the channel, L, that has to be etched is a function of
the dimensions of the Apiezon W black wax. Now, if the radius of curvature is
included in the above analysis, equating the etch and diffusion fluxes is given as
foliows[YaGS7]:
=
(3.3)
Integrating this equation in the same fashion as above, the maximum speed that the
AlAs can be removed is given as:
_
1
Dn
.
v= i
Therefore the total effective channel length that needs to be etched out is now
\Rt
expressed by ttJ — which results in a much smaller value than the actual physical
channel length defined by the wax.
Upon complete lift off, the sample is transferred to a surrogate substrate
where it is bonded by various methods such as van der Waals (VDW) bonds,
adhesive-based bonds, and metal/alloy-based bonds. Once the substrate is bonded to
the alternative substrate, the Apiezon W wax is removed with a solvent such as
trichloroethylene (TCE). This author has found that trichloroethane (TCA) works
just as well and is not as toxic as TCE. In addition, toluene can also be used to
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22
remove the wax, but since TCA is in wider abundance, it was used in this research.
The following sections in this chapter describe in more depth the procedures used for
the epitaxial lift off of a wide variety of films.
3.3 Sample Preparation for Epitaxial Lift Off*
The epitaxial growth of the device structure is obviously the first step in
preparing the sample for ELO. The AlAs release layer, as indicated earlier, does not
have to be very thick and is usually kept within 100A to 500A. Whereas MBE
growth of the active device layers in most of this research occurs at = 600°C, the
growth of the AlAs release layer was usually higher at 630°C in an effort to keep the
surface as smooth as possible before growth of the actual device layers. In addition,
for two terminal devices, where the heavily doped n-type or p-type GaAs substrate
acts as one terminal, the AlAs can also be very heavily doped n-type or p-type with
very little impact on the electrical properties of the device, as shown in Figure 3.2.
The typical Si doping concentration in the AlAs release layer is = 6 x lO1^ cnrA
J ~
\
___
J ~ \
_________________ n+ GaAs buffer layer
___________n+ AlAs release laver (= 100A-500A)______________
n+ GaAs substrate (=500pm)
Indium backside ohmic contact
Figure 3.2: Illustration showing typical cross-section of ELO layer structure for twoterminal mesa isolated device that can be tested both before ELO and after ELO. Note
that mesa etch must be controlled such that the etch does not penetrate the AlAs
release layer.
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23
Therefore, after device fabrication, one can test the devices both before ELO and after
ELO. This allows a direct observation of the impact of ELO on the characteristics of
any such two-terminal device. If an ELO device is grown on a semi-insulating GaAs
substrate, then the AlAs can be grown nominally undoped.
There are many ways in which to apply the Apiezon W wax to the sample
before lift off. In addition, the wax can be applied both before or after device
fabrication depending on the particular process flow that is being used. The majority
of this work is based on devices that have been fabricated first and then lifted off
from their substrates. There are three types of Apiezon W wax, with different
properties as shown in Table 3.1 [BidSl] :
Wax W40
Approximate Softening point, °C
45
Temperature for application, °C
45-50
Coefficient of expansion per °C, over
0.00063
20°C-30°C
Permittivity
2.9
Volume resistivity, ohm/cm2
5.055 x 1015
WaxWlOO
55
80
?
2.7
1.64x1015
Wax W
85
100
0.00062
2 .8
6.31 x 1015
Table 3.1: Physical Properties of Apiezon W Waxes (from [BidSl]).
These waxes are of high purity and have a strong gettering action on greasy or
chemical impurities. This gettering action is based on the very high average
molecular weights of these hydrocarbons resulting in an ability for strong adsorption
[Bid81]. Furthermore, these waxes are chemically resistant to acids such as HF, HC1
and HNO3 . The simplest way to apply the wax to an ELO sample is by melting it
directly onto the sample. With already processed devices, it was found that melting
the wax directly onto the sample did not hurt the metallization or the device structure
at all. With the use of a teflon coated tool, the wax and its shape can be manipulated
and pressed onto the ELO sample. In addition, if the Apiezon W wax is dissolved in
TCA and allowed to dry, it forms a very soft paste that can be applied to ELO
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24
samples without having to heat the sample. Furthermore, if the wax is dissolved in
TCA and not allowed to dry, the liquid mixture of TCA and wax can be spun onto the
ELO sample in a similar fashion as spinning photoresist on a wafer. The advantage
of using a solvent to soften the wax is that shaping the wax becomes easier.
Rectangular shaped wax carriers are reported to work the best due to their radius of
curvature \YaH90], but square or oval shapes with lengths of up to 2 cm also have
been found to work. The disadvantage of using solvents to soften the wax is that the
wax needs to be annealed to drive off all the solvent so that the wax becomes rigid,
hard and dome'Shaped. The dome-shape is believed to assist in lifting the film up at
the edges and provides a smooth round surface which allow a vacuum tool to easily
pick up or manipulate the sample. After application of the black wax to the ELO
sample, exposure of the ALAs at all cleaved edges must be verified. Typically, the
sample edges are cleaved up to the edge of the black wax or a teflon coated tool can
be used to press the wax to the edges of the sample.
For mesa isolated device structures which contain heterojunctions consisting
of AlxGai-xAs/GaAs (with x > 0.5), care must be taken when performing ELO on
these samples since the 10% HF can also attack the device itself. Here the black wax
must be applied such that there is uniform step coverage over the mesas with no gaps
in between the wax and the devices. Upon application of the black wax to these mesa
isolated devices, see Figure 3.3, the wax is re-annealed or re-melted to obtain the
dome-shape in the wax carrier, as shown in Figure 3.4. The height of this dome on
the chip is usually < 0.25 cm. In addition, the mesa isolation etch must not go down
through the AlAs release layer or the ELO method will not woTk since the AlAs
release layer itself is blocked from the 10% HF etchant. Several samples were lost in
this work due to unexpected high etch rates which went through the AlAs release
layers.
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25
Rounded edge teflon press
'oftened Apiezon W black wax
_______ n+ GaAs buffer layer
n+ AlAs release layer (~ 100A-500A)
n+ GaAs substrate (~ 500pm)
Indium backside ohmic contact
Figure 3.3: Illustration of the application of Apiezon W black wax to a mesa isolated
AlGaAs/GaAs heterojunction device. To make sure that good step coverage of the
black wax over the mesas occurs, a teflon press is used to press the softened wax
over the edges of the mesas. The wax can be softened either by raised temperature or
through the use of solvents such as TCA and toluene.
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26
Smooth dome-shaped black wax
carrier after pressing wax and re-melting
n+ GaAs buffer layer
n+ AlAs release layer (~100A-500A)
n+ GaAs substrate
Indium backside ohmic contact
Figure 3.4: Illustration of dome-shape in black wax carrier on mesa isolated
AlGaAs/GaAs heterostructures. The AlAs release layer is exposed at all edges before
inserting the sample into the 10% HF etch.
3.4 Epitaxial Lift Off and Manipulation of ELO Filins
Once the black wax carrier has been properly formed on the sample, the
sample is placed in a 10% HF etch bath that is usually kept at 0°C. The low
temperature is used to prevent excessive H2 bubble formation which can hinder the
complete undercut of the AlAs release layer. The time required to achieve complete
lift off depends on the surface area of the ELO film and cannot be determined from
the extrapolated etch rates of AlAs which represent an upper limit. ELO films with a
surface area of 1cm2 usually take about 5 to 6 hours for complete separation from the
substrate. Films as large as 4cm2 have been separated from the substrate in one
overnight period (=12 hours) while other samples have taken up to 48 hours to
separate from the substrate. As the 10% HF etches the AlAs exposed at the edges of
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27
the cleaved substrate, the tension in the black wax causes the film to peel upward at
the edges, as shown in Figure 3.5.
Mesa Isolated AlGaAs/GaAs
heterostructure devices
Apiezon W Wax
n+GaAs buffer layer
n+ GaAs Substrate
Indium backside ohmic contact
Figure 3.5: Illustration showing the edges of a mesa isolated AlGaAs/GaAs
heterostructure (i.e., AlAs/GaAs double barrier resonant tunneling diodes,
AlGaAs/GaAs double heterostructure LEDs) being peeled back by the tension in the
Apiezon W black wax as the AlAs release layer is being etched out by 10% HF.
With the larger ELO films, care must be taken that the film does not separate from the
substrate and reseat back onto the substrate. In these situations, the ELO film may readhere to the GaAs substrate and become very difficult to remove. In ideal situations,
once the ELO film has completely separated from the substrate, the black wax carrier
and the ELO film will float to the top of the 10% HF. In most situations, though, the
wax carrier and film will separate from the substrate and then slide away from the
substrate but still remain underneath the etch solution. In an effort to circumvent this
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28
problem, the ELO film can be suspended in the etchant with a thin piece of HF
resistant teflon or wire, as shown in Figure 3.6.
Teflon acid
resistant beaker
Apiezon W
Wax Carrier
Figure 3.6: Illustration showing the suspension of an ELO sample in the 10% HF.
Upon complete separation, the substrate drops away from the ELO film.
With the ELO film suspended, re-adhesion to the substrate is avoided and the ELO
film is prevented from touching any part of the teflon beaker or settling down at the
bottom of the beaker where damage to the thin epitaxial film may occur.
Manipulation of the thin ELO films after they have been released from their
substrates involves first the complete dilution of the 10% HF and the subsequent use
of a pen vacuum probe with a rubber or teflon cup. The dome shape of the wax
carrier makes it easily handled by the pen vacuum probe. Forceps or tweezers have
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29
been used and found to cause cracks in the ELO film, even when the edges of the
wax carrier are held. The pen vacuum probe is tied to a water trap, thus allowing
underwater manipulation of the ELO film.
3.5
Issues Regarding Bonding of ELO films
Whereas lifting off the ELO films from the growth substrates is a relatively
straightforward and easy task, bonding the ELO film to alternative substrates without
any cracks, bubbles, or particulate contamination can be very difficult. The process
depends not only on the cleanliness in the process, but also on the type of adhesives
or bonds that are used as well as the properties of the thin film and the substrate.
Adhesion can be defined as the holding together of two surfaces by valence forces,
mechanical anchoring, or by a combination of both. At the interface between a film
and a substrate, a thermodynamic expression can be used to describe the work
required to separate the film and the substrate [Ohr92] :
w = Y f + y , - y fs
(3-5)
where yf is the specific surface energy of the thin film, ys is the specific surface
energy of the substrate, and YfSis the specific interfacial energy. Thus, the properties
of the film and the substrate play an important role in the adhesion between the two.
For W>0, there is adhesion and for W<0, there is repulsion. Since metals have a
high surface free energy, when they come into contact with each other, they have a
tendency to adhere. This property of metals is the reason why the eutectic-metalbonding (EMB) method, mentioned in section 3.11, has utilized a bond between a
metallized substrate and a metallized thin film. The adhesion also depends on the
chemical interaction and interdiffusion that occurs between the two films. In the
following sections, 3.6 and 3.7, a discussion of the various possible bonds used for
the ELO films will be presented.
3.6 Van der Waals (VDW) Bonding of ELO Films
Once the ELO films, which are as thin as 100A, have been separated from
their original substrates, the black wax is used to act as the carrier and to provide
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30
mechanical support. The ELO GaAs films can be bonded to various smooth
substrates through the use of weak, long range electrostatic van der Waals (VDW)
forces [YaH90\ . The various substrates that can be used are any dielectric (i.e.
glass, quartz, sapphire, AI2 O 3 , etc.) and semiconductor (GaAs, Si, InP and
diamond). Van der Waals bonds cannot be made to metals since their electrostatic
charges overlap. To achieve a reliable van der Waals bond, a couple of conditions
must be met. First, the environment under which the bonding takes place must be
absolutely clean. Dust particles not only prevent a good mechanical contact to the
substrate, but may also outgas, form bubbles and damage the film. Etching the
substrates and using an O2 plasma to remove any organic residues is useful in
improving the van der Waals bonds. In addition, if there is no cleanroom
environment in which to perform the bond, bonding in DI-H2 O is very useful [75/92]
\YaS91] . Second, the total bond strength is area dependent and the use of larger area
films may help increase the bond strength between the substrate and the film. Films
on the order of 1 in2 have been lifted off and VDW bonded to other substrates.
Furthermore, the combination of surface tension forces from the DI-H2 O, pressure as
the sample is being bonded, and the temperature of the sample during the bond, all
contribute to a reliable VDW bond. It has been noted that with DI-H2 O in between
the epitaxial film and substrate, an inequality between the surface free energies of the
substrate/film ysf, the water-substrate yws, and the water/film Ywf exists such that the
film and substrate have a tendency to come together, forcing the DI-H2 O outward
[!YaH90].
y^< y«r+ y*r
<3*6)
With the subsequent application of pressure, the majority of the water is pressed out
from underneath the film. The sample is usually left under pressure until all the water
has been driven out from underneath the ELO film through extremely small diffusion
paths. Raising the temperature of the sample to about 50°C to 60°C aids in the
removal of water and the formation of a reliable VDW bond to the substrate.
An improved method to obtain VDW bonds to substrates is through the use of
a vacuum bag [TsR91] . The vacuum bag can be inserted in the DI-H2 O environment
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31
where the sample and substrate are placed In this DI-H2 O environment, a Kim-wipe
can be placed on top of the sample/substrate combination. With the vacuum line tied
to a water trap, the vacuum can be used to draw all the water out of the bag and into
the water trap.
Uniform pressure applied to wax carrier and alternative
substrate with a sealed vacuum bag that can withstand
temperatures up to 80 °C (shown as dashed lines)
\t
n+ GaAs buffer layer
Alternative substrate
(i.e. glass, quartz, sapphire, diamond, and Si)
Figure 3.7: Illustration of uniform pressure applied by vacuum bag to wax carrier as
ELO film is pressed together with an alternative substrate for a VDW bond A lint
free Kim-wipe is placed between the wax carrier and vacuum bag to prevent pinching
off of the vacuum. This process can also be used on the metal/alloy based bonds.
Once the water is removed, the sample and substrate are pressed together with
uniform and even pressure on top of the black wax carrier, as shown in Figure 3.7.
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32
With the vacuum line touching the Kim-wipe, one is guaranteed in preventing the
vacuum bag from pinching off the vacuum and therefore the uniform pressure over
any portion of the ELO sample. The vacuum speeds removal of moisture from
underneath the ELO film. In addition, the vacuum bag can be placed in an oven for
any raised temperature bonding cycles that may be required.
The
pressure/temperature variables are very important parameters for a good VDW bond.
Pressure as high as 15 lb/in2 have been used without any breakage or cracking in the
epitaxial film [Trf?97]. The temperature should be kept below the softening point of
the wax carrier unless specifically testing the elasticity of the ELO film. In this work,
pressures between 7-15 lb/in2 and temperatures from 30°C - 60°C have been used.
This technique is an improvement over the simple placement of a weight on top of the
black wax carrier. In addition, the pressure can be adjusted with a pressure regulator.
Avoiding bubbles in the ELO films bonded to other substrates is very difficult
even when using a clean room environment or DI-H2 O environment If there are any
asperities or defects which may trap moisture or gas, bubbles may form after bonding
and degrade the overall bond to the substrate. In addition, when patterning and mesa
isolating these ELO films down to the alternate substrates, the overall reliability of the
VDW bond is degraded because the total surface area has been reduced. If the
patterned ELO films are very small, on the order of 100 pm2, it has been observed
that their bonds to the surrogate substrate do not survive. Demeester and co-workers
report similar findings, but also indicate that the bubble size is proportional to the
thickness of the epitaxial film thickness [DeP90]. Therefore, the VDW bonds of
thinner films that are mesa isolated all the way down to the surrogate substrate have a
higher percentage survival rate over thicker films. This author also observes the same
trends for thinner and thicker films, but feels the trend may be more a function of the
etch time required to completely mesa isolate these films; thinner films require less
time in the etchant than the thicker films. The etchant, usually peroxide based, can be
quite exothermic as well as turbulent and can separate the ELO films from their hybrid
substrates. Combined with a reduced mesa size, the films ability to adhere to the
substrate is degraded. Bubble size and bubble density in the ELO films seem to be
more a function of the actual bonding technique, substrate surface, and particulate
contamination.
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33
3.7 Adhesive and Metal/Alloy Based Bonds to Alternative Substrates
With the limitations of the VDW bonds, other bonding methods have been
investigated. The two primary methods are adhesive based bonds and alloy based
bonds. The type of bond is basically determined by the type of device and alternative
substrate one is working with. For a two-terminal device structure with one contact
on top and the backside used as another contact, both a mechanical and electrical
contact must be made to the backside of the ELO layer. For a planarized
microwave/millemeter wave device, where all the electrical contacts are made on the
top, it may be more appropriate to place this type of ELO device on an insulating
substrate where the dielectric constant is lower than that of the original GaAs
substrate. For optical studies of quantum wells and bulk material, it is sometimes
desired to obtain complete transmission through the film which can only be
accomplished if it is put on a transparent substrate. Furthermore, for devices which
generate significant amounts of heat, such as semiconductor lasers and impact
ionization avalanche transit time (IMPATT) diodes, bonds to substrates with very
high thermal conductivity are important. Here, the adhesive or metal/alloy must,
itself, have a high thermal conductivity.
Adhesive bonds to transparent substrates were initially investigated by
Yablonovitch and co-workers [YaK89] . Here they used Norland Optical Adhesive
61 which is a clear, transparent, optically curable liquid photo-polymer. In addition,
cyanoacrylates have been used primarily in this work when bonding ELO films to
transparent substrates. Whereas the VDW and metal/alloy bonds are performed in a
DI-H2 O environment, the adhesive bonds usually involve immediate transfer of the
ELO film from the completely diluted etch environment to the alternative substrate.
The main benefit of these optically transparent adhesives is that they allow optical
contact to the back of the ELO device layers. Furthermore, these optically transparent
bonds have the ability to survive complete mesa isolation to the substrate whereas the
VDW had a tendency to fail when the ELO film was mesa isolated. In Figure 3.8, =
16pm2 blocks of GaAs were mesa isolated to the quartz substrate. Here the epitaxial
GaAs film was 3 pm thick. When using cyanoacrylates as an adhesive, care must be
taken not to get the cyanoacrylate on the black wax carrier since the cyanoacrylate
does not dissolve in TCA and makes subsequent removal of the wax carrier difficult
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Care must be taken not to allow the acetone to attack the cyanoacrylate b
film and surrogate substrate. Quick rinses in acetone are usually not a pn
The use o f conductive silver-based epoxies (Epo-Tek H20E,
H20D) and polyimides (Epo-Tek P10) was also investigated as a means
an electrical contact to the backside of the ELO layers. Since these i
polyimides required thermal curing, the vacuum bag/oven combinatio
The results on all of the silver-based conductive adhesives were not
provide a damage free mechanical bond to the ELO films. The failure
attributed to the size of the silver flakes which are dispersed in the <
polyimide. The thickness of these flakes appear to be as thick as the
causing significant cracking in the ELO films and poor mechanical cc
substrate.
Figure 3.8: SEM micrograph showing the complete mesa isolation of an
ELO film into = 4pm by 4pm islands. The "mushroom" cap on top o
island is the remaining photoresist after the mesa etch.
R eproduced w ith perm ission o f the cop yrig ht ow ner. F urthe r rep rod uction prohibited w ith o u t perm ission.
35
Figure 3.9: SEM micrograph showing an ELO film that has been bonded to P-20
silver polyimide. Note that the size of the silver flakes appear to be on the order of
the ELO film thickness and does not provide a smooth flat bond line.
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36
For electrical contacts, especially ohmic contacts, to the backside of ELO
layers, the metal/alloy based bonds have been much more promising. Some of the
earlier efforts include bonding of the ELO film directly onto Au-coated substrates
[YoD91] lYoF91] and by the deposition of AuGe/Ni onto the backside of the ELO
layer just after it had separated from the substrate [PoD90] . From the metalsemiconductor contact literature, Au can react with GaAs through a dissociative
diffusion process at fairly low temperatures including room temperature, but can also
result in severe pitting in the GaAs with pit dimensions larger than a micron once the
sample is annealed [WeF88 ] . Furthermore, it is well known that Au contacts to
GaAs result in nonuniform, spiking contacts. No discussion was given in these
works about the specific contact resistivity of the backside contact. Evaporation of
AuGe/Ni onto the backside of ELO films in this research has proven to be
unsuccessful due to severe deformation of the wax carrier and cracking of the ELO
film from the heat generated by the evaporation sources. Another method to obtain
ohmic contacts to the backside of the ELO layers involves directly bonding the ELO
layer onto In/AuCr coated substrates. After bonding the films to the substrates is
complete, the wax carrier is removed in TCA and the ELO sample/substrate
combination is alloyed at a temperature of approximately 350°C, which results in a
graded InAs/InGaAs/GaAs ohmic contact [LaK84] . This method has been shown to
provide adequate ohmic contacts to some of the devices in this work. Although the
electrical ohmic contact to the backside of the ELO sample is adequate, the mechanical
contact was rather poor and did not survive a simple "Scotch" tape test A typical
bond to a In/AuCr substrate is shown in Figure 3.10. In an effort to improve the
mechanical bond to the In, flux was applied to an In coated substrate before an ELO
sample was bonded to it [Cam91] . The surface morphology seemed to be slightly
improved, but the bond still did not survive a tape test Yablonoviteh and co-workers
were the first to find an improved bonding method to any type of substrate through
the use of a palladium, Pd, based bond \YaS91], In this study, bonds to substrates
coated with Pd were found to occur at low temperatures (< 200°C) including even
room temperature, provided an ohmic contact to heavily p and n-type doped GaAs
ELO films, and were quite reliable and strong even surviving "Scotch" tape tests.
The basis for this improved bond is the low temperature solid phase reaction between
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37
GaAs and Pd which forms Pd^GaAs similar to the dissociative diffusion process
between Au and GaAs mentioned earlier. The Pd displaces any native oxides and
reacts with the GaAs. With Pd based contacts to GaAs, it is well known that they are
non-spiking and therefore produce a much more uniform and smooth interface.
Regardless of the topography, even if it is slightly nonplanar, the ELO film can
elastically conform to the substrate and react with the Pd. Therefore, this reaction
process has been referred to as a solid-phase "topotaxial" reaction [YaS91]. This
process has been extremely useful in this research allowing a wide variety of bonds to
many different substrates such Si, quartz, and copper. A typical SEM of an ELO
bond to Pd is shown in Figure 3.11.
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38
Figure 3.10: SEM micrograph of an ELO device bonded to an In/AuCr coated glass
substrate. The specific contact resistivity of the ohmic contacts were indirectly
extracted and found to be 8 x 10^ O-cm2. The mechanical contact and bond strength
were poor. Note the roughness of the In at the edges of the ELO film.
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39
Figure 3.11: SEM micrograph of an ELO device bonded to a Pd/AuCr coated Si
substrate. The electrical ohmic contacts were indirectly extracted and found to be = 1
x 10' 5 O-cm2. The mechanical contact and bond strength was very good. Note the
smooth morphology of the Pd surface and the excellent bond at the edges of the film.
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40
3.8 Hybrid substrates used in ELO
One of the optimal alternative substrates is silicon which provides the
opportunity to integrate AlGaAs/GaAs devices with silicon devices. Furthermore, the
surrogate silicon substrate acts as a better heat sink with - 3 times the thermal
conductivity than that of GaAs. In addition, as stated earlier in Chapter 2, the silicon
substrates are more rugged and cost significantly less than GaAs substrates.
Alternative quartz substrates also offer special advantages since they are transparent
and have a lower dielectric constant than the GaAs substrate. Substrates with large
electro-optic coefficients and low losses, such as lithium niobate (LiNbC>3 ), were
found to be useful in coupling ELO metal-semiconductor-metal (MSM) detectors with
the LiNbOs waveguides [YiC89] . Substrates of even higher thermal conductivity,
such as copper, diamond Ha, and silicon carbide, have become viable candidates as
hybrid substrates for an ELO device through the use of Pd based topotaxial bonds. A
discussion of bonding double barrier resonant tunneling diodes to substrates of
higher thermal conductivity will be presented in Chapter 5.
Pre-pattemed or nonplanar substrates of any type, (copper, Si, glass,
LiNb 0 3 >, are of interest from the viewpoint that the ELO film can be made to
conform to the shape of the substrate or bend over the substrate. Within the elastic
limits of the ELO film, it can be made to conform to the shape of the substrate without
damage to the ELO film. Studies have been performed with ELO GaAs/AlGaAs
quantum wells placed over pre-pattemed substrates for purposes of examining the
effects of strain induced lateral variations in the bandgap of the semiconductor
[ChR92] . Furthermore, beyond the elastic limits of the ELO film, pre-pattemed
substrates can be used to define the manner in which the film is cleaved. In other
words, the pre-pattemed substrate can be used to define the physical dimensions of a
certain device. In this situation, alignment of the film to the substrate becomes a very
important issue. Methods as simple as marking or scribing the wax carrier before
ELO and using these scribes as alignment keys after ELO can provide reasonable
alignments to substrates. More advanced methods include the use of transparent
polyimide diaphragms as transfer mediums for the ELO films [CaH91].
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41
3.9 Epitaxial Lift Off of Strained Layer Films
The insertion of an AlAs release layer in the layer structure of any common
AlGaAs/GaAs heterostructure device results in minimal strain in the films since the
lattice mismatch is only about 0.1%. For the InGaAs/InAlAs heterostructures latticed
matched to InP substrates, the insertion of an AlAs release layer results in
considerable strain with a lattice mismatch of about 3.5%. If the typical AlAs release
layer thicknesses used on AlGaAs/GaAs device structures, as shown in the previous
illustrations, were used in InGaAs/InAlAs layers, there would be a significant amount
of dislocations and defects. The motivation for applying the ELO method to the
InGaAs/InAlAs system is that it extends the range of devices that can be studied, such
as longer wavelength photonic devices [ScG89] and higher current density, higher
r.f. output power double barrier resonant tunneling diodes (DBRTDs). The strain
induced from these layer structures can impact the overall radius of curvature of the
film. The critical layer thickness for InGaAs on AlAs is around 50A and based on the
discussion in section 3.1, any ELO layer structure with an AlAs release layer of ^
50A should not face any significant difficulties in allowing the 10% HF to completely
separate the ELO film from its InP substrate. In our work, we have been able to lift
off InGaAs/AlAs DBRTDs from their InP substrates using 40A AlAs release layers.
Such a structure is shown in Figure 3.9, which was bonded to a conductive
polyimide on Si.
The metallization of the epitaxial films can also contribute to the overall strain
that the film is exposed to. ELO layers with metallizations as thick as 1.2 |i.m and
covering = 90% of the sample surface area were successfully lifted off with no
observed difficulties [IsT91] . In fact, it is believed that this thick metallization
provides additional support for the fragile ELO film during sample manipulation and
bonding. Pollentier and co-workers have shown that Pd/Ge metallizations induced
the least amount of stress compared to AuGe/Ni, AuZn, and TiW/Au metallizations
[PoZ91] .
Although ELO has been proposed as an alternative for GaAs on Si growth,
there has been work performed that combines the two technologies in an effort to
relieve the strain in the heteroepitaxial GaAs on Si [DeV91] [BuF92A] [BuF92B] .
This method, referred to as mesa release and deposition, MRD, by some, involves
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42
the insertion of an AlAs release layer on heteroepitaxially grown GaAs on Si. The
device layers are subsequently processed and mesa isolated down past the AlAs
release layer. Then through the use of a "photoresist clamp", rather than the usual
Apiezon W black wax carrier, the AlAs release layer is etched out, thus relieving the
strain in the GaAs film, and subsequently rebonding the layer back onto the Si. This
method has the advantage of placing strain free GaAs films on Si, just like in the
standard ELO method, but also has the advantage of not having to deal with the
difficulties involved with sample transfer and manipulation of very thin and fragile
epitaxial films. The MRD method also avoids having to use solvents such as TCA to
remove a black wax carrier and instead rely on the simple removal of the photoresist
with acetone. This method does not address issues concerning ohmic contacts to the
backside of the lifted off layers and apparently requires a planarized process. The
MRD method solely addresses the issue of strain relief in GaAs on Si films and does
not allow the benefits that are intrinsic to the ELO process, such as bonding to
alternative substrates that are transparent or of higher thermal conductivity.
3.10 Epitaxial Lift Off of Silicon on Insulator (SOI)
As a proof of principle, the ELO method was performed on some silicon on
insulator (SOI) material obtained from IBM [Kes91~\. A typical cross-section of the
SOI material used is shown in Figure 3.12.
Si overlayer (1330A)
SiC>2 (Buried Oxide) (4750A)
Si Substrate (1-2 Q-cm)
Figure 3.12: Cross-sectional schematic of a silicon-on-insulator (SOI) sample used
in the ELO process. A standard 49% HF solution was used to etch out the oxide as
the Si overlayer was held to a Apiezon W black wax carrier.
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43
The application of the Apiezon W black wax and ELO process used on this SOI
sample were very similar to the AlAs/AlGaAs/GaAs structures described in the
previous sections. The only major difference here was the use of a standard 49% EOF
solution to etch out the oxide from underneath the Si overlayer. The Si0 2 (oxide)
underneath the Si overlayer is not thermally grown oxide but created through a threestage oxygen implant and anneal process [Kes91]. Although no data could be
collected on the etch rates of this type of oxide in 49% HF, a figure of merit that can
be used is the 300A/second etch rate of thermally grown oxides at 25°C \WoT86 ] .
Note that this etch rate of thermally grown Si0 2 is much slower than the quoted etch
rates of AlAs, which are about 50-60 pm/minute [DeP90\. With these much slower
etch rates, the complete separation of the Si overlayer from its substrate required
about 2 days for a 1cm2 sample. Upon complete separation from the substrate, the
sample was VDW bonded to a quartz slide. Once the Apiezon W black wax was
removed from the ELO Si Elm, it was observed that the Elm was multi-colored,
which was probably due thickness variations in the original Si overlayer that could be
observed before ELO. The motivation for this experiment was more a test of
principle rather than using ELO as a tool for fabricating thin Si film devices. In the
silicon area, the technologies are much more mature including those used in
developing extremely thin film devices such as the Bond and Etchback SOI (BESOI)
method [Las86] [HunSS] and the use of a high energy boron implant that can be used
as an etch stop combined with BESOI [.MaP91] . Using the BESOI method, four
inch wafers have been thinned to 1000A ± 100A for very thin, single crystalline
substrates used for fabricating CMOS devices [Mas91] . The current level of
development of the ELO process and the fact that the etch rate of the oxide underneath
the Si overlay is = 30 times slower than that of AlAs does not provide a viable
alternative to the more developed BESOI technologies.
3.11 Alternative Processes other than the ELO Process
Other thin film monolithic/hybrid integration methods include GaAs on Si
MBE growth, ponding by atomic rearrangement (BAR) where currently
InP/InGaAsP structures and possibly GaAs/AlGaAs structures are bonded to silicon
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44
\LoB91\ and bonding by sutectic-metal-honding (EMB) where GaAs/AlGaAs
epitaxial films are grown on lattice matched and nearly thermal matched Ge substrates
\VeT92\. The disadvantages associated with GaAs on Si MBE growth have already
been previously mentioned in Section 2.6 of Chapter 2. Both the BAR and EMB
methods have the disadvantage of having to completely etch back the substrate,
generating a significant amount of GaAs waste by-products. In addition, both
methods use a fairly high (> 400°C) temperature cycle for bonding GaAs to Si.
Although all the methods described above are capable of integrating extremely thin
layers of GaAs with Si, the ELO technique has proven to be the most versatile in
allowing GaAs integration with almost any substrate, including nonplanar and
transparent substrates. Anodic bonding of GaAs to glass has been investigated for
purposes of attaching optoelectronic devices to optical fibers [H3C83] , but the
process is rather involved requiring temperatures of 360°C and applied voltages of
800V. The ELO method allows bonds to a wide variety of transparent substrates
such as glass, quartz, sapphire, and diamond.
For InGaAs/InAlAs films grown latticed matched to InP substrates, a highly
selective HC1 substrate back-etch provides a useful alternative to the ELO method
[YiC90] . Since the ELO method requires the insertion of an AlAs release layer,
which induces strain in the InGaAs/InAlAs films, an alternative method may involve
etching back the InP substrate with HC1 which has a high etch selectivity over
InGaAs. Furthermore, for device structures which may already have strain from the
intrinsic device structure itself, such as AlAs/InGaAs structures, the additional strain
from the AlAs release layer may not be desired. Thin film, substrateless
AlAs/InGaAs double barrier resonant tunneling diodes have been fabricated using this
substrate back-etch technique and were topside bonded to alternative substrates using
silver epoxy. Selective back-etching of GaAs substrates that have AlGaAs etch stops
have also been performed using NH4 0 H:H2 0 2 , but the etch selectivities are not as
high and not as controllable [AnE75] [LeP80] . Again, the drawback to these
substrate back-etch methods is the amount of waste by-products produced in
selectively etching away the whole substrate to get the desired thin films whereas the
ELO method etches away an extremely thin AlAs release layer and leaves behind a
reuseable substrate.
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Chapter 4
AlAs/GaAs Double Barrier Resonant Tunneling Diodes
4.1
Introduction
The existence of cLc. negative resistance devices has been observed since the
late 1950's in many different structures or devices that utilized thin anodic oxides
[Hic62], degenerately doped p-n junctions (tunnel diodes) [Esa58], and
heterojunction devices where quantum interference effects are utilized (double banier
resonant tunneling diodes and real space transfer devices) [TsE73] [HeM79] . The
negative differential resistance (NDR) in the I-V characteristics of these devices has
been used in many applications involving microwave/millemeter wave oscillators,
high speed logic devices and switches.
Of these devices, the double barrier resonant tunneling diode (DBRTD) has
gained the most attention in recent years with the improvements in molecular beam
epitaxial (MBE) growth. Originally proposed by Tsu and Esaki [TsE73], the first
experimental observation of resonant tunneling in a double barrier structure occurred
in 1974 by Chang, Esaki and Tsu [ChE74] . It was only until 1983 that significant
interest in the DBRTD occurred when the first high frequency experiments utilizing
these structures was performed by Sollner and co-workers [SoG83]. Subsequently,
a flood of research was performed on the DBRTD ranging from fundamental
quantum transport theory, new materials and MBE growth related issues, high
frequency oscillator applications, logic and switching applications, and three-terminal
resonant tunneling structures [CaK85] [ReF89] [S5A88] [SeC88 \ [!TaM88] [SeK92]
. High frequency oscillations of up to 712 GHz have been observed in InAs/AlSb
DBRTDs [BrS91] . Switching times as low as 2 picoseconds have been observed
using electro-optic sampling on AlAs/GaAs DBRTDs \WhM88 \ .
In this chapter, some of the basic principles of the DBRTD will be presented.
The current MBE growth and fabrication procedures for the AlAs/GaAs DBRTDs and
Quantum 2£ell Injection Transit (QWITT) diodes used in this research will be
summarized. In addition, issues concerning barrier asymmetries in the quantum well
of our DBRTDs and how they affected the resulting DC-IV characteristics will be
addressed in Chapter 5 . Comparisons of the experimental results will be made with
45
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46
device simulations from both a Schrodinger-Drift/diffusion model [Mil93] and a
Schrodinger-Poisson model [Gul91] .
4.2
Background Discussion for the AlAs/GaAs DBRTD
The concept of resonant tunneling of electrons can be generalized in the
Kronig-Penney model where the periodic square well potentials result in allowed
values of energy and forbidden gaps in energy. In these allowed bands of energy,
there can be resonant transmission of electrons. Analogous structures are realized
artificially with AlGaAs/GaAs superlattices grown by MBE where the allowed values
of energy (minibands) are dependent on the well widths and the barrier heights. In
these structures, Tsu and Esaki proposed that the application of an electric field to the
structure would result in NDR. A typical AlAs/GaAs double barrier resonant
tunneling diode (DBRTD) is formed by sandwiching a GaAs quantum well between
two AlAs tunnel barriers as shown in Figure 4.1. Also see Figure 4.8 for a more indepth cross-sectional layer structure.
Spacer layers
Figure 4.1: Illustration of the T-T conduction band profile of a typical AlAs/GaAs
DBRTD, similar to those grown by MBE in this work. The conduction band offset
between I aias and ToaAs is = 1.04 eV.
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47
For the double barrier resonant tunneling diode (DBRTD), the phenomenon
of resonant transmission of electrons through the double barriers may not be intuitive
at first. In order to describe the nature of resonant tunneling through double barrier
structures, we first examine the transmission coefficient, T b (E z), as a function of
electron energy for a single barrier. Classically the transmission coefficient would be
zero. From quantum mechanics, it is well known that even if the electron has an
energy less than the height of the potential barrier, there exits some probability that
the electron can tunnel through the single barrier if it is thin enough. A plot of the
transmission coefficient versus energy is shown in Figure 4.2.
1.0
0 .8 s:
6
T*T(Single)
T*T(Double)
0.6 -
a
a©
0 .4 -
i
0.0
0.0
0.2
0.4
0.6
0.8
Energy (eV)
Figure 4.2: Plots of the transmission coefficient versus electron energy for an
AlAs/GaAs single barrier structure and a double barrier structure. The barriers are
17A and the quantum well of the DBRTD is 50A. Plot courtesy of K.K. Gullapalli.
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48
For a DBRTD with barriers of the same thickness as the single barrier, the total
transmission coefficient, T2b(Ez), for both barriers exhibits an interesting feature.
T2b(Ez) shows resonant peaks in its features that are approximately equal to one at
lower energies than T b ( E z ) . The resonant peaks in the transmission coefficient
versus electron energy curve imply that when an electron obtains the energy where
one of the resonant peaks exists, the probability for the electron to tunnel through the
double barriers is approximately one. The way in which the electron obtains this
energy in an actual DBRTD is through the application of an electric field across the
device. The kinetic energy can be expressed as follows,
(4.1)
where EZ(V) is the longitudinal energy or energy parallel to current flow, m* is the
effective mass and E, = —— is the transverse energy. The transmission coefficient
2m
is calculated using the transfer-matrix method \TsE73] [RiA84\ . Subsequently, the
current density in the DBRTD can be determined from the Tsu-Esaki model as:
\ TzB{El)N{Et)dEi
where
(4.2)
is commonly called the "supply function" [GuR89] which is defined as;
(4.3)
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49
Figure 4.3 (a) shows the various steps in the operation of an AlGaAs/GaAs
DBRTD. Figure 4.3 (b) defines specific J-V parameters of interest for DBRTDs.
w. w, w,
u-U—
AE
Z
o
(A
<a
O
1 ZS |
I l*-l<
I, <O I. <IB I, <IB I.
I oI o I a I
r>
O
z
<a
O
VOLTAGE
VOLTAGE
(a)
50
40
AJ
I
30
*9
20
s:
£
5
10
4
0
0.0
V
v
1.0
1.5
(b) Voltage (V)
Figure 4.3: (a) Illustration depicting the operation of an AlGaAs/GaAs DBRTD as a
voltage is applied to the device. Taken from Sollner, etaL[5oG53]. (b) Measured JV characteristics of an AlAs/GaAs DBRTD with specific parameters of interest
highlighted: Peak voltage (Vp), Valley voltage (Vv), Peak current density (Jp), Valley
current density (Jv), AV = Vv - Vp, and AJ = Jp - Jv.
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50
The resonant peaks correspond to the energy levels of the quasi-bound states in the
quantum well when at thermal equilibrium or when the device is not under a voltage
bias. When a voltage bias is applied to the right side contact of the DBRTD shown in
Figure 4.3, the conduction band of the right side contact is pulled down, bringing the
first quasi-bound state in the quantum well more in line with the left side contact
Fermi level. Note typically these contacts are degenerately doped and therefore the
Fermi level is usually in or above the conduction band edge. Thus the supply of
electrons in the left side contact begin to tunnel through the double barriers and the
current in the I-V characteristic increases. As the voltage is increased further, the
electrons in the left hand side contact gain more energy and the supply of electrons on
the left hand side contact become lined up with the first quasi-bound state in the well.
This is the point at which the transmission probability is a maximum and the supply
of electrons is the greatest for tunneling through the double barriers. This point
shows up as the peak current, Ip, in the I-V characteristics. The voltage at which the
Ip occurs is referred to as the peak voltage, Vp. Ideally, this voltage is given as
Vp > ^ '
e
(4.4)
but in most actual devices there are lightly doped spacer layers near the quantum well
which result in voltage drops on both the accumulated and depleted side of the well.
As the voltage is increased still further, the quasi-bound state is now pulled below the
Fermi level of the left hand side contact and the supply of electrons decreases. Thus a
drop in the cun-ent in the I-V characteristics is seen which is the well known NDR
phenomena we mentioned earlier. Finally, as the voltage is still increased even
further, the current is seen to rise in the I-V characteristics. This rise is attributed to
thermionic emission over the barriers or Fowler-Nordheim type tunneling through the
upper comer of the barriers.
43
Simulations Used for Analyzing the DBRTD
With the simple Esaki-Tsu model, predictions of the peak current density of
DBRTDs are possible, but to date accurate simulations of the I-V characteristics of the
DBRTD over its whole operating range have not been achieved. A step closer to
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51
those goals was obtained when the space charge effects in DBRTDs were taken into
account by using a self-consistent calculation that couples the Schrodinger equation in
the quantum well region to the drift-diffusion equation in the rest of the device
[MH93] or the Schrodinger-Poisson model [CaM87] [Gul92]. Both the
Schrodinger/Drift-Diffusion models and the Schrodinger-Poisson models have been
used by the author as a tool for designing and understanding certain DBRTD device
structures that will be discussed later. The main distinction between the
Schrodinger/Drift-Diffusion model and the Schrodinger-Poisson model is that the
electric Held is assumed to be constant across the quantum well in the
Schrodinger/Drift-Diffusion model [M il93]. In the more commonly used
Schrodinger-Poisson model, the electric field is calculated at every point in the device
structure. Accurate values for the peak voltage can be predicted once all the external
parasitic and series resistances from the contacts were taken into account in both
models. The Schrodinger-Poisson model relies on the converged solutions of V(z),
'PCkz.z), and n(z) in the following equations [MiT89] :
+ V(z)'¥(kt ,z) = Et'¥(k',z)
(4.5)
where m* is the position dependent effective mass, Ez is the longitudinal electron
energy, ^¥(kz,z) is the electron wavefunction, and V(z) is the effective potential
energy which can be described as:
V(z) = - c ^ . ( z ) + ^ ( z ) + Vxe(Z)
(4.6)
where <feiec(z) is the electrostatic potential, Vh(z) is the effective potential energy due
to the heterojunction offset, and Vxc(z) is the local exchange-correlation potential
energy [SrSS4] which is included in a few of the models used to simulate DBRTDs
[GaD92] . The electron concentration, n(z), and the Poisson equation are given as
follows:
(4.7)
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52
<4 - 8 >
where e(z) is the position dependent dielectric constant, N d + ( z ) is the ionized donor
concentration, and n(z) is the free electron concentration. Although the SchrodingerPoisson model provides good quantitative results for the peak current density, Jp, and
the peak voltage, Vp, it does not provide a good estimate of the valley voltage, Vv or
the valley current density, Jv, and therefore the peak-to-valley current ratio, PVCR.
(See Figure 4.3 (b)) Many mechanisms which contribute to the valley current are not
taken into account by the simple Schrodinger-Drift/diffusion model or SchrodingerPoisson model. Some of these mechanisms include interface roughness scattering
[GuR89\, r-X mixing [MeW87] , and phonon-assisted tunneling [ChV89\ .
Furthermore, the above mentioned coherent tunneling models do not take into
account the energy loss mechanisms that occur in the depleted spacer layers. Without
including these energy loss mechanisms, there is a gross underestimation of the
electron concentration in the depleted spacer layers and the magnitude of the space
charge resistance is underestimated. A recent "hybrid" model has been used to take
into account these energy loss mechanisms in which the coherent tunneling model is
used to account for electron injection from the double barrier structure and the
Boltzmann transport equation is used to account for the semiclassical dynamics which
occur in the depleted spacer layer [GuM91] . This hybrid model is useful in properly
accounting for the space charge resistance in DBRTDs with long spacer layers. It
should also be mentioned that more advanced simulations of DBRTDs have been
implemented using the quantum kinetic equations such as the Wigner distribution
function or the Lattice Wigner distribution function [MiN91].
4.4
Coherent vs. Sequential Tunneling and Inelastic Tunneling
The Esaki-Tsu model described earlier is based on a coherent tunneling model
which is analogous to the Fabry-Perot resonator. This model relies on calculating the
total transmission coefficient, T2 b(Ez) of the whole structure. In 1985, Luryi
proposed an alternative viewpoint that explains the NDR phenomena in DBRTDs
which has subsequently been termed "sequential tunneling" or "incoherent tunneling"
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53
[Lur85~\ . From this different perspective, Luryi proposed that NDR could occur
without the resonant Fabry-Perot analogy, but rather from considering a step by step
procedure in which the electron can first tunnel from the emitting electrode to the
quasi-bound state in the well and subsequently tunnel from the quasi-bound state to
the collecting electrode. Thus, this two-step process was given the name sequential
tunneling [Lur85]. In the interim, the electron can face many inelastic scattering
events which would cause it to lose its phase coherence [WeV87] [Kho90] . Viewing
the tunneling process of the DBRTD as sequential was quite appealing to many
\WeV87], [Kho90], [G0T88 ] because it allowed the inclusion of inelastic scattering
events and other interactions in the well rather than the somewhat idealistic view of
total elastic processes in the quantum well.
It was found that although the sequential tunneling model could incorporate
scattering events in the well, the calculated peak current densities were equivalent to
those calculated in the coherent tunneling model [Kho90],[[JoG90\. In addition, the
PVCRs determined from these models were still overpredicting those measured
experimentally. In fact, with the more advanced physically-based quantum transport
models, the issue of coherent tunneling or sequential tunneling is a moot point since
these more advanced models are based on a many body particle point of view and not
a single particle point of view [MU.91].
Nonresonant inelastic tunneling in AlAs/GaAs DBRTDs must be taken into
account Inelastic tunneling is named as such due to tunneling through the lower
TGaAs-XAiAs barrier due to various inelastic scattering events such as phonon
scattering, impurity scattering and interface roughness scattering as shown by
Mendez and co-workers who examined the effects of hydrostatic pressure on the DCIV characteristics of AlAs/GaAs DBRTDs at 77K [MeC88 \ . Through the hydrostatic
pressure studies and by using the valley current as a monitor for inelastic tunneling,
Mendez found that thicker ALAs barriers exhibit more inelastic tunneling whereas
thinner ALAs barriers (= 8ML) exhibit reduced inelastic tunneling. Intuitively, one
may expect inelastic tunneling since the rGaAs_rALAs discontinuity in the conduction
band is approximately 1.04 eV and the TcaAs-XMAs discontinuity is approximately
0.19 eV as shown in Figure 4.4. Similar results were found by Kyono and coworkers in which they studied the tunneling processes in AlAs/GaAs single barrier
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54
structures as a function of barrier thickness and temperature. They distinguished the
temperature dependent inelastic current processes from non-temperature dependent
elastic tunneling processes [KyK89] . In this study, it was determined that
perpendicular transport through a 5 ML ALAs single barrier was primarily iGaAsIaia s elastic tunneling dominated but in an 11 ML AlAs single barrier the current
transport began to show inelastic temperature dependent tunneling effects. The
question though is whether or not these inelastic tunneling effects exhibit themselves
at some point in between 5 ML and 11 ML. These inelastic tunneling effects in
AlAs/GaAs DBRTDs exhibit a temperature dependence and are a major cause of the
higher valley currents and the reduced PVCRs.
1.04 eV
x - T —
0.48 eV
r
—^ -----—
------------------
0.19 e\
X-point conduction band profile
F-point conduction band profile
Figure 4.4: Conduction band profiles of both the T-point and X-point minimums for
an AlAs/GaAs DBRTD. The offset values were taken from Liu \LiuB7 ].
4.5 The QWITT diode and the use of depleted spacer layers
The basic distinction between the QWITT diode and the DBRTD is the
addition of an undoped or lighdy doped GaAs layer downstream or on the collector
side of the AlAs/GaAs quantum well, as shown in Figure 4.5. Although the
influence of space charge effects on the DC-IV characteristics of DBRTDs has been
previously investigated [CaM87\, the importance of space charge resistance and its
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55
impact on the high frequency performance of resonant tunneling structures was made
apparent by Kesan, et al. {KeN87\ .
Electron energy
5000A
100k
100A
50A
17A
50A
17A
50A
2000A
4 x 10?8 cm~3
6 x 1017 cnr3
5 x 1016 cm'3
Undoped
Undoped
Undoped
Undoped
Undoped
S xlO 16 cm'3
^
GaAs
GaAs
GaAs
GaAs
AlAs
GaAs
AlAs
GaAs
GaAs
n+ GaAs substrate
Figure 4.5: Illustration depicting the cross-sectional layer structure and conduction
band profile of a typical AlAs/GaAs QWITT. (Not drawn to scale.)
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56
Since a significant part of the voltage is dropped across the depleted spacer layers, it
is found that the NDR region is pushed out to higher voltages and also broadened
along the voltage axis. As a result, the AV can be increased through the addition of a
lightly doped spacer layer after the quantum well. From equation 4.12, the r.f.
output power of such devices can be improved. The normalized injection
conductance, a, is an important parameter for small signal analysis and is defined as
follows [KeN88 ] :
f
dJqw
dV
V»J
I
where 1 is the length of the quantum well region, Jqw is the current density, Vqw is
the voltage across the quantum well, Eqw is the electric field across the quantum
well, and V0 is the dc bias voltage. From this injection conductance, the optimum
depleted spacer layer width, W, at a given frequency can be determined as well as the
specific negative resistance of the device. Unfortunately, extracting the J-E
characteristics from the measured DC-IV characteristics can be very difficult because
it requires an exact knowledge of parameters such as specific contact resistance of the
device being measured, the doping concentration in all the epi-layers, and the
thickness of all the epi-layers. Due to realities of MBE growth and fabrication, even
at their level of sophistication where layer thicknesses and doping concentrations are
now controlled very well, there is always some uncertainties in the parameters
mentioned above which may result in deviations in the extraction of parameters such
as the injection conductance of the quantum well. In addition, the Cinj. is highly
dependent on the quantum well structure and the related material system. The two
most important parameters for o are the AJ and the AV and the quantum well
structure should be designed accordingly and not be based just on an optimum peakto-valley current ratio (PVCR). A comparison of J-V characteristics between an
AlAs/GaAs DBRTD and AlAs/GaAs QWITT with the same quantum well structure is
shown in Figure 4.6.
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57
50
AlAslGaAs .
QWITT
o AlAslGaAs
o3 DBRTD
40
CSJ
§
30
3
I
^
Q
c
£
on
20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Voltage (V)
Figure 4.6: Measured J-V characteristics for an AlAs/GaAs DBRTD and an
AlAs/GaAs QWITT with the same quantum well structure. The quantum well
consists of 17A AlAs barriers, a 50A GaAs well and an CTjnj = 0.3 ( 1/D-cm).
Since it is not the purpose of this research to investigate the r.f. aspects of the
QWITT and the DBRTD, the reader shall be referred to the appropriate references
[KeN88 ]. A few points should be made for completeness about the basic premise
and usefulness of the QWITT structure. When the QWITT structure is biased into the
NDR regime, the electric fields in the drift region are typically in the 100 KV/cm2 to
300 KV/cm2 range and it is assumed that the electrons traverse the drift region at their
saturation velocity. In the majority of the calculations used in the analysis of these
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58
devices, the saturation velocity, vs, used is 6xl0 6 cm/sec. Once the optimum drift
region length has been found, combined with the injection conductance of the
quantum well, the r.f. characteristics of the device can be predicted. The two
frequency regimes under which the QWITT operation can be described are to > loi/e
and co < lal/e. The frequencies that our group has been able to work with have been
at co < lol/e and therefore the overall specific negative resistance of the QWITT can be
expressed as [KeN88 ]:
where W is the drift region length, e is the dielectric constant of the GaAs drift
region, and vs is the saturation velocity. The first term in the above expression
represents the space charge resistance associated with the quantum well injector
coupled to the drift region using the assumption of a constant saturated velocity and
the second term in the above expression represents the space charge resistance of the
depleted drift region which is always positive. Note here that it is important to design
the drift region length and doping concentration such that the drift region is almost
fully depleted when the QWITT is under bias; otherwise any undepleted drift region
will contribute a positive series resistance to the overall specific resistance of the
device. Typically one must also take into account the specific contact resistance of the
contacts if the specific contact resistance is much higher than 5x10‘6 Q-cm 2.
Therefore, in order to maximize the r.f. characteristics of the QWITT structure,
several important structural considerations must be taken into account such as the
depleted drift region length, the quantum well structural design for maximum
injection conductance, and minimization of contact resistances. The maximum
frequency at which an optimized QWITT can oscillate in a circuit is given by
[KeN88 ],
(4.11)
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59
where Rcont is the contact resistance, Rcircuit is the resistance of the external circuit,
and A is the device area. As well as being able to predict the maximum frequency at
which these devices can operate, it is also useful to approximate the maximum r.f.
power that these devices can deliver. From the tunnel diode literature [KiB61]
[StN61~\, the maximum r.f. output power is determined by treating the current as a
cubic polynomial of the voltage and is expressed as:
Prf = — A V x A I
16
(4.12)
Experimentally, it has been shown that equation 4.12 seems to underpredict the total
output power of some of the QWITT diodes and that the time averaged power, f*ac>
calculated using a quasi-static method appears to give better results [ReT90A\ . One
reason that the quasi-static power calculation may compare better with experimental
data is the fact that the voltage swing is not restricted to lie within the boundaries of
the peak and valley voltage and may extend outside these regions. The highest
oscillation frequency obtained so far on a DBRTD structure is 712 GHz in an
InAs/AlSb DBRTD mounted in rectangular waveguide resonator [BrS91]. Here it
should be noted that the injection conductance of the DBRTD in the InAs/AlSb is
much higher than the AlAs/GaAs system and therefor allows a higher cutoff
frequency.
4.6 Temperature Dependence of AlAs/GaAs DBRTDs and QWITTs
The impact of temperature on the DC-IV characteristics of AlAs/GaAs or
AlGaAs/GaAs DBRTDs has been examined experimentally with varying degrees of
agreement (H uI87] [VaL89] [ShX91'\ . It is well known that the quantum
interference effects observed in DBRTDs become more pronounced at low
temperatures as thermionic based current and inelastic tunneling mechanisms are
reduced. These mechanisms exhibit their influence primarily in the valley current
Thus, an obvious characteristic in the DC-IV characteristics of a DBRTD as the
temperature rises is a corresponding rise in the valley current Experimentally, other
research groups have observed the peak current to increase and decrease as the
temperature of the device is increased. These discrepancies may be due to the
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60
quantum well structures used in each study [HuI87\,[VaLS9\,\ShX91'\. The peak
voltages are observed to decrease slightly with increased temperature and the valley
voltages are observed to decrease to an even greater extent with increasing
temperature. The significant decrease in the valley voltage with temperature
corresponds to the increasing thermionic based currents that also occur with
temperature. In order to predict the peak current density at low temperature, one can
use the following expression from the Tsu-Esaki model which expresses Jp in the
limit as T approaches 0 K [TsE73]:
J =y
^
^
^
Ta (B ,)d E ,+ \l-v( E ,-E ,) r 1,(E ,)dE^
V < Ez (4.14)
Temperature dependent measurements have also been taken on the AlAs/GaAs
DBRTD and AlAs/GaAs QWITT structures fabricated by our group using a twoprobe MMR low-temperature probe station that allows one to take DC-IV
measurements of devices down to 77K. This low-temperature system utilizes a
refrigerator based on the Joule-Thompson effect and therefore the refrigerator itself
must be enclosed in vacuum as it is cooled down to 77K in order to avoid
condensation. The temperature is monitored with a silicon diode and the sample can
be heated with a resistance heater [MMR84] . The gas used in the Joule-Thompson
refrigerator is nitrogen which is fed into the refrigerator by a capillary at pressures
ranging from 1500 psi to 1800 psi. In actual practice, it was found that the system
could only be brought down to about 80K and held there for about 30 minutes before
the temperature would start rising. Another limitation that made it very difficult to
take many measurements on the DBRTDs was the fact that the microscope used for
viewing the device under vacuum through a viewport had limited magnification which
made it extremely difficult to see the 5pm to 15pm pads of our devices and to probe
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61
them repeatably. Nevertheless, a few measurements were taken to examine the
change in DC-IV characteristics at low temperatures, but no systematic study could be
attempted. In Figure 4.7, a plot of the valley current and the PVCR versus
temperature are given for an AlGaAs/GaAs DBRTD (No publications could be found
on the systematic variation of the temperature of AlAs/GaAs DBRTDs).
peak current
30
ptvr T
valley current
-200
— theory
• experiment
-100
100
Temperature
°C
Figure 4.7: Variation of valley current and PVCR versus temperature for
AlGaAs/GaAs DBRTDs. Taken from [VaL89].
4.7 MBE Growth of AlAs/GaAs DBRTDs and QWITTs
The first use of MBE to grow the layer structures for AlGaAs/GaAs DBRTDs
was first performed by Chang, Esaki, and Tsu in 1974 [ChE74]. Since that time,
improvements in material quality, materials characterization, and epitaxial growth
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62
techniques have led to continued improvements in the peak-to-valley current ratio
(PVCR), precise control over barrier and well thicknesses, and control over doping
profiles. The substrate preparation and system description for MBE growth in the
Varian Gen II have already been discussed in Chapter 2. In this section, the specifics
related to growth of the AlAs/GaAs DBRTDs will be discussed.
Specific to the MBE growth of DBRTDs is the accurate determination of the
AlAs and GaAs growth rates by RHEED. As will be discussed later in Chapter 5,
any variation in the barrier thickness of the DBRTD can result in dramatic changes in
the current density of the device as well as the Ginj.. In addition, any variation in the
quantum well width will result in different peak voltages. Therefore, in order to be
able to repeatably perform MBE growth of DBRTD structures, growth rates were
determined both before and after every MBE run. Especially as source material
begins to deplete in their respective effusion cells, the growth rates can fluctuate
significantly over a couple of hours.
The beam equivalent pressure of the As2 cracker is set to obtain the proper
As/Ga incorporation ratio of = 1.5-1.7 for a growth rate of 1 ML/sec.. The native
oxide is usually desorbed at raised substrate temperatures of = 660°C under an As
overpressure. For the device structures grown in this research, the AlAs growth rate
was typically kept at 0.25 ML/sec or 0.3 ML/sec and the GaAs growth rate for the
quantum well and all spacer layers was kept at 0.4 ML/sec. The GaAs growth rate
for all other layers outside of the quantum well and spacer layers was 1.0 ML/sec.
Typical growth temperatures were 600°C. CAR rotation is kept at 5 rpm during the
whole growth cycle. The quantum well consists of a 50A nominally undoped GaAs
quantum well surrounded by 17A AlAs barriers. The three-step spacer layers consist
of a 50A nominally undoped GaAs layer, a 100A GaAs layer n-type doped at 5 x
1016 cm*3, and a 100A GaAs layer n-type doped at 6 x 101 7 c n r3. The growth
interrupts at each interface inside or adjacent to the quantum well was 4 seconds. The
growth interruption during each change in Si doping setpoints usually required about
10 minutes for the Si effusion cell to stabilize. This structure is referred to as a
"baseline" structure since it is the most commonly used structure in our AlAs/GaAs
DBRTDs and QWITTs. A typical cross-section of a baseline AlAs/GaAs DBRTD
grown in this research is shown in Figure 4.8.
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63
5000A
100A
100A
50A
17A
50A
17A
50A
100A
100A
4 x 1018 cm'3
6 x 1017 cm'3
5 x 1016 cm'3
GaAs
GaAs
GaAs
Undoped
Undoped
Undoped
Undoped
Undoped
5 x 1016 cm'3
6 x 1017 cm'3
GaAs
AlAs
GaAs
AlAs
GaAs
GaAs
GaAs
5000A
4 x 1018 cmr3
GaAs
n+ GaAs substrate
-2 -4 x 1018 cm:3
Growth Interruption Schedule
--------- 600 seconds
600 seconds
--------4 seconds ■
fi |
---------4 seconds
I 2
--------4 seconds •
8 5--------4 seconds ■ R 3
--------4 seconds ■ a. a
5" &
--------4 seconds ■ * • 3
--------- 600seconds'
--------- 600 seconds
Temperature o f substrate
during growth is 600°C
Figure 4.8: Cross-sectional layer structure for a "baseline" AlAs/GaAs DBRTD and
the growth interrupts associated with the MBE growth of the device.
4.8 Formation of Ohmic Contacts and Fabrication Issues
The impact and influence of the specific contact resistivity, pc, on the d.c. and
r.f. performance of double barrier resonant tunneling diodes (DBRTDs) has been an
important area of concern of our group during the initial development of the QWITT
and DBRTD structures. The specific contact resistivity can be defined as:
_ dV
Pe l i / 1
(C l-cm 2)
(4.14)
Since the typical device sizes we work with are on the order of 100 pm2, we need a
fairly low specific contact resistivity to reduce the overall series resistance in the
device. There are many definitions for an ohmic contact such as: 1) that the I-V curve
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64
is linear through the origin 2) that the contacts are not injecting and 3) that the contact
resistance is small compared to the device resistance [PiG83]. High series resistance
effects can degrade the overall r.f. output power by a concurrent drop in the AV (Vp Vv), as seen in equation 4.12. In addition, the maximum oscillator frequency, fma»,
of the DBRTD is inversely proportional on the contact series resistance in the
structures as shown in Equation 4.11. The effects of a high pc can be seen by adding
its series resistance to the actual J-V characteristics of a standard AlAs/GaAs QWITT
diode. Values of 10Q, 20Q, and 30Q (lxlO*5 Cl-cm2 ,2 x l0 *5 £2-cm2 and 3xl0 *5 Cl­
em2, which can actually occur in a poor process) were added to the I-V characteristics
of an AlAs/GaAs QWITT diode, as shown in Figure 4.9.
0. 030
Increasing series resistance
causes Vp to move out
faster than Vv
0. 025
B Baseline
* 10 ohm s
O 20 ohm s
• 30 ohm s
0.020
2
|
0. 015
0.010
0. 005
0.000
0
1
2
3
4
Voltage (V)
Figure 4.9: Impact of series resistance on the I-V characteristics of an AlAs/GaAs
QWITT diode with additional series resistances of 10Q, 20£2 and 30Q added to the IV curves. Note that AV decreases with increasing series resistance.
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65
Two significant problems that plagued the r.f. performance of the QWITT and
DBRTD oscillators were high specific contact resistivity (£2-cm2) and poor contact
adhesion to the substrate. Various metallization schemes and surface preparations
were used to improve these two parameters. In this section, ohmic contacts to
GaAs, specific contact resistivity extraction issues, and fabrication related issues will
be discussed.
It is well known that in GaAs the Fermi level is pinned approximately 0.7-0.9
eV below the conduction band as result of interface state formation or the effective
workfunction of microscopic clusters of oxide/metal phases [WoF<5 / ] . Gold, for
example, has been observed to have a Schottky banier height of 0.88 eV on a 100 ntype GaAs surface [RkW88 ] . The source of these interface states have been heavily
investigated with many theories as to their origin and effect on ohmic contacts
[W0F8 I]. The result of Fermi level pinning in GaAs results in a Schottky barrier
when an unalloyed contact is formed on the GaAs. The two most common methods
to obtain an ohmic contact are to thin the barrier such that the electrons can tunnel
through the banier or lower the barrier such that the electrons can traverse the metal
semiconductor interface unimpeded. Thus, a way must be found to avoid thermionic
emission over this Schottky barrier and tunnel through the barrier either by thermionic
field emission or field emission. Thermionic field emission occurs when the carriers,
in our case electrons for metal-n+ contacts, acquire enough energy such that they can
tunnel through the top of the Schottky barrier. Field emission occurs when the
electrons can tunnel through the Schottky barrier which usually is very thin through
the use of a degenerately doped n+ GaAs layer. Both thermionic emission and
thermionic field emission are temperature dependent In fact for metals on heavily ntype doped GaAs material, the depletion region does not extend fully into the n+
doped layer, thus allowing electrons to tunnel through the barrier. In our actual
contacts, the specific contact resistivity was quite high when the contacts were
unannealed. Therefore we had what could be referred to as "poor" ohmic contacts
and/or "leaky" Schottky diodes. In order to improve the specific contact resistivity of
these "poor" ohmic contacts on heavily n-type doped GaAs layers, work has been
performed investigating surface preparation, metallization techniques, alloying
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66
recipes, and MBE growth conditions for some of the delta-doped and indium based
nonalloyed contacts. In addition, the contact resistance measurements and their
limitations will be discussed.
The two most common alloyed ohmic contact metallurgies to n+ GaAs are the
AuGe/Ni system and the PdGe system. Germanium is the preferred n-type dopant
over tin because it does not diffuse as fast in GaAs. The AuGe/Ni system was
originally developed in 1967 by Braslau, Gunn and Staples [BrG67\ and has been
investigated very heavily, even up to the present. The standard Au-Ge eutectic
specified is 8 8 % Au and 12% Ge by weight The use of Ni and its puipose have
changed since its initial use in such contacts. Several studies have investigated indepth the mechanisms that occur when the AuGe/Ni system is alloyed and variations
of the metallization scheme to achieve a lower specific contact resistivity [BrP87]
[KuB83] . The number of various metallization schemes or "recipes" that can be
cited in the literature is almost endless, thus indicating that there is not a set procedure
in making AuGe/Ni contacts [Oga80] [CaP85] [MuC86] . Instead the number of
recipes most likely can find their origin based on the type of surface preparation,
vacuum/evaporator setup and source material purity that was implemented. Many
factors must be taken into account when deciding upon the layers and layer
thicknesses to be used in a AuGe/Ni contact scheme such as ohmic contact adhesion,
equipment capabilities (two or three evaporation sources), specific contact resistivity,
sheet resistance of the final alloyed metallization, whether the contact metallization
will be patterned by lift off or by etching, and will the contact metallization be used as
an etch mask during mesa isolation.
The original contact metallization used on the AlAs/GaAs DBRTD and
QWITT structures consisted of approximately 800A-1000A of Au-1 2 % Ge and 200A
of Ni. A typical surface preparation before the evaporation consisted of the 2:1
HC 1:DI-H 2 0 etch for 30 seconds. The metal evaporation was performed in a
standard bell jar evaporator, named "Philvac", utilizing a rough pump, Varian
coldtrap and diffusion pump. Typical base pressures of SxlO^-SxlO*6 Toir were
achieved in this system. The alloying of these contacts was performed in a rapid
thermal annealer (RTA) at 450 *C for 30 seconds in forming gas. This contact
metallization resulted in poor contact adhesion in both the metallization lift off process
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67
and the metallization etch process that was used in fabricating our QWITT diodes and
DBRTDs. In addition, the metallization scheme used above resulted in poor and
highly unrepeatable specific contact resistivities in the range of 6x1c)-6 Si-cm2 - 5x105 Q-cm2. Possible causes of the poor quality of these contacts are oxygen
contamination of the Ge during thermal evaporation using alumina coated tungsten
boats [M0T88 ] , the high base pressure in our bell jar evaporator, or most likely poor
formation of a Ni2 GeAs alloy at the metal-semiconductor interface. With this specific
AuGe/Ni contact metallization scheme, it was apparent that consistent, repeatable
results were not able to be achieved. As stated, many different mechanisms have
been proposed during alloying of the AuGe/Ni contacts. Some of the mechanisms
that appear to be common among those proposed are [BrP87] [ChL91],and [KuB83]:
In the early stages of alloying (300 *C) the Ge and Ni diffuse to the contact interface.
Ga is found to accumulate where the Au is and As accumulates in the region where
the Ni is located. Thus two concurrent reactions have initially occurred: Au +
GaAs =>AuGa + As and Ni + As =» NiAs. The NiAs formation at the interface is
critical for the subsequent formation of the Ni2 CeAs phase which provides the ohmic
contact. In the later stages of alloying (400 *C), the temperature is well above the
AuGe eutectic temperature of 356 *C and continued movement of Ni and Ge to the
NiAs interface occurs. It is the formation of the Ni2 GeAs phase that apparently
provides the low specific contact resistivities. Thus the goal is to find the appropriate
metallization scheme that produces the Ni2 GeAs phase in large percentages at the
interface and reproducibly. The remaining Ni on the top helps prevent the Au from
balling up during the latter stages of the alloy cycle.
A new metallization scheme chosen to obtain improved specific contact
resistivities repeatably was = 15A Ni, 8 OOA-IOOOA AuGe and = 150A Ni. In the
metallization lift off process, which is currently used more often since it has two less
etch steps than the metallization etch process, a 2:1 HC1:DI-H2 0 etch is used as a
surface preparation to remove surface oxides. The first layer Ni is used to improve
contact adhesion [MuC86\ to the GaAs as well as aid in the formation of the Ni2 GeAs
phase. The top layer Ni, again, aids in the prevention of excessive Au balling during
the alloy. A typical SEM micrograph of the Ni/AuGe/Ni contact after alloy is shown
in Figure 4.10.
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00 13
25KV
Figure 4.10: SEM micrograph showing an alloyed Ni/AuGe/Ni ohmic contact
of a mesa isolated AlAs/GaAs DBRTD. This contact was made using a metal)
lift off process where AZ1350J-SF photoresist is used to define and lift
contact pattern. Note the metal flags at the edge of the metallization due to the
procedure.
With this metallization we observed lower specific contact resistivities in the r
7 x l0 7 Q-cm2 to 4xl0 ' 6 Q-cm2.
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69
The specific contact resistivities were determined through the use of CoxStrack test structures [CoS67] as shown in Figure 4.11.
►
n- GaAs epi-layer
n+ GaAs substrate
Indium Backside Ohmic Contact
Figuie4.il: Schematic drawing of Cox-Strack structures used to extract the
specific contact resistivity of the ohmic contact metallization
In this measurement scheme, specific contact resistivities are extracted with the ohmic
contacts on thin epitaxial layers of a certain doping concentration (resistivity). The
total measured resistance, Rt, of these structures can be broken up into various terms
as follows:
Rt = Rc + R . + R ^iO )
Rc = ^ T V
<f)
(4.15)
(Q)
(4-16)
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70
/r •
(Q)
(4.17)
where Rt is the total measured resistance, Rc is the contact resistance, Repi is the
spreading resistance through the epi-layer, Rext is the external resistances in the test
setup, pc is the specific contact resistivity, pepi is the resistivity of the epi-layer, and
tepi is the thickness of the epi-layer. The above resistance terms can be separated out
by measuring the total resistance of contacts of different diameters. Although these
test structures result in larger errors than other methods, the Cox-Strack structures
allow for quick and simple measurements and are based on perpendicular current
transport through the epi-film as is also done on our two-terminal DBRTD and
QWITT structures. The contact sizes that are measured in this technique must be as
small as possible in order to reduce the error that occurs in measuring larger contacts.
The typical contact diameters measured are 4pm, 6pm, 8pm, 10pm, 12pm and
14pm. To reduce error, the device area of every test structure is measured with an
HMOS optical measurement tool Since the doping concentration is known quite well
through C-V and Hail measurements, the resistivity can be determined from tables in
any text.
Although the Ni/AuGe/Ni metallization provided a low specific contact
resistivity and was repeatable, there were two problems with this metallization. The
first problem was related to the fact that the metallization did not act as a good etch
mask in the "lift off’ process when mesa etching our device structures with any
peroxide based etchant such as 8:1:1 H2S04:H20:H202- In fact, most of the etchants
used for mesa isolation of our diodes appeared to attack the top layer Ni. The second
problem is seen in the fact that the Ni/AuGe/Ni alloyed metallization has a fairly high
sheet resistance in the range of 2 D/square [Wil90). The sheet resistance of the
metallization is not negligible compared to the interfacial sheet resistance or the sheet
resistance of the degenerately doped GaAs semiconductor layer underneath the
metallization. Thus probing this type of metallization will result in irreproducible
results since there is a resistive drop across the pads. Since our tungsten probe tip
diameters are on the order of 0.6pm- 1.2pm, probing larger pads will result in larger
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71
ohmic resistance across the pad. This additional external series resistance on our
larger pads which range 20 pm to SO pm diameter resulted in reduced AVs in our
DBRTDs and QWITT structures. Therefore, although the Ni/AuGe/Ni metallization
provided a low specific contact resistivity it had a high sheet resistance which resulted
in series resistance losses in our DBRTDs with larger pads.
In order to circumvent the above mentioned problems, a 1000A layer of Au
was used to cap the standard Ni/AuGe/Ni metallization to reduce its sheet resistance.
The concern here was to make sure the Au cap layer did not degrade the specific
contact resistivity. Our results showed no degradation in pc when a Au cap layer was
used with similar conclusions stated by others [ChL91] [Wil90\. In addition, the Au
cap layer was ideal for an etch mask during mesa etching of our diodes.
Other types of ohmic contact schemes have been reported in the literature with
the In-based non-alloyed contacts and the PdGe contacts as the most prominent.
These metallizations have been looked at with respect to the processes used in
Epitaxial Lift Off, which has been described in Chapters 3 and 6 .
With the metallization pattern formed on top of the layer structures for the
AlAs/GaAs DBRTDs or QWITTs, they are subsequently mounted on glass cover
slips with clear glycophalate wax and mesa etched in 8:1:1 H2 S0 4 :H2 0 2 :H2 0 . The
cover slips protect the In backside ohmic contact metallization from the etchant. Etch
rates for all these peroxide based etches used are not tabulated in this work. It is
strongly suggested that etch calibration samples be made and used in combination
with an Alpha-step profilometer before committing a device sample to an etch. After
the mesas are etched to their desired depth, the samples are removed from the cover
slips and rinsed in acetone, ethanol, and DI-H2 O. The samples are finally alloyed at
450°C for 30 seconds in a rapid thermal annealer (RTA). The devices are tested using
a Keithley 230 programmable voltage source and a Keithley 195A digital multimeter
controlled by an IBM PC-AT. Once the raw I-V data has been collected, the contact
sizes of the devices under test are measured using an HMOS optical measurement
tool. Typical sizes range from 5 pm to 45 pm. To extract the parameters of interest
for the DBRTDs and QWITT diodes (PVCR, Vp, Jp, Vv, Jv. Ep, Ev, Oinj., etc.)
would require a significant amount of time. A program written by D.R. Miller has
been utilized to extract these parameters from the raw I-V data [Mil90\ .
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72
4.9 MBE Growth of AlAs/GaAs DBRTDs with AS2 and AS4
The growth of AlGaAs/GaAs heterostructures with either dimeric arsenic,
As2 , or tetramic arsenic, AS4 , has been studied in-depth. The use of As2 has gained
much interest due to the observations that GaAs growth with AS2 results in lower
deep level concentrations, lower recombination velocities at AlGaAs/GaAs interfaces,
improved surface morphologies during growth of AlGaAs [LeS86 ] and from a
practical point of view, can save up to twice as much of the elemental As source
during growth runs. However, there are also certain disadvantages of using As2 One of the possible problems that may occur when thermally cracking AS4 at high
temperatures is the generation of AsO. Furthermore, at these high temperatures (>
770°C), contamination and generation of defects may also occur. Typically in the
Varian Gen n, the arsenic cracker is set at temperatures of 570°C-670°C (setpoints of
10-12 on the PID controller) such that not all the AS4 is thermally cracked due to
observations that higher cracker settings can cause high AsO concentrations which
significantly degrade the RHEED intensity oscillations and photoluminescence (PL)
intensity [BIS91] . In a few occasions, the As2 cell has been depleted through heavy
use and the AS4 had to be used to grow certain layers before bringing the MBE
system up to air to re-load materials. In this section, an AlAs/GaAs DBRTD grown
with AS4 will be compared to a standard AlAs/GaAs DBRTD grown with partially
cracked AS4 at a cracker setting of = 670°C.
The layer structure, MBE growth, fabrication and device testing of the
DBRTDs in this section follows those procedures described in section 2.2, section
2.3, section 4.7 and section 4.8. Since the majority of the DBRTDs are grown with
the arsenic cracker, the main concern about growing with the AS4 cell is to make sure
that the above mentioned problems associated with AS4 do not degrade any
parameters of interest in the DC-IV characteristics. In table 4.1, specific DC-IV
parameters are given for a standard DBRTD grown with the As2 cell and the DBRTD
grown with the AS4 cell.
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73
DBRTD Structure
(Bias)
Peak
Voltage, V„
AV=Vp-Vv
Peak Current
Density, JD PVCR
DBRTD with As4
(Forward Bias)
DBRTD with As4
(Reverse Bias)
DBRTD with As2
(Forward Bias)
DBRTD with As2
(Reverse Bias)
0.76± 0.04
0.27 ± 0.03
48.8 ± 3.8
4.1 ± 0.1
-0.62 ± 0.03 -0.24 ± 0.02 -44.3 ± 3.5
4.5 ±0.1
0.71 ± 0.02
0.29 ± 0.01
52.2 ± 2.2
3.8 ± 0.2
-0.61 ±
-0.29 ± 0.01 -48.0 ± 2.1
4.4 ± 0.3
0 .0 2
Table 4.1: Table of specific DC-IV parameters for a standard AlAs/GaAs DBRTD
grown using the As2 cell and the AlAs/GaAs DBRTD using die AS4 cell. Note that
all die layer thicknesses including those in the quantum well are die same for both
devices, as shown in Figure 4.8.
From the data, it is seen that there is no significant difference between the two
devices. Although the deleterious effects mentioned above may exist in the samples
grown with AS4 , the AlAs/GaAs DBRTD devices do not appear to be sensitive to
these effects.
4.10 Growth, Fabrication, and Testing of Depletion-Edge Modulation
AlAs/GaAs QWITTS
The AlAs/GaAs QWITT structures, as described in section 4.5 and shown in
Figure 4.5, utilized lightly doped GaAs spacer layers downstream from the
AlAs/GaAs quantum well. In these devices, the depleted spacer layer length,W, was
not optimized since the specific injection conductance, a(V), is a function of voltage.
One way of optimizing the depleted spacer layer length as a function of voltage is to
alter the doping profile downstream from the AlAs/GaAs quantum well. Ideally, one
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74
would like to start depleting the spacer layer downstream from the quantum well at
the Vp and fully deplete the spacer layer downstream at the Vv. Therefore, one would
like to have an optimized W at every voltage bias. To accomplish this task, the spacer
layer doping profiles must be altered accordingly. In fact, to succeed in this endeavor
requires precise knowledge of the doping concentrations, a of the quantum well
based on a linear fit, layer thicknesses, and repeatable specific contact resistivities.
One way to prevent the electric fields from becoming too large before the DBRTD
reaches resonance is by inserting a doping spike between the quantum well and the
spacer layers [KeNSS]. Since the electric fields in this region are usually > 100
kV/cm, the doping spike can be used to reduce the fields and still maintain a
saturation velocity of = 6 x 106 cm/second. By adjusting the doping spike/depleted
spacer layer length and doping accordingly, reduced voltage drops across the device
can be obtained resulting in higher dc-to RF conversion efficiencies. Furthermore, if
the depleted spacer layer doping is decreased or left nominally undoped, the depleted
spacer length can be increased resulting in a larger AV and negative resistance. The
device structures which utilize this doping spike and a longer depleted spacer layer
length are referred to as depletion-£dge modulation QWITTs or DEM-QWTTTs.
Several structures have been designed through simulation involving the "baseline"
quantum well structure, a doping spike and 1 pm nominally undoped downstream
spacer layer. Simulations have also been used to design a structure where a
composite spacer layer/doping spike/spacer layer (1500A GaAs doped at 1 x 1 0 16cnr
3 ,100A GaAs doped at 5 x 1017 cm*3, and 1 pm GaAs doped at 1.5 x 1016 cm_3) is
placed downstream from a quantum well of lower O since the 1 pm depleted GaAs
spacer layer cannot support quantum wells that supply higher current density, (n > Nd
must be avoided to prevent large electric fields). The quantum well structure consists
of an 8 ML AlAs/ 18 ML GaAs / 6 ML ALAs layer structure grown by MBE, as
shown in Figure 4.12. The layer structure, MBE growth, fabrication and device
testing of the DEM-QWITT in this section follows those procedures described in
section 2.2, section 2.3, section 4.7 and section 4.8.
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75
5000A
100A
100A
50A
22.6A
50A
17A
50A
1500A
100A
4 x l0 18cmr3 n+GaAs
6 x 1017 cmr3 n GaAs
S x l& 6 cm-3 n-GaAs
Undoped
GaAs
Undoped
AlAs
Undoped
GaAs
Undoped
AlAs
Undoped
GaAs
1 x 1016cm:3 n-GaAs
5 x 1017 cmr3 n GaAs
10000A 15X1016cmr3 n GaAs
o
500A n+ AlAs release layer
5000A 4 x1b18 cmr3 n+GaAs
n+ GaAs substrate
Desired mode
o f operation for
this device structure
e~
▼
Temperature o f substrate
during growth ofAlAs release
layer is 640°C
Temperature o f substrate
during growth o f all
other layers is 600°C
Figure 4.12: Cross-sectional layer schematic for a spacer layer/doping spike/spacer
layer combination placed downstream (on the anode side) of an asymmetric
AlAs/GaAs/AlAs quantum well. The current density is therefore reduced in such a
structure, but the AV should be increased. The purpose of the AlAs release layer will
be discussed in Chapter 6 , section 6.3.
The results that were obtained from this device structure are shown in Figure
4.13 and Table 4.2. These results show the expected lower current densities and
larger AVs. The unexpected results were the large amount of hysteresis which was
observed in the device characteristics and the observation that many of the devices
tested would break down when biased much further than the valley voltage. This
hysteresis is due to significant series resistance that can occur from any undepleted
GaAs in the 1 iim spacer layer.
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76
20
--
15
I
g
10
0
10
5
15
Voltage (V)
Figure 4.13: J-V characteristics of an AlAs/GaAs DEM-QWITT with a spacer
layer/doping spike/spacer layer combination placed downstream (on the anode side)
of an asymmetric AlAs/GaAs/AlAs (8ML/18ML/6ML) quantum well. Note that two
measurements were taken as a result of the amount of hysteresis observed in the J-V
characteristics; one curve with the voltage swept upward and one curve with the
voltage swept downward. This hysteresis is a result of significant series resistance
from any undepleted GaAs in the 1 p.m spacer regions. Also note that the AV on
such a structure was about 4 V.
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77
Device Structure
Peak
Voltage, V„
AV=Vp-Vv
AlAs/GaAs
DEM-QWITT
(Forward Bias)
AlAs/GaAs
DEM-QWITT
(Reverse Bias)
1.0 ± 0.04
0 .2
-7.5 ± 0.41
-4.9 ± 0.35
±
0 .0 1
Peak Current
Density, Jp PVCR
21.4 ± 0.8
1.5 ± 0.1
-14.1 ± 1.2
2.6 ± 0.3
Table 4.2: Characteristic J-V data for the AlAs/GaAs DEM-QWITT with an
asymmetric quantum well and a spacer layer/doping spike/spacer layer combination
placed downstream from the quantum well
It should be noted that other structures similar to the one above were grown and
processed. The devices would breakdown before reaching the NDR regime. Thus,
in this set of experiments, the ideal J-V characteristics for an AlAs/GaAs DEMQWITT were not obtained as a probable result of not achieving the exact doping
profiles desired in the doping spike/spacer layer regions.
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Chapter 5
Intentional Barrier Asymmetries in AlAs/GaAs
Double Barrier Resonant Tunneling Diodes
5.1
Introduction
In recent years, there has been considerable work on improving the high
frequency [BrS91] and output power properties of double barrier resonant tunneling
diodes (DBRTDs) [.ReT90]. Corresponding models and simulations have helped to
direct device structure design as well as understanding some of the more fundamental
issues regarding current transport through these devices. Structural device
parameters such as quantum well, barrier, and spacer layer thicknesses significantly
impact the peak-to-valley current ratio (PVCR), the peak current density (Jp), the
difference between the peak voltage and the valley voltage (AV), and the difference
between the peak current density and the valley current density (AJ). Furthermore,
variations in the dopant profiles and the thickness of the spacer layers can also
significantly alter device characteristics.
Intentionally induced structural asymmetries have been proposed and studied
in AlAs/GaAs DBRTDs and AlGaAs/GaAs DBRTDs for a variety of reasons. Ricco
and Azbel proposed that under bias, the electric field destroyed the symmetry of two
symmetric barriers, and thus reduced the resonance in the device [RiA84\. To negate
the effects of the asymmetry caused under bias, it was suggested that die entry barrier
that the electron traverses first be made thinner with respect to the exit barrier that the
electron traverses last For purposes of examining issues of bistability and tunneling
processes in DBRTDs, barrier thickness asymmetries have been incorporated [A/£8S]
[G0 T8 S] [RoG90] . Typically these thick AlGaAs barriers were highly asymmetric
such that they differed in thickness by more than a couple of monolayers. Inducing
an asymmetry between the barrier heights of two AlGaAs barriers has been made
[ZaG88] .
In our nominally grown symmetric AlAs/GaAs structures, a slight asymmetry
is seen in the DC-IV characteristics where the PVCR is higher, the Vp is lower and Jp
lower in the reverse bias, which corresponds to the electron traveling through the top
AlAs barrier first, as shown in Figure 5.1.
78
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79
60000
40000
•«C
*O
*
iifonwdlias.____
20000
s:
Q
&
Higher J p, higher Vp
i nd low er J ’VCR
s
5 :
I
s
-20000
i, / m w r V [
-40000
-60000
- 1 .5
and high zr PVCR
in revers r Idas
-1.0
-0.5
0. 0
0.5
1.0
1.5
Voltage (V)
Figure 5.1: Measured J-V characteristics for a baseline, nominally symmetric
AlAs/GaAs DBRTD. Slight asymmetries in the J-V characteristics are observed
where the Jp is higher, the Vp is higher, and the PVCR is lower, all in the forward
bias mode (Forward bias here implies the electron traverses the bottom AlAs barrier
first.)
This asymmetry could not be fully explained fully using models which consider
interface roughness at the inverted (GaAs on AlAs) and normal (AlAs on GaAs)
interfaces [LiC88] . These models predict that when there is electron injection
through the bottom AlAs barrier first (the normal interface first), the PVCR is higher
than when there is election injection through the top AlAs barrier first (the inverted
interface). In the measurements taken in this research, the experimental results
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80
showed the exact opposite. Thus, there was some basis for believing that there was
some physical asymmetry in the device structure induced by MBE growth.
Specifically, the Vp and Jp in the above J-V curve seem to indicate a slightly thicker
top AlAs barrier. Therefore, an initial experiment was to find out how much
asymmetry existed in the baseline AlAs/GaAs DBRTDs by intentionally varying the
top AlAs barrier thickness. In this chapter, the impact of intentional small barrier
thickness asymmetries on the characteristics of AlAs/GaAs DBRTDs, where the
thickness of the asymmetric barrier is adjusted nominally in increments of a halfmonolayer based on growth rates using RHEED intensity oscillations will be
presented. Comparisons with simulations will also be presented. In addition, a
DBRTD structure which utilizes a composite AlGaAs/ALAs "chair" barrier that was
grown, processed and tested by this author will be presented. This device structure
addresses the issues concerning inelastic tunneling and improved PVCRs.
5.2
Half-monolayer scale barrier asymmetries in AlAs/GaAs DBRTDs
The basic surface preparation of the substrate, MBE growth, and fabrication
of the devices in this set of experiments follows the discussion presented in Chapter
4. Specific to this experiment, though, were the half-monolayer growths. Here the
top AlAs barrier thickness was intentionally varied on the order of a half-monolayer,
based on growth rates as determined from RHEED intensity oscillations. Growth
rate calibrations were performed immediately before and after growth of the actual
devices. The AlAs growth rates were 0.25 ML/sec or 0.30 ML/sec, while the growth
rate for the GaAs spacer layers and GaAs well was 0.4 ML/sec. On six different
samples, the bottom AlAs barrier and GaAs quantum well growth times were set to
produce nominal layer thicknesses of 6ML and 18ML, while the top AlAs barrier
growth time was adjusted to produce nominal layer thicknesses of 5, 5.5, 6, 6.5,7,
and 8 monolayers, (MBE Runs# 1021, 1525, 1523, 1526, 1020, and 1524, see
appendix 1 for all J-V data), respectively. On one sample, the top AlAs barrier and
the GaAs quantum well had nominal layer thicknesses of 6ML and 18ML
respectively, while the bottom AlAs barrier thickness was increased to 7ML. See
Figure 5.2 for a cross-sectional diagram of the device structures grown by MBE.
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81
Reverse
Bias
e~
▼
e~
Forward
Bias
5000A
100A
100A
50A
T
50A
17A
50A
100A
100A
4 x 1018 cmr3 n+ GaAs
6 x 1017 cm’3 n GaAs
5 x 1016 cm’3 n~ GaAs
Undoped
GaAs
Undoped Top AlAs
Undoped
GaAs
Undoped Bottom AlAs
Undoped
GaAs
5 x l( fl6 cm’3 n-GaAs
6 x 1017 cm'3 n GaAs
5000A
4 x 1018cmr3 n+GaAs
n+ GaAs substrate
=2-4 x 1018 cmr3
Growth Interruption
Schedule
600 seconds
600 seconds
4 seconds
|
4 seconds
s iT
4 seconds
£ *
o ^
4 seconds
S g
§3
4 seconds
4 seconds
600 seconds
600 seconds
Growth rates are
monitored before
and after every
MBE run.
Figure 5.2: Illustration showing the cross-sectional layer structure of the AlAs/GaAs
DBRTDs used to examine the impact of intentional barrier thickness asymmetries on
the DC-IV characteristics. Note reverse bias implies electron injection through the
top AlAs barrier first, whereas forward bias implies electron injection through the
bottom AlAs barrier first. The top AlAs barrier thickness, T, was altered to produce
nominal layer thicknesses of 5.0, 5.5, 6.0, 6.5,7.0, and 8.0 ML.
After growth, all DBRTD structures were processed in the same fashion as described
in Chapter 4. Briefly, before metallization, the photolithographically pre-pattemed
material was etched in a 2:1 HC1:H2 0 solution in order to remove surface oxides and
to improve ohmic contact adhesion. An array of 5|J.m to 45 p.m diameter
Ni/AuGe/Ni/Au frontside contacts were defined using the lift off. Using the
frontside contacts as an etch mask, the device structures were mesa isolated using an
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82
8:1 :i H2SC>4:H202:H20 etch. Finally, the device structures were annealed at 450°C
for 30 sec.
Experimental and simulation results are summarized in Figures 5.3 and 5.4.
In the simulations, an AlAs effective mass of 0.11 me in the SchrodingerDrift/diffusion and 0.09me in the Schiddinger-Poisson models provided the best fit to
the experiments. Since these devices were measured at room temperature, it is
unreasonable to expect that these simple models take into account all the mechanisms
which affect the J-V characteristics. Ideally, low temperature measurements should
be made when extracting a fitted AlAs effective mass [LaA92]. These experimental
results were compared to simulations not to obtain close fits by using the AlAs
effective mass as a fitting parameter, but to observe how much the J-V characteristics
changed when varying the AlAs barrier thickness and by using a fitted AlAs effective
mass that is within reason compared to the literature [LaA92] . The change from the
band edge value of 0.15me to 0.09me has been attributed to strong renormalization of
the r electron effective mass in the AlAs [.Brde90] . Figures 5.3 and 5.4 show that
for biases ("reverse" bias) such that electrons are incident on the top AlAs barrier
first, the peak current density drops dramatically as this width is varied from 5 to 8
monolayers. For electron injection through the fixed-thickness bottom barrier first
("forward" bias), the variation is significantly less. Figure 5.5 shows similar
behavior for the peak voltage in forward and reverse bias. Both the simulation and
experimental results show that thickness variations in the entry barrier have a much
larger impact on DC-IV characteristics than thickness variations in the exit barrier.
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83
100
80 -
s
Q
«■*
60*
o g
40-
CCM
r
^
■
20*
4.5
5.0
5.5 6.0
6.5
7.0 7.5
8.0
8.5
Top AlAs Barrier Thickness
Figure 5.3: Peak current density vs. top AlAs barrier thickness for both simulation
and experimental results.
-)• Electron injection through variable thickness
top AlAs barrier first; (- - O - ): Simulation results (from S ch rd d in g erDrift/diffusion) for electron injection through variable thickness top AlAs barrier
first; (-----■— ): Electron injection through 6ML bottom AlAs barrier first; (--- □—
): Simulation results for electron injection through 6 ML bottom AlAs barrier first.
An AlAs effective mass of 0.11 mo was used in the simulations. One-sigma error
bars are included for experimental data. The simulations shown here were run on a
device simulator written by D.R. Miller.
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84
80
60-
5
40-
s
20-
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
Top AlAs Barrier Thickness (ML)
Figure 5.4: Peak current density vs. top AlAs barrier thickness for both simulation
and experimental results. (* * # - -): Electron injection through variable thickness
top AlAs barrier first; (- - O - ~): Simulation results (from Schrodinger-Poisson)
for electron injection through variable thickness top AlAs barrier first; (----■— ):
Electron injection through 6ML bottom AlAs barrier first; (---- □— ): Simulation
results for electron injection through 6 ML bottom AlAs barrier first An AlAs
effective mass of 0.09mo was used in the simulations. One-sigma error bars are
included for experimental data. The simulations shown here were run on a device
simulator written by K.K. Gullapalli.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
85
o.»
0. 8-
o
0.7-
05
CO
o
>
JSC
CO
a>
~©
o.e0.5-
a.
0.34.5
5.5
6.5
7.5
8 JS
Top AlAs Barrier Thickness (ML)
Figure 5.5: Peak voltage vs. top AlAs barrier thickness for both simulation and
experimental results.
-): Electron injection through variable thickness top
AlAs barrier first; (- - O - -): Simulation results (from S c h ro d in g e rDrift/diffusion) for electron injection through variable thickness top AlAs barrier
first; (-----■— ): Electron injection through 6ML bottom AlAs barrier first; (--- □—
): Simulation results for electron injection through 6 ML bottom AlAs barrier first.
One-sigma error bars are included for experimental data. The simulations were run
on a device simulator written by D.R. Miller.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
86
=as 5~
>s
o
V•
(S
©
Q.
c©
£
3
O
4.5
5.5
6.5
7J5
8.5
Top AlAs Barrier Thickness (ML)
Figure 5.6: Peak to valley current ratio vs. top AlAs barrier thickness for
experimental results. ( O— ): Election injection through variable thickness top
AlAs barrier first;
- -): Electron injection through 6ML bottom AlAs barrier
first One-sigma error bars are included for this experimental data.
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87
3-
4
5
6
7
8
9
Top AlAs Barrier Thickness (ML)
Figure 5.7: Ratio of the forward and reverse bias DC-IV parameters versus the top
AlAs barrier thickness. This graph displays the asymmetry in DC-IV parameters as
top AlAs barrier thickness is varied. The device with a 5.5 ML top AlAs barrier is
shown to be most symmetric. (---- □— ): Ratio of the forward and reverse bias
peak current densities, Jpf/Jpr. (— ■— ): Ratio of the forward and reverse bias
valley current densities, Jvf/Jvr- (— O— )•' Ratio of the forward and reverse peakto-valley ratios, PVCRf/PVCRr. (— &— ): Ratio of the forward and reverse bias
peak voltages, Vpf/Vpr.
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88
Figure 5.6 shows that structural asymmetries also have a significant impact on
peak-to-valley current ratio. Significantly higher PVCRs were observed when the
electrons passed through the thicker barrier first, regardless of whether the thicker
banier is on the top or bottom of the GaAs well. As the top AlAs barrier thickness
was varied from 5 ML to 7ML, an increase in the PVCR in the reverse bias case
(electron injection through the top AlAs first) was seen. This trend did not continue,
however, as the top AlAs barrier thickness was increased to 8ML. It is believed that
as the thickness increased from 7ML to 8ML inelastic TcaAs-XAiAs tunneling effects
may become significant, which tends to degrade the PVCR. Note that the trends
observed here only apply to the devices with the exact same doping profiles and
spacer layer thicknesses. The 7/18/6 monolayer AlAs/GaAs DBRTD demonstrated a
PVCR of 5.6 in reverse bias, which is the highest reported to date in the literature for
a simple AlAs/GaAs DBRTD. As stated previously in Chapter 4, for high frequency,
high r.f. output power oscillators, the PVCR is not as important as AJ and AV, but
the high PVCR is indicative of the maximum possible quantum interference effects
that can occur using this specific material system. It is from this point of view that
the high PVCRs are noteworthy. See appendix 1 for a summary of all J-V data.
The amount of DC-IV asymmetry in each of the devices is summarized by
taking the ratios of the forward and reverse bias data, as shown in Figure 5.7.
Interestingly, the device that exhibited the most symmetric characteristics was not the
nominally 6/18/6 monolayer DBRTD, but rather the 5.5/18/6 monolayer DBRTD.
This indicates that there may be an MBE growth asymmetry of unknown origin
which causes the AlAs barrier grown after the GaAs quantum well to be
approximately half a monolayer thicker than the barrier grown before the well.
Furthermore, a sample was run where the bottom AlAs barrier thickness was
varied while the top AlAs barrier thickness was held constant at 6 ML (MBE Run#
1120, See Appendix 1). The bottom AlAs barrier thickness was 7 ML, giving a
6/18/7 structure. From the DC-IV measurements on this device, it is seen that Jp is
now higher in the reverse bias mode and the Vp and PVCR are higher in the forward
bias mode. These results follow the trends of the six samples described above.
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89
5.3
Asymmetric Barriers Utilizing AlGaAs/AlAs/GaAs "Chair"
Barriers
Inelastic tunneling through a T-X discontinuity, described in section 4.4 of
Chapter 4, significantly contributes to the valley current in AlAs/GaAs DBRTDs
which one may expect since the roaAs'^AlAs offset is 1.04 eV and the TGaAs-^AlAs
offset is 0.19 eV. Furthermore, the inelastic tunneling is more predominate in the
valley where the electrons have more energy. Thus, one way to achieve improved
PVCRs is to reduce to the inelastic tunneling in the AlAs/GaAs DBRTD.
The AlGaAs/ALAs "chair" barrier was conceived of by Cheng and co-workers
as a way to reduce inelastic tunneling and obtain improved PVCRs in AlAs/GaAs
DBRTDs [ChH90] . In this structure, a four monolayer Alo.14 Gao.8 6 As layer was
placed adjacent to the bottom outer edge of an 7 ML/18 ML/7 ML AlAs/GaAs/AlAs
quantum well structure. If the device structure is biased such that the electron
traverses the "chair" barrier first, then a lower peak current density, Jp, would be
expected. In addition, when the device is biased at Vv, the valley voltage, the "chair"
barrier acts to reduce coherent tunneling through the EGaAs-CAlAs discontinuity since
the "effective" barrier that the electron must tunnel is now thicker with the "chair"
barrier and also acts to reduce the inelastic tunneling through the T GaAs*XAlAs
discontinuity. This reduced inelastic tunneling can be anticipated since the TcaAs*
XAlGao.i4Aso.86 discontinuity (0.42eV) is much higher than the T GaAs-XAlAs
discontinuity (0.19eV).
Since implementation of the "chair" barrier reduces the peak current density,
an AlGaAs/AlAs/GaAs "chair" barrier DBRTD was grown with slightly thinner
barriers than those chosen by Cheng, et.al.. This device structure utilizes a 4 ML
Alo.2 0 Gao.8 0 As "chair" adjacent to 6 ML/18 ML/6 ML AlAs/GaAs/AlAs quantum
well structure, similar to the "baseline" DBRTDs used in this study. See Figure 5.8
for a cross-sectional layer schematic of this structure.
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90
Reverse
Bias
▼
4
5000A
100A
100A
50A
lU A
17A
50A
17A
50A
100A
100A
11000A
Forward
Bias
Growth Interruption
Schedule
4 x K fi8 cmr3 n+ GaAs
^ — 600 seconds
6 x 10A7 cm~3 n GaAs
^ — 600 seconds
5 x ICA6 cm’3 n- GaAs
^
4 seconds
Undoped
GaAs
^
4 seconds
Undoped Al02Ga0.8As
^
4 seconds
Undoped
AlAs
^
4 seconds
GaAs
Undoped
^
4 seconds
Undoped
AlAs
^
4 seconds
Undoped
GaAs
^
4 seconds
5 x 1016 cm'3 n- GaAs
^ 600 seconds
6 x 10A7 cmr3 n GaAs
^ 600 seconds
4 x 1018 cmr3 n+ GaAs
n+ GaAs substrate
-2 -4 x 1018 cmr3
L
a *sS 5
I! »
©2
S 0
I*
55"
a.
Substrate temperature
during MBE growth
is 600°C
Figure 5.8: Cross-sectional diagram of the Alo.2 0 Gao.8 0 As/AlAs/GaAs "chair"
barrier DBRTD used in this study. The Alo.2 Gao.8 As "chair" was placed on the top
AlAs barrier based on the higher PVCRs obtained when the "baseline" DBRTDs
were reverse biased. Note that minor corrections have been made in the doping
profiles and layer thicknesses in this cross-sectional diagram.
The conduction band profile for the Alo.2 0 Gao.soAs/ALAs/GaAs "chair" barrier
DBRTD is given in Figure 5.9.
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91
1.04 eV
0.48 eV
A 0.19 e\
rG
aAs
0424 eV with respect to rG
aAs
r Alo2Gao.8As = 016 6 eV with ™ pect to
~x Alo2Gao.8As
=
X-point conduction band profile
------------------
F-point conduction band profile
Figure 5.9: Conduction band profiles of both the T-point and the X-point minimums
for the Alo.20 Gao.8 0 As/AlAs/GaAs "chair" barrier DBRTD. All energies shown are
in reference to the T-point of GaAs. The offset values for GaAs/AlAs are from Liu
[Liu87] and Alo.2 Gao.8 As/GaAs from Adachi [ Ada85].
Note that from the earlier discussion in section 5.2, it was decided to grow the
"chair" barrier on top of the quantum well since higher PVCRs were normally
observed when the electrons moved through the top AlAs barrier first The MBE
growth, fabrication, and DC-IV testing for this "chair" barrier DBRTD were
performed by A.J. Tsao [ReT90B] using the methods as described earlier in Chapter
4. The results obtained by this author are shown in comparison to a "baseline”
AlAs/GaAs DBRTD in Table 5.1. From the DC-IV measurements, an average
PVCR in the reverse bias mode (reverse bias implies electrons traversing the "chair"
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92
barrier first) for the "chair" barrier DBRTD of 6.0 ±0.1 was obtained with a high of
6.3.
Baseline AlAs/GaAs
DBRTD.
Highest Peak to
Valley Current
Ratio
Average Values
Peak to Valley
Current Ratio
Peak Voltage V„ (V)
AV(V)
Peak Current
Density Jp
(kA/cm2)
Valley Current
Density, Jv (kA/cm2)
AJ (kA/cm2)
AlAs/GaAs DBRTD
with Alo.2 Gao.8As
Chair Barrier.
3.9 (Reverse Bias)
6 3 (Reverse Bias)
Reverse Bias Forward
Bias
3.4 ± 0.2
3.7 ± 0.2
Reverse Bias Forward
Bias
6.0 ± 0.13
T 4 ± 0 .l5
0.93 ± 0.02
0.53 ± 0.03
0.98 ± 0.03 0.47 ± 0.02
0.33 ± 0.05 0.30 ± 0.02
52.4 ± 4.1
53.2 ± 4.2
31.3 ± 4.1
44.9 ± 5.3
14.4 ± 1.3
38.0 ± 3.2
15.8 ± 1.2
37.4 ± 3.5
5.2 ± 0.6
26.1 ± 4.7
13.3 ± 1.4
31.6 ± 6.7
0.72 ± 0.02
0.33 ± 0.03
Table 1: Comparison of J-V data for a "baseline" AlAs/GaAs DBRTD and the
AlGaAs/AlAs/GaAs "chair" barrier DBRTD. Note that the "chair" barrier DBRTD
obtained a PVCR of 6.3 at room temperature, which remains the highest PVCR to
date for an AlGaAs/GaAs DBRTD. Both of the above devices were grown by MBE,
processed, and DC-IV tested by A J . Tsao.
This PVCR of 6.3 remains the highest PVCR obtained at room temperature for an
AlGaAs/GaAs DBRTD. Furthermore, with the 6 ML AlAs barriers used in this
study, as opposed to the 7 ML AlAs barriers used by Cheng, et.al., higher current
densities were realized making this device more useful in possible oscillator
applications. A comparison between the J-V characteristics of a "baseline" DBRTD
and the "chair" barrier DBRTD is shown in Figure 5.10.
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93
40
20
S
u
2
•20
ChairI carter
DBITD
•40
-60
-1 .5
Symmeti ic baselim
DB, ITD
-
1.0
-0.5
0.0
0.5
1.0
1.5
Voltage (V)
Figure 5.10: Measured J-V curves for a standard "baseline" AlAs/GaAs DBRTD and
the AlGaAs/AlAs/GaAs "chair” barrier DBRTD, taken by this author. Note that in
the reverse bias mode, the "chair” barrier DBRTD has a slightly smaller Jp than the
standard DBRTD.
5.4 Use of an AlGaAs/AlAs/GaAs "Chair" Barrier in a QWITT Diode
As a result of the high peak-to-valley current ratios (PVCRs) obtained on the
chair barrier DBRTD, mentioned earlier in section 5.3, an attempt was made to
implement a similar type structure in an AlAs/GaAs QWITT. For this type of device
to be useful, though, the AJ must be high, regardless of the PVCR. In other words,
if the PVCR is improved but the current density of the device goes down, as
observed in the "chair" barrier DBRTD in section 5.3, then there are no real gains in
terms of using this device in an oscillator type application. Thus, in this study, the
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94
"chair" barrier itself was altered in an attempt to retain the beneficial features of this
composite barrier while increasing the current density of the device. To obtain this
increase in current density, the AlAs portion of this composite barrier was made
thinner by one monolayer (2.83A), from =17A down to =14.2A. In addition, the
Alo.3 Gao.7 As portion of the composite barrier was also made thinner by one
monolayer, from =11.3A to = 8.5A. From section 5.2, it is obvious that a one
monolayer thinner barrier will result in a significant increase in the current density of
the device, especially when the electron enters the thinner barrier first The crosssectional diagram of this device is shown in Figure 5.11.
Reverse
Bias
Forward
Bias
5000A
100A
100A
50A
8JA
142A
50k
17k
50A
4 x 1018 cm'3 n+ GaAs
6 x 1017 cm'3 n GaAs
S x l0 k 6 cmr3 n-GaAs
Undoped
GaAs
Undoped ^ 0 3 ^ 0 .7 ^
Undoped
AlAs
Undoped
GaAs
Undoped
AlAs
Undoped
GaAs
2000A
5x1016 cmr3 n-GaAs
20000A
4 x 1018 cmr3 n+ GaAs
n+ AlAs release layer
n+ GaAs substrate
-2 -4 xlO 18 cmr8
Growth Interruption
Schedule
^ — 600 seconds
^ — 600 seconds
^ — 4 seconds
^ — 4 seconds
^ — 4 seconds
^
4 seconds
^ — 4 seconds
^ — 4 seconds
^ " 4 seconds
^
^
^
^
^
^
^
^
^
<L
s S'
II
5 »
Si.
600 seconds
Temperature o f substrate
iring growth o f AlAs releai
layer is 640°C
during growth o f all
other layers is 600°C
Figure 5.11: Cross-sectional diagram of the Alo.3 0 Gao.7 0 As/AlAs/GaAs "chair"
barrier QWITT discussed in this section. Here both the AlAs and Alo.3 Gao.7 As
portions of the chair barrier were thinned by one monolayer to examine the impact on
the measured Jp and PVCR.
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95
The purpose of the AlAs release layer shown in Figure 5.11 will be explained in
Chapter 6, section 6.3. It has minimal impact on the measurements to be described.
The important J-V characteristics measured from this device are summarized in table
5.2.
Device Structure
Chair Barrier
QWITT
(Forward Bias)
Chair Barrier
QWITT
(Reverse Bias)
Peak
Voltage, Vp
(V)
AV=Vp-Vv
(V)
Peak Current
Density, Jp
PVCR
(kA/cm2)
0.61 ± 0.07
0.36 ± 0.05
46.8 ± 1.5
-2.71 ± 0.1
-0.98 ± 0.09 -64.4 ± 1.9
3.0 ±0.1
3.8 ± 0.2
|
Table 5.2: Characteristic J-V data for a "chair" barrier QWITT structure.
From the above characteristics, the current densities are significantly higher than the
baseline AlAs/GaAs QWITTs, described in Chapter 4, section 4.5. In addition, the
AJ for this structure, in the reverse bias mode or "QWITT" mode, was = 47 kA/cm2
which is higher than typical AJSof = 30 kA/cm2 for the baseline AlAs/GaAs QWITT.
The peak voltages, Vps, of this device in the QWITT mode are slightly higher than
those of the baseline structures. In this study, the chair barrier helped maintain a
reasonably high PVCR and AJ as both components of the chair barrier were thinned
by one monolayer.
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Chapter 6
Application of the ELO Technique to
Microwave and Photonic Devices
6.1
Introduction
The epitaxial lift gff (ELO) method, already discussed in Chapter 3, has been
shown to be an important processing technique that has allowed manipulation of
extremely thin epitaxial films. It has also allowed the hybrid integration of devices
from different material systems on a common alternative substrate. Hybrid
integration with transparent substrates allows optical contact to the back of the device
which is usually not accessible with common substrate thinning methods such as
back-lapping. Hybrid integration with alternative substrates with higher thermal
conductivity is useful for devices with high power dissipation. Furthermore, hybrid
integration with Si substrates opens up the opportunity to integrate high quality,
unstrained AlGaAs/GaAs devices with Si devices.
In this chapter, work will be presented on AlxGai-xAs/GaAs heterostructure
devices that have been separated from their GaAs substrates and bonded to alternative
substrates. DC-IV characteristics will be taken on AlAs/GaAs double barrier resonant
tunneling diodes (DBRTDs) and quantum well injection transit (QWITT) diodes both
before and after ELO. Furthermore, a discussion of the specific contact resistivity of
the ohmic contacts formed on the backside of the ELO layers will be presented. The
benefits of bonding various devices to transparent substrates will also be presented.
These devices include an optically controlled coplanar waveguide structure and
double heterostructure and multi-quantum well type light emitting diodes (LEDs).
6.2 Epitaxial Lift Off of AlAs/GaAs DBRTDs and Integration with
Alternative Substrates using In-based Bonds
As discussed in Chapters 4 and 5, the AlAs/GaAs DBRTDs and QWITTs that
have been grown, fabricated and tested in this research exhibit very high current
densities that typically range from 20 kA/cm2 to 100 kA/cm2. With these high current
densities, one can expect that the "junction" temperatures of these devices reach fairly
high temperatures. These high temperatures can increase inelastic tunneling,
96
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97
especially in AlAs/GaAs devices, and other thermionic based components of the
overall current already discussed in Chapters 4 and 5. Increased inelastic tunneling
contributes to a rise in the valley current and a reduction in the peak-to-valley current
ratio (PVCR) of DBRTDs and QWITTs. Experimentally, the valley currents and
PVCRs of AlGaAs/GaAs DBRTDs have been monitored as a function of
temperature[//u/S7] [VaL89\ [ShX91'\. Currently, there are no models which can
accurately predict the overall characteristics of a DBRTD. The mechanisms which
occur in the NDR region and into the valley are specifically not well understood at
this time. In Chapter 5, an AlGaAs/AlAs chair barrier was utilized to reduce the
valley current and increase the PVCR. In this section, through the use of ELO, the
effects of placing the high current density AlAs/GaAs DBRTD and QWITT on
alternative substrates of higher and lower thermal conductivity are examined.
Without going through the thermal model, at least it is intuitive that the "junction" or
in this case, the quantum well should be placed as close to a substrate of higher
thermal conductivity as possible. With this goal in mind, ELO is an ideal tool for
placing the "junction" of a device very close to an alternative substrate. Furthermore,
a simple thermal model is used as a guide.
The first AlAs/GaAs DBRTD that has been lifted off its GaAs substrate was
bonded to an In/AuCr coated glass slide. Since the two-terminal device structures
that are fabricated in this process are not planarized, the n+ GaAs substrate is
normally used as the second terminal, as shown in Figure 3.2. This first ELO
AlAs/GaAs DBRTD was actually grown on a semi-insulating substrate and therefore
could not be tested before ELO. A typical cross-sectional diagram of this device is
shown in Figure 6.1. Since this sample could not be tested before ELO, the DC-IV
characteristics of this device will be compared to DBRTDs with the exact same layer
structures as this sample.
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98
Reverse 5000A
Bias 100A
100A
50A
17A
50A
17A
50A
100A
100A
4 x 1018 cm~3
6X1017 cmr3
5X 1016 cmr3
Undoped
Undoped
Undoped
Undoped
Undoped
5 x 1016 cm'3
6 x 1017 cm'3
n+ GaAs
n GaAs
n-GaAs
GaAs
AlAs
GaAs
AlAs
GaAs
n-GaAs
nGaAs
soooA
4 x 1018 cmr3 n+ GaAs
1000A undoped AlAs release layer
Forward
Bias
Semi-insulating GaAs substrate
Growth Interruption Schedule
600 seconds
600 seconds ■
4 seconds •Ig - 5S"
g
4 seconds■
3 £
4 seconds•
§ 2
|L a
4 seconds•
4 seconds ■
a.
4 seconds•
600 seconds600 seconds
Temperature o f substrate
during growth o f AlAs release
layer is 640°C
Temperature o f substrate
daring growth o f all
other layers is 600°C
Figure 6.1: Cross-sectional diagram of the layer structure for the first ELO
AlAs/GaAs DBRTD (MBE Run# 1043) grown in this study. Note that this sample
was grown on a semi-insulating substrate and therefore could not be tested before
ELO. Subsequent DBRTDs (MBE Run#1376) and QWITTs (MBE Runs# 1437 and
2028) were grown on n+ GaAs substrates with heavily n+ doped AlAs release layers.
The topside ohmic contact metallization was evaporated onto the pre-pattemed sample
using the fabrication procedures in Chapter 4, section 4.8. The sample was then
mesa isolated, making sure that the mesa isolation etch did not penetrate the 5000A
n+ GaAs layer just above the AlAs release layer. The mesa etch used was a 8:1:1
H2 S0 4 :H2 0 2 :H2 0 etchant. The ohmic contacts are then annealed at 450°C for 30
seconds. After complete processing, the samples were prepared for ELO as
described previously in Chapter 3. As shown in Figures 3.3 and 3.4, since the
quantum well of these DBRTDs also contain AlAs layers, it is very important to
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99
protect them by ensuring complete coverage of the edge of the mesas with the
Apiezon W black wax. After the ELO DBRTDs have lifted-off from the GaAs
substrate, they were transferred onto an In/Au/Cr coated glass slide. The top indium
metallization on the slide was 2000A thick. The samples, still wet from a DI-H2 O
rinse, were then placed on the metallized slide. The DBRTD/slide combination was
placed overnight in a vacuum bag, which provides about 105 Pa (15 lb/in2) of
uniform pressure to the top of the sample. Afterwards the samples were baked in an
oven at 90°C to remove any moisture and to obtain better adherence to the indium
metallized slide. Subsequently, the lift off device was placed on a hot plate at 100°C
to obtain direct heating of the back of the glass slide. Slight deformation of the black
wax carrier did occur which resulted in a few cracks in the ELO film. After cooling,
the Apiezon W wax was removed with trichloroethane (TCA), with the ELO
DBRTDs remaining on the In/Au/Cr glass slide. The ELO DBRTDs were then
annealed at 350°C for 150 seconds in order to form an alloyed In/GaAs ohmic
backside contact [.LaK84] . The purpose on the Au is to help reduce the sheet
resistance of the composite In/Au/Cr since this layer must now be used as the 2nd
terminal to the ELO DBRTD. The Cr is used to ensure that the composite
metallization adheres to the glass slide.
Upon completion of processing the devices were tested using a Keithley 230
programmable voltage source and a Keithley 195A digital multimeter controlled by an
IBM PC-AT. The results shown here are for devices approximately 3-5 |J.m in
diameter. The ELO DBRTDs were tested with a two-probe arrangement with one
probe touching the topside contact and the other probe touching the In/Au/Cr
metallization on the glass slide.
The current density-voltage (J-V) characteristics (average and standard
deviation) for both structures are summarized in Table 6.1. Also a typical forward
bias J-V characteristic of the ELO DBRTD is plotted together with forward bias J-V
characteristics of the baseline DBRTDs in Figure 6.2. Forward bias is defined as
electron injection from the backside contact through the quantum well to the topside
contact
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100
ELO
DBRTD
Baseline
DBRTD
Reverse
Bias
Forw ard
Bias
Reverse
Bias
Param eters
Forw ard
Bias
Peak Voltage, Vp
0.97± 0.03 0.81 ± .03 0.72 ± .07 0.64 ± .06
VD- Vv, AV
Peak Current Density
Jp (kA/cm2)
Jp - Jy» AJ
Peak-to-Valley
Current Ratio
0.11 ±.02
45 ± 6
0.13 ± .03 6.3 ± .04 0.26 ± .05
42 ± 5.5
52.1 ± 4.7 51.3 ±4.4
21A ± 4.7 28.9 ± 4.3 3&6 ± 4.6 36.3 ± 4.5
2.6 ± 0.17 3.2 ± 0.22 3.9 ± 0.4 4.3 ± 0.5
Table 6.1: Characteristic J-V data for the ELO DBRTD (MBE Run# 1043) and a
standard baseline DBRTD. Note the higher peak voltage, lower AV, lower AJ, and
lower PVCR of the ELO DBRTD.
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101
60000
50000
o II
j
40000
3
30000
5
Q
|
•o
•o
20000
C>
10000
0.0
0.2
0 .4
0.6
0.8
1.0
1.2
1 .4
Voltage (V)
Figure 6.2: Typical forward bias J-V characteristics for the ELO DBRTD and a
baseline DBRTD. The closed circles are the measurements taken for a baseline
AlAs/GaAs DBRTD and the open circles are the measurements taken for an ELO
AlAs/GaAs DBRTD. Note in the J-V characteristic of the ELO DBRTD on
In/AuCr/glass that the valley current profile the ELO DBRTD rises faster and the
PVCR and the AV are reduced.
As is evident from Figure 6.2, the ELO DBRTD exhibited NDR with J-V
characteristics comparable to the baseline DBRTDs. Slight degradations in the key
electrical parameters (PVCR, AV, and AJ) of the ELO DBRTD may be attributed to a
poor backside ohmic contact and the observed faster rise in its valley current. As
stated earlier, the valley current is a function of the temperature dependent inelastic
tunneling that occurs in AlAs/GaAs DBRTDs. The possible rise in temperature may
be due to the fact that the ELO DBRTD was mounted on a metallized glass substrate,
which actually produces a higher thermal resistance than the n+ GaAs substrate of the
baseline DBRTDs. Although the specific contact resistivity of the backside ohmic
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102
contacts cannot be determined directly from these structures, it has been approximated
indirectly from a program which can extract current density-electric field, J-E, curves
from measured DC-IV characteristics [Mil90] . Since the o of the quantum well is
known, as well as the doping concentrations and layer thicknesses, one can
approximate the specific contact resistivity o f the backside ohmic contact. Using this
program, the specific contact resistivity of the backside contact was 8 x l0 ‘6 O-cm2.
Although the electrical contact to the device was satisfactory, the mechanical and
thermal contact to the substrate were quite poor. As with all thin films, it is difficult
to quantitatively evaluate the amount o f adhesion between the ELO film and its
substrate. A primitive test is to use a "Scotch" tape test. The ELO DBRTDs on In
did not survive the tape tests. In fact, as shown in Figure 6.3, since mechanical
contact to the substrate was poor, it is probable that the thermal contact was also poor
resulting in a higher thermal resistance between the substrate and the device.
Figure 6.3: SEM micrograph of an ELO device bonded to an In/AuCr coated glass
substrate after an anneal at 350°C. Note the roughness o f the In at the edges of the
ELO film. This type o f bond did not survive a "Scotch" tape test.
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103
Thus, from this initial experiment, it was found that possible improvements could be
made on these ELO DBRTDs if an alternative substrate of higher thermal conductivity
was used. In addition, a better mechanical and thermal bond are required for better
reliability and thermal contact to the substrate. Furthermore, improved lower specific
contact resistivities are needed to remove parasitic series resistance in the device
measurements which reduce AV. Note that the extracted backside specific contact
resistivities presented on the previous page for the In-based backside contacts and the
other ohmic backside contacts to be presented later represent the best possible or a
lower limit on the backside specific contact resistivity. The choice of alternative
substrates for the AlAs/GaAs DBRTDs is made based not only on their thermal
conductivities, but also on their pre-existing surface smoothness, whether they are
optically smooth and are amenable to VDW bonding. Therefore, an attempt was
made to bond a similar ELO DBRTD to a Si substrate coated with the same In/AuCr
metallization to provide an ohmic contact to the backside of the ELO layer. Similar
results were observed on an another ELO AlAs/GaAs DBRTD (MBE Run# 1376).
This DBRTD utilizes the same structure seen in Figure 6.1 except that the substrate is
n+ GaAs and there is now a 500A ALAs release layer that is very heavily doped ntype. With such an arrangement, the ELO DBRTD can be tested both before and after
ELO so that the effects of the integration of the ELO AlAs/GaAs DBRTD to another
substrate can be observed. The J-V characteristics for this DBRTD before and after
ELO are summarized in Table 6.2.
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104
AFTER ELO
MBE Run # 1376
BEFORE ELO
MBE Run # 1376
Forward
Bias
Parameters
Forward
Bias
Reverse
Bias
Peak Voltage, Vp
0.76 ± 0.02
Vp - Vv, AV
0.24 ± 0.01
-0.65 ± 0.02 0.98 ± 0.05 -0.82 ±
0.03
-0.23 ± 0.02 0.08 ± 0.03 -0.07 ±
0.03
-57.7 ± 2.6 57.2 ± 5.4 -50.7 ± 4.4
Peak Current Density 63.3 ± 3.0
Jp (kA/cm2)
Valley Current
15.9 ± 1.7
Density, Jv
Peak-to-Valley
4.0 ± 0.3
Current Ratio
-12.8 ± 0.6
4.5 ± 0.2
Reverse
Bias
19.0 ±2.1
-14.4 ± 1.3
3.0 ±0.1
3.5 ± 0.03
1
Table 6.2: Characteristic J-V data for an AlAs/GaAs DBRTD (MBE Run# 1376)
both before and after ELO. Again note the higher peak voltage, lower AV, lower AJ,
and lower PVCR of the ELO DBRTD. Although the device was bonded to Si, a
reduction in the valley current density was not seen. As shown in Figure 6.3, it is
believed that the mechanical and thermal contact to the backside of the ELO DBRTD
did not provide an improvement over the original substrate.
From the data in Table 6.2, it was observed that bonding an ELO DBRTD to an
In/AuCr coated Si substrate, with its higher thermal conductivity and smoother optical
polish, still did not provide an adequate mechanical, thermal, or electrical ohmic
contact to the new substrate. Again, as in the previous sample mentioned earlier
(MBE Run# 1043), the valley current density was higher and the AV and the PVCR
were reduced. Assuming a o of 0.3 (1/Q-cm) for the quantum well, the extracted
specific contact resistivity of the backside contact is 9.5 x 10"6 Q-cm2. Furthermore,
this type of bond did not survive a simple "Scotch" tape test As a result of the
unsatisfactory bonds to various In coated substrates, an alternative bonding medium
was required that could provide both a better ohmic contact to the backside of an
ELO device and an improved mechanical bond to the alternative substrate. The
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105
previously mentioned silver epoxies in Chapter 3 did not provide reasonable ohmic
contacts and required long cure times at temperatures near the softening point of the
Apiezon W black wax.
6.3 Epitaxial Lift Off of AlAs/GaAs QWITTs and Integration with
Alternative Substrates using Pd-based Bonds
An improved bonding method to alternative substrates, as discussed in
Chapter 3, section 3.7, incorporates Pd as the bonding medium \YaS91] . Although
these bonds provide very good mechanical bonds to the alternative substrates, the
electrical ohmic contacts quoted were not impressive. In an effort to test these bonds
to alternative substrates, several AlAs/GaAs QWTTT structures with n+ ALAs release
layers were grown on n+ GaAs substrates and processed based on the standard
process flows described in Chapters 3 and 4.
The first device structure described here is an ELO AlAs/GaAs DEM-QWITT.
The J-V characteristics of this device, before ELO, have already been described in
Chapter 4, section 4.10. Since the ALAs release layer is very heavily doped n-type,
measurements could be taken before ELO. A cross-sectional layer structure of this
device is shown in Figure 4.12. After complete device characterization, the samples
were separated from the GaAs substrate and bonded to a Pd/AuCr coated Si
substrate. During the vacuum bag bonding procedure, as described in Chapter 3,
section 3.6 and 3.7, the pressure was maintained at 15 lb/in2 and the temperature was
kept at 50°C overnight. Upon removal of the Apiezon W black wax, the device was
tested again with the following J-V characteristics summarized in Table 6.3. No alloy
was attempted initially to improve the backside ohmic contacts.
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106
BEFORE ELO
MBE Run # 2028
1 AFTER ELO
| MBE Run # 2028
Reverse
Bias
Forward
Bias
Reverse
Bias
Peak Voltage, Vp
1.01 ±0.04
-7.5 ± 0.41
1.2 ± 0.05
-6.7 ± 0.7
0.20 ± 0.00
Peak Cunent Density 21.4 ± 0.8
Jp (kA/cm2)
Valley Current
14.3 ± 0.8
Density, Jv
Peak-to-Valley
1.5 ± 0.1
Current Ratio
-4.9 ± 0.36
-14.1±1.2
0.1710.04 -3.0 ± 0.6
21.6 ± 0.6 -13.9 ± 0.4
>
<
Forward
Bias
1
Parameters
-6.5 ± 0.6
B13.5 ± 0.4
-4.6 ± 0.1
2.2 ±0.3
11.6 ± 0.01
3.010.1
Table 6.3: Characteristic J-V data for an AlAs/GaAs DEM-QWITT (MBE Run#
2028) both before and after ELO. Note that the PVCR is actually higher and the
valley current lower after ELO, in both bias modes. The AV has decreased after
ELO, indicating that the backside ohmic contact has an overall higher series
resistance.
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107
A schematic showing a typical mesa isolated ELO device bonded to Pd/AuCr coated
Si substrate is shown in Figure 6.4.
J= K .
_________________ n+ GaAs buffer layer___________
j
_______________________257A Palladium_______________________
_______________________ 2000A Gold_________________________
55A Chromium
/t+ silicon substrate
Figure 6.4: Illustration showing a mesa isolated ELO DBRTD or QWITT bonded to
a Pd/AuCr coated silicon substrate. This bond is initially created using a vacuum
bag/oven combination which provides the proper pressure/temperature combination to
cause a solid phase reaction between the GaAs and Pd to form PdUGaAs.
The utilization of Pd as a bonding medium has allowed extremely reliable bonds with
very good mechanical and thermal contact to the Si substrate. From the DC-IV
characteristics, it was observed that the PVCR and Jv did not degrade and in fact
improved slightly. From discussions of the temperature dependence of the valley
current, in section 4.6, and inelastic tunneling, in section 4.4, it is possible that the
AlAs/GaAs DEM-QWITT is operating at a slightly lower temperature and therefore
exhibits a lower Jv and higher PVCR. The AV was reduced after ELO, possibly
indicating that the contact resistance of the backside contact was higher than before
ELO. This result is qualitatively consistent with the high specific contact resistance
reported by Yablonovitch and co-workers using Pd bonds [YaS91]. The
morphology of the edges of the ELO layer and Pd appear to be very clean, with no
gaps or bumps at the interface, as shown in Figure 6.5.
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108
0040
2 5 KU
XS. 0 0 0
WD12
Figure 6.5: SEM micrograph of an ELO DEM-QWITT bonded to a Pd/AuCr coated
n+ silicon substrate after an overnight bond in a vacuum bag. Note the smooth
surface with no gaps, bumps or defects at the edges of the ELO film. This bond is
much improved over the In based bonds in terms of bond strength and reduced
defects.
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109
The sample was alloyed at 350°C for 1 minute in forming gas to see if an
improvement in the backside ohmic contact resistance would occur. After the alloy,
no improvements electrically were found and in addition, there was some damage to
the ELO film as some large bumps and cracks formed in the film. Once cracks form
in the ELO film, there can be a tendency for the film to lift up from the surrogate
substrate which can peel up additional areas of film, which will be discussed further
in Section 6.4. A rough estimate of the backside specific contact resistivity, using the
extraction program mentioned earlier, was found to be around 1.3 x 10~5 Q-cm2.
This specific contact resistivity is slightly worse than those extracted using an In­
based bond.
In an attempt to improve the backside ohmic contact resistance, the common
PdGe recipes for normal topside ohmic contacts [MaZ87] \YuW89] \WaL89] are
used in a second device structure. The second device structure described here is an
ELO Alo.3 Gao.7 As/AlAs/GaAs chair barrier QWITT (MBE Run# 1437). The J-V
characteristics of this device, before ELO, have already been described in Chapter 5,
section 5.4. A cross-sectional diagram of this device is given in Figure 5.9. After
complete device characterization, the samples were separated from the substrate and
bonded to a PdGe coated Si substrate as shown in Figure 6 .6 . Subsequently, the
ELO device/bonding medium/substrate combination were alloyed at 300°C for 5
minutes in forming gas in an effort to create ohmic contacts to the backside. As in the
previous sample, the high temperature step created a significant amount of bumps and
cracks in the film. The origins of this type of defect are related to trapped gas around
particles which may expand at high temperatures, which will be discussed further in
Section 6.4.
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110
/?+ GaAs buffer layer
SOOA Palladium
1400A Germanium
400A Palladium
n+ silicon substrate
Figure 6 .6 : Illustration showing a mesa isolated ELO DBRTD or QWITT bonded to
a typical Pd/Ge/Pd coated silicon substrate. This bond is created using a vacuum
bag/oven combination, discussed in Chapter 3, which provides the proper
pressure/temperature combination to cause a solid phase reaction between the GaAs
and Pd to form Pd4 GaAs. Subsequently, the ELO film/Pd/Ge/Pd combination are
alloyed at 300°C for S minutes in order to form an ohmic contact.
The results of the measured J-V characteristics before and after ELO are given in
Table 6.4. From the data presented in Table 6.4, it is observed that the PVCR
increased and the valley current density decreased. The AV was also observed to
decrease which indicates that the Pd/Ge/Pd ohmic backside contacts after anneal still
did not provide an adequate specific backside contact resistance. Several factors may
have contributed to the poor backside specific contact resistance. The Pd/Ge/Pd
metallization scheme was not tested as a topside ohmic contact to the mesa isolated
DBRTDs or QWITTs and furthermore, no Cox-Strack specific contact resistance
measurements were performed yet. Ideally, a vacuum system with a very low base
pressure (in the 10' 7 Torr range) is desired for this type of metallization since Ge is
very reactive and can be oxygen contaminated from the alumina coated tungsten boats
or a high base pressure.
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I ll
BEFORE ELO
MBE Run # 1437
AFTER ELO
MBE Run # 1437
Parameters
Forward
Bias
Reverse
Bias
Forward
Bias
Reverse
Bias
Peak Voltage, Vp
0.61 ± 0.07
-2.71 ± 0.1
1.1 ±0.18
-3.2 ± 0.1
Vp - Vv, AV
0.36 ± 0.05
-6 .$fc ± 6.6$ 0.07 ±0.04 -0.54 ±
0.04
-64.4 ± 1.9 46.3 ± 1.7 -6 0 . 1 ± i o
Peak Current Density 46.8 ± 1.5
Jp (kA/cm2)
Valley Current
15.6 ± 0.3
Density, Jv
Peak-to-Valley
3.0 ±0.1
Current Ratio
-17.1 ± 0.4
14.2 ± 0.5
-14.5 ± 0.6
3.8 ± 0.2
3.3 ± 0.1
4.1 ±0.1
Table 6.4: Characteristic J-V data for an Alo.3 Gao.7 As/AlAs/GaAs QWITT (MBE
Run# 1437) both before and after ELO. Note that the PVCR is actually higher and
the valley current lower after ELO, in both bias inodes. The AV has decreased after
ELO, indicating that the backside ohmic contact has an overall higher series
resistance.
The evaporation system used in this study, named "Philvac", has a base pressure of
only 3 x 10*6 Torn Furthermore, the high backside contact resistance may also be
related to the damage that occurred to the film during the alloy cycle. The extracted
specific contact resistance of the backside ohmic contacts is approximated to be 1 .2 x
10*5 Q-cm2. From this section, it is observed that no degradation in the PVCR and
Jv were observed after ELO, but there was significant decrease in AV as a result of
the higher backside ohmic contact resistance. In Figure 6.7, a comparison between
the J-V curves of the ELO chair barrier QWITT before and after ELO is shown.
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112
50000
40000 30000 -
20000
-
10000
-
Closed circles: After ELO
-
10000-
-20000 -3 0 0 0 0
-4 0 0 0 0 -5 0 0 0 0 -
Open circles: Before ELO
-6 0 0 0 0 -7 0 0 0 0
-5
-3
-1
1
Voltage (V)
Figure 6.7: Characteristic J-V data for the ELO Chair barrier QWITT before and after
ELO. Note that the PVCR in both bias directions improved slightly with the only
significant degradation in device characteristics occurring in the AV due to a higher
backside contact resistance after ELO.
The samples described in this section and the previous section represent the first time,
to the best of this author's knowledge, that AlAs/GaAs DBRTD or QWITT structures
have been integrated with Si substrates. Other substrates have been investigated as
possible surrogate substrates based on their thermal conductivities, as shown in Table
6.5.
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113
Alternative Substrate Material
GaAs (n)
GaAs (n+)
Si(undoped)
Si (high doping)
Diamond Da
Copper (OFHC)
Gold
Thermal Conductivity, k, (Watts/°C-cm)
0.5
0.4
1.45
1.15
2 2 .0
1
4.0
3.16
Table 6.5: Thermal conductivities for various materials. Taken from B.S. Perlman
[Col76] .
For cases of constant thermal conductivity and no internal heat generation, the
appropriate form of the steady state heat conduction equation is Laplace's equation:
The thermal conductivity is defined from Fourier's heat conduction equation, as
shown in equation 6 .2 .
dx
(6 .2)
where qx is the rate at which heat is transferred per unit area by conduction (heat
flux), k is the thermal conductivity, T is the temperature, and A is the area through
which the heat is transferred. Simple solutions to these equations were used as a
guide in determining the possible benefits of using a particular substrate and how
much the thermal resistance could be reduced. Complex solutions, which were
performed in this work, must take into account arbitrary shapes, the temperature
dependent thermal conductivity of the materials used, the aluminum mole fraction
dependent thermal conductivity of the AlxGai_xAs/GaAs layers [Ada85], internal heat
generation, and the thermal contact resistance of the interfaces between the device and
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114
its corresponding hybrid substrate. The thermal resistance, R^, for a particular
device can be determined in an analogous fashion to electrical resistance, which is
defined as:
where Rth is the thermal resistance, Tmar is the maximum temperature at the source of
heat, Ta is the ambient temperature, and Pdiss is the power generated from the device
and is equal the rate of heat transfer. One way to reduce the thermal resistance is to
thin the substrate as much as possible, for which the ELO method is ideal, and bond
it to an alternative substrate of higher thermal conductivity.
It should be noted that ELO DBRTDs and QWTTTs have been lifted from their
original growth substrates and bonded to Pd coated copper substrates, which have
higher thermal conductivities than silicon, but the resultant J-V characteristics were
nominally worse in all parameters of interest The cause of this degradation of all
parameters may be due to the rough surface of the commercially purchased copper
foil. Ideally, this copper foil should have been optically polished for the smoothest
surface before an ELO bond was attempted. As a result future work must include
optically polishing the copper foil before ELO. Therefore the electrical measurements
obtained thus far on copper substrates will not be presented.
6.4 Process Problems Associated with ELO DBRTDs and QWITTs
As already discussed in Chapter 3, sections 3.5-3.7 and Chapter 6 , sections
6.2-6.3, achieving reliable bonds between the ELO devices and their surrogate
substrates is one of the most difficult parts of the ELO process. Obtaining good
backside ohmic contacts to the back of the ELO layers puts further restraints on this
process. One of the major problems in obtaining good contact between the ELO
device and its surrogate substrate is particulate contamination. Even in a DI-H2 O
environment, complete removal of particulates is very difficult. Particulates on the
order of < 1 pm can severely degrade the overall reliability of the bond between an
ELO film and its surrogate substrate, as shown in Figure 6 .8 .
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115
Figure 6 .8 : SEM micrograph of particles on the order of ljim preventing a reliable
bond at the edge of an ELO QWITT layer and its alternative silicon substrate.
To avoid particulate problems, cleaving the original growth substrate up to the edges
of the Apiezon W black wax carrier before ELO will aid in preventing excessive
amounts of the ELO film from extending beyond the mechanical support of the wax
carrier and therefore preventing loose, broken pieces of the ELO film from readhering to the bottom of the ELO layer. Even in a DI-H2 O environment, these
broken pieces of the ELO film can cause severe particulate contamination. A clean
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116
room environment would also be ideal for performing the particle sensitive ELO
bonding procedure. Other types of particulates can also trap gas bubbles. These
bubbles prevent any formation of a VDW or metal/alloy bond. In addition, during the
alloy stages of creating a metal/alloy bond, the particulates and/or bubbles tend to
expand and burst causing pits or extremely small "craters", as shown in Figure 6.9.
Figure 6.9: Photograph showing regions where there were very small bubbles that
burst or broke upon rapid thermal annealing the backside ohmic contacts.
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117
Preventing excessive bubble formation can be done through using the proper vacuum
bag/oven temperature settings and proper substrate cleaning methods. The strong
vacuum in the vacuum bag helps draw out both moisture and any trapped air that may
be underneath the ELO film. While under vacuum, the vacuum bag/ELO sample
combination can be placed in a Blue M Bake oven at slightly elevated temperatures.
These raised temperatures initiate the solid phase reaction between the ELO film and
the In-based or Pd-based bonding medium. Pressures of 15 lb/in2 and oven
temperatures of 50°C for one overnight period have been found to work very well in
preventing bubble formation during ELO bonding to In-based or Pd-based bonding
mediums. Pre-existing cracks in the ELO films, due to damage that can occur to an
ELO film if it is not suspended or anchored after it has separated from its original
substrate, can also result in poor bonds to the alternative substrate, as shown in
Figure 6.10.
8045
25KU
X550
10HB WD12
Figure 6.10: SEM micrograph of cracks that formed in an ELO DEM-QWITT and its
subsequent release from the surrogate substrate.
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118
Specific to the DBRTDs and QWlTTs, it is very important to apply the Apiezon W
black wax properly over the mesa isolated devices since the AlAs barriers of the
quantum wells can also get attacked by the 10% HF during the lift off procedure. In
Figure 6.11, a DBRTD at the edge of the ELO film was not properly protected with
Apiezon W black wax.
Figure 6.11: SEM micrograph showing the peeling up of the top half of an
AlAs/GaAs DBRTD, above the quantum well, which was not covered properly with
Apiezon W black wax during the lift off in 10% HF.
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119
6.5 Epitaxial Lift Off of an Optically Controlled Schottky Contacted
Coplanar Waveguide (CPW) Phase Shifter and Bonds to Transparent
Substrates
The purpose of this section is to show the significant improvement in the
performance of a Schottky-contacted coplanar waveguide (CPW) structure as a result
of using the ELO method. Device fabrication and testing of this device is performed
by M. Saiful Islam [Isl93~\ with the ELO fabrication methods performed by this
author. The ELO Schottky-contacted CPW phase shifter is a device that allows
microwave signals to be carried along its length which undergo large phase shifts due
to optically controlling the RC shunt admittance of the transmission line. The
Schottky contacts are heavily reverse biased until the lightly n-type doped epi film is
almost fully depleted, as shown in Figure 6.12. For the layer thicknesses shown in
Figure 6.12, reverse biases of about 20 V are needed to fully deplete the epi-layer. At
these voltage biases, small amounts of illumination can cause significant changes in
the admittance of the device structure. For this optically sensitive device to be useful,
the metallization must be made very thick to avoid any losses. If the optical
illumination is incident from the top of the sample, it is apparent that the thick
metallization shadows or blocks the majority of the illumination. Typical parameters
of interest for this type of device are the insertion loss, the optically induced phase
shift, and most importantly, the loss per degree of phase shift or the "loss figure".
In the fabrication of this devices [Isl93], the metallization pattern is laid down
on the epitaxial GaAs/semi-insulating GaAs substrate using a photoresist/polyimide
lift off process. Since the metallization is extremely thick, the photoresist profile is
very important where a reverse gradient in the profile is desired. Unfortunately, this
profile does not always occur and therefore lfim tall metal flags remain after the
photoresist has been removed. These flags can break and sometimes short out the
r.f. signal line to r.f. ground. In the ELO process, the application of the Apiezon W
black wax apparently helps remove these flags, many times improving the device
yield after ELO compared to the yield before ELO.
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120
Illuminationfrom the top is almost completely
shadowed by the metallization which covers
the majority of the device.
I
I 7pm I
r f ground
350A Cr + 1.2 pmAg
10pm
r f signal
I 7pm I
2pm n- GaAs epitaxial layer
=7* 1015 cm:3
rf ground
SSOA Cr + 12pmAg
500A AlAs Release Layer
Semi-insulating GaAs Substrate
500 pm thick
Access to fully depleted epitaxial layer impossible
due to thick GaAs substrate.
Figure 6.12: Illustration depicting a typical Schottky contacted CPW phase shifter
before ELO. Note all device processing and testing performed by M. Saiful Islam.
The ELO processing of this device is performed by this author.
Since these devices are fairly large, typical dimensions of the ELO films for these
devices are about 0.8 inches by 0.5 inches. Films as large as 1 inch by 1 inch have
been separated from their substrate. The ELO process, as applied to the ELO CPWs,
follows the process described in Chapter 3 with some minor variations to the process.
First, since these device structures are very large, the time for complete separation
from the GaAs substrate may be realistically as long as 64 hours due to bubble
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121
formation, indium on the edges of the chip, and improper tension in the wax carrier.
Once separated from the substrate, the ELO film is quite sturdy due to the thick
topside metallization. These ELO CPWs are usually bonded by VDW bonds or
cyanoacrylates to clear fused quartz slides with dimensions of 1.S inches by 0.7S
inches. If VDW bonds are used, then the ELO Elm’s manipulation and bonding all
occur under DI-H2 O which is the cleanest environment that was available. If
adhesives such as cyanoacrylates or UV curable epoxies are used, then the film
manipulation and bonding are performed in a fume hood. The bond line of the
cyanoacrylates is very thin and uniform and offer a very good bond to the transparent
quartz slides. During the bonding stage of these ELO CPWs, attention must be paid
to the thick topside metallization which occasionally extends beyond the wax carrier’s
periphery. Since the topside metallization is very flexible, it has a tendency to wrap
around the bottom of the wax carrier during VDW or cyanoacrylate bonding. The
best way to avoid this problem is to cleave the sample/substrate to the edges of the
Apiezon black wax carrier on all sides such that this topside metallization does not
become a problem. Furthermore, excessive amounts of cyanoacrylates should be
avoided since any extra cyanoacrylate that gets pushed out from underneath the
sample during vacuum bag bonding will spread onto the top of the wax carrier.
Cyanoacrylate on top of the wax carrier prevents subsequent removal of the black
wax with TCA. Although acetone can remove the cyanoacrylate, it can also degrade
the backside bond of the ELO film to the quartz slide at the edges. The use of
cyanoacrylates over VDW bonds has allowed the freedom to work in a noncleanroom environment and given much more reliable bonds to transparent
substrates. A typical schematic of an ELO CPW after ELO is shown in Figure 6.13.
Once the ELO CPW has been bonded to the quartz slide, the sample is now on a
transparent substrate as well as a substrate of lower dielectric constant. GaAs has a
relative dielectric constant of er = 13 whereas quartz has a relative dielectric constant
of er = 3.8 [Ba.189] . Through the use of a transparent surrogate substrate, greater
optical control of the ELO CPW can be obtained now that optical contact to the
backside of the fully depleted n- GaAs epi-layer can be obtained. Optical illumination
of the device can be done by either a light emitting diode or semiconductor laser diode
operating a t» 800nm.
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122
Illuminationfrom the top is almost completely
shadowed by the metallization which covers
the majority of the device.
I 7pm I
rf ground
whkmmvzm
7
10pm
rf signal
I 7pm I
— '~***2pmn- GaAs epitaxial layer
350A Cr hi-12 pm Ag
~7 X 1015 cm~3
r f ground
j
350ACr+12 pmAg
Clearfused quartz slide
i
f
i
l
l
!
!
!
Optical contact to the fully depleted n-GaAs layer
is now possible with no shadowing or blocking
<of optical illumination due to substrate or metallization
Figure 6.13: Illustration showing the ELO CPW bonded to a clear fused quartz slide
using either cyanoacrylates or VDW bonds.
The following data [/s/93] is taken for an ELO CPW using a semiconductor laser
diode operating at 809nm with an optical intensity of 0.65 mW/cm2.
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123
Phase shift (°/cm)
at 30 GHz
Insertion Loss
(dB/cm) at 30 GHz
Approximate Loss
Figure (dB/degree)
at 30 GHz
ELO, A fter
ELO,
B efo re
ELO , A f t e r
illumination from illumination from illumination from
the backside.
the topside.
the topside.
45?
350?
250?
-15
-25
-40
-1 .0
-0 . 1
-0 .1
Table 6 .6 : Measurement taken on an ELO CPW before and after ELO. The
measurements were taken by M. S. Islam [IsT91~\.
The ELO CPW has achieved the best loss figures of =-0.1 dB per degree of phase
shift for any optically controlled phase shifter. In the ELO CPW, it is observed that
not only was an ELO device integrated with a surrogate substrate with certain desired
characteristics, but the performance of the ELO device improved dramatically as a
direct result of ELO. Improvements in a similar ELO device, an ELO GaAs Schottky
photodiode [KoS92] , were reported after this work [IsT91] was already published.
Another group has also used ELO to obtain significant improvements in the quantum
efficiency of AlGaAs/GaAs/AlGaAs double heterostructures by placing these
heterostructures on substrates of higher reflectivity [ScY93] .
In an effort to fully integrate an optically controlled Schottky contacted CPW
with its light source, an attempt was made to perform a back-to-back integration of an
ELO CPW and ELO light emitting diode (LED) with a clear quartz slide in between
the two devices as shown in Figure 6.14.
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124
Illuminationfrom the top is almost completely
shadowed by the metallization which covers
the majority o f the device.
I I I i J I
j* -4
I 7/Jmt
10pm
I 7pm I
mmmmm
_____ _
350A Cr f 1 2 pm Ag
2pm n- GaAs epitaxial layer
=7* 1015 cm'3
^50A Cr
h1 2
pm A g
Clearfused quartz slide
1111111111
LbB^BBw
Ground
GaAs buffer layer thickness < lpm
4
W
ELO light emitting diodes
^
Ground
Figure 6.14: Hybrid back-to-back bonding of an ELO CPW and an ELO double
heterostructure LED or multi-quantum well (MQW) LED. Both the ELO CPW and
ELO LED are bonded to the surrogate quartz substrate with cyanoacrylate.
Several double heterostructure and multiquantum well (MQW) LEDs were grown by
MBE and processed using a stripe mask for use as an integrated source of optical
illumination for the ELO CPW. The designs and layer structures used for the double
heterostructure LEDs follow those taken from the literature [PoD90 ] \PoA90\. The
use of ELO on LEDs has been shown to produce significant improvement in output
power by using a back reflector once the GaAs substrate has been removed [PoA90].
A typical cross-section of an ELO MQW LED grown in this study is shown in Figure
6.15.
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125
1000A
1000A
1000A
1000A
ioooA
1000A
ioooA
1000A
1000A
500A
p+GaAs
1 . 4 x 1 f t lW 3
P+ Alo.^GaoeAs
P- AlfuGao.fiAs
undoped GaAs
undoped Alo^Gao.7As
undoped GaAs
n- Alo 4 Gao ^As
n+ Alo.4 Gao.6 As
n+GaAs
4.3 x 10l8cm-3
n+ ALAs release layer
x 14
3000A n+ GaAs buffer laver
n+ GaAs substrate
Figure 6.15: Illustration showing a typical MQW LED type structure designed for
emission of light with a wavelength of = 750nm using software written by T.R.
Block.
Since a planarized LED was not possible due to the inavailability of a proper mask
set, a single layer stripe mask or dot mask was used to pattern the topside contacts
which consisted of 50A Cr and 1000A Au. Subsequently, the device was mesa
isolated and then a ground contact (Ni/AuGe/Ni/Au) was made to the n+ GaAs buffer
layer. Once the device was completely processed, it was separated from its substrate
using the ELO method, as described above for the ELO CPW and in Chapter 3, and
bonded to a clear fused quartz slide with cyanoacrylate. Upon testing this device, it
was observed that minimal light was emitted from the backside or the edges. A
possible explanation for this poor performance is due to the fact that these devices
were grown by MBE during a time when there were a significant number of oval
defects generated in these film. Furthermore, a planarized mask set for these devices
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126
would have simplified the processing of these type of devices. With the above
process, the alloy of Ni/AuGe/Ni/Au contacts had to occur after the AuCr stripes or
dots were patterned. The alloy subsequently caused the stripes or dots to ball up.
Mesa isolation may also not have been desired due to the high surface recombination
velocity at the exposed edges of the mesas, but without a planarized mask, this step
cannot be removed.
6.6 Future Work Involving Hybrid Integration of ELO Devices
A great majority of the possible ELO integration schemes could have been
simplified if planarized processes were used where all external contacts are on the
topside. For example, bonding ELO DBRTDs and QWITTs to substrates of higher
thermal conductivity would be much simpler if the requirement of a good electrical
ohmic contact were lifted and only the requirements of a good mechanical and thermal
contact to the substrate were essential. Thus, the need for a special metallization or
bonding medium that forms an ohmic contact to GaAs is not needed. Planarization of
DBRTDs and QWITTs would allow the possible use of solventless, high thermal
conductivity epoxies which contain no silver flakes dispersed within the epoxy. A
four level planarized mask set has been designed for the DBRTDs and QWITTs
which utilizes air-bridge isolation instead of dielectric isolation [.Jav91] , as shown in
Figure 6.16. By inserting a highly resistive, low temperature (LT) GaAs layer
between the active device layers of a standard ELO AlAs/GaAs DBRTD or QWl'lT
and the AlAs release layer, one can obtain electrical isolation between the active
device layers and the alternative substrate after ELO. A few difficulties with this
mask set are still being worked out and therefore this process has not be attempted
yet As this process is developed, a structure similar to the one shown in Figure 6.16
will allow the opportunity to integrate planarized DBRTDs and QWITTs to alternative
substrates without any concern of obtaining an electrical ohmic contact to the backside
of the ELO layers.
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127
Two metallization steps required:
1. Ni/AuGe/Ni Ohmic Contact Metallurgy (1000A)
This metallization provides the electroplating base.
2. Electroplated Au Interconnect Metallurgy (1 Jim)
X
Ni/AuGe/Ni/Au air bridge used to
isolate the bias pad from the eround
To
Ground
Plane
V
n+ GaAs Buffer Layer
Mesa Isolated DBRTD
01 Q w rrr structure
Nominal
50 AGaAs
Wed
Low temperature (LT) GaAs Buffer Layer
undoped or n+ AlAs Epitaxial Liftoff Layer (500A -1 0OOA)
Semi-insulating or n+ (100) GaAs Substrate
Figure 6.16: Illustration showing the planarized ELO DBRTD or QWl'lT utilizing an
air-bridge for device isolation and an LT-GaAs layer for backside isolation.
In a similar manner, a planarized process for the LEDs used in this study
would allow fabrication of device structures that have large pads that can be bonded
to an external carrier using a wire bonder. With the ELO LED mounted on the
external carrier, an ELO CPW can easily be integrated to the back of the LED's quartz
substrate. This would allow easy external control of the ELO LED as it is used to
optically control the ELO CPW.
Further work should be continued in the area of bonding ELO double
heterostructure LEDs or MQW structures to pre-pattemed substrates. Preliminary
work has been performed where AlGaAs/GaAs double heterostructures and MQW
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
128
heterostructures have been patterned with stripes, separated from their substrates
using ELO, and then bonded to pre-pattemed silicon and copper substrates coated
with Pd. These pre-pattemed substrates are etched down ^ 5pm with straight edges.
After evaporating Pd on these pre-pattemed substrates, the ELO stripe patterns are
aligned orthogonally to the edge of the patterns in the substrate and bonded. Once
placed in the vacuum bag for overnight bonding, the temperature in the oven is raised
above the softening point of the Apiezon W black wax carrier. The pressure from the
vacuum bag causes die film to bend over the edge of the pattern. Upon removing the
black wax with TCA, it is found that the stripes are cleaved over the patterned edge of
the surrogate substrate. Thus, this method may be applied to formed cleaved facets
for stripe lasers with pre-defined lengths as specified by the patterns etched in the
surrogate substrates. This method provides a simpler method of cleaving stripe lasers
than the wedge-induced facet cleaving (WFC) method [PoB91] .
Reproduced with permission of the copyright owner. Further reproduction prohibited w ithout permission.
Chapter 7
Summary and Conclusion
Some of the major concerns associated with AlAs/GaAs DBRTDs and
QWITTs are the asymmetries seen in their DC-IV characteristics. The impact that
these asymmetries have on the DC-IV parameters of interest, AJ, AV, PVCR, and Jp,
are very important in designing devices that arc useful in oscillator or switching type
applications. Through the use of a composite AlxGai-xAs/AlAs "chair" hairier, a
PVCR of 6.3 were obtained on a DBRTD structure. This PVCR is currently the
highest reported to date, to the best of the author’s knowledge, for any AlxGai.
xAs/GaAs DBRTD device. The minor barrier thickness asymmetries observed in the
baseline, symmetric AlAs/GaAs DBRTDs have also been investigated by intentionally
varying the top AlAs barriers. Here the top AlAs barrier thickness was intentionally
varied on the order of a half-monolayer, based on growth rates determined from
RHEED intensity oscillations. The device that exhibited the most symmetric DC-IV
characteristics was not the nominally symmetric structure (6ML/18ML/6ML
AlAs/GaAs/AlAs), but instead the device with a 5.5 ML top AlAs banier. This
indicates that there is an MBE growth asymmetry of unknown origin which causes
the AlAs barrier grown after the quantum well to be approximately half a monolayer
thicker than the barrier grown before the well. Furthermore, in this study, an
AlAs/GaAs DBRTD with a 7 ML top AlAs barrier produced a PVCR of 5.6. This
PVCR is the highest reported to date, to the best of the author's knowledge, for any
AlAs/GaAs DBRTD.
AlAs/GaAs DEM-QWITTs were grown by MBE, processed, and tested.
These devices utilize a doping spike downstream from the quantum well such that the
depleted drift region length is optimized at every voltage bias. These device
structures are highly dependent on accurate doping setpoints and layer thicknesses.
The structures in this study did not achieve the desired goals since they exhibited
significant hysteresis in their J-V characteristics which may be due to parasitic series
resistance from any undepleted drift region. These devices did, however, exhibit
higher AV and specific negative resistance than the baseline QWITT structures.
129
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
130
The ELO technique was utilized to separate a variety of AlAs/GaAs DBRTDs
and QWITTs from their host substrates and bond them to alternative hybrid
substrates. In addition to the requirements of a good mechanical and thermal contact,
the issues of obtaining an ohmic backside contact to the ELO DBRTDs and QWITTs
was addressed by using In-based and Pd-based metal/alloy bonds. While the In­
based bonds appeared to have slightly better backside specific contact resistances, the
Pd-based bonds displayed dramatically improved mechanical and thermal contacts to
the surrogate substrates. The ELO technique was shown to provide dramatic
improvement in the microwave characteristics of optically controlled Schottkycontacted CPW structures due to the fact that optical contact to the back of the fully
depleted epi-layers of this device was now made possible by bonding the device to a
transparent substrate. As an extension of the ELO method, thin Si epi-layers were
removed from their SOI substrates and thin InGaAs/AlAs DBRTDs were removed
from their InP substrates. In addition, etchback of InP substrates was performed as
an alternative to the ELO method in acquiring substrateless devices.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix 1
Parametric Summary of All DBRTD and QWITT Devices
The following data is a list of all the pertinent MBE runs related to double
barrier resonant tunneling diodes and quantum well injection transit diodes. Note that
the parameters Vp, AV, Jp, Jv, and PVCR are obtained directly from the
measurements and therefore have one sigma standard deviations associated with
them. The specific negative resistances and Pr.f. are also obtained directly from the
DC-IV measurements with no standard deviations given for convenience and space in
the table. The Ep, Ev, and a are extracted from the measured DC-FV characteristics,
device profile, and specific contact resistance of 3 x 10- 6 Q-cm2 and therefore have
no standard deviations associated with them. Note that the values for Ep Ev, and c
may be misleading if the specific contact resistivity used is significantly off target or if
the intrinsic structure of the quantum well is not accurately grown by MBE.
Especially for the ELO DBRTDs (after ELO), the backside contact resistances were
higher than before ELO and therefore values of Ep, Ev, and o are misleading. Since
all device parameters, such as Ep Ev, and a, are extracted with the assumption of a
specific contact resistance of < 3 x 10*6 Q-cm 2 these values do not accurately
represent the intrinsic characteristics of the quantum well and are noted by a "**" or
131
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D tic r lp lio n
M B E R un*
P eak
V alley
P eak -to -
S p e c ific
A pprox. r.f. P eak
V a lle y
In je c tio n
P eak
C u rre n t
C u rre n t
V alley
N e g ativ e
o u tp u t
E le c tric
E le c tric
C o n d u ctan ce
V oltage, Vp A V = V p.V v
D enally, J p
D enally, J v
R a tio ,
R e a la ta n c e ,
p o w e r,
F ield, Ep
F ield , Ey
0 * (dJ/dE )
(k A /cm 1 )
PVCR
R (ohm s)
P rr= 3 /ltA V
(k V /cm )
(k V /cm )
(Q -cm )*1
(kA /cm 1 )
•A I (mW )
i f
Alo.2Gao.8A t/
AlAr/GiAa
C heir Barrier
DBRTD
Alo.2Oao.8A t/
AlAi/OaAa
C hair Barrier
DBRTD
7/18/6 A lA r/
GaAa/AlAa
Asymmetric
DBRTD
7/18/6 A lA s/
GaAt/AlAa
Aaymmetrie
DBRTD
S/18/6 AlAa/
GaAt/AlAa
Aaymmetrie
DBRTD
5/18/6 AlAa/
GaAt/AlAa
Aaymmetrie
DBRTD
987AAT
0.72 1 0.02
0.33 1 0 .0 3
4 5 .7 1 4 .2
1 3 .2 1 1 .1
3 .4 5 1 0 .1 5
•1.0* i<r5
1.27
177
298
•0.27
•0.4610.01
-0.3110.01
•3 1 .7 1 3 .0
- 5 .3 1 3 .0
6 .0 1 0 .1
•1.2* 10-5
0.97
-118
-230
-0.24
0.81 1 0.03
0 .3 1 1 0 .0 3
3 4 .2 1 4 .6
1 0 .6 1 1 .4
3 .2 1 0 .2
•1.3 x 10-5
0.28
219
326
-0.22
•0.54 ± 0 .0 2
•0 .3 1 1 0 .0 2
-2 4 .1 1 3 .8
-4 .6 1 1 .0
5 .3 1 0 .3
-1.7 x io ^
0.23
•150
-258
-0.18
0.75 1 0.04
0 .3 0 1 0 .0 4
5 9 .0 1 3 .3
13 .2 1 1 .1
4 .5 1 0 .4
•6 5 x 10-6
0.85
178
308
-0.36
•0.84 ± 0 .0 4
•0 .2 4 1 0 .0 3
•74.513.1
-2 4 .9 1 1 .2
3 .0 1 0 .1
•4.8 x 10®
0.73
•188
•303
-0.43
0.98 1 0.03
0 .3 2 1 0 .0 5
5 3 .2 1 4 .2
1 5 .8 1 1 .2
3 .4 1 0 .2
•8.9 x 10®
1.15
248
372
•0.30
•0.9310.01
•0 .3 3 1 0 .0 3
•52 .4 1 4 .1
•1 4 .4 1 1 .3
3 .7 1 0 .2
•8.7 x 10-®
1.17
•235
•361
-0.30
(Forward B iu)
987AAT
(Reverie Biaa)
1020AAT
(Forward B iu)
1020AAT
(RevcneBiaa)
1021AAT
(Forward Biaa)
1021AAT
(RevcneBiaa)
1022AAT
(Forward Biaa)
6/18/6 AlAa/
GaAi/AlAi
Baseline
DBRTD
1022AAT
(Reverie B iu)
Summary of All DBRTD and QWITT Runs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D evice
S tru c tu re
® 50 t f / O
0 >Oi*
®®hJOS OOQ®
£« I * as 1*5 e r t l 5 " i _ g | | S S'S
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D ev ic e
S tru c tu re
D e ic rlp tlo n
M B E R un*
P eek
V a lle y
P e a k -to -
N eg ativ e
A p p ro x . r.f. P eak
V alley
In je c tio n
Peek
C u rre n t
C u rre n t
V alley
R e s is ta n c e ,
o u tp u t
E le c tric
E le c tric
C o n d u ctan ce
V ollege, V p A V sV p-V y
D ensity, J p
D ensity, J y
R a tio ,
R (ohm s)
p o w e r,
Field, Ep
F ield , E v
o = (dJ/dE )
(k A /cm 2 )
PVCR
(k V /cm )
(k V /cm )
(O -c m )’ 1
(k A /c m 2 )
P ,r» 3 /1 6 A V
•A I (mW )
6/11/7 A lA i/
GaAsMlAs
Asymmetric
DBRTD
6/18/7 A lA s/
GiAa/AlA*
Asymmetric
DBRTD
6/18/6 AlAs/
GsAs/AlAs
DBRTD using
A s4 C d l
6/18/6 AlAs/
OsAs/AlAs
DBRTD using
As4CeU
6/18/6 AlAs/
OsAs/AlAs
DBRTD Qusl:
new mbe cvclc
6/18/6 AlA s/
GsAs/AlAs
DBRTD Qusl:
new mbe cycle
ELO DBRTD
before liftoff.
6/18/6 AlA s/
GsAs/AlAs
ELO DBRTD
before liftoff.
6/18/6 AlAs/
OsAs/AlAs
U20AAT
(Foiwud Biss)
0.59 1 0.04
0 .2 7 1 0 .0 4
2 9 .6 1 1 .6
7 .3 1 0 .7
4.1 1 0 .3
-1 .2 * ID 5
0.14
160
258
■0.23
U20AAT
•0.67 ± 0.03
•0 .2510.03
-3 8 .9 1 3 .5
• 1 2 0 1 1 .0
3 .3 1 0 .2
•9.2* 10-6
0.16
-173
-268
•0.28
0 .7 6 1 0 .0 4
0 .2 7 1 0 .0 3
48.8 1 3.8
1 2 0 1 1 .0
4.1 1 0 .1
-7.2* ID*
1.4
190
301
•0.34
•0 .6 2 1 0 .0 3
-0 .2 4 1 0 .0 2
•4 4 .3 1 3 .5
•9 .8 1 0 .8
4 .5 1 0 .1
•7.1 * IB®
1.2
•156
•259
-0.33
0 .7 1 1 0 .0 2
0.2 9 1 0 .0 1
522122
1 3 .7 1 1 .1
3 .8 1 0 .2
-7.5 x ID®
0.69
174
290
•0.33
-0 .6 1 1 0 .0 2
-0.2910.01
-4 8 .0 1 2 1
-1 1 .1 1 0 .9
4.4 1 0 .3
-7.8 * ID®
0.67
-1 4 9 1 3
-266 1 3
-0 .3 2 1 0 .0 2
1376AAT
B efore ELO
(Eorwud B iu)
0.76 s- 0.02
0.2 4 1 0 .0 1
6 3 .3 1 3.0
1 5 .9 1 1 .7
4 .0 1 0 .3
-5.2* ID®
0.67
178
•
2 90*
I376AAT
Before ELO
(R eveneB iu)
•0 .6 S 1 0 .0 2
•0 .2 3 1 0 .0 2
-5 7 .7 1 2 .6
- 1 2 8 1 0 .6
4 .5 1 0 .2
-5.3 xlB®
0.60
•1 5 2 1 7
•
-2 6 0 1 2
•
(RcveiseBiu)
1165AAT
(Forward Biss)
1165AAT
(R eveneB iu)
1343AAT
(Forward B iu)
1343AAT
(R eveneB iu)
Summary of All DBRTD and QWl'lT Runs
-0.42 1 0 .0 2
Jp is high and
contact
resistance hieh
-0 .4 1 1 0 .0 2
Jp is high and
contact
resistance hiah
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CO
D evice
S tru c tu re
D e s c rip tio n
M BE R un*
P eak
V alley
P cak -to -
N eg ativ e
A pprox, r.f. P eak
V alley
In je c tio n
P eak
C u rre n t
C u rre n t
V alley
R e s is ta n c e ,
o u tp u t
E le c tric
E le c tric
C o n d u ctan ce
V oltage, V0 A V =V p-V »
D ensity, J p
D ensity, J v
R a tio ,
R (ohm s)
p o w e r,
F ield, E p
Field, E v
0 » (dJ/dE )
(k A /cm 2 )
(k A /c m 2 )
PVCR
P ,p 3 /1 « A V
(k V /cm )
(k V /cm )
(O -cm )-1
•A I (mW )
ELO DBRTD
after liftoff on
In/CrAu/Sl
subetntes
ELO DBRTD
ifter liftoff on
In/CrAu/Si
aubstntee
ELO QW ITT
w ith 2000A
drift region el
lxlO , 7cm ’3
ELO QW ITT
w ith 2000A
drift region el
lx l 0 , 7cm '3
ELO QW ITT
(A lo.lO 10.7A1
3M L Cheir on
S/18/6 RTD+
2000A Drift)
ELO QW ITT
(AI0.lO i0.7As
3M L Chair on
5/18/6 RTD+
2000A Drift)
elo
Qwrrr
1376AAT
A fter EL O
0.98 ± 0.05
0.08 ± 0.03
57.2 ± 5.4
19.0 ± 2 .1
3.0 ± 0 .1
-2 0 * 10-*
0.12
243 • •
299 aa
•0.68 • •
(Forward Bias)
I376AAT
A fter EL O
•0.82 ± 0.01
-0.07 ± 0.03
•50.7 ± 4 .4
-14.4 ± 1.3
3.5 ± 0.03
•1.9 * 1 0 6
0.11
•207
•a
•261
aa
•0.68
aa
(Reverse B iu)
1377AAT
0.66 ± 0.04
0.29 ± 0 .0 3
36.1 ± 2 3
10.2 ± 0.6
3.5 ± 0.1
•1.1 * 10-5
0.43
179
285
•0.25
-1.3 ± 0.04
•0.83 ± 0.04
•423 ± 2 5
-10.6 ± 0.8
4.0 ± 0.1
- 2 6 * 1 0 -5
1.47
•117
•207
■0.35
0.61 ± 0.07
0.36 ± 0.06
46.8 ± 1.S
15.6 ± 0 .3
3.0 ± 0.1
•1.2 * 10s
0.37
155
285
•0.24
-271 ± 0.1
-0.98 ± 0.09
-64.4 ± 1 .9
-17.1 ± 0 .4
3.8 ± 0.2
•21 * lO-5
1.52
-71
•194
•0.39
1.05 ± 0.18
0.07 ± 0 .0 4
46.3 ± 1.7
14.2 ± 0 .5
3.3 ± 0.1
•2 4 * 10®
0.28
273
•a
323
aa
■0.67
aa
•99
•199
•0.46
aa
aa
aa
(Forward B iu)
1377AAT
(R eveneB iu)
1437BAT
Before ELO
(Forward B iu)
1437BAT
B efore ELO
(R eveneB iu)
bonded
to 1437BAT
PdGe/Si subsk A fter EL O
(Forward B iu)
ELO QW ITT 1437BAT
bonded
to A fter ELO
PdOe/Si subek (R eveneB iu)
•3.2 ±0.05
-0 5 4 ± 0.04
•60.1 ± 2 0
•145 ± 0 .6
4.1 ± 0.1
• 1.2 * 10-*
Summary of All DBRTD and QWITTRuns
3.11
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
IT
m)
D ev ic e
S tru c tu re
D e ic rlp llo a
M BE R u n !
P eak
V a lle y
P e s k -to -
N e g a tiv e
A p p ro x . r.f. P eek
Peak
C u rre a t
C u rre n t
V alley
R e s is ta n c e ,
o u tp u t
V oltage, Vp A V =V p-V y
Dcneltjr, J p
D ensity, J*
R a tio ,
R (ohm s)
(k A /cm * )
(k A /c m 2 )
PVCR
p o w e r,
P t t = 3 /U A V
V alley
I n je c tio n
E le c tric
E le c tric
C o n d u ctan ce
Field, Ep
F ield, Ev
o = (dJ/dE )
<kV /cm )
(k V /cm )
( O - c m ) '1
•A I (m W )
6/18/6 A lA t/
GsAs/AlAs
BsscKne
DBRTD
6/18/6 AlAe/
OaAe/AlAi
BeeeHne
DBRTD
8/18/6 AlAe/
CUAe/AlAe
A iyirnittric
DBRTD
8/18/6 AlAe/
GtAi/AlAe
Asymmetric
DBRTD
5.5/18/6 AlAe/
GtAi/AlAe
Asymmetric
DBRTD
5.5/18/6 AlAe/
O tA i/AlAi
Asymmetric
DBRTD
6.5/18/6 AlAe/
GaAe/AlAe
Asymmetric
DBRTD
6.5/18/6 AlAe/
G1A 1/AIA1
Asymmetric
DBRTD
1S23BAT
0.67 ± 0 .0 2
0.26 ± 0 .0 2
42.1 ± 1.3
11.7 ± 0 .4
3.6 ± 0.1
-8.6 * ID®
0.98
174
278
•0.29
•0.59 ± 0.0}
•0.24 ± 0 .0 2
•39.1 ± 0 .7
•9.0 ± 0 .2
4.4 ± 0.1
•7.9 * 10-*
0.88
-151
-250
-0.31
0.86 ± 0.02
0.22 ± 0.01
14.3 ± 0.3
5.6 ± 0 .2
2 6 ± 0 .0 4
•2 6 * 10*9
0.40
250
319
■0.13
-0.40 ±0.01
•0.25 ± 0.01
-6.0 ± 0 .3
•1.5 ± 0.1
4.1 ± 0 .2
•5.5 x 10-*
0.24
•130
-207
-0.06
0.67 ± 0.03
0.31 ± 0.03
45.3 ± 3.5
10.6 ± 0 .7
4.3 ± 0 .3
•9.1 x 1 0 *
0.62
171
294
-0.28
•0.60 ± 0 .0 3
•0.27 ± 0 .0 2
•45.7 ± 3 .5
•11.9 ± 0 .8
3.9 ± 0 .2
■ 8 .0 x 1 0 *
0.52
•150
•261
•0.31
0.77 ± 0 .0 2
0.24 ± 0.02
42.8 ± 2 5
13.1 ± 0 .7
3.3 ± 0.1
•8.1 x 1 0 6
0.38
200
296
■0.31
•0.52 ±0.01
•0.26 ± 0 .0 2
-30.4 ± 1 .8
-6.6 ± 0 .4
4.6 ± 0 .2
-1.1 x 10*
0.32
-140
•238
•0.25
(Forwerd B iu)
I523BAT
(Reverse Biss)
1S24BAT
(ForwudBUe)
1524BAT
(ReveoeBiee)
1S25BAT
(Forwerd Bier)
1S25BAT
(ReveoeBiee)
1526BAT
(Forwerd B iu)
1526BAT
(ReveoeBiee)
Summary of All DBRTD and QWITT Runs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VO
CO
D c ic rlp tlo n
P eek
M BE Run*
V ollage, Vp A V sV p-V y
P eak
V alley
P eak -lo -
N e g a tiv e
A p p ro a. r.f. P eak
V a lle y
In je c tio n
C u rre n t
D e u lljr, J p
C u rre n t
V alley
R e ilila n c e ,
o u tp u t
E le c tric
E le c tric
C o n d u ctan ce
D enelty, J »
R a tio ,
R (ohm e)
p o w er,
F ield, E p
F ield , Ey
a = (dJ/dE )
(k A /cm * )
(k A /c m 2)
PVCR
P r fs3/14A V
(k V /cm )
(k V /c m )
( Q - c m ) 'l
•A ! (mW )
ELO QW ITT
(GeAa/InGaAa/
G iA s well, 20
% ln)
e l o Q w rrr
(GaAa/InOaAl/
O tA i well, 20
% ln)
ELO QW ITT
(G tAi/InGiAi/
O tA t well, 20
% In)
ELO QW ITT
(GeAe/InGiAi/
OeAi well, 20
%In>
6/18/6 AlAe/
OeAi/AlAe
BeaeEne
DBRTD
6/18/6 A lA i/
OeAi/AlAe
BueEne
DBRTD
8/18/6 ELO
AlAa/OaAe
DEM-QWTIT
w lu m drift.
8/18/6 ELO
AlAe/OtAi
DEM-Qwrrr
w lu m drill.
1779AAT
Before ELO
(Forw udBiu)
0.91 ± 0.01
0.31 1 0 .0 2
4 3 .2 1 0 7
2 4 .4 1 0 .4
1 .810.01
-1.6 a 1 0 s
0.35
235
334
•0.19
I779AAT
Before ELO
(R eveneB iu)
•3 .5 3 1 0 .0 2
-0 .1 9 1 0 .0 3
6 3 .6 1 1 .0
5 2 .9 1 0 .4
1.2 1 0 .0 1
•1.8 a Iff5
0.12
•157
•184
•0.41
1779BAT
A fter ELO
(Forw udBiu)
0 .9 9 1 0 .0 5
0.21 1 0 .0 4
4 1 .1 1 0 5
2 0 .0 1 0 .3
2 1 1 0 .0 3
•1.0 a Iff5
0.51
237
325
•0.24
1779BAT
A fter ELO
(ReveneBiu)
•3 .7 1 1 0 .0 8
•1 .1 7 1 0 .1 6
•5 8 .6 1 1 .0
-2 9 .6 1 2 .9
2 1 1 0 .2 2
-3.9 a KT*
4.07
•168
274
•0.29
1797AAT
0.88 1 0 .0 3
0.18 1 0 .0 2
6 0 .9 1 OS
1 7 .0 1 0 .2
3 .6 1 0 .0 7
-4.1 a If f 6
1.69
201
282
•0.54
-0 .6 0 1 0 .0 3
•0 .1 8 1 0 .0 2
-4 7 .2 1 0 .4
11 .6 1 0 .1
4 .1 1 0 .0 1
-4.9 a Iff4
1.33
•143
•222
•0.46
1.0 1 1 0 .0 4
0 .2 0 1 0 .0 0
2 1 .4 1 0 8
1 4 .3 1 0 .8
1 .5 1 0 .1 0
•2 8 a Iff5
0.17
275
338
•0.11
-7.5010.41
-4 .8 5 1 0 .3 6
-1 4 .1 1 1 .2
•6 .5 1 0 .6
2 2 1 0 .3
•6.3 a Iff4
4.5
•127
•235
•0.07
(Forw udBiu)
I797AAT
(R eveneB iu)
2Q28BAT
B efore ELO
(F orw udB iu)
2028BAT
Before ELO
(R eveneB iu)
Summary of All DBRTD and QWITT Runs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D ev ice
S tru c tu re
D tic r lp tlo n
M BE R un#
P eek
V oltage, Vp A V .V p -V v
Peak
V alley
P e n k -to -
N e g a tiv e
A p p ro x . r.f. P eak
V a lle y
In je c tio n
C u rre n t
D ensity, J p
C u rre n t
D enally, J ,
V a lle y
R e s is ta n c e ,
o u tp u t
C o n d u ctan ce
R a tio ,
R (ohm s)
(k A /cm 2)
PVCR
p o w e r,
P ,p 3 /1 6 A V
E le c tric
F ield , E«
(k V /cm )
(k V /cm )
(Q -cm )**
(k A /c m 1 )
E le c tric
F ield, Ep
o > (dJ/dE )
•A I (tnW )
8/18/6 ELO
AlAs/GsAs
DEM-QWTTT
w lum drift
8/18/6 ELO
AlAc/OiAt
DEM-QWTIT
w 1um drift.
5/18/5 ELO
AlAi/OsAr
DBRTD
5/18/5 ELO
AlAr/OsAs
DBRTD
2028BAT
A fter E L O
(Forw udBiu)
1.1 1 0 .0 5
0 .1 7 1 0 .0 4
2 1 .6 1 0 .6
1 3 .5 1 0 .3
1 .6 1 0 .0 7
-21 x 10-5
0.16
303
••
359
*e
•0.15
•e
2028BAT
A fter ELO
(R eveneB iu)
•6 .7 1 0 .6 7
■ 3.010.62
•1 3 .9 1 0 .4 4
-4 .6 1 0 .1 2
3 .0 1 0 .6
-3.2 x l O 4
3.3
-123
••
•227
*•
•0.09
•»
2245AAT
B efore ELO
(F orw udB iu)
0 .9 3 1 0 .0 2
0 .0 6 1 0 .0 2
1 0 6 .0 1 5 .9
3 0 .9 1 1 .8
3 .4 1 0 .1
•8.3 x 10-7
0.71
184
277
•0.81
2245AAT
B efore ELO
(R eveneB iu)
•0 .8 4 1 0 .0 2
-0.0610.01
-1 0 1 .2 1 5 .6
•2 6 .3 1 1 .5
3 .9 1 0 .1
-7.3 x l O 7
0.63
•163
-255
-0.82
0 .5 3 1 0 .0 3
0 .0 6 1 0 .0 2
3 2 .7 1 2 7
6 .2 1 0 .3
4 .2 1 0 .2
•2 4 x 10"®
0.22
320
420
•0.25
•0 .9 2 1 0 .0 4
-0 .2 0 1 0 .0 2
-47.8 1 3 .2
-1 9 .1 1 1 .2
2 5 0 1 0.1
-7.0 x l O 6
0.86
232
313
-0.35
0 5 4 1 0 .0 1
0 .3110.01
6 2 .0 1 5 .0
1 5 .0 1 1 .0
4 .1 1 0 .1
•6.7 x l O 6
0.66
118
262
•0.33
•0.7810.01
•0 .2 0 1 0 .0 2
•1 1 6 .4 1 6 .4
• 5 6 .3 1 2 0
2 1 1 0 .1
•3.4 x l O 6
0.55
•133
•257
•0.48
6/18/6 A1A«/
G iA c DBRTD 2297AAT
with n+ d oce (Forw udBiu)
to O.W.
6/18/6 A1A«/
GiA« DBRTD 2297AAT
wiUi n e close (R eveneB iu)
to O.W.
4/18/6 ELO
2356AAT
AlAa/QaAs
B efore ELO
(Forw udB iu)
DBRTD
4/18/6 ELO
A lA l/O tA l
DBRTD
2356AAT
B efore E L O
(R eveneB iu)
Summary of All DBRTD and QWITT Runs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
D ev ic e
S tr u c tu r e
D ev ic e
S tru c tu re
D e s c rip tio n
M BE R un*
P eak
V alley
P ea k -to -
N eg a tiv e
A p p ro x . r.T. P eak
V a lle y
In je c tio n
P eak
C u rre n t
C u rre n t
V a lle y
R e s is ta n c e ,
o u tp u t
E le c tric
E le c tric
C o n d u ctan ce
V oltage, Vp A VcVp-Vy
D ensity, J p
D ensity, Jy
R a tio ,
R (ohm s)
p o w e r,
F ield, E p
F ield, E v
O a (dJ/dE)
(k A /c m 2 )
(k A /c m 2 )
PV CR
P ,f= 3/14A V
(k V /cm )
(k V /cm )
(Q -c m ) 'l
*AI (mW)
6/18/6 A lA s/
GsAsBsseline 2429AAT
DBRTD
(Forw udBiu)
0.57 ± 0 .0 2
0.29 ± 0.01
43.1 ± 0.7
9 2 ± 0.1
4.7 ± 0 .1
-8.5 x l O 6
1.2
143
259
-0.29
6/18/6 A lA s/
GaAs Baseline 2429AAT
DBRTD
(R eveneB iu)
•055 ±0.01
-0.29 ±0,01
-42.5 ± 0 .7
-9.0 ± 0 .1
4.7 ± 0 .1
-8.6x 10-6
1.2
-138
-253
-0.29
Summary of All DBRTD and QWITT Runs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
On
Appendix 2
AZ5214E Photolithographic Process
using the HTG System 3 Aligner
The exposure times given below are highly dependent on the intensity of the
UV lamp and the wavelengths that are filtered by two dielectric mirrors. From the
most recent lamp and mirror change (10/21/91), the following intensities were
measured over a 4 inch by 4 inch exposure area. On the above date, a damaged midUV dielectric mirror (part # 70-000-755-0003) was replaced by a 365-405 nm
dielectric minor (part # 70-000-726-0000) which significandy increased the intensity
of the system at 405 nm. The measured intensities, using an HTG Model 100 optical
powermeter, over the exposure area with the new 365-405 nm dielectric mirror are
given below:
C/I Mode
4.94
5.00
5.40
4.78
4.86
5.30
5.10
5.15
5.60
Intensity of the HTG System 3 within a 4 inch by 4 inch exposure area in units of
mW/cm2.
140
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
141
The "intensity/power" meter on the power supply has been calibrated to the external
power supply meter. The x,y, and z alignments have already been adjusted, with the
following intensities and powers measured:
CP Mode: Intensity = 4.46 mW/cm2, Power = 265 Watts
Cl Mode: Intensity = 4.80 mW/cm2, Power = 290 Watts
I. IMAGE REVERSAL PATTERNING
1. Spin on primer @ 4000 rpm for 30 sec.
2. Spin on 5214E (3) 4000 rpm for 30 sec.
3. Prebake for 70 seconds @ 90°C (on hot metal block in a Blue M bake oven.)
4. Imagewise expose for 21 seconds.
5. Image reversal bake for 70 seconds @ 105°C (on a hot metal block in the
Blue M bake oven.) or at 120*C for 35 seconds.
6. Flood expose for 55 seconds.
7. Develop with AZ 425 MIF developer using slow agitation for 30 seconds.
Do not develop for one minute or you may get Saran wrap.
II.
NORMAL POSITIVE PATTERN
1.
2.
3.
4.
5.
Spin on primer @ 4000 rpm for 30 sec.
Spin on 5214E @ 4000 rpm for 30 sec.
Prebake for 60 to 90 seconds @ 90°C (on hot metal block in the oven.)
Pattern expose for 17 to 23 seconds.
Develop with AZ 425 MIF developer for 1 minute.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Appendix 3
General Epitaxial Lift Off Procedure
L Considerations during epitaxial growth of layer structures for device.
A. Device structures with conductive substrates
1. Insert a n+ AlAs release layer (= 100A - 500A) between n+ GaAs
substrate/buffer layer and the active device layer structure. For p+ GaAs
substrates/buffer layers, insert a p+ AlAs release layer (=100A - 500A).
Doping of the AlAs release layer will allow device testing before epitaxial lift
off. Typical growth temperatures for this layer are above 630°C.
2. If the device structure will be mesa isolated, a fairly thick GaAs buffer
layer (at least 2500A) should be grown on top of the AlAs release layer to take
into account variations in etch rates.
B. Device structure with semi-insulating substrates
1. Usually, the AlAs release layers are grown undoped.
H. Sample preparation for already processed ELO device structures. (See Figure 3.2)
A. Clean sample with acetone, ethanol, and DI-H2 O.
B. Perform O2 plasma descum, 1/2 power for 1 minute.
C. Application of Apiezon W black wax to sample.
1. Apiezon W black wax that has been softened by mixing with TCA.
a) Apply wax with dental tool and press wax with teflon press.
b) Slowly bake sample and wax in oven at 85°C for 20 minutes. Raise
temperature to 120°C and bake for 3 minutes. Wax should be dome-like in
shape with a height of £ 0.25 cm of the base of the substrate.(See Fig. 3.4)
2. Apiezon W black wax that is softened by raised temperature.
a) Place Apiezon W wax on sample and heat sample/wax combination on a
hot plate set at 90°C using a surface thermometer or an oven set at 125° for
3 minutes.
b) Remove sample from source of heat and before completely cooling
press wax with a teflon press. Wax should be dome-like in shape with a
height of < 0.25 cm of the base of the substrate. (See Figure 3.4)
142
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
143
D. Make sure that wax covers the mesa isolated structures which contain
AlGaAs layers in their active device structures.
E. Expose the AlAs release layer at all edges of the sample.
1. Cleave substrate up to the edge of the black wax carrier.
2. Remove any indium that may be on the edges of the sample.
F. Attach HF resistant teflon or wire to black wax carrier for suspension in 10%
HF etchant Otherwise sample is ready to be inserted into etchant
m . Etching out AlAs release layer
A. Pour 10% HF etchant. 4.5:1 DI-H20:HF, The HF used usually comes as a
standard 50% HF mix. Make sure a Nalgene HF resistant beaker is used and not
a Pyrex glass beaker.
B. Cool 10% HF etchant to = 0°C. Although use of a refrigerator or freezer
seems tempting, they should not be used due to the lack of fume handling
capabilities and the endangerment of others. A useful alternative is "blue" ice
and a small cooler which can be placed in a fume hood. With the lid just barely
cracked open, the etchant is kept for as long as 12 hours. The AlAs etch rates
may vary 50 |lm/min to 60 |im/min.
IV. Removing sample from 10% HF etch after complete separation from substrate
A. Dilute 10% HF etchant by gently flowing DI-H2 O into beaker. Dilution will
sometimes help free the ELO film from the substrate if it has not already
separated from the substrate. Make sure that the sample does not strike the edges
of the beaker. If the sample is suspended, it is easier to control the sample.
Wear appropriate acid resistant gloves, face shield, and lab coat.
1. Place beaker into a large Nalgene HF resistant tray and allow etchant to
overflow into tray. Once the HF etchant has been completely diluted (<
0.01% HF), it can be poured down an acid drain.
2. Do not take the ELO sample out of the DI-H2 O environment to prevent
particulate contamination of the bare epitaxial film.
B. Have a clean surrogate substrate already at hand for immediate bonding. See
Chapter 3, section 3.8
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
144
1. The surrogate substrate should have gone through an O2 plasma.
C. Hook up vacuum pen and vacuum bag for sample transfer and bonding.
1. For bonding under DI-H2 O, water traps and two vacuum lines are
required as shown in the figure below. VDW and metal/alloy bonds are
usually performed in a DI-H2 O environment.
Tygon tubing
Vacuum bt
Vacuum pen
ELO sample
Surrogate substrate
Large acid resistant tray
containing DI-H2O
Water traps hooked up
to vacuum lines
2. Adhesive bonds do not require a DI-H2 O environment
3. Apply vacuum pressure and temperature to samples. See Chp. 3.
V. Bonds to alternative substrates.
A. See Chapter 3, sections 3.6 and 3.7 and Chapter 6, sections 6.2, 6.3, and
6.4.
VI. Remove Apiezon W black wax with TCA. Rinse with acetone, ethanol, and DIh 2o .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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E. Yablonovitch, T. Sands, D.M. Hwang, I. Schnitzer, T.J. Gmitter,
S.K. Shastiy, D.S. Hill, and J.C.C. Fan, "Van der Waals bonding of
GaAs on Pd leads to a permanent, solid-phase-topotaxial, metallurgical
bond," Appl. Phys. L ett., Vol. 59, No. 24, pp. 3159-3161, 1991.
YiC89
A. Yi-Yan, W.K. Chan, T J. Gmitter, L.T. Florez, J.L. Jackel,
E.Yablonovitch, R. Bhat, and J.P. Harbison, "Grafted GaAs Detectors
on Lithium Niobate and Glass Optical Waveguides," IEEE Photonics
Technology Letters, Vol. 1, No. 11, pp. 379-380, 1989.
YiC90
A. Yi-Yan, W.K. Chan, C.K. Nguyen, T.J. Gmitter, R. Bhat, JJL.
Jackel, "GalnAs/InP pin Photodetectors Integrated with Glass
Waveguides," Electronics Letters, Vol. 27, No. 1, pp. 87-89,1990.
YoD91
G.W. Yoffe and J.M. Dell, "Multiple-Quantum-Well Reflection
Modulator using a Lifted-Off GaAs/AlGaAs Film Bonded to Gold on
Silicon," Electronics Letters, Vol. 27, No. 7, pp. 557-558,1991.
YoF91
G.W. Yoffe, "High-Efficiency Reflection Modulators using Lifted-Off
GaAs/AlGaAs Layers Bonded to Gold on Silicon," Electronics Letters,
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Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
150
Chapter 4
B1S91
T.R. Block and B.G. Streetman, "Correlation between the dampening of
RHEED oscillations and the photoluminescence of quantum wells in die
presence of AsO," J. Crystal Growth, Vol. I l l , pp. 98-104, 1991.
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N. Braslau, J.B. Gunn and J.L. Staples, "Metal-Semiconductor Contacts
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BrP87
R.A. Bruce and G.R. Piercy, "An Improved Au-Ge-Ni Ohmic Contact to
n-Type GaAs," Solid-State Electronics, Vol. 30, No. 7, pp. 729-737,
1987.
BrS91
E.R. Brown, J.R. Soderstrom, C.D. Parker, L.J. Mahoney, K.M.
Molvar, and T.C. McGill, "Oscillations up to 712 GHz in InAs/AlSb
resonant tunneling diodes," Appl. Phys. Lett, Vol. 58, No. 20, pp. 22912293, 1991.
CaK85
F. Capasso and R.A. Kiehl, "Resonant tunneling transistor with quantum
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L.L. Chang, L. Esaki, and R. Tsu,"Resonant Tunneling in
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ChL91
S.J. Chua, S.H. Lee, R. Gopalakrishnan, K.L. Tan, and T.C. Chong,
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ChV89 * F. Chevoir and B. Vinter, "Calculation of Phonon-assisted tunneling and
valley current in a double barrier diode," Appl. Phys. Lett, Vol. 55, No.
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CoS67
R.H. Cox and H. Struck, "Ohmic Contacts for GaAs Devices," SolidState Electronics, Vol. 10, pp. 1213-1218, 1967.
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L. Esaki, "New Phenomenon in Narrow Germanium p-n Junctions,"
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V.J. Goldman, D.C. Tsui, and J. E. Cunningham, "Breakdown of
Coherence in Resonant Tunneling Through Double-Barrier
Heterostructures," Solid-State Electronics, Vol. 31, No. 3/4, pp. 731734, 1988.
Gul91
K.K. Gullapalli, Master's Thesis, The University of Texas at Austin,
1991.
GuM91
K.K. Gullapalli, D.R. Miller, and D.P. Neikirk, "Hybrid Boltzmann
Transport-Schrodinger Equation Model for Quantum Well Injection
Transit (QWITT) Diodes," 1991 International Electron Device Meeting
(EEDM), pp. 511-514, 1991.
GuR89
P. Gueret, C. Rossel, W. Schlup, and H.P. Meier, "Investigations on
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C.I. Huang, K. Ikossi-Anastasiou, M.J. Paulus, C.A. Bozada, C.E.
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AlGaAs/GaAs Double Barrier Diodes with High Peak-to-Valley Current
Ratios," 1987 IEEE Cornell High Speed Device Conference, pp. 356364, 1987.
KeN87
V.P. Kesan, D.P. Neikirk, B.G. Streetman, and P.A. Blakely, "A New
Transit Time Device using Quantum Well Injection," IEEE Electron
Device Lett., Vol. EDL-8 , pp. 129-131,1987.
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152
KeN88
V.P. Kesan, D.P. Neikirk, P.A. Blakely, B.G. Streetman, and T.D.
Linton, "The Influence of Transit-Time Effects on the Optimum Design
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1987.
MU90
D.R. Miller, private communication, 1990.
Mil91
D.R. Miller, private communication, 1991.
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153
Mil93
D. Miller, PhD Dissertation, The University of Texas at Austin, 1993.
MiN91
D.R. Miller and D.P. Neikirk, "Simulation of intervalley mixing in
double-barrier diodes using the lattice Wigner function," Appl. Phys.
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MiT89
H. Mizuta, T. Tanoue, and S. Takahashi, "Theoretical Analysis of Peakto-Valley Ratio Degradation Caused by Scattering Processes in MultiBarrier Resonant Tunneling Diodes," 1989 IEEE Cornell High Speed
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A. Piotrowska, A. Guivarc’h, and G. Pelous, "Ohmic Contacts to DI-V
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ReF89
M.A. Reed, W.R. Frensley, R J. Matyi, J.N. Randall, and A.C.
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ReT90A
V.K. Reddy, A.J. Tsao, S. Javalagi, G.K. Kumar, D.R. Miller, and
DJ*. Neikirk, "Quantum Well Injection Transit Time (QWITT) Diode
Oscillators," 15th International Conference on Infrared and Millimeter
Waves, pp. 88-90, 1990.
RhW8 8
E.H. Rhoderick and R.H. Williams, Metal-Semiconductor Contacts. 2nd
Edition, Oxford University Press, 1988.
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B. Ricco and M. Ya. Azbel, "Physics of resonant tunneling. The one­
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SeC8 8
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Resonant-Tunneling Bipolar Transistor Operating at Room Temperature
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and its Application as a Frequency Multiplier," TEF.F. Electron Device
Letters, Vol. 9, No. 10, pp. 533-535, 1988.
SeK92
A.C. Seabaugh, Y.C. Kao, and H.T. Yuan, "Nine-State Resonant
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ShX91
G.D. Shen, D.X. Xu, M. Willander, and G.V. Hansson, "The Origin of
the Temperature Dependence in Resonant Tunneling Transport," 1991
IEEE Cornell High Speed Device Conference, pp. 84-93,1991.
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on the resonant tunneling diode," IEEE Electron Device Lett., Vol. 9, No.
5, pp. 200-201, 1988.
SoG83
T.C.L.G. Sollner, W.D. Goodhue, P.E. Tannenwald, C.D. Parker, and
D.D. Peck, "Resonant Tunneling through Quantum Wells at Frequencies
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TaM8 8
T. Tanoue, H. Mizuta, and S. Takahashi, "A Triple-Well ResonantTunneling Diode for Multiple-Valued Logic Application," IEEE Electron
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O. Vanbesien and D. Lippens, "DC and AC Analysis of High Current
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T. Weil and B. Vinter, "Equivalence between resonant tunneling and
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W0 F 8 I
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Chapter 5
Ada85
S. Adachi, "GaAs, AlAs, and AlxGai-xAs: Material parameters for use in
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A1E88
E.S. Alves, L. Eaves, M. Henini, O.H. Hughes, M.L. Leadbeater, F.W.
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Bide90
G. Brozak, E.A. de Andrada e Silva, L.J. Sham, F. DeRosa, P. Miceli,
S.A. Schwarz, J.P. Harbison, L.T. Florez, and S.J. Allen, Jr.,
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1990).
BrS91
E.R. Brown, J.R. Soderstrom, C.D. Parker, L.J. Mahoney, K.M.
Molvar, and T.C. McGill, "Oscillations up to 712 GHz in InAs/AlSb
resonant tunneling diodes," Appl. Phys. Lett, Vol. 58, No. 20, pp. 22912293, 1991.
ChH90
P. Cheng and J.S. Harris, "Improved design of AlAs/GaAs resonant
tunneling diodes," Appl. Phys. Lett., Vol. 56, No. 17, pp. 1676-1678,
1990.
G0 T8 8
V J. Goldman, D.C. Tsui, and J.E. Cunningham, "Breakdown of
Coherence in Resonant Tunneling Through Double Barrier
Heterostructures," Solid-State Electronics Vol. 31, No. 3/4, pp. 731-734,
1988.
LaA92
D. Landheer, G.C. Aers, and Z.R. Wasilewski, "Effective Mass in the
Barriers of GaAs/ALAs Resonant Tunneling Double Barrier Diodes,"
Superlattices and Microstructures, Vol. 11, No. 1, pp. 55-59,1992.
LiC8 8
H.C. Liu and D.D. Coon, "Interface-roughness and island effects on
tunneling in quantum wells," J. Appl. Phys., Vol. 64, No. 12, pp. 67856789, 1988.
Liu87
H.C. Liu, "Resonant tunneling through single layer heterostructures,"
Appl. Phys. Lett., Vol. 51, No. 13, pp. 1019-1021, 1987.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
156
ReT90
V.K. Reddy, A J. Tsao, S. Javalagi, G.K. Kumar, D.R. Miller, and
D.P. Neikirk, "Quantum Well Injection Transit Time (QWITT) Diode
Oscillators," 15th International Conference on Infrared and Millimeter
Waves, pp. 88-90, 1990.
ReT90B
V.K. Reddy, AJ . Tsao, and D.P. Neikirk, "High Peak-to-Valley Current
Ratio AlGaAs/AlAs/GaAs Double Barrier Resonant Tunneling Diodes,"
Electronics Letters, Vol. 26, No. 21, pp. 1742-1743,1990.
RiA84
B. Ricco and M. Ya. Azbel, "Physics of resonant tunneling. The one­
dimensional double barrier case," Phys. Rev. B, Vol. 29, No. 4, pp.
1970-1981, 1984.
RoG90
C. Rossel, P. Gueret, and H.P. Meier, "Tunneling through asymmetric
double barrier quantum well heterostructures," J. Appl. Phys., Vol. 67,
No. 2, pp. 900-903, 1990.
ZaG8 8
A. Zaslavsky, V.J. Goldman, D.C. Tsui, and J.E. Cunningham,
"Resonant tunneling and intrinsic bistability in asymmetric double­
barrier heterostructures," Appl. Phys. Lett, Vol. 53, No. 15, pp. 14081410,1988
Chapter 6
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C.A. Balanis, Advanced Engineering Electromagnetics. John Wiley &
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D.J. Colliver, Compound Semiconductor Technology, Artech House,
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HuI87
C.I. Huang, K. Ikossi-Anastasiou, M.J. Paulus, C.A. Bozada, C.E.
Stutz, R.L. Jones, and K. R. Evans, "Temperature Effects on
AlGaAs/GaAs Double Barrier Diodes with High Peak-to-Valley Current
Ratios," 1987 IEEE Cornell High Speed Device Conference, pp. 356364, 1987.
Isl93
Issues specific to the Schottky contacted CPW phase shifter have been
addressed by M. Saiful Islam in his Ph.D. research. The purpose of
presenting the ELO CPW is to show the positive impact that the ELO
method has had on this device structure.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
157
IsT91
M.S. Islam, A J . Tsao, V.K. Reddy, and D.P. Neikirk, "GaAs on Quartz
Coplanar Waveguide Phase Shifter," IEEE Microwave and Guided
Wave Letters, Vol. 1, No. 11, pp. 328-330,1991.
Jav91
S. Javalagi, This mask set was designed by Shiva Javalagi.
KoS92
F. Kobayashi and Y. Sekiguchi, "GaAs Schottky Photodiode Fabricated
on Glass Substrate using Epitaxial Lift-Off Technique," Jpn. J. Appl.
Phys., Pt. 2, Vol. 31, pp. L850-L852, 1992.
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Lakhani, A.A., "The Role of Compound Formation and Heteroepitaxy in Indium-based Ohmic Contacts to GaAs", J. Appl. Phys., Vol.
56, No. 6 , pp. 1888-1891, 1984.
MaZ87
E.D. Marshall, B. Zhang, L.C. Wang, P.F. Jiao, W.X. Chen, T.
Sawada, S.S. Lau, K.L. Kavanagh, T.F. Kuech, "Nonalloyed ohmic
contacts to n-GaAs by solid-phase epitaxy of Ge," J. Appl. Phys., Vol.
62, No. 3, pp. 942-947, 1987.
Mil90
The software program used here was written by D.R. Miller, 1990.
PoA90
I. Pollentier, A. Ackaert, P. De Dobbelaere, L. Buydens, P. Van Daele,
and P. Demeester, "Fabrication of High-radiance LEDs by Epitaxial
Lift-off," SPIE Vol. 1361 Physical Concepts of Materials for Novel
Optoelectronic Device Applications, pp. 1056-1062,1990.
PoB91
L Pollentier, L. Buydens, P. Van Daele, and P. Demeester, "Fabrication
of a GaAs-AlGaAs GRIN-SCH SQW Laser Diode on Silicon by
Epitaxial Lift-Off," IEEE Photonics Technology Letters, Vol. 3, No. 2,
pp. 115-117, 1991.
PoD90
I. Pollentier, P. Demeester, A. Ackaert, L. Buydens, P. Van Daele, and
R. Baets, "Epitaxial Lift-Off GaAs LEDs to Si for Fabrication of Opto­
electronic integrated circuits,", Electronics Letters, VoL 26, No. 3, pp.
193-194, 1990.
ScY93
I. Schnitzer, E. Yablonovitch, C. Caneau, and T.J. Gmitter, "Ultrahigh
spontaneous emission quantum efficiency, 99.7% internally and 72%
externally, from AlGaAs/GaAs/AlGaAs double heterostructures," Appl.
Phys. Lett., Vol. 62, No. 2, pp. 131-133, 1993.
ShX91
G.D. Shen, D.X. Xu, M. Willander, and G.V. Hansson, "The Origin of
die Temperature Dependence in Resonant Tunneling Transport," 1991
IEEE Cornell High Speed Device Conference, pp. 84-93,1991.
VaL89
O. Vanbesien and D. Lippens, "DC and AC Analysis of High Current
Double Barrier Structures," Solid-State Electronics, Vol. 32, No. 12, pp.
1533-1537, 1989.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
158
WaL89
L.C. Wang, S.S. Lau, E.K. Hsieh, and J.R. Velebir, "Low-resistance
nonspiking ohmic contact for AlGaAs/GaAs high electron mobility
transistors using the Ge/Pd scheme," Appl. Phys. Lett., Vol. 54, No. 26,
pp. 2677-2679, 1989.
YaS91
E. Yablonovitch, T. Sands, D.M. Hwang, I. Schnitzer, T J. Gmitter,
S.K. Shastry, D.S. Hill, and J.C.C. Fan, "Van der Wails bonding of
GaAs on Pd leads to a permanent, solid-phase-topotaxial, metallurgical
bond," Appl. Phys. L e t t , Vol. 59, No. 24, pp. 3159-3161,1991.
YuW89
L.S. Yu, L.C. Wang, E.D. Marshall, S.S. Lau, and T.F. Kuech, "The
temperature dependence of contact resistivity of the Ge/Pd and the Si/Pd
nonalloyed contact schemes on n-GaAs,” J. Appl. Phys., Vol. 65,
pp.1621, 1989.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
VITA
Alwin James Tsao was bom in Washington D.C., on October 3, 1962, the
son of James Jhy-Yuan Tsao and Vicki I-shien Wei Tsao. After completing his work
at John Foster Dulles High School, Stafford, Texas, in 1981, he entered Texas A&M
University in College Station, Texas. He received the degree of Bachelor of Science
in Electrical Engineering from Texas A&M University in May, 1985. From 1985 to
1988 he was employed as a Process Development Engineer at Advanced Micro
Devices, Austin, Texas. In September, 1985, he entered the Graduate School of The
University of Texas. In December, 1988, he received the Master of Science in
Electrical Engineering from The University of Texas. In September, 1988, he left
Advanced Micro Devices to pursue the Ph.D. in Electrical Engineering on a full-time
basis.
Journal Publications:
“Epitaxial Liftoff of AlAs/GaAs Double Barrier Resonant Tunneling Diodes”, A J .
Tsao, V.K. Reddy, and D.P. Neikirk, Electronics Letters, March 14, 1991, Vol. 27,
No. 6, pg. 484.
“Effect of Barrier Thickness Asymmetries on the Electrical Characteristics of
AlAs/GaAs Double Barrier Resonant Tunneling Diodes”, A.J. Tsao, V.K. Reddy,
D.R. Miller, K.K. Gullapalli, and D.P. Neikirk, J. Vac. Sci. Technol. B 10 (2),
Mar/Apr 1992, pg. 1042.
“High Peak-to-valley Current Ratio AlGaAs/AlAs/GaAs Double Barrier Resonant
Tunneling Diodes”, V.K. Reddy, A.J. Tsao, and D.P. Neikirk, Electronics Letters,
October 14, 1990, Vol. 26, No. 21, pg. 1742.
“GaAs on Quartz Coplanar Waveguide Phase Shifter”, M.S. Islam, A.J. Tsao, V.K.
Reddy, and D.P. Neikirk, Microwave and Guided Wave Letters, November 1991,
Vol. 1, No. 11, pg. 328.
“Interface and Barrier Asymmetries in AlAs/GaAs Double Barrier Resonant
Tunneling Diodes”, A.J. Tsao, V.K. Reddy, K.K. Gullapalli, and D.P. Neikirk, To
be submitted to the Journal of Applied Physics.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Conference Papers:
“Quantum Well Injection Transit Time (QWTTT) Diode Oscillators”, V.K. Reddy,
A.J. Tsao, S. Javalagi, G.K. Kumar, D.R. Miller, and D.P. Neikirk, Fifteenth
International Conference on Infrared and Millimeter Waves, Dec. 10-14,1990, pg.
88.
“Effect of Barrier Asymmetries in AlAs/GaAs Double Barrier Resonant Tunneling
Diodes: Experiment and Numerical Simulation”, A.J. Tsao, K.K. Gullapalli, and
D.P. Neikirk, 11th Annual Joint Symposium on Electronic Materials, Processing,
and Characterization, North Texas Materials Characterization Symposium, June 1&2,
1992.
“Epitaxial Liftoff of GaAs/AlGaAs Thin Film Device Structures for Hybrid
Integration on Silicon and Quartz Substrates”, A.J. Tsao, M.S. Islam, and D.P.
Neilcirk, 11th Annual Joint Symposium on Electronic Materials, Processing, and
Characterization, North Texas Materials Characterization Symposium, June 1&2,
1992.
Awarded Best Student Presentation
“Epitaxial Liftoff of Millimeter Wave Devices for Hybrid Integration on Silicon and
Quartz Substrates”, A J . Tsao, M.S. Islam, and D.P. Neikirk, To be presented at the
17th International Conference on Infrared and Millimeter Waves, Dec. 14-18,1992.
“Observation of Zero-Bias Multi-State Behavior in Selectively Doped Two-Terminal
Quantum Tunneling Devices”, K.K. Gullapalli, A J . Tsao, and D J . Neikirk, To be
presented at the 1992 IEEE International Electron Devices Meeting (IEDM), Dec. 1316, 1992.
Permanent Address: 3139 Amesbury Place, Sugar Land, Texas 77478
This dissertation was typed by the author.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
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