# Design of High Power Wideband Microwave Frequency GaN HEMT Frequency Doublers Using Reflector Networks and Filtering

код для вставкиСкачатьDesign of High Power Wideband Microwave Frequency GaN HEMT Frequency Doublers Using Reflector Networks and Filtering By CLAUDIA WING YIN WONG B.S. (University of California, Davis) 2008 THESIS Submitted in partial satisfaction of the requirements for the degree of MASTERS OF SCIENCE in Electrical and Computer Engineering in the OFFICE OF GRADUATE STUDIES of the UNIVERSITY OF CALIFORNIA DAVIS Approved: ________________________________ Chair: George R. Branner ________________________________ Neville C. Luhmann Jr. ________________________________ Preetham K. Kumar Committee in Charge 2012 i UMI Number: 1519818 All rights reserved INFORMATION TO ALL USERS The quality of this reproduction is dependent upon the quality of the copy submitted. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if material had to be removed, a note will indicate the deletion. UMI 1519818 Published by ProQuest LLC (2012). Copyright in the Dissertation held by the Author. Microform Edition © ProQuest LLC. All rights reserved. This work is protected against unauthorized copying under Title 17, United States Code ProQuest LLC. 789 East Eisenhower Parkway P.O. Box 1346 Ann Arbor, MI 48106 - 1346 UMI Number: 1519818 All rights reserved INFORMATION TO ALL USERS The quality of this reproduction is dependent upon the quality of the copy submitted. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if material had to be removed, a note will indicate the deletion. UMI 1519818 Published by ProQuest LLC (2012). Copyright in the Dissertation held by the Author. Microform Edition © ProQuest LLC. All rights reserved. This work is protected against unauthorized copying under Title 17, United States Code ProQuest LLC. 789 East Eisenhower Parkway P.O. Box 1346 Ann Arbor, MI 48106 - 1346 Abstract This thesis presents the theory, design, and implementation of an active high power (~1 W) microstrip S-band RF/microwave wideband frequency doubler with a fundamental operating frequency of 3.333 GHz using a GaN (gallium nitride) HEMT (high electron mobility transistor) device. A narrowband analysis employing reflector networks is performed resulting in a widebanding theory that utilizes a bandpass filter to wideband the response of a frequency doubler. The studies presented in this thesis are performed with the aid of harmonic balance simulations in ADS (Agilent Advanced Design System) using various idealized and nonidealized non-linear large signal HEMT transistor models to analyze the mechanisms behind harmonic generation with different bias levels and combinations of reflector networks. The results of these studies are then extended to present a widebanding theory in order to optimize the performance of a wideband frequency doubler. A microstrip wideband frequency doubler is then fabricated with an input and output reflector network and has also been presented in [1]. Small signal and large signal measurements are performed to characterize the doubler. For Pavs = 30 dBm, 13.3% bandwidth with a maximum 30.2 dBm of 2fo output power has been achieved. A conversion gain of 0.2 dB, 0.2% poweradded efficiency (PAE), and 4.8% of drain efficiency (DE) has also been achieved at the same input power level. These results show that reflector networks can also be applied in a wideband application and still maintain a high output power. ii Acknowledgements I am most thankful to my parents, Oliver and Sylvia Wong, who have sacrificed a lot to allow me to succeed in my education. I have many thanks to my older sister Olivia Wong who has always supported me even if it meant flying halfway around the world to do it. I would like to thank my major professor, Dr. G. Rick Branner who has given me this opportunity. Without his guidance, support, and occasional movie references this thesis would not have been possible. I would like to thank my research group members and friends, Kelvin Yuk and Swapnil S. Jain who have always been great help, guidance, and a joy to work with. Kelvin as my TA and research colleague has taught me invaluable skills in the lab. In addition, Kelvin’s research in transistor modeling has made this thesis a possibility. This thesis is dedicated to my parents, my sister, Kelvin, Swapnil, and last but not least my professor, G. Rick Branner. iii Table of Contents 1 2 Introduction and Motivation ................................................................................................... 1 1.1 Introduction ...................................................................................................................... 1 1.2 Basic Frequency Multiplier Theory ................................................................................. 2 1.3 Conventional Frequency Multipliers................................................................................ 6 1.4 Frequency Multipliers with Reflector Networks .............................................................. 7 1.5 Multiplier Performance Metrics ....................................................................................... 8 1.6 Design Goal .................................................................................................................... 10 1.7 Design Strategy .............................................................................................................. 10 Large Signal HEMT Models ................................................................................................. 12 2.1 Introduction .................................................................................................................... 12 2.2 Construction of Idealized Piece-wise Linear Models .................................................... 14 2.2.1 Model A .................................................................................................................. 15 2.2.2 Model B .................................................................................................................. 18 2.2.3 Model C .................................................................................................................. 23 2.3 Construction of Idealized Non-linear Models: Yuk Model ........................................... 25 2.3.1 3 Study of Harmonic Generation in Model A.......................................................................... 31 3.1 Harmonic Generation without Reflector Networks ....................................................... 31 3.1.1 Midway Bias ........................................................................................................... 35 3.1.2 Pinch-off Bias ......................................................................................................... 47 3.1.3 Forward Conduction Bias ....................................................................................... 59 3.1.4 Summary of Results for Multiplier without Reflector Networks ........................... 68 3.2 Harmonic Generation using Input Reflector Networks.................................................. 69 3.2.1 3.3 Harmonic Generation using 2fo Input Reflector Network ...................................... 70 Harmonic Generation using Output Reflector Networks ............................................... 74 3.3.1 4 Yuk GaN Model ...................................................................................................... 25 Harmonic Generation using an fo Output Reflector Network ................................. 76 Study of Harmonic Generation in Model B .......................................................................... 79 4.1 Harmonic Generation without Reflector Networks ....................................................... 79 4.1.1 4.2 Pinch-off Bias ......................................................................................................... 79 Harmonic Generation using Input Reflector Networks.................................................. 87 4.2.1 Harmonic Generation using 2fo Input Reflector Network ..................................... 87 iv 4.3 Harmonic Generation using Output Reflector Networks ............................................... 89 4.3.1 4.4 5 6 Harmonic Generation using fo Output Reflector Network ..................................... 89 Harmonic Generation using Input and Output Networks............................................... 92 Wideband Multiplier Design................................................................................................. 98 5.1 Introduction .................................................................................................................... 98 5.2 Wideband Doubler Design Theory ................................................................................ 98 5.2.1 Bias Point ................................................................................................................ 98 5.2.2 Circuit Topology ..................................................................................................... 99 Wideband Multiplier Design and Results ........................................................................... 116 6.1 Practical Wideband Doubler Design ............................................................................ 117 6.2 GaN Broadband Doubler Results ................................................................................. 145 6.3 Comparison with Narrowband Doubler Results .......................................................... 158 6.4 Summary of Frequency Multiplier Performance ......................................................... 160 7 Conclusion .......................................................................................................................... 161 8 Appendices .......................................................................................................................... 162 8.1 9 Appendix A .................................................................................................................. 162 References ........................................................................................................................... 172 List of Figures Figure 1-1: Generic Single Ended Active High Power Frequency Multiplier................................ 2 Figure 1-2: Single sided clipped output waveform example .......................................................... 3 Figure 1-3: Double sided clipped output waveform example......................................................... 5 Figure 2-1: Yuk Model Schematic for Cree Inc. CGH40010F 10W RF Power GaN HEMT [6] [1] [7] .................................................................................................................................................. 13 Figure 2-2: Model A Schematic.................................................................................................... 15 Figure 2-3: IDS(A) vs. VGS(V) for Model A .................................................................................. 16 Figure 2-4: IDS(A) vs. VDS(V) for Model A .................................................................................. 16 Figure 2-5: Model A, Ids vs. Vds, Modeled vs. Measured ........................................................... 17 Figure 2-6: Model A, Ids vs. Vgs, Modeled vs. Measured ........................................................... 17 Figure 2-7: Model B Schematic .................................................................................................... 18 Figure 2-8: Model B, Ids vs. Vgs .................................................................................................. 19 Figure 2-9: Model B, Ids vs. Vds .................................................................................................. 20 Figure 2-10: Model B, Ids vs. Vds, Modeled vs. Measured ......................................................... 20 Figure 2-11: Model B, Ids vs. Vgs, Modeled vs. Measured ......................................................... 21 Figure 2-12: Model B, Ids vs. Vgs, Modeled vs. Measured ......................................................... 22 Figure 2-13: Model B, Ids vs. Vgs, Modeled vs. Measured ......................................................... 22 Figure 2-14: Model C Schematic .................................................................................................. 23 Figure 2-15: Model C, Ids vs. Vgs ................................................................................................ 24 Figure 2-16: Model C, Ids vs. Vds ................................................................................................ 24 v Figure 2-17: Yuk Model Schematic for Cree Inc. CGH40010F 10W RF Power GaN HEMT [6] [1] [7] ............................................................................................................................................ 25 Figure 2-18: Yuk Model, Pinchoff Bias, Ids vs. Vds, Modeled (Red) vs. Measured (Blue Dots) 28 Figure 2-19: Yuk Model, Pinch-off Bias, Ids vs. Vgs, Modeled (Red) vs. Measure (Blue Dots) 28 Figure 2-20: Yuk Model, Midway Bias, Ids vs. Vds, Modeled (Red) vs. Measured (Blue Dots) 29 Figure 2-21: Yuk Model, Midway Bias, Ids vs. Vgs, Modeled (Red) vs. Measured (Blue Dots) 30 Figure 3-1: Basic Frequency Multiplier Network without Reflector Networks ........................... 31 Figure 3-2: Model A, Kusher Plot for Midway Bias (Red, Pavs = 6 dBm; Blue, Pavs = 12 dbm; Green, Pavs = 18 dBm) ................................................................................................................. 36 Figure 3-3: Model A, Spectral Plot for Midway Bias, Pavs = 6dbm (Red); Pavs = 12 (Blue); dBm; Pavs = 18 dBm (Green)....................................................................................................... 37 Figure 3-4: Model A, Midway Bias, Pout vs Pavs at fo, 2fo and 3fo ........................................... 40 Figure 3-5: Model A, Midway Bias, Convesion Gain vs. Pavs at fo, 2fo, and 3fo ........................ 41 Figure 3-6: Model A, Midway Bias, Reflected Power vs. Pavs at fo, 2fo, and 3fo...................... 42 Figure 3-7: Model A, Midway Bias, Power at the Gate vs. Pavs at fo, 2fo and 3fo..................... 44 Figure 3-8: Model A, Midway Bias, PAE vs. Pavs at fo ............................................................... 45 Figure 3-9: Model A, Midway Bias, PAE vs. Pavs at 2fo and 3fo................................................. 45 Figure 3-10: Model A, Midway Bias, CDE vs Pavs at fo ............................................................. 46 Figure 3-11: Model A, Midway Bias, CDE vs Pavs at 2fo and 3fo ............................................... 47 Figure 3-12: Model A, Kusher Plot for Pinch-off Bias, Pavs = 6dBm (Red), 12 dBm(Blue), 18 dBm (Green) ................................................................................................................................. 48 Figure 3-13: Model A, Spectral Plot for Pinch-off Bias, Pavs = 6dBm (Red); 12 dBm(Blue); 18 dBm (Green) ................................................................................................................................. 49 Figure 3-14: Model A, Pinch-off Bias, Pout vs Pavs at fo, 2fo, and 3fo ........................................ 51 Figure 3-15: Model A, Pinch-off Bias, Conversion Gain vs. Pavs ............................................... 52 Figure 3-16: Model A, Pinch-off Bias, Reflected Power vs. Pavs at fo, 2fo, 3fo........................... 54 Figure 3-17: Model A, Pinch-off Bias, Power at the Gate vs. Pavs at fo, 2fo, 3fo ........................ 55 Figure 3-18: Model A, Pinch-off Bias, PAE vs Pavs at fo ............................................................ 56 Figure 3-19: Model A, Pinch-off Bias, PAE vs Pavs at 2fo and 3fo ............................................. 57 Figure 3-20: Model A, Pinch-off Bias, CDE vs Pavs at fo ........................................................... 58 Figure 3-21: Model A, Pinch-off Bias, CDE vs Pavs at 2fo and 3fo ............................................. 59 Figure 3-22: Model A, Forward Bias, Kushner Plot Pavs = 6 dBm (Red), 12 dBm (Blue), and 18 dBm (Green) ................................................................................................................................. 60 Figure 3-23: Model A, Forward Bias, Spectral Plot Pavs = 6 dBm (Red), 12 dBm (Blue), and 18 dBm (Green) ................................................................................................................................. 60 Figure 3-24: Model A, Forward Bias, Output Power vs. Pavs at fo, 2fo, 3fo .................................. 62 Figure 3-25: Model A, Forward Bias, Conversion Gain vs. Pavs at fo, 2fo, 3fo ............................. 63 Figure 3-26: Model A, Forward Bias, Reflected Power vs. Pavs at fo, 2fo, 3fo .............................. 64 Figure 3-27: Model A, Forward Bias, Total Power at the Gate vs. Pavs at fo, 2fo, 3fo .................. 65 Figure 3-28: Model A, Forward Bias, PAE vs. Pavs at fo ............................................................ 66 Figure 3-29: Model A, Forward Bias, PAE vs. Pavs at 2fo and 3fo .............................................. 66 Figure 3-30: Model A, Forward Bias, CDE vs. Pavs at fo ............................................................ 67 Figure 3-31: Model A, Forward Bias, CDE vs. Pavs at 2fo and 3fo .............................................. 67 Figure 3-32: Multiplier Circuit diagram with Input Reflector Network ....................................... 70 Figure 3-33: Insertion Loss vs. Frequency of 2fo Lumped Element Reflector Network .............. 71 Figure 3-34: Insertion Phase vs. Frequency of 2fo Lumped Element Reflector Network ............ 72 vi Figure 3-35: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, 2fo Input Reflector ........................................................................................................ 73 Figure 3-36: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, 2fo Input Reflector .................................................................................................................... 74 Figure 3-37: Multiplier Circuit Diagram with fo Output Reflector Network................................ 75 Figure 3-38: Insertion Loss, S(2,1) dB, fo Output Reflector Network .......................................... 76 Figure 3-39: Return Loss, S(1,1) dB, fo Output Reflector Network ............................................. 76 Figure 3-40: Return Loss, S(1,1) dB, fo Output Reflector Network ............................................. 77 Figure 3-41: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, fo Output Reflector........................................................................................................ 77 Figure 3-42: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, fo Output Reflector ................................................................................................................... 78 Figure 4-1: Kushner Plot, Model B, Pinch-off Bias, Pavs = 6 dBm (Red), Pavs = 12 dBm (Blue), Pavs = 18 dBm (Green) .................................................................................................................. 80 Figure 4-2: Spectral Plot, Model B, Pinch-off Bias, Pavs = 6 dBm (Red), Pavs = 12 dBm (Blue), Pavs = 18 dBm (Green) .................................................................................................................. 80 Figure 4-3: Output Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) ................................................................................................ 82 Figure 4-4: Conversion Gain (dB) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) ................................................................................................ 83 Figure 4-5: Reflected Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) ................................................................................................ 84 Figure 4-6: Model B, Pinch-off Bias, CPAE vs. Pavs at fo .......................................................... 85 Figure 4-7: Model B, Pinch-off Bias, CPAE vs. Pavs at 2fo and 3fo ............................................ 85 Figure 4-8: Model B, Pinch-off Bias, CDE vs. Pavs at fo ............................................................. 86 Figure 4-9: Model B, Pinch-off Bias, CDE vs. Pavs at 2fo and 3fo............................................... 87 Figure 4-10: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, 2fo Input Reflector ........................................................................................................ 88 Figure 4-11: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, 2fo Input Reflector .................................................................................................................... 89 Figure 4-12: fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector ................................................................................................................... 90 Figure 4-13: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector ........................................................................................................ 91 Figure 4-14: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector ................................................................................................................... 91 Figure 4-15: Multiplier Circuit Diagram with 2fo Input Reflector Network and fo Output Reflector Network ......................................................................................................................... 92 Figure 4-16: Output Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks ........................................................................................................... 93 Figure 4-17: Conversion Gain (dB) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks ........................................................................................................... 94 Figure 4-18: Conversion PAE (%) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks ........................................................................................................... 96 Figure 4-19: Conversion DE (%) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks ....................................................................................................................... 96 vii Figure 4-20: Output Power (dBm) vs. Frequency (GHz), Model B, Pinch-off Bias with Input and Output Reflector Networks ........................................................................................................... 97 Figure 5-1: Generic Multiplier Circuit Diagram ........................................................................... 99 Figure 5-2: Harmonic Output Power versus Frequency, Model B, Pinch-off Bias, fo Output Reflector ...................................................................................................................................... 101 Figure 5-3: Selected S-parameters of fo Output Reflector Network ........................................... 102 Figure 5-4: Selected S-parameters of N = 3, 20% Bandwidth Butterworth Bandpass Filter ..... 103 Figure 5-5: fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) ........................................................................................................................ 105 Figure 5-6: 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) ........................................................................................................................ 106 Figure 5-7: 2fo Conversion Gain (dB) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) ........................................................................................................................ 106 Figure 5-8: 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) ........................................................................................................................ 107 Figure 5-9: Zoomed in 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) .................................................................................................... 108 Figure 5-10: 2fo Conversion Gain (dB) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) .................................................................................................................. 108 Figure 5-11: Zoomed in 2fo Conversion Gain (dB) vs Phase Line Length (deg), Line Impedance Zo (Ω), and Frequency (GHz) ..................................................................................................... 109 Figure 5-12: Multiplier Circuit Diagram with Output Bandpass Filter, Model B ...................... 109 Figure 5-13: 2fo Output Power (dBm) vs Frequency (GHz)....................................................... 110 Figure 5-14: fo Output Power (dBm) vs Frequency (GHz)......................................................... 111 Figure 5-15: Wideband Doubler Circuit Diagram, Model B ...................................................... 112 Figure 5-16: 2fo Output Power (dBm) vs Frequency (GHz) Comparison .................................. 113 Figure 5-17: fo Output Power (dBm) vs Frequency (GHz) Comparison .................................... 113 Figure 5-18: 2fo CPAE (dBm) vs Frequency (GHz) Comparison .............................................. 114 Figure 5-19: 2fo CDE (dBm) vs Frequency (GHz) Comparison ................................................ 115 Figure 6-1: Idealized Practical Wideband Doubler Circuit Diagram ......................................... 117 Figure 6-2: Comparison Selected S-parameters of M1 network, Model B (red), Yuk Model (blue dotted) ......................................................................................................................................... 119 Figure 6-3: Comparison Selected S-parameters of M2 network, Model B (red), Yuk Model (blue dotted) ......................................................................................................................................... 120 Figure 6-4: Circuit Diagram of Specialized Drain Bias Network............................................... 121 Figure 6-5: Return Loss (dB) and VSWR of Drain Bias Network ............................................. 122 Figure 6-6: Insertion Loss (dB) and DC/AC Isolation (dB) of Drain Bias Network .................. 123 Figure 6-7: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network ................................................................................................. 125 Figure 6-8: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit without Specialized Drain Bias Network ................................................................................................. 125 Figure 6-9: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network ................................................................................................. 127 Figure 6-10: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network .............................................................................................................................. 128 viii Figure 6-11: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub .................................................................................................... 129 Figure 6-12: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub .............................................................................................. 129 Figure 6-13: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub .................................................................................................................... 130 Figure 6-14: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30 and 40 Ω Input Reflector Stub ............................................................................................... 131 Figure 6-15: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30, and 40 Ω Input Reflector Stub ........................................................................................ 132 Figure 6-16: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30, and 40 Ω Input Reflector Stub ........................................................................................................... 132 Figure 6-17: Insertion Loss (dB) vs. Frequency (GHz) 2fo Input Reflector Network with Varying Stub Impedance ........................................................................................................................... 133 Figure 6-18: VSWR vs. Frequency (GHz) 2fo Input Reflector Network with Varying Stub Impedance ................................................................................................................................... 134 Figure 6-19: Pgate (dBm) vs. Frequency (GHz) 2fo Input Reflector Network with Varying 2fo Input Reflector Stub Impedance ................................................................................................. 135 Figure 6-20: Pgate (dBm) vs. Frequency (GHz) 2fo Input Reflector Network with Varying 2fo Input Reflector Stub Impedance ................................................................................................. 135 Figure 6-21: Ideal Transmission line and Microstrip Comparision, Ideal (Red) Microstrip (Blue) ..................................................................................................................................................... 137 Figure 6-22: Ideal Transmission line and Microstrip Comparision, Ideal (Red) Microstrip (Blue) ..................................................................................................................................................... 138 Figure 6-23: Ideal Transmission line and Microstrip Comparision M2 Output Network, Ideal (Red) Microstrip (Blue) .............................................................................................................. 139 Figure 6-24: Ideal Transmission line and Microstrip Comparision M2 Output Network, Ideal (Red) Microstrip (Blue) .............................................................................................................. 140 Figure 6-25: Microstrip Representation of Wideband Frequency Doubler ................................ 141 Figure 6-26: 2fo Output Power (dBm) versus Frequency (GHz), Ideal and Microstrip Comparison ..................................................................................................................................................... 142 Figure 6-27: fo Output Power (dBm) versus Frequency (GHz), Ideal and Microstrip Comparison ..................................................................................................................................................... 143 Figure 6-28: 2fo Conversion Gain (dB) versus Frequency (GHz), Ideal and Microstrip Comparison ................................................................................................................................. 144 Figure 6-29: 2fo CPAE (%) versus Frequency (GHz), Ideal and Microstrip Comparison ......... 145 Figure 6-30: Return Loss (dB) vs. Frequency (GHz) of Measured Input Network .................... 146 Figure 6-31: Return Loss Phase (deg) vs. Frequency (GHz) of Measured Input Network ........ 147 Figure 6-32: Insertion Loss (dB) vs. Frequency (GHz) of Measured Input Network ................ 147 Figure 6-33: Insertion Loss Phase (deg) vs. Frequency (GHz) of Measured Input Network ..... 148 Figure 6-34: Input Return Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network....................................................................................................................................... 149 Figure 6-35: Input Return Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network .......................................................................................................................... 149 Figure 6-36: Input VSWR vs. Frequency (GHz) of Measured and Simulated Output Network 150 ix Figure 6-37: Insertion Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network....................................................................................................................................... 151 Figure 6-38: Insertion Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network....................................................................................................................................... 151 Figure 6-39: Output Return Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network....................................................................................................................................... 152 Figure 6-40: Output Return Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network .......................................................................................................................... 152 Figure 6-41: Output VSWR vs. Frequency (GHz) of Measured and Simulated Output Network ..................................................................................................................................................... 153 Figure 6-42: 2fo Output Power (dBm) vs. Frequency (GHz)...................................................... 154 Figure 6-43: 2fo Conversion Gain (dB) vs. Frequency (GHz) .................................................... 155 Figure 6-44: 2fo PAE (%) vs. Frequency (GHz) ......................................................................... 156 Figure 6-45: 2fo Drain Efficiency, η, (%) vs. Frequency (GHz) ................................................ 157 Figure 6-46: Output Power (dBm) versus Pavs ( dBm) ............................................................... 158 Figure 6-47: Output Power (dBm) versus Frequency (GHz) Comparison ................................. 159 Figure 6-48: Output Power (dBm) versus Frequency (GHz) Comparison ................................. 160 Figure 8-1: Ids vs. Vds, Model A ............................................................................................... 162 Figure 8-2: Ids vs. Vgs, Model A ............................................................................................... 163 Figure 8-3: Model A, Midway Bias, Ids vs. Vds with Loadline ................................................. 164 Figure 8-4: Model B, Midway Bias, Ids vs. Vds with Loadline ................................................. 164 Figure 8-5: Model A, Midway Bias, Fundamental PAE vs. Pavs .............................................. 166 Figure 8-6: Model A, Midway Bias, Fundamental Drain Efficiency vs. Pavs ........................... 167 Figure 8-7: Model A, Midway Bias, Corrected Fundamental PAE vs. Pavs.............................. 168 Figure 8-8: Model A, Midway Bias, Corrected Fundamental Drain Efficiency vs. Pavs .......... 168 Figure 8-9: Model A, Midway Bias, Corrected Fundamental PAE vs. Pavs.............................. 170 Figure 8-10: Model A, Midway Bias, Corrected Fundamental Drain Efficiency vs. Pavs ........ 171 x 1 1 Introduction and Motivation 1.1 Introduction Frequency multipliers are mainly used in communication systems where frequency conversion is required. These systems are used in satellite television signals, cellular phone signals, and global positioning service (GPS). Multipliers are generally used to increase the frequency of a signal for transmission where it would be otherwise too costly to create an oscillator at that frequency. The focus of this thesis is to study the design of a single-ended wideband high power active frequency doubler with reflector networks with the aid of Agilent’s Advanced Design System (ADS). The design of this high power multiplier was made possible with the use of Kelvin Yuk’s highly accurate GaN HEMT device model [1]. In order to obtain a generalized understanding of the behavior of the GaN device highly simplified piecewise transistor models will be presented and employed. Reflector networks at different harmonics are known to assist in harmonic generation and efficiency. In addition to utilizing simplified transistor models a study of multipliers using these reflector networks will also be presented. However these networks have a very narrow bandwidth. A theory will also be presented in order to transition the reflector networks from use in a narrowband multiplier to a wideband doubler. Below in Figure 1.1 is the generic single-ended topology for a narrowband frequency multiplier. M1 and M2 are passive matching networks and the source and load are ideal 50 Ohm terminations. 2 † Figure 1-1: Generic Single Ended Active High Power Frequency Multiplier The following section (1.2) will provide motivation towards the use of reflector networks. Section 1.3 will discuss the use of reflector networks in contrast to none. 1.2 Basic Frequency Multiplier Theory It is well known that transistors will output a signal with harmonics when driven with a large enough input signal. The type of output waveform can contain the desired harmonics of the frequency multiplier one wishes to design. In this section, we will discuss both rectified sine wave and square wave transistor output waveforms. The input signal to a potential frequency multiplier can be written as the superposition of a DC signal and sinusoidal excitation as shown below in Equation 1.1. () = + cos( ) (1.1) In Equation 1.1, with reference to Figure 1-1, VGG is the DC gate bias voltage and Vgs is the magnitude of the AC excitation signal. ‡ An example of the output from a transistor excited † In practice VGG is a negative voltage because the transistor used in this thesis is a depletion mode FET device with a negative pinch-off voltage. 3 with this type of signal is shown below in Figure 1-2. Here, the resultant output is seen to be a single sided clipped waveform. Figure 1-2a is a plot of Vgs versus time, Figure 1-2b Ids versus Vgs, and Figure 1-2c Ids versus time. In this figure, Vp is the pinch-off voltage and Ip is the peak drain current of the transistor model as shown. Ids (A) 2.0 2.0 (b) 1.5 1.5 1.0 1.0 Vp 0.5 0.0 -8 Time (s) Ip 0.5 0.0 0 (c) -6 -4 -2 0 1 (a) 0 200 400 600 Time (ps) -2E-10 -4E-10 -6E-10 -8 -6 -4 -2 0 1 Vgs (V) Figure 1-2: Single sided clipped output waveform example With the Vgs waveform as illustrated in Figure 1-2a, the transistor will conduct when Vgs is greater than Vp. In this case, as illustrated in the figure, the conduction angle is defined by 2. ‡ This equation is only valid for a non-conducting gate-source diode. When the gate-source diode conducts, Vgs(t) is no longer purely sinusoidal. 4 This indicates the time for which the transistor is on and operating above the pinch-off voltage Vp. The conduction angle may be calculated by the following expression. = cos−1 � − � (1.2) From Equation 1.2, the Fourier representation of the output drain current waveform can be determined to be [2] [3]: = sin − cos ⎧ 1 − cos ⎪ ⎪ − cos sin 1 − cos ⎨ ⎪ ⎪2 cos sin − sin cos ⎩ (2 − 1)(1 − cos ) = 0⎫ ⎪ ⎪ = 1 ⎬ ⎪ ≥ 2⎪ ⎭ (1.3) An ideal half-rectified sine wave (i.e. 2 = ) will cause many terms in Equation 1.3 to simplify or vanish. Setting 2 = in Equation 1.3 will yield Equation 1.4. ⎧ ⎪ ⎪ = 2 ⎨2 1 ⎪ ⎪ 2 − 1 ⎩0 = 0⎫ ⎪ ⎪ = 1 ⎬ = ( ≠ 0)⎪ ⎪ = ( ≠ 1)⎭ (1.4) As indicated in Equation 1.4, the output drain current waveform will then only have even harmonics in addition to the fundamental. Therefore, in the design of a frequency doubler, a halfrectified sine wave output is most desireable. Conventionally, active frequency doublers will use a transistor that is biased at pinch-off to help create a half-rectified output drain current waveform. 5 Figure 1-3 illustrates an example of a transistor under large signal excitation where the output is a double sided clipped waveform. § This occurs as a result of the input signal driving the gate of the transistor in to forward conduction as illustrated in Figure 1-3a. Figure 1-3a shows the Vgs versus time. Figure 1-3b shows Ids versus Vgs. Figure 1-3c shows Ids versus time. 2 2.0 (b) (c) Ids (A) 1.5 Ip 1.0 1 Vp 0.5 0.0 0 -8 -5.0E-11 -6 -4 -2 0 2 (a) 0 100 200 300 400 500 Time (ps) Time (s) -1.5E-10 -2.5E-10 -3.5E-10 -4.5E-10 -5.5E-10 -8 -6 -4 -2 0 2 Vgs (V) Figure 1-3: Double sided clipped output waveform example The conduction angle is again defined by 2, and indicates the time for which the transistor is turned on and is the same Equation 1.2. § Note that Vgs(t) is not a pure sinusoid and hence the input signal in Equation 1.1 is not valid. 6 The coefficients of the Fourier series of the output drain current waveform can be written as follows [2]: ** = � 2 1 sin() = 0 ≥ 1 � (1.5) An ideal double sided clipped waveform (i.e. a square wave) will have a conduction angle of 2 = . When this conduction angle value is substituted in to Equation 1.5 many of the coefficients are equal to zero. This simplifies and eliminates many of the terms in Ids. The resultant Fourier coefficients are given below in Equation 1.6. ⎧ ⎪2 = 0 ⎨2 1 ⎪ ⎩ = 0 ⎫ ⎪ ( ≠ 0) ⎬ ⎪ ⎭ (1.6) As seen in Equation 1.6, all of the even harmonic terms have disappeared leaving only the fundamental and odd harmonics. Hence, an output drain current waveform that is doublesided clipped is most desirable for an odd harmonic frequency multiplier. In conventional frequency multipliers, the transistor is typically biased at midway (between pinch-off and forward conduction) to obtain a double-sided and symmetrically clipped waveform. In the next section we will discuss conventional frequency multipliers. 1.3 Conventional Frequency Multipliers Frequency multipliers are fed a large signal sinusoidal input at the fundamental frequency (fo) at the input of the transistor in Figure 1-1. As mentioned earlier in section 1.2, the large ** A thorough derivation of the Fourier coefficients for a double-sided clipped waveform are developed in [3] 7 signal non-linear characteristic of the transistor will result in an output that contains power with multiple harmonics (fo, 2fo, 3fo,…). As was numerically demonstrated earlier in Section 1.2, the bias type can affect the types of harmonics that are present in the output of the multiplier. A midway bias will enable the output drain current waveform to have double-sided clipping which is necessary for an odd harmonic output. A pinch-off bias will enable an output drain current waveform that is single sided clipped which is necessary for even harmonic output. Hence, frequency doublers are typically biased at pinch-off, and frequency triplers are typically biased midway. However, ideal and pure waveforms containing only the desired harmonics are typically difficult to achieve because of device limitations and parasitics. This will cause unwanted harmonics being sent to the load of the multiplier. To alleviate this problem previous work done in frequency multipliers use harmonically tuned circuits to short out the unwanted harmonics and to terminate the desired harmonic to the load [4] [5]. 1.4 Frequency Multipliers with Reflector Networks As mentioned in the previous section, unwanted harmonics will arise at the output due to device limitations and parasitics. Conventional multipliers will use a harmonically tuned network to short the unwanted harmonics while allowing the desired harmonic to terminate to load. This results in wasted power that could have gone towards generating the desired harmonic. Reflector networks can be used to send particular undesirable harmonic power back into the transistor for more mixing to create the desired harmonic [5]. At the gate, a large signal will also generate harmonics which are reflected along with fo back to the generator, Vg, in Figure 1-1. An example of this was shown in Figure 1-3, where the Vgs(t) waveform is not a pure sinusoid and contains harmonics. This power can also be used to constructively create more of the desired harmonic at the output. To do this, the input network 8 M1 can re-reflect these signals with a favorable phase shift back into the transistor. As will be shown in this thesis, the input network can also contain a fundamental frequency input matching network. At the output of the transistor, the output network M2 in Figure 1-1 can contain reflectors networks that are tuned to the unwanted harmonics - especially fo. These unwanted harmonics and fo are undesirable at the output. Instead of wasting the power at these harmonics, reflector networks that are tuned to the unwanted harmonics are inserted in to the circuit. These reflectors will reflect those harmonics back into the drain with the proper phase shift to re-mix and create the desired harmonic. The desired harmonic, depending on the type of multipler, can be sent through to an impedance matching network to be terminated in the load RL. 1.5 Multiplier Performance Metrics Frequency multiplier performance can be measured by output power, conversion gain, and efficiency. The output power is generally measured in terms of dBm which is a decibel referenced to a milliwatt of power. In a multiplier, the output power is defined at the nth harmonic (for n > 0). Referring to Figure 1-1, the output power at the nth harmonic is 1 = { }. 2 (1.7) Conversion gain will be defined here as the ratio between the output power at a particular harmonic frequency to the input power at the fundamental frequency. In other words, = where, (1.8) 9 = 2 . 8 (1.9) Pav is the available power at the fundamental frequency. Vg is the peak generator voltage and Rgen is the resistance of the generator as shown in Figure 1-1. The two types of efficiency that will be referred in this thesis are drain efficiency (η) and power added efficiency (PAE). The definitions for these will be similar to the ones for power amplifiers. In the case of a multiplier, we are interested in the harmonic. As has been previously defined in [5], we will instead refer to conversion drain efficiency and conversion PAE (CPAE) [5]. Hence, conversion drain efficiency is, = where, = + (1.10) (1.11) where, = = . (1.12) PGS and PDS are the power at the gate and drain, respectively. VGS, IGS, VDS, IDS are the DC values of Vgs, Igs, Vds, Ids respectively and as indicated in Figure 1-1. †† Finally, the CPAE is defined as, = − (1.13) One may notice that with Pavs in the numerator of Equation 1.14, there exists a possibility for negative values. This will occur when Pavs is larger than the output power at a particular †† Note that a capitalized subscript indicates a DC value whereas a lower case subscript will indicate the AC value. This convention will be used throughout. 10 harmonic. Placing Pavs in the demoninator will eliminate the possibility for negative numbers. However this placement would give less consideration to the input power. Therefore it is important that both ηn (or conversion drain efficiency = CDE) and CPAEn are considered for a true picture of efficiency in a frequency multiplier [5]. In this thesis, the fundamental frequency, fo, is 3.333 GHz. This sets 2fo = 6.666 GHz, and 3fo = 9.999 GHz ≈ 10.00 GHz. 1.6 Design Goal The primary design goal for the frequency multipliers in this thesis is to create a high output power frequency multiplier. The secondary goals are the conversion gain and the efficiency. In the case of the broadband frequency doubler, the goal is to have a wide bandwidth of operation while maintaining a high power level. To achieve these goals, Cree Inc.’s CGH40010F 10W GaN HEMT (High Electron Mobility Transistor) [6] device will be used. This GaN HEMT is commercially available in discrete packages that are capable of handling high powers up to approximately 10W. 1.7 Design Strategy The design of each of the frequency multipliers is performed in Agilent’s Advanced Design System (ADS). Each design step will undergo an increasing level of complexity and realism. We will begin with a transistor model called Model A which yields ideal results. Model B will add a level of complexity in its IV characteristics that will give a better indication the performance level of the multiplier. Model C will add yet another level of complexity, but for reasons later discussed this model will not be used in simulations. Model D, also known as the Yuk Model [5] [1] [7], which has been developed by Kelvin Yuk will yield simulation results which are the best 11 representation of the final circuit performance. The Yuk Model will be used to obtain the final design of the frequency multiplier for fabrication and testing. 12 2 Large Signal HEMT Models 2.1 Introduction To design a high power active microwave frequency multiplier we desire a transistor technology which has the following characteristics: 1. High Breakdown Voltage – to provide more output power 2. High Frequency of Operation – to be able to generate the desired harmonic content 3. High Power Density – to keep the circuit compact The transistor technology that matches these requirements is the GaN HEMT technology. More specifically we will use Cree Inc.’s CGH40010F [6]. Large bandgap and high power density transistors such as the GaN HEMT are subject to self-heating and charge trapping which will degrade the RF and DC performance. An accurate model is required to model the complex electrical behavior of these devices. Hence it is a challenge to create an accurate model that is required for creating an accurate design. For the purposes of the frequency multipliers in this thesis, the desired model must also include accurate harmonic behavior. Fortunately a complex and accurate model has been created by Kelvin Yuk( [1] [7]) This empirical model was created by performing extensive pulsed-gate and pulsed-drain IV measurements. In addition to accurately predicting large signal output, the Yuk model can also predict harmonic behavior and takes into account the self heating and charge trapping effects that are inherent in this technology [1] [7]. The complete model schematic which is shown below in Figure 2-1 has been implemented in ADS. The first step to undertake in designing a high power frequency multiplier is to gain insight and understanding of the behavior of the GaN HEMT under a large signal excitation. A simpler 13 version of the Yuk model will allow us to identify the fundamental mechanisms that drive harmonic generation in these circuits and provide a foundation upon which a final design can be made. In other words, we will begin with the most ideal model characteristics and from there add levels of realism and complexity to achieve a practical design. These models are defined as Models A, B, C, and D. This was previous done for the case of a SiC MESFET in [5]. Model D for a SiC MESFET in [5] was further broken down into a family of models known as D.0, D.1, D.2, D.3 and D.4 as the complete Yuk Model [5]. More specifically, the large-signal models developed in [5] refer to CREE Inc.’s CRF24010 High Power SiC MESFET [8]. In the current thesis, Models A, B, C, and the Yuk Model will be developed for the CGH40010F 10W RF Power GaN HEMT [6] instead of the CRF24010 SiC MESFET explored in [5]. Model D in this thesis will refer to the entire Yuk GaN Model and will be labeled as such. The complete Yuk GaN HEMT model is shown below in Figure 2-1. Figure 2-1: Yuk Model Schematic for Cree Inc. CGH40010F 10W RF Power GaN HEMT [6] [1] [7] 14 2.2 Construction of Idealized Piece-wise Linear Models As has been previously mentioned, Models A, B, and C are simplified versions of the Yuk Model in Figure 2-1 containing a limited number of components from it. The components in these models include Ids (drain-source current source), Dgs (gate-source diode), and Dgd (gatedrain diode) and were realized in ADS using piece-wise linear functions. The defining parameters of these components were obtained based on pulsed-gate-and-drain IV measurement data performed in [1] and [7]. For ease of reference, the parameters for each model are summarized below in Table 2-1 below. Symbol Vp IDSS Vfwd Ron Iss Vki Vfwd G Gb VGBrbd Parameter Description Value -2.5V 1 Model Component Ids Model A Model B Model C Pinch-off Voltage of HEMT Saturation Current of the HEMT Turn-on Voltage of GateSource Diode Turn-on Resistance of GateSource Diode Saturation Current of GateSource Diode Knee Voltage of the HEMT Turn-on Voltage of the GateDrain Diode Turn-on Conductance of the Gate-Drain Diode Reverse Breakdown Conductance of the GateDrain Diode Reverse Breakdown Voltage of the Gate-Drain Diode 2A Ids 0V Dgs 0.01 Ω Dgs 1e-13A Dgs 8V Ids 0V Dgd 100S Dgd 0.1S Dgd -85V Dgd Table 2-1: Models A, B, C Idealized Parameters The following sections will provide a detailed analysis of each model and a comparison with the measured pulsed IV data to assess its validity. 1 In [6] the pinch-off voltage is recorded as -3V. However, up to about -2.5V there is negligible amounts of drain current especially at lower Vds biases. Hence -2.5V will be used as the ideal pinch-off voltage. 15 2.2.1 Model A The schematic for Model A is shown below in Figure 2-2. It consists of a gate-source diode, Dgs and a piece-wise linear current source Ids. Figure 2-2: Model A Schematic The diode, Dgs, in this model is defined in terms of the current flowing through it, Igs and is a function of the given gate-source voltage, Vgs, and ISS, the gate-source diode saturation current. It is defined below in Equation 2.1. � � = � − < ≥ (2.1) The current source, Ids, is defined below in Equation 2.2. 0 � � = � < ≤ ≤ 0 > 0 (2.2) Ids is a function of the gate-source voltage, Vgs. Vfwd in both equations is the turn-on voltage of the gate-source diode. Vp is the pinch-off voltage of the HEMT device. These parameters have also been previous defined in Table 2-1. The static DC curves are shown below in Figure 2-3 and Figure 2-4. Figure 2-3 shows Ids versus Vgs. Figure 2-4 shows Ids versus Vds. Notice that in Figure 2-3 and Figure 2-4, the drainsource current Ids depends only on Vgs and is entirely independent of Vds. 16 2.0 Ids (A) 1.5 1.0 0.5 0.0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Vgs (V) Figure 2-3: IDS(A) vs. VGS(V) for Model A 2.0 Vgs=0.000 Vgs=-0.500 Ids (A) 1.5 Vgs=-1.000 1.0 Vgs=-1.500 0.5 Vgs=-2.000 0.0 Vgs=-2.500 Vgs=-3.000 0 10 20 30 40 50 60 Vds (V) Figure 2-4: IDS(A) vs. VDS(V) for Model A To assess the validity of Model A, we compared the modeled DC curves with measured DC curves below as shown in Figures 2.5 and 2.6. In Table 2-1, Vgs = -2.5V was chosen as the pinch-off voltage for the models. Recall that the actual pinch-off voltage in [6] is actually -3V. A Vgs = -2.5V was chosen because of the negligible amount of Ids present until Vgs = -2.5V. Taking 17 a look at Figure 2-5, the measured data for Vgs = -2.5V has negligible amounts of Ids current especially at lower values of Vds. Therefore, the earlier assumption in Section 2.2 is valid 2. Ideal_0V Vgs=0.000000 Ideal_0125V Vgs=-1.250000 2.0 Ids (A) 1.5 1.0 Ideal_0250V Vgs=-2.500000 Measured_0V Vgs=0.000000 Measured_0125V Vgs=-1.250000 Measured_0250V Vgs=-2.500000 0.5 0.0 0 10 20 30 40 50 60 Vds (V) Figure 2-5: Model A, Ids vs. Vds, Modeled vs. Measured Figure 2-6 below compares the measured and ideal Ids (given in Equation 2.2) versus Vgs given a Vds = 60V. This figure shows the close agreement between the ideal Model A performance and the actual measured data. A Vds = 28V was chosen here because this is the quiescent bias point for VDS that will be used in all of the simulations. 2.5 Vds=28.000000 Ids (A) 2.0 Ideal 1.5 Measured_28V 1.0 0.5 0.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 Vgs (V) Figure 2-6: Model A, Ids vs. Vgs, Modeled vs. Measured 2 The assumption in Section 2.2, repeated here, was that the pinch-off voltage was selected to be -2.5V instead of 3V because of the negligible amount of drain current until -2.5V. 18 2.2.2 Model B The circuit diagram for Model B is shown below in Figure 2-7. Figure 2-7: Model B Schematic Note that the schematics for Models A and B are exactly the same and the diode. Furthermore, Dgs is still defined as it was in Equation 2.1.The difference here now is that the drain-source current, Ids is now a function of Vds and Vgs as shown in Equation 2.3 below. This will effectively add a “knee” into the IV characteristics of the model as shown in Figure 2-9. 0 ⎧ ⎪ �1 − � � � � , � = ⎨ ⎪ �1 − � ⎩ ≥ ; ≥ ; < 0 ≤ ≤ (2.3) > The model parameters in Equation 2.3, Vp, IDSS, Vfwd, and Vki, have been previously defined in Table 2-1. Equation 2.3 shows that for Vds between 0 and Vki, the drain current will follow a linear relationship dependent on Vds. In comparison, for values of Vds greater than Vki the Ids will be a constant flat value and independent of Vds. Figure 2-8 shows the Ids versus Vgs curve. As mentioned earlier in Equation 2.3, Ids is now a function of both Vgs and Vds. This is due to the fact that there are now different Ids 19 currents for different Vds. Previously in Model A, there was only one current value with respect to Vgs and regardless of what Vds is 3. 5 Vds=8.000 Ids (A) 4 Vds=7.000 Vds=6.000 3 Vds=5.000 Vds=4.000 2 Vds=3.000 Vds=2.000 1 Vds=1.000 0 Vds=0.000 -4 -3 -2 -1 0 1 2 3 Vgs (V) Figure 2-8: Model B, Ids vs. Vgs Figure 2-9 below shows the Ids versus Vds curves for different levels of Vgs as shown. The different from Model A is that now there is a knee in the IV characteristics that will add a level of complexity for the design analysis. 3 Figure 2-3: IDS(A) vs. VGS(V) for Model A can also be thought of as having all the Ids curves placed on top of each other for all values of Vds . 20 5 Vgs=3.000 Ids (A) 4 Vgs=2.000 3 Vgs=1.000 2 Vgs=0.000 1 Vgs=-1.000 Vgs=-2.000 Vgs=-3.000 0 0 25 50 75 100 Vds (V) Figure 2-9: Model B, Ids vs. Vds Now we will compare the Model B performance against the measured performance of the GaN HEMT. Figure 2-10 below compares Ids versus Vds. 2.0 Ids (A) 1.5 1.0 0.5 Ideal_000V Vgs=0.000000 Ideal_0125V Vgs=-1.250000 Ideal_0250V Vgs=-2.500000 Measured_0000V Vgs=0.000000 Measured_0125V Vgs=-1.250000 Measured_0250V Vgs=-2.500000 0.0 0 10 20 30 40 50 60 Vds (V) Figure 2-10: Model B, Ids vs. Vds, Modeled vs. Measured 21 Now, for the sake of clarity, we will compare Ids versus Vgs in two plots in Figure 2-11 and Figure 2-12 4. Figure 2-11 compares the Ids versus Vgs of Model B to the measured data of the GaN HEMT for Vds = 1V and 3V, respectively. Notice that in Figure 2-11 the measured and modeled curves do not agree as closely as they do in Figures 2-6 or 2-12. This is due to the region of operation for the particular Vds shown in the figures Model B has very clearly defined regions of operation as shown in Figure 2-9 (i.e. there is an abrupt change between linear and saturation regions of operation). However in the actual GaN device these boundaries are not as clear and are therefore difficult to model [1] [7]. As will be shown later, the Yuk Model will provide a much better approximation for the Ids versus Vgs curves. 1.5 Ids (A) 1.0 0.5 0.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 Ideal1 Vds=1.000000 Ideal2 Vds=3.000000 Measured1 Vds=1.000000 Measured2 Vds=3.000000 0.0 Vgs (V) Figure 2-11: Model B, Ids vs. Vgs, Modeled vs. Measured Figure 2-12 compares Ids versus Vgs of Model B to the measured GaN HEMT for Vds = 6V and 7V, respectively. We now see that there is a closer agreement between the measured and modeled data. This is due to the same reasons that we have just discussed. At a higher Vds the 4 If Figures 2-11 and 2-12 were on one plot it would be too confusing to interpret. Thus the one plot has been separated into two. 22 region of operation is better defined and so the measured and simulated results will agree more closely. In the case of Figure 2-12, we are in the linear region of operation. 2.0 Ids (A) 1.5 1.0 0.5 Ideal3 Vds=6.000000 Ideal4 Vds=7.000000 Measured3 Vds=6.000000 Measured4 Vds=7.000000 0.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Vgs (V) Figure 2-12: Model B, Ids vs. Vgs, Modeled vs. Measured In Figure 2-13 below, is a comparison between the measured and Model B for Vds = 28V and 29V. We see almost no differentiation between the measured and simulated. This is because are well in to the saturation region of operation as illustrated in Figure 2-9 and Figure 2-10. Vds = 28V will also be the bias for the subsequent circuit designs. 2.0 Ids (A) 1.5 1.0 0.5 Ideal5 Vds=28.000000 Ideal6 Vds=29.000000 Measured5 Vds=28.000000 Measured6 Vds=29.000000 0.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Vgs (V) Figure 2-13: Model B, Ids vs. Vgs, Modeled vs. Measured 23 2.2.3 Model C The circuit diagram for Model C is shown in Figure 2-14 below. Figure 2-14: Model C Schematic Ids and Dgs are still defined the same way as in Model B. The difference now is that Model C has a new diode, Dgd across the gate and the drain as shown in Figure 2-14. Dgd can be described in Equation 2.4 below. The purpose of Dgd is to add the reverse breakdown characteristic in the IV curves. The model parameters have been previously defined in Table 2-1. � − � < ≤ ≤ � � = � 0 � − � > (2.4) The following figures, Figure 2-15 and Figure 2-16 both illustrate the static DC curves of Model C. As one can see in Figure 2-15 there is now a reverse breakdown current in the IV characteristics. 24 3 2 Ids (A) Vds=8.000 Vds=7.000 Vds=6.000 Vds=5.000 Vds=4.000 Vds=3.000 Vds=2.000 Vds=1.000 1 0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Vgs (V) Figure 2-15: Model C, Ids vs. Vgs 3 Vgs=-1.000 Vgs=-2.000 Ids (A) 2 Vgs=-3.000 1 0 0 20 40 60 80 100 Vds (V) Figure 2-16: Model C, Ids vs. Vds It should be noted that the information for the breakdown voltage was obtained from the manufacturer’s data sheet [6]. This was done because the instruments necessary to measure the reverse breakdown voltage were not available. As such, Model C cannot be compared with 25 measured data. It also means that we will not be exploring Model C any further due to the impractical nature of measuring such a design. 2.3 Construction of Idealized Non-linear Models: Yuk Model We will now discuss the Yuk model for the GaN HEMT device. In [5], the SiC model was also known as Model D with five different versions ranging from D.0 to D.4. Each model introduced added levels of complexity and realism up through D.4 which was also called the full Yuk Model [5]. In this thesis, we will only refer to the full Yuk Model for the GaN HEMT device. 2.3.1 Yuk GaN Model The Yuk model schematic is shown below in Figure 2-17. Figure 2-17: Yuk Model Schematic for Cree Inc. CGH40010F 10W RF Power GaN HEMT [6] [1] [7] In Figure 2-17, the drain current source Ids is non-linear and is defined by equations described in [1] and [7]. The Yuk model also models charge-trapping and self heating effects. Cgs, Cds, and Cgd are bias dependent non-linear capacitances. Dgs and Dgd are non-linear diodes. The linear elements Rs, Lg, Rd, Ld, Rgs, Cpgd, Rs, and Ls are linear and are determined 26 by the device packaging. The thermal subcircuit defined by Pdiss, Rth, Cth, and T0 models the selfheating behavior of the transistor [1] [7]. The Yuk Model was developed in [1] and [7] by using pulsed-gate IV (PGIV) and pulsed-gate-pulsed-drain IV (PIV) measurements. Both types of measurements were performed because of the power limitations of available PIV systems [7]. In addition, the GaN HEMTs are subject to self-heating and charge trapping effects. If the GaN HEMTs were measured using conventional long pulse IV measurements, the heating in the device will cause the IV curves to deviate from what they would look like under RF drive. In addition, the long pulses will cause charge traps in the surface and substrate to behave differently than when under RF drive. PGIV measurements were performed to model the self-heating effects on the gm and Ids of the device. However, a limitation of PGIV measurements is that it does not differentiate between the effects of self-heating and charge trapping. It also does not provide accurate predictions of drain-source transconductance, gds, at RF frequencies which, for this thesis, are relevant. It therefore becomes necessary to use both PIV and PGIV measurements to better predict large signal RF behavior [7]. Here we will only focus on the PGIV measurements. As will be shown, the IV characteristics are now dependent on the quiescent bias. In Models A, B, and C, the drain current was defined by a series of piecewise functions. However in the Yuk Model, the drain current is now a non-linear continuous function which means that there are no distinct boundaries between different regions of operation. For example in Models A, B, and C, the pinch-off bias was defined for a gate voltage Vgs = -2.5V. While [6] indicates that pinch-off is actually at Vgs = -3.0V no appreciable voltage was found until Vgs = 2.5V. However, to ensure that we are in the pinch-off region for the more realistic Yuk model, 27 Vgs = -3.0V. Now the midway bias for the Yuk Model will be Vgs = -1.5V. For forward conduction bias in Model B, the forward bias voltage was at 0V. But because we now have a practical diode on the drain, a more proper voltage drop would be 0.7V for forward conduction bias. The bias points for the Yuk Model are summarized below in Table 2-2. Gate Bias Pinch-off Midway Forward Conduction Bias Voltage (V) -3.0 -1.5 0.7 Table 2-2: Yuk Model Bias Convetion Using ADS, a comparison of the pulsed gate IV characteristics between the simulated Yuk Model and the measured GaN HEMT are shown below. Figure 2-18 and Figure 2-19 show the IV characteristics for a quiescent pinch-off bias of Vgsq = -3.0V and Vdsq = 28V as has been previously defined in Table 2-2: Yuk Model Bias Convetion. In both of these figures, Vgs is swept from -3.0V to 0.0V and Vds is swept form 0.0V to 50V. In Figure 2-19 Vds only goes up to 10V for the sake of clarity. Similar results have also been presented in [1] and [7]. 28 2.0 Ids (A) 1.5 1.0 0.5 0.0 0 10 20 30 40 50 Vds (V) Figure 2-18: Yuk Model, Pinchoff Bias, Ids vs. Vds, Modeled (Red) vs. Measured (Blue Dots) 2.0 Ids (A) 1.5 1.0 0.5 0.0 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 Vgs (V) Figure 2-19: Yuk Model, Pinch-off Bias, Ids vs. Vgs, Modeled (Red) vs. Measure (Blue Dots) 0.0 29 Figure 2-20 and Figure 2-21 below are for an approximate midway bias where Vgsq = -1.7V and Vdsq = 28V. In both figures, Vgs is swept from -3.0V to 0.0V and Vds is swept from 0.0V to 50V. In Figure 2-21, Vds is only swept to 10V for the sake of clarity. Similar results have also been presented in [1] and [7]. 2.5 Ids (A) 2.0 1.5 1.0 0.5 0.0 0 10 20 30 40 Vds (V) Figure 2-20: Yuk Model, Midway Bias, Ids vs. Vds, Modeled (Red) vs. Measured (Blue Dots) 50 30 2.0 Ids (A) 1.5 1.0 0.5 0.0 -0.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 Vgs (V) Figure 2-21: Yuk Model, Midway Bias, Ids vs. Vgs, Modeled (Red) vs. Measured (Blue Dots) The following chapters will present the results of harmonic generation simulations on Models A and B at different bias points. 31 3 Study of Harmonic Generation in Model A This chapter will cover the frequency multiplier performance of Model A at pinchoff, midway, and forward bias with different types of passive reflector networks. As the reader may recall, Model A was defined in Section 2.2.1 with the parameters defined in Table 2-1. It is an ideal piecewise linear model whose current Ids is dependent on Vgs but is independent of Vds. This makes the load resistor RL in Figure 1-1 the sole controlling factor in the output power relationship between Vds and Ids. 3.1 Harmonic Generation without Reflector Networks In this section we will discuss harmonic generation of Model A without the aid of reflector networks. The concept of a reflector network has been previous discussed in Section 1.4. This will help to determine the appropriate quiescent bias point that will generate the most of the desired harmonic content. The circuit topology without reflector networks is shown below in Figure 3-1. Figure 3-1: Basic Frequency Multiplier Network without Reflector Networks 32 In contrast to Figure 1-1, M1 and M2 do not contain networks that need to be designed since they will only have the bias-T networks. In either one of these bias-T networks, the capacitor C acts as a DC current block that prevents DC from leaking out into the RF generator or the load RL. At the same time, it will allow any RF or AC signal to pass through to the transistor model. The inductor, L, does the opposite and protects the DC sources VGG and VDD from any AC current. As mentioned earlier, the primary reason for studying a multiplier network without reflectors is to understand which quiescent bias point would output the most amount of harmonic content. The pinchoff voltage Vgsq = -2.5V 10 has been previously determined in Section 2.2 and is also listed in Table 2-1. This subsequently sets the midpoint bias voltage Vgsq = -1.25V and forward bias voltage Vgsq = 0V. For the maximum output power we must choose Vdsq such that we maximize the voltage and current swing at the drain. One would believe that Vdsq should therefore lie between the knee voltage, Vki (= 8V) and the breakdown voltage, Vrbd (= 85V). 11 However, clipping of these waveforms may result in more harmonics. Therefore we will choose Vdsq such that it is lower than the midway point between Vki and Vrbd ( ( Vki+Vrbd)/2 = 46.5V which represents the midpoint) in order to take advantage of clipping that occurs at the knee. In [1] and [7], Vdsq = 28V was used. Vdsq = 28V will be used for these simulations because it is less than 46.5V and it is consistent with [1] and [7]. One may notice the DC matching resistors Rgg and Rdd in Figure 3-1 on the respective gate and drain biases. As shown above in Figure 3-1, Rgg is set to be 50 Ohms. The purpose of this resistor is to prevent shifting of the gate voltage waveform due to DC-level shifts from the 10 11 Note that Vgsq denotes the quiescent gate bias. In reference to Figure 3-1, this will refer to VGG Reverse breakdown was demonstrated in Model C in Figure 2-16 in Section 2.2.3 33 clipping of Vgs(t). Without Rgg, the Vgs(t) waveform will clip prematurely [5]. To determine the value of Rgg we will now take a look at the following equations. First, we know Vgs in Figure 3-1 to be the sum of its AC and DC components. = + = + � − � (3.1) Note that VgsAC can also be defined as, = − (3.2) which we will now substitute back into Equation 3.1. = � − � + � − � = − + � − � + − = − � + � + + � − � (3.3) = − + + � − � = − + � + + � − �� Looking at Equation 3.1, the choice for the value of Rgg is now clear and the reason it is chosen to be 50 Ohms is so that it matches Rgen. This will eliminate the Vgs dependence on the DC gate current, IgsDC [5]. The same can be said of the DC matching resistor on the drain, Rdd. It would serve to prevent the shifting of the drain voltage waveform from DC level shifts in with the clipping of Vds(t). Quantitatively, the analysis is as follows. = + = + � − � (3.4) Only the AC current will reach the terminating load resistor so, = − . Now we insert Equation 3.5 back into Equation 3.4. (3.5) 34 = − + � − � = −( − ) + � − � = − + + − (3.6) = − + � + ( − )� From Equation 3.6 we can see that Vgs has a dependence on IdsDC that can be eliminated by choosing Rdd equal to RL or 50 Ohms [5]. However, as shown in Figure 3-1, the resistor value is left at 0 Ohms. To understand this choice we must take a look at Vds for Rdd = RL = 50 Ohms. From Equation 3.6 and setting RDD = RL we obtain the following equation below. = − + (3.7) From Equation 3.7, it is clear that in order to achieve a particular Vds swing, the Vdsq will have to increase. In other words, the DC drain bias supply would have to increase in contrast to the case where the IdsDC dependence still exists. To avoid the requirement of a high drain bias, we choose Rdd = 0 Ohm and therefore must tolerate the load line shifts [5]. Equation 3.6 can also be rewritten in terms of Ids which will be used later on. = − ⁄ + ⁄ + (3.8) Now the values of both of the biasing resistors have been determined and the simulation set up can proceed. The table below summarizes the different cases and bias points for the following ADS simulations has had been previously mentioned earlier in this section. 35 Case Pinch-off Bias Midway Bias Forward Bias Gate Bias (VGG) Drain Bias (VDD) Pav (dBm) Vgsq= -2.5V Vgsq= -2.5V Vgsq= -2.5V Vgsq= -1.25V Vgsq= - 1.25V Vgsq= - 1.25V Vgsq= 0V Vgsq= 0V Vgsq= 0V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V Vdsq= 28V 6 12 18 6 12 18 6 12 18 AC Input Voltage Mag (Vg) |Vp|/2 |Vp| 2*|Vp| |Vp|/4 |Vp|/2 |Vp| |Vp|/2 |Vp| 2*|Vp| Conduction Angle: 2φ (deg) 180 180 180 360 360 360 180 180 180 Table 3-1: Model A, Input, Bias, and Loading Conditions for Harmonic Study Load RL (Ohm) 50 50 50 50 50 50 50 50 50 Vgsq will be explored at pinch-off, midway, and forward bias cases as indicated in Table 3-1 above. The drain bias, Vdsq will be constant at 28V for the reasons previously explained. For these three bias points, the ADS simulation will sweep the available power (in dBm) to ascertain the harmonic output content for doubler/tripler preformance. Power reflected at the gate will also be studied to better understand how it may be utilized to improve performance with input reflector networks. We will now present results for each of the biases. 3.1.1 Midway Bias The analysis of the results will be done using Kushner plots and spectral plots where the available power has been chosen such that the AC input voltage magnitude is |Vp|/2, |Vp|, and 2*|Vp|. This corresponds to input power levels of 6, 12, and 18 dBm, respectively. Kushner plots show the Vgs, Ids, and Vds waveforms with respect to time. It also shows the loadlines from the simulation. The spectral plots show the harmonic content of Vgs, Ids, and Vds by plotting them with respect to frequency. The results of this analysis have are shown in Figure 3-2 and Figure 3-3 below. 36 Ids, A 2 2.0 (b) 1 -8 -6 -4 -2 0 2 1.5 1.0 1.0 0.5 0.5 100 200 300 400 500 -40 -20 0 20 40 60 80 100 (e) -5.0E-11 -1.5E-10 Time, s -1.5E-10 Time, s (d) 0.0 0 time, psec (a) 2.0 1.5 0.0 0 -5.0E-11 (c) -2.5E-10 -3.5E-10 -2.5E-10 -3.5E-10 -4.5E-10 -4.5E-10 -5.5E-10 -5.5E-10 -8 -6 -4 -2 0 2 -40 -20 0 20 40 60 80 100 Vgs, V Vds, V Figure 3-2: Model A, Kusher Plot for Midway Bias (Red, Pavs = 6 dBm; Blue, Pavs = 12 dbm; Green, Pavs = 18 dBm) 37 1.4 (a) 70 (b) 1.2 60 2.5 1.0 50 2.0 0.8 40 Vds, V 3.0 Ids, A Vgs, V 3.5 1.5 0.6 30 1.0 0.4 20 0.5 0.2 10 0.0 0 0.0 0 2 4 6 freq, GHz 8 10 (c) 0 2 4 6 freq, GHz 8 10 0 2 4 6 8 10 freq, GHz Figure 3-3: Model A, Spectral Plot for Midway Bias, Pavs = 6dbm (Red); Pavs = 12 (Blue); dBm; Pavs = 18 dBm (Green) Vgs(t) Performance In reference to the Vgs(t) plot of Figure 3-2a above, it is clearly shown that Model A has been biased at midway between pinchoff and forward conduction bias. Observing that for a Pavs ≤ 6 dBm (the red curve), Vgs(t) is a pure sinusoidal signal. But once Pavs increases to 12 dBm (blue curve), the Vgs(t) waveform is now being clipped due to the signal hitting the forward conduction region at Vgs = 0V. At Vgs = 0V, the gate-source diode turns on and prevents Vgs(t) from going beyond 0V. As Pavs is increased even further (green curve), the sinusoid is clipped even further. Then Vgs(t) begins to resemble a rectified sine wave with a conduction angle approaching 180 degrees. This is of special interest because this results in a half-rectified sine wave that is rich in even harmonics. The even harmonics can also be seen in the spectral plot of Vgs in Figure 3-3a. 38 Another characteristic of the GaN device that we can see here from Model A is the smaller voltage swing range as defined between Vfwd and Vpinch. Compared to the SiC transistor used in [5], the waveform begins to clip at a much lower Pavs. This means that the GaN transistor can more readily generate harmonic content at a possibly higher efficiency because of the less amount of power required from the source. Ids(t) Performance Looking at the plot of Ids(t) in Figure 3-2c, the Ids(t) waveform is a symmetric sinusoid for Pavs = 6 dbm. But once the power level has been increased to 12 dBm, the Ids(t) waveform begins to clip on both the upswings and downswings of the curve. Because we are at midpoint bias, the waveform will, in this case, exhibit symmetric clipping. Later on we will see that symmetric clipping will not occur at the other biases. At Pavs = 18 dBm, the Ids(t) waveform is clipped even further and even more resembles a square wave. A square wave is known to be rich in odd harmonic content. This is evidently shown in the spectral plot of Ids in Figure 3-3b where there is no second harmonic power but rather third harmonic power. Notice that IdsDC (the DC current), is also 1.0 A in Figure 3-3b. Vds(t) Performance In Figure 3-2e, the Vds(t) plot appears to be a scaled and inverted version of the Ids(t). This is further evidenced in Figure 3-3c the Vds has the same harmonic content as Ids. From the Ids(t) and Vds(t) data in Figure 3-2c and Figure 3-2e, respectively, we can generate a load line as shown in Figure 3-2d on the I-V plane. Notice that the load lines are not varying. To explain, we earlier had from Equation 3.6, = − + − = − + where IdsAC, RL, and Vdsq were all previously defined in Section 3.1. (3.9) 39 In solving for Ids we obtain, = � − � + (3.10) If we substitute in Vdsq = 28V, RL = 50 Ohms, and IdsDC = 1.0 A we have, = 28⁄50 − ⁄50 + 1.0 = − ⁄50 + 1.56 (3.11) Equation 3.11 is the equation for the load line that has been superimposed onto the I-V plane in Figure 3-2. Notice that it seems like additional DC current has been generated due to the ⁄ term in Equation 3.10. This comes from the DC current from the quiescent drain bias in the load resister. It is for these reasons that in the case of Model A and a midway bias point, IdsDC is constant. This means that the load lines are also constant and depend only on Vds as shown in Equation 3.10. This explains the fact that the load lines appear to be constant in Figure 3-2d. We will later see that this will not be the case once the bias point has changed. We now move on to analyzing the output power at fo, 2fo, and 3fo, the reflected power, the conversion gain, and efficiency. Output Power (Pout) The simulated output power versus Pavs plots for the midpoint bias of Model A is shown below in Figure 3-4. The red dot symbol curve is the output power at the fundamental frequency (fo), the blue triangle symbol curve is the output power at the second harmonic (2fo), and the pink square symbol curve is the output power at the third harmonic (3fo). Earlier in Section 1.2 on basic multiplier theory, it was mentioned that midway bias will result in a double-sided clipped waveform that is rich in odd harmonic content. Figure 3-2c shows a square Ids(t) waveform and Figure 3-4 clearly indicates the existence of third harmonic 40 output power for Pavs ≥ 6 dBm. Notice that 3fo output power does not rise above -20 dBm until Pavs ≥ 6 dBm of available power to the model. This is because the drive level was not high enough for the Ids(t) to be symmetrically clipped. Also notice that at this bias the second harmonic output power remains relatively low even at higher Pavs levels. 50 40 Pout (dBm) 30 20 Pout_fo Pout_2fo 10 Pout_3fo 0 -10 -20 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-4: Model A, Midway Bias, Pout vs Pavs at fo, 2fo and 3fo Conversion Gain (CG) Now we will analyze the conversion gain was defined in Equation 1.8 which is plotted in Figure 3-5. For Pavs < 6 dBm, there is no appreciable harmonic conversion gain because there is no harmonic output power at below Pavs = 6 dBm as was shown in Figure 3-4. Once Pavs > 6 dBm, the third harmonic conversion gain (CG3) rises rapidly. This coincides with the rise in third harmonic output power in Figure 3-4. Also, the second harmonic conversion gain remains very low which again coincides with the amount of second harmonic output power in Figure 3-4. 41 Notice that for CG1 and CG3, the gain begins to decrease after Pavs = 6 dBm for CG1 and Pavs = 12 dBm for CG3. If we were to compare this with the respective output powers in Figure 3-4, we notice that the output powers have reached a maximum and leveled off. The decrease in conversion gain is therefore attributed to the continued increase in Pavs without a comparative increase in Pout. This demonstrates that there is a certain Pavs for which one can obtain the most efficient generation of harmonic output power. 12 Based on the information from Figures 3-4 and 3-5, a compromise between the maximum conversion gain and the maximum output power would be around Pavs = 12 dBm. We now move on to analyzing the reflected power from the gate. 50 40 Conversion Gain (dB) 30 20 10 0 CG1 -10 CG2 -20 CG3 -30 -40 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Pavs (dBm) Figure 3-5: Model A, Midway Bias, Convesion Gain vs. Pavs at fo, 2fo, and 3fo 12 While one particular Pavs will achieve the most efficient harmonic conversion it is not necessarily the same Pavs that will give yield the most harmonic output power. While this is not as readily apparent in Model A, it will become much more clear in later models and especially the Yuk Model. In practice it therefore becomes the decision of the designer to determine which Pavs is the most appropriate. 42 Reflected Power (Pref) We will now analyze the reflected power at the gate of Model A versus the available power. The simulation results are shown in Figure 3-6 below. All of these results were obtained from simulations of Model A in ADS. For the reflected power at fo, there is a linear increase for Pavs ≤ 6 dBm. For the Vgs(t) waveform of Figure 3-2a, for Pavs ≤ 6 dBm, it can been seen that no clipping has occurred. 30 20 10 Pref (dBm) 0 -10 -20 -30 -40 Prefl1 Prefl2 Prefl3 -50 -60 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Pavs (dBm) Figure 3-6: Model A, Midway Bias, Reflected Power vs. Pavs at fo, 2fo, and 3fo This agrees with the linear increase in reflected fo power. For Pavs ≥ 6 dBm in Figure 3-2a, we see that Vgs(t) begins to asymmetrically clip. At the same power levels, we see that Figure 3-6 begins to show the existence of harmonic content for Pavs ≥ 6 dBm. Additionally, due to the asymmetric clipping of Vgs(t) in Figure 3-2a, there is more second harmonic content than third harmonic. The third harmonic exists in this case because the gate voltage is not a pure half- 43 rectified sine wave (i.e. the conduction angle is less than 180° which is what is required for optimium odd harmonic generation). Notice as well in Figure 3-6 that for Pavs ≥ 6 dBm that the reflected power at the fundamental has begun to saturate. To explain this we must examine the total power at the gate of Model A which is plotted in Figure 3-7 below. We know that in an ideal simulation such as the one we are performing here, the reflected power (Prefl) and the total power at the gate (Pgs) 13, shown in Figure 3-7, are both proportional to Pavs. In other words, = + = − (3.12) In Figure 3-6, Prefl1, the reflected power at the fundamental is constant for Pavs ≥ 8 dBm. At the same time, Pgs1 keeps on increasing in Figure 3-7. As illustrated in Equation 3.12, the reflected power at fo is the difference between the input power and power at the gate at fo. By this reasoning, it is no surprise that Prefl1 is constant with respect to Pavs. 13 Pgs has been previously defined in Equation 1.12 in Section 1.5. 44 40 30 20 Pgs (dBm) 10 0 -10 -20 Pgs1 -30 Pgs2 -40 Pgs3 -50 -60 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-7: Model A, Midway Bias, Power at the Gate vs. Pavs at fo, 2fo and 3fo Referring back to Figure 3-6, we see that there is significant 2fo reflected power. By using a reflector network in M1 as shown in Figure 1-1 with a resonance at 2fo this power can be sent back to the gate and possibly create additional 2fo output power. This can go against conventional multiplier theory as explained in Section 1.2 where midway bias is the best point at which to operate for odd harmonic content generation. This requires further investigation and will be explored later in the case where we use a 2fo input reflector. We now move on to analyzing the efficiencies of this simulation. Efficiency (CPAE and CDE) Below in Figure 3-8 and Figure 3-9 are power-added efficiencies, PAE at fo, 2fo, and 3fo. 14 14 PAE has been previous defined in Equation 1.13 in Section 1.5. 45 80 PAE (%) 60 40 20 PAE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-8: Model A, Midway Bias, PAE vs. Pavs at fo 8 PAE_2fo PAE (%) 6 PAE_3fo 4 2 0 -2 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-9: Model A, Midway Bias, PAE vs. Pavs at 2fo and 3fo From Figure 3-8, we see that the PAE at the fundamental frequency peaks at about 75% for Pavs = 23 dBm. From Figure 3-9, we see that the 3fo PAE peaks at nearly 8% at Pavs = 25 dBm 46 and the 2fo PAE is at most 0%. 15 The drain efficiencies 16 are similarly plotted in Figure 3-10 and Figure 3-11. 80 CDE (%) 60 40 20 DE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-10: Model A, Midway Bias, CDE vs Pavs at fo In Figure 3-11 below, the 3fo efficiency rises at about Pavs = 12 dBm. This corresponds to the rise in 3fo output power. The 2fo efficiency remains at 0%. This is to be expected since there was essentially no 2fo output power. 15 It should be noted that the efficiencies here are calculated with a correction factor in the DC due to limitations in Model A. The model as it is allows the loadlines to swing past the Vds = 0V axis. Because the DC power is calculated in ADS using the absolute value of Vds, it appeared that a very small Vds gave rise to a very high fundamental output. This gave erroneous efficiencies above 100%. The correction offset is determined by the extent to which the loadlines extend into the negative Vds region. Appendix A contains a quantitative discussion 16 Drain efficiency has been defined in Equation 1.10 in Section 1.5 47 10 DE_2fo CDE (%) 8 DE_3fo 6 4 2 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-11: Model A, Midway Bias, CDE vs Pavs at 2fo and 3fo 3.1.2 Pinch-off Bias We will now analyze the case where Model A has been biased at pinch-off (Vgs = -2.5 V = Vpinch). The Kusher plot and spectral plot for this case are shown below in Figure 3-12 and Figure 3-13, respectively. Pavs = 6, 12, and 18 dBm respectively correspond to an AC input voltage magnitude of |Vp|/2, |Vp|, and 2*|Vp|. 48 Ids, A 2.0 2.0 (c) 1.5 1.5 1.5 1.0 1.0 1.0 0.5 0.5 0.5 0.0 0.0 0.0 -8 0 -6 -4 -2 0 1 (a) -1E-10 -1E-10 -2E-10 -2E-10 -4E-10 -5E-10 0 20 40 0 time, psec -3E-10 (d) -40 -20 0 100 200 300 400 500 600 Time, s Time, s 2.0 (b) 60 80 (e) -3E-10 -4E-10 -5E-10 -6E-10 -6E-10 -8 -6 -4 Vgs, V -2 0 1 -40 -20 0 20 40 60 80 Vds, V Figure 3-12: Model A, Kusher Plot for Pinch-off Bias, Pavs = 6dBm (Red), 12 dBm(Blue), 18 dBm (Green) 49 1.4 (a) 3 Ids, A Vgs, V 4 2 1 0 0 2 4 6 8 10 freq, GHz (b) 70 1.2 60 1.0 50 0.8 40 Vds, V 5 0.6 (c) 30 0.4 20 0.2 10 0.0 0 0 2 4 6 8 10 0 2 4 6 8 10 freq, GHz freq, GHz Figure 3-13: Model A, Spectral Plot for Pinch-off Bias, Pavs = 6dBm (Red); 12 dBm(Blue); 18 dBm (Green) Vgs(t) Taking a look at the Vgs(t) plot in Figure 3-12a, by comparing the point where the gate voltage goes to zero, it is clearly shown that the gate of the model is now biased at pinchoff. It now also takes a higher RF drive level for Vgs(t) to begin clipping. Here we see that Pavs > 12 dBm is required to clip Vgs as opposed to Pavs > 6 dBm from the midway bias case. Ids(t) Notice now that Ids(t) in Figure 3-12 is a half-rectified sine wave for all RF drive power levels due to the pinch-off bias. Previously in Section 1.2 it was determined that a half-rectified sine-wave will be rich in even harmonic content which is useful for designing a frequency doubler. This is readily evidenced in Figure 3-13b where Ids is ~0.4 A at 2fo. In contrast the midway bias case has essentially no Ids current at 2fo (Figure 3-3b). 50 In Figure 3-13, the 2fo Ids peaks at Pavs = 12 dBm (blue arrow) but decreases for Pavs = 18 dBm (green arrow). This is due to the higher Pavs which results in a larger swing of the Ids(t) current waveform shown in Figure 3-12c. In fact, the swing has become large enough at Pavs = 18dBm (green curve), that the Ids(t) is now beginning to clip on both sides. This is directly causes the 3fo current as shown in Figure 3-13b at Pavs = 18 dBm. The resulting square-wave like waveform will hence contain more third harmonics and less second harmonic. This is in contrast to Pavs = 12 dBm where the Ids(t) waveform of Figure 3-12c (blue curve) is a half-rectified sine wave and will therefore contain mostly second harmonic power. Vds(t) The most noticeable difference in Vds(t) in Figure 3-12e is that now the waveforms shift as opposed to the midway bias case (Figure 3-2e). The waveforms are shifting in such a way as to keep the average Vds = Vdsq = 28 V. Notice as well that the loadlines are now shifting. This shifting has been explained in Section 3.1 by Equation 3.8 and by our choice of Rdd. The equation is repeated here for convenience. = − ⁄ + ⁄ + (3.13) The slope of the loadline is determined by RL and the Vds = 0 axis intercept is determined by Vdsq, and IdsDC. RL and Vdsq are clearly constant with respect to Pavs whereas IdsDC is not. In fact, IdsDC will increase to a certain maximum value as Pavs increases. This can be seen in Figure 3-12d. Therefore, the loadlines are shifting in Figure 3-12d because IdsDC changes with respect to Pavs and it determines the value of Ids at which the loadline crosses the Vds = 0V axis. Loadline 51 shifting will not affect this simulation because Model A has only one region of operation (i.e. saturation). 17 We will see that shifting will affect the later models. We now move on to analyzing the output power, the reflected power, the conversion gain, and efficiency at fo, 2fo, and 3fo. Output Power (Pout) The output power, Pout is plotted versus Pavs in Figure 3-14 below. 50 45 40 Pout (dBm) 35 30 25 20 15 Pout1 10 Pout2 5 Pout3 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-14: Model A, Pinch-off Bias, Pout vs Pavs at fo, 2fo, and 3fo For Pavs ≤ 12 dBm, the output power consists of only fundamental and second harmonic output powers. At Pavs = 12 dBm, the 2fo output power peaks and begins to decrease for increasing Pavs and 3fo output power begins to increase and eventually saturate. This agrees with the data from Figure 3-12 and Figure 3-13. To recall from those figures, the 3fo output power 17 This was explained in Section 2.2.1 52 began to increase as 2fo output power decreased corresponding to a double-sided clipping of the Ids(t) waveform. The 3fo output power rises rapidly but also quickly saturates because the amplitude of Ids(t) is no longer increasing. Conversion Gain (CG) The plot of conversion gain for this case is shown below in Figure 3-15. 35 30 CG (dB) 25 20 CG1 15 CG2 10 CG3 5 0 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Pavs (dBm) Figure 3-15: Model A, Pinch-off Bias, Conversion Gain vs. Pavs For Pavs ≤ 12 dBm, the fundamental gain is approximately at a steady 32 dB. At the same time, the second harmonic conversion gain is approximately at a steady 24 dB. No positive conversion gain at the third harmonic exists. If we look back at Figure 3-12, it is easy to understand why this occurs. For Pavs ≤ 12 dbm, the Ids(t) current waveforms are essentially half 53 rectified sine waves and as a result will not contain any third harmonic output power. 3fo output power does not begin to arise until Pavs ≥ 13 dBm. At the same time, 2fo conversion gain begins to sharply decrease. This corresponds to the decrease in output power in Figure 3-14. This behavior can be explained by the double sided clipping of the Ids(t) waveform. As mentioned before, a waveform of this nature will be rich in odd harmonics. Thus far it is apparent that a pinch-off bias will be good for generating a frequency doubler or a tripler depending on the input power level. For a doubler, the input power level should be ≤12 dBm. For a tripler, the input power level should be ≥12 dBm. However to compare the conversion gains shown in Figure 3-5 (midway bias conversion gain) and Figure 3-15 (pinch-off bias conversion gain) it is apparent that a pinch-off bias is much more suitable as a doubler. To obtain better insight we will now investigate the reflected power at the gate. Reflected Power (Prefl) The reflected power for the pinch-off bias case is shown below in Figure 3-16. For Pavs ≤ 11 dBm, there is only the fundamental power being reflected at the gate. In fact the power reflected at the gate is proportional to Pavs. This is because the gate-source diode in the model is off and therefore open-circuited. If we look back at Figure 3-12, we see that for Pavs = 6 dBm, Igs(t) behaves as a sinusoid with one frequency. This is because the gate-source diode is open (i.e. non-conducting). A conducting gate-source diode would result in a multi-harmonic Igs(t) 54 30 20 10 Prefl(dBm) 0 -10 -20 -30 Prefl1 -40 Prefl2 -50 Prefl3 -60 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-16: Model A, Pinch-off Bias, Reflected Power vs. Pavs at fo, 2fo, 3fo Once Pavs increases, the gate-source diode begins to turn on and conduct. This results in the clipping of the Igs(t) sinusoid. This corresponds to the rise of the reflected powers at 2fo and 3fo in Figure 3-16. We will now take a look at the power at the gate defined as Pgate as illustrated Figure 3-17. 55 40 Pgate( dBm) 20 0 -20 Pgate1 Pgate2 -40 Pgate3 -60 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-17: Model A, Pinch-off Bias, Power at the Gate vs. Pavs at fo, 2fo, 3fo For Pavs ≥ 12 dBm, the fundamental and second harmonics are proportional to Pavs. In contrast, the third harmonic is much smaller and is relatively constant with respect to Pavs. This result can be explained by Vgs(t) as an approximate half-rectified sine wave as illustrated in Figure 3-12a. Because the conduction angle is not exactly 180 degrees (not a perfect halfrectified sine wave), some third harmonic power will exist at the gate. Notice in both Figure 3-16 (the reflected power) and Figure 3-17 (the gate power) that the second and third harmonics are exactly the same. This implies that the harmonic power generated at the gate is being completely reflected back for Pavs ≥ 12 dBm. At the same time, the reflected power at the fundamental in Figure 3-16 is saturated. This shows that more power is being sent to the gate as evidenced in Figure 3-17. 56 The use of reflector network would help utilize this unused harmonic power at the gate. However this may change the optimal Pavs = 12 dBm from Figure 3-14 for which we would have maximum 2fo output power since there is not much harmonic content at the gate at Pavs = 12 dBm. This would seem to imply that in order to effectively use the harmonics generated at the gate, we would have to operate at a higher Pavs. We will now analyze the efficiency of the pinch-off bias case. Efficiency (CPAE and CDE) Below are the plots for power-added efficiency, PAE at fo (Figure 3-18), 2fo, and 3fo (Figure 3-19). Conversion PAE has been previously defined in Section 1.5. PAE (%) 60 40 20 PAE1 0 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 3-18: Model A, Pinch-off Bias, PAE vs Pavs at fo 25 30 57 8 PAE2 PAE3 PAE (%) 6 4 2 0 -2 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-19: Model A, Pinch-off Bias, PAE vs Pavs at 2fo and 3fo As was mentioned for the midway bias case, these efficiencies have been calculated with a Vds offset as explained in detail in Appendix A. The fundamental PAE peaks at 59% while the second harmonic PAE peaks at nearly 8%. For the pinch-off bias case, there is a very clear peak in efficiency at Pavs = 12 dBm. To obtain the full picture we must also take a look at the drain efficiency shown below in Figure 3-20 and Figure 3-21. We see again that the 2fo DE peaks at Pavs = 12 dBm. This coincides with the point at which the 2fo output power begins to roll off as 3fo output power begins to rise in Figure 3-14. We can conclude that in the case of a doubler, operating at Pavs = 12 dBm will yield the maximum 2fo output power, conversion gain (Figure 3-15), and efficiencies. When it comes to designing a tripler at pinchoff bias, however, there is a tradeoff. In Figure 3-19, the 3fo PAE peaks at Pavs = 26 dBm. According to Figure 3-14, this is not where the peak 3fo output power would be. Also, as shown in Figure 3-15, the peak third harmonic CG is at a 58 much lower Pavs. Hence, in the case of a tripler, there are tradeoffs amongst conversion gain, output power, and efficiency. We will later see that conversion PAE and conversion DE for particular harmonics will improve with the use of harmonically tuned reflector networks. CDE (%) 60 40 20 CDE1 0 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 3-20: Model A, Pinch-off Bias, CDE vs Pavs at fo 25 30 59 8 CDE2 CDE3 CDE (%) 6 4 2 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-21: Model A, Pinch-off Bias, CDE vs Pavs at 2fo and 3fo 3.1.3 Forward Conduction Bias We will now study the forward conduction bias case. The gate is now biased in forward conduction (Vgsq = Vfwd = 0V). The Kushner plot and spectral plots are shown below in Figure 3-22 and Figure 3-23, respectively. Pavs = 6, 12, and 18 dBm respectively correspond to an AC input voltage magnitude of |Vp|/2 (red), |Vp| (blue), and 2*|Vp| (green). 60 Ids, A 2.0 2.0 (b) 2.0 (c) 1.5 1.5 1.5 1.0 1.0 1.0 0.5 0.5 0.5 0.0 0.0 -6 0.0 -4 -2 0 0.0 0 2 100 200 300 400 500 time, psec (a) -20 0 20 40 60 80 100 (e) -5.0E-11 -1.5E-10 Time, s -1.5E-10 Time, s (d) -3.5E-10 -2.5E-10 -3.5E-10 -4.5E-10 -5.5E-10 -5.5E-10 -6 -4 -2 0 -20 2 0 20 40 60 80 100 Vds, V Vgs, V Figure 3-22: Model A, Forward Bias, Kushner Plot Pavs = 6 dBm (Red), 12 dBm (Blue), and 18 dBm (Green) 3.0 1.8 (a) 70 (b) 1.6 2.5 (c) 60 1.4 1.5 1.0 Vds, V Ids, A Vgs, V 50 1.2 2.0 0.8 40 30 0.6 1.0 20 0.4 0.5 10 0.2 0.0 0.0 0 2 4 6 freq, GHz 8 10 0 0 2 4 6 freq, GHz 8 10 0 2 4 6 8 10 freq, GHz Figure 3-23: Model A, Forward Bias, Spectral Plot Pavs = 6 dBm (Red), 12 dBm (Blue), and 18 dBm (Green) 61 Vgs(t) We can easily see that the gate is biased at forward conduction by looking at Vgs(t) in Figure 3-22a. Because Vgsq = 0V, the positive swing of Vgs(t) is automatically clipped for all input power levels. This means there is always a half-rectified sine wave at the gate. As expected the Vgs spectral plot in Figure 3-23 shows that it is rich in fo (3.333 GHz) and 2fo (6.666 GHz) but not 3fo (9.999 GHz) at all of the input power levels. Ids(t) Ids(t) as shown in Figure 3-22b starts off as a half-rectified sine wave. Once Pavs = 18 dBm, the waveform ends up being double-sided clipped. Similarly in Figure 3-23, Ids displays both 2fo and 3fo harmonic content. As was in the case of pinch-off bias, Pavs = 12 dBm contains the most amount of 2fo power but no 3fo power. At Pavs = 18 dBm, 3fo power has arisen and there is less 2fo output power. Vds(t) Looking at Vds(t) in Figure 3-22e, we see that for each Pavs the waveform is shifting in order to make its average equal to Vdsq = 28V. Earlier we have seen that the shifting loadlines can be explained from Equation 3.13. This is again similar to the pinch-off bias case except that now the loadlines are shifting to the left (towards a smaller Vds). Recall earlier in the pinch-off case that the loadlines were shifting to the right (towards a larger Vds in Figure 3-14d). Here in the forward bias case, IdsDC is shown to decrease in Figure 3-23 for increasing Pavs. Since Vds is inversely proportional to IdsDC in Equation 3.13, Vds will have to decrease and therefore has the effect of shifting the loadlines to the left. Since Model A contains only the saturation region of operation, loadline shifting will have no effect. This will not be the case when we examine Model B. 62 Output Power (Pout) The output power at fo, 2fo, and 3fo are plotted versus Pavs in Figure 3-24 below. 50 40 Pout (dBm) 30 20 Pout 10 Pout2 0 Pout3 -10 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-24: Model A, Forward Bias, Output Power vs. Pavs at fo, 2fo, 3fo Notice that for Pavs ≤ 12 dBm, both Pout and Pout2 increase linearly with respect to Pavs. At Pavs = 12, the fo output power reaches a saturation point. At the same time, a maximum 2fo output power is reached and begins to decline while 3fo output power rises as Pavs increases. This behavior corresponds to the spectral plot in Figure 3-23b where the Ids second harmonic content peaked at a particular power level and then decreased as third harmonic content arose for Pavs ≥ 12 dBm. This can also be explained by the Kushner plot in Figure 3-22 where Ids(t) is initially a half-rectified sine wave. As Pavs was increased to 18 dBm, the waveform began to resemble a square wave. Since the generated square wave is not perfectly symmetric, 2fo power will still exist but at a decreased level. 63 Conversion Gain (CG) The conversion gain as previously defined in Section 1.5 in Equation 1.8 is plotted versus Pavs for fo, 2fo, and 3fo below in Figure 3-25. 40 CG (dB) 20 0 CG1 -20 CG2 CG3 -40 -60 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-25: Model A, Forward Bias, Conversion Gain vs. Pavs at fo, 2fo, 3fo The fundamental and 2fo conversion gain are constant until Pavs = 12 dBm. After that, the two conversion gains decrease as 3fo conversion gain rises. Similar to the pinch-off bias case, the drop off in the 2fo conversion gain can be explained by the doubled sided clipping of the Ids(t) waveform. This is also the cause of the rise in 3fo conversion gain. Back in Figure 3-24, we see that the rise in 3fo conversion gain also corresponds to the rise in 3fo output power. Similarly we also see that the decrease in 2fo conversion gain corresponds to the decreasing 2fo output power. Reflected Power (Prefl) The reflected power at fo, 2fo, and 3fo are plotted below in Figure 3-26. 64 40 Pref1 30 Pref2 Pref3 Prefl (dBm) 10 -10 -30 -50 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-26: Model A, Forward Bias, Reflected Power vs. Pavs at fo, 2fo, 3fo It is clear that there is mostly second harmonic content being reflected. Furthermore, the reflected power at 2fo is above 0 dBm for Pavs ≤ +8 dBm. To obtain a better understanding of this result we will take a look at the total power at the gate plotted below in Figure 3-27. From this figure, the total power at the gate consists of mostly fundamental and second harmonic power. The fundamental power is also consistently higher than the 2fo power. The total available power is a sum of the power at the gate and the reflected power. 18 Here in Figure 3-27, we see that the fundamental power is entirely at the gate. For each Pavs we see that the fundamental Pgate power is the same. Hence it is no surprise that there is so little reflected power at the fundamental. 18 Note that the power at the gate, Pgate can also be thought of as the transmitted power. 65 40 Pgate (dBm) 30 10 -10 Pgate1 Pgate2 -30 Pgate3 -50 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-27: Model A, Forward Bias, Total Power at the Gate vs. Pavs at fo, 2fo, 3fo It is also no surprise that there is no 3fo power to be found due to the waveform for Igs(t) that we saw in Figure 3-22. As may be recalled, Igs(t) was a half-rectified sine wave for all input power levels and thus contains no third harmonic power. In terms of multiplier design, placing a 2fo input reflector at the gate maybe may increase the Pavs that would give the most 2fo output power. In addition, since there is no 3fo reflected or at the gate, a 3fo input reflector would do little to improve overall multiplier performance. Efficiencies (CPAE and CDE) The conversion PAE and conversion DE are plotted below in Figure 3-28, Figure 3-29, Figure 3-30, and Figure 3-31. 66 80 PAE1 CPAE (%) 60 40 20 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-28: Model A, Forward Bias, PAE vs. Pavs at fo 8 PAE2 6 CPAE (%) PAE3 4 2 0 -2 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 3-29: Model A, Forward Bias, PAE vs. Pavs at 2fo and 3fo 25 30 67 80 Pdrain1 CDE (%) 60 40 20 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 3-30: Model A, Forward Bias, CDE vs. Pavs at fo 8 Pdrain2 Pdrain3 CDE (%) 6 4 2 0 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 3-31: Model A, Forward Bias, CDE vs. Pavs at 2fo and 3fo 25 30 68 Not surprisingly the efficiency is behaving in the same way as the pinch-off bias case. This is because of the similar behavior of the waveforms in Figure 3-22 to the pinch-off bias case in Figure 3-12. In both cases, the Ids(t) waveforms begin as a single sided clipped waveform which leads to a peak in the 2fo efficiencies. As Pavs increases, the waveform begins to clip on both sides. This results in an increase of 3fo output power and a decrease in 2fo output power. For efficiency, this means a decrease in the 2fo PAE and DE while the 3fo PAE and DE increase. The peak efficiencies for 2fo CPAE and CDE occur at roughly the same Pavs as in pinch-off. The pinch-off case did exhibit slightly better efficiency since the gate-source diode is always on in the forward conduction bias. 3.1.4 Summary of Results for Multiplier without Reflector Networks We will now summarize the results of the multiplier performance without reflector networks. Below in Table 3-2, the results are organized according to a doubler or tripler multiplier performance. Each table shows the maximum power, maximum conversion gain, maximum CPAE, and maximum CDE with the respective Pavs that each maxima occur at. 69 Doubler Statistics Maximum Power Maximum CG Maximum CPAE Maximum CDE Gate Bias Pavs (dBm) Pout (dBm) Pavs (dBm) CG (dBm) Pavs (dBm) CPAE (%) Pavs (dBm) CDE (%) Forward Conduction 13 36.690 6 24.609 13 7.54 13 7.52 Midway NA NA NA NA NA NA NA NA Pinch-off 13 36.697 -6 24.618 12 7.70 12 7.73 Tripler Statistics Maximum Power Maximum CG Maximum CPAE Maximum CDE Gate Bias Pavs (dBm) Pout (dBm) Pavs (dBm) CG (dBm) Pavs (dBm) CPAE (%) Pavs (dBm) CDE (%) Forward Conduction 30 36.272 18 14.799 26 6.61 30 7.70 Midway 27 36.472 12 20.832 25 7.57 27 8.30 Pinch-off 30 36.293 18 14.806 26 5.294 30 6.132 Table 3-2 Model A No Reflector Maximum Performance Parameters 3.2 Harmonic Generation using Input Reflector Networks We will now examine harmonic generation with the GaN HEMT Model A using input reflector networks. In general, reflector networks on the gate or drain can be synthesized with specific dimensions that can be constructed to reflect particular harmonic frequencies at an optimal phase. A reflector network on the input can affect a multiplier circuit in two ways. A reflector network designed for a particular harmonic, nfo, can interact with the input waveform to create additional nfo power at the output. Phasing on the reflector can also be adjusted to reflect nfo harmonic power back to the device model to create additional nfo at the output. Secondly, re- 70 reflected harmonics can mix (or interact with the device’s non-linear properties) with other harmonics and fo to create more harmonic output power [5]. A circuit diagram of a frequency multiplier utilizing a reflector network on the gate circuit, M1, is shown below in Figure 3-32. Figure 3-32: Multiplier Circuit diagram with Input Reflector Network The reflector network essentially consists of a resonant circuit. The reflector network in Figure 3-32 is designed in such a way that it is a short circuit at a particular harmonic frequency. The reflected power is sent back to the gate of the device at a phase offset determined by Linnfo At the same time it is open circuited at the other harmonic frequencies so that those frequencies are not affected by the reflector [5]. 3.2.1 Harmonic Generation using 2fo Input Reflector Network First we will explore the use of a 2fo input reflector network. The network consists of a series LC resonant circuit and a length of transmission line Linnfo as shown in Figure 3-32. We can find the values of L and C according to the equation = 1⁄�(), where in this case, 71 = 2(2 ) = 2(6.6669). A high Q factor is also desired for the reflector network. In order to achieve a large Q factor a relatively large L and small C is required to maintain the same resonant frequency. 19 By choosing L = 100 nH, the resultant C is 5.700e-15 F. The resultant reflector network was individually simulated with its responses shown below in Figure 3-33 and Figure 3-34. 30 Insertion Loss (dB) 25 20 15 10 5 0 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 Frequency (GHz) Figure 3-33: Insertion Loss vs. Frequency of 2fo Lumped Element Reflector Network 19 In a series RLC circuit = 1⁄ �⁄ . From this we see that a large L will result in a higher Q. However in order to maintain the same resonant frequency C must become smaller. 72 Insertion Phase (deg) 100 m6 freq=6.666GHz phase(S(2,1))=0.000 50 m6 0 -50 -100 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 Frequency (GHz) Figure 3-34: Insertion Phase vs. Frequency of 2fo Lumped Element Reflector Network Realistically a lumped element reflector network is not very practical for our purposes, but for the sake of an ideal simulation it will suffice. The other portion of the input reflector network is a length of transmission line between the gate and the resonant network as shown in Figure 3-32. The transmission line provides an optimal phase to reflect 2fo harmonic signals back to the gate of the device, thus improving harmonic output performance. In order to utilize the input reflector we must first determine the proper length of Linnfo through simulation. This simulation sweeps the transmission line length from 0º to 180º over a range of Pavs values. The extremes of the range of Pavs is determined from the previous power sweep simulations without the use of any input reflectors. We will now explore the use of a 2fo input reflector network on the gate of Model A at pinch-off bias since it has previously been shown that this is the optimal bias for 2fo generation. 73 3.2.1.1 Pinch-off Bias We now move on to investigating how a 2fo input reflector will affect harmonic generation at pinch-off bias. First we must determine the proper length of transmission line for the input reflector through the simulation process described in the last section. The range of Pavs to simulate over is determined from Figure 3-14 which shows that the 2fo output power peaks at Pavs = 13 dBm. A range of 8 ≤ Pavs ≤ 18 dBm will bracket this peak and provide a good picture of how the input power affects performance. The results of this simulation are shown in Figure 3-35 and Figure 3-36 for 2fo output power and conversion gain, respectively. 38 Pout_2fo 36 Pavs=8.000000 34 Pavs=10.000000 32 Pavs=12.000000 Pout_2fo 30 Pavs=14.000000 28 Pavs=16.000000 26 Pavs=18.000000 24 22 20 18 16 0 20 40 60 80 100 120 140 160 180 fo6667len Figure 3-35: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, 2fo Input Reflector 74 25 CG_2fo Pavs=8.000000 20 Pavs=10.000000 Pavs=12.000000 CG_2fo 15 Pavs=14.000000 Pavs=16.000000 10 Pavs=18.000000 5 0 0 20 40 60 80 100 120 140 160 180 fo6667len Figure 3-36: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, 2fo Input Reflector Both figures demonstrate that fo6667len = 90º will provide a maximum 2fo output power and conversion gain. Based on these simulations it is observed that the output power and conversion gain both peak for 12 ≤ Pavs ≤ 14 dBm and then decrease as Pavs moves beyond these values. This is not surprising considering that the peak 2fo output power was found to be at Pavs = 13 dBm in Figure 3-14. Now we will move on to analyzing the effects of an fo output reflector on Model A. 3.3 Harmonic Generation using Output Reflector Networks In this section we will analyze the effects of the output reflector networks on the multiplier network. Previously we had only explored the use of a reflector network on the gate/input of the device in network M1. Now we will place a reflector network on the drain/output of the device in network M2 as shown in Figure 3-37. In the M2 network as shown, Loutfo represents the length of transmission line that will provide the optimal phasing required to improve the performance at 75 a particular harmonic. Output reflector networks can theoretically affect the multiplier in three ways. First, an output reflector containing a resonant network for a particular nfo harmonic will reflect it back towards the drain of the device and may cause more of the desired mfo to appear at the output. For example, we will show that an fo output reflector network can reflect the fo signal back to the device to mix with the 3fo signal to create more 2fo output. With the Loutfo transmission line, the additional mfo output power can be phased in such a way as to constructively add to the initial mfo power already available at the output. Secondly, the nfo that is being reflected back towards the drain can re-appear at the gate of the device where it can be used constructively to add to the nfo output. This will happen if there is a feedback path in the transistor between the gate and the drain. Finally, an output reflector is very effective in suppressing undesired harmonic powers from reaching the output. This will result in a more pure output waveform that is reaching the load RL as shown in Figure 3-37. In this section the M1 network will remain unchanged and only contain the biasing network as shown. Figure 3-37: Multiplier Circuit Diagram with fo Output Reflector Network 76 3.3.1 Harmonic Generation using an fo Output Reflector Network In this section we will focus on the use of an output reflector at fo. We will see how it affects multiplier performance at pinch-off bias on Model A. The output reflector network is realized with a length of transmission line Loutfo and a series inductor and capacitor of L = 100 nH and C = 2.28018264e-14 F, respectively. Figure 3-38 shows the insertion loss (dB) versus frequency (GHz) for the reflector network. Figure 3-39 and Figure 3-40 show the return loss (dB) and return loss phase (deg) versus frequency (GHz), respectively. Insertion Loss (dB) 0 m1 freq=3.333GHz dB(S(2,1))=-133.611 -50 -100 m1 -150 0 2 4 6 8 10 12 Frequency (GHz) Figure 3-38: Insertion Loss, S(2,1) dB, fo Output Reflector Network Return Loss (dB) 50 m2 freq=3.333GHz -dB(S(1,1))=1.813E-13 40 30 20 10 m2 0 0 2 4 6 8 10 12 Frequency (GHz) Figure 3-39: Return Loss, S(1,1) dB, fo Output Reflector Network 77 180 m3 freq=3.333GHz phase(S(1,1))=-180.000 Return Loss Phase (deg) 140 100 60 20 -20 -60 -100 m3 -140 -180 0 2 4 6 8 10 12 Return Loss Phase (deg) Figure 3-40: Return Loss, S(1,1) dB, fo Output Reflector Network In the following section we will examine the effects of an fo ouput reflector network on a multipler circuit with Model A at pinch-off bias. 3.3.1.1 Pinch-off Bias In this section we will examine the effects of the fo output reflector on Model A at pinchoff bias. The results are shown below in Figure 3-41 and Figure 3-42. 37 Pout_2fo Pavs=8.000000 36 Pout_2fo Pavs=10.000000 35 Pavs=12.000000 Pavs=14.000000 34 Pavs=16.000000 33 Pavs=18.000000 32 0 20 40 60 80 100 120 140 160 180 Out_len Figure 3-41: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, fo Output Reflector 78 26 CG_2fo 24 Pavs=8.000000 Pavs=10.000000 CG_2fo 22 Pavs=12.000000 20 Pavs=14.000000 Pavs=16.000000 18 Pavs=18.000000 16 14 0 20 40 60 80 100 120 140 160 180 Out_len Figure 3-42: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model A, fo Output Reflector Notice that the conversion gain and output power are not affected by the fo output reflector. There is no effect because of the constant Ids and Vds relationship in Model A as was shown in Section 2.2.1. In other words, Ids is independent from Vds which means that reflecting the fundamental output power will not affect the harmonic content of Ids. Therefore the fo output reflector has no effect and no further examination is required. Furthermore, a combination of the input and output reflector networks will theoretically have no advantage over the single 2fo input reflector network. 79 4 Study of Harmonic Generation in Model B In this chapter we will utilize Model B to better analyze the effects of reflector networks on a more realistic transistor model. Model B has been previously defined in Section 2.2.2. In this section we will first investigate the harmonic generation behavior of Model B without the use of any reflector networks on the input or output. Then we will investigate the use of an individual reflector networks on the input and the output. Finally, a section is presented where both input and output reflector networks are used. 4.1 Harmonic Generation without Reflector Networks In this section we will investigate harmonic generation in Model B without the use of any reflector networks. The simulations performed here are identical to the ones performed for Model A in Section 3.1 except that Model B will now be used. We will examine only the pinchoff bias case, since we have previously indicated that this has been shown to provide optimum 2fo harmonic generation. 4.1.1 Pinch-off Bias In this section we will examine the large signal behavior of Model B at pinch-off bias. Below are the Kushner and spectral plots 20 in Figure 4-1 and Figure 4-2, respectively. Vgs(t) Performance Figure 4-1a shows Vgs(t) versus time waveforms for Pavs = 6, 12, and 18 dBm (Vgs = |Vp|/2 (red), |Vp| (blue), and 2*|Vp| (green). From Figure 4-1a and Figure 4-1b it is seen that Model B is indeed biased at pinch-off. For Pavs = 6 dBm (red curve) Figure 4-1a illustrates that 20 See Section 3.1.1 for a discussion about these plots 80 the Vgs(t) waveform exhibits no clipping. Correspondingly, Figure 4-2a shows that there is 2fo present in Vgs for Pavs ≥ 12 dBm. Ids (A) 2.0 2.0 (b) 2.0 (c) 1.5 1.5 1.5 1.0 1.0 1.0 0.5 0.5 0.5 0.0 0.0 -8 0.0 -6 -4 -2 0 1 0.0 0 100 200 300 400 500 600 time, psec (a) 0 10 20 30 40 50 60 (e) -5.0E-11 -1.5E-10 -1.5E-10 Time (s) Time (s) (d) -3.5E-10 -2.5E-10 -3.5E-10 -4.5E-10 -5.5E-10 -5.5E-10 -8 -6 -4 -2 0 0 1 10 Vgs (V) 20 30 40 50 60 Vds (V) Figure 4-1: Kushner Plot, Model B, Pinch-off Bias, Pavs = 6 dBm (Red), Pavs = 12 dBm (Blue), Pavs = 18 dBm (Green) 0.7 (a) 35 (b) (c) 0.6 30 25 0.5 25 20 0.4 20 15 Vds (V) 30 Ids (A) Vgs (V) 35 0.3 15 10 0.2 10 5 0.1 5 0 0.0 0 2 4 6 Freq (GHz) 8 10 0 0 2 4 6 Freq (GHz) 8 10 0 2 4 6 8 10 freq, GHz Figure 4-2: Spectral Plot, Model B, Pinch-off Bias, Pavs = 6 dBm (Red), Pavs = 12 dBm (Blue), Pavs = 18 dBm (Green) 81 Ids(t) Performance Figure 4-1c displays Ids versus time for Pavs = 6, 12, and 18 dBm (red, blue, green – respectively). It will be noted that because we are at pinch-off bias, Ids(t) contains harmonics even when Vgs(t) does not. Initially the waveform contains more 2fo than 3fo (6.666 GHz and 10 GHz, respectively) as evidenced by the red arrows in Figure 4-2b. When Pavs increases to 18 dBm, we see that there is more 3fo content. This is due to the double-sided clipping of the Ids waveform. The resulting square-like waveform shown in green in Figure 4-1c which, has been previously established, will contain more odd harmonic content than even harmonics. This is also readily shown in Figure 4-2b. Vds(t) Performance The Vds(t) waveform is shown in Figure 4-1e for Pavs = 6, 12, and 18 dBm (red, blue, and green – respectively). We can see from the spectral plot in Figure 4-2c that the relative harmonic content is identical to that of Ids in Figure 4-2b. Hence the analysis of the waveform is the same as Ids(t). We will now examine the output power versus input power response. Output Power Pout Figure 4-3 below shows the output power for each harmonic versus input power. 82 45 40 35 Pout (dBm) 30 25 20 15 Pout1 10 Pout2 5 Pout3 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-3: Output Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) From this figure it is seen that the output power at fo saturates at 40 dBm as Pavs becomes greater than 20 dBm. In the case of the 2fo response it is seen that the response increases until it peaks at a value of 27.6 dBm at Pavs = 5 dBm. For Pavs > 5 dBm, the 2fo output power decreases. At the same time, for values of Pavs > 3 dBm, the figure indicates that 3fo output power is increasing. The 3fo output power peaks at 30.5 dBm for Pavs = 30 dBm and this is also where the fundamental output power level saturates. Notice that initially for Pavs < 5 dBm, the 2fo output power is much higher than the 3fo output power. This corresponds to the harmonic behavior evidenced in the spectral plot of Ids and Vds in Figure 4-2b and 4-2c. As the input power level Pavs becomes larger, the output waveforms begin to clip on both sides. This results in the lower 2fo output power and the higher 3fo output power because the waveofmr is becoming more symmetrical. 83 Conversion Gain (CG) Figure 4-4 below shows the conversion gain versus input power for fo, 2fo, and 3fo. The maximum 2fo CG is 24.6 dB at Pavs = -5 dBm. For Pavs > 2 dBm the 2fo CG begins to drop off. Correspondingly, at this point, the 3fo conversion gain begins to rise. The 3fo CG is seen to have maximum of 14.1 dB at Pavs = 11 dBm. 40 CG1 Conversion Gain (dB) 35 CG2 30 CG3 25 20 15 10 5 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-4: Conversion Gain (dB) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) The behavior of the conversion gain must be considered in addition to the output power especially when we later examine efficiency. We will now examine the power at the gate and the reflected power. Reflected Power (Pref) Below in Figure 4-5 is a plot of the reflected power at the gate. The reflected power at fo may be observed to increase linearly until Pavs = 13 dBm at which point it saturates to about 14 84 dBm of reflected power. The 2fo reflected power rises rapidly for Pavs ≥ 13 dBm. On the other hand, the 3fo reflected power saturates to about 5 dBm. 30 25 Pref1 20 Pref2 15 Pref3 Prefl (dBm) 10 5 0 -5 -10 -15 -20 -25 -30 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-5: Reflected Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias at fo (Red Dot), 2fo (Blue Triangle), 3fo (Pink Square) Conversion Power Added Efficiency and Drain Efficiency Now we will examine the CPAE and CDE of Model B at pinch-off bias. 85 80 CPAE (%) 60 40 20 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-6: Model B, Pinch-off Bias, CPAE vs. Pavs at fo 10 CPAE (%) 8 6 4 2 0 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 4-7: Model B, Pinch-off Bias, CPAE vs. Pavs at 2fo and 3fo 25 30 86 Figure 4-6 is a plot of the PAE at the fundamental frequency. This figure shows that the maximum PAE of 68.8% occurs at Pavs = 19 dBm. The 2fo PAE as shown in Figure 4-7, peaks at a significantly less value of 7.9% for Pavs = 3 dBm. Finally the 3fo PAE peaks at 6.1% for Pavs = 20 dBm. The conversion drain efficiencies (CDE) are shown below in Figure 4-8 (fo) and Figure 4-9 (2fo and 3fo), respectively. The fundamental DE peaks at 69.4% at Pavs = 20 dBm while the 2fo and 3fo DEs peak respectively at 7.9% at Pavs = 3 dBm and 7.5% at Pavs = 26 dBm. The values of these efficiencies are expected since the fundamental output power and conversion gain are the highest. Because we are operating at pinch-off bias the 2fo efficiencies are higher than 3fo. 80 CDE (%) 60 40 20 0 -10 -5 0 5 10 15 20 Pavs (dBm) Figure 4-8: Model B, Pinch-off Bias, CDE vs. Pavs at fo 25 30 87 8 CDE (%) 6 4 2 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-9: Model B, Pinch-off Bias, CDE vs. Pavs at 2fo and 3fo Now we will move on to examining the effects of a 2fo input reflector on Model B. 4.2 Harmonic Generation using Input Reflector Networks We will now explore the effects of an input reflector network on harmonic generation employing Model B. The same type of reflector network and circuit topology that was shown in Figure 3-32 will be used. 4.2.1 Harmonic Generation using 2fo Input Reflector Network In this section we will utilize the same 2fo input reflector network that was described in Section 3.2.1 for Model A. In addition, the same type of simulation will be used in order to determine the proper length of input reflector transmission line to optimize output power performance at 2fo. Only pinch-off bias will be examined since it is the bias at which the most 2fo harmonic content is generated. 88 4.2.1.1 Pinch-off Bias In Section 3.2.1.1 a 2fo input reflector was used on the gate of Model A and a simulation was performed in order to determine the optimal length of transmission line to improve 2fo harmonic production at the output. The same circuit and process will be utilized in this section with Model B. Similarly, we will refer to Figure 4-3 to determine the range of Pavs over which to perform the simulation. Based on that figure we see that 2fo output power peaks at Pavs = 5 dBm, and that a range of -4 ≤ Pavs ≤ 14 dBm will give a good picture of the effects that the length of transmission line will have on the 2fo performance. The resultant 2fo output power and conversion gain are shown below in Figure 4-10 and Figure 4-11, respectively. 28 Pout_2fo Pout_2fo 26 24 Pavs=-4.000000 22 Pavs=-2.000000 20 Pavs=0.000000 18 Pavs=2.000000 16 Pavs=4.000000 14 Pavs=6.000000 12 Pavs=8.000000 10 Pavs=10.000000 8 Pavs=12.000000 6 0 20 40 60 80 100 120 140 160 180 Pavs=14.000000 Lin2fo Figure 4-10: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, 2fo Input Reflector 89 25 CG_2fo 20 Pavs=-4.000000 Pavs=-2.000000 CG_2fo 15 Pavs=0.000000 10 Pavs=2.000000 5 Pavs=4.000000 Pavs=6.000000 0 Pavs=8.000000 -5 Pavs=10.000000 Pavs=12.000000 -10 0 20 40 60 80 100 120 140 160 180 Lin2fo Pavs=14.000000 Figure 4-11: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, 2fo Input Reflector The results in both of the above figures are similar to Model A in Section 3.2.1.1. For both plots the peak performance is consistently reached when Lin2fo = 90º (Figure 3-32) and when 2 ≤ Pavs ≤ 4 dBm. The peak range of Pavs is not surprising considering that the peak 2fo output power was at Pavs = 5 dBm as was shown in Figure 4-3. Now we will move on to analyzing the use of an fo output reflector network on Model B. 4.3 Harmonic Generation using Output Reflector Networks The concept of an output reflector network tuned to fo has been previously described in Section 3.3. The same circuit topology in Figure 3-37 will be used here. 4.3.1 Harmonic Generation using fo Output Reflector Network The fo output reflector network that was shown in Section 3.1.1 will also be used in this analysis. 90 4.3.1.1 Pinch-off Bias Effect on fo Output Power Previously in Section 3.3.1.1 with Model A, it was seen that an output reflector had no effect on the harmonic output of the transistor. In the case of Model B, however, the output reflector will have an effect since now Ids is dependent on Vds as was shown in Section 2.2.2. The same simulation from before is performed. Below in Figure 4-12 is the fo output power versus transmission line length. The multiplier response without reflector networks was previously shown in Figure 4-3. There the peak fo output power was 40 dBm. Now, because of the fo output reflector, the peak is only 12 dBm. 15 Pout_fo Pavs=-4.000000 10 fo Output Power (dBm) Pavs=-2.000000 5 Pavs=0.000000 Pavs=2.000000 0 Pavs=4.000000 Pavs=6.000000 -5 Pavs=8.000000 Pavs=10.000000 -10 Pavs=12.000000 -15 0 20 40 60 80 100 120 140 160 180 Pavs=14.000000 Loutfo (deg) Figure 4-12: fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector Effect on 2fo Output Power The 2fo output power and conversion gain are shown below in Figure 4-13 and Figure 4-14, respectively. 91 40 Pout_2fo 2fo Output Power (dBm) 35 Pavs=-4.000000 Pavs=-2.000000 30 Pavs=0.000000 25 Pavs=2.000000 Pavs=4.000000 20 Pavs=6.000000 15 Pavs=8.000000 10 Pavs=10.000000 Pavs=12.000000 5 0 20 40 60 80 100 120 140 160 180 Pavs=14.000000 Loutfo (deg) Figure 4-13: 2fo Output Power (dBm) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector 30 CG_2fo 2fo Conversio Gain (dB) 25 Pavs=-4.000000 Pavs=-2.000000 20 Pavs=0.000000 15 Pavs=2.000000 10 Pavs=4.000000 Pavs=6.000000 5 Pavs=8.000000 0 Pavs=10.000000 Pavs=12.000000 -5 0 20 40 60 80 100 Loutfo (deg) 120 140 160 180 Pavs=14.000000 Figure 4-14: Conversion Gain (dB) vs. Transmission Line Length (deg), Pinch-off Bias, Model B, fo Output Reflector Figure 4-13 is a plot of the 2fo output power versus the length of transmission line on the reflector, Loutfo over a range of Pavs (-4 to 14 dBm). In this figure, a dip in the 2fo output power is observed at Loutfo = 90º. Recall that back in Figure 4-12, for the same line length, the fo output power experiences a peak. Because of the peak in fo output power, less fo is being sent back in to the drain to create additional 2fo output power. For Loutfo from 20º to 60º the output power is 92 highest for Pavs = 12 or 14 dBm. When no reflector networks have been used the 2fo output power peaked at Pavs = 5 dBm, as was shown in Figure 4-3. Now it appears that the peak 2fo output power occurs at Pavs = 14 dBm. However the peak 2fo conversion gain in Figure 4-14 is observed to occur at Loutfo = 80º for Pavs = -4 or -2 dBm. Now that both the input and output reflector networks have been determined we will place these networks on the multiplier and analyze its output. 4.4 Harmonic Generation using Input and Output Networks In Section 4.2.1 the optimum 2fo input reflector line length was determined to be Lin2fo = 90º. In Section 4.3.1, the optimum fo output reflector line length was chosen to be Loutfo = 40º. From the same section it was indicated that Loutfo = 40º will not give the highest possible conversion gain – especially for small Pavs. But choosing Loutfo = 40º, the output power and conversion gain will both achieve an improved performance. Both of these reflectors will now be placed in the same multiplier circuit (Figure 4-15 below) to analyze the benefits of using both networks. Figure 4-15: Multiplier Circuit Diagram with 2fo Input Reflector Network and fo Output Reflector Network 93 A power sweep simulation with -10 ≤ Pavs ≤ 30 dBm is performed with the circuit shown above in Figure 4-15. Figure 4-16 and Figure 4-17 show the output power and conversion gain 40 Input and Output Reflectors Pout_2fo (dBm) 35 Output Reflector Only Input Reflector Only 30 25 20 15 No Reflectors 10 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-16: Output Power (dBm) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks 94 2fo Conversion Gain (dB) 30 Input and Output Reflector 20 10 Output Reflector Only 0 Input Reflector Only -10 No Reflectors -20 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-17: Conversion Gain (dB) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks Figure 4-16 shows a comparison of the behavior of the multiplier with both reflector networks (Pout_2fo), with only the input reflector (Pout2_Input), with only the output reflector (Pout2_Output), and no reflector networks (Pout2_NoRefl). From this figure it is apparent that the input reflector network is effective only for Pavs > 12 dBm. In contrast, the output reflector causes a much more significant increase in the 2fo output power at Pavs > 3 dBm and saturates at about 36.8 dBm. Pout_2fo has the highest amount of output power especially for Pavs > 14 dBm, and saturates at about 37.5 dBm. Figure 4-17 shows the 2fo conversion gain for the case with both reflector networks (CG_2fo), with only the input reflector (CG2_Input), with only the ouput reflector (CG2_Output), and no reflector networks (CG2_NoRefl). Notice that for Pavs ≤ 2 dBm, all cases have the same conversion gain with a peak at about 24.6 dB. For CG2_NoRefl, the conversion gain decreases starting at Pavs = 2 dBm. For CG2_Input the conversion gain also decreases at Pavs 95 = 2 dBm, but has improved conversion gain over the no reflector case for Pavs > 14 dBm. In the case of the CG2_Output conversion gain, the peak conversion gain is maintained until about Pavs = 10 dBm. Furthermore the conversion gain decreases at a much slower rate. For CG2_2fo, the conversion gain is observed to have a similar behavior but decreases at a slightly slower rate for Pavs > 14 dBm. Figure 4-18 shows the 2fo conversion PAE (CPAE) for the case with both reflector networks (PAE2), input reflector only (PAE2_Input), output reflector only (PAE2_Output), and the no reflector network (PAE_NoRefl). For Pavs ≤ 2 dBm, all cases exhibit the same CPAE. For Pavs > 12 dBm, PAE2_Input has a higher CPAE than the no reflector case. With the output reflector case, the CPAE actually increases for Pavs > 2 dBm to a peak of 24.9% for Pavs = 13 dBm. For PAE2, the efficiency increases further than PAE2_Output and peaks at 30% for Pavs = 19 dBm before decreasing. Figure 4-19 shows the 2fo DE for the case with both reflector networks (Pdrain2), input reflector only (Pdrain2_Input), output reflector only (Pdrain2_Output), and no reflectors (Pdrain2_NoRefl). The analysis, in each case, is the same as the CPAE and yields an optimal Pdrain2. From both Figure 4-18 and Figure 4-19 it is apparent that the reflector networks have a remarkable advantage when it comes to efficiency. This arises from the fact that 2fo output power has significantly increased with the aid of the reflector networks. Notice that the CPAE with both the input and output reflectors is the highest. In fact by adding the input reflector to the output reflector, about 5% of CPAE is gained for 17 < Pavs < 30 dBm even though there is not much output power gained. 96 30 Input and Output Reflectors 25 2fo CPAE (%) 20 Output Reflector Only 15 Input Reflector Only 10 5 0 No Reflectors -5 -10 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-18: Conversion PAE (%) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks 35 Input and Output Reflectors 30 2fo CDE (%) 25 Output Reflector Only 20 Input Reflector Only 15 No Reflectors 10 5 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 4-19: Conversion DE (%) vs. Pavs (dBm), Model B, Pinch-off Bias with Input and Output Reflector Networks 97 While these reflector networks result in a much more efficient frequency multiplier, these networks are unfortunately very narrowband. Figure 4-20 below illustrates the frequency response of this multiplier circuit (Figure 4-15) with Pavs = 30 dBm. The achieved 3-dB bandwidth of this multiplier is 0.8%. m38 2fo Output Power (dBm) 40 m38 RFFreq=3.337E9 Pout_2fo=37.771 Max 35 0.8% 30 25 20 15 10 3.50E9 3.45E9 3.40E9 3.35E9 3.30E9 3.25E9 3.20E9 3.15E9 3.10E9 3.05E9 3.00E9 Frequency (GHz) Figure 4-20: Output Power (dBm) vs. Frequency (GHz), Model B, Pinch-off Bias with Input and Output Reflector Networks The next section will present a theory to expand the bandwidth the multiplier circuit which will lead to a practical design for a wideband frequency doubler. 98 5 Wideband Multiplier Design 5.1 Introduction All discussions up to this point have been concerning narrowband frequency multipliers that utilize simple reflector networks to improve harmonic generation. In this chapter a theory is presented on how to expand the reflector network concept for a high power wideband frequency multiplier. Model B will be utilized to present the theory until the practical design where we will begin to use the Yuk Model Section 2.3.1. First we will discuss what is required in order to design a wideband frequency doubler. 5.2 Wideband Doubler Design Theory In this section we will discuss the bias point and circuit topology for the theoretical design of a wideband frequency doubler. These aspects of the doubler are determined based on previous experience in other multiplier works [9] [10] [11]. Since this is a presentation on theory, Model B will be employed. 5.2.1 Bias Point The pinch-off bias point will be used for the wideband doubler. This particular bias point has been shown to have good even harmonic generation. It was also the bias point used in [9] for the narrowband frequency doubler. As explained in Section 2.2.2 for Model B, the pinch-off bias point is VGSQ = -2.5V and VDSQ = 28V. 99 5.2.2 Circuit Topology The same circuit topology for the narrowband frequency multiplier will be used for the wideband multiplier and is repeated below in Figure 5-1. In this section, the topologies for the input network M1 and output network M2 will be discussed. Model B, discussed in Section 2.2.2, will be employed. Figure 5-1: Generic Multiplier Circuit Diagram M1 Input Network The input network for the wideband doubler will consist of a 2fo input reflector as described in Section 4.2.1. Based on previous experience in frequency doublers in [9] a 2fo input reflector is the most effective at improving 2fo harmonic generation as evidenced in Section 4.2.1. Notice that the 2fo input reflector network described in the aforementioned section is a narrowband network. This seems counterintuitive for a wideband application. As we will see in the next subsection, the widebanding technique can be achieved using a bandpass filter. The 100 microstrip realization of the bandpass filter will result in more losses than gains when used on the input. Furthermore, an input reflector does not affect harmonic generation as much as an output reflector. This has been readily evidenced in Section 4.4 where the output reflector network case showed a much larger improvement in 2fo harmonic generation than an input reflector alone. It is for these two reasons that the M1 input network has been chosen to remain as a simplistic input reflector network. M2 Output Network In this subsection we will discuss the M2 output network and present a theory that provide a method to filter and suppress the unwanted harmonics from the output across a range of frequencies. First we will examine the harmonic generation versus frequency of Model B with an fo output reflector network. The fo reflector network described in Section 3.3.1 is reused here. The fundamental and second harmonic output power versus frequency are respectively shown below in Figure 5-2a and b. Figure 5-2a displays an fo output power of approximately 40 dBm except for the narrow frequency range where the output power dips below 0 dBm. In Figure 5-2b, the 2fo output power peaks at the same frequency (3.333 GHz) that the fo output power dips. 21 The goal with the wideband doubler is to widen the range of fo output power reflection and increase the frequency range of 2fo output power. In order to widen this reflection range we will examine the S-parameters of the fo reflector network by itself. 21 In practice with a microstrip realization, the 3fo harmonic will also be suppressed since it is the secondary harmonic of the fundamental. 101 (a) 40 30 20 10 40 2fo Output Power (dBm) fo Output Power (dBm) 45 0 3.0E9 (b) 35 30 25 20 15 10 3.1E9 3.2E9 3.3E9 Frequency (GHz) 3.4E9 3.5E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 Frequency (GHz) Figure 5-2: Harmonic Output Power versus Frequency, Model B, Pinch-off Bias, fo Output Reflector Figure 5-3a, b, and c respectively show the return loss, insertion loss, and insertion loss phase versus frequency. The return loss in Figure 5-3a demonstrates the narrow frequency range over which the return loss approaches 0 dB so that |S11| = 1. At the same frequency the insertion loss also reaches a peak ( |S21|2 = 1 - |S11|2 ). Recall from Figure 5-2 that at this particular frequency, the fo output power decreased below 0 dB and the 2fo output power achieved a maximum. Therefore in order to widen the frequency response of the doubler, we must widen the frequency range over which the return loss is 0 dB (range of |S11| ). 102 140 (a) 120 Insertion Loss (dB) Return Loss (dB) 40 30 20 100 80 60 40 10 20 0 200 (b) Insertion Loss Phase (deg) 50 0 2 4 6 8 Freq (GHz) 10 (c) 100 0 -100 -200 2 4 6 8 Freq (GHz) 10 2 4 6 8 10 Freq (GHz) Figure 5-3: Selected S-parameters of fo Output Reflector Network A bandpass filter is one type of circuit that will be able to provide 0 dB return loss across a range of frequencies (or |S11| ≈ 1). The two most popular type of bandpass filters are the Chebychev or the Butterworth (maximally flat) bandpass filters. The Chebychev bandpass filter will contain an in band ripple but has a better out of band attenuation. The Butterworth bandpass filter will the most consistent in band response but may have out of band overshoot or ringing. Because a more consistent in band output power is desired, we will employ the use of an N = 3, 20% bandwidth Butterworth bandpass filter. A lumped element realization of this filter has been analyzed using ADS. The selected S-parameter response of the filter is shown below in Figure 5-4. Figure 5-4a, b, and c respectively show the return loss, insertion loss, and insertion loss phase. 103 Insertion Loss (dB) 25 Return Loss (dB) 80 (a) 20 15 10 5 (b) 60 40 20 0 0 2 4 6 8 Freq (GHz) 10 2 4 6 8 Freq (GHz) 10 200 Insertion Loss Phase (deg) 30 (c) 100 0 -100 -200 2 4 6 8 10 Freq (GHz) Figure 5-4: Selected S-parameters of N = 3, 20% Bandwidth Butterworth Bandpass Filter Notice in Figure 5-4a that the return loss now remains at 0 dB across the 2 to 4 GHz frequency range. Previously in Figure 5-3a, the return loss was only 0 dB at only 3.333 GHz. Figure 5-4b also shows the insertion loss remaining at 0 dB across a 20% bandwidth range centered around 2fo = 6.666 GHz. Now we will replace the output fo reflector network with the bandpass filter that has just been characterized. Recall from Figure 4-15 that there is a length of transmission line between the drain of Model B and the fo resonant network also called the phase line. A phase line will also be required for the bandpass filter. As was done with the fo reflector, the phase line will provide an optimal phase at which band rejected frequencies can be used to aid in harmonic generation. For the case of the broadband multiplier we will also investigate the characteristic impedance for the phase line. By changing the characteristic impedance it will assist in providing an impedance match between the bandpass filter and the drain of the device. In order to determine the optimal impedance and length of the phase line a simulation that sweeps both the line length and line impedance across a range of frequencies will be performed. This type of simulation will require a 104 specific Pavs at which to operate. 22 For this simulation Pavs = 30 dBm (1 W). Recall in Figure 4-3 that Pavs = 30 dBm produced one of the lowest 2fo output powers so operating this multiplier at this Pavs appears counterproductive. However, notice that in Figure 4-16 the highest 2fo output power occurs at the higher Pavs when there is an fo output reflector network (pink and red lines). Given the variables and numerous combinations they present, a coarse simulation will have to be performed. Once a narrow range is determined, a fine simulation can be performed. The coarse simulation will consist of a frequency sweep from 2.7 to 3.7 GHz in steps of 0.1 GHz, a phase line sweep of 10 to 90° in steps of 10°, and a phase line impedance sweep of 20 to 100 Ohms in steps of 20 Ohms. 23 The fo output power, 2fo output power, and 2fo conversion gain are respectively shown below in Figure 5-5, Figure 5-6, and Figure 5-7. For simplicity and clarity, only the selected results of the worst, average, and best performing cases are shown. 24 Figure 5-5 below shows the effect the bandpass filter has on the fo output power across the simulated frequency range. Each differently colored line represents the frequency response of the multiplier for different phase line lengths (Loutfo) and phase line impedance (Zoutfo). In this case the red, blue, and pink lines in each of the following plots respectively represent the worst, average, and best case. The worst case is given by Zoutfo = 20Ω and Loutfo = 30°. The average case is given by Zoutfo = 60Ω and Loutfo = 30°. Finally, the best case is given by Zoutfo = 100Ω and Loutfo = 50°. As was previously shown in Figure 5-2a for the narrowband case, the fo output power was only suppressed at 3.333 GHz and was approximately 40 dBm at other frequencies. Now we see for the wideband case that the fo output power is below 15 dBm across a 1 GHz range. 22 Note that with the narrowband multiplier, only a sweep versus Pavs at one specific frequency. In the case of the wideband multiplier the simulation must be performed across a range of frequencies at one specific Pavs. 23 The parameters of this simulation were chosen with consideration towards practical limitations. 24 The worst, average, and best cases were defined according to the 2fo output power and bandwidth. 105 -2 -4 -6 fo Output Power (dBm) -8 -10 -12 -14 -16 -18 -20 Zoutfo20_Loutfo30 -22 Zoutfo60_Loutfo30 -24 Zoutfo100_Loutfo50 -26 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-5: fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) Figure 5-6 and Figure 5-7 below respectively show the 2fo output power and conversion gain. Again the red, blue, and pink lines respectively show the worst, average, and best cases. Upon a close inspection of all of the results, it was determined that Loutfo= 50° and Zoutfo = 100Ω will provide the widest band of 2fo output power and conversion gain. 106 40 Zoutfo20_Loutfo30 Zoutfo60_Loutfo30 2fo Output Power (dBm) 35 Zoutfo100_Loutfo50 30 25 20 15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-6: 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) 10 Zoutfo20_Loutfo30 Zoutfo60_Loutfo30 2fo Conversion Gain (dB) 5 Zoutfo100_Loutfo50 0 -5 -10 -15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-7: 2fo Conversion Gain (dB) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) Now a fine simulation will be performed over the same frequency range but Loutfo will sweep from 45° to 55° in steps of 2° and Zoutfo will sweep from 90Ω to 100Ω in steps of 2Ω. Again for the sake of simplicity and clarity only three selected results illustrating the best, average, and worst case will be shown. The worst case is given by Zoutfo = 100Ω and 107 Loutfo = 55°. The average case is given by Zoutfo = 94Ω and Loutfo = 51°. Finally, the best case is given by Zoutfo = 100Ω and Loutfo = 45°. The 2fo output power results are presented below in Figure 5-8 followed by a zoomed in view in Figure 5-9. The 2fo conversion gain for Pavs = 30 dBm is shown in Figure 5-10 and zoomed in in Figure 5-11. 40 2fo Output Power (dBm) 35 30 25 Zoutfo100_Loutfo55 20 Zoutfo94_Loutfo51 Zoutfo100_Loutfo45 15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-8: 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) 108 40 2fo Output Power (dBm) Zoutfo100_Loutfo45 39 Zoutfo94_Loutfo51 Zoutfo100_Loutfo55 38 37 36 35 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-9: Zoomed in 2fo Output Power (dBm) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) 10 2fo Conversion Gain (dB) 5 0 -5 Zoutfo100_Loutfo55 Zoutfo94_Loutfo51 -10 Zoutfo100_Loutfo45 -15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-10: 2fo Conversion Gain (dB) vs Phase Line Length (deg) ), Line Impedance Zo (Ω), and Frequency (GHz) 109 2fo Conversion Gain (dB) 10 Zoutfo100_Loutfo45 9 Zoutfo94_Loutfo51 Zoutfo100_Loutfo55 8 7 6 5 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-11: Zoomed in 2fo Conversion Gain (dB) vs Phase Line Length (deg), Line Impedance Zo (Ω), and Frequency (GHz) Upon a close inspection of all of the results, it is determined that Loutfo = 45° and Zoutfo = 100Ω will yield the best wideband performance. The above determined phase line, with values of Loutfo = 45° and Zoutfo = 100Ω, is now placed in the multiplier circuit of Figure 5-1. The M2 output network is now placed in the doubler circuit as shown in Figure 5-12 and is simulated versus frequency. Figure 5-12: Multiplier Circuit Diagram with Output Bandpass Filter, Model B 110 The multiplier circuit is now simulated at Pavs = 30 dBm with a frequency sweep from 2.7 to 3.7 GHz in steps of 0.001 GHz. The 2fo output power of this simulation is shown below in Figure 5-13. An in-band ripple of 0.75 dB in band ripple and a 3-dB bandwidth of 21.1% has been achieved. Previously in Figure 5-2 for the narrowband case, the maximum 2fo output power was 37.7 dBm with an accompanying 8.9% bandwidth. 40 21.1% 2fo Output Power (dBm) 35 30 25 20 15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-13: 2fo Output Power (dBm) vs Frequency (GHz) The fo output power is shown below in Figure 5-14. The maximum fo output power is -10 dBm across the simulated frequency range whereas previously in Figure 5-2a the same output power was over 40 dBm except in the narrow band around 3.333 GHz, the resonant frequency of the fo output reflector. This was because the simple resonator network is, by design, effective at reflecting the fo output power at only one particular frequency. Therefore fo output power in Figure 5-14 has been reflected across this entire frequency range. Thus, Figure 5-2 and Figure 111 5-14 demonstrate the effectiveness of the bandpass filter in suppressing the fo output power and providing a wider 2fo output power response. -8 -10 fo Output Power (dBm) -12 -14 -16 -18 -20 -22 -24 -26 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-14: fo Output Power (dBm) vs Frequency (GHz) With the output network decided we will now place both M1 and M2 networks on Model B as shown in Figure 5-15 below.. The response of this circuit is then simulated over a wideband frequency range from 2.7 to 3.7 GHz. We will compare the effect of having both M1 and M2 networks on the multiplier versus only having the output bandpass filter. The 2fo output power of the entire multiplier circuit is presented in Figure 5-16 and the fo output power is presented in Figure 5-17. In both plots, the dotted red line indicates the multiplier circuit with both networks and the blue line indicates the multiplier with only the output bandpass filter. 112 Γ1(f) Θ1=90° Rgen = 50Ω Γ2(f) Θ2=45° 24Ω 50Ω c + Vg - c L L Model B Rdd = 50Ω Rdd = 0Ω RL = 50Ω VDD VGG Input 2fo Reflector Output Phase Line Output Bandpass Filter Figure 5-15: Wideband Doubler Circuit Diagram, Model B In Figure 5-16, the maximum 2fo output power for the multiplier with both networks (red line) is 40.0 dBm with a bandwidth of about 21.6%. Previously with only the output bandpass filter (blue line) the maximum output power was 39.7 dBm with a bandwidth of about 21.0%. Figure 5-17 shows the fo output power versus frequency. The same overall trend is observed with the fo output power. Because the only difference between the two cases is the addition of an input 2fo reflector network, the fo output power will not experience significant change as is observed in Figure 5-17. 113 2fo Output Power (dBm) 40 35 30 25 Input_Output_Networks 20 OutputBPFonly 15 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-16: 2fo Output Power (dBm) vs Frequency (GHz) Comparison -8 -10 fo Output Power (dBm) -12 -14 -16 -18 -20 -22 -24 Input_Output_Networks -26 OutputBPFonly -28 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-17: fo Output Power (dBm) vs Frequency (GHz) Comparison 114 As may be recalled earlier from Figure 4-18, the CPAE and CDE improved by about 5% when using both an input and output reflector network. 25 In the wideband case a similar increase in efficiency is observed. Figure 5-18 below shows a comparison of the 2fo CPAE. When using only the M2 output network, the peak CPAE is 59.4%. When using both the M1 and M2 networks, the peak CPAE is 65.9% - an improvement of 6.5%. Similarly, Figure 5-19 below shows a comparison of the 2fo CDE. When using only the M2 output network, the maximum CDE is 69.5%. In comparison, when using both the M1 and M2 networks, the maximum CDE is now 76.4% for an improvement of 6.9%. 70 60 2fo CPAE (%) 50 40 30 20 10 Input_Output_Networks 0 OutputBPFonly -10 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-18: 2fo CPAE (dBm) vs Frequency (GHz) Comparison 25 An improved efficiency was seen for large Pavs. Since this wideband multiplier is simulated with Pavs = 30 dBm, an increase in efficiency is expected. 115 80 70 2fo CDE (%) 60 50 40 30 20 Input_Output_Networks 10 OutputBPFonly 0 2.7E9 2.8E9 2.9E9 3.0E9 3.1E9 3.2E9 3.3E9 3.4E9 3.5E9 3.6E9 3.7E9 Frequency (GHz) Figure 5-19: 2fo CDE (dBm) vs Frequency (GHz) Comparison Now that a theory on a technique for widebanding the response of a frequency doubler, we will now apply this technique to a practical design. 116 6 Wideband Multiplier Design and Results In this chapter we will present design method for a practical high power wideband doubler. The complete circuit diagram of the wideband doubler utilizing ideal transmission lines is shown below in Figure 6-1. The design of this wideband doubler will utilize a realistic multi-harmonic GaN HEMT model called the Yuk Model (Section 2.3). The next section will discuss the ideal transmission line representation of the doubler circuit in parts beginning with the M1 input network and then the M2 output network. This is followed by a discussion of the Drain Bias Network as illustrated in Figure 6-1. Each M1 and M2 network is compared to the corresponding networks used in the Model B wideband doubler that was discussed in Section 5.2.2. Next the harmonic generation of the wideband doubler utilizing ideal transmission lines is presented. The ideal transmission lines models (ADS component, TLIN) are then replaced with the microstrip model (ADS component, MLIN). The two multipliers’ responses are then compared. Section 6.2 is a presentation of the S-parameters of the fabricated M1 and M2 networks’ responses compared with their ADS simulated responses. Then the harmonic generation of the fabricated wideband doubler is compared with the simulated microstrip version. These results are similar to the ones presented in [11]. 117 Figure 6-1: Idealized Practical Wideband Doubler Circuit Diagram 6.1 Practical Wideband Doubler Design In this section we will apply the widebanding theory presented in Section 5.2 to a practical doubler design and is the same design shown in [11]. All simulations prior to this section have utilized simplified transistor models. For the practical design described in this section, the more realistic Yuk Model (described in Section 2.3.1) must be used. The practical design will be discussed in parts (M1, M2, and Drain Bias Network) as was illustrated in Figure 6-1. All subnetworks shown in Figure 6-1 are first realized in ADS utilizing ideal transmission line elements (TLIN). These networks are compared with the corresponding lumped element networks that utilized Model B (presented in Section 5.2.2, Figure 5-15). Then the sub-networks in Figure 6-1 are synthesized as microstrip elements in ADS utilizing the Rogers RT/Duroid 5880 substrate parameters (MLIN) and compared with the ideal transmission line networks. 118 6.1.1 Circuit Design and Description M1 Input Network The M1 input network Model B described in Section 5.2.2 is a simple 2fo input reflector utilizing a method presented in Section 4.2.1 to find the length of transmission line for optimal phasing. The same circuit topology and design method are used to design the M1 input network shown in Figure 6-1. The length of transmission line for optimal phasing was found to be 22° with respect to fo and has an impedance of 50Ω. The reflector itself is synthesized as a 50Ω open circuited ideal transmission line with a length of 45° with respect to fo 26. Below in Figure 6-2 is a comparison between the insertion loss of this newly designed M1 input network (utilizing ideal transmission lines, Jansen model) to the M1 input network from Section 4.2.1 (utilizing lumped elements). Both the Model B and Yuk Model M1 networks were simulated without the DC bias networks. 26 Notice that when referring to fo or 2fo, it means the center fundamental or second harmonic across a 20% bandwidth. For fo this means 3.333 GHz and consequently 2fo means 6.666 GHz. 119 40 10 (a) 80 (b) 9 30 Return Loss (dB) 60 7 VSWR Insertion Loss (dB) (c) 70 20 10 5 50 40 30 20 3 10 0 0 1 Freq (GHz) 12 11 9 7 Freq (GHz) 8 5 7 3 6 1 5 5 6 7 8 Freq (GHz) Figure 6-2: Comparison Selected S-parameters of M1 network, Model B (red), Yuk Model (blue dotted) 27 M2 Output Network The M2 output network for Model B that was shown in Figure 5-12 involves the use of a bandpass filter and a phase line. The same type of network will be used here on the Yuk Model. As shown in Figure 6-1, the phase line has been synthesized as an ideal transmission line having an impedance of 24Ω and length 29°. In the same figure, the bandpass filter is realized as an N = 3, 20% bandwidth side-coupled ideal transmission line bandpass filter. Below in Figure 6-3 is a comparison of the M2 output network for the Yuk Model (blue dotted line) with the M2 network used with Model B that was described in Section 5.2.2 (red line, utilizing lumped elements). The M2 network used for Model B exhibits shaper return and insertion losses because it was simulated as a lumped element filter. In contrast, the M2 network designed for use with the Yuk 27 Note that the network port connected to the transistor model is considered the input port when discussing the networks separately. 120 Model is simulated with ideal coupled transmission lines. Both networks were simulated without the DC bias networks. 12 10 (a) 35 (b) 9 30 Insertion Loss (dB) 7 VSWR Return Loss (dB) 10 8 6 (c) 5 4 3 2 25 20 15 10 5 0 1 5 6 7 8 9 Freq (GHz) 0 5 6 7 8 9 Freq (GHz) 5 6 7 8 9 Freq (GHz) Figure 6-3: Comparison Selected S-parameters of M2 network, Model B (red), Yuk Model (blue dotted) Notice that due to the coupled transmission lines, DC cannot be applied as has been done previously in [10] to the output of the M2 output network. This presents a problem for the DC bias on the drain and will require a specially designed bias network. A specialized drain bias network was used in [11] to present a bias to the drain of the transistor due to the M2 network having a coupled line element. The bias network described here is a more practical and stable version of the bias network in [11]. This bias network has a few requirements: 1) It must be able to pass the DC drain bias to the transistor. 2) The bias network should be “invisible” at 2fo so as to not disturb the 2fo output power from reaching the bandpass filter. 3) It must choke and reflect the fo (and to a lesser extent the 3fo) output power back towards the drain of the device. 4) It must maintain a simple circuit so as to reduce circuit losses. 121 In order to meet these requirements the bias network will also contain bypass capacitors. A circuit diagram of the bias network is shown below in Figure 6-4. Port 1 connects to the drain of the device. Port 2 connects to the bandpass filter. And finally, Port 3 connects to the DC drain bias supply. The 100Ω transmission line in conjunction with the 20 pF capacitor aids in choking out the fo output power. Notice that in order be effective the capacitor must be placed at exactly 45° from the main branch of the circuit. Only DC power should be present beyond the capacitor. The two 50Ω transmission lines on Ports 1 and 2 have no bearing on the bias network and are not used on the multiplier circuit. 28 Figure 6-4: Circuit Diagram of Specialized Drain Bias Network 28 In the multiplier circuit, Ports 1 and 2 respectively connect to the phase line and the bandpass filter without the use of the 50Ω transmission lines shown in Figure 6-4. 122 Selected S-parameters of the bias network are shown below in Figure 6-5 and Figure 6-6. Figure 6-5a and 6-6a respectively show the return loss for 2fo is about 50.5 dB and the insertion loss is about 0 dB. This means that the bias network has little effect at 2fo. At fo, the return loss is 11.9 dB and the insertion loss is 0.3 dB. This shows that the fo is essentially being choked out from the circuit as designed. Figure 6-6b shows the S-parameter response at Port 3 given an excitation from Port 1 (S(3,1)). Across the range of frequencies that the multiplier will experience, all losses are 45 dB or less. 29 These results demonstrate the feasibility of the bias network which is now placed in the multiplier circuit. The capacitors are realized by soldering on lumped element capacitors and connecting them to a ground via. 100 11 (a) 9 Input VSWR Return Loss (dB) 80 (b) 60 40 7 5 20 3 0 1 12 11 9 7 5 3 1 12 11 9 7 5 3 1 Freq (GHz) Freq (GHz) Figure 6-5: Return Loss (dB) and VSWR of Drain Bias Network 29 In practice, another external bias-T is used in order to further eliminate any sinusoidal signal to prevent it from entering the DC drain bias supply. 123 (a) Insertion Loss (dB) 5 4 3 2 1 0 50 DC Port to AC Port Isolation (dB) 6 (b) 45 40 35 30 25 20 15 10 12 11 9 7 5 3 1 12 11 9 7 5 3 1 Freq (GHz) Freq (GHz) Figure 6-6: Insertion Loss (dB) and DC/AC Isolation (dB) of Drain Bias Network The complete circuit diagram of the doubler described in this section utilizing ideal transmission line elements was shown in Figure 6-1 and is the same figure that was shown in [1]. Now we will analyze the harmonic generation of this (Figure 6-1) circuit. 6.1.2 Simulated Wideband Doubler Circuit Performance Ideal Transmission Line Wideband Doubler Performance The 2fo output power of the ideal wideband doubler is presented below in Figure 6-7 with Pavs = 30 dBm. A 16.7% 3-dB bandwidth has been achieved with a 0.3 dB variation at the plateau of the response. This result presents a question as to why the bandwidth is not the expected 20% that the bandpass filter was designed for. Recall in Section 5.2.2 that the 20% bandwidth was achieved with a 20% bandpass filter for Model B. Model B was an idealized transistor model. Here we are using the Yuk Model that realistically models the parasitics and 124 self-heating and charge trapping behavior of the actual device [2] which results in the reduced bandwidth. Also, there is a sudden decrease to 27.4 dBm of 2fo output power at f = 3.130 GHz. Figure 6-8 below shows the 2fo output power of the same circuit but without the specialized drain bias network. This response has no sudden decreases and has higher overall 2fo output power unlike in Figure 6-7. Hence the decrease in output power at f = 3.130 GHz can be attributed to the specialized drain bias network. More specifically, it was found that the length of transmission line (TL8) between the bypass capacitor in Figure 6-4 and the 50Ω transmission lines affects the bandwidth and the location of the dip in the 2fo output power. While there are certain lengths of TL8 that will eliminate the dip, it is at the cost of output power, bandwidth, and the bias network’s ability to choke out unwanted frequencies. The entire bias network does not have a large effect on the bandwidth of the doubler as shown by the 0.1% decrease in Figure 6-8. Given these circumstances, the specialized drain bias network may not be the best option to use and other biasing options can be explored but for the purposes in this thesis it will suffice. 125 2fo Output Power (dBm) 32 30 28 16.7% 26 24 22 20 18 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-7: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network 2fo Output Power (dBm) 35 30 16.6% 25 20 15 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-8: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit without Specialized Drain Bias Network 126 Below in Figure 6-9 is a plot of the 2fo conversion gain versus fundamental input frequency with the specialized drain bias network. Because the circuit is simulated with Pavs = 30 dBm, and the 2fo output power was at most 28.8 dBm, there is an in-band conversion gain ranging from 0.12 dB to -2.9 dB. It may be recalled from Section 5.2.2 where the Model B wideband doubler was discussed (Figure 5-15), there was a significant conversion gain for that case. This can be attributed to the fact that we are now using the realistic Yuk Model instead of an idealized Model B. Figure 6-2 and Figure 6-3 show the reduced quality factor (Q-factor) of the ideal transmission line networks when compared to the lumped element networks. This would initially lead one to believe that the reduced Q-factor has resulted in the reduced gain of the circuit. To increase the Q-factor of these circuits, the characteristic impedance of the transmission lines must be increased. As an example we will later show that increasing the characteristic impedance of the 2fo input reflector stub will increase the Q-factor but at an expense. 127 2fo Conversion Gain (dB) 2 0 -2 -4 -6 -8 -10 -12 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-9: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network Below in Figure 6-10 is the 2fo CPAE versus frequency of the wideband doubler with the specialized drain bias network. The maximum achieved CPAE is 0.13%. Previously in the Model B case of Figure 5-18, there was a maximum 65.9% CPAE. The reason for the greatly reduced CPAE here is again due to the more realistic Yuk Model ([2]) and the lower Q-factor of the microstrip line. In the next subsection we will explore the effects of increasing the characteristic impedance of the 2fo input reflector. 128 1 2fo CPAE (%) 0 -1 -2 -3 -4 -5 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-10: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with Specialized Drain Bias Network 2fo Input Reflector Stub Q-Factor To demonstrate the effect of the Q-factor on the networks, the characteristic impedance of the 2fo input reflector stub in Figure 6-1 was changed from 50Ω to 60 and 75Ω. Afterwards, we will also examine the effects of decreasing the characteristic impedance below 50Ω. Each of these reflector stubs were re-simulated in the wideband circuit. The 2fo output power of each of these circuits is presented below in Figure 6-11. The red, blue, and pink lines each represent the Zo = 50, 60, and 75Ω cases, respectively. The Zo = 50Ω (red line) has a bandwidth of 16.7%. For Zo = 60Ω (blue line), the gain decreases but the bandwidth has increased to 17.0%. Finally for Zo = 75Ω (pink line), the gain decreases even further but the bandwidth is now 17.3%. 129 31 Pout2_50ohm 30 2fo Output Power (dBm) Pout2_60ohm Pout2_75ohm 28 26 24 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-11: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub Figure 6-12 below shows the conversion gain versus frequency for each of these cases. Again the Zo = 50, 60, and 75Ω cases are each respectively represented by the red, blue and pink lines. The conversion gain is observed to decrease as the Zo increases however the bandwidth is gradually increasing in the same manner as the output power. 2fo Conversion Gain (dB) 1 CG_50ohm 0 CG_60ohm -1 CG_75ohm -2 -3 -4 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-12: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub 130 Below in Figure 6-13 is the 2fo CPAE comparison between the different cases. Here again the 50, 60, and 75Ω cases are illustrated by the red, blue, and pink lines, respectively. The CPAE is highest for the 50Ω case, but has more variation for the in band response than the 75Ω case. 2 PAE2_50ohm 0 2fo CPAE (%) -2 PAE2_60ohm -4 PAE2_75ohm -6 -8 -10 -12 -14 -16 -18 -20 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-13: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 60, and 75 Ω Input Reflector Stub It appears that the higher impedance will only provide minimal improvement in bandwidth while sacrificing output power, conversion gain, and CPAE. This seems contrary to the expected increase in gain as the Q-factor of the network is increased. An explanation for this will follow. Now we will examine the effects of decreasing the characteristic impedance of the stub on the 2fo input reflector to 20, 30, and 40Ω. The 2fo output power is shown below in Figure 6-14 where the 50, 20, 30, and 40Ω response are respectively represented by the red, blue, pink, and green lines. With the 2fo input reflector stub’s characteristic impedance at 30Ω (pink line) the highest output power across the entire band is achieved but with only 14.7% 3-dB bandwidth. Comparatively the 50Ω response (red line) has 16.7% 3-dB bandwidth. Decreasing the 131 characteristic impedance even further to 20Ω reduces the 3-dB bandwidth to 7.8% while maintaining roughly the same amount of 2fo output power as the 30Ω case. Since 40Ω is pretty close to 50Ω, the bandwidth is only decreased to 16.6%, a difference of 0.1% from the 50Ω case. 30 2fo Output Power (dBm) 35 Pout2_50ohm Pout2_20ohm Pout2_30ohm 30 Pout2_40ohm 25 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Frequency (GHz) Figure 6-14: 2fo Output Power (dBm) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30 and 40 Ω Input Reflector Stub Figure 6-15 below is the 2fo conversion gain versus frequency of the same series of simulations on the 2fo input reflector stub. Again we see that while the conversion gain has overall increased with the 30Ω case (pink line) the bandwidth has decreased and the 50Ω case still has the most bandwidth (red line). Finally, Figure 6-16 shows the 2fo CPAE versus frequency with the 2fo input reflector stub at characteristic impedances of 20 (blue), 30 (pink), 40 (green), and 50Ω (red). With the characteristic impedances at 20 and 40Ω, the CPAE is highest at about 6%. While the 50Ω case will have the most bandwidth, it will have the least CPAE overall. 30 With such a small difference in the bandwidth, the decision to change the characteristic impedance of the 2fo input reflector stub is at the discretion of the designer. 132 2fo Conversion Gain (dB) 5 CG_50ohm 3 CG_20ohm 1 CG_30ohm CG_40ohm -1 -3 -5 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Frequency (GHz) 2fo CPAE (%) Figure 6-15: 2fo Conversion Gain (dB) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30, and 40 Ω Input Reflector Stub 10 8 6 4 2 0 -2 -4 -6 -8 -10 PAE2_50ohm PAE2_20ohm PAE2_30ohm PAE2_40ohm 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Frequency (GHz) Figure 6-16: 2fo CPAE (%) vs. Frequency (GHz), Ideal Wideband Circuit with 50, 20, 30, and 40 Ω Input Reflector Stub It has been observed that lowering the characteristic impedance (and consequently the Qfactor) of the input reflector stub actually increases the gain of the wideband doubler. Again it was expected that increasing the Q-factor would increase the gain. To explain this we will look at the insertion loss and VSWR of the reflector network shown below in Figure 6-17 and Figure 6-18, respectively. In Figure 6-17 at f = 3.333 GHz, the insertion loss decreases as the characteristic impedance of the reflector stub decreases. Furthermore, it illustrates an insertion 133 loss range of about 2 to 10 dB as characteristic impedance increases from 20 to 75Ω. At the same frequency (fo = 3.333 GHz), Figure 6-18 shows a decreasing VSWR as the characteristic impedance increases. These two plots show that as the characteristic impedance decreases, the insertion loss increases and therefore more fo power can be transferred from the source to the gate. With less fo power at the gate, less power is available to generate more 2fo output power. To confirm this we place the various 2fo reflector network stubs in the wideband doubler simulation and observe the fundamental power at the gate of the Yuk Model. 25 S11_20ohm S11_30ohm Insertion Loss (dB) 20 S11_40ohm f = 3.333 GHz S11_50ohm 15 S11_60ohm 10 S11_75ohm 5 0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-17: Insertion Loss (dB) vs. Frequency (GHz) 2fo Input Reflector Network with Varying Stub Impedance 134 10 9 VSWR_20ohm VSWR_30ohm VSWR 7 VSWR_40ohm VSWR_50ohm 5 VSWR_60ohm VSWR_75ohm 3 f = 3.333 GHz 1 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-18: VSWR vs. Frequency (GHz) 2fo Input Reflector Network with Varying Stub Impedance Figure 6-19 and Figure 6-20 below show the power at the gate at the fundamental frequency versus frequency. Figure 6-19 shows the power at the gate for stub characteristic impedances of 50, 60, and 75Ω. Figure 6-20 shows the gate power for characteristic impedances of the stub of 20, 30, 40, and 50Ω. Both figures illustrate that as characteristic impedance decreases, the fo gate power increases. For example, in Figure 6-19 at 3.333 GHz, we see that the 50Ω stub and 75Ω stub case have a 1 dBm difference in fo power at the gate. As a result a 0.9 dBm difference occurs in the 2fo output power at the drain for the same frequency and impedances as illustrated in Figure 6-11. In another example, in Figure 6-20, the fo power at the gate at 3.333 GHz is about 19 dBm for the 30Ω stub and about 17.4 dBm for the 50Ω stub for a 1.5 dBm difference. This resulted in approximately 1.3 dBm difference in 2fo output power at 3.333 GHz as illustrated in Figure 6-14. 135 21 Pgate_50hm Pgate (dBm) 20 Pgate_60hm 19 Pgate_75ohm 18 17 16 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Frequency (GHz) Figure 6-19: Pgate (dBm) vs. Frequency (GHz) 2fo Input Reflector Network with Varying 2fo Input Reflector Stub Impedance Pgate (dBm) 21.0 20.5 Pgate_50hm 20.0 Pgate_20ohm 19.5 Pgate_30hm 19.0 Pgate_40hm 18.5 18.0 17.5 17.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Frequency (GHz) Figure 6-20: Pgate (dBm) vs. Frequency (GHz) 2fo Input Reflector Network with Varying 2fo Input Reflector Stub Impedance These plots demonstrate that increasing the amount of fo power at the gate will result in more 2fo output power. 31 It also confirms the fact that in the wideband case, increasing the Qfactor of the input reflector network will not result in increased 2fo output power. 31 These findings present a strong argument for the use of an input matching network. 136 With the data presented in this section, it is apparent that by increasing the characteristic impedance of the 2fo input reflector stub will provide a slight increase in bandwidth at the expense of output power, conversion gain, and efficiency. However by increasing the characteristic impedance the gains in bandwidth are actually minimal compared to the risk of circuit burn out [6]. Also, it has been evidenced that by decreasing the characteristic impedance a higher output power, conversion gain, and efficiency can be achieved at the cost of bandwidth. Since the wideband doubler for this thesis is primarily concerned with bandwidth and output power, the decision was made to keep the characteristic impedance of the 2fo input reflector stub at 50Ω. Ideal Transmission Lines versus Microstrip Lines Now the individual M1 input and M2 output networks are realized using microstrip models in ADS. The dimensions for each microstrip line element were obtained from LineCalc using the substrate parameters of a Rogers RT/Duroid 5880 board. First we will analyze these networks individually and compare them against the ideal transmission line versions. M1 Input Network Below in Figure 6-21 is the VSWR, return loss, and return loss phase of the M1 input network in an ideal transmission line (red) and microstrip line (blue) simulation. 32 Figure 6-21a, b, and c agree almost exactly. 32 Remember that when discussing the networks individually, port 1 on the M1 input network is the port that connects to the gate of the transistor. 137 VSWR 7 5 3 15 10 5 0 1 (c) 100 0 -100 -200 10 9 7 5 3 Freq (GHz) 1 10 9 7 5 3 1 10 9 7 5 3 1 Freq (GHz) 200 (b) Return Loss Phase (deg) 9 20 (a) Return Loss (dB) 10 Freq (GHz) Figure 6-21: Ideal Transmission line and Microstrip Comparision, Ideal (Red) Microstrip (Blue) Figure 6-22 below is the insertion loss and insertion loss phase comparison between the ideal transmission line (red) and microstrip line (blue) simulations of the M1 input network. Figure 6-22a in particular shows the insertion loss of the ideal (red) network to be higher than that of the microstrip network. This is because the ideal transmission lines will have a higher Qfactor than the microstrip version. The microstrip version can achieve a higher Q-factor if the characteristic impedance increases. However due to practical limitations in manufacturing and the risk of burn out, the impedance cannot be increased beyond a certain limit. 138 60 Insertion Loss Phase (deg) 50 Insertion Loss (dB) 100 (a) 40 30 20 10 0 (b) 50 0 -50 -100 -150 10 9 7 5 3 1 10 9 7 5 3 1 Freq (GHz) Freq (GHz) Figure 6-22: Ideal Transmission line and Microstrip Comparision, Ideal (Red) Microstrip (Blue) 139 M2 Output Network Below in Figure 6-23 and Figure 6-24 is a comparison of the M2 output network in an ideal transmission line (red) and microstrip line (blue) simulation. The VSWR, return loss, and return loss phase respectively in Figure 6-23a, b, and c are all closely matched. 10 6 (a) 200 (b) 9 Return Loss (dB) VSWR 5 Return Loss Phase (deg) 5 7 4 3 2 3 1 50 0 -50 -100 -200 10 9 7 5 3 1 Freq (GHz) 10 9 7 5 3 1 10 9 7 5 3 1 Freq (GHz) 100 -150 0 1 (c) 150 Freq (GHz) Figure 6-23: Ideal Transmission line and Microstrip Comparision M2 Output Network, Ideal (Red) Microstrip (Blue) It is important to note that in Figure 6-23a and b that the VSWR at fo = 3.333 GHz is extremely high, indicating that the M2 network is an excellent reflector at the fundamental frequency (fo = 3.333 GHz). The insertion loss in Figure 6-24a agrees closely except in the 1-4 GHz and 9-10 GHz ranges. However since this is considered outside the target 20% bandwidth of the wideband doubler it will not be an issue. The insertion loss phase in Figure 6-24b also agrees very closely across the entire range. Finally, in Figure 6-24c is the DC to AC port isolation comparison where the microstrip version of the circuit (blue) has better isolation than the ideal version (red). This can be attributed to the fact that the microstrip model is more realistic and has parasitics that would therefore result in better DC to AC isolation. 140 80 200 (a) 70 40 30 20 DC to AC Port Isolation (dB) Insertion Loss Phase (deg) 50 (c) 200 150 60 Insertion Loss (dB) 210 (b) 100 50 0 -50 -100 190 180 170 160 150 140 10 -150 130 0 -200 120 10 9 7 5 3 1 Freq (GHz) 10 9 7 5 3 1 10 9 7 5 3 1 Freq (GHz) Freq (GHz) Figure 6-24: Ideal Transmission line and Microstrip Comparision M2 Output Network, Ideal (Red) Microstrip (Blue) Now we will move on to analyzing the microstrip implementation shown below in Figure 6-25 and compare the simulation with the ideal transmission line circuit which was illustrated in Figure 6-1. Again, these dimensions were calculated using LineCalc in ADS with the substrate parameters of a Rogers RT/Duroid 5880 board. 141 Figure 6-25: Microstrip Representation of Wideband Frequency Doubler Figure 6-26 illustrates the 2fo output power versus frequency simulations of the ideal transmission line and microstrip line wideband multipliers. The red line is the ideal transmission line version of the wideband multiplier that is shown in Figure 6-1. The blue line is the microstrip version of the wideband multiplier that is shown in Figure 6-25. As expected with the additional circuit losses, the microstrip version has a lower overall gain across the band with about 16.7% bandwidth. In contrast, the ideal version has more gain while still maintaining roughly the same 16.7% bandwidth. 142 2fo Output Power (dBm) 32 30 28 26 24 22 Ideal 20 Microstrip 18 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-26: 2fo Output Power (dBm) versus Frequency (GHz), Ideal and Microstrip Comparison Because the microstrip model in ADS is a more realistic representation that includes more losses, less fo output power is transmitted to the output than in the ideal case as illustrated in Figure 6-27 below. Figure 6-28 below shows the 2fo conversion gain versus frequency between the microstrip (blue) and ideal transmission line (red) simulations of the wideband doubler. As was seen in Figure 6-26, the 2fo output power was higher for the ideal case than the microstrip line case. Hence the maximum conversion gain for the microstrip version is -0.36 dB compared to the maximum +0.12 dB of the ideal transmission line case. For both cases, the bandwidth is 16.7%. 143 -6 fo Output Power (dBm) -8 -10 -12 -14 -16 -18 Ideal -20 Microstrip -22 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-27: fo Output Power (dBm) versus Frequency (GHz), Ideal and Microstrip Comparison 144 2fo Conversion Gain (dB) 2 0 -2 -4 -6 -8 Ideal -10 Microstrip -12 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-28: 2fo Conversion Gain (dB) versus Frequency (GHz), Ideal and Microstrip Comparison Figure 6-29 below shows the 2fo CPAE versus frequency between the microstrip (blue) and ideal transmission line simulations (red) of the wideband doubler. The CPAE for the ideal circuit (red line) is consistently 0.3% higher than the microstrip circuit (blue line). Again this can be attributed to the additional losses resulting from a more realistic transmission line model. The 3-dB bandwidth for each case has been previously defined in Figure 6-26. For the microstrip case the minimum in band CPAE is -2.74% while the ideal transmission line case has a minimum in band CPAE of -2.47%. 145 1 2fo CPAE (%) 0 -1 -2 -3 Ideal -4 Microstrip -5 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Fundamental Input Frequency (GHz) Figure 6-29: 2fo CPAE (%) versus Frequency (GHz), Ideal and Microstrip Comparison Now that a microstrip version of the circuit has been simulated and agrees closely with the ideal transmission line version we can build and test the circuit. In the next section, the measured circuit will be compared to the microstrip simulation of the circuit that was presented in Figure 6-25. 6.2 GaN Wideband Doubler Results The wideband doubler networks described in Section 5.3 were synthesized in to microstrip networks and fabricated Rogers RT/Duroid 5880 substrate and tested. Prior to final circuit assembly and measurement, each network was individually tested on an Agilent 8364B PNA. The results for each network are presented in the following paragraphs. 146 M1 Input Network The measured S-parameters of the fabricated input network are compared below to the simulated S-parameter response. 33 This network has been tuned using the PNA (power network analyzer) by adjusting the length of the shunt microstrip stub on the 2fo input reflector to improve response. 20 Meas_S11 Sim_S11 Return Loss (dB) 15 10 5 0 -5 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-30: Return Loss (dB) vs. Frequency (GHz) of Measured Input Network 33 It is important to note that the data labels showing S11 actually refer to the port on the input network that is connected to the gate of the transistor. 147 150 Meas_S11ph 100 Sim_S11ph 50 0 -50 -100 -150 -200 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-31: Return Loss Phase (deg) vs. Frequency (GHz) of Measured Input Network 50 Meas_S21 Sim_S21 40 Insertion Loss (dB) Return Loss Phase (deg) 200 30 20 10 0 2 3 4 5 6 7 8 9 Frequency (GHz) Figure 6-32: Insertion Loss (dB) vs. Frequency (GHz) of Measured Input Network 10 148 200 Insertion Loss Phase (deg) Meas_S21ph Sim_S21ph 100 0 -100 -200 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-33: Insertion Loss Phase (deg) vs. Frequency (GHz) of Measured Input Network The results in Figure 6-30, Figure 6-31, and Figure 6-32 agree very closely with the simulated results. Figure 6-33, however, shows a large difference between simulated and measured. This may be due to human error in the manufacturing process where obtaining the exact insertion loss phase is very difficult. However this is not as important since the phasing that is presented to the gate of the transistor (called S11 here) will determine the effectiveness of the 2fo input reflector. M2 Output Network Now we will examine the measured S-parameter results of the ideal M2 output network described in Section 5.3 and compare it with the simulation of the M2 output network responses of Figures 6-23 and 6-24. The results presented in this section include the bias network. 34 This network was not tuned. 35 The measured and simulated input return loss and phase for M2 are shown versus frequency in Figures 6-34 and 6-35, respectively. The VSWR is shown in Figure 6-36. The input return loss and phase agree closely with the simulated responses especially 34 For the S-parameter measurement, the bias network port was terminated in a 50 Ohm load. Otherwise it is terminated in the Vdd bias shown in Figure 6-25 35 The output M2 network was not tuned because of the difficulty in symmetrically tuning the bandpass filter. The filter was realized as a side-coupled bandpass filter with a very narrow coupling between the microstrip lines. 149 where it counts at fo = 3.333 GHz (the measured value is, fortuitously even better at 2fo). It is difficult to obtain an exact match with the simulated response due to losses in the microstrip to SMA connection. 2 0 Input Return Loss (dB) -2 -4 -6 -8 -10 -12 meas_S11 -14 sim_S11 -16 -18 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-34: Input Return Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network 200 meas_S11ph Input Return Loss Phase (deg) 150 sim_S11ph 100 50 0 -50 -100 -150 -200 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-35: Input Return Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network 150 10 sim_VSWR 9 meas_VSWR Input VSWR 7 5 3 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-36: Input VSWR vs. Frequency (GHz) of Measured and Simulated Output Network The measured and simulated M2 insertion loss and phase are respectively shown in Figure 6-37 and Figure 6-38. The measured response is a little bit off from the simulated response. However notice that around 6.666 GHz, the insertion loss and phase agree very closely. This is important considering the desired bandwidth of the multiplier circuit. The 3-dB bandwidth of the insertion loss of the network is found to be 14.1%. 151 0 14.1% Insertion Loss (dB) -20 -40 -60 meas_S21 -80 sim_S21 -100 5 6 7 8 9 10 Frequency (GHz) Figure 6-37: Insertion Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network 200 Insertion Loss Phase (deg) meas_S21ph sim_S21ph 100 0 -100 -200 5 6 7 8 9 10 Frequency (GHz) Figure 6-38: Insertion Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network The output return loss and phase are respectively shown in Figure 6-39 and Figure 6-40. And finally the output VSWR is shown in Figure 6-41. Again it is difficult to have the measured 152 response match the simulated response closely due to manufacturing errors and the fact that given what was available the circuit was not tunable. 10 Output Return Loss (dB) 0 -10 -20 -30 meas_S22 -40 sim_S22 -50 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-39: Output Return Loss (dB) vs. Frequency (GHz) of Measured and Simulated Output Network 200 meas_S22ph Output Return Loss Phase (deg) 150 sim_S22ph 100 50 0 -50 -100 -150 -200 2 3 4 5 6 7 8 9 10 Frequency (GHz) Figure 6-40: Output Return Loss Phase (deg) vs. Frequency (GHz) of Measured and Simulated Output Network 153 Output VSWR 10 9 sim_VSWR2 8 meas_VSWR2 7 6 5 4 3 2 1 5 6 7 8 9 10 Frequency (GHz) Figure 6-41: Output VSWR vs. Frequency (GHz) of Measured and Simulated Output Network Wideband Doubler Response Now we will look at the measured wideband doubler response with Pavs = 30 dBm. Similar results have been presented in [11]. Figure 6-42 shows the 2fo output power versus frequency. For Pavs = 30 dBm, a maximum 30.2 dBm of 2fo output power with 13.3% bandwidth has been achieved and is close to the simulated response. 154 2fo Output Power (dBm) 35 30 25 20 measured_xtrALPHA simulated 15 3.0 3.1 3.2 3.3 3.4 3.5 3.6 Fundamental Frequency (GHz) Figure 6-42: 2fo Output Power (dBm) vs. Frequency (GHz) Below in Figure 6-43 is the 2fo conversion gain versus frequency at Pavs = 30 dBm. A maximum 0.2 dB conversion gain has been achieved and is close to the simulated response. 155 2fo Conversion Gain (dB) 5 0 -5 -10 CG2 -15 CG2_sim -20 3.0 3.2 3.4 3.6 Fundamental Frequency (GHz) Figure 6-43: 2fo Conversion Gain (dB) vs. Frequency (GHz) Figure 6-44 below shows the measured and simulated 2fo power added efficiency (PAE) versus frequency for Pavs = 30 dBm. The maximum achieved PAE is 0.1% and the minimum in band PAE is -1.8% over the bandwidth defined by the 2fo output power in Figure 6-42. 156 1 0 PAE (%) -1 -2 -3 PAE2 -4 PAE2_sim -5 3.0 3.2 3.4 3.6 Fundamental Frequency (GHz) Figure 6-44: 2fo PAE (%) vs. Frequency (GHz) The drain efficiency for the second harmonic has also been determined. Figure 6-45 shows the measured and simulated 2fo drain efficiency (DE), or η versus frequency for Pavs = 30 dBm. The minimum and maximum drain efficiencies across the band are 2.4% and 4.8%, respectively. 157 5 Eta (%) 4 3 2 DrainEff 1 DrainEff_sim 0 3.0 3.2 3.4 3.6 Fundamental Frequency (GHz) Figure 6-45: 2fo Drain Efficiency, η, (%) vs. Frequency (GHz) In Figure 6-46 below, we compare the different harmonics versus an input power sweep simulation with Pavs =19 to 36 dBm. This measurement was performed with f = 3.333 GHz. The measured 2fo output power closely matches the simulated response. The fo and 3fo output power does not match as closely and shows that there is more reflection at these harmonics than was simulated. The outcome of this is that a wideband doubler has been developed which has a 2fo output power that matches closely with simulation across a range of frequencies and across a range of Pavs. This also results in a conversion gain that matches closely with simulation. 158 40 30 2fo 20 Pout (dBm) 10 0 fo -10 -20 -30 -40 3fo -50 19 21 23 25 27 29 31 33 35 36 Pavs (dBm) Figure 6-46: Output Power (dBm) versus Pavs ( dBm) 6.3 Comparison with Narrowband Doubler Results In this section we will compare the results of the wideband multiplier to a previously documented GaN frequency doubler presented in [9]. This doubler was tested from 3.17 to 3.42 GHz with Pavs = 33 dBm with an estimated 3-dB bandwidth of 5%. In Figure 6-47 below is a comparison with the wideband doubler tested at Pavs = 30 dBm with a 13.3% bandwidth. However the peak output power of the narrowband doubler is 35.7 dBm compared to the 30.2 dBm of the narrowband doubler. 159 2fo Output Power (dBm) 40 [9] 37 34 31 28 This Work 25 3.17 3.27 3.37 3.42 Frequency (GHz) Figure 6-47: Output Power (dBm) versus Frequency (GHz) Comparison Now we will provide an estimated response of the wideband doubler with Pavs = 33 dBm to compare with the narrowband doubler below in Figure 6-48. With Pavs = 33 dBm, the bandwidth is now 13.2% compared to the estimated 5% of the narrowband doubler. Again we see that the narrowband doubler has a higher peak output power. It is expected that we would have a lower output power in order to gain a wider bandwidth. 160 2fo Output Power (dBm) 40 [9] 37 34 31 28 This Work 25 3.17 3.27 3.37 3.42 Frequency (GHz) Figure 6-48: Output Power (dBm) versus Frequency (GHz) Comparison 6.4 Summary of Frequency Multiplier Performance A wideband high power frequency doubler has been achieved. For Pavs = 30 dBm, 13.3% 3dB bandwidth and 30.2 dBm (1.05 W) of 2fo output power has been achieved. Given the same excitation it has 0.2 dB of conversion gain, 0.1% PAE, and 4.8% DE. In comparison to the narrowband doubler previously developed in [9], approximately 8.3% bandwidth has been gained at the expense of 5.5 dBm of peak 2fo output power. Even though the bandpass filter was designed with a 20% bandwidth, it was seen that the fabricated circuit only had 14% bandwidth. This and other parasitic losses in the actual GaN transistor resulted in the reduced bandwidth of 13.3%. 161 7 Conclusion A wideband high power GaN microwave frequency doubler has been achieved. The design of this doubler began with a basic analysis of harmonic generation using a simple transistor model (Model A). More complex models were then used with an analysis using narrowband input and output reflector networks which improved harmonic generation. The theory of reflector networks was then extended to a wideband theory which utilizes a bandpass filter in order to create a wideband frequency doubler. Based on the extended theory, a wideband frequency doubler was designed and tested. The resulting frequency doubler, with Pavs = 30 dBm, has a maximum 30.2 dBm of 2fo output power, 13.3% bandwidth, 0.2 dB of conversion gain, 0.2% PAE, and 4.8% DE. 162 8 Appendix 8.1 Appendix A In Section 3.1.1, Footnote 14, it was noted that an adjustment factor was added in to the DC of the conversion gain and efficiency calculations of Model A. In this appendix we will explain the reasoning behind the correction factor. First, we will illustrate why the adjustment is necessary. Then we will explain how the adjustment is found and added in to the calculations. The I-V characteristics of Model A are repeated here below in Figure 8-1 and Figure 8-2. 2.0 Ids (A) 1.5 1.0 0.5 0.0 -100 -80 -60 -40 -20 0 20 Vds (V) Figure 8-1: Ids vs. Vds, Model A 40 60 80 100 163 2.0 Ids (A) 1.5 1.0 0.5 0.0 -10 -8 -6 -4 -2 0 2 4 6 8 10 Vgs (V) Figure 8-2: Ids vs. Vgs, Model A In Figure 8-1, it can be observed that Ids is independent of Vds and is actually only dependent on Vgs as shown in Figure 8-2. We can also conclude from Figure 8-1 that Model A contains only the saturation region of operation. When Model A is subject to any AC signal excitation and terminated with a load, a load line can be superimposed on the I-V curves in Figure 8-1. Below in Figure 8-3 is such an example and is the same as Figure 3-2d. Notice that the loadline is a line of constant slope and Vds ≤ 0, the loadline continues. If Model A was to have a linear region of operation like Model B, the loadline would stop. This is illustrated in Figure 8-4 where a loadline has been superimposed onto the Model B I-V characteristics. 164 2.0 Ids (A) 1.5 1.0 0.5 0.0 -40 -20 0 20 40 60 80 100 Vds (V) Figure 8-3: Model A, Midway Bias, Ids vs. Vds with Loadline Ids (A) 1.5 1.0 0.5 0.0 0 20 40 Vds (V) 60 Figure 8-4: Model B, Midway Bias, Ids vs. Vds with Loadline 80 165 To fully understand the implications of the Model A loadlines, we must take another look at the conversion gain and drain efficiency equations which are repeated below from Section 1.5, respectively. = = − (11.1) (11.2) Recall that for Equation 11.1 (drain efficiency) and Equation 11.2 (conversion PAE), where, = + = = . (11.3) (11.4) In ADS, PGS and PDS were actually calculated using the absolute values of the products in Equation 11.4. Even when the loadline extends in to the negative VDS region, the calculated power will still be positive. Hence the denominators in Equations 11.1 and 11.2 will always be positive. The problem in these equations arises when the loadline swings in to the region where Vds ≤ 0V because the absolute value of PDC is small while the output power can be comparatively large. Recall that output power is defined as 1 = { }. 2 (11.5) 166 Ioutn is also known as the drain current. 36 Output power can increase in such a way that CPAEn or ηn become greater than 1. This is especially problematic at the fundamental frequency when the transistor model can have a lot of gain. Below in Figure 8-5 is an example showing this problem of the PAE at the fundamental. The marker indicates a PAE of 142.3% which is impossible. It will also result in higher efficiencies at the other harmonics. m26 PAE (%) 150 m26 Pow= 20.000 PAE_fo=142.345 Max 100 50 PAE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-5: Model A, Midway Bias, Fundamental PAE vs. Pavs Similarly, the conversion drain efficiency at the fundamental harmonic is shown in Figure 8-7. It shows a maximum of 143% which is again impossible. 36 We must be careful to not confused DC current with AC current. Ioutn is referring to the Ids, or drain current in AC at the nth harmonic. 167 m31 CDE (%) 150 m31 Pow= 25.000 DE_fo=143.049 Max 100 50 DE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-6: Model A, Midway Bias, Fundamental Drain Efficiency vs. Pavs To correct this, a correction factor is added to the DC power calculation. The correction factor is graphically determined from the loadline and is the amount at which the loadline extends to the left of the Vds = 0 axis (i.e. how negative Vds is). Once this value is determined graphically, it is then added in to the DC power calculation. In the case of the simulation in Figure 8-5, the correction factor was determined to be 25. The corrected PAE is shown below Figure 8-7. 168 m26 80 m26 Pow= 23.000 PAE_fo=75.311 Max PAE (%) 60 40 20 PAE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-7: Model A, Midway Bias, Corrected Fundamental PAE vs. Pavs Now the fundamental PAE has a maximum 76.3% PAE. The correction factor has the effect of mathematically shifting the loadlines from extending in to the negative Vds region. Similarly, the fundamental DE has also been corrected as shown below in m31 80 m31 Pow= 26.000 DE_fo=75.859 Max CDE (%) 60 40 20 DE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-8: Model A, Midway Bias, Corrected Fundamental Drain Efficiency vs. Pavs The other method to correct the efficiencies is to graphically shift the loadlines. This can be easily done by increasing the VDSQ, the quiescent drain bias. In all of the simulations in this thesis, VDSQ = 28V which is also the average Vds as previously explained in Section 3.1.1. The 169 amount by which the quiescent drain bias should increase in order to bring efficiency below 100% can be mathematically determined. Recall from Section 1.2 the Fourier coefficients for a symmetrically clipped waveform (as is approximately the case in a midway bias with a large signal). ⎧ ⎪2 = 0 ⎨2 1 ⎪ ⎩ = 0 ⎫ ⎪ ( ≠ 0) ⎬ ⎪ ⎭ ⎧ ⎪2 = 0 ⎨2 1 ⎪ ⎩ = 0 ⎫ ⎪ ( ≠ 0) ⎬ ⎪ ⎭ (11.6) Similarly for voltage (11.7) To obtain the power for the odd harmonic (i.e. n = 1, fundamental harmonic) we take the product of the voltage and current coefficients and divide by half. 37 Hence, for n = 1, the power is 1 1 = 1 1 2 = 1 2 2 2 =2 (11.8) 50�2 � 2 The DC power is 37 More specifically P = ½*V*conj(I). In this case, the voltage and current waveforms are in phase so all that needs to be done is a simple product. 170 = (11.9) = 1 ∗ The minimum VDSQ required to make PAE and η 100% or less is when Pds1 = PDC. With Ip = 2A as defined in Model A 38, we will find that = 100(4) ≈ 40.5 2 (11.10) We now change the ADS simulation to have VDSQ = 40.5V. The resulting PAE is shown below in Figure 8-9 with a maximum PAE of 98.5%. Similarly in Figure 8-10 the maximum drain efficiency is 99.2%. This supports our earlier analysis. 39 m26 100 m26 Pow= 20.000 PAE_fo=98.494 Max PAE (%) 80 60 40 PAE_fo 20 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-9: Model A, Midway Bias, Corrected Fundamental PAE vs. Pavs 38 See Section 2.2 It is important to remember that the correction factor only applies to simulations of Model A due to the limitations of its I-V characteristics. 39 171 m31 100 m31 Pow= 25.000 DE_fo=99.171 Max CDE (%) 80 60 40 20 DE_fo 0 -10 -5 0 5 10 15 20 25 30 Pavs (dBm) Figure 8-10: Model A, Midway Bias, Corrected Fundamental Drain Efficiency vs. Pavs

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