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Microwave Nonlinear Modeling and Active Frequency Multiplier Design for High Power Silicon-Carbide and Gallium-Nitride Field-Effect Transistors

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Microwave Nonlinear Modeling and Active Frequency Multiplier Design for
High Power Silicon-Carbide and Gallium-Nitride Field-Effect Transistors
By
KELVIN SHING-TAK YUK
B.S. (University of California, Davis) 2001
M.S. (University of California, Davis) 2004
DISSERTATION
Submitted in partial satisfaction of the requirements for the degree of
DOCTOR OF PHILOSOPHY
in
Electrical and Computer Engineering
in the
OFFICE OF GRADUATE STUDIES
of the
UNIVERSITY OF CALIFORNIA
DAVIS
Approved:
_____________________________________
G. R. Branner, Chair
_____________________________________
Neville C. Luhmann, Jr.
_____________________________________
K. Wayne Current
Committee in Charge
2012
-i-
UMI Number: 3540759
All rights reserved
INFORMATION TO ALL USERS
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In the unlikely event that the author did not send a complete manuscript
and there are missing pages, these will be noted. Also, if material had to be removed,
a note will indicate the deletion.
UMI 3540759
Published by ProQuest LLC (2012). Copyright in the Dissertation held by the Author.
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Abstract
Wide bandgap silicon-carbide (SiC) and gallium-nitride (GaN) FETs are the premier
microwave solid-state power technology and are presently being deployed in a variety of
commercial applications.
However, performance-degrading self-heating and charge-
trapping effects create new challenges for characterization and modeling of these devices.
Accurate nonlinear models capable of predicting these effects are necessary to maximally
exploit the benefits of this emerging, high power density technology.
An empirical modeling methodology for the SiC MESFET and GaN HEMT using
high power dynamic IV measurements to exploit and characterize self-heating and
charge-trapping is applied over a vast range of electrothermal operating conditions.
Nonlinear diode modeling and multibias, small-signal techniques are performed to create
complete nonlinear models for SiC and GaN FETs, which are capable of predicting DC,
pulsed, small- and large-signal RF behavior over a wide range of bias and frequency.
The presented models are valid for drain currents beyond 2A, drain voltages greater than
50V and up to 10W at RF.
These harmonically-accurate models permit the new application of CAD-based active
frequency multiplier design for wide bandgap devices. Frequency doublers and triplers
are demonstrated in SiC MESFET and GaN HEMT technology, producing some of the
highest power, single-transistor microwave frequency multipliers to date. This work
reports SiC- and GaN-based C-band frequency doublers with >5W output power and a
GaN-based X-band frequency tripler with 1W output power.
-ii-
To my baba
-iii-
Acknowledgment
I would like to thank my father, Hung Nin Yuk, and my mother, Tsu Ying Yuk, for
giving me life, love and support. I would also like to thank my brother, Michael Yuk,
and his family for all of his love and support.
I would like to thank Prof. G. R. Branner, Prof. K. W. Current and Prof. N. C.
Luhmann, Jr. for looking after me all these years and for teaching, encouraging and
challenging me to do the best work that I can.
I would like to thank the Japanese American Student Society 2009-2011 who, without
judgment, welcomed me and re-taught me the meaning of friendship when I needed
someone the most.
Lastly, I would like to thank Monica Lee for the many nights you spent with me in
the lab, patient and unwavering. This work belongs to you too.
-iv-
Table of Contents
CHAPTER 1. INTRODUCTION................................................................................1
1.1. Introduction......................................................................................................1
1.2. Importance and Development of Wide Bandgap Technology ...........................2
1.2.1.
SiC Technology........................................................................................5
1.2.2.
GaN Technology ......................................................................................9
1.2.3.
Advancements in SiC and GaN Fabrication ............................................12
1.3. Nonlinear Modeling .......................................................................................13
1.4. Active Frequency Multipliers .........................................................................15
1.5. This Work......................................................................................................19
CHAPTER 2. NONLINEAR FET MODELING .......................................................21
2.1. Introduction....................................................................................................21
2.1.1.
Device Physics .......................................................................................21
2.1.2.
Necessity of Modeling............................................................................25
2.1.3.
Large-signal FET Model Overview ........................................................25
2.1.3.1.
Physics-based Models.....................................................................26
2.1.3.2.
Empirical Models ...........................................................................26
2.1.4.
History of Empirical FET Models...........................................................29
2.1.5.
Objectives ..............................................................................................35
2.2. Technical Approach .......................................................................................37
2.2.1.
Preface to the Modeling Process .............................................................37
2.2.2.
Modeling Topology and Technical Approach .........................................38
2.2.3.
Dynamic Drain Current Modeling Using Modified Angelov...................48
2.2.3.1.
Conventional Angelov Approach ....................................................48
2.2.3.2.
Dynamic IV Characterization..........................................................53
2.2.3.3.
Drain Current Modeling Strategy ....................................................63
2.2.3.4.
SiC MESFET Drain Current ...........................................................68
2.2.3.5.
GaN HEMT Drain Current..............................................................83
2.2.3.6.
Self-heating ....................................................................................96
2.2.3.7.
Charge-trapping ............................................................................142
2.2.3.8.
Static IV Characterization .............................................................170
2.2.4.
Diodes and Parasitic Resistances Using the Fukui Method....................172
2.2.5.
Small-signal Model Identification.........................................................184
2.2.5.1.
Extrinsic FET Modeling................................................................186
2.2.5.2.
Intrinsic FET Modeling Using Hot-FET S-parameters ..................212
2.2.6.
Assembly of the Complete Large-signal Model ....................................240
2.3. Model Performance Under Small- and Large-signal RF Drive......................243
2.3.1.
SiC MESFET Large-signal Model ........................................................243
2.3.2.
GaN HEMT Large-signal Model ..........................................................250
2.3.3.
Model Performance Comparison ..........................................................260
2.4. Summary......................................................................................................262
-v-
CHAPTER 3. HIGH POWER ACTIVE FREQUENCY MULTIPLIER DESIGN...263
3.1. Overview .....................................................................................................263
3.2. Active Microwave Frequency Multiplier Theory ..........................................264
3.2.1.
Harmonic Power of a Nonlinear FET Device........................................265
3.2.2.
Limitations on Standard Conduction Angle-based Design ....................270
3.2.3.
Ideal FET Models.................................................................................274
3.2.4.
Fourier Analysis of Ideal Operating Modes...........................................295
3.2.4.1.
Single-sided Clipped.....................................................................297
3.2.4.2.
Double-sided Clipped ...................................................................314
3.2.4.3.
Unclipped .....................................................................................334
3.2.5.
Harmonic Progression Analysis ............................................................345
3.2.6.
Generic Analytical Case-based Model ..................................................366
3.2.7.
Effect of Dispersive Phenomena on Model D .......................................372
3.2.8.
Harmonic Termination Analysis Using Ideal Frequency Multiplexers...374
3.3. Frequency Multiplier Design Using High-Precision Nonlinear Models.........379
3.3.1.
Harmonically-Accurate Nonlinear Models............................................379
3.3.2.
Single-ended Frequency Multiplier Topology.......................................380
3.3.3.
Design Procedure .................................................................................381
3.4. High Power C-Band Frequency Doublers Using SiC and GaN FETs ............386
3.5. High Power X-band Frequency Tripler Using a GaN HEMT........................396
CHAPTER 4. CONCLUSION ................................................................................405
4.1. Technology ..................................................................................................405
4.2. Nonlinear Modeling .....................................................................................405
4.3. Active Frequency Multipliers .......................................................................407
APPENDIX A. MODELING ....................................................................................409
A.1. SiC MESFET Drain Current Parameters.......................................................409
A.2. Self-Heating Thermal Model Analysis .........................................................410
A.3. Substrate Trapping Model Analysis..............................................................418
A.4. Fukui-related Analyses.................................................................................428
A.5. Pinched-FET Model Analysis and Parameter Extraction ..............................431
A.6. Cold-FET Model Analysis and Parameter Extraction ...................................433
A.7. Hot-FET Model Analysis and Parameter Extraction .....................................438
APPENDIX B. FREQUENCY MULTIPLIER ..........................................................450
B.1. Power Available from an RF Source ............................................................450
B.2. Fourier Series of a Periodic Waveform.........................................................452
B.3. Summary of Fourier Coefficients for All Operating Modes ..........................460
APPENDIX C. TEST AND MEASUREMENT ........................................................463
C.1. Test Board and Fixture for Device Characterization .....................................463
C.2. IV Characterization ......................................................................................464
C.3. Small-Signal Characterization ......................................................................466
C.4. Large-Signal High-Power Harmonic Measurement System ..........................475
-vi-
APPENDIX D. ADS SCHEMATICS OF MODELS .................................................480
REFERENCES……………………………………………………………………….... 482
-vii-
List of Figures
Fig. 1-1
Fig. 1-2
Fig. 1-3
Fig. 1-4
Fig. 1-5
Fig. 2-1
Fig. 2-2
Fig. 2-3
Fig. 2-4
Fig. 2-5
Fig. 2-6
Fig. 2-7
Fig. 2-8
Fig. 2-9
Physical structure of SiC MESFET on (a) conductive SiC substrate [27] and
(b) semi-insulating SiC substrate [31]..........................................................8
Physical structure of AlGaN/GaN HEMT device [34]................................11
Frequency multipliers in various systems (a) Receiver (b) Frequency
synthesizer [61] (c) Dual-band [63] (d) Automotive Radar [66]. ................16
Passive frequency multiplier, optional filter and buffer amplifier combined
into a single active, high power frequency multiplier. ................................17
Devices under study: (a) Cree Inc. CRF-24010 10W SiC MESFET [78] and
(b) Cree Inc. CGH-40010F 10W RF Power GaN HEMT [79]....................19
Device physics of a generic MESFET device.............................................22
Device physics of a generic HEMT device [82]. ........................................24
A generalized empirical FET model. .........................................................28
Typical drain current characteristics of FET transistor. ..............................30
Generic nonlinear FET model topology. ....................................................39
Model identification process, high level flow.............................................40
Parameter optimizer/tuner conceptual block (a) basic error and parameter
modifier block (b) parameter optimizer/tuner block with model.................44
DC model showing parasitic resistances. ...................................................46
Explanation of the Angelov model from its mathematical parts (a)
I ds , a = tanh (ψ ) (b) I ds ,b = 1 + tanh (ψ ) (c) I ds ,c = I pk (1 + tanh (ψ )) (d)
I ds , d = I pk (1 + tanh (ψ )) , ψ = (V gs − V pk ) . ...................................................50
Fig. 2-10
Behavior of the Angelov model I ds , f = I pk (1 + tanh (ψ )) where
ψ = P1 (Vgs − V pk ) for different P1 values (a) I ds , e -vs- V gs and (b)
g m,e -vs- V gs . ..............................................................................................51
Fig. 2-11
Behavior of the Angelov model I ds , f = I pk (1 + tanh (ψ )) where
ψ = P1 (Vgs − V pk ) + P3 (V gs − V pk ) 3 for different P3 values (a) I ds , f -vs- V gs
Fig. 2-12
Fig. 2-13
Fig. 2-14
and (b) g m , f -vs- V gs ...................................................................................52
IV curve example (a) without dispersion and (b) with dispersion. .............54
PIV excitation on FET under test...............................................................56
PIV examples with device biased at (a) Vgsq =0V, Vdsq =0V quiescent (zero
Fig. 2-15
trapping, zero self-heating state) and (b) Vgsq =-3V, Vdsq =30V (non-zero
trapping, non-zero self-heating state).........................................................56
PGIV excitation on FET device under test. Note: The Vdsq ^ is nearly DC
Fig. 2-16
but will change slightly due to the voltage drop across Rdd when the drain
current pulses. ...........................................................................................60
PGIV examples with device biased at (a) Vgsq =-11V (non-zero trapping,
zero self-heating states) and (b) Vgsq =-5V (non-zero trapping, non-zero selfheating states)............................................................................................60
-viii-
Fig. 2-17
The evolutionary phases of I ds for the SiC MESFET model......................66
Fig. 2-18
Fig. 2-19
The evolutionary phases of I ds for the GaN HEMT model. .......................67
Measured and modeled PGIV I ds -vs- V gs characteristic. (SiC)...................70
Fig. 2-20
Algorithm for modeling I ds (V gs , Vds ) . (SiC) ...............................................72
Fig. 2-21
Algorithm for analyzing and modeling g mpk , V pk and I pk . (SiC)...............73
Fig. 2-22
PGIV-computed g m -vs- Vgs at four Vds values illustrating no peaking
Fig. 2-24
behavior except at low Vds . (SiC) ..............................................................74
(a) g mpk -vs- Vds and (b) V pk -vs- Vds extracted from PGIV at Vgsq =-11.0V.
(SiC) .........................................................................................................75
Independently modeled I ds -vs- Vgs curves at four Vds biases. (SiC)...........77
Fig. 2-25
Extracted and modeled Pn -vs- Vds (a) P1 (b) P2 (c) P3 (d) P4 . (SiC).........78
Fig. 2-26
PGIV for Vgsq =-11.0V after parameter extraction but prior to parameter
Fig. 2-23
optimization for Vgsq =-11.0V. (SiC) ..........................................................79
Fig. 2-27
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-11.0V showing I ds , g m and g ds . (SiC) ...........................................80
Fig. 2-28
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-3.0V showing I ds , g m and g ds . (SiC) .............................................81
Fig. 2-29
Comparison of I ds -vs- Vgs measured (triangles), modeled formulas (solid
lines) and those from [88] (X’s) of (a) g m -vs- Vgs and (b) I ds -vs- Vgs at
Vgsq =-3.0V, Vdsq =50V illustrating asymmetry. (GaN)................................85
Fig. 2-30
Multiplication factor M Ipk (triangles) and I ds (measured=circles,
modeled=solid lines) versus Vgs at Vgsq =-3.0V, Vdsq =50V. (GaN) .............87
Fig. 2-31
Algorithm for modeling I ds (V gs , Vds ) . (GaN) .............................................89
Fig. 2-32
PGIV-computed g m -vs- Vgs at four Vds values illustrating asymmetric
Fig. 2-33
peaking behavior at all Vds . (GaN) ............................................................91
Independently modeled I ds -vs- Vgs curves at four Vds biases. (GaN) .........92
Fig. 2-34
Extracted and modeled, P1 , P2 , P3 , M Ipkb and QM versus Vds . (GaN) ......94
Fig. 2-35
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-4.0V showing I ds , g m and g ds . (GaN)............................................95
Transient of thermal self-heating effect on drain current. ...........................97
Self-heating thermal subcircuit utilizing multiple time constants. ..............98
Self-heating thermal subcircuit utilizing single time constants. ..................99
(a) Setup for the Rth characterization (b) forward-bias gate diode
characteristics at different PD (and different temperature). ......................100
Rth extraction algorithm using forward-conduction DC measurements. ...102
Fig. 2-36
Fig. 2-37
Fig. 2-38
Fig. 2-39
Fig. 2-40
-ix-
Fig. 2-41
Measured ln( I gs ) -vs- V gs curves for Rth extraction. (SiC) .......................104
Fig. 2-42
Measured I ds , PD , ∆T and Rth versus Vds . (SiC) ...................................105
Fig. 2-43
Fig. 2-44
Fig. 2-45
Measured I ds , PD , ∆T and Rth versus PD . (SiC) ...................................105
Extracted and modeled thermal resistance Rth model (a) versus PD and (b)
versus T . (SiC) .......................................................................................107
Extracted and modeled I pk -vs- Vdsq for various Vgsq . (SiC) ......................110
Fig. 2-46
Fig. 2-47
Fig. 2-48
Modeling algorithm for thermal-varying I pkth . (SiC) ...............................112
Algorithm for computing the ∆T matrix. ................................................114
Computed and linear fit K Ipk -vs- Vdsq for each Vgsq =[-8.5:0.5:-3.0]V
Fig. 2-49
(measured=symbols, modeled=solid lines). (SiC) ....................................115
Extracted and modeled K Ipk1 and K Ipk 0 coefficients versus Vgsq . (SiC) ...116
Fig. 2-50
Fig. 2-51
Fig. 2-52
Fig. 2-53
Fig. 2-54
Fig. 2-55
Fig. 2-56
I pk ,T0 -vs- Vds extracted from the corresponding V pk =0.5V. Extracted and
modeled values shown. (SiC) ..................................................................118
Thermally-varying Pnth parameters. (SiC)................................................120
PGIV characteristics under pulsed transient excitation. Measured (symbols)
and modeled (solid lines). (SiC) ..............................................................123
I pk -, P1 -, P2 -, P3 - and M Ipkb -vs- Vds for the Vgsq =-4.0V and -2.0V cases.
(GaN)......................................................................................................126
Modeling algorithm for thermal-varying I pkth . (GaN)..............................128
Thermally-varying parameters. (GaN) .....................................................130
PGIV-based g m - and I ds -vs- V gs at Vdsq =50V for (a) Vgsq =-3.0V (b)
Vgsq =-2.1V (c) Vgsq =-1.7V. Full PGIV at (d) Vgsq =-3.0V (e) Vgsq =-2.1V (f)
Fig. 2-57
Fig. 2-58
Fig. 2-59
Fig. 2-60
Vgsq =-1.7V with quiescent biases (X’s). Measured (symbols), modeled
(solid lines). (GaN)..................................................................................135
Equivalent normalized thermal model circuit...........................................136
Long duration PGIV transient measurement and modeled using first- and
third-order thermal models. (a) Standard view and (b) Zoomed view. (SiC)
................................................................................................................139
Long duration PGIV transient measurement and modeled using first- and
third-order thermal models (a) Standard view and (b) Zoomed view. (GaN)
................................................................................................................141
PGIV
PIV
PIV
Comparison of PGIV{ V gsq
} and PIV{ V gsq
, Vdsq
} characteristics for
substrate trapping extraction (a) Case I: PGIV{ V p } vs. PIV{ V p ,0V} and (b)
Case II: PGIV{ V p } vs. PIV{ V p ,>0V}. ...................................................147
Fig. 2-61
Fig. 2-62
Fig. 2-63
Extraction of the trapping factor using I ds -vs- Vgs from PIV data and PIVexcited model. .........................................................................................150
Comparison of PIV model and PIV data for surface trapping extraction
using for a (a) high gate pulse and (b) low gate pulse...............................152
Algorithm for substrate-trapping extraction. (SiC) ...................................154
-x-
Fig. 2-64
Fig. 2-65
Fig. 2-66
Fig. 2-67
Fig. 2-68
Fig. 2-69
Fig. 2-70
Fig. 2-71
Fig. 2-72
Fig. 2-73
Fig. 2-74
Fig. 2-75
Fig. 2-76
Fig. 2-77
Fig. 2-78
Substrate trapping extraction from PIV at {0V,0V} for Vds =[12,24,36,48]V.
(SiC) .......................................................................................................155
Substrate trapping extraction from PIV at {-3V,30V} for
Vds =[12,24,36,48]V. (SiC) ......................................................................157
PIV characteristics measured and modeled at (a) {0V,0V} (b) {-3V,30V}
and (c) {-6V,48V}. (SiC) ........................................................................159
Algorithm for substrate- and surface-trapping extraction. (GaN)..............160
Substrate trapping extraction from PIV at {-3V,14V} for (a)
Vds =[12,24,36,48]V. (GaN).....................................................................162
Substrate trapping extraction from PIV at {-3V,56V} for
Vds =[12,24,36,48]V. (GaN).....................................................................163
PIV for (a) {0V,0V} (b) {-1.4V,0V} (c) {-3V,0V} with no surface trapping
model and (d) {0V,0V} (e) {-1.4V,0V} (f) {-3V,0V} with surface trapping
model. (GaN) ..........................................................................................166
PIV modeled and measured at (a) {-3V,14V} (b) {-3V, 28V} (c) {-3V,56V}
(d) {-1.1V,14V} (e) {-1.7V,28V} (f) {-2.1V,56V}. (GaN) ......................168
Output conductance g ds -vs- Vds from PIV at (a)-(c) {-3.0V,28V} and at
(d)-(f) {-1.7V,28V} for Vgs = [-1.75:0.5:-0.75]V. (GaN) ..........................169
Static IV curves, measured (symbols) and modeled (solid). (SiC) ............171
Static IV curves, measured (symbols) and modeled (solid). (GaN) ..........172
Fukui measurement. (a) IV curve of diode and series R. DC FET models
with (b) drain-open/source-short (c) drain-short/source-open and (d) drainshort/source-short. ...................................................................................175
Shockley diode model. ............................................................................176
Algorithm for the application of Fukui measurement. ..............................177
Extraction of Fukui resistances from measured data (a) I g -vs- V g and (b)
∂V g ∂I g -vs- V g . (SiC) ............................................................................178
Fig. 2-79
Extraction of diode parameters from I g , a , I g ,b and I g ,c . (SiC) ................179
Fig. 2-80
Fukui I g -vs- V g curves, measured and simulated. (SiC) ..........................181
Fig. 2-81
Forward bias gate current (a) I gs -vs- V gs and (b) I gd -vs- V gd . (GaN) .......182
Fig. 2-82
Fig. 2-83
Fig. 2-84
Fig. 2-85
Fig. 2-86
Fig. 2-87
Fig. 2-88
Fig. 2-89
Fig. 2-90
Fig. 2-91
Extraction of diode parameters from I g , a and I g ,b . (GaN).......................182
Small-signal model for FETs. ..................................................................184
Algorithm for determining extrinsic FET parameters...............................187
(a) Pinched-FET model (b) equivalent pinched-FET model. ....................188
Pinched FET Im{Y } -parameters. (SiC) ...................................................191
Pinched-FET Im{Y } -parameters. (GaN) .................................................192
Cold-FET circuit model [108]. ................................................................193
Cold-FET Z-parameters for L extraction. (SiC) ......................................197
Extraction of parasitic R ’s using cold-FET [108]. (SiC) .........................199
Hower-Bechtel technique with (a) extraction of the built-in potential Vbi (b)
extrapolation of Re{Z 22 } to extract Rs + Rd . (SiC) .................................200
-xi-
Fig. 2-92
Fig. 2-93
Fig. 2-104
Cold-FET Z-parameters for L extraction. (GaN).....................................202
Extraction of parasitic R ’s using the real part of the cold-FET Zparameters. (GaN) ...................................................................................204
Wideband pinched-FET small-signal model. ...........................................206
Wideband pinched-FET model for parameter verification and tuning. (SiC)
................................................................................................................207
Comparison of Y-parameters for the wideband pinched-FET model. (SiC)
................................................................................................................208
Wideband pinched-FET model for parameter verification and tuning. (GaN)
................................................................................................................210
Comparison of Y-parameters for the wideband pinched-FET model. (GaN)
................................................................................................................211
Reduction of complete small-signal network into intrinsic FET network..214
Algorithm for hot-FET extraction of intrinsic network elements. .............218
Multibias hot-FET extraction and nonlinear capacitance modeling
algorithm.................................................................................................220
Hot-FET Y”-parameters intrinsic extraction. (SiC) ..................................221
Hot-FET S-parameters evaluation for the { Vgsq , Vdsq } biases of (a)
{-6V,48V} (b) {-8V,48V} (c) {-10V,48V} (d) {-8V,12V} (e) {-8V,4V} (f)
{-8V,2V}. (SiC) ......................................................................................223
Multibias intrinsic parameters g m , g ds , C gd , C gs and Cds for
Fig. 2-105
Vgsq =[-10:1:-5]V, Vdsq =[0:2:58]V. Modeled C gd , C gs and Cds are also
shown. (SiC) ...........................................................................................225
S-parameters of the multibias, Vgsq =-6V, Vdsq =[0:4:48]V. (SiC) ..............226
Fig. 2-94
Fig. 2-95
Fig. 2-96
Fig. 2-97
Fig. 2-98
Fig. 2-99
Fig. 2-100
Fig. 2-101
Fig. 2-102
Fig. 2-103
Fig. 2-106
Fig. 2-107
Fig. 2-108
Fig. 2-109
Fig. 2-110
Fig. 2-111
S-parameters of the multibias sweep , Vgsq =[-10:1:-5]V, Vdsq =48V. (SiC)
................................................................................................................227
S-parameters of the multibias small-signal model with nonlinear capacitance
models at Vgsq =-6V, Vdsq =[0:4:48]V. (SiC) .............................................229
S-parameters of the multibias small-signal model with nonlinear capacitance
models at Vgsq =[-10:1:-5]V, Vdsq =48V. (SiC) ..........................................230
Hot-FET Y”-parameters for intrinsic extraction. (GaN) ...........................231
Hot-FET S-parameters evaluation for the { Vgsq , Vdsq } biases of (a)
{-1.9V,28V} (b) {-2.2V,28V} (c) {-2.5V,28V} (d) {-2.2V,16V} (e)
{-2.2V,8V} (f) {-2.2V,1V}. (GaN)..........................................................232
Multibias intrinsic parameters g m , g ds , C gd , C gs and Cds for
Vgs =[-2.6:0.1:-1.9]V, Vds =[0:variable:28]V. The modeled C gd , C gs and
Fig. 2-112
Fig. 2-113
Cds are also shown. (GaN) ......................................................................234
S-parameters of the multibias sweep , Vgsq =-1.9V, Vdsq =[1,8,16,28]V.
(GaN)......................................................................................................235
S-parameters of the multibias sweep , Vgsq =[-2.6:0.1:-1.9]V, Vdsq =28V.
(GaN)......................................................................................................236
-xii-
Fig. 2-114
Fig. 2-118
Multibias S-parameters of the multibias with the capacitance models,
Vgsq =-1.9V, Vdsq =[1,8,16,28]V. (GaN) ....................................................239
S-parameters of the multibias with capacitance model,
Vgsq =[-2.6:0.1:-1.9]V, Vdsq =28V. (GaN)..................................................240
S-parameters at (a) {-10V,55V} and (b) {-7V,55V}. (SiC) ......................244
Harmonic Prefl and Pout versus Pavs at (a) {-10V,55V} and (b) {-7V,55V}.
(SiC) .......................................................................................................246
Static I dsq -vs- Pavs at two biases. (SiC) ....................................................247
Fig. 2-119
Harmonic Prefl and Pout versus Vgsq at Vdsq =55V with an incident power of
Fig. 2-120
Pavs =33dBm. (SiC)..................................................................................248
Harmonic Prefl and Pout versus Vdsq at Vgsq =-7V with an incident power of
Fig. 2-121
Pavs =33dBm. (SiC)..................................................................................248
Harmonic Prefl and Pout versus frequency over a 20% fractional bandwidth
Fig. 2-115
Fig. 2-116
Fig. 2-117
Fig. 2-122
Fig. 2-123
Fig. 2-124
Fig. 2-125
Fig. 2-126
Fig. 2-127
Fig. 2-128
Fig. 2-129
Fig. 3-1
Fig. 3-2
Fig. 3-3
Fig. 3-4
Fig. 3-5
Fig. 3-6
Fig. 3-7
Fig. 3-8
centered at f o =2.00GHz. (SiC) ...............................................................249
Input reflected and output IM3 and fundamental products. (SiC) .............250
S-parameters at (a) {-2.5V,28V} and (b) {-1.9V,28V}. (GaN).................252
Harmonic Prefl and Pout versus Pavs for f o =3.333GHz at (a) {-2.5V,28V}
and (b) {-1.9V,28V}. (GaN)....................................................................254
Static I dsq -vs- Pavs at two biases. (GaN) ...................................................255
Harmonic Prefl and Pout versus f o from 1.8 to 3.9 GHz at (a) {-2.5V,8V}
and (b) {-1.9V,28V}. (GaN)....................................................................257
Input reflected and output IM3 and fundamental power per tone with
f1 =3.3333GHz and f 2 = f1 +100kHz at {-1.3V,28V}. (GaN) ..................258
Measured Z d 1 (X), Z d 2 (circle) and Z d 3 (triangle) and load-pull contours
(1dB per contour) at Pavs =36dBm and {-2.5V,28V}. Max predicted
Pout =41.77dBm. (GaN) ...........................................................................259
Pout (X’s), Gain (triangles), and PAE (circles) under optimum f o load
termination at (a) {-2.5V,28V} and at (b) {-1.9V,28V}. Measured
(symbols), modeled (solid lines). (GaN) ..................................................260
(a) Generalized and (b) unilateral large-signal two-port configurations for
analysis of a nonlinear circuit or device. ..................................................267
Illustration of the voltage requirements to achieve certain conduction angles.
................................................................................................................273
Model A with one hard nonlinearity: pinchoff. .......................................275
Model A IV characteristic versus (a) V g and versus (b) Vds . ...................276
Model B with two hard nonlinearities: pinchoff and forward conduction.277
Piecewise (a) I gs -vs- Vgs and (b) Z Dgs -vs- Vgs characteristics...................278
Circuit analogue of the ideal gate-source diode........................................278
V gs -vs- V g voltage transfer characteristic. ................................................280
-xiii-
Fig. 3-9
Transformation of V g into V gs into I ds due to forward conduction...........281
Fig. 3-10
Fig. 3-11
Model B IV characteristic versus (a) V g and versus (b) Vds .....................282
Model C with three hard nonlinearities: pinchoff, forward conduction, knee
................................................................................................................283
Model C IV characteristic versus (a) V g and versus (b) Vds .....................285
Fig. 3-12
Fig. 3-13
Fig. 3-14
Fig. 3-23
Waveform of I ds clipped by knee region. ................................................286
Model C highly idealized IV characteristic versus (a) V g and versus (b) Vds .
................................................................................................................287
Waveform of I ds clipped by high ideal knee. ..........................................288
Model D with four hard nonlinearities: pinchoff, forward conduction, knee,
breakdown...............................................................................................289
Ideal piecewise gate-drain diode reverse breakdown characteristic. .........289
IV characteristics employing (a) the gate-drain diode breakdown model and
(b) approximation of the breakdown effect. .............................................291
Waveform of I ds clipped by breakdown region. ......................................293
Model D highly idealized IV characteristic versus (a) V g and versus (b) Vds .
................................................................................................................294
Waveform of I ds clipped by high ideal breakdown region. ......................295
Four hard nonlinearities of Model D and the associated double-sided clipped
waveform pairs using real Z L ..................................................................296
V p -clipped waveform analysis. ...............................................................298
Fig. 3-24
V p -clipped Fourier coefficients for four harmonics (a) I dsn / I p1 -vs- 2φ1 and
Fig. 3-25
(b) I dsn / I DSS -vs- 2φ1 ................................................................................301
V f -clipped waveform analysis. ...............................................................302
Fig. 3-26
V f -clipped Fourier coefficients for four harmonics (a) I dsn / I p -vs- 2φ 2 and
Fig. 3-27
Fig. 3-28
Fig. 3-29
(b) I dsn / I DSS -vs- 2φ 2 . ..............................................................................308
Vk -clipped waveform analysis.................................................................309
VBV -clipped waveform analysis. ..............................................................312
Composition of a double sided clipped waveform using two single-sided
clipped waveforms. .................................................................................315
V p / V f -clipped waveform analysis. .........................................................316
Fig. 3-15
Fig. 3-16
Fig. 3-17
Fig. 3-18
Fig. 3-19
Fig. 3-20
Fig. 3-21
Fig. 3-22
Fig. 3-30
Fig. 3-33
Generation of operating angles { φ1 , φ 2 } using the constant V A derivation (a)
{ π / 2 , 0 } (b) { π , 0 } (c) { π , π / 2 } (d) { π , π }....................................320
Generation of operating angles { φ1 , φ 2 } using the constant Ip derivation (a)
{ π / 2 , 0 } (b) { π , 0 } (c) { π , π / 2 } (d) { π , π }....................................323
Contour plots of I dsn / I p -vs-{ 2φ1 , 2φ 2 } for n = 1,2,3,4 . ...........................327
Fig. 3-34
Three-dimensional plots of I dsn / I p -vs-{ 2φ1 , 2φ 2 } for n = 1,2,3,4 ............328
Fig. 3-35
I ds 0 / I p -vs-{ 2φ1 , 2φ 2 } (a) contour plot and (b) 3D plot............................328
Fig. 3-31
Fig. 3-32
-xiv-
Fig. 3-36
Vk / V p -clipped waveform analysis. ..........................................................329
Fig. 3-37
VBV / V f -clipped waveform analysis. ........................................................331
Fig. 3-38
Fig. 3-39
Fig. 3-40
Fig. 3-41
Fig. 3-42
Fig. 3-43
Fig. 3-44
Fig. 3-45
Fig. 3-46
Fig. 3-47
Fig. 3-48
Fig. 3-49
Fig. 3-50
Fig. 3-51
Vk / VBV -clipped waveform analysis. ........................................................333
Linear waveform analysis, general case. ..................................................335
Linear waveform analysis, specific case V A = −V B . .................................336
Complete pinchoff waveform analysis, general case. ...............................337
Complete pinchoff waveform analysis, specific case V A = VB . ................338
Complete forward conduction waveform analysis, general case. ..............339
Complete forward conduction waveform analysis, specific case V A = −VC .
................................................................................................................340
Complete knee waveform analysis, general case......................................342
Complete knee waveform analysis, specific case V A = −VC ,eff . ................343
Complete breakdown waveform analysis, general case. ...........................344
Complete breakdown waveform analysis, specific case V A = VB ..............345
Harmonic progression analysis example. .................................................347
Flow map of harmonic progression for amplitude. ...................................350
Case (a.1) Complete pinchoff V p -clipped V p / V f -clipped. .............351
Fig. 3-52
Case (a.2) Linear V p -clipped V p / V f -clipped. ................................352
Fig. 3-53
Case (a.3) Linear V p / V f -clipped. .......................................................353
Fig. 3-54
Case (a.4) Linear V f -clipped V p / V f -clipped. ................................354
Fig. 3-55
Case (a.5) Complete fwd. cond. V f -clipped V p / V f -clipped...........355
Fig. 3-56
Case (b.1) Complete pinchoff V p -clipped Vk / V p -clipped. .............356
Fig. 3-57
Case (b.2) Linear V p -clipped Vk / V p -clipped. ................................357
Fig. 3-58
Case (b.3) Linear Vk / V p -clipped. .......................................................358
Fig. 3-59
Case (b.4) Linear Vk -clipped Vk / V p -clipped..................................359
Fig. 3-60
Case (c.1) Linear VBV -clipped VBV / V f -clipped. .............................360
Fig. 3-61
Case (c.2) Linear VBV / V f -clipped.......................................................361
Fig. 3-62
Case (c.3) Linear V f -clipped VBV / V f -clipped. ..............................362
Fig. 3-63
Case (c.4) Complete fwd. cond. V f -clipped VBV / V f -clipped. ........363
Fig. 3-64
Fig. 3-65
Fig. 3-66
Fig. 3-67
Fig. 3-68
Fig. 3-69
Case (d.1) Linear Vk -clipped Vk / VBV -clipped. ...............................364
Case (d.2) Linear Vk / VBV -clipped.......................................................365
Case (d.1) Linear VBV -clipped Vk / VBV -clipped. .............................366
Flow chart for setting of the upper and lower I ds parameters...................371
Flow chart determining the generic operating mode.................................372
Application of self-heating and charge-trapping on Model D by modifying
I DSS .........................................................................................................373
Conceptual operation of an ideal multiplexer with N=4. ..........................374
Transistor operation with bias T. .............................................................375
Fig. 3-70
Fig. 3-71
-xv-
Fig. 3-72
Fig. 3-73
Fig. 3-74
Fig. 3-75
Fig. A-4
Fig. A-5
Fig. A-6
S-matrix of an ideal bias T.......................................................................376
Transistor operation with multiplexer. .....................................................377
S-matrices of the triplexer with DC and high order harmonic discharge...379
Canonic realization of a single-ended active, k th -order frequency multiplier.
................................................................................................................381
Generalized frequency multiplier design algorithm..................................382
Generalized harmonic load-/source-pull analysis simulation. ...................384
Simulated PIV characteristics of the (a) SiC MESFET model and (b) GaN
HEMT model. .........................................................................................387
Derived harmonic load and source impedances for the (a) SiC MESFET and
(b) GaN HEMT. ......................................................................................389
Topology of the prototype SiC MESFET and GaN HEMT-based frequency
doublers. .................................................................................................390
Photo of high power frequency doublers based on the (a) SiC MESFET and
(b) GaN HEMT. ......................................................................................391
Harmonic Pout for the (a) SiC MESFET and (b) GaN HEMT doublers.
Measured (symbols), simulated (solid lines). ...........................................392
CG 2 , η 2 and PAE 2 for the (a) SiC MESFET and (b) GaN HEMT doublers.
Measured (symbols), simulated (solid lines). ...........................................393
Harmonic Pout over a 5% FBW for the (a) SiC MESFET and (b) GaN
HEMT doublers. Measured (symbols), simulated (solid lines). ...............394
Pout 2 -vs- VDD at Pavs =[23,27,31,36]dBm for the (a) SiC MESFET and (b)
GaN HEMT doublers. Measured (symbols). ............................................395
(a) Pout 2 -vs- Pavs and (b) CG2 -vs- Pavs comparing GaN doubler at VDD =28V
and VDD =39V. Measured (symbols). ......................................................396
Simulated PIV characteristics of the GaN HEMT model at a bias of (a)
Vgsq =-3.0V, Vdsq =28V and (b) Vgsq =-2.3V, Vdsq =28V..............................398
Harmonic load and source impedances from GaN tripler simulation. .......399
Circuit topology of GaN frequency tripler prototype................................401
Photo of high power frequency GaN HEMT tripler. ................................402
Harmonic Pout of the GaN tripler for three harmonics. Measured (symbols),
simulated (solid lines)..............................................................................403
CG3 and η3 of GaN tripler. Measured (symbols), simulated (solid lines).
................................................................................................................403
Electrical circuit analogue for first order thermal model. .........................410
Electrical circuit analogue for K-order thermal model. ............................414
Internals of the DC model under DC power dissipation (a) applied terminal
excitation (b) schematic (c) ln( I gs ) -vs- V gs curve for extraction...............416
Implementation of substrate trapping model. ...........................................419
Transient diagram of the full substrate trapping model.............................420
(a) Complete dynamic trapping model from [55][56][57] with τ capture < τ release
Fig. A-7
and (b) reversed submodel with τ capture > τ release . ......................................422
Transient diagram of the simplified substrate trapping model. .................425
Fig. 3-76
Fig. 3-77
Fig. 3-78
Fig. 3-79
Fig. 3-80
Fig. 3-81
Fig. 3-82
Fig. 3-83
Fig. 3-84
Fig. 3-85
Fig. 3-86
Fig. 3-87
Fig. 3-88
Fig. 3-89
Fig. 3-90
Fig. 3-91
Fig. 3-92
Fig. A-1
Fig. A-2
Fig. A-3
-xvi-
Fig. A-8
Fig. A-9
Fig. A-10
Fig. A-11
Fig. A-12
Fig. A-13
Fig. A-14
Fig. B-1
Fig. B-2
Fig. C-1
Fig. C-2
Fig. C-3
Fig. C-4
Fig. C-5
Fig. C-6
Fig. C-7
Fig. C-8
Fig. C-9
Fig. C-10
Fig. C-11
Fig. C-12
Fig. C-13
Fig. D-1
Fig. D-2
Charge-trapping model used in the SiC MESFET and GaN HEMT models.
................................................................................................................426
Equivalent model for Fukui measurement with drain short and source short.
................................................................................................................429
Equivalent pinched-FET model. ..............................................................431
Two-port circuit definitions for cold-FET model. ....................................434
Two-port network subtracting parasitic capacitances. ..............................439
Two-port network subtracting parasitic inductances and resistances. .......440
Intrinsic small signal network..................................................................442
Power available from the source. .............................................................450
Single-sided clipped waveform analysis of Clarke and Hess. ...................454
Test fixture (a) top (b) angle (c) side (d) bottom. .....................................463
Static IV test setup...................................................................................464
PGIV test setup. ......................................................................................465
PGIV test setup photo 2009 (a) Full view and (b) Zoomed view of test
fixture (gate voltage optional and not probed here). .................................465
S-parameters test setup. ...........................................................................466
Test fixture dimensions. ..........................................................................468
Microstrip TRL THRU standard..............................................................469
Microstrip TRL LINE standard................................................................470
Microstrip TRL OPEN standard. .............................................................471
S-parameter fixture plate. ........................................................................473
Single-tone high power harmonic test setup.............................................476
Photo of single-tone high power harmonic test setup. ..............................477
Two-tone source generation.....................................................................479
SiC MESFET ADS schematic. ................................................................480
GaN HEMT ADS schematic....................................................................481
-xvii-
List of Tables
Table 1-1
Table 2-1
Table 2-2.
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Material Properties of Si, GaAs and SiC (6H and 4H) [18][19][20] .............5
Summary of classical FET drain current models ........................................34
Characterization summary for each component of generic FET model.......41
I ds parameters, final deembedded and optimized (SiC) .............................83
Rth -vs- PD model parameters (SiC) .........................................................107
Rth -vs- T model parameters (SiC) ...........................................................108
K Ipk model parameters (SiC)...................................................................116
Table 2-7
Analytical model parameters of I pk ,T0 (SiC).............................................118
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
Table 2-22
Table 2-23
Table 2-24
Table 2-25
Table 2-26
Table 2-27
Table 2-28
Table 2-29
Table 2-30
Table 2-31
Table 2-32
Table 2-33
Pnth model parameters (SiC) ....................................................................121
Thermally-varying model parameters (GaN) ...........................................131
I ds parameters, final deembedded and optimized (GaN)..........................133
First-order thermal model parameters (SiC) .............................................139
Third-order thermal model parameters (SiC) ...........................................140
First-order thermal model parameters (GaN) ...........................................141
Third-order thermal model parameters (GaN)..........................................142
PIV model and data comparison at {0V,0V} (SiC) ..................................156
PIV model and data comparison at {-3V,30V} (SiC) ...............................157
Substrate trapping deembedding parameters (SiC)...................................158
PIV model and data comparison at {-3V,14V} (GaN) .............................162
PIV model and data comparison at {-3V,56V} (GaN) .............................164
Substrate- and surface-trapping model parameters (GaN) ........................164
Extracted Fukui R’s and computed parasitic R’s. (SiC)............................179
Extracted and optimized diode parameters (SiC) .....................................180
Extracted and optimized diode parameters (GaN) ....................................183
Parasitic R’s determined under DC optimization (GaN)...........................184
Extracted parasitic capacitances (SiC) .....................................................191
Extracted parasitic capacitances (GaN)....................................................192
Extracted parasitic inductances using cold-FET (SiC)..............................197
Extracted parasitic resistances using cold-FET (SiC) ...............................201
Extracted parasitic inductances using cold-FET (GaN) ............................202
Extracted parasitic resistances using cold-FET (GaN)..............................204
Extracted and optimized parasitics using wideband pinched-FET (SiC) ...209
Extracted and optimized parasitics using wideband pinched-FET (GaN) .212
Extracted and optimized C gs , C gd and Cds model parameters (SiC)........228
Table 2-34
Table 2-35
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Extracted and optimized C gs , C gd and Cds model parameters (GaN) ......238
Comparison of SiC MESFET and GaN HEMT models............................261
Lower saturated parameter assignments...................................................367
Upper saturated parameter assignments ...................................................368
Lower clipped parameter assignments .....................................................368
Upper clipped saturated parameter assignments.......................................369
-xviii-
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 3-9
Table A-1
Table C-1
Table C-2
Table C-3
Table C-4
Double-clipped parameter assignments....................................................370
SiC- and GaN-based doubler network electrical lengths...........................391
High power frequency doubler performance summary and comparison ...393
GaN-based tripler network electrical lengths ...........................................402
High power frequency tripler performance summary and comparison......404
SiC MESFET Ids parameters post optimization for all PGIV datasets......409
Cal Kit Standards for TRL calibration .....................................................472
Standard Class Assignments for TRL calibration.....................................472
Microwave substrate parameters used in this work ..................................473
Final TRL calibration parameters ............................................................474
-xix-
Notation Definitions
Two bracket-type notations are used frequently in this work:
Curly bracket notation {}
The curly bracket notation {} is a compact way of denoting a pair of operating
conditions, which define an operating point:
{operating condition 1, operating condition 2}
Ex. {-3.0V,28V}
This means an operating point with the first parameter at -3.0V and the second parameter
at 28V. Usually the first value is a quiescent gate voltage and the second value is a
quiescent drain voltage.
Square bracket notation []
The square bracket notation [] is a compact way of specifying a range or a set of numbers
and is used in conjunction with a variable.
Below is the application of [] for an explicit series of numbers:
variable=[value 1, value 2, value 3, value 4]unit
Ex. V gs =[1,4,8,16]V
This means the gate voltage, V gs , takes on four values, 1V, 4V, 8V, and 16V.
-xx-
Below is another application of [] for a range of numbers specified by the minimum and
maximum:
variable=[minimum value:step value:maximum value]unit
Ex. Pavs =[0:1:20]dBm
This means the power available from the source, Pavs , is a range of values starting at
0dBm, stepped by 1dBm, and stopping at 20dBm.
Note: Square brackets [] are also used to identify references, however, these references
will never be accompanied by a variable name, equal sign or unit.
-xxi-
1
CHAPTER 1. INTRODUCTION
1.1.
Introduction
The demand for new technologies for wireless applications is rising at an
unprecedented rate. A constant evolution of microwave power systems is necessary to
keep pace with a growing wireless infrastructure, which includes cellular base station,
local area network, Wi-Fi distribution, defense and radar applications [1].
Modern
communication systems like W-CDMA require power devices which provide gain,
linearity, efficiency and output power [2]. One of the most promising technologies
capable of meeting these demands are wide bandgap III-V semiconductors [3]. These
technologies have risen to the forefront of microwave solid-state amplifiers and are
positioned as the primary technologies for the next generation of wireless systems.
Early investigation of wide bandgap technology brought forth two competing
candidates for the eventual commercialization and wide deployment in compact, high
power microwave systems: the silicon-carbide (SiC) metal-semiconductor-field-effect
transistor (MESFET) and aluminum-gallium-nitride/gallium-nitride (AlGaN/GaN or
simply GaN) high-electron mobility transistor (HEMT). The advantages inherent in SiC
MESFETs and GaN HEMTs such as high power density, thermal conductivity,
breakdown voltage and millimeter-wave operation make them ideal for broadband, highefficiency, high-power amplifier design. High power SiC MESFET amplifiers have been
demonstrated [4] and have achieved as much as 250W at S-Band [5]. More impressively,
GaN HEMT amplifiers producing as much as 800W at S-band have been reported [6].
2
Although recently, GaN devices have emerged as the dominant device in solid-state
power amplifier research, the unique nonlinear characteristics of both types of
technologies continue to be explored for a variety of circuit applications. Novel circuit
implementations such as SiC- and GaN-based mixers [7][8], oscillators [9][10] and
frequency multipliers [11][12] demonstrate the potential of combining high gain and
power output with signal processing functionality. Of particular interest are SiC and GaN
active frequency multipliers which are explored extensively in this work.
The design of an efficient, high power frequency multiplier typically requires a good
nonlinear model which can correctly predict the nonlinear electrical behavior of the
device under a variety of drive, bias and impedance conditions. However, because SiC
and GaN are relatively new technologies, they pose a challenge for conventional
modeling methods.
The technology-associated issues include thermal effects, a
byproduct of high power density; and charge trapping, defects introduced during
fabrication. As fabrication and yield improve, charge-trapping effects will diminish.
However, self-heating will always be prevalent for high-power density devices.
In this chapter, the importance of SiC and GaN is given along with a brief history of
the development of SiC and GaN devices. Then, the motivation for device modeling and
the frequency multiplier development in SiC and GaN technology is presented.
1.2.
Importance and Development of Wide Bandgap Technology
Presently, silicon (Si) and gallium-arsenide (GaAs) technologies have matured in
terms of their power handling capabilities [13]. As the demand for improved frequency
operation and output power increases, Si and GaAs will soon cease to provide the
3
performance required in modern microwave systems.
Although these established
technologies will continue to provide high frequency microwave operation for many
years, demands in the output power of small systems have highlighted their numerous
shortcomings.
One important evaluation of the power performance of semiconductor devices is the
measure of power density. This is defined as the RF output power per millimeter of gate
width (W/mm) for a constant gate length [14]. Once way to increase the power density is
to increase the breakdown voltage of the device, thus allowing it to operate at higher
output terminal voltages.
Presently this is done in conventional Si-based LDMOS
devices which have breakdown voltages of >700V [15].
However, increasing the
breakdown voltage is only effective to a certain degree since thermal self-heating effects
become more dominant as devices always operate at their thermal limit [14]. Thermal
self-heating is a function of the thermal conductivity of the device technology and
ultimately determines the power handling capability per unit of die area [14].
Si and
GaAs materials have poor thermal conductivity, increasing self-heating and limiting the
power density and downward scalability of devices.
In order to compensate for low power density and produce a prescribed output power
in Si or GaAs, the overall output current must be increased by enlarging the periphery of
the device, which is typically done by using multi-fingered layout topologies. However,
there are two main limitations to doing this.
First, the periphery of the device is
constrained by the wavelength of operation. Therefore, although GaAs devices can be
made very large, their frequency of operation is limited by the die size [14]. Secondly,
the output current scales with device width but the maximum terminal voltage remains
4
the same. This creates an output impedance that is low and difficult to match. As long as
the low output impedance can still be transformed to 50 ohm, this does not pose a
problem but may further complicate the supporting circuitry, especially over broad
bandwidths.
Furthermore, the device is still built upon low thermal conductivity
substrate which increases operating temperature. This excess heat may necessitate the
use of external cooling methods, thereby reducing the overall economy of the circuit.
The resulting power-bandwidth-efficiency conundrum is most easily circumvented
through the use of other technologies that possess higher operational limits.
Wide
bandgap devices provide the means to increase power density and retain
microwave/millimeter wave frequency operation through its superior material properties.
The development of the wide bandgap silicon carbide (SiC) material for use as a
semiconductor substrate is responsible for providing a foundation for which wide
bandgap semiconductor technology is built. Some of the desirable properties which
make SiC ideal for microwave power devices are a high breakdown field (4 x 106 V/m),
high thermal conductivity (4.9W/cm-K), and high saturated electron velocity [16][17]. A
table comparing the material properties of Si, GaAs and SiC is shown in Table 1-1.
5
Table 1-1
Si
GaAs
SiC
(6H)
SiC
(4H)
GaN
Material Properties of Si, GaAs and SiC (6H and 4H) [18][19][20]
Bandgap
Eg
(eV)
1.11
1.43
2.9
Rel.
Perm.
(εr)
Sat.
Electron
Vel.
(cm/s)
1 x 107
1 x 107
2 x 107
Electron
Mobility
µe
(cm2/V-s)
1350
6000
380*
Hole
Mobility
µh
(cm2/V-s)
450
330
95
Therm
Cond.
(W/cm-K)
BFOM
11.8
12.8
9.7
Breakdown E
field#
(V/cm)
6 x 105
6.5 x 105
35 x 105
1.5
0.46
4.9
300
300
—
3.2
9.7
35 x 105
2 x 107
800*
120
4.9
600
3.4
9.5
20 x 105
1500
—
>1.5
700
2.5 x
107
#
17
-3
at Nd = 1 x 10 cm *perpendicular to the c-axis
3
BFOM = Baliga’s Figure of Merit for power transistor performance = ( µεE g )
Implementation of SiC and GaN technologies results in the creation of transistors
with extremely high power densities. Within the last decade, wide bandgap devices have
been developed to achieve power densities in up to 8.9W/mm at 2GHz for SiC [21] and
up to 20.7 W/mm at 4GHz [22] for GaN, alleviating many of the drawbacks of Si and
GaAs technology.
1.2.1. SiC Technology
Bandgap and high breakdown field
The wide bandgap of III-V semiconductors is the primary attribute allowing high
power density at microwave frequencies.
Devices fabricated in a wide bandgap
technology can withstand larger internal electric fields and have breakdown voltages
greater than that of Si and GaAs. The superior breakdown voltage limitation translates
into safe device operation at higher voltages. The breakdown voltage of SiC is ten times
higher than Si or GaAs and therefore can produce a much higher output power density
[14][23].
6
High thermal conductivity
Since extreme channel temperatures due to self heating limit the power density, heat
generated from large static power dissipation in the device need to be properly expelled.
Otherwise, it remains confined in the lattice, reducing carrier mobility in the active region
and causing failed or highly frequency limited operation [24]. Therefore, good thermal
conductivity in the substrate is necessary. The thermal conductivity of SiC is >4W/cm-K
[2], which is more than eight times higher than GaAs [14]. However, high thermal
conductivity can complicate testability since it provides a lower junction-to-case
temperature increase than other technologies operating at the same power density [25].
This makes reliability assessment challenging since the ambient or flange temperature
must be further increased to achieve a desired junction temperature than would be
required for a GaAs or Si device [26].
Saturated electron drift velocity
The major drawback of SiC is its poor low-field electron mobility (300-500 cm2/Vsec for Nd=1e17 to 5e17) in comparison with other established technologies [14][23].
This results in larger source resistances, lower transconductance than GaAs [14] and thus
lower operating frequencies. Low electron mobility is partially offset by SiC’s ability to
operate in high E fields with a saturated electron drift velocity of > 2 times that of GaAs
allowing the device to achieve microwave operation [14][16][17][23].
7
Development of SiC
Early in the development of SiC devices, two among 200 different crystal structure
polytypes were carefully investigated for the development of semiconductor devices [14].
These two polytypes, 6H-SiC and 4H-SiC, were chosen due to their high-quality single
crystalline substrates [14]. Initially 6H-SiC garnered more attention since it possessed
better crystal quality. Submicron MESFETs were built in 6H-SiC as demonstration
devices. However, it was soon discovered that 4H-SiC had even more potential for high
power, high frequency operation. This is because 4H-SiC has a larger bandgap (3.26eV
vs 3.00eV) and a higher electron mobility, which is twice that of 6H-SiC, while retaining
other desirable properties of 6H-SiC [14].
This led to devices possessing better
breakdown voltage and frequency operation.
The first 4H-based SiC MESFETs were built on conducting N+ SiC substrates which
employed the use of a p- buffer layer to provide isolation between the channel region and
the substrate (Fig. 1-1a) [27].
Although this produced a functional MESFET, the
frequency response was limited by the conductivity of the SiC substrate in an effect
similar to that found in Si BJTs. In order to increase the operating frequency and to
exploit the high thermal conductivity of SiC, development of large-area semi-insulating
SiC substrates was necessary (Fig. 1-1b) [24]. As a comparison, in one work SiC FETs
with conducting substrates had an f max of 16.3GHz, while SiC FETs with semiinsulating (high-resistivity) substrates could achieve an f max of 42GHz [17]. Some other
methods successfully used to increase the operating frequency include increasing the
doping and reducing the gate length [24][27].
8
SiC MESFETs have excellent linearity [1], high breakdown voltages in excess of
100V [14] and high power density output of around 4W/mm [28]. Due to the low
electron mobility of SiC MESFETs, they are usually designed to have a relatively low
pinchoff voltage of around -9 to -10V [14][29] in order to obtain the adequate current for
the FET to be used as a power device. Some 0.7um gate length devices achieve channel
current density ~300mA/mm. SiC power devices are good for high temperature, high
frequency operation for extreme power levels [30].
Fig. 1-1
Physical structure of SiC MESFET on (a) conductive SiC substrate [27] and
(b) semi-insulating SiC substrate [31].
Defects
As a developing technology, some of the early problems that arose with SiC included
the introduction of large-scale defects in the fabricated SiC bulk called “micropipes”
[14]. These micropipes are dislocations in the crystal that have open cores and pinholes
in the wafer and are typically characterized in terms of “micropipe density.” However,
over the years, processing yield has improved significantly and presently SiC substrates
have been refined to the point that these micropipe densities are very small. However,
non-structural defects such as trapping continue to exist and affect device performance.
9
1.2.2. GaN Technology
Beyond making SiC MESFETs a viable microwave power device, bulk-grown semiinsulating SiC substrates have, more importantly, allowed the development of high
electron mobility transistors (HEMTs, sometimes called MODFETs [32]) using
AlGaN/GaN [24]. To overcome the reduced frequency response due to lower carrier
mobility in SiC MESFETs, HEMTs utilizing AlGaN/GaN heterojunctions grown on
semi-insulating SiC substrates were created to improve bandwidth and provide even
greater power densities that SiC MESFETs.
Technology properties
Some of the qualities that make the AlGaN/GaN combination ideal for HEMT
devices include the wide bandgap energy, high sheet carrier density and its compatibility
with SiC substrates.
The wide bandgap energy of GaN is 3.4eV, which gives
AlGaN/GaN materials a high breakdown field >2 x 106 V/cm [33].
The heterojunction created by the mating of AlGaN and GaN creates a large
conduction band offset giving rise to two beneficial effects:
piezoelectric strain
polarization (PE) and spontaneous polarization (SP). These two effects establish strong E
fields in the AlGaN layer and naturally induce a high 2DEG sheet carrier density
(~1x1013 / cm2) [33][34]. In addition, AlGaN/GaN heterojunctions give rise to a high
saturated electron drift velocity [20][33]. GaN also is able to operate at high temperature
[2].
10
GaN on SiC
AlGaN/GaN HEMT devices were first produced using sapphire substrates and
demonstrated reasonable power densities [35].
However, because sapphire has low
thermal conductivity [36], junction temperatures in these devices became very high
(>300C), reducing performance and making bonding of flip-chip realizations difficult
[37]. The solution was to grow GaN devices on semi-insulating SiC substrates instead so
that the high frequency, high power density properties of the AlGaN/GaN heterojunction
can be mated with the thermal benefits of SiC.
GaN and SiC have a close lattice match, making semi-insulating SiC an excellent
substrate for AlGaN/GaN HEMTs. This results in a lower defect density than growing
GaN-on-sapphire [24][30]. The higher thermal conductivity of SiC substrate is critical
for dissipating very high power density of GaN systems [24] and enables GaN HEMT
devices to take advantage of the SiC thermal conductivity which is 7 times higher than
sapphire (3.3W/cm-K) [33]. The combination of these properties makes GaN-on-SiC an
excellent, heat-minimizing device realization [1][33]. The cross section of a typical
AlGaN/GaN HEMT device fabricated on semi-insulating SiC substrate is shown in Fig.
1-2.
11
Gate
Source
Drain
undoped AlGaN 10 nm
2e18/cm3 AlGaN 12 nm
undoped AlGaN 5 nm
Insulating GaN 2 um
AlN Nucleation Layer
Semi-insulating 4H-SiC
Sheppard (2000)-Technology Development for GaN-AlGaN HEMT
Hybrid and MMIC Amplifiers on Semi-Insulating SiC Substrates
Fig. 1-2
Physical structure of AlGaN/GaN HEMT device [34].
Development of GaN
Although the power density ratings in W/mm provide insight into the power potential
of a technology, high values can be misleading in terms of the upward scalability of a
device. The total power from a large periphery device is more important where device
yield and thermal design become the performance limiting factors [38]. Early in the
development of GaN HEMTs, the gate peripheries of prototypes were too small and did
not produce useful microwave power [33]. During those times, large-periphery devices
experienced thermal problems arising from difficulty in attaching the die causing
inefficient heat transfer into the carrier. This was the case in [34], where CW operation
could not be achieved without damaging the device. However, these problems were
eventually solved. In one interpretation, the wide bandgap of GaN gives rise to a high
power density per unit gate width (W/mm), while the high thermal conductivity SiC
substrate enables very high power density per die area (W/mm2) [33].
12
Defect levels affect the performance of both SiC MESFETs and GaN HEMTs.
However, since SiC is more mature, the defect levels in SiC MESFET technology are 4-5
times lower than GaN devices. Despite this, the RF power density of SiC MESFETs is
lower than expected due to deep level impurities in SiC substrate [38]. Material defects
in GaN HEMT devices result in lower breakdown voltages than SiC MESFETs [38].
However, their advantages over SiC MESFETs in terms of operating frequency far offset
the drawbacks of lower breakdown [38].
GaN HEMTs also possess good linearity
[1][30].
1.2.3. Advancements in SiC and GaN Fabrication
Additional advancements in fabrication techniques have further improved the
performance of these devices.
Some of the trapping phenomena occurring at the
semiconductor surface and the interface between the substrate and the channel can be
removed by improving the buffer layer and surface passivation [1]. Also, T-shaped gates
have been implemented in order to reduce gate capacitance and resistance by minimizing
the gate footprint and maximizing cross section [1]. A field plate can also be integrated
with the gate electrode [39] and is recessed through passivation to the AlGaN surface.
Improvements on mobility and sheet charge density include the development of an AlN
interlayer between AlGaN barrier and GaN channel to give high mobility (>2000
cm2/V-s) simultaneously with high sheet charge density [2]. Additionally, the intrinsic
GaN material serves as a thick buffer between the substrate and channel and it must be
highly resistive in order to block extremely high voltages during the upper part of the RF
voltage excursion [34]. Device isolation is also improved with mesa etching [34].
13
1.3.
Nonlinear Modeling
As SiC- and GaN-based these devices are pushed to their power limitations, new
methods of utilizing nonlinearities have been explored. Recent work in power amplifiers
utilizing the manipulation of harmonics to achieve increased efficiency, output power and
gain have been reported [40][41]. This has led to the desire for nonlinear models which
accurately predict harmonic generation at the gate reflected and drain output terminals.
The accurate utilization and manipulation of these harmonics are the driving force in
developing models which predict highly nonlinear operation.
The rapid evolution of semiconductor technology makes it difficult to construct
accurate nonlinear circuit models for these physical devices. Technology design kits for
ICs are typically released with foundry-constructed models which provide reasonably
good predictions of nonlinear behavior due to high yield and repeatability.
Commercially-available packaged devices are also released in a standardized fashion
with an associated part number and predicted performance margins. However, contrary
to ICs, commercial devices in developing technologies can exhibit considerable
fabrication mismatch, causing variability in transistor turn-on voltage, gain and maximum
output current. Although these mismatches are reduced as the production matures, they
may pose a significant problem in early realizations of the technology. Furthermore,
foundry-supplied models are usually validated for a prescribed set of applications and
over a select range of bias and drive levels. This allows the user to predict output
performance over a designated operating range, but not at extreme regions for which
highly nonlinear circuits, like frequency multipliers, are often driven. Device models that
14
are valid up to the electrical limits of the device are rare. Therefore, many nonlinear
power amplifiers and frequency multipliers are built either without the use of nonlinear
device models or using approximate models. This is especially true in the case of high
power amplifiers, in which thermal effects and nonlinear clipping make the performance
drastically deviant from small-signal.
A user-defined, harmonically-accurate model customized for the particular
application would be ideal in terms of accuracy.
However, since comprehensive
nonlinear characterization is a daunting, time-consuming operation, the modeling of
active devices in emerging technologies is often bypassed to quickly produce
demonstrable circuit prototypes. As a substitute, key device parameters and conduction
angle analysis are used as a guide to circuit development [42]. The drawback of this
method is that the potential of such devices is often understated. Without a software
model, the designer cannot efficiently maximize multiple performance parameters and
winds up targeting one performance metric while sacrificing others.
Two high-order effects, self-heating and charge-trapping, introduce anomalies and
performance degradations at DC and RF and pose a challenge for modeling SiC and GaN
devices. Self-heating arises from the high power density of the device whereas chargetrapping originates due to imperfections in the semiconductor lattice. Although the latter
is reduced with improved fabrication, the former cannot be easily alleviated since it is
limited by the material properties. Proper modeling of these physical properties and
effects eventually translate into a model which is accurate at the electro-thermal level.
The dispersive effects of self-heating and charge-trapping create a dependency
between the IV response and electrothermal operating point, making the development of
15
a nonlinear model valid over large excitation ranges extremely challenging. Dispersive
drain current phenomena has been characterized in numerous studies using dynamic IV
measurements which can specifically exploit the effects of self-heating and chargetrapping at different quiescent points [43][44][45][46][47][48].
Once characterized, the influence of self-heating can be implemented by making
various drain current model parameters sensitive to the quiescent bias [43][44][45][46]
and to changes in temperature due to dissipated power [49][50][51][52][53][54][48].
The observed effects of charge-trapping on dynamic IV measurements can be used to
produce transient delay networks which compute the effective internal potentials based
on the quiescent operating point [55][56][57]. These effective biases are implemented as
the I ds control voltages to emulate the effect of trap-related current degradation [49][51].
Existing models for SiC MESFETs and GaN HEMTs are based on modified versions
of the Angelov model [49][53][54][58].
Many provided accurate drain-current and
capacitance predictions [58]. However, few report I ds predictions valid beyond 1A and
only a handful report predictions of higher order harmonics [52][59].
Advanced modeling on the complex thermal behavior of GaN HEMTs have also
been conducted with great success [59][60].
1.4.
Active Frequency Multipliers
Frequency multipliers are important in a variety of microwave and millimeter-wave
(mm-wave) applications. Due to the high-cost of developing low phase-noise oscillators,
frequency multipliers are often employed alongside VCOs, PLLs, amplifiers and mixers
in a variety of system applications such as transceivers (Fig. 1-3a), frequency
16
synthesizers (Fig. 1-3b) [61], downconverters [62], dual-band Wi-Fi transmitters [63]
(Fig. 1-3c) and commercial digital broadcast satellite transceivers (DBS) [64].
Additionally, frequency multipliers are commonly used in mm-wave signal generation
for 60GHz future broadband wireless systems [65], automotive radar (Fig. 1-3d) [66] and
phased array applications [67].
Fig. 1-3
Frequency multipliers in various systems (a) Receiver (b) Frequency
synthesizer [61] (c) Dual-band [63] (d) Automotive Radar [66].
Use of an LO oscillator-multiplier pair for microwave and millimeter wave (mmwave) signal generation [42] alleviates many design constraints of the oscillator and
related circuitry where low-noise, low-distortion, phase-coherent signals are needed.
Although frequency multipliers generate a theoretical 20 log( N ) phase noise power
17
increase, in practice they still offer better performance than an LO developed at the
desired frequency [42].
In a typical application of passive frequency multipliers, a LO’s fundamental ( f o )
signal is multiplied to the desired harmonic by a single or chain of passive, nonlinear
elements then amplified by a buffer stage and delivered to the system as shown in Fig.
1-4. It is frequently necessary to employ buffer amplifier stages to obtain sufficient
power and filtering to suppress unwanted harmonics.
Since all passive multipliers
usually exhibit significant conversion loss, this topology may be cumbersome due to the
added complexity of multiple stages and the requirement of power amplifiers.
LO
Freq. Mult.
fo x k
k*fo
k*fo
Unwanted
harm.
Buffer
To
System
Filter
(single or chain)
High Power
Active Frequency
Multiplier
Fig. 1-4
xk
Passive frequency multiplier, optional filter and buffer amplifier combined
into a single active, high power frequency multiplier.
In comparison with passive diode- or varactor-based frequency multipliers, transistorbased active frequency multipliers can potentially achieve low conversion loss (and even
conversion gain CG , high DC-to-RF conversion efficiency ( η ), and high output power.
The positive CG and high output power of active frequency multipliers may relax the
design requirements of the buffer stages or even eliminate them altogether. In most
18
designs, however, positive CG is sacrificed for increased output frequency operation.
These performance benefits suggest that active frequency multipliers can improve the
multiplication chain shown in Fig. 1-4, while minimizing complexity (biasing, inter-stage
matching) and form-factor.
SiC and GaN for Frequency Multipliers
Many of the improvements and development directions of frequency multipliers are
driven by advances in existing and emerging semiconductor technologies including InP,
GaAs metamorphic HEMT (for millimeter wave), SiGe HBTs and BiCMOS process and
GaN (for power applications). Existing technologies like GaAs-based pHEMT devices
have also retained a presence as the standard microwave technology.
Despite the advancements of MMIC frequency multipliers, hybrid frequency
multipliers are still important since they allow designers to exploit the unique traits of
various technologies in one system. So far, the power output of existing, large-scale
volume standard IC technologies cannot match the output power of PA-oriented
technologies like wide-bandgap semiconductors like SiC MESFETs and GaN HEMTs.
These technologies have become the forefront in solid-state microwave power amplifier
(PA) development and are potential substitutes for varactors and diodes used in high
power frequency multipliers for various transmitter, phased array radar and imaging
applications [68][69][70].
19
1.5.
This Work
The work presented in this dissertation endeavors to characterize and understand the
behavior and operation of SiC MESFETs and GaN HEMTs for high power microwave
applications. This work is a detailed culmination of [71][72][73][74][75][76][77].
A complete modeling strategy is devised along with new techniques for addressing
the unique challenges of modeling the behavior of the SiC and GaN transistors. Models
are developed which can accurately predict the DC, pulsed, small-signal RF and largesignal RF harmonic behavior of the device in a 50 ohm system. The model development
is described in Chapter 2.
Additionally, the novel application of frequency multipliers on high-power SiC and
GaN devices is investigated. New Fourier analyses techniques specific to the design of
frequency multipliers are investigated. The nonlinear models developed in this work are
used to develop high power, high CG, high efficiency active frequency multipliers. Close
agreement between simulations and measurements of the designed frequency multipliers
also validates the modeling effort.
The active frequency multiplier development is
described in Chapter 3.
Fig. 1-5
Devices under study: (a) Cree Inc. CRF-24010 10W SiC MESFET [78] and
(b) Cree Inc. CGH-40010F 10W RF Power GaN HEMT [79].
20
The two representative devices studied in this work are the commercially available
Cree CRF-24010 10W Silicon Carbide MESFET [78] and Cree CGH-40010 10W
Gallium Nitride HEMT [79] shown in Fig. 1-5a and Fig. 1-5b, respectively.
Both the
CRF-24010 and CGH-40010 are unmatched devices packaged in a 440166 package with
flange and measures about 14.09mm x 4.19mm x 3.43mm. Large-signal models for both
devices are available from the manufacturer [80][81], but their technical specifications
are not publicly available. Although, these two devices are the basis for this study, many
of the techniques presented here may be applied to a wide variety of high power devices.
21
CHAPTER 2. NONLINEAR FET MODELING
2.1.
Introduction
In this chapter, the background, state of the art and technical process of modeling the
SiC MESFET and GaN HEMT is described. First, an overview of MESFET and HEMT
operation is given followed by a summary of modeling families and classical FET
models. The technical process is given next, describing in detail the DC, pulsed and RF
characterization and the stepwise identification of the nonlinear and linear components of
the model.
Model identification consists of composing mathematical formulas
specifically for the drain current of SiC and GaN devices, while integrating self-heating
and charge-trapping effects.
It also consists of modeling the junction diodes and
extracting the linear and nonlinear parasitics. The complete model is verified against IV,
small-signal and large-signal microwave measurements.
2.1.1. Device Physics
MESFET
The cross section of a generic MESFET device is shown in Fig. 2-1 and consists of an
n-doped active layer, which serves as the channel region of the FET, grown over a semiinsulating substrate layer. The source and drain terminals are formed by implanting n+
regions and creating ohmic contacts over those regions. A Schottky contact is created by
depositing metal atop the semiconductor between the source and drain terminals. This
22
serves as a gate terminal and gives rise to a depletion region which is controlled by the
reverse bias gate voltage.
Source
Gate
Drain
n+
depletion
region
n+
n channel Layer
semi-insulating substrate
Fig. 2-1
Device physics of a generic MESFET device.
During operation, a positive voltage is applied between the drain and source terminals
to create a lateral electric field. When the gate bias is strongly negative, a depletion
region is formed in the vertical direction which cuts off or pinches off the channel region
such that electrons cannot flow from source to drain. When the gate bias is increased
towards zero, the depth of the depletion region decreases, and this space-charge blockade
is reduced allowing electrons to flow from source to drain. The resulting electron flow
creates a positive drain-source current. The MESFET device is a depletion mode device
because current flow increases as the depletion region depth is decreased.
Since
conduction is performed by majority carriers and the depletion region of the Schottky
junction can be modulated at very high frequencies, MESFET devices are often excellent
for microwave frequency operation.
23
SiC MESFET devices typically consist of a highly doped n-type channel layer atop a
semi-insulating SiC substrate. Although the detailed topology of the Cree CRF-24010
SiC MESFET is proprietary, it can be conceptually represented by the general device
structure described previously.
HEMT
In a MESFET, the semiconductor is doped with impurities to increase its carrier
concentration. However, these doping impurities also reduce carrier mobility, limiting
the frequency performance of the device. Contrarily, the mobility within an undoped
material is the greatest since no doping impurities exist to impede carrier transport. It is
possible to achieve a high carrier concentration, while retaining a high mobility by
combining the qualities of highly-doped and undoped semiconductor using a
heterojunction, or a junction composed of materials with different bandgaps.
The
resulting FET device is called a high electron mobility transistor (HEMT). A cross
section of a generic HEMT is shown in Fig. 2-2a illustrating the doped and undoped
semiconductor layers. The source and drain contacts are created by n-type implantation.
24
Fig. 2-2
Device physics of a generic HEMT device [82].
A heterojunction causes carriers from the doped material to pass over to the undoped
side and form a two-dimensional electron gas (2DEG) just at the upper surface of the
undoped layer. When an electric field is applied between the source and drain terminals,
the carriers in the 2DEG pass from the source to the drain with extremely high mobility.
The result is a transistor with increased responsiveness and frequency performance.
The energy bands of the heterojunction are illustrated in Fig. 2-2b. When the doped
and undoped materials are mated, the Fermi levels of the doped and undoped layers align
and the difference in bandgap creates a quantum well in which carriers collect and move
freely above the conduction energy. This quantum well represents the locations and
energy levels of the 2DEG.
In practical AlGaN/GaN devices, aluminum-doped GaN is used in a number of
possible layer arrangements atop an undoped GaN layer (see Chapter 1). The entire
AlGaN/GaN structure resides on a semi-insulating SiC substrate. Like a MESFET, the
bias across the metal-semiconductor Schottky gate diode controls the depletion region
25
and subsequent flow of electrons from source to drain. However, the current flow with
respect to gate bias behaves differently from that of MESFETs since the depletion region
affects both a densely populated 2DEG as well as a MESFET-like channel in the AlGaN
layer above it.
Although the specifics of the Cree CGH40010 are not known, the conceptual
operation of the generalized HEMT is a valid guideline for the physical operation of the
AlGaN/GaN device modeled here.
2.1.2. Necessity of Modeling
The invention of high power wide bandgap devices has fueled the need for new
characterization and modeling techniques which deal with the side effects of increased
power density and fabrication defects. There exist many different avenues for creating
nonlinear models which can provide accurate predictions of the electrical behavior of SiC
and GaN devices.
2.1.3. Large-signal FET Model Overview
Model development for microwave circuit design is the creation of a mathematical
abstraction which mimics the electrical characteristics of a physical device. Models are
important for understanding the behavior of the device when it is subject to various forms
of electrical excitation.
Circuit designers rely on models to create a virtual test
environment and so that they can simulate designs without the need for trial and error
measurement-based design approaches.
Models are a vital tool for predicting and
analyzing circuit behavior with the goal of maximizing desirable performance
26
parameters. Mathematical FET models fall into one of several categories: physics-based,
empirical analytical-based and empirical table-based.
2.1.3.1.
Physics-based Models
Physics-based models can very accurately predict the electrical and thermal behavior
of a device through knowledge of its structure and composition. They are often used for
experimenting with different physical parameters when designing new devices and,
therefore, may already exist as a precursor to the end-user product.
Physics-based
models are advantageous in that they can precisely interpret the behavior of charge
transport within the semiconductor.
However, due to the time-consuming, multi-
dimensional complexity of simulating physics-based models (finite-element), it is often
not practical to use these models in circuit design. Furthermore, the internal design
parameters such as doping concentrations and exact geometries are unknown, making it
difficult to create a physics-based model from a characterization perspective.
2.1.3.2.
Empirical Models
Circuit designers are only interested in the terminal electrical behavior of the device.
Therefore, only the manifestation of its physical behavior at the external device terminals
is needed. Empirical models are based on the electrothermal properties measured at the
device terminals due to external stimuli. The resulting black-box treatment of the device
under study results in a behavioral abstraction of the physical device capable of
replicating those measured responses. The correctness of the model at the physical level
is only secondary in importance to its behavioral accuracy. In the case of microwave
27
circuits, the current and voltage response over frequency is of prime importance. Second
order physical phenomena such as self-heating and charge-trapping, present in modern
high power devices, are relevant only to the extent of their effect on electrical behavior.
Analytical
Various forms of analytical empirical FET models exist, but the most common one
assumes a generalized circuit topology like that shown in Fig. 2-3. This topology and its
components are based on generic FET physics but are independent of device width, using
consolidated representations of distributed elements. Determination of the parameters is
performed by conducting specific experiments on the device and extracting values from
the measured responses. A correctly defined composite model using this topology can
produce highly accurate predictions.
28
+
-
+
-
Fig. 2-3
A generalized empirical FET model.
Modeling of the major nonlinearities is performed using analytical expressions which
provide concise, yet accurate representations for all nonlinear characteristics. However,
deriving good analytical models is nontrivial. Therefore, improving nonlinear analytical
expressions for the drain current and nonlinear capacitances is heavily emphasized in the
literature.
Table-based
Another option is table-based models which are extremely accurate since the model
directly consists of measured data.
Polynomial curve fitting is usually used in
conjunction with table-based models to interpolate the available data points, thereby
extending the applicability over continuous ranges of biases and drive levels.
29
Although table-based models are highly accurate, analytical models provide better
insight and impart some understanding of basic physical principles. Also, table-based
models require a large amount of stored data which may be difficult to adjust when
accommodating variations of the device under study.
Fortunately, table-based methods can be implemented to various extents and can be
combined with analytical functions. The end-models developed in this work for SiC and
GaN devices are empirically-based using analytical expressions. However, tabulated data
and parameters are extensively used within intermediate modeling stages and act as
placeholders during the parameter consolidation process. This process is illustrated later
in this chapter.
2.1.4. History of Empirical FET Models
The most vital task of large-signal modeling is characterizing and developing
analytical expressions for the drain-source current, I ds , since it is responsible for the IV
characteristics and is the major contributor of device nonlinearity.
30
2.5
Ids (A)
2.0
1.5
1.0
0.5
0.0
0
10
20
30
40
50
Vds (V)
Fig. 2-4
Typical drain current characteristics of FET transistor.
The example set of IV characteristics shown in Fig. 2-4 identifies five distinct
characteristics of the I ds response: the knee region (or linear regime), the pinchoff
region (or cutoff region), and the active region characterized by the transconductance
( g m ) and output conductance due to channel length modulation ( g ds ). Part of developing
a complete I ds model is correctly implementing all of these effects into a single
expression. Two other IV nonlinearities, the maximum drain current limit and the drainsource breakdown region are not included in the I ds expression since they are actually
effects of the Schottky junction diodes.
Next, the major classical empirical FET drain-current models are summarized. All of
these models handle the five IV features in different ways and it is interesting to trace the
evolution of these models over time.
31
Curtice (’80)
I ds (Vgs ,Vds ) = β (Vgs + VT ) (1 + λVds ) tanh (αVds )
2
(2-1)
The Curtice [83] model of (2-1) is one of the first large-signal models and uses a
square-law approximation for the I ds -vs- V gs relationship.
The channel length
modulation is modeled using a linear term. A hyperbolic tangent term is used to model
the linear regime (or region below the knee). However, one drawback is that since the
function is only quadratic, it is incapable of computing intermodulation distortion
products (IMD) and mixer spurious response.
The introduction of this equation is
accompanied by the use of junction diode capacitance models for C gs and C gd .
Materka (’85)
I ds
 Vgs
= I dss 1 −
 VT
2
 αVds

 tanh 
V −V
T

 gs




(2-2)
(2-3)
VT = VT + γVds
The Materka [84] model of (2-2)-(2-3) also utilizes a square law I ds -vs- V gs
relationship but employs the concept of a saturation current I dss ( I ds at V gs =0). A
hyperbolic tan term is used to model the linear region but is a function of both V gs and
Vds to enhance control in the knee region. The pinchoff voltage VT accounts for shifts
due to channel length modulation leading to improved Gds .
Curtice-Ettenberg (’85)
(
)
I ds = A0 + A1V1 + A2V12 + A3V13 tanh (γVds )
(2-4)
32
V1 = Vgs [1 + β (Vds 0 − Vds )]
(2-5)
In the Curtice-Ettenberg [85] model of (2-4)-(2-5), the drain-source formula is
changed from quadratic to cubic. The cubic approximation for the V gs dependence
improves I ds by allowing IMD and spurious product predictions. The channel length
modulation is also handled by a Vds dependency in the V1 term within the cubic
operation. The C gs and C gd equations used in Curtice-Ettenberg are similar to those
used in Curtice ’80. The resulting Gds predictions are better than in the Statz model
(shown next).
Statz (’87)
3
 αVds  
I ds =
  (1 + λVds )
1 − 1 −
1 + b(Vgs − VT )  
3  
β (Vgs − VT ) 
(2-6)
The Statz [86] model of (2-6) combines the square-law operation at small (Vgs − VT )
values with the linear operation at large (Vgs − VT ) values and allows IMD simulation.
For modeling the linear regime, the Statz model uses a truncated polynomial, which
approximates the behavior of a hyperbolic tangent but with improved speed. The channel
length modulation relationship is linear. The Statz model also introduces an improved
capacitance model with a dependence on Vds .
TriQuint’s Own Model (TOM) (’90)
I ds =
(
I ds 0
3
1 − [1 − (αVds ) / 3]
1 + δVds I ds 0
)
(2-7)
33
I ds 0 = β (Vgs − VT ) Q
(2-8)
VT = VT − γVds
(2-9)
TriQuint’s Own Model (TOM) [87] of (2-7)-(2-9) is a modified version of Statz and
introduces an arbitrary power law for the I ds -vs- V gs relationship to increase versatility.
The pinchoff voltage is linearly dependent on
Vds to account for channel length
modulation. Also, there exists a term in the denominator of (2-7) that takes into account
the DC dissipated power of the device, creating a variable I-V slope. The introduction of
dissipated power in the I ds expressions is significant development.
Here, another
approximation of the tanh term is used to improve computational speed. The Statz
capacitance models are used.
Angelov (’92)
I ds = I pk (1 + tanh (ψ ))(1 + λVds ) tanh(αVds )
(2-10)
ψ = P1 (Vgs − V pk ) + P2 (V gs − V pk )2 + P3 (Vgs − V pk )3 K
(2-11)
Angelov [88] introduced the first hyperbolic tangent-based I ds -vs- V gs relationships
for HEMT models shown in (2-10)-(2-11). The model is not mathematically oriented
around the pinchoff voltage, but rather around the peak transconductance and associated
drain-source current and gate-source voltage point ( g mpk , I pk , V pk ). The derivative of the
tanh -based function gives a bell-shaped curve which closely resembles the g m -vs- V gs
characteristic of HEMTs. Device pinchoff is dictated indirectly by the design of ψ and
the shape of tanh rather than by an explicit pinchoff value. The complete model is a
34
product of the hyperbolic tangent, linear channel length modulation and knee inducing
terms.
The Angelov model has been revised in numerous ways over the years
[89][90][91].
A summary of the classical FET drain current models is shown in Table 2-1.
Table 2-1 Summary of classical FET drain current models
Ref
Drain current equation
Features
2
[83] I (V ,V ) = β (V + V ) (1 + λV ) tanh (αV )
-Square-law I ds -vs- V gs
ds
gs
ds
gs
T
ds
ds
-Linear I ds -vs- Vds
- tanh knee region
-No IMD since quadratic
-Junction-based C gs , C ds
[84]
[85]
[86]
[87]
2
 αVds
 V 
I ds = I dss 1 − gs  tanh
 Vgs − VT
 VT 

VT = VT + γVds
(




)
- tanh I ds -vs- Vds vary wrt V gs
-Pinchoff varies with Vds
-Improved g ds - Vds
I ds = A0 + A1V1 + A2V12 + A3V13 tanh (γVds )
-Cubic I ds -vs- V gs
V1 = Vgs [1 + β (Vds 0 − Vds )]
- V gs modified by Vds
- tanh knee region
-Allows IMD sim.
-Curtice caps
-Square-law at V gs small
3
 αVds  
I ds =
  (1 + λVds )
1 − 1 −
1 + b(Vgs − VT )  
3  
β (Vgs − VT ) 
(
3
)
I ds = I d 1 − [1 − (αVds ) / 3] , I d =
I ds 0
1 + δVds I ds 0
I ds 0 = β (Vgs − VT )Q , VT = VT − γVds
[88]
-Square-law I ds -vs- V gs
I ds = I pk [1 + tanh(ψ )](1 + λVds ) tanh(αVds )
ψ = P1 (Vgs − V pk ) + P2 (V gs − V pk ) 2 + ...
P3 (V gs − V pk ) 3 + K
-Linear V gs large
-Approximate tanh with poly.
-Linear I ds -vs- Vds relation
-Allows IMD sim.
-Power-law I ds -vs- V gs
-Power dissipation function
-Pinchoff varies with Vds
-Approximate tanh with poly.
-Statz caps
- 1 + tanh(ψ ) for bell- g m
-Linear I ds -vs- Vds
- tanh knee region
-Angelov caps
35
In summary, early analytical models used quadratic (square-law) relationships but
could only replicate g m behavior that unilaterally increases with V gs . Therefore, cubic or
arbitrary order polynomial relationships were used to improve transconductance while
allowing the prediction of IMD products. However, the high order needed to realize the
pinchoff region and improve the g m -vs- V gs characteristic became cumbersome.
Therefore, the tanh -based model was created to comfortably mimics the bell-shaped g m
and pinchoff region of I ds .
Many recently-developed analytical models use a modified version of Angelov’s
model. This work presents modified versions of Angelov’s model which will adequately
model the unique characteristics of the SiC MESFET and GaN HEMT devices.
2.1.5. Objectives
The main objective is to develop general-purpose empirical large-signal models
capable of accurately predicting the DC, small-signal and large-signal RF behavior of the
representative SiC MESFET and GaN HEMT devices. Each modeling task contains two
parts: (1) characterization and (2) modeling of the physical device in a concise, precise
and comprehensive manner.
In this chapter, a complete and systematic approach to nonlinear characterization,
modeling and verification is presented. A method of characterizing the high power I ds
behavior under various quiescent conditions using dynamic IV measurements is
described.
Key features of the acquired IV data are analyzed to accentuate the
shortcomings of existing models and the modifications needed to improve the IV match.
36
Improved I ds formulations based on Angelov’s model are used to can track the
unique transconductance ( g m ) and output admittance ( g ds ) characteristics of high power
SiC MESFETs and GaN HEMTs up to very high voltage levels. The self-heating and
charge-trapping effects which cause electrical degradation are methodically exploited,
modeled and integrated into the I ds model.
The modeling of the Schottky junction diodes which create hard nonlinearities in the
IV characteristics is also described.
Additionally, computer-aided techniques are
employed on small-signal data to extract and model the intrinsic and extrinsic parasitics
and bias-dependent capacitances.
Validation of the resulting models includes comparisons between measured and
simulated pulsed and dc drain-current behavior, broadband S-parameters and large-signal
multiharmonic gate (input) reflected and drain (output) transmitted RF power over a wide
range of bias, frequency and at various output impedances. Additionally, third-order
intermodulation distortion is also used for model validation.
It is the author’s opinion that this is the most accurate and comprehensive work in
terms of simultaneously large voltage, current, power and frequency range validity for
SiC MESFET and GaN HEMT modeling. The models developed here are eventually
used for the design of high power frequency multipliers described in Chapter 3.
37
2.2.
Technical Approach
2.2.1. Preface to the Modeling Process
The primary goal in this work is to produce a microwave device model that accurately
predicts nonlinear RF behavior. Nonlinear RF accuracy can only be verified after the
complete treatment of all large- and small-signal components using a myriad of linear
and nonlinear, DC and RF, small- and large-signal characterizations. Hence, the model
identification process can often be unnerving without the ability to evaluate the efficacy
of intermediate stages on the large-signal RF accuracy.
Only proven wisdom and
fundamental device physics instills confidence that the end composite model will prevail.
Development of a nonlinear model is fascinating in that it is an integrated multitude
of measurements, components and functionality based on appropriate approximations. In
contrast to closed-form linear modeling, empirical nonlinear modeling is a nontrivial
problem with many possible solutions. It is important to recognize that from an empirical
standpoint, significant assumptions are made in order to compose a working model.
The most important assumption is the adoption of a generalized topology based on
device fundamentals as the model foundation. The assumed physical structure of this
generic FET topology may be significantly different from the actual device and in many
cases, is an extreme simplification. Furthermore, it is assumed that the topology is valid
for all FET devices regardless of device width, length and area and that the extracted
electrical parameters will accurately reflect the properties of these dimensions.
Importantly, the adoption of a generic topology allows the model composer to effectively
apply mature extraction techniques.
38
The detailed technical modeling strategy is described next. In each section, methods
of characterization, parameter extraction and optimization are presented.
Model
descriptions and insights leading to the derivation of those models are included. Detailed
flow algorithms of each sub-procedure are given. Each step of the modeling flow is
accompanied by resulting data and results from the SiC and GaN devices.
The provided algorithms facilitate observation and creation of mathematical models
which can lead to parameter minimization and streamlining of the overall modeling
process. The provided algorithms may not be optimal, but serve as a valid record of the
applied procedure. They may serve as a precursor to a semi-/fully-automated modeling
computer program.
2.2.2. Modeling Topology and Technical Approach
Generalized modeling theory
The complete model topology is shown in Fig. 2-5. The nonlinear elements consist of
the drain current I ds , junction diodes Dgs and D gd and bias-dependent capacitances C gs
and C gd . The drain-source capacitor C ds is usually weakly nonlinear and implementing
it as a bias-dependent component is optional. The linear elements consist of the package
resistances ( R g , Rd , Rs ), inductances ( Lg , Ld , Ls ) and capacitances ( C pg , C pd , C pgd ).
The package parasitics are not shown in the cross section illustration (Fig. 2-3) because
their conceptual location relative to the active device area may vary.
39
Fig. 2-5
Generic nonlinear FET model topology.
While under characterization, the SiC MESFET and GaN HEMT devices were
mounted on a recessed aluminum fixture plate secured to a heat sink and cooling fan
which permits efficient evacuation of heat generated from the device under high power
dissipation. A photograph of the test fixture is provided in Appendix C.1.
40
The complete empirical circuit model is implemented using the Agilent Advanced
Design System (ADS) software.
Fig. 2-6
Model identification process, high level flow.
A systematic modeling strategy is vital since many of the parameters and steps are
codependent. The general algorithm for the device-to-model translation process is shown
in Fig. 2-6. The block diagram illustrates the major steps for extracting all nonlinear
model parameters from the FET device. The suggested order of the model identification
algorithm is shown but certain steps have no restriction on order. The sub-algorithms
corresponding to each major task listed in Fig. 2-6 will be presented in detail. The block
diagram does not show parameter interdependency between stages, but this
interdependency is extremely important to preserve the overall consistency of the model.
41
A summary of the measurements and characterization types used for each model
component is provided in Table 2-2.
Table 2-2. Characterization summary for each component of generic FET model
Parameter
Description
Measurement/Characterization
Nonlinear drain current
Pulsed IV, pulsed-gate IV
I ds
Rth , Cth
Thermal model parameters
I gs DC IV, pulsed-gate IV
V gs ,eff
Pulsed IV
Dgs , D gd
Charge-trapping model
parameters
Nonlinear Diodes
I gs , I gd DC IV
C pg , C pd , C pgd
Extrinsic capacitances
Pinched-FET S-parameters
Lg , Ld , Ls
Extrinsic inductances
Cold-FET S-parameters
R g , Rd , Rs
Extrinsic resistances
C gs , C gd , C ds
Intrinsic capacitances
(Nonlinear)
Fukui DC IV, cold-FET
S-parameters
Hot-FET S-parameters,
large-signal power
Most classic modeling techniques were created along with the technology of the time
so applying them to wide bandgap technologies creates several key challenges. These
include modifying the characterization method and adapting existing mathematical
models valid for high power SiC and GaN technology; designing functional parameter
extraction algorithms; and verifying the efficacy of the modeling process.
Here several important issues are addressed before delving into the detailed model
identification process.
Characterization
As explained in Chapter 1, several physical properties allow wide bandgap devices to
operate under extreme electrical conditions. Where normal technologies would fail under
high voltage excitation, wide bandgap devices can continue to operate, providing
42
increased power output. However, accommodating a heightened electrical and thermal
environment creates many challenges in characterization and requires new testing setups
and procedures. Several test setups are described in Appendix C. Due to the dynamic
properties of the device, applications of pulsed IV measurements are necessary to isolate
and better understand performance degrading effects.
In general, the modeling processes usually are three-fold:
measurement, rough
extraction (by hand or formula), parameter optimization (gradient based to refine element
values and to check consistency). This method is repeated for many of the routines in
this modeling effort.
Data acquisition
Detailed characterization/extraction/curve-fitting algorithms are presented in this
work. However, it is important to note that data acquisition may be performed in a
different order than these algorithms suggest due to time/efficiency constraints. Often,
repeated data acquisitions are performed entirely in a single session followed by
individual processing in later stages of the algorithm.
For example, rather than
measuring and analyzing one PGIV dataset at a time, all expected PGIV measurements
are taken during a single session and each dataset is then is processed by its
corresponding algorithm.
Model derivation
Model derivation depends heavily on the characteristics of the available data, which
dictate the necessary modifications.
Once the features of the data are analyzed,
43
modifications to better accommodate those unique characteristics can be explored. For
example, in the case of the I ds model, the Angelov formula is modified to support
variations across the large drain-source voltage and current ranges. Finalization of the
derived models usually requires performing several iterations of curve-fitting and
adjustment to ensure that the mathematics adequately support the data response. During
this process, an analytical extraction strategy is also developed.
Optimization/tuning
Nearly all parameter determination procedures presented in this work use analytical
extraction to determine an initial fit followed by tuning or computerized optimization to
refine that fit. This tandem analytical-optimization process is repeated as necessary
throughout the model identification. Computerized optimization and tuning are used
frequently in this work to aid in the determination of model parameters. The goal of
optimization and tuning in modeling is to produce a parameter set that allows the model
to replicate a set of measured data as closely as possible. Parameter optimizer may or
may not be set to optimize all the parameters based on the operator’s discretion.
A high-level, conceptual block diagram of the optimization/tuning operator is
illustrated in Fig. 2-7a and is typically implemented in an iterative loop as shown in Fig.
2-7b. An initial parameter set which comes from a preceding analytical extraction is used
to create the first simulated dataset. The optimization/tuning operator compares the
measured and simulated datasets and computes an error which is used to evaluate an
improved, output parameter set. The model is then re-simulated and the process repeats
until changes in the parameter set do not result in improved error.
Fig. 2-7
Simulated dataset
Initial parameter set
Output
parameter set
Output
parameter set
Measured dataset
Initial
parameter set
Simulated
dataset
Measured
dataset
44
Parameter optimizer/tuner conceptual block (a) basic error and parameter
modifier block (b) parameter optimizer/tuner block with model.
Conceptually, the blocks shown in Fig. 2-7 are valid for both manual tuning, in which
a human computes the error (usually graphically) and controls the parameter
modification, and optimization, in which the computer performs those tasks. The details
of the optimizer are not shown in the block diagram, which only serves as an algorithmic
abstraction of the process. The optimizer/tuner block may execute complex analyses,
storing parameter sets and errors at every iteration.
Consistency
Model parameters are extracted from a large plethora of measurements. Therefore it
is important that the completed composite model exhibits behavior which is consistent
45
with the individual measurements from which it was constructed without parameter
conflicts.
For example, DC- and S-parameter-based extraction may produce two different
values for Rg . Depending on the degree of the variation, the model designer must either
reconcile these differences or re-evaluate the applicability of the measurements.
Otherwise, the composite model will only be able to accurately reproduce either the DC
or S-parameters, but not both. Therefore, compromises are made in order to satisfy all of
the criteria.
Another avenue where inconsistencies can exist is between large-signal and smallsignal operation. Certain components extracted using small-signal measurements are
expected to remain constant and valid under large-signal excitation. However, their
values may exhibit incompatibility under large-signal excitation. These behaviors need
to be identified and modeled so that the composite model can predict both small and large
signal responses.
Intrinsic and extrinsic voltage dependencies
Another issue to be addressed is the dependency on intrinsic and extrinsic terminals
identified in the complete model (Fig. 2-5). The extrinsic gate-source and drain-source
voltages are denoted Vgs and Vds , respectively. The intrinsic gate-source and drainsource voltages are denoted Vgsi and Vdsi , respectively. Voltage differences across R g ,
Rd and Rs create discrepancies between the intrinsic and extrinsic voltages and pose an
accuracy problem affecting all nonlinear model elements extracted from terminalmeasured data.
46
Rg
Rd
Vgsi
Ids
Vgs
Vgs
Rs
Fig. 2-8
Vdsi
Ids
DC model showing parasitic resistances.
The DC model of the transistor under active FET operation with R gs =0 is shown in
Fig. 2-8. Both Dgs and D gd are reverse-biased and remain effectively open. Therefore,
no gate current exists and the drain current flows entirely through Rd and Rs between
the drain and source,. In the gate path, the voltage drop across Rs causes Vgsi < Vgs .
Likewise, in the drain path, the voltage drops across Rd and Rs causes Vdsi < Vds .
Performing a KVL analysis of the DC model provides a relationship between the
extrinsic and intrinsic voltages:
V gs = V gsi + I ds R s
(2-12)
Vds = Vdsi + I ds ( Rs + Rd )
(2-13)
Since I ds can often reach values of up to 2A for the SiC MESFET and 2.5A for the
GaN device, Vgsi and Vdsi can both vary by a significant amount from their extrinsic
values. Although the absolute deviation can be much higher for the drain-source voltage
47
than for the gate-source (since ( Rs + Rd ) > Rs ), Vgsi is a larger relative departure from
Vgs than Vdsi is from Vds . Furthermore, I ds is much more sensitive to Vgs , which serves
as its main control mechanism.
There are several methods to addressing this problem. The first method is to pre-map
the measured data onto the internal bias voltages prior to curve fitting. This may be
convenient in the case of I ds since a model can be directly employed on de-embedded IV
data.
However, if the parasitic resistances are altered in any way, either due to
discrepancies in S-parameter- or Fukui-based extraction, the I ds model parameters will
have to be re-evaluated. Furthermore, the exploratory component of creating innovative
I ds formulas comes from observing real data. If de-embedded data is used, the designer
is faced with creating an uncertain model for pre-formed, post-processed data, rather than
one that can assuredly model real data.
The second method is to create a model and extract its parameters based on
externally-measured data, irrespective of voltage drops across parasitic R’s.
The
nonlinear component parameters and terminal dependencies can then be adapted to the
intrinsic voltages once the parasitic R’s have been independently determined.
The
challenge of this method is dealing with parasitic embedded data. This is the method
used throughout this work for all nonlinear components ( I ds , C gs , C gd , Dgs , D gd ).
Although plausible to build the models based on extrinsic voltages ( Vgs and Vds ), it is
technically correct to use intrinsic voltages ( Vgsi and Vdsi ), which properly define the IV
relationship of a two-terminal component. The consequences of using extrinsic voltages
are not known but a problem with simulator convergence may arise. Reliance on external
48
measurements may also set a precedent for the categorization as a behavior model rather
than a circuit model.
2.2.3. Dynamic Drain Current Modeling Using Modified Angelov
In this section, the drain current formulas for SiC MESFETs and GaN HEMTs are
developed. First a detailed background on the Angelov model is given followed by a
discussion on pulsed IV techniques.
Then the drain current derivations of the two
devices are provided followed by the implementation of self-heating and charge-trapping
effects.
2.2.3.1.
Conventional Angelov Approach
The conventional I ds modeling approach uses the Angelov formula of (2-10)-(2-11)
which serves as the basis for many HEMT microwave models due to its mathematical
applicability and efficacy. It is a versatile, elegant and compact way of describing the
device drain current across the entire large-signal transconductance regime. As a singleequation rather than piecewise formulation, it provides the benefits of continuity and
differentiability. The Angelov formula is dissected to illustrate the functional role of
each mathematical element.
Transconductance
The key element is the tanh operation, which provides upper and lower saturation
levels that are synonymous with large-signal current and transconductance behavior of
HEMTs. When Vgs is at or below the pinchoff voltage, V p , the transistor conducts no
49
current. At Vgs > V p , the transistor conducts current and provides positive g m . At some
Vgs significantly above V p , g m decreases for increasing Vgs . The unique shape of the
tanh can concisely embody the pinchoff, active and g m decrease of HEMTs.
The tanh(ψ ) function is symmetric about a “pivot point” as identified in Fig. 2-9a.
At this pivot point, the derivative of tanh(ψ ) reaches a peak. The magnitude of the
tanh(ψ ) curve can be shifted to zero or positive values by adding 1 (Fig. 2-9b) and
scaled by multiplying I pk such that the magnitude ranges from 0 to 2 I pk (Fig. 2-9c).
The ψ expression is a polynomial function of (V gs − V pk ) , which centers the expression
about V pk (Fig. 2-9d). Finally, the power series expression of ψ allows the manipulation
of the shape of the transition between the lower bound 0 and upper bound 2 I pk . A plot
of the effect of ψ on I ds and g m is shown for various values of P1 in Fig. 2-10 and P3 in
Fig. 2-11. (The second order term is zero and is not considered.)
50
2.0
1.0
Ids,a=tanh(psi)
2.0
1.5
0.8
0.0
0.4
-0.5
-1.0
0.5
0.6
0.0
0.4
-0.5
-1.0
0.2
-1.5
0.2
-1.5
-2.0
0.0
-6
-4
-2
0
2
4
-2.0
6
0.0
-6
-4
-2
psi
(a)
1.0
Ids,c=Ipk(1+tanh(psi))
Ipk=0.5
1.5
0.5
2
4
6
0.4
-0.5
-1.0
0.2
-1.5
1.0
Ids,d=Ipk(1+tanh(psi))
psi=(Vgs-Vpk)
Ipk=0.5
Vpk=-2
0.8
0.5
0.6
0.0
0.4
-0.5
-1.0
0.2
-1.5
-2.0
0.0
-6
-4
-2
0
2
4
-2.0
6
psi
(c)
0.0
-6
-4
-2
0
2
4
Vgs
(d)
Explanation of the Angelov model from its mathematical parts (a)
I ds , a = tanh (ψ ) (b) I ds ,b = 1 + tanh (ψ ) (c) I ds ,c = I pk (1 + tanh (ψ )) (d)
I ds , d = I pk (1 + tanh (ψ )) , ψ = (V gs − V pk ) .
(DISS_Angelov_explained.dds)
6
gm,d
0.6
0.0
1.0
gm,c
Ids,c
2.0
0.8
1.0
Fig. 2-9
0
psi
(b)
Ids,d
1.5
gm,b
0.6
gm,a
Ids,a
0.5
0.8
1.0
Ids,b
1.0
2.0
1.0
Ids,b=1+tanh(psi)
1.5
51
1.0
Ids,e
0.8
0.6
Ids,e=Ipk(1+tanh(psi))
psi=P1(Vgs-Vpk)
Ipk=0.5, Vpk=-2
0.2
0.4
Ipk
0.6
0.8
0.4
P1 values
1.0
0.2
Vpk
0.0
-8
-6
-4
-2
0
2
4
Vgs
(a)
0.5
gm,e
0.4
1.0
gmpk
0.8 P1 values
0.6
0.4
0.2
0.3
0.2
0.1
Vpk
0.0
-8
Fig. 2-10
-6
-4
-2
0
2
Vgs
(b)
Behavior of the Angelov model I ds , f = I pk (1 + tanh (ψ )) where
ψ = P1 (Vgs − V pk ) for different P1 values (a) I ds , e -vs- V gs and (b)
g m,e -vs- V gs .
(DISS_Angelov_explained2.dds)
4
52
1.0
Ids,f
0.8
0.6
Ids,f=Ipk(1+tanh(psi))
psi=P1(Vgs-Vpk)+P3(Vgs-Vpk)^3
Ipk=0.5, Vpk=-2, P1=0.6
0
0.025
Ipk
0.05
0.4
P3 values
0.2
Vpk
0.0
-8
-6
-4
-2
0
2
4
Vgs
(a)
0.5
gm,f
0.4
0
gmpk
0.3
P3 values
0.025
0.05
0.2
0.1
Vpk
0.0
-8
-6
-4
-2
0
2
4
Vgs
(b)
Fig. 2-11
Behavior of the Angelov model I ds , f = I pk (1 + tanh (ψ )) where
ψ = P1 (Vgs − V pk ) + P3 (V gs − V pk ) 3 for different P3 values (a) I ds , f -vs- V gs
and (b) g m , f -vs- V gs .
(DISS_Angelov_explained3.dds)
Channel-length modulation
A channel length modulation multiplication factor (1 + λVds ) is used to extend the
I ds -vs- Vgs relationship across Vds . The exact same I ds -vs- Vgs characteristic is scaled as
53
a function of Vds by the channel length modulation parameter, λ . This assumes that the
g m -vs- Vgs shape and the V pk value remain the same and are insensitive to Vds . If the
straight-line portion of the IV curves in saturation is extrapolated towards Vds =0, then the
points intersecting the I ds -axis can be used as a basis for extracting the parameters of the
I ds -vs- Vgs relationship. However, in practice, the I ds -vs- Vds relationship may not follow
such a linear trajectory, and poses an important modeling challenge.
Linear/knee region
The tanh(αVds ) term is used to model the transition from the active region through
the linear regime to zero. This region is called the knee due to the appearance of the
current rolloff towards zero with the α factor determining its steepness. Similar to Fig.
2-9a, the positive tanh(αVds ) slope crosses through the origin then saturates to unity as a
function of Vds .
2.2.3.2.
Dynamic IV Characterization
For mature, lower power technologies like GaAs HEMT, static IV characteristics are
used to represent the small- and large-signal drain current behavior of the device at all
frequencies. However, minor discrepancies between the g m and g ds extracted from
small-signal measurements and those extracted from IV characteristics are sometimes
observed. These effects are attributed to low-level dispersive phenomena and can be
compensated by implementing a supplemental RF g m generator in the large-signal model
[91].
54
2.0
2.0
Dispersion-free IV
Dispersion-heavy IV
1.5
Ids (A)
Ids (A)
1.5
1.0
0.5
Negative Gds?
1.0
0.5
0.0
0.0
0
5
Fig. 2-12
10 15
20 25
30 35
40 45 50
55 60
0
5
10 15
20 25
30 35
Vds (V)
Vds (V)
(a)
(b)
40 45 50
55 60
IV curve example (a) without dispersion and (b) with dispersion.
In the case of high power wide bandgap devices, dispersive phenomena can be
extreme and require innovative characterization and modeling techniques.
Static
measurements of high power-density devices give rise to anomalies in the IV
characteristics, dubbed as “dispersive” or “dispersion.”
Exemplary dispersion-free
(conventional) and dispersion-heavy IV characteristics are shown in Fig. 2-12a and Fig.
2-12b, respectively, illustrating the extreme differences in transconductance and output
admittance. While conventional IV characteristics may be suitable in an RF model,
dispersion-heavy IV characteristics are not since g m declines at high I ds and Vds and g ds
appears to be negative, which is contrary to the physical understanding of FETs.
Increases in Vds cannot lead to decreases in I ds , so another effect is responsible for the
current “droop.” Therefore, g m and g ds extracted from dispersive IV will not be valid in
an RF model since most dispersive phenomena have slow response times and do not track
at high frequency.
55
The discrepancy between the two datasets can be partially explained by self-heating
and charge-trapping. Self-heating arises due to power dissipation in the device which
causes increased lattice temperature, reduced carrier mobility and reduced current.
Charge-trapping arises from fabrication defects which introduce interstitial, chargecapturing energy levels. As a result, the internal E-fields which are responsible for
charge-transport are altered, thereby affecting I ds . Self-heating and charge-trapping are
dynamic processes affected by ambient conditions, DC power dissipation and quiescent
bias.
Static IV characteristics of wide bandgap devices exude a different self-heating and
charge-trapping state at each data point and therefore do not reflect the large-signal RF
IV behavior. It is incorrect to assume that dispersion-heavy, static IV characteristics are
valid at RF and force fit them using conventional I ds models. The use of static IV is
limited to the characterization of DC operating point behavior and should not be
implemented with a direct I ds formula that ignores temperature and transient behavior.
Dispersion cannot be removed but its effect on IV can be characterized using
dynamic IV measurements. Dynamic (or pulsed) IV records the pulsed IV behavior
corresponding to controlled, electrothermal-equilibrium operating points. Pulsed IV data
of dispersive devices share a similar shape with static IV data of dispersion-free devices.
Therefore, they can be modeled using conventional I ds formulas, but are only valid at
specific quiescent points.
The characterization strategy used in this work for wide bandgap devices will employ
two types of dynamic IV measurements: pulsed gate and drain IV (PIV) and pulsed gate
only IV characteristics (PGIV).
56
Pulsed-gate, pulsed-drain IV (PIV)
Fig. 2-13
2.5
2.5
Vgsq=0V
Vdsq=0V
2.0
Vgsq=-3V
Vdsq=30V
2.0
1.5
Ids (A)
Ids (A)
PIV excitation on FET under test.
1.0
0.5
1.5
1.0
0.5
0.0
0.0
0
Fig. 2-14
10
20
30
40
50
0
10
20
30
Vds (V)
Vds (V)
(a)
(b)
40
50
PIV examples with device biased at (a) Vgsq =0V, Vdsq =0V quiescent (zero
trapping, zero self-heating state) and (b) Vgsq =-3V, Vdsq =30V (non-zero
trapping, non-zero self-heating state).
The concept of PIV characterization [92] is illustrated in Fig. 2-13. The FET device
under test is connected to pulse generators with adjustable DC level at the gate and drain.
The gate is biased at a quiescent voltage Vgsq and the drain is biased at a quiescent
voltage Vdsq , giving rise to a quiescent drain current I dsq . The device will dissipate a DC
57
power and reach a steady state temperature through self-heating under this quiescent
operating point. At the same time, the static fields created by the applied Vgsq and Vdsq
will activate certain static trapping mechanisms in the device. The applied Vgsq , Vdsq and
the resulting I dsq give rise to a single static electrothermal operating point for the ensuing
PIV dataset.
An IV measurement is made when the gate and drain are simultaneously pulsed from
their quiescent values to target gate ( Vgs ) and drain ( Vds ) voltages, respectively. The
device will generate a drain current pulse I ds representative of Vgs , Vds and its quiescent
state. This I ds is sampled during the pulse and stored as a data point. The pulsedexcitation process is repeated for combinations of Vgs and Vds to form the points of the
PIV dataset.
The pulses have infinitesimally small rise and fall times and occur for a very short
duration such that Vgs and Vds do not alter the quiescent state. The optimal pulse widths
may vary depending on the device, but in general, the temperature and charge-trapping
state is insensitive to pulses on the order of 100ns [93]. A Nanometrics DiVA Dynamic
I-V Analyzer [94] employing 200ns pulse durations is used to measure all PIV
characteristics presented in this work.
Two example PIV datasets are illustrated Fig. 2-14 conceptually illustrates two PIV
datasets. In Fig. 2-14a, a FET device is biased at Vgsq =0V, Vdsq =0V, I dsq =0A. This
quiescent point is identified with a blue dot. At this bias, there is no self-heating since no
drain current flows and there is no charge trapping since there is no electric field in the
device (under zero applied quiescent bias). One-by-one, the device is pulsed to different
58
Vgs and Vds values and the corresponding I ds is measured until the desired range of Vgs
and Vds values has been covered. Since this is a depletion-mode FET device, Vgs is
pulsed in the negative direction ( Vgs < Vgsq ) for a majority of the data points while Vds is
always pulsed in the positive direction ( Vds > Vdsq ). The characteristic shown in Fig.
2-14a exhibits no dispersion and represents the maximum I ds performance of the device.
In Fig. 2-14b, the same device is biased at Vgsq =-3V, Vdsq =30V resulting in an
I dsq ~800mA and giving rise to a non-zero DC dissipated power. This quiescent point is
identified with a blue dot. As a FET, there is little to no gate-source current or power
dissipation (as long as the device is not pulsed into forward conduction on the gate-source
diode).
Therefore, the DC dissipated power can be computed solely at the drain:
PD = I dsqVdsq =(0.8A)(30V)=24W. The gate and drain voltages are pulsed over the desired
measurement range and I ds is measured. Under this nonzero quiescent bias, the gate and
drain may need to be pulsed below or above the quiescent values in order to cover the
entire IV plane. The device exhibits self-heating which is apparent in the reduction of
output current and current gain compared to the case shown in Fig. 2-14a. Also, the nonzero quiescent biases cause charge-trapping and a further reduction in drain current,
though this effect is smaller than self-heating. The amount of static self-heating and
charge-trapping at this quiescent point ( Vgsq , Vdsq , I dsq ) is embodied in this associated IV
characteristic.
Importantly, both PIV characteristics resemble conventional IV in terms of shape and
do not show negative g ds . PIV is the most accurate way of characterizing the IV
behavior under large-signal RF drive. Most RF circuits are operated in a synonymous
59
matter, like power amplifiers which are biased to a particular operating regime and driven
by a CW excitation. The large-signal drive under a single quiescent bias causes the
current and voltage to swing across the IV plane.
PIV is most appropriate for
characterizing this dynamic IV plane and multiple datasets can provide an understanding
of the IV behavior as a function of quiescent bias.
A pulsed IV measurement system is typically characterized by the maximum
instantaneous pulsed power ( Ppulse = I ds Vds ) that can be supplied. For wide bandgap
devices, high power characterization up to and beyond 100W may be necessary to
develop accurate large-signal models. However, most PIV systems are limited to a
maximum pulse power in the tens of Watts due to the 50 ohm generator impedances
which terminate and provide stability to the DUT [94]. A 50 ohm pulse generator can
deliver its entire voltage to the FET gate, which draws little to no current. However, it
may only deliver a severely reduced voltage to the FET drain, which draws up to several
amps and causes a significant voltage drop across the generator impedance.
Existing medium-power systems [94] are effective but may exclude high drain
voltage/high drain current regions of the IV plane, providing only a limited perspective of
the transistor’s operating regimes. High voltage, high current pulse generators can be
employed but are expensive.
Another possibility is to use lower pulse generator
impedances as long as it does not introduce instability.
Another constraint of high-voltage drain pulsing are the rise and fall times necessary
to produce adequately short-duration that do not alter the charge-trapping state.
Furthermore, performing a comprehensive characterization using only PIV
measurements may be too time-consuming considering the vast number of possible
60
quiescent points. Therefore, for a generalized model valid for all quiescent regions, PIV
may best serve as a companion role in conjunction with other IV datasets to provide a
complete portrait of the device behavior.
Pulsed-gate IV (PGIV)
Fig. 2-15
PGIV excitation on FET device under test. Note: The Vdsq ^ is nearly DC
but will change slightly due to the voltage drop across Rdd when the drain
current pulses.
2.0
2.0
Vgsq=-11V
1.5
Ids (A)
1.5
Ids (A)
Vgsq=-5V
1.0
1.0
0.5
0.5
0.0
0.0
0
10
20
30
Vds (V)
Fig. 2-16
40
50
60
0
10
20
30
40
50
60
Vds (V)
PGIV examples with device biased at (a) Vgsq =-11V (non-zero trapping,
zero self-heating states) and (b) Vgsq =-5V (non-zero trapping, non-zero selfheating states).
Another type of pulsed IV characterization is pulsed-gate IV measurement (PGIV)
[95]. In PGIV measurement, only the gate of the DUT is pulsed while the drain is biased
61
at DC as shown in Fig. 2-15. The gate is biased at Vgsq and the drain is biased at Vdsq ,
giving rise to a quiescent current I dsq . The device settles to a quiescent thermal and
trapping state representative of this bias. The gate is then pulsed from Vgsq to Vgs while
Vdsq remains constant causing the drain current to pulse from I dsq to I ds , which is
sampled and stored. The Vdsq is then changed to the next DC value and the gate voltage
pulsing and I ds sampling process is repeated until an entire IV dataset is obtained.
The PGIV dataset in Fig. 2-16a shows the PGIV dataset corresponding to Vgsq =-11V
(below pinchoff for SiC MESFETs) with quiescent states identified by the blue dots. At
each Vdsq , the gate-source voltage is pulsed from Vgsq to Vgs and the I ds is measured.
The PGIV dataset corresponding to Vgsq =-5V with quiescent states highlighted by blue
dots is shown in Fig. 2-16b. Self-heating exists at Vgsq =-5V, except at Vds =0V. At each
Vgsq value, the gate-source voltage is pulsed above or below Vgsq to obtain the
corresponding I ds measurement.
Unlike PIV, the PGIV dataset embodies many quiescent states ranging over different
Vdsq values. Only one Vgsq value is used in each IV set but the entire range of Vdsq is
represented in the curves. Therefore the resulting PGIV characteristics cannot be as
interpreted in the same way as PIV curves.
There are certain measured I ds points which are shared between PIV and PGIV
datasets.
PGIV
PIV
PGIV
PIV
Under the condition that Vgsq
= Vgsq
and Vdsq
= Vdsq
= VdsPIV , the PIV
measurement is equivalent to the PGIV measurement because Vds is not pulsed. In fact, a
set of PGIV data can be viewed as a composite of individual snapshots of a vast number
62
of PIV datasets. As such, PGIV characteristics are advantageous in that they can provide
a reasonably complete picture of the dispersive IV behavior using a limited number of
datasets.
Since only the gate voltage is pulsed in PGIV, the constraints on the drain excitation
are alleviated and very high pulse power can be achieved with a fairly straightforward
setup using commonly available equipment. A DC supply at the drain may give a low
drain impedance, but causes few stability problems in practice.
However, the lack of pulsed control on Vds prohibits the discrimination between selfheating and charge-trapping effects, which are lumped together under PGIV.
This
limitation also prevents the measurement of an ideal, dispersion-free dataset in which
both self-heating and charge-trapping are set to zero (in depletion mode FET devices,
gate pinchoff requires a negative voltage).
Due to these drawbacks, PGIV characterization alone cannot fully characterize the
self-heating and trapping phenomena in a device. Therefore, PIV, PGIV and a technique
to identify self-heating from charge-trapping effects are necessary.
In this work, Vdsq and Vds are used interchangeably when referring to PGIV
responses. The PGIV system used in this work is described in Appendix C.2.
Pulsed-drain IV (PDIV)
A third type of pulsed measurement is pulsed-drain only (PDIV) measurement.
While PDIV measurements may be useful, especially for exploiting substrate trapping
phenomenon, their advantages are limited since they do not circumvent the power
63
limitations needed for drain pulse generation. As a result, PDIV are not discussed in this
work.
2.2.3.3.
Drain Current Modeling Strategy
It is common practice to build a model around an intended operating point by using a
single set of PIV data along with the necessary RF measurements.
The acquired PIV
dataset is treated as the DC IV behavior, thereby preserving all other standardized
modeling techniques.
Such single-bias models can be reasonably accurate under
moderate nonlinear RF operation. However, the model may not be adequate for highly
nonlinear operation in which the internal operating point shifts under large RF drive.
Also, biasing the device at a different operating point will require a new model in most
cases.
More recently, the development of a unified model that can track the dynamic IV
behavior over quiescent bias has been explored. An ideal approach would be to obtain
the PIV characteristics measured under zero self-heating and zero charge-trapping
conditions to serve as a dispersion-free foundation for I ds .
Then, self-heating and
charge-trapping functionality is added to the foundation model. This strategy, however,
does not circumvent the power limitations of PIV measurement.
In this work, a method of using a combination of PGIV and PIV (without an
excessive number of datasets) to produce a complete characterization over a wide range
of biases is described [73][74]. High power PGIV data are used to characterize the selfheating thermal effects, while supplemental medium-power PIV sets are used to
characterize the charge-trapping effects on I ds .
64
Evolution of the drain current formula
The SiC MESFET and GaN HEMT I ds equations evolve through several phases as
illustrated in Fig. 2-17 and Fig. 2-18, respectively. These figures serve as a roadmap for
I ds as it increases in complexity and functionality. The processes for the two devices
vary slightly since, chronologically, the SiC MESFET was investigated first, followed by
the GaN HEMT. Therefore some exploratory aspects are included in the SiC MESFET
modeling process.
On the other hand, the GaN HEMT modeling process is more
consolidated.
In the first phase, I ds equations are derived by adapting the Angelov model to the SiC
MESFET and GaN HEMT devices, respectively, based on detailed analyses of high
power PGIV data under zero self-heating. The resulting equations form the foundation of
the SiC and GaN I ds models and are detailed in Chapter 2.2.3.4 and 2.2.3.5, respectively.
In the second phase, self heating and its effect on drain current is investigated using
PGIV over a comprehensive range of quiescent biases. A self-heating thermal model is
created and thermal modifications on the I ds model are implemented, adding the ability
to predict PGIV datasets under various self-heating conditions. This phase is detailed in
Chapter 2.2.3.6.
In the third phase, charge-trapping and its effect on I ds is investigated using PIV at
select quiescent biases. Charge-trapping is integrated into the I ds model in the form of
deembedding formulas allowing for accurate predictions of PIV characteristics under
various trapping conditions. This phase is detailed in Chapter 2.2.3.7.
65
The deembedding of parasitic resistances as described in Chapter 2.2.2.7 by
modifying the terminal dependencies of I ds for intrinsic biases significantly affects the
I ds parameters and marks the first step of integrating I ds into the larger component
network of Fig. 2-5. There is no required order for performing the deembedding step.
For the SiC MESFET, deembedding is performed in SiC-Phase Ib, after deriving the
foundation model of I ds in SiC-Phase Ia.
For the GaN HEMT, deembedding is
performed in GaN-Phase IIb, after the implementation of thermal self-heating in GaNPhase IIa.
In many of the equations presented in this chapter, the intrinsic voltages dependencies
are omitted to preserve generality, but must be used at some point under practical
applications.
66
SiC-Phase Ia: Create Ids for high power IV
I ds = I pk (1 + tanh(ψ ) )
ψ = P1 (Vgs − V pk ) + P2 (Vgs − V pk )2 + ... + PN (Vgs − V pk )N
M
Pn = (Qn 0 + Qn1Vds + ... + Qn MVds ) tanh(α PnVds ) + Pno , n = 1,3,4
SiC MESFET
Ids Phases
SiC-Phase Ib: Modify Ids for intrinsic voltages
I ds = I pk (1 + tanh(ψ ) )
ψ = P1 (Vgsi − V pk i ) + P2 (Vgsi − V pk i )2 + ... + PN (Vgsi − V pk i )N
M
Pn = (Qn 0 + Qn1Vdsi + ... + Qn MVdsi ) tanh(α PnVdsi ) + Pn o , n = 1,3,4
SiC-Phase II: Modify Ids for self-heating
SiC-Phase III: Modify Ids for charge-trapping
I ds = I pkth (1 + tanh(ψ ) )
I ds = I pkth (1 + tanh(ψ ) )
ψ = P1th (Vgsi − V pk ) + P2th (Vgsi − V pk )2 + ... + PNth (Vgsi − V pk )N
M
Pn ,T = (Qn 0 + Qn1Vdsi + ... + QnMVdsi ) tanh(α PnVdsi ) + Pno , n = 1,3,4
ψ = P1th (Vgs,eff − V pki ) + P2th (Vgs,eff − V p ki )2 + ... + PNth (Vg s,eff − V pki )N
M
Pn ,T = (Qn 0 + Qn1Vdsi + ... + QnMVdsi ) tanh(α PnVdsi ) + Pno , n = 1,3,4
Rth = R2 exp(− PD / δ 2 ) + R1 exp(− PD / δ1 ) + R0
Rth = R2 exp(− PD / δ 2 ) + R1 exp(− PD / δ1 ) + R0
0
(
3
2
)
I pk ,T0 = J 3Vds + J 2Vds + J1Vds + J 0 tanh(α IpkVds )
I pkth =
K Ipk
I pk ,T0
1 + K Ipk ∆T '
= K Ipk1Vdsq + K Ipk 0
(
∆T ' = ∆T = Rth PD (steady state)
(
Pnth = Pn,T0 (1 + K Pn ∆T ' )
K Pn = K Pn, 2Vds + K Pn,1Vds + K Pn, 0 , n = 1,3,4
K Pn,u = K Pn,u 2 (Vgs − Vgsq, Pn,u ) 2 + K Pn,u1 (Vgs − Vgsq, Pn,u ), u = 0,1, 2
3
2
)
I pk ,T0 = J 3Vds + J 2Vds + J 1Vds + J 0 tanh(α IpkVds )
I pkth =
K Ipk
)
K Ipkj = K Ipkj max 1 − (−1) j tanh(ψ Ipkj )
ψ Ipk j = C j1 (Vg sq − V gsq, Ipk j ) + C j 3 (V gsq − Vgsq, Ipk j) 3 , j = 0,1
2
0
I pk ,T0
1 + K Ipk ∆T '
= K Ipk1Vdsq + K Ipk 0
(
K Ipkj = K Ipkj max 1 − (−1) j tanh(ψ Ipkj )
∆T ' = ∆T = Rth PD (steady state)
)
ψ Ipk j = C j1 (Vgsq − Vgsq, Ip k j) + C j 3 (Vg sq − Vgsq, Ipk j )3 , j = 0,1
Pnth = Pn,T0 (1 + K Pn ∆T ' )
2
K Pn = K Pn, 2Vds + K Pn,1Vds + K Pn, 0 , n = 1,3,4
K Pn,u = K Pn,u 2 (Vgs − Vgsq, Pn,u ) 2 + K Pn,u1 (Vgs − Vgsq, Pn,u ), u = 0,1, 2
Vgs ,eff = V gsi + Voff ,subs
Voff ,subs = ρ subs (Vds − Vdsq )
ρ subs = ρ subs1 (Vdsq + Vsubs0 )
Fig. 2-17
The evolutionary phases of I ds for the SiC MESFET model.
Practical simulation
Different simulation types are required at each development phase of I ds . The I ds
derivation of phase I is performed using DC simulations to explore the validity of certain
equation formats. However, once dispersive effects are considered in Phase II and III,
transient simulations are required since the simulator must maintain the steady-state
isothermal, isotrapping conditions of the device while it is excited to different voltages.
Only transient simulations will allow the validation of the pulsed IV model behavior
versus data.
67
GaN-Phase I: Create Ids for high power IV
I ds = I pk (1 + M Ipk tanh(ψ ) )tanh(αVds )
ψ = P1 (Vgs − V pk1 ) + P2 (V gs − V pk 2 ) 2 + P3 (Vgs − V pk 3 )3
M Ipk = 1 + (1 / 2)∆M Ipk (1 + tanh(ψ M ) )
ψ M = QM (Vgs − VgsM )
∆M Ipk = M Ipkb − 1
GaN-Phase IIb: Modify Ids for intrinsic voltages
I ds = I pkth (1 + M Ipk tanh(ψ ) )tanh(αVdsi )
Pn = ( Pn 0 + Pn1Vds ) tanh(α PnVds ) + Pno , n = 1, 2,3
2
3
M Ipkb = ( PM 0 + PM 1Vds + PM 2Vds + PM 3Vds ) tanh( α M Vds ) + PMo
QM = ( PQ 0 + PQ1Vds ) tanh(α QVds ) + PQo
ψ = P1th (Vgsi − V pk1 ) + P2th (Vgsi − Vpk 2 ) 2 + P3th (Vgsi − Vpk 3 )3
M Ipk = 1 + (1 / 2)∆M Ipk (1 + tanh(ψ M ) )
ψ M = QM (Vgsi − VgsM )
∆M Ipk = M Ipkbth − 1
Pn ,T0 = ( Pn 0 + Pn1Vdsi ) tanh(α PnVdsi ) + Pno , n = 1, 2,3
2
GaN-Phase IIa: Modify Ids for self-heating
I ds = I pkth (1 + M Ipk tanh(ψ ) )tanh(αVds )
2
ψ = P1th (Vgs − V pk1 ) + P2th (Vgs − V pk 2 ) + P3th (Vgs − V pk3 )
M Ipk = 1 + (1 / 2)∆M Ipk (1 + tanh(ψ M ) )
ψ M = QM (Vgs − VgsM )
3
∆M Ipk = M Ipkbth − 1
3
M Ip kb,T0 = ( PM 0 + PM 1Vdsi + PM 2Vdsi + PM 3Vdsi ) tanh(α M Vd si ) + PMo
QM = ( PQ0 + PQ1Vdsi ) tanh(α QVdsi ) + PQo
∆T ' = ∆T = Rth PD (steady state)
I pkth = I pk ,T0 (1 + K Ipk ∆T ' )
K Ipk = ( K Ipk 0 + K Ipk 1Vdsi ) tanh(α KIpk Vdsi )
Pnth = Pn ,T0 (1 + K Pn ∆T ' ), n = 1, 2,3
K Pn = ( K Pn0 + K Pn1Vdsi ) tanh(α KPnVdsi ), n = 1,2,3
M Ipkbth = M Ipkb,T0 (1 + K MIpkb∆T ' )
K MIpk b = ( K MIpk b0 + K MIpk b1Vdsi ) tanh(α KMIpk bVdsi )
Pn ,T0 = ( Pn0 + Pn1Vds ) tanh(α PnVds ) + Pno , n = 1,2,3
2
3
M Ipkb,T0 = ( PM 0 + PM 1Vds + PM 2Vds + PM 3Vds ) tanh(α M Vds ) + PMo
QM = ( PQ 0 + PQ1Vds ) tanh(α QVds ) + PQo
I pkth = I pk ,T0 (1 + K Ipk ∆T ' )
∆T ' = ∆T = Rth PD (steady state)
K Ipk = ( K Ipk 0 + K Ipk1Vds ) tanh(α KIpkVds )
Pnth = Pn ,T0 (1 + K Pn ∆T ' ), n = 1, 2,3
K Pn = ( K Pn 0 + K Pn1Vds ) tanh(α KPnVds ), n = 1,2,3
M Ipkbth = M Ipkb,T0 (1 + K MIpkb∆T ' )
K MIpk b = ( K MIpk b0 + K MIpk b1Vds ) tanh(α KMIpk bVds )
GaN-Phase III: Modify Ids for charge-trapping
I ds = I pkth (1 + M Ipk tanh(ψ ) )tanh(αVdsi )
ψ = P1th (Vgs,eff − V pk1 ) + P2th (Vgs,eff − V pk 2 ) 2 + P3th (Vgs,eff − V pk3 ) 3
M Ipk = 1 + (1 / 2)∆M Ipk (1 + tanh(ψ M ) )
ψ M = QM (V gs,eff − V gsM )
∆M Ipk = M Ipkbth − 1
Pn ,T0 = ( Pn 0 + Pn1Vdsi ) tanh(α PnVdsi ) + Pno , n = 1, 2,3
2
3
M Ip kb,T0 = ( PM 0 + PM 1Vdsi + PM 2Vdsi + PM 3Vdsi ) tanh(α M Vd si ) + PMo
QM = ( PQ0 + PQ1Vdsi ) tanh(α QVdsi ) + PQo
I pkth = I pk ,T0 (1 + K Ipk ∆T ' )
∆T ' = ∆T = Rth PD (steady state)
K Ipk = ( K Ipk 0 + K Ipk 1Vdsi ) tanh(α KIpk Vdsi )
Pnth = Pn ,T0 (1 + K Pn ∆T ' ), n = 1, 2,3
GaN HEMT
Ids Phases
K Pn = ( K Pn0 + K Pn1Vdsi ) tanh(α KPnVdsi ), n = 1,2,3
M Ipkbth = M Ipkb,T0 (1 + K MIpkb∆T ' )
K MIpk b = ( K MIpk b0 + K MIpk b1Vdsi ) tanh(α KMIpk bVdsi )
Vgs ,eff = V gsi + Voff ,subs + Voff ,surf
Voff , subs = ρ subs (Vdsi − Vdsqi )
ρ subs = ρ subs1 (Vdsqi + Vsubs0 )
Voff , surf = ρ surf (Vgsi − V p )
ρ surf = ρ surf 1 (Vgsqi − Vp )
Fig. 2-18
The evolutionary phases of I ds for the GaN HEMT model.
68
2.2.3.4.
SiC MESFET Drain Current
Definition
Development of a drain current equation that can accurately express the highly
nonlinear behavior of high current, high voltage SiC MESFET devices is the most
challenging aspect of modeling. The SiC MESFET drain current can reach up to 2A at
drain voltages up to 58V and exhibit many nonlinear nuances.
Although the original Angelov I ds model [88] assumes separability of Vgs and Vds
and a linear dependency on Vds , later work by the same group has shown a strong
interdependence of I ds parameters on both Vgs and Vds . This appears necessary to
accurately model high power devices that exhibit significant self-heating and current
dispersion [49][53][54].
In devices such as high-power SiC MESFETs, it is especially important to model the
nonlinear relationships between I ds and Vgs across the entire range of Vds in both
saturation and linear regimes. Such an expansive fit requires functions of adequate
generality, which can be tailored for the particular device of interest.
The drain-current model employed in this study is presented in (2-14)-(2-16) and is
an adaptation of the Angelov model [89][90][91] to improve the fit over high I ds and
high Vds ranges.
To achieve this, the Pn and I pk parameters are converted from
constants into functions of Vds .
I ds = I pk (1 + tanh(ψ ) )
(2-14)
ψ = P1 (Vgs − V pk ) + P2 (Vgs − V pk )2 + ... + PN (Vgs − V pk )N
(2-15)
Pn = (Qn 0 + Qn1Vds + ... + QnM Vds ) tanh(α PnVds ) + Pno , n = 1,2, K, N
(2-16)
M
69
Here, the Pn parameters of the power series describing the Vgs dependence are each a
power series expansion of Vds multiplied by a tanh(α PnVds ) term and shifted by Pno .
The parameter V pk is normally the Vgs value at the peak transconductance g mpk .
HEMT devices exhibit a bell-shaped g m from which g mpk can be identified. For
high power HEMTs, the accompanying V pk can vary as a function of Vds . However, as
can be seen from Fig. 2-19, the SiC MESFET biased in its active region does not present
a bell-shaped response by the same mechanism as in HEMTs. The exception is at the
low Vds regime, which is accommodated by using the Pno and tanh(α PnVds ) terms for
each Pn parameter.
The lack of a bell-shaped g m in SiC MESFETs causes the selection of g mpk to lose
its usual meaning. Therefore, it is necessary to select a certain V pk such that the draincurrent model can be used effectively. This selected V pk will serve as a mathematical
pivot point for which the hyperbolic tan operation of (Fig. 2-9) can anchor onto and use
its lower tail to model I ds (see Chapter 2.2.3.1).
70
SiC MESFET: PGIV Vgsq=[-11:0.5:0.5], Vdsq=[5,55]V
0.30
Vgsq=-11.0V
Vdsq=55V
gm (A/V)
0.25
0.20
0.15
0.10
Vdsq=5V
0.05
0.00
-11 -10 -9
-8
-7
-6 -5 -4 -3
-2
-1
0
1
0
1
Vgs (V)
(a)
2.0
Vgsq=-11.0V
Vdsq=55V
Ids (A)
1.5
1.0
0.5
Vdsq=5V
0.0
-11 -10 -9
-8
-7
-6 -5 -4 -3
-2
-1
Vgs (V)
(b)
Fig. 2-19
Measured and modeled PGIV I ds -vs- V gs characteristic. (SiC)
(DISS_Tran_ls_model_xtr3633_IV_PGIV_gm_vgsq110_opt.dsn)
Parameter Identification
In characterizing the SiC MESFET, a multiplicity of PGIV measurements is taken to
obtain the device’s performance over varying levels of dispersion. The IV characteristics
71
of the device are measured from V gs =[-11.0:0.5:0.5]V and Vds =[0:2:58]V at quiescent
biases of V gsq =[-11.0:0.5:-3.0]V using a pulse width of 100ns and a pulse period of
400ms. The pulse parameters are carefully chosen here to prevent the onset of dispersion
during the pulsed state and sufficient relaxation of the dynamic device behavior between
pulses.
The algorithm used for the SiC MESFET I ds modeling and parameter extraction is
shown in Fig. 2-20. Although the SiC datasheet [78] states a V p =-10V, the device may
produce current slightly below Vgsq =-10V at high Vds voltages due to channel length
modulation. Therefore, the curve-fitting process is demonstrated by modeling the PGIV
dataset at Vgsq =-11.0V, since this case is guaranteed free of static self-heating, even at
high Vds . First, the g m behavior of the acquired PGIV data is analyzed using the
algorithm provided in Fig. 2-21. In this analysis, g m -vs- Vgs curves at each Vds are
computed from the PGIV dataset. Then, g mpk and V pk are systematically extracted from
the responses.
72
Measure Pulsed Gate IV Curves
Vgs
gmpk, Vpk, Ipk
analysis and
modeling
Vds
Divide IV into Ids vs Vgs at each available Vds
Curve fit Ids-vs-Vgs
Vds #1
Ipk
Curve fit Ids-vs-Vgs
Vds #2
Vpk
P2
Curve fit Ids-vs-Vgs
Vds #3
Vpk
Vgs
P1
Ipk
P3
P4
P1
P2
Curve fit Ids-vs-Vgs
Vds #N
Vpk
Vgs
P3
P4
P1
P2
Vgs
P3
P4
P1
Parameter set #3
P2
P3
P4
Parameter set #N
Collect Pn parameters and sort vs Vds
Curve fit P1-vs-Vds
Curve fit P2-vs-Vds
Vds
Curve fit P3-vs-Vds
Curve fit P4-vs-Vds
Vds
Vds
Vds
Q20 Q21 αP2 P2o
Q30 Q31 αP3 P3o
Q10 Q11 αP1 P1o
Q40 Q41 αP4 P4o
Collect Parameters
Simulate PGIV
curves from Model
Vgs
Vgs
Vds
Vds
Parameter Optimizer
Qnm αPn Pno
Final Parameter Set
Fig. 2-20
Algorithm for modeling I ds (V gs , Vds ) . (SiC)
Ipk
Vpk
Vgs
Parameter set #2
Parameter set #1
Ipk
Measured
Ids(Vgs,Vds)
73
(
3
2
I pk ,T0 = J 3Vds + J 2Vds + J 1Vds + J 0
)
Fig. 2-21
Extracted
Ipk vs Vds
Vpk0
tanh(α IpkVds )
Algorithm for analyzing and modeling g mpk , V pk and I pk . (SiC)
The g m -vs- Vgs characteristics for the SiC MESFET at four different Vds values are
shown in Fig. 2-22. Since the g m computed from the derivative of the raw data exhibits
inaccuracies, a polynomial is fitted to the g m curves to accentuate the extraction of g mpk
and V pk , instead of performing a direct extraction from data. The overlaying polynomial
fits are shown in Fig. 2-22.
74
gm at Vds=4V, PGIV Vgsq=-11.0V
gm at Vds=12V, PGIV Vgsq=-11.0V
0.15
0.3
0.25
0.1
0.2
gm
gm
0.15
0.05
0.1
0.05
0
0
-0.05
-15
-10
-5
Vgs
0
-0.05
-15
5
0.3
0.25
0.25
0.2
0.2
0.15
0.15
0.1
0.05
0
0
Fig. 2-22
-10
-5
Vgs
0
0
5
0.1
0.05
-0.05
-15
-5
Vgs
gm at Vds=48V, PGIV Vgsq=-11.0V
0.3
gm
gm
gm at Vds=24V, PGIV Vgsq=-11.0V
-10
5
-0.05
-15
-10
-5
Vgs
0
5
PGIV-computed g m -vs- Vgs at four Vds values illustrating no peaking
behavior except at low Vds . (SiC)
(DISS_yuk_orig_dec07\tanhfit_IV_dec07.m, f199)
Collecting the extracted g mpk and the corresponding V pk over Vds results in the
curves shown in Fig. 2-23a and Fig. 2-23b, respectively.
The V pk -vs- Vds response
appears to be prematurely limited by the maximum available Vgs value of 0.5V. As
described previously, the g m of MESFET devices does not exhibit peaking by the same
mechanism found in HEMTs, but will eventually peak due to forward conduction of D gs .
75
The true peaking behavior is not observed since the pulsed-gate voltage levels are limited
to 0.5V to protect the device from gate-source overdrive. Furthermore, there is not
enough resolution at data points above Vgs >0 to allow a pinpoint of the true g mpk and V pk
for all Vds .
(b) Vpk extracted from PGIV Vgsq=-11.0V
2
0.3
0
0.25
-2
0.2
-4
Vpk
gmpk
(a) gmpk extracted from PGIV Vgsq=-11.0V
0.35
0.15
-6
0.1
-8
0.05
-10
0
0
Fig. 2-23
10
20
30
Vds
40
50
60
-12
0
10
20
30
Vds
40
50
60
(a) g mpk -vs- Vds and (b) V pk -vs- Vds extracted from PGIV at Vgsq =-11.0V.
(SiC)
(DISS_yuk_orig_dec07\tanhfit_IV_dec07.m, f1)
A solution is to select the maximum Vgs data point to serve as a constant valued V pk
as illustrated in the blue line shown in Fig. 2-23b. Selecting a constant V pk =0.5V is
reasonable as it does coincide with the actual g mpk value at Vds =22V. The justification
for this approximation is similar to the selection of V p in some classical models in which
a constant value extracted at the onset of the active region is used [83][86], although by
definition, the pinchoff point inevitably changes with Vds due to channel length
76
modulation [87]. Furthermore, the model of [88] uses a constant V pk and makes no case
of its variation across Vds .
The corresponding I pk = I ds (at Vgs = V pk =0.5V) is used to form a table-based
I pk -vs- Vds model, which is passed to the curve-fitting stage of the modeling algorithm
shown in Fig. 2-20. The functional versatility of the Angelov formula will allow for
modeling of the IV data even though the V pk is not exact for all Vds .
In the next extraction stage, the PGIV dataset is divided into individual I ds -vs- Vgs
curves according to Vds and each is modeled using expressions (2-14)-(2-15). The curve
fitting operation uses the table-based I pk model from the g m analysis and relies on
optimization to determine the Pn parameters. One of the tasks in this process is to
determine the minimum order of ψ necessary to adequately reproduce the response.
Results of curve-fitting I ds -vs- Vgs at several Vds are shown in Fig. 2-24.
77
Ids vs Vgs, Vds=12V
2
1.5
1.5
Ids
Ids
Ids vs Vgs, Vds=4V
2
1
0.5
0
1
0.5
-10
-5
Vgs
0
0
-10
2
1.5
1.5
1
0.5
0
Fig. 2-24
0
Ids vs Vgs, Vds=48V
2
Ids
Ids
Ids vs Vgs, Vds=24V
-5
Vgs
1
0.5
-10
-5
Vgs
0
0
-10
-5
Vgs
0
Independently modeled I ds -vs- Vgs curves at four Vds biases. (SiC)
(DISS_yuk_orig_dec07\tanhfit_IV_dec07.m, f299)
The outcome of the optimization-assisted curve-fitting process are the Pn parameters
which are plotted against Vds as shown in Fig. 2-25. A fourth order ψ function appears
to provide an adequate fit for all Vds biases. Also, due to the mathematical form of the
Angelov model, P2 is zero, further simplifying the extraction.
The three other Pn
parameters are modeled using expression (2-16) to obtain the Qnm , α Pn and Pno curvefitting parameters.
78
-4
0
x 10
-3
(a) P4 vs Vds
0
x 10
(b) P3 vs Vds
0
20
-0.2
-1
P3
P4
-0.4
-2
-0.6
-3
-4
-0.8
0
20
40
-1
60
Vds
-4
2
x 10
(c) P2 vs Vds
(d) P1 vs Vds
0.2
0.15
P1
P2
60
Vds
1
0
-1
-2
40
0.1
0.05
0
20
40
60
0
0
Vds
Fig. 2-25
20
40
60
Vds
Extracted and modeled Pn -vs- Vds (a) P1 (b) P2 (c) P3 (d) P4 . (SiC)
(DISS_yuk_orig_dec07\tanhfit_IV_dec07.m, f1000)
The measured and modeled PGIV responses prior to optimization for Vgsq =-11.0V are
shown in Fig. 2-26. The computed results show that, for a large range of biases, the
formulation is extremely effective at modeling the PGIV characteristics with zero static
power dissipation. All other Pn parameters are equal to zero.
79
PGIV complete analytical model Vgsq=-11V,Vgs=[-11.0:0.5:0.5]V
2
Ids (A)
1.5
1
0.5
0
Fig. 2-26
0
10
20
30
Vds (V)
40
50
60
PGIV for Vgsq =-11.0V after parameter extraction but prior to parameter
optimization for Vgsq =-11.0V. (SiC)
(DISS_yuk_orig_dec07\tanhfit_IV_dec07.m, f600)
The parameter set composed of Qnm , α Pn and Pno are then optimized to further
improve the fit with data and ensure that the entire IV dataset is maximally matched to
(2-14)-(2-16). The I ds , g m and g ds for the PGIV at Vgsq =-11.0V are shown in Fig. 2-27
from which the fidelity of the model can be confirmed. Additionally, a zoomed view of
I ds at low current levels is provided.
80
SiC MESFET: Vgsq=-11.0V, Vgs=[-12:0.5:0.5]V, Vgs=[0:2:58]V
(a)
(b)
2.2
0.30
2.0
0.25
1.8
1.6
0.20
1.2
Ids (A)
Ids (A)
1.4
1.0
0.8
0.15
0.10
0.6
0.4
0.05
0.2
0.0
0.00
0
10
20
30
40
50
60
0
10
20
Vds (V)
30
40
50
60
Vds (V)
(c)
(d)
0.35
0.25
0.30
0.20
0.25
0.15
gds (A/V)
gm (A/V)
0.20
0.15
0.10
0.10
0.05
0.05
0.00
0.00
-0.05
-0.05
-12
-10
-8
-6
-4
-2
0
1
0
5
10
Vds (V)
15
20
25
30
35
40
45
50
55
60
Vds (V)
Qn0
Qn1
alphaPn
Pno
n=4
-1.538E-4
8.032E-7
3.764E-2
-1.614E-4
n=3
-4.698E-4
-6.020E-7
9.825E-2
1.100E-3
n=1
1.483E-1
-2.788E-4
1.338E-1
1.981E-2
DISS_IV_equation_xtr3633_IV_PGIV_vgsq110_dec07_opt
Fig. 2-27
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-11.0V showing I ds , g m and g ds . (SiC)
(DISS_IV_equation_xtr3633_IV_PGIV_vgsq110_dec07_opt.dsn)
The I ds modeling process is applied to all available PGIV datasets to investigate the
evolution of its parameters under different levels of dispersion, especially self heating.
This will serve as a precursor to the self-heating model discussed in Chapter 2.2.3.6. The
results for modeling the PGIV dataset at Vgsq =-3.0V are shown in Fig. 2-28 and
81
demonstrate (2-14)-(2-16)’s ability to represent even highly dispersive PGIV
characteristics.
The post-optimization I ds model parameters for all available PGIV
datasets are given in Table A-1.
SiC MESFET: Vgsq=-3.0V, Vgs=[-12:0.5:0.5]V, Vgs=[0:2:58]V
(a)
(b)
2.2
0.30
2.0
0.25
1.8
1.6
0.20
1.2
Ids (A)
Ids (A)
1.4
1.0
0.8
0.15
0.10
0.6
0.4
0.05
0.2
0.0
0.00
0
10
20
30
40
50
60
0
10
20
Vds (V)
30
40
50
60
Vds (V)
(c)
(d)
0.35
0.25
0.30
0.20
0.25
0.15
gds (A/V)
gm (A/V)
0.20
0.15
0.10
0.10
0.05
0.05
0.00
0.00
-0.05
-0.05
-12
-10
-8
-6
-4
-2
0
1
0
5
10
Vds (V)
15
20
25
30
35
40
45
50
55
60
Vds (V)
Qn0
Qn1
alphaPn
Pno
n=4
-1.532E-4
7.958E-7
9.661E-2
-1.269E-4
n=3
-5.205E-4
-1.757E-6
9.731E-2
1.152E-3
n=1
1.460E-1
-1.627E-4
1.440E-1
2.818E-2
DISS_IV_equation_xtr3633_IV_PGIV_vgsq030_dec07_opt
Fig. 2-28
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-3.0V showing I ds , g m and g ds . (SiC)
(DISS_IV_equation_xtr3633_IV_PGIV_vgsq030_dec07_opt.dsn)
(yuk_orig_dec07/vgsq030/tanhfit_IV_dec07.m)
(IV_equation_xtr3633_IV_PGIV_vgsq030_dec07.dsn)
82
Intrinsic dependencies
The SiC MESFET I ds equation is transitioned from external to internal bias
dependency as described in Chapter 2.2.2.7 and the affected parameters are selectively
compensated. The parameters affected by the intrinsic bias transition are I pk , V pk , Qnm ,
α Pn and Pno .
As a table-based model, I pk does not have any dynamic terminal
dependencies and therefore, its values do not need to be modified to reflect the adoption
of V gsi and Vdsi . Instead it can remain as a lookup table as long as the applied external
terminal voltages of the model are accessible. (Note: If desired, the table-based I pk
model can be adapted to depend on intrinsic Vdsi by transforming the Vds =0 to 58V table
range into a corresponding Vdsi range.)
However, it is imperative that V pk within the (2-15) is modified since the adapted
V pki (the Vgsi value under Vgs = V pk =0.5V) must correlate with Vgsi in ψ . Since I pk is
defined over a large Vds range, V pki can be defined over the same range by equating
Vgsi = V pki , I ds = I pk and rearranging (2-12):
V pki = I pk Rs − V pk
(2-17)
Once I pk and V pk have been modified, the Qnm , α Pn and Pno parameters can be
adjusted using gradient-based optimization on the large-signal model implementing
parasitic resistances.
provided in Table 2-3.
The final SiC MESFET I ds parameters for Vgsq =-11.0V are
83
I ds parameters, final deembedded and optimized (SiC)
Table 2-3
Q40
-244.43e-6
Q30
-607.70e-6
Q10
172.53e-3
2.2.3.5.
Q41
1.3891e-6
Q31
-925.45e-9
Q11
-302.75e-6
α P4
62.717e-3
α P3
107.26e-3
α P1
147.32e-3
P4o
-256.11e-6
P3o
443.88e-6
P1o
27.988e-3
GaN HEMT Drain Current
Definition
The Angelov model [88][91] has frequently been used to model HEMT I ds due to
improved predictions of g m on GaN HEMTs [49][50]. An analytical I ds model based on
[74][96] is developed here for the high-power GaN HEMT. This new model is given by
(2-18)-(2-22) as:
I ds = I pk (1 + M Ipk tanh(ψ ) ) tanh(αVds )
(2-18)
ψ = P1 (Vgs − V pk1 ) + P2 (Vgs − V pk 2 ) 2 + P3 (Vgs − V pk 3 )3
(2-19)
M Ipk = 1 + (1 / 2)∆M Ipk (1 + tanh(ψ M ) )
(2-20)
ψ M = QM (Vgs − VgsM )
(2-21)
∆M Ipk = M Ipkb − 1
(2-22)
where Pn are the coefficients of the ψ polynomial, M Ipk is the I pk -multiplier for the
hyperbolic tangent operator, ψ M controls the shape of M Ipk as a function of Vgs centered
around V gsM , QM is the coefficient for ψ M , and M Ipkb defines the upper bound for M Ipk .
In contrast with the SiC MESFET device model presented in Chapter 2.2.3.4 [72], the
formulation of (2-18)-(2-22) for GaN HEMTs accurately represents its highly asymmetric
84
bell-shaped g m . A model of increased complexity over the SiC MESFET is required for
high power GaN HEMT devices which exhibit a distinct g m peaking behavior. The
measured and modeled g m -vs- Vgs at high Vds obtained from PGIV measurements is
depicted in Fig. 2-29a.
The original Angelov model [88] which was not initially
developed to model g m asymmetry is also shown in Fig. 2-29a for comparison. The
corresponding I ds -vs- Vgs is shown in Fig. 2-29b. Two modifications to the original
Angelov model have been developed and
implemented to permit accurate
characterization of the g m shape for this class of device. The first modification assigns a
unique V pkn to each polynomial term of ψ in (2-19). This creates the skewing of the bell
shaped g m [74][96]. The second modification introduces a multiplier term M Ipk in
(2-18) which allows the elongation of the g m bell-shape for Vgs > V pk [74].
85
1.2
gm (A/V)
1.0
Vgsq=-3.0V, Vdsq=50V
This work
gmpk
0.8
0.6
0.4
0.2
0.0
-3.0
Angelov '92
Vpk
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
Vgs (V)
(a)
3.0
Vgsq=-3.0V, Vdsq=50V
2.5
This work
Ids (A)
2.0
1.5
2Ipk
1.0
0.5
Ipk
0.0
-3.0
Angelov '92
Vpk
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
Vgs (V)
(b)
Fig. 2-29
Comparison of I ds -vs- Vgs measured (triangles), modeled formulas (solid
lines) and those from [88] (X’s) of (a) g m -vs- Vgs and (b) I ds -vs- Vgs at
Vgsq =-3.0V, Vdsq =50V illustrating asymmetry. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_gm_vgsq030_opt.dds)
86
In early implementations of the Angelov model, M Ipk =1 and the maximum drain
current is equal to 2 I pk [88]. However, examination of the measured I ds behavior as a
function of Vgs reveals that I ds increases to values well beyond the 2 I pk limit as shown
in Fig. 2-29b. The inclusion of M Ipk permits the drain current to increase beyond 2 I pk
as a function of Vgs and results in significantly improved accuracy at high Vgs . The
M Ipk -vs- Vgs characteristic is shown in Fig. 2-30. For Vgs < V pk , M Ipk remains close to
unity.
However, for Vgs > V pk , M Ipk increases and, in turn, elongates the I ds
characteristic. Consequentially, an accurate portrayal of the slow decline of g m from its
peak value as shown in Fig. 2-29a is achieved. The parameter M Ipkb serves as the upper
bound of the hyperbolic tangent-based M Ipk characteristic with respect to Vgs .
Care must be taken when implementing M Ipk since its use may present a condition in
which the I ds formula of (2-18)-(2-22) as computes values below zero when Vgs is near
pinchoff. This hazard can be avoided by making the lower tail of M Ipk converge to the
value 1 at or above the device pinchoff. (Unfortunately, this issue was not investigated
until the model completion and therefore negative I ds appears for a small range of Vgs
below pinchoff).
87
3.0
3.0
Vgsq=-3.0V, Vdsq=50V
MIpkb
2.5
2.5
2.0
1.5
1.5
2Ipk
1.0
1.0
Ipk
0.5
0.0
-3.0
Ids (A)
MIpk
2.0
0.5
Vpk
-2.5
-2.0
-1.5
0.0
-1.0
-0.5
0.0
0.5
1.0
Vgs (V)
Fig. 2-30
Multiplication factor M Ipk (triangles) and I ds (measured=circles,
modeled=solid lines) versus Vgs at Vgsq =-3.0V, Vdsq =50V. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_gm_vgsq030_opt.dds)
In addition to its appearance in the tanh operation in (2-18), Vds -dependencies exist
in Pn , M Ipkb and QM as shown below:
Pn = ( Pn 0 + Pn1Vds ) tanh(α PnVds ) + Pno ,
2
n = 1,2,3
3
(2-23)
M Ipkb = ( PM 0 + PM 1Vds + PM 2Vds + PM 3Vds ) tanh(α M Vds ) + PMo
(2-24)
QM = ( PQ 0 + PQ1Vds ) tanh(α QVds ) + PQo
(2-25)
where Pn0 , Pn1 , α Pn and Pno describe the Vds relationships for Pn ; PM 0 , PM 1 , PM 2 , PM 3 ,
α M and PMo describe the Vds relationship for M Ipkb ; and PQ 0 , PQ1 , α Q and PQo describe
the Vds relationship for QM .
The drain-source voltage relationships for parameters Pn , M Ipkb and QM shown in
(2-23), (2-24) and (2-25), respectively, permit modeling of I ds and g m across Vds .
88
Those Vds relationships share a similar form and are necessary in modeling the subtle
complexities of the knee region as illustrated in the next section.
Parameter identification
In order to acquire adequate data for model development, multiple PGIV datasets are
obtain under various Vgsq biases. Pulse durations of 100ns are used since these are short
enough to prevent the onset of dynamic self-heating and charge-trapping effects [93]. In
describing the extraction process for the GaN HEMT I ds formula, the PGIV dataset at
Vgsq =-4.0V where the device is biased below pinchoff is considered. This bias is used
initially to prove the validity of (2-18)-(2-22) and guarantees no influence from dissipated
power since Vgsq =-4.0V is far below the turn-on of the device, even at high Vds voltages.
However, the I ds formulation is later employed to Vgsq =-3.0 V (Chapter 2.2.3.6.3), which
serves as the pinchoff reference point for modeling the complete I ds characteristic [74].
The GaN HEMT I ds extraction algorithm is shown in Fig. 2-31 and follows a similar
process as that used for the SiC MESFET. However, this extraction procedure is a bit
more elegant than for the SiC as efforts to limit the number of parameters under a more
complex model are attempted.
Another difference is that a g m pre-analysis is not
performed. Instead, g m is analyzed when considering the I ds -vs- Vgs curves at each Vds .
89
Measure Pulsed Gate IV Curves
Vgs
Vds
Divide IV into Ids-vs-Vgs at each available Vds
Ids-vs-Vgs
at Vds #1
Ids-vs-Vgs
at Vds #2
Ids-vs-Vgs
at Vds #3
Ids-vs-Vgs
at Vds #N
Curve fit Ids-vs-Vgs
Vds #1
Curve fit Ids-vs-Vgs
Vds #2
Curve fit Ids-vs-Vgs
Vds #3
Curve fit Ids-Vgs
Vds #N
Vgs
Vgs
Vgs
Vgs
Parameter set #1
Parameter set #2
Parameter set #3
Parameter set #N
Collect Pn parameters and sort vs Vds
Determine and Divide Vds-dependent and Vds-independent parameters
(Dynamic loop illustrating re-extraction of Vds-dependent parameters not shown)
P1-vs-Vds
P2-vs-Vds
P3-vs-Vds
MIpkb-vs-Vds
QM-vs-Vds
Fit P1-vs-Vds
Fit P2-vs-Vds
Fit P3-vs-Vds
Fit MIpkb-vs-Vds
Fit QM-vs-Vds
P10 P11 αP1 P1o
P20 P21 αP2 P2o
P30 P31 αP3 P3o
PM0 PM1 PM2 PM3 αM PMo
PQ0 PQ1 αQ PQo
Ipk Vpk1 Vpk2 Vpk3 VgsM
Collect Parameters
Simulate PGIV
curves from Model
Vgs
Vgs
Vds
Vds
Parameter Optimizer
P10 P11 αP1 P1o P20 P21 αP2 P2o P30 P31 αP3 P3o
PQ0 PQ1 αQ PQo PM0 PM1 PM2 PM3 αM PMo
Final Parameter Set
Fig. 2-31
Algorithm for modeling I ds (V gs , Vds ) . (GaN)
90
First, the PGIV dataset is divided according to Vds into I ds -vs- Vgs curves which are
individually curve fit to the formulas in (2-18)-(2-22).
Curve fitting consists of
computing and analyzing the g m -vs- Vgs curves; four of which are shown in Fig. 2-32 at
different Vds . Observation of the g m -vs- Vgs curves reveals the need to modify the I ds
formula to accommodate the asymmetric bell-shaped g m behavior. The mathematical
modifications previously described (introduction of M Ipk and V pkn ) are implemented and
must be expansive enough such that a solution set of parameters exists for I ds -vs- Vgs at
all Vds biases.
91
GaN HEMT: PGIV Vgsq=-4.0V, Vgs=[-3:0.1:1]V
1.5
Vdsq=4V
1.0
gm (A/V)
gm (A/V)
1.5
0.5
0.0
Vdsq=12V
1.0
0.5
0.0
-3
-2
-1
0
1
-3
-2
1.5 Vdsq=24V
1.5
1.0
1.0
0.5
0.0
1
0
1
Vdsq=48V
0.5
0.0
-3
-2
-1
0
1
Vgs (V)
Fig. 2-32
0
Vgs (V)
gm (A/V)
gm (A/V)
Vgs (V)
-1
-3
-2
-1
Vgs (V)
PGIV-computed g m -vs- Vgs at four Vds values illustrating asymmetric
peaking behavior at all Vds . (GaN)
(DISS_DC_equation_IV_PGIV_vgsq40_vdsNN_MTT.dds)
The fitted I ds -vs- Vgs curves produce a working set of parameters, I pk , P1 , P2 , P3 ,
V pk1 , V pk 2 , V pk 3 , M Ipkb , QM and V gsM at each available Vds . The I ds curve fit for four
Vds biases is shown in Fig. 2-33. Each parameter is then collected and plotted to identify
those which are highly sensitive to Vds . The parameters I pk , V pk1 , V pk 2 , V pk 3 and V gsM
do not vary with Vds and their values are set to constant values shared between all the
I ds -vs- Vgs curves.
The curve-fitting process for each I ds -vs- Vgs characteristic is
92
repeated to extract updated values for the remaining Vds -dependent parameters, P1 , P2 ,
P3 , M Ipkb and QM which are then modeled using the functions described in (2-23)-(2-25)
as shown in Fig. 2-34. This process serves as a parameter reduction and extraction stage
and can be performed iteratively as necessary.
GaN HEMT: PGIV Vgsq=-4.0V, Vgs=[-3:0.1:1]V
3.0
Vdsq=4V
2.5
2.5
2.0
2.0
1.5
1.5
Ids (A)
Ids (A)
3.0
1.0
1.0
0.5
0.5
0.0
0.0
-0.5
Vdsq=12V
-0.5
-3
-2
-1
0
1
-3
-2
Vgs (V)
3.0
Vdsq=24V
2.5
2.5
2.0
2.0
1.5
1.5
1.0
1
0
1
Vdsq=48V
1.0
0.5
0.5
0.0
0.0
-0.5
-0.5
-3
-2
-1
Vgs (V)
Fig. 2-33
0
Vgs (V)
Ids (A)
Ids (A)
3.0
-1
0
1
-3
-2
-1
Vgs (V)
Independently modeled I ds -vs- Vgs curves at four Vds biases. (GaN)
(DISS_DC_equation_IV_PGIV_vgsq40_vdsNN_MTT.dds)
Finally all of the individual parameters are collected and optimized to ensure a close
match between the entire measured and simulated PGIV dataset.
For the PGIV at
Vgsq =-4.0V, the I ds , g m and g ds are shown in Fig. 2-35 from which the fidelity of the
93
model can be confirmed. Additionally, a zoomed view of I ds at low current levels is
provided.
In the case of the SiC drain current, many PGIV datasets are taken and evaluated
using (2-14)-(2-16). However, in the case of the GaN HEMT, only two PGIV dataset
with a quiescent bias below pinchoff is modeled using (2-18)-(2-25) in an effort to
consolidate the number of necessary modeling steps.
As stated earlier, the PGIV at Vgsq =-3.0V eventually supplants the PGIV at
Vgsq =-4.0V and serve as the foundation of the model since it is closer to the onset of
pinchoff. The application of PGIV at Vgsq =-3.0V is shown in Chapter 2.2.3.6.3. The
only other GaN HEMT PGIV dataset used to characterize the drain current is taken at
Vgsq =-2.0V and is placed through a portion of the steps outlined in the algorithm of Fig.
2-31. This modified procedure entailing PGIV at Vgsq =-3.0V and Vgsq =-2.0V is further
explained in the self-heating explanation of Chapter 2.2.3.6.3.
94
GaN HEMT: Vds=[6:2:58]V
500
4.0
3.8
MIpkb
P1 (1E-3)
450
400
350
3.6
3.4
3.2
300
3.0
0
10
20
30
40
50
60
0
10
20
40
50
60
40
50
60
Vds (V)
400
850
350
800
QM (1E-3)
P2 (1E-3)
Vds (V)
30
300
250
750
700
200
650
0
10
20
30
40
50
60
Vds (V)
0
10
20
30
Vds (V)
160
P3 (1E-3)
150
140
130
120
110
100
0
10
20
30
40
50
60
Vds (V)
Fig. 2-34
Extracted and modeled, P1 , P2 , P3 , M Ipkb and QM versus Vds . (GaN)
(DISS_DC_equation_IV_PGIV_vgsq40_vdssweep_parameters_MTT.dsn)
95
GaN HEMT: Vgsq=-4.0V, Vgs=[-2.9:0.2:0.7]V, Vds=[0:2:58]V
(a)
(b)
2.5
0.50
0.45
2.0
0.40
0.35
1.5
Ids (A)
Ids (A)
0.30
1.0
0.25
0.20
0.15
0.5
0.10
0.05
0.0
0.00
0
10
20
30
40
50
60
0
10
20
30
Vds (V)
40
50
60
Vds (V)
(c)
(d)
1.2
0.25
1.0
0.20
0.8
gds (A/V)
gm (A/V)
0.15
0.6
0.4
0.10
0.05
0.2
0.00
0.0
-0.2
-0.05
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
0
5
10
15
20
25
Vds (V)
Pn0
30
35
40
45
Pn1
al phaPn
Pno
2.618E-1
4.541E-17
1.449E-1
-2.576E-14
n=2
-9.809E-1
-1.987E-3
2.423E-1
1.080E0
-1.750E0
n=3
-5.470E-2
-2.534E-4
5.246E-2
1.997E-1
-1.502E-1
alphaM
PMo
3.979E0
PQ0
-1.591E0
VgsM
-7.037E-1
55
60
Vpkn
n=1
PM0
50
Vds (V)
PM1
PM2
1.278E-2
PM3
0.000E0
PQ1
0.000E0
alphaQ
-4.699E-4
Ipk
1.050E0
2.607E-1
-3.810E0
-7.082E-1
PQo
2.577E0
alpha
5.705E-1
1.000E0
DISS_DC_equation_IV_PGIV_vgsq40_full_MTT
Fig. 2-35
Post-optimization equation-only I ds modeling results for PGIV dataset at
Vgsq =-4.0V showing I ds , g m and g ds . (GaN)
(DISS_DC_equation_IV_PGIV_vgsq40_full_MTT.dds)
96
2.2.3.6.
Self-heating
Self-heating is the effect of a device’s temperature increasing due to its own electrical
power dissipation.
Electrical power dissipation in the device leads to increases in
temperature which can substantially affect the I ds performance of the device.
The self-heating effect on I ds is illustrated in Fig. 2-36 which shows the transient
stepped behavior of a generic high power device biased at a nonzero Vdsq . At t 0 , the
device has been in steady-state for a long time, the gate voltage Vgs = V gs ,a and the
temperature T = Ta , the ambient temperature. This quiescent operating point gives rise to
a drain current I ds (V gs ,a , Ta ) . At t1 , the gate voltage is stepped to V gs ,b and I ds rises in
response to the increased Vgs . However, because the packaged semiconductor device
takes time to warm up, T initially remains close to Ta resulting in a current peak of
I ds (V gs ,b , Ta ) . Between time t1 and t 2 , the temperature rises and saturates exponentially
to Tb . Simultaneously, I ds decays from its peak and saturates to I ds (V gs ,b , Tb ) . At time
t 3 , the V gs is stepped back down to V gs ,a . However, because the device also takes time to
cool, it initially remains near Tb and the drain current dips to I ds (V gs ,a , Tb ) , which is
lower than the original value, I ds (V gs ,a , Ta ) . Once the excess heat is evacuated and the
temperature returns to Ta , the drain current rises to I ds (V gs ,a , Ta ) by time t 4 .
97
∆T = Rth Pdiss
Fig. 2-36
Transient of thermal self-heating effect on drain current.
Since device temperature due to self-heating follows an exponential charging and
discharging behavior, it is possible to model it using an analogous self-heating thermal
subcircuit. As a function of both bias and temperature, I ds follows a similar exponential
trend.
However, the behavior of I ds is not directly proportional to changes in
temperature.
Additionally, the charging and discharging behavior is not necessarily
symmetric as portrayed in Fig. 2-36.
The self-heating effect on I ds is a feedback mechanism. Temperature increases
caused by self-heating alter I ds while the I ds creates power dissipation, thereby
increasing temperature. Therefore, self-heating must be characterized using controlled
98
drain current excitations and then independently evaluated and modeled before reimplementing it back into the complete I ds model.
∆T’
T
Fig. 2-37
Cth,1
Cth,2
Cth,K
Rth,1
Rth,2
Rth,K
PD
T0
Self-heating thermal subcircuit utilizing multiple time constants.
The self-heating thermal subcircuit utilizing multiple time constants shown in Fig.
2-37 serves as an electrical analog in modeling the thermal charging and discharging
behavior of the device. The computation of thermal behavior using an electrical model
improves compatibility with circuit simulator software. The thermal model presented
here is a generalization of the single time-constant models presented in [49][72][74][91].
This multiple time constant model is highly accurate in computing the transient
temperature behavior as a function of dissipated power as described by the expressions
(See Appendix A.2 for analysis):
K


T = T0 + ∆T ' = T0 + ∆T 1 − ∑ Rˆ th , k e −t / τ k 
 k =i

(2-26)
∆T = PD Rth = ( I ds ⋅ Vds ) Rth
(2-27)
K
Rth = ∑ Rth, k
k =i
(2-28)
99
Rth ,k
Rˆ th , k =
Rth
(2-29)
τ k = Rth, k C th, k
(2-30)
In the thermal model equations above, T is the temperature, T0 is the ambient
temperature, ∆T ' is the time-varying temperature change, ∆T is the static temperature
change, PD is the instantaneous dissipated power and Rth is the total thermal resistance.
The thermal time constants τ k are determined by the product of the partitioned thermal
resistances and capacitances, Rth , k and C th ,k , respectively, and K is the total number of
time constants.
The normalized Rˆth ,k is the ratio of Rth ,k to Rth,eq and is used to
implement the multi-time constants model.
It is important to note that this model
assumes a symmetric charging and discharging thermal behavior for simplicity.
For a first order self-heating thermal subcircuit, the model reduces to a familiar form
used in numerous previous works [91] shown in Fig. 2-38.
Fig. 2-38
Self-heating thermal subcircuit utilizing single time constants.
2.2.3.6.1. Self-Heating Thermal Resistance
Characterization of the thermal resistance is important in understanding the effect of
dissipated power on device temperature and ultimately device performance. There exist a
100
number of approaches for extracting the nonlinear thermal resistance, Rth , which relates
the junction temperature to the dissipated power [97][98][99][100][101][102]. In the
approach used here, Rth is extracted from DC forward bias Dgs current measurements,
which are performed over a range of static Vds in a manner similar to [47][97]. The
technique provides values for Rth characterized over various dissipated powers and uses
simple DC measurements that require no special equipment.
The IV characteristic of Dgs is temperature sensitive due its dependency on the
thermal voltage. Changes in gate-current characteristics under different static power
states are indicative of self-heating and can be used to gauge temperature changes in the
FET device.
Fig. 2-39
(a) Setup for the Rth characterization (b) forward-bias gate diode
characteristics at different PD (and different temperature).
When the device is placed under a controlled DC bias (as shown in Fig. 2-39a), it
undergoes self-heating as a direct function of PD . Self-heating affects the I gs -vs- V gs
101
characteristic of the device through the associated thermal voltage parameter (nVT )
which is obtained by computing the slope of ln( I gs ) -vs- V gs as shown in Fig. 2-39b.
slope =
∂ ln( I gs )
∂V gs
=
1
nVT
(2-31)
A temperature increase due to dissipated power causes the slope of the ln( I gs ) -vs- V gs
characteristic to decrease, representing an increased thermal voltage.
To characterize Rth , the baseline thermal voltage under a zero DC power state of
PD 0 , which infers an ambient device temperature ( T0 = 300 K ), is extracted. From this
baseline thermal voltage, n is computed by
(nVT 0 ) = nkT0
q
⇒n=
q
(nVT 0 )
kT0
(2-32)
Then, the device is placed under non-zero DC power states of PDi in which selfheating will cause increases in device temperature. For these cases, the associated (nVTi )
is extracted and Ti is computed using n from (2-32).
Ti =
q
(nVTi )
nk
(2-33)
from which Rth is computed by
Rth =
∆T Ti − T0
=
PDi
PDi
(2-34)
The algorithm for the Rth extraction process over different dissipated power levels is
shown in Fig. 2-40. When applying this technique, care is taken to make sure that the
incoming gate current flows completely out of the source, otherwise the measurement
will be invalid. For the zero power baseline case, this is assured by measuring I gs -vs- Vgs
102
with the drain open. If I gs -vs- Vgs were measured with the drain shorted, the gate current
would flow through both the grounded source and the grounded drain.
Extract (nVT)1
Extract (nVT)K
PD1
PDK
Extract (nVT)0
PD0=0
(nVT)K
Set VdsK, measure
Igs-vs-Vgs and IdsK
(PDK=VdsKIdsK)
(nVT)1
Set Vds1, measure
Igs-vs-Vgs and Ids1
(PD1=Vds1Ids1)
(nVT)0
Set drain open,
measure Igs-vs-Vgs
compute n
Compute T1, ∆T1
Rth1=∆T1/PD1
Compute TK, ∆TK
RthK=∆TK/PDK
RthK
n
Rth1
n
Generate Rth-vs-PD from
model
Computed
Rth vs RD
R0 R1 R2 δ1 δ2
Initial parameter set
Extracted
Rth vs PD
Collect
Rth ( PD ) = R2 exp(− PD / δ 2 ) +
R1 exp( − PD / δ1 ) +
R0
Parameter Optimizer
R0 R1 R2 δ1 δ2
Final parameter set
Fig. 2-40
Rth extraction algorithm using forward-conduction DC measurements.
First, the baseline I gs -vs- Vgs is acquired to compute n .
Next, I gs -vs- Vgs
measurements are taken at various PD . Since PD cannot be explicitly set, Vds is used as
103
an indirect self-heating control parameter. Under measurement of I gs -vs- Vgs , Vds is set
to a constant value greater than Vgs , which reverse biases D gd and forces all of the
incoming gate current to flow out of the source. At the same time, since Vgs is biased to
positive values, the channel will completely open up, allowing I ds to rise to its
unimpeded maximum DC value. This I ds and Vds product determines the corresponding
PDi , from which the temperature Ti is computed. The Rth extraction process is repeated
for as many Vds (and resulting PD ) values as desired.
SiC MESFET
The Rth extraction applied to the SiC MESFET is illustrated next. The individual
ln( I gs ) -vs- V gs curves at different Vds values are plotted in Fig. 2-41. The portion of each
ln( I gs ) curve which most closely resembles a straight line with constant slope is
highlighted in red and is used to compute Rth .
104
ln(Igs) vs Vgs at Vds=[0.1:0.1:16.1]V
-4
Data
nVT extract region
-5
Increasing Vds and PD
-6
-7
ln(Igs)
-8
-9
-10 Measurement
Floor
-11
-12
-13
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Vgs
Fig. 2-41
Measured ln( I gs ) -vs- V gs curves for Rth extraction. (SiC)
(DISS_thermal\thermal_resistance_extraction\DISS_thermal_model_rth_xtr3633.m, f2)
The I ds , PD , ∆T and Rth for each ln( I gs ) -vs- V gs curve are plotted against Vds in
Fig. 2-42 and against PD in Fig. 2-43.
105
Ids vs Vds
PD vs Vds
2
30
20
PD
Ids
1.5
1
10
0.5
0
0
5
10
Vds
deltaT vs Vds
0
15
10
Vds
Rth vs Vds
15
0
5
10
Vds
15
200
50
100
0
Fig. 2-42
5
100
Rth
deltaT
300
0
0
5
10
Vds
0
15
Measured I ds , PD , ∆T and Rth versus Vds . (SiC)
(DISS_thermal_model_rth_xtr3633.m)
Ids vs PD
PD vs PD
2
30
20
PD
Ids
1.5
1
10
0.5
0
0
10
20
0
30
0
10
0
10
PD
deltaT vs PD
200
50
100
0
0
10
20
PD
Fig. 2-43
30
100
Rth
deltaT
300
20
PD
Rth vs PD
30
0
20
30
PD
Measured I ds , PD , ∆T and Rth versus PD . (SiC)
(DISS_thermal\thermal_resistance_extraction\DISS_thermal_model_rth_xtr3633.m)
106
Ideally, Rth is constant. However, as shown in Fig. 2-44a, the Rth for the SiC
MESFET is high at low PD but decreases and saturates with increasing PD . This
behavior coincides with the saturation of the junction temperature at around 570K (Fig.
2-44b). An analytical expression is developed to model the nonlinear Rth characteristic
as a function of PD :
Rth ( PD ) = R2 e − PD / δ 2 + R1e − PD / δ1 + R0
(2-35)
where R0 , R1 and R2 are the fitting coefficients, and δ1 and δ 2 are the decay constants
of the first and second exponentials, respectively. The modeled Rth curve provides a
sufficient match to the measured characteristic shown in Fig. 2-44a and the model
parameters are provided in Table 2-4.
107
(a) Measured and modeled Rth vs PD
Rth (C/W)
100
50
0
0
5
10
15
PD (W)
20
25
30
550
600
(b) Measured and modeled Rth vs T
Rth (C/W)
100
50
0
300
Fig. 2-44
350
400
450
T (K)
500
Extracted and modeled thermal resistance Rth model (a) versus PD and (b)
versus T . (SiC)
(DISS_thermal_model_rth_xtr3633.m)
(DISS_IV_equation_xtr3633_IV_thermal_Rth_opt.dsn for optimization)
Table 2-4
Parameter
R2
δ2
R1
δ1
R0
Rth -vs- PD model parameters (SiC)
Value
41.0187
10.9999
60.1912
2.18674
6.60522
The thermal resistance can alternatively be modeled as a function of T which results
in a simple linear model.
Rth (T ) = R X 1T + R X 0
(2-36)
108
where R X 1 , R X 0 are the fitting parameters. The linearly modeled Rth curve is shown in
Fig. 2-44b and the tabulated model parameters are provided in Table 2-5.
Table 2-5
Parameter
RX 1
RX 0
Rth -vs- T model parameters (SiC)
Value
-3.711124E-1
2.231175E2
GaN HEMT
Determination of the thermal resistance over dissipated power allows for accurate
computation of the device temperature. However, a nonlinear thermal resistance may
unnecessarily complicate the overall model since the primary interest is in the effect of
PD on I ds alone.
Investigation of GaN HEMT thermal effects reveals that a constant Rth model
provides sufficient information to develop a relationship between the thermal state of the
device and I ds . The constant Rth,eq value of 5.0 C/W obtained from the device datasheet
is used in the model [79].
2.2.3.6.2. Self-heating Effect on SiC MESFET Drain Current
The controlled characterization using PGIV at different Vgsq reveals the heavy
influence of self-heating on I ds .
Mainly, static power dissipation and increased
temperatures cause I ds and g m to decrease. A relationship which properly relates PGIV
behavior with temperature is necessary to replicate the self-heating effects on I ds .
109
A unique set of I ds parameters for each SiC MESFET PGIV dataset was produced in
Chapter 2.2.3.4. Comparing the I ds parameters extracted in the presence of self-heating
with those void of self-heating reveals those which vary the most with temperature.
These thermally-sensitive parameters consist of I pk , P1 , P3 , P4 since PGIV datasets at
Vgsq above pinchoff are synonymous with nonzero PD .
Thermal modification of I pk
In particular, the parameter which is most sensitive to quiescent bias and self-heating
is I pk which serves as the “backbone” of the I ds formula. The I pk -vs- Vgsq curves for a
range of Vgsq biases are shown in Fig. 2-45, illustrating the degree of variation with
different PD .
110
SiC MESFET: Vpk=0.5V, Vgsq=[-11:0.5:-3]V,Vdsq=[0:2:58]V
2
Ipk (A)
1.5
1
0.5
0
Fig. 2-45
0
10
20
30
Vds (V)
40
50
60
Extracted and modeled I pk -vs- Vdsq for various Vgsq . (SiC)
(DISS_thermal\DISS_thermal_IV_relation_Ipk.m f40)
Self-heating effects can be integrated primarily by modifying I pk according to the
change in temperature [91]. A standard thermal dependency is adopted and provides a
thermal-sensitive adaptation of I pk :
I pkth = I pk (∆T ' ) =
I pk ,T0
1 + K Ipk ∆T '
(2-37)
where I pk ,T0 is I pk at room temperature T0 , ∆T ' is the time-dependent temperature
change computed by the self-heating subcircuit, and K Ipk is the nonlinear thermal fitting
parameter.
The equation of (2-37) is mathematically equivalent to the relationship
111
presented in [91], but is written in this form to emphasize that I pk will generally decrease
as temperature increases.
The K Ipk parameter satisfies the thermal relationship of (2-37) for all biases and is
modeled using the algorithm shown in Fig. 2-46.
112
Ipk-vs-Vdsq extracted
from PGIV at Vgsq0
(pinchoff)
Set as Ipk,T0-vs-Vdsq
(zero self heating)
I pk,T0-vs-Vdsq
Ipk-vs-Vdsq extracted
from PGIV at Vgsq1
Ipk-vs-Vdsq extracted
from PGIV at VgsqN
Set as Ipk,Vgsq1-vs-Vdsq
Set as Ipk,VgsqN-vs-Vdsq
Ipk,Vgsq1-vs-Vdsq
Ipk,VgsqN-vs-Vdsq
Vgsq1
VgsqN
Obtain
∆TVgsq1-vs-Vdsq
from ∆T table
(Fig. 2-47)
Obtain
∆TVgsqN-vs-Vdsq
from ∆T table
(Fig. 2-47)
∆TVgsq1-vs-Vdsq
∆TVgsqN-vs-Vdsq
Compute KIpk,Vgsq1-vs-Vdsq
K Ipk ,Vgsq1 =

1  I pk ,T0
− 1

∆TVgsq1  I pk ,Vgsq1

Compute KIpk,VgsqN-vs-Vdsq
K Ipk ,VgsqN =
KIpk,Vgsq1 vs Vdsq
 I pk ,T0


− 1
I

 pk ,VgsqN

KIpk,VgsqN vs Vdsq
Linear fit KIpk-vs-Vdsq
Linear fit KIpk-vs-Vdsq
K Ipk ,Vgsq1 = K Ipk1,Vgsq1Vdsq + K Ipk 0,Vgsq1
K Ipk ,VgsqN = K Ipk1,VgsqNVdsq + K Ipk 0,VgsqN
KIpk1,Vgsq1
KIpk1,VgsqN
KIpk0,Vgsq1
Collect KIpk1-vs-Vgsq
Curve fit KIpk1-vs-Vgsq
K Ipk1 = K Ipk1max (1 + tanh(ψ Ipk1 ) )
ψ Ipk1 = C13 (Vgsq − Vgsq ,Ipk1 ) 3 +
KIpk0,VgsqN
Collect KIpk0-vs-Vgsq
KIpk1-vs-Vgsq
KIpk0-vs-Vgsq
Curve fit KIpk0-vs-Vgsq
K Ipk 0 = K Ipk 0 max (1 − tanh(ψ Ipk 01 ) )
ψ Ipk 0 = C03 (Vgsq − Vgsq ,Ipk 0 )3 +
C11 (Vgsq − Vgsq ,Ipk1 )
KIpk1max C13 C11 Vgsq,Ipk1
Fig. 2-46
1
∆TVgsqN
C01 (Vgsq − Vgsq,Ipk 0 )
KIpk0max C03 C01 Vgsq,Ipk0
Modeling algorithm for thermal-varying I pkth . (SiC)
Since it has been established that the PGIV at Vgsq =-11.0V provides a room
temperature case, the I pk -vs- Vdsq from that dataset is chosen to serve as I pk ,T0 , the
baseline for the I pkth model. Next, the I pk -vs- Vdsq curves from PGIV at other Vgsq are
113
used to compute K Ipk , the bias-dependent I ds -to-self-heating relational term. Under
steady state thermal conditions, ∆T ' = ∆T , and K Ipk can be solved using:
K Ipk =
1
∆T
 I pk ,T0


− 1
 I pkth



(2-38)
The required ∆T is pre-computed using Rth and the I dsq -vs- Vdsq curve from each
PGIV dataset as illustrated in Fig. 2-47. This provides each I pk -vs- Vdsq curve with an
associated PD -vs- Vds and ∆T -vs- Vds curve. These curves are assembled into a matrix
and also used for the thermal relationships of the Pn parameters.
114
PGIV at Vgsq0
(pinchoff)
PGIV at Vgsq1
PGIV at VgsqN
Extract Idsq-vs-Vdsq
Extract Idsq-vs-Vdsq
Extract Idsq-vs-Vdsq
Idsq,Vgsq0-vs-Vdsq
Idsq,Vgsq0-vs-Vdsq
Idsq,VgsqN-vs-Vdsq
Compute
PD=IdsqVdsq
Compute
PD=IdsqVdsq
Compute
PD=IdsqVdsq
PD,Vgsq0-vs-Vdsq
PD,Vgsq1-vs-Vdsq
PD,VgsqN-vs-Vdsq
Collect into PD matrix
Vgsq1
VgsqN
Vdsq1
PD,11
PD,1N
VdsqM
PD,M1
PD,MN
Vgsq1
VgsqN
Vdsq1
Rth11
Rth1N
VdsqM
RthM1
RthMN
Vgsq1
VgsqN
Vdsq1
∆T11
∆T1N
VdsqM
∆TM1
∆TMN
PD-vs-Vgsq-vs-Vdsq
Compute Rth matrix using
Rth-vs-PD model
Rth-vs-Vgsq-vs-Vdsq
Compute ∆T matrix
∆T=PDRth (element-by-element)
∆T-vs-Vgsq-vs-Vdsq
Create ∆T table
∆T table
Fig. 2-47
Algorithm for computing the ∆T matrix.
The K Ipk -vs- Vdsq behavior computed from PGIV at Vgsq =[-8.5:0.5:-3.0]V are shown
in Fig. 2-48, illustrating the bias-dependency of the thermal relationship.
115
-3
2.5
x 10
SiC MESFET: Vgsq=[-8.5:0.5:-3.0]V, Vds=[0:2:58]V
0
10
2
1.5
KIpk
1
0.5
0
-0.5
-1
Fig. 2-48
20
30
Vds
40
50
60
Computed and linear fit K Ipk -vs- Vdsq for each Vgsq =[-8.5:0.5:-3.0]V
(measured=symbols, modeled=solid lines). (SiC)
(DISS_thermal\DISS_thermal_IV_relation_Ipk.m f3)
A linear fit is performed on the K Ipk -vs- Vdsq curves at each Vgsq using
K Ipk = K Ipk1Vdsq + K Ipk 0
(2-39)
which produces coefficients K Ipk1 and K Ipk 0 for each Vgsq . The individual linear fits are
also shown in Fig. 2-48. The coefficients K Ipk1 and K Ipk 0 are then plotted across Vgsq in
Fig. 2-49.
116
-5
x 10
6
-4
SiC MESFET: Vgsq=[-11:0.2:3]V
4
5
SiC MESFET: Vgsq=[-11:0.2:3]V
2
4
0
3
KIpk0
KIpk1
x 10
2
-2
-4
1
-6
0
-1
-12
-10
-8
-6
-4
-2
-8
-12
-10
-8
Vgsq
Fig. 2-49
-6
-4
-2
Vgsq
Extracted and modeled K Ipk1 and K Ipk 0 coefficients versus Vgsq . (SiC)
(DISS_thermal_IV_relation_Ipk.m)
The K Ipk1 -vs- Vgsq and K Ipk 0 -vs- Vgsq characteristics are modeled using a tanh-based
model:
K Ipkj = K Ipkj max (1 − (−1) j tanh(ψ Ipkj ) )
(2-40)
j = 0,1
ψ Ipkj = C j1 (Vgsq − Vgsq, Ipkj ) + C j 3 (Vgsq − Vgsq , Ipkj )3
j = 0,1
(2-41)
where K Ipkj max , C j1 , C j 3 , and Vgsq , Ipkj are fitting parameters. The parameters which
successfully model the responses are shown in Table 2-6.
Table 2-6
K Ipk model parameters (SiC)
Parameter
K Ipkj max
j=0
-0.00036672
j=1
4.49739e-005
C j1
-0.333298
0.196581
C j3
-0.0502088
0.00195504
Vgsq , Ipkj
-6.3829
-3.62762
117
The complete, thermal-sensitive I pkth model is shown in Fig. 2-45 and demonstrates
an excellent agreement with the extracted I pk data.
Analytical Modeling of I pk ,T 0
The SiC MESFET I ds formula of (2-14)-(2-16) utilizes a table-based model for
I pk -vs- Vds to supply I pk values. Since the I pk -vs- Vds curve at Vgsq =-11.0V serves as the
foundation of the I ds formula, it is important to model it using an analytical expression
rather than a discrete set of measured points to reduce the effects of measurement error
on the completed model. Using an analytical expression also simplifies the absolute
number of parameters values by forgoing the table-based model.
This analytical
modeling step is also identified in the algorithm of Fig. 2-21.
The I pk ,T0 characteristic ( I pk at Vgsq =-11.0V) is shown in Fig. 2-50 and can be
modeled using the following expression:
(
3
2
)
I pk ,T0 = J 3Vds + J 2Vds + J 1Vds + J 0 tanh(α IpkVds )
(2-42)
where the J 3 , J 2 , J1 , J 0 and α Ipk values are fitting parameters. It is shown in Fig. 2-50,
that this model does a suitable job of representing the I pk ,T0 -vs- Vds characteristic. The
parameters of the model are provided in Table 2-7.
118
Ipk vs Vds, fitted vs extracted at Vpk=0.5V
2
1.8
1.6
1.4
Ipk
1.2
1
0.8
0.6
0.4
0.2
0
Fig. 2-50
0
10
20
30
Vds
40
50
60
I pk ,T0 -vs- Vds extracted from the corresponding V pk =0.5V. Extracted and
modeled values shown. (SiC)
(tanhfit_IV_dec07.m)
(DISS_IV_equation_xtr3633_IV_thermal_Ipk_model_opt.dsn for optimization)
Table 2-7
Analytical model parameters of I pk ,T0 (SiC)
Parameter
J3
Value
9.35141E-7
J2
J1
J0
-2.02796E-4
1.84565E-2
1.42487
α Ipk
0.151000
Thermal modification of Pn
Once I pkth has been characterized, a similar process for analyzing the thermal
dependency is performed for the Pn parameters. The P1 , P3 and P4 parameters extracted
from the PGIV at several Vgsq biases are plotted versus Vds in Fig. 2-51 to investigate
their sensitivity to self-heating.
119
Observation of the Pn -vs- Vds curves shows that despite the large ranges of Vgsq and
Vds , the parameters do not actually vary much from the baseline values at Vgsq =-11.0V.
Therefore the thermal effects are not as pronounced on Pn as they are on I pk .
Parameter Pn is modified using a standard thermal dependency to produce the
thermal adaptation, Pnth [53]:
Pnth = Pn,T0 (1 + K Pn ∆T ' )
for n = 1,3,4
(2-43)
where Pn,T0 is the Pn extracted at room temperature T0 =300K and K Pn is the biasdependent thermal factor, which relates self-heating temperature changes to Pn .
Rather than innovate the extraction of K Pn to produce a reduced-parameter fitting
model as is done for K Ipk , polynomial models are used to model the multibias response
of K Pn under static thermal conditions ( ∆T ' = ∆T ):
2
K Pn = K Pn , 2Vds + K Pn ,1Vds + K Pn , 0 ,
n = 1,3,4
K Pn,u = K Pn ,u 2 (Vgs − Vgsq ,Pn ,u ) 2 + K Pn ,u1 (Vgs − Vgsq ,Pn ,u ), u = 0,1,2
(2-44)
(2-45)
where K Pn ,u 2 , K Pn ,u1 and Vgsq , Pn ,u are fitting parameters for n = 1,3,4 and u = 0,1,2 . The
advantages of this model are a straightforward implementation and parameter
determination using established polynomial fitting and gradient-based optimization. The
parameters are determined under the observation of the Pn -vs- Vdsq error function and
then optimized under transient pulsed simulations to best reproduce the PGIV
characteristics.
The modeled Pnth responses show reasonable accuracy with the extract values as
shown in Fig. 2-51. The optimized parameters values are provided in Table 2-8.
120
0
-50
-100
-150
-200
-250
-300
-350
-400
-450
-500
1.0
0.5
P3th (1E-3)
P4th (1E-6)
SiC MESFET: Pnth vs Vds for Vgsq=[-11:0.5:0.5]V
0.0
-0.5
-1.0
-1.5
0
10
20
30
40
50
60
0
10
20
1.0
200
0.5
150
0.0
50
-1.0
0
10
20
30
40
50
60
0
10
Vds (V)
Fig. 2-51
50
60
40
50
60
100
-0.5
0
40
Vds (V)
P1th (1E-3)
P2th (1E-3)
Vds (V)
30
Thermally-varying Pnth parameters. (SiC)
(DISS_IV_equation_xtr3633_IV_thermal_P1th_opt.dds)
20
30
Vds (V)
121
K Pn , 02
Pnth model parameters (SiC)
n=1
n=3
-4.59924e-007
1.29466e-005
n=4
4.93169e-006
K Pn , 01
-2.17173e-005
4.33906e-006
1.62381e-005
Vgsq ,Pn , 0
-0.140734
-16.5861
-6.61018
K Pn ,12
1.13032e-007
6.98253e-008
2.25654e-007
K Pn ,11
8.85487e-007
1.64487e-006
1.54919e-006
Vgsq ,Pn ,1
-0.508302
-1.57022
-3.68627
K Pn , 22
9.29367e-012
2.70445e-009
1.19254e-013
K Pn , 21
6.7698e-011
5.31589e-010
1.90489e-013
Vgsq ,Pn , 2
-15.8348
-1.22423
-4.94914
Table 2-8
Since parameter reduction for these responses is not investigated in depth, the order
of (2-44)-(2-45) is not optimal. However, trading off higher mathematical complexity for
a straightforward model provides an immediate alternative to table-based models.
Furthermore, the successful integration of self-heating with Pn -vs- Vds reveals that the
determination of Qmn for every set of PGIV as done in Chapter 2.2.3.4 is not necessary.
Once the proper Qmn are obtained for Vgsq =-11.0V, only the Pn -vs- Vds curves at
Vgsq >-11.0 are needed to derive the correct thermal modifiers satisfying (2-43)-(2-45).
Determining Qmn at Vgsq >-11.0V may help to verify the validity of the I ds formula of
(2-14)-(2-16) for dispersive cases, but may be bypassed once the mathematical validity of
the model has been established.
Validation using transient PGIV
The efficacy of the thermal I ds relationships can be verified by comparing PGIV data
and PGIV simulated using transient pulsed excitations. At this point, even a first order
122
self-heating model of Fig. 2-38 is not complete since Cth has not yet been accurately
determined. However, Cth can be set temporarily to an arbitrarily large value to retain a
distinction between quiescent and short-duration pulsed effects.
The PGIV
characteristics of the I ds model with thermal self-heating compared with data for five
Vgsq biases is shown in Fig. 2-52. The accurate reproduction of PGIV under transient
excitation is important since it is the first true test of the model’s ability to distinguish
quiescent from pulsed behavior and validates the application of the I pkth and Pnth thermal
relationships presented in this section. The curves shown in Fig. 2-52 comparing PGIV
data with PGIV simulations are different from those shown in Fig. 2-27 and Fig. 2-28
comparing PGIV data with DC simulations used to demonstrate the mathematical
applicability of (2-14)-(2-16).
123
SiC MESFET: Transient PGIV Vgs=[-11:0.5:0.5]V, Vds=[0:2:58]V
2.2
2.0
Vgsq=-11.0V
1.8
1.6
Ids (A)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
5
10 15 20 25 30 35 40 45 50 55 60
Vds (V)
(a)
2.2
2.2
Vgsq=-9.0V
2.0
1.8
1.8
1.6
1.6
1.4
1.4
Ids (A)
Ids (A)
2.0
1.2
1.0
1.2
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
Vgsq=-7.0V
0.0
0
5 10 15 20 25 30 35 40 45 50 55 60
0
5 10 15 20 25 30 35 40 45 50 55 60
Vds (V)
Vds (V)
(b)
2.2
Vgsq=-5.0V
2.0
1.8
1.8
1.6
1.6
1.4
1.4
Ids (A)
Ids (A)
2.0
(c)
2.2
1.2
1.0
1.2
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0
5 10 15 20 25 30 35 40 45 50 55 60
Vds (V)
(d)
Fig. 2-52
Vgsq=-3.0V
0
5 10 15 20 25 30 35 40 45 50 55 60
Vds (V)
(e)
PGIV characteristics under pulsed transient excitation. Measured (symbols)
and modeled (solid lines). (SiC)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsqXXX_opt.dds)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsq090_opt.dsn)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsq070_opt.dsn)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsq050_opt.dsn)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsq030_opt.dsn)
124
2.2.3.6.3. Self-heating Effect on GaN HEMT Drain Current
As it has already been shown, self-heating affects the I ds performance of the device.
In particular, increased temperature causes reduced carrier mobility, which is detrimental
to both g m and I ds . A definitive relationship between self-heating and the GaN HEMT
I ds is carefully investigated here.
Thermal modeling of the SiC MESFET serves as validation that the presented
algorithms, formulas and techniques can provide an accurate portrayal of the thermallyaffected device. Many of these techniques can be applied to the GaN HEMT. However,
an additional effort to simplify the thermal modeling process is made to compensate for
the added complexity of the basic GaN HEMT I ds behavior of (2-18)-(2-22). These
simplifications include minimizing the number of modeling steps, limiting the amount of
PGIV data required and reducing the number of thermal model parameters without
sacrificing accuracy. Simplification of the thermal model saves time and provides a
streamlined modeling process that can then be applied to any un-characterized device.
In the pursuit of a thermal relationship for the SiC MESFET, PGIV datasets at
different Vgsq were modeled using the associated I ds modeling algorithm of Fig. 2-20.
However, since the thermal modifications of (2-37) and (2-43) are applied to the highlevel I pk and Pn parameters rather than low-level Qmn parameters, the full modeling of
each PGIV dataset is not necessary. The determination of the Qmn parameters is only
necessary for the baseline case of Vgsq =-11.0V. Furthermore, a large number of PGIV
datasets were applied to the thermal characterization of the SiC MESFET but may have
been excessive since many of the PD points between datasets overlap. Finally, the
125
number of thermal parameters for (2-40)-(2-41) and (2-44)-(2-45) shown in Table 2-6
and Table 2-8, respectively, is high.
For the GaN device, only two PGIV datasets are used in the thermal model
identification process: one below pinchoff and free of self-heating at Vgsq =-4.0V and one
under heavy self-heating at Vgsq =-2.0V. The baseline case at Vgsq =-4.0V is modeled
using the complete algorithm of Fig. 2-31. The heavy self-heating PGIV at Vgsq =-2.0V
contains enough information to build the thermal model and is modeled through only a
portion of the algorithm of Fig. 2-31; until the I pk -, P1 -, P2 -, P3 -, M Ipkb - and QM -vs- Vds
curves are obtained. Any other PGIV dataset can be used as verification and refine the
model but is not needed for the initial identification process.
Comparison of the I ds parameter sets respective of the two PGIV datasets reveal five
which are most sensitive to variations in PD and subsequent ∆T .
The thermally-
sensitive parameters are identified as I pk , P1 , P2 , P3 and M Ipkb of (2-18)-(2-22) and
their values from PGIV at Vgsq =-4.0 and Vgsq =-2.0V are shown in Fig. 2-53.
126
GaN HEMT: Ipk, P1, P2, P3, MIpkb computed at Vgsq=[-4:2:-2]V, Vdsq=[0:2:28]V
1.0
800
Vgsq=-2.0V
Vgsq=-2.0V
0.9
600
0.8
P1
Ipk
0.7
Vgsq=-4.0V
0.6
0.5
400
Vgsq=-4.0V
200
0.4
0.3
0
0
10
20
30
40
50
60
0
10
20
Vds (V)
30
40
50
60
40
50
60
Vds (V)
700
300
Vgsq=-2.0V
Vgsq=-2.0V
500
200
P3
250
P2
600
400
150
300
100
Vgsq=-4.0V
Vgsq=-4.0V
200
50
0
10
20
30
40
50
60
0
10
20
Vds (V)
30
Vds (V)
7
Vgsq=-2.0V
6
MIpkb
5
4
Vgsq=-4.0V
3
2
1
0
10
20
30
40
50
60
Vds (V)
Fig. 2-53
I pk -, P1 -, P2 -, P3 - and M Ipkb -vs- Vds for the Vgsq =-4.0V and -2.0V cases.
(GaN)
(DISS_DC_equation_thermal_parameter_model_opt.dds)
127
Thermal modification of drain current parameters
A standard thermal modification is applied to these five parameters [91].
The
thermally-sensitive adaptations are functions of ∆T ' by the following relationships:
I pkth = I pk ,T0 (1 + K Ipk ∆T ' )
(2-46)
Pnth = Pn,T0 (1 + K Pn ∆T ' ), n = 1, 2,3
(2-47)
M Ipkbth = M Ipkb,T0 (1 + K MIpkb∆T ' )
(2-48)
where I pk ,T0 , Pn,T0 and M Ipkb,T0 are the respective parameters at room temperature
(T=300K) and K Ipk , K Pn , and K MIpkb are the respective bias-dependent thermal factors.
The I pk ,T0 , Pn,T0 and M Ipkb,T0 terms are set to the zero self-heating values extracted
under the pinchoff condition (at Vgsq =-4.0V).
The algorithm for determining and
modeling K Ipk is shown in Fig. 2-54 and is similar to the algorithm for the SiC MESFET
of Fig. 2-46. However, the algorithm of Fig. 2-54 eliminates the dependency on Vgsq by
assuming that the self-heating afflicted PGIV data points at Vgsq =-2.0V alone are suffice
to characterize the thermal effects on I ds . This greatly simplifies the modeling process
over a multiplicity of thermal parameters. Modeling of K Pn and K MIpkb follow a very
similar algorithm with the exception that Pn,T0 and M Ipkb,T0 are Vds -dependent whereas
I pk ,T0 is constant for the GaN HEMT.
128
K Ipk =
1  I pk ,Vgsq1 
−1

∆TVgsq1  I pk ,T0

K Ipk = K Ipk1Vdsq + K Ipk 0
Fig. 2-54
Modeling algorithm for thermal-varying I pkth . (GaN)
The thermal factors K Ipk , K Pn , and K MIpkb are computed from data by rearranging
(2-46)-(2-48) and assuming steady-state thermal conditions ( ∆T ' = ∆T ) to obtain:
K Ipk =
1
∆T
 I pkth


− 1
 I pk ,T


0

(2-49)
K Pn =
1
∆T
 Pnth


− 1 for n = 1,2,3
 Pn,T

 0

(2-50)
129
K MIpkb =
1
∆T
 M Ipkbth


− 1
 M Ipkb,T


0

(2-51)
The change in temperature ∆T can be computed in a manner similar to the algorithm
described in Fig. 2-47. In this computation, the bias points of the PGIV at Vgsq =-2.0V
contained in the I dsq -vs- Vdsq characteristic are used to compute PD and ∆T which are
placed into a vector. The computation for the GaN HEMT is simpler than for the SiC
MESFET because Rth is constant and only a single Vgsq is considered. The computed
values as functions of Vdsq are shown in Fig. 2-55.
The bias dependent thermal factors can then be modeled over Vdsq using simple linear
formulas modified with a tanh-based multiplier to cover the low Vgsq regime:
K Ipk = ( K Ipk 0 + K Ipk1Vds ) tanh(α KIpkVds )
(2-52)
K Pn = ( K Pn 0 + K Pn1Vds ) tanh(α KPnVds ) for n = 1,2,3
(2-53)
K MIpkb = ( K MIpkb0 + K MIpkb1Vds ) tanh(α KMIpkbVds )
(2-54)
where the fitting parameters, K Ipk 0 , K Ipk1 , K Pn 0 , K Pn1 , K MIpkb0 and K MIpkb1 , are
determined using linear fitting algorithms. The partial-fit linear models are shown in Fig.
2-55 and the unoptimized parameters are provided in Table 2-9. The parameters α KIpk ,
α KPn , α KMIpkb are then determined manually to force zeroing at low Vdsq .
130
0
20
-5
15
KP1
KIpk
GaN HEMT: KIpk, KP1, KP2, KP3, KM from PGIV at Vgsq=-2V, Vdsq=[0:2:28]V
-10
10
-15
5
-20
0
0
10
20
30
40
50
60
0
10
20
40
0
30
-5
20
10
50
60
40
50
60
-10
-15
0
-20
0
10
20
30
40
50
0
60
10
20
Vds (V)
15
KM
30
Vds (V)
20
10
5
0
0
10
20
30
40
50
Vds (V)
Fig. 2-55
40
Vds (V)
KP3
KP2
Vds (V)
30
Thermally-varying parameters. (GaN)
(DISS_DC_equation_thermal_parameter_model_opt.dds)
60
131
K Ipk 0
Thermally-varying model parameters (GaN)
Unoptimized
Tuned/Optimized
-0.00825228
-0.00313982
K Ipk1
4.2046e-005
5.62613e-006
α KIpk
N/A
0.0816306
K P 30
-0.00707723
-0.00188697
K P 31
4.66134e-005
-5.325e-006
α KP 3
N/A
0.202857
K P 20
0.0372809
0.000534833
K P 21
α KP 2
-0.000542379
N/A
-5.50012e-006
1.57538
K P10
0.00990784
-0.00188697
K P11
α KP 1
-0.000110974
N/A
-5.325e-006
0.202857
K MIpkb0
0.0131147
0.000534833
K MIpkb1
-8.91299e-005
-5.50012e-006
α KMIpkb
N/A
1.57538
Table 2-9
Validation using transient PGIV
The true efficacy of the GaN HEMT I ds thermal relationships is confirmed through
comparisons with transient PGIV simulations. However, several permutations of the
present I ds model (and thermal relationships) are required in order to make a valid
comparison with PGIV data.
1. Adapt the I ds equations to depend on internal bias dependency
The I ds model for the GaN HEMT has not yet been adjusted for parasitic resistances.
Therefore, first, the I ds formula is implemented as a network component and placed in a
132
large-signal topology. The terminal dependencies are then modified for the intrinsic
biases as described by Fig. 2-18.
2. Transition the model to Vgsq =-3.0V
Next, the zero self-heating baseline of the I ds model is altered.
The PGIV at
Vgsq =-4.0V is used as a baseline dataset from which the I ds parameters under zero self-
heating are extracted. However, a Vgsq =-4.0V places the device under a deep pinchoff
state which may cause increased charge trapping phenomena.
Charge-trapping is
explained in detail in Chapter 2.2.3.7. Therefore, it is important to form the foundation of
the model using a pinchoff state that does not subject the device to excessive chargetrapping. The PGIV at Vgsq = V p =-3.0V is used as the new I ds reference since it is closer
to the actual pinchoff of the device.
3. Temporarily assume large time constant (large Cth )
At this point, the GaN HEMT I ds model does not yet have a fully characterized
thermal model because it lacks a precise Cth value. An interim Cth is set to a value large
enough to provide a time-constant that is insensitive to short duration voltage pulses.
This Cth used in a first-order model of Fig. 2-38 allows the accurate simulation of PGIV
characteristics and refinement of the thermal relational parameters despite the use of an
incomplete thermal model.
4. Optimization of the I ds model to attain a PGIV match
133
The re-evaluation of the I ds model for PGIV at Vgsq = V p =-3.0V including parasitic
resistances requires an adaptation of the parameters extracted from PGIV at Vgsq =-4.0V.
This is performed using optimization under transient PGIV simulations. The g m - and
I ds -vs- V gs characteristics under Vgsq = V p =-3.0V, Vdsq =50V are shown in Fig. 2-56a and
the full PGIV curves at Vgsq = V p =-3.0V are shown in Fig. 2-56b. The curves demonstrate
a high precision of the GaN HEMT I ds formulation over a very large range of Vdsq and
I dsq . Accurate characterization and modeling of pulsed power up to 132W at Vdsq =56V
is observed. The final I ds model parameters are provided in Table 2-10.
Table 2-10 I ds parameters, final deembedded and optimized (GaN)
P10
P11
α P1
P1o
V pk1
6.7168e-1
P20
1.3998e-3
P21
1.9607e-1
-1.2481e-1
P2o
-2.1622
V pk 2
-4.5689e-1
P30
-9.2484e-4
P31
4.0000e-1
α P3
1.0612e0
P3o
-1.5581
V pk 3
-3.5538e-1
PM 0
2.9293e0
PMo
-9.5577e-4
PM 1
4.2749e-2
PQ 0
8.3328e-2
PM 2
-1.0711e-3
PQ1
7.0601e-1
PM 3
8.6205e-6
αQ
-0.71072
9.3855e-1
PQo
3.3322e-3
VgsM
-1.4907e-1
I pk
-5.3123e-4
5.7575e-2
9.2327e-1
-0.084480
0.61463
1.1512e+1
α P2
αM
α
5. Optimization of thermal parameters
The thermal relational parameters extracted in the previous section are optimized
under transient PGIV simulations at two other quiescent gate biases: Vgsq =-2.1V and
-1.7V. The final, optimized thermal parameters are provided in Table 2-9.
134
At Vgsq =-2.1V, the g m - and I ds -vs- V gs at Vdsq =50V and the full PGIV curves are
shown in Fig. 2-56c and Fig. 2-56d, respectively. Additionally at Vgsq =-1.7V, the g m and I ds -vs- V gs at Vdsq =50V and the full PGIV curves are shown in Fig. 2-56e and Fig.
2-56f, respectively.
A perusal of the comparative measured data and modeled
computations shown in Fig. 2-56a, Fig. 2-56c, Fig. 2-56e illustrate the efficacy of the
thermal model in predicting degradations of g m and I ds due to self-heating. Furthermore
the close predictions of the full PGIV datasets of Fig. 2-56b, Fig. 2-56d, Fig. 2-56f
validate the capability of the thermally-modified I ds formula to accurately depict
complete PGIV characteristics under various levels of self-heating.
Therefore, despite the simplifications applied to the GaN HEMT thermal model, the
resulting formulations are excellent in predicting the pulsed electrical behavior of the
device.
135
2.5
2.5
0.8
2.0
2.0
0.6
1.5
0.4
1.0
1.0
0.2
0.5
0.5
0.0
0.0
gm (A/V)
1.0
0.0
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Ids (A)
3.0
Vgsq=-3.0V, Vdsq=50V
Vgs=[-2.9:0.2:0.7]V
Ids (A)
3.0
1.2
Vgsq=-3.0V, Vdsq=[0:2:56]V, Vgs=[-2.7:0.2:0.7]V
1.5
0
1.0
10
20
Vgs (V)
(a)
2.5
2.5
0.8
2.0
2.0
0.6
1.5
0.4
1.0
1.0
0.2
0.5
0.5
0.0
0.0
Vgsq=-2.1V, Vdsq=50V
Vgs=[-2.9:0.2:0.7]V
gm (A/V)
0.0
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
Ids (A)
3.0
1.0
0
1.0
10
20
0.8
2.0
2.0
0.6
1.5
0.4
1.0
1.0
0.2
0.5
0.5
0.0
0.0
gm (A/V)
0.0
Fig. 2-56
-1.5
-1.0
-0.5
0.0
0.5
1.0
Ids (A)
2.5
Ids (A)
2.5
Vgsq=-1.7V, Vdsq=50V
Vgs=[-2.9:0.2:0.7]V
-2.0
40
50
56
(d)
3.0
-2.5
30
Vds (V)
3.0
-3.0
56
1.5
(c)
1.0
50
Vgsq=-2.1V, Vdsq=[0:2:56]V, Vgs=[-2.7:0.2:0.7]V
Vgs (V)
1.2
40
(b)
3.0
Ids (A)
1.2
30
Vds (V)
Vgsq=-1.7V, Vdsq=[0:2:56]V, Vgs=[-2.7:0.2:0.7] V
1.5
0
10
20
30
Vgs (V)
Vds (V)
(e)
(f)
40
50
56
PGIV-based g m - and I ds -vs- V gs at Vdsq =50V for (a) Vgsq =-3.0V (b)
Vgsq =-2.1V (c) Vgsq =-1.7V. Full PGIV at (d) Vgsq =-3.0V (e) Vgsq =-2.1V (f)
Vgsq =-1.7V with quiescent biases (X’s). Measured (symbols), modeled
(solid lines). (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_gm_vgsq030_opt.dds)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_gm_vgsq021_opt.dds)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_gm_vgsq017_opt.dds)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_ultimate_vgsq030_opt.dds)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_ultimate_vgsq021_opt.dds)
(DISS_Tran_lsmodel_xtr09_IV_PGIV_ultimate_vgsq017_opt.dds)
136
2.2.3.6.4. Thermal Time Constants and Thermal Capacitance
The requirement for the accurate simulation of short-duration PGIV characteristics is
that the thermal time constant is much larger than the pulse duration. Previously, a
simple first-order model (Fig. 2-38) with Rth and Cth set to an arbitrarily large value is
used to make the thermal behavior insensitive to short duration pulses. This allows for
the computation of the thermal relational parameters which dictate the pulsed and
quiescent I ds behavior. However, once the short duration pulsed behavior is obtained, a
precise characterization of the transient behavior using a K-order self-heating model can
be achieved. Extraction of this model consists of partitioning Rth into Rth, k and finding
the corresponding C th ,k .
However, explicit determination of Rth, k and C th ,k is be impeded by the use of a
nonlinear Rth (2-35) which is bound by (2-28) to retain the correct computation of the
thermally-modified I ds behavior. Therefore, nonlinear Rth can be separated from the
thermal circuit elements and combined with the current source as shown in the
normalized thermal model of Fig. 2-57.
∆T '
T
Fig. 2-57
Cˆ th ,1
Cˆ th , 2
Cˆ th , K
Rˆ th ,1
Rˆ th , 2
Rˆ th , K
PD Rth ,eq
Equivalent normalized thermal model circuit.
T0
137
The normalized thermal model is mathematically equivalent to the unnormalized
thermal model of Fig. 2-37 and retains the correct transient behavior.
The main
difference is that the time constants are determined by the normalized values
τ k = Rth ,k Cth ,k = Rˆ th, k Cˆ th, k
(2-55)
Cˆ th ,k = Cth ,k Rth
(2-56)
where Rˆ th ,k are fractions of 1 while Cˆ th ,k are thermal capacitances scaled by Rth . The
Rˆ th ,k and Cˆ th ,k can be determined without a direct value for Rth .
Although the
normalization does not provide the correct units for Rˆ th ,k and Cˆ th ,k , it is convenient for
deembedding Rth from the thermal circuit so that the time constants can be determined
separately.
The behavior of I ds due to transient temperature changes will follow an exponential
response similar to that described in (2-26).
Therefore, once Rth and the thermal
relationships of I ds are known, the time-constant parameters can be extracted from PGIV
transient behavior measured over long pulse durations. First- and third-order normalized
self-heating thermal models are developed for both the SiC MESFET and GaN HEMT.
SiC MESFET
For the SiC MESFET, a long-duration PGIV transient at V gsq =-11.0V and Vdsq =55V
is measured over a pulse width of ~10ms as shown in Fig. 2-58. At t=20ms, the gate is
increased to Vgs =-3V and I ds reaches a peak value of ~1.15A. As self heating sets in,
138
I ds decays to a steady state value of ~800mA. Finally, at around t=30ms, the gate is
stepped back down to Vgs =-11V causing I ds to drop towards its quiescent value.
Since Rth ,eq is nonlinear in the case of the SiC MESFET, Rth, k and C th ,k cannot be
explicitly determined. Instead, Rˆ th ,k and Cˆ th ,k are determined using optimization with the
goal of matching the pulsed shape of I ds over time. The transients computed using firstand third-order models are shown in Fig. 2-58 alongside the measured data revealing a
first-order accuracy up to 2ms and a third order accuracy over the entire 10ms pulse. The
Rˆ th ,k and Cˆ th ,k values for the first- and third-order models are summarized in Table 2-11
and Table 2-12, respectively.
139
SiC MESFET: Vgsq=-11.0V, Vgs=-3.0V, Vdsq=55V
Ids (A)
1.5
Complete view
K=3
1.0
0.5
K=1
0.0
10
15
20
25
30
35
40
35
40
time, msec
1.2
Zoomed view
Ids (A)
1.1
1.0
0.9
K=3
0.8
0.7
K=1
0.6
10
15
20
25
30
time, msec
Fig. 2-58
Long duration PGIV transient measurement and modeled using first- and
third-order thermal models. (a) Standard view and (b) Zoomed view. (SiC)
(DISS_Tran_ls_thermal_IV_PGIV_long_pulse.dsn)
Table 2-11 First-order thermal model parameters (SiC)
Rˆ th,1
Cˆ th ,1 (E-3)
1
4.20
140
Table 2-12 Third-order thermal model parameters (SiC)
Rˆth ,1
Rˆth , 2
Rˆth ,3
Cˆ th ,1 (E-3)
6.77878E-1
2.73863E-3
3.19384E-1
24.3022
Cˆ th , 2 (E-3)
Cˆ th ,3 (E-3)
9.22899
3.14731
GaN HEMT
For the GaN HEMT, a long-duration PGIV transient at Vdsq =28V is measured over a
5ms pulse width and 500ms period as shown in Fig. 2-59. At t=2ms, the gate is pulsed
from Vgsq =-2.64V to Vgs =-1.7V and the subsequent I ds is excited from zero to a peak
value of ~600mA. This is followed by a slow decay of I ds towards ~550mA as thermal
charging due to the dissipated power reaches steady-state. At t=7ms, Vgs returns to
-2.64V causing and I ds to drop towards its original value.
In the case of the GaN HEMT, Rth ,eq is implemented as a constant and therefore, Rth, k
and C th ,k can be explicitly computed once Rˆ th, k and Cˆ th ,k are found.
The model
parameters are determined through optimization such that the computed transient I ds
matches the measured trace over a maximized duration. The computed I ds transients
using the first- and third-order models are provided in Fig. 2-59. The first-order model
provides accuracy only up to 0.2ms and, as such, prematurely predicts the degradation of
I ds to its quiescent value. In comparison, the third-order thermal model provides an
improved accuracy over the entire 5ms pulse duration. The Rˆ th, k , Cˆ th ,k , Rth, k and C th ,k
values for the first- and third-order models are summarized in Table 2-13 and Table 2-14,
respectively.
141
GaN HEMT: Vgsq=-2.64V, Vgs=-1.7V, Vdsq=28V
800
Complete view
K=3
Ids (mA)
600
400
200
K=1
0
0
1
2
3
4
5
6
7
8
9
7
8
9
time, msec
650
Zoomed view
Ids (mA)
600
K=3
550
K=1
500
450
0
1
2
3
4
5
6
time, msec
Fig. 2-59
Long duration PGIV transient measurement and modeled using first- and
third-order thermal models (a) Standard view and (b) Zoomed view. (GaN)
(DISS_Tran_lsmodel_xtr02_IV_PGIV_long_pulse.dds)
Table 2-13 First-order thermal model parameters (GaN)
Rˆ th,1
Cˆ th ,1 (E-3)
1
Rth,1 ( Ω )
0.45
C th ,1 (mF)
5
0.09
142
Table 2-14 Third-order thermal model parameters (GaN)
Rˆth ,1
Rˆth , 2
Rˆth ,3
Cˆ th ,1 (E-3)
Cˆ th , 2 (E-3)
Cˆ th ,3 (E-3)
7.10052E-1
Rth,1 ( Ω )
1.34160E-1
Rth, 2 ( Ω )
1.55788E-1
Rth, 3 ( Ω )
72.2566
C th ,1 (mF)
6.18363
C th , 2 (mF)
0.39974
C th ,3 (mF)
3.55026
0.6708
0.77894
14.45132
1.236726
0.079948
It is important to note that the accurate computation of the drain current under the
instances of pinchoff, pulsed excitation and self-heating is due to correctly implemented
baseline drain current and thermal relational parameters. For the SiC MESFET these
respective instances occur when the drain current initializes under Vgsq =-11.0V, peaks at
t~20ms and saturates due to Vgsq =-8.0V. For the GaN HEMT these respective instances
occur when the drain current initializes under Vgsq =-2.64V, peaks at t~2ms and saturates
due to Vgsq =-1.7V.
2.2.3.7.
Charge-trapping
As relatively immature processes, SiC MESFETs and GaN HEMTs fabrication gives
rise to interstitials, which that can trap charges and alter charge-transport.
Characterization of trapping phenomenon and their adverse effects on microwave
performance is important. Although III-V semiconductor fabrication is improving, the
existence of trapping phenomena is inevitable in any emerging semiconductor
technology. Therefore, a solid strategy for modeling trapping phenomena is necessary.
There are two main types of charge-traps: substrate and surface trapping. Substrate
traps exist in the bulk due to imperfections in the semiconductor lattice. The presence of
substrate traps causes a reduction of mobility due to the capture and release of charges,
hindering charge transport. The occupied substrate traps disrupt the internal electric
143
fields of the device, reducing the efficacy of the externally applied potentials. The net
effect of these byproducts is a reduction of I ds .
Surface traps exist due to imperfections in the lattice at the metal-semiconductor gate
interface. These surface traps can reduce the mobility of the carriers due to the capture
and release processes at that junction and further impair the efficacy of the applied gate
potential.
There is no means to measure the density and occupation state of charge-trapping
using empirical methods and the exact mechanics of trapping due to the electrical state
are not well-defined [105]. However, the influence of trapping on I ds can be detected
through IV measurements. Static measurements have revealed anomalous “kink” effects
in the IV characteristics of GaN devices [103][104][105] and PIV characterization can
be used to exploit the charge-trapping state of the device represented at a particular
operating point [57].
An explanation and dynamic model for the electrical effect due to charge-trapping
was presented in [55]. Further applications of this dynamic model have been performed
in [56][57]. A detailed investigation of the charge-trapping circuit analogue and its
reduction to a simplified form as used in this work is provided in Appendix A.3.
In this section, a technique for characterizing surface and substrate charge-trapping
using PIV to compile a simplified, quasi-static model is presented. The identification of
charge-trapping effects on PIV data is described followed by an extraction of the model
parameters for the SiC and GaN device.
Once the charge-trapping model is
implemented, the complete large-signal models of both devices will be further validated
for PIV prediction capabilities.
144
Effect of charge-trapping on PIV
High power PGIV characteristics can partially exploit current dispersion, but cannot
differentiate the effects of self-heating from those of charge-trapping.
Additionally,
PGIV lacks drain-pulsing and therefore may not provide accurate predictions of g ds at
RF. Therefore, it is necessary for the I ds model to accommodate PIV in addition to
PGIV to provide a better prediction of large-signal RF behavior at a given operating
point. Strategies for modeling the influence of trapping on I ds using isothermal PIV
measurements have been published [56][57].
Dynamic charge-trapping effects can be avoided by using short duration
( τ pulse << τ trap ) PIV datasets of the same thermal but different electrical operating points.
Differences between these PIV sets can be attributed to the static trapping associated with
the quiescent bias only [93]. Substrate traps produce a backgate voltage while surface
traps directly reduce the effect of the applied gate bias. Ultimately, both effects can be
incorporated as modifications to the effective gate-source voltage, Vgs ,eff , which
substitutes all instances of Vgs in the large-signal model [55][56][57][72][74]:
Vgs ,eff = V gs + Voff , subs + Voff , surf
(2-57)
where Voff , subs and Voff , surf are the offset voltages determined by substrate and surface
trapping, respectively.
Comparison of isothermal PIV measurements will exploit a relationship between the
gate offset voltages and the quiescent bias. In an ideal modeling process, a large-signal
model based on zero-charge-trapping PIV characteristics is created, a self-heating
145
thermal model is implemented and then charge-trapping relationships are applied. Under
this situation, Voff , subs and Voff , surf degrade Vgs ,eff in the presence of charge-trapping.
However, the I ds model presented here has been defined using high power PGIV data
which consequentially includes embedded static trapping states, making a PIV-based
charge-trapping free I ds model unavailable. Under these circumstances, Voff , subs and
Voff , surf may degrade or enhance Vgs ,eff depending on the given operating point.
A strategy to simultaneously characterize and deembed charge-trapping is pursued.
Characterization is performed by extracting Voff , subs and Voff , surf through comparisons of
the PGIV-based model output and measured PIV datasets at certain quiescent bias. Any
direct comparison requires an equivalent self-heating state, leaving only differences
created by charge-trapping.
Unfortunately, PGIV curves consist of points spanning
across Vdsq , each of which exhibits a different self-heating level.
One important
exception is PGIV at Vgsq ≤ V p , where the device is void of self-heating. PIV datasets
biased at any quiescent point in which Vgsq ≤ V p and/or Vdsq =0V will be void of selfheating.
Substrate trapping
A substrate trapping deembedding model can be deduced at pinchoff. Subjecting the
I ds model in its present state to PIV excitation will only produce PGIV curves since the
model cannot distinguish between quiescent and pulsed excitations at the drain. This
provides a gateway for developing a relationship between PIV and PGIV.
146
Consider the illustration of two cases comparing measured and modeled PIV
characteristics. The first case (Fig. 2-60a), shows a measured PIV curve obtained with
PIV
PIV
the device biased at a zero-self-heating point of { Vgsq
= V p , Vdsq
=0V}, pulsed to a
constant VgsPIV and pulsed over a range of VdsPIV . Here, the device exhibits no substrate
PIV
trapping since Vdsq
=0V. The figure also shows a PGIV curve obtained with the device
PGIV
PGIV
biased at Vgsq
= V p and pulsed to a constant VgsPGIV , over a range of Vdsq
, where
PGIV
VgsPGIV = VgsPIV and Vdsq
= VdsPGIV . The discrepancy between the PIV and PGIV points can
PGIV
be viewed as a difference in g ds due to Vdsq
-dependent substrate trapping experienced
under PGIV.
The PIV trace, on the other hand, remains substrate trapping-free at
PIV
Vdsq
=0. Alternatively, a reduced g ds can be interpreted as a reduced g m that changes
with Vds .
147
Data
VgsqPIV=Vp
VdsqPIV=0V
VgsPIV=const
VdsPIV=range
Ids
Model
VgsqPGIV=Vp
VgsPGIV=const
VdsqPGIV=range
Data
VgsqPIV=Vp
VdsqPIV>0V
VgsPIV=const
VdsPIV=range
Ids
Model
VgsqPGIV=Vp
VgsPGIV=const
VdsqPGIV=range
PIV
curve
PIV
curve
PGIV
curve
PGIV
curve
One IV point
overlaps
One IV point
overlaps
VdsqPIV
One Q-point
overlaps
Vds
Ids
VdsqPIV
One Q-point
overlaps
Vds
Ids
PIV
curve
PIV
curve
Voff
Voff
PGIV
curve
Voff
PGIV
curve
Interpret as
Vgs,effPIV > Vgs,effPGIV
Interpret as
Vgs,effPIV > Vgs,effPGIV
(a)
Fig. 2-60
Interpret as
Vgs,effPIV < Vgs,effPGIV
Vds
(b)
Vds
PGIV
PIV
PIV
Comparison of PGIV{ Vgsq
} and PIV{ Vgsq
, Vdsq
} characteristics for
substrate trapping extraction (a) Case I: PGIV{ V p } vs. PIV{ V p ,0V} and (b)
Case II: PGIV{ V p } vs. PIV{ V p ,>0V}.
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_vgsq110_opt.dds verification)
The second example (Fig. 2-60b) shows a PIV curve biased at a different zero-selfPIV
PIV
heating point { Vgsq
= V p , Vdsq
>0V} and pulsed to a constant VgsPIV and over the same
VdsPIV range as in the previous example. However, at this bias point, the device exhibits
PIV
substrate trapping associated with the nonzero Vdsq
. The figure also shows the PGIV
PGIV
PIV
PGIV
curve from the previous example where Vgsq
= Vgsq
and Vdsq
= VdsPIV . Although the
g ds of the PIV curve is higher than the PGIV curve over the entire Vds range, g m is not.
148
PGIV
PIV
For Vdsq
> Vdsq
, the PIV curve is higher than the PGIV curve since the PGIV data
exhibits more substrate trapping than the PIV case (as in the previous case). However,
PGIV
PIV
< Vdsq
, the PIV curve is lower than the PGIV curve since the PGIV data
for Vdsq
exhibits less substrate trapping than the PIV case.
Therefore, deembedding of the charge-trapping from the PGIV-based I ds formula can
be performed through an offset voltage modification to the effective gate-source voltage,
Vgs ,eff . The change in Vgs ,eff depends on the drain-source pulse magnitude and direction
relative to Vdsq :
1. Reduce Vgs ,eff at Vds < Vdsq (pulse the drain-source below Vdsq ) and increase Vgs ,eff
at Vds > Vdsq (pulse the drain-source above Vdsq ).
2. Increase the degree of Vgs ,eff modification in proportion to how far away the
pulsed Vds is from Vdsq .
Mathematically, the offset voltage is
Voff , subs = ρ subs (Vds − Vdsq )
(2-58)
where ρ subs is the substrate trapping factor. The variation of the degree of substrate
trapping with Vdsq is accounted for by
ρ subs = ρ subs1 (Vdsq + Vsubs 0 )
(2-59)
where ρ subs1 (Volts-1) and Vsubs 0 are constants determining the influence of substrate
trapping as a function of Vdsq and the instantaneous Vds .
149
The device experiences increased substrate trapping at higher Vdsq .
When the
instantaneous Vds is pulsed to values below a given Vdsq , Vgs ,eff is reduced during that
pulse due to backgating since the substrate trapping is dictated by the higher Vdsq .
On the other hand, Vgs ,eff is enhanced when the instantaneous Vds is pulsed above
Vdsq . The substrate trapping relationships shown in (2-58)-(2-59) accurately account for
this effect which is more pronounced as Vdsq increases.
There exist many corresponding PGIV-PIV trace pairs which can be used to extract
the substrate trapping factor since the only requirement is the use of a quiescent bias at
Vgsq <= V p . Additionally, even PGIV-PIV trace pairs with Vgsq > V p can be used as long
as self-heating has been implemented correctly, and there is no surface trapping activated
by nonzero Vgsq .
Extraction of the substrate trapping factor is performed by comparing I ds -vs- Vgs
PGIV
curves from the PGIV-based model with PIV data at a common Vdsq
= VdsPIV as
illustrated in Fig. 2-61. The Voff , subs corresponding to the difference in I ds at a fixed Vgs
can be found and the substrate trapping factor can be computed be rearranging (2-58) and
solving for ρ subs :
ρ subs =
Voff , subs
PIV
VdsPIV − Vdsq
(2-60)
This process can be repeated at several drain-source voltages and the values can be
averaged to obtain a generalized ρ subs . Determination of ρ subs is performed at multiple
150
PIV
Vdsq
, from which a linear fit is performed to extract ρ subs1 and Vsubs 0 of (2-59). At
Vdsq =0V, the trapping factor is equal to the product ρ subs1Vsubs 0 .
Fig. 2-61
Extraction of the trapping factor using I ds -vs- Vgs from PIV data and PIVexcited model.
Surface trapping
Once substrate trapping effects have been deembedded from I ds , surface trapping
effects can be addressed. Like substrate trapping and its relationship to Vdsq , surface
trapping is exploited using PIV measurements at different Vgsq biases. However, since
I dsq is highly sensitive to Vgsq , the selection of PIV which will exploit surface trapping
without triggering self-heating is limited to cases where Vdsq =0V. With self-heating and
substrate trapping accounted for, the effect of surface trapping can be explored by using
PIV datasets at different Vgsq .
151
PIV 1
PIV 1
Consider a single PIV trace biased at V gsq
=0V, Vdsq
=0V, pulsed to a constant
V gsPIV 1 and over a range of VdsPIV 1 as illustrated in Fig. 2-62a. This PIV trace will represent
measured data. Under this quiescent point the device exhibits the best possible PIV
performance at these pulsed voltages since both charge-trapping and self-heating
( I dsq =0A) are absent.
Although the model has been deembedded for Vds -dependent substrate-trapping, it
cannot correctly predict g m at this quiescent bias, since it is founded on PGIV at pinchoff
and does not discriminate the charge-trapping effects associated with Vgsq (it only
discriminates self heating effects created by PD due to the Vgsq -controlled I dsq ). Instead,
PIV 2
PIV 2
the model will produce curves which closely resemble PIV at Vgsq
= V p , Vdsq
=0 under
the same pulsed excitations ( VgsPIV 2 = VgsPIV 1 , VdsPIV 2 = VdsPIV 1 ) as illustrated in Fig. 2-62a.
This reduction of g m due to surface trapping can be deembedded from the model using a
gate-source offset voltage, Voff , surf . The magnitude of the offset voltage is proportional to
the difference in the pulsed voltage and pinchoff.
Voff , surf = ρ surf (V gs − V p )
where ρ surf is the surface trapping factor.
(2-61)
152
Data
VgsqPIV1=0V
VdsqPIV1=0V
VgsPIV1>>Vp
VdsPIV1=range
Ids
Model
VgsqPIV2=Vp
VdsqPIV2=0V
VgsPIV2>>Vp
VdsPIV2=range
Ids
Data
VgsqPIV1=0V
VdsqPIV1=0V
VgsPIV1>Vp
VdsPIV1=range
Model
VgsqPIV2=Vp
VdsqPIV2=0V
VgsPIV2>Vp
VdsPIV2=range
PIV data
PIV data
PIV model
PIV model
One IV point
overlaps
One Q-point
overlaps
VdsqPIV
Vds
Ids
PIV data
Vds
VdsqPIV
Ids
PIV data
Voff
Voff
PIV model
PIV model
Interpret as
Vgs,effdata > Vgs,effmodel
(a)
Fig. 2-62
Interpret as
Vgs,effdata > Vgs,effmodel
Vds
Vds
(b)
Comparison of PIV model and PIV data for surface trapping extraction
using for a (a) high gate pulse and (b) low gate pulse.
Furthermore, the surface trapping deembedding applies only for Vgsq > V pinch (at which
the model is founded), and the trapping factor increases for every volt that Vgsq is greater
than V pinch as illustrated in Fig. 2-62b. The quiescent-dependent ρ surf can be expressed
by
ρ surf = ρ surf 1 (Vgsq − V p )
where ρ surf 1 is a constant fitting parameter of the surface trapping factor.
(2-62)
153
Another possible way of characterizing surface trapping is to use PDIV (pulsed-drain
only IV) measurements under Vdsq =0V with Vgsq set anywhere between V p and V f , the
forward conduction voltage, while Vds is pulsed over a range.
Extraction of the surface trapping factor is performed by comparing I ds -vs- Vgs
curves computed from the model under PIV excitation and PIV data at a particular Vds as
is done for substrate trapping shown in Fig. 2-61. The Voff , surf corresponding to the
difference in I ds at a fixed Vgs can be found and the surface trapping factor ρ surf can be
computed by rearranging (2-61)
ρ surf =
Voff , surf
V gs − V p
(2-63)
This process can be repeated at different Vds and the values can be averaged to obtain
a generalized ρ surf . Performing the extraction process over various Vgsq , ρ surf can then
be linearly fit using (2-62).
Optimizing any of the charge-trapping parameters can be performed to achieve the
best fit with PIV. By employing the deembedding method presented here, the device
obtains the ability to predict PIV without affecting its ability to predict PGIV.
SiC MESFET
The extraction of the trapping parameters for the SiC MESFET are described next.
The algorithm used to extract and optimize the trapping parameters is shown in Fig. 2-63.
154
ρ subs
ρ subs
ρ subs
ρ subs
Vgs ,eff = Vgs + Voff ,subs
Simulated PIV
characteristics
ρ subs1 Vsubs0
Initial parameter set
Measured
PIV
characteristics
ρ subs1 Vsubs 0
Voff , subs = ρ subs (Vds − Vdsq )
ρ subs = ρ subs1 (Vdsq + Vsubs0 )
ρ subs1 Vsubs 0
Fig. 2-63
Algorithm for substrate-trapping extraction. (SiC)
It was shown that charge trapping within SiC MESFETs is dominated by substrate
traps and that surface trapping effects are limited since SiC is a relatively mature III-V
semiconductor technology [72]. Therefore, the surface trapping parameter is ignored
( ρ surf =0) and attention is placed on the substrate trapping parameter extraction.
In the first deembedding phase, the model is compared with PIV measurements
performed at Vdsq =0V where the device free of substrate trapping. Unfortunately, PIV
155
data at { Vgsq , Vdsq }={ V p ,0V} is unavailable for making a direct comparison to the model
(as shown Fig. 2-60a). Instead PIV at {0V,0V} are used. Although not ideal, this is still
a valid comparison since surface trapping in SiC devices is negligible.
The I ds -vs- Vgs data and model output computed under PIV excitation at {0V,0V} for
four different pulsed Vds values are shown in Fig. 2-64. As explained earlier, the output
from the model resembles PGIV at Vgsq =-10V despite being under PIV excitation. The
Voff , subs is extracted at each Vds and the corresponding ρ subs are computed as provided in
Table 2-15.
1.8
1.8
Vgsq=0V, Vdsq=0V, Idsq=0A
1.6 Vds=12V
1.4
Voff,subs=0.25V
Vgsq=0V, Vdsq=0V, Idsq=0A
Vds=24V
1.4
Voff,subs=0.65V
1.2
Ids (A)
Ids (A)
1.2
1.6
1.0
Data
0.8
0.6
1.0
Data
0.8
0.6
Model
0.4
Model
0.4
0.2
0.2
0.0
0.0
-14
-12
-10
-8
-6
-4
-2
0
-14
-12
-10
Vgs (V)
1.8
1.6
Vgsq=0V, Vdsq=0V, Idsq=0A
Vds=36V
1.4
Voff,subs=0.95V
1.8
-6
-4
-2
0
1.6
Vgsq=0V, Vdsq=0V, Idsq=0A
Vds=48V
1.4
Voff,subs=1.20V
1.2
Ids (A)
Ids (A)
1.2
1.0
Data
0.8
1.0
0.8
Data
0.6
0.6
Model
0.4
Model
0.4
0.2
0.2
0.0
0.0
-14
-12
-10
-8
-6
Vgs (V)
Fig. 2-64
-8
Vgs (V)
-4
-2
0
-14
-12
-10
-8
-6
-4
-2
0
Vgs (V)
Substrate trapping extraction from PIV at {0V,0V} for Vds =[12,24,36,48]V.
(SiC)
(DISS_Tran_ls_thermal_xtr3633_IV_PGDIV_vgsq000_vdsq000_trap_extract.dds)
156
Table 2-15 PIV model and data comparison at {0V,0V} (SiC)
Vds (V)
Voff , subs (V)
ρ subs
Average ρ subs
12
24
36
48
0.25
0.65
0.95
1.20
0.021
0.027
0.026
0.025
0.025
Next, ρ subs is extracted under a different Vdsq . The I ds -vs- Vgs data and model output
computed under PIV excitation at {-3V,30V} for the same four pulsed Vds are shown in
Fig. 2-65. Despite the presence of self-heating, comparisons at this quiescent bias are
valid as long as no surface trapping exists and the model is equipped with a self-heating
model. This is true at this stage of the SiC MESFET model development. Unlike PIV at
{0V,0V}, the model output in Fig. 2-65 will not exactly resemble PGIV curves.
However, the same technique of extracting Voff , subs at each Vds and computing ρ subs can
be applied. The ρ subs parameters are provided in Table 2-16.
157
1.6
1.6
Vgsq=-3V, Vdsq=30V, Idsq=927mA
1.4 Vds=12V
1.2
Voff,subs=-0.22V
Vgsq=-3V, Vdsq=30V, Idsq=927mA
Vds=24V
1.2
Voff,subs=-0.05V
1.0
Ids (A)
Ids (A)
1.0
1.4
0.8
Model
0.6
0.8
Model
0.6
0.4
0.4
Data
0.2
Data
0.2
0.0
0.0
-14
-12
-10
-8
-6
-4
-2
0
-14
-12
-10
Vgs (V)
1.6
Vgsq=-3V, Vdsq=30V, Idsq=927mA
1.4 Vds=36V
Voff,subs=0.04V
Ids (A)
Ids (A)
-4
-2
0
1.4
Vgsq=-3V, Vdsq=30V, Idsq=927mA
Vds=48V
1.2
Voff,subs=0.11V
1.0
1.0
0.8
0.8
0.6
0.6
Data
0.4
Data
0.4
0.2
Model
0.2
Model
0.0
-14
-12
-10
-8
-6
0.0
-4
-2
0
Vgs (V)
Fig. 2-65
-6
Vgs (V)
1.6
1.2
-8
-14
-12
-10
-8
-6
-4
-2
0
Vgs (V)
Substrate trapping extraction from PIV at {-3V,30V} for
Vds =[12,24,36,48]V. (SiC)
(DISS_Tran_ls_thermal_xtr3633_IV_PGDIV_vgsq030_vdsq300_trap_extract.dds)
It can be observed that although substrate trapping deembedding is required as
illustrated by Fig. 2-60b, the magnitude is less pronounced at {-3V,30V} than at
{0V,0V}.
Table 2-16 PIV model and data comparison at {-3V,30V} (SiC)
Vds (V)
Voff , subs (V)
ρ subs
Average ρ subs
12
24
36
48
-0.22
-0.05
0.04
0.11
0.012
0.008
0.007
0.006
0.008
158
Once the average ρ subs from the two quiescent biases have been obtained, ρ subs1 and
Vsubs 0 can be computed using a linear fit and then optimized such that a good match
between measured and modeled is reached for all available PIV datasets.
Optimization is performed for three PIV datasets: {0V, 0V}, {-3V,30V}, {-6V,48V}
(third one not used in initial parameter extraction) and the resulting measured and
modeled curves are shown in Fig. 2-66. The extracted and optimized ρ subs1 and Vsubs 0 are
provided in Table 2-17.
Table 2-17 Substrate trapping deembedding parameters (SiC)
Parameter
Extracted
Optimized
-5.67e-4
-4.5e-4
ρ subs1
Vsubs 0
-44.0917
-61.111
Good agreement exists between the model output and measurements, validating the
efficacy of the substrate trapping relationship. Furthermore, if surface trapping exists, the
PIV at the isothermal quiescent points of {-3V,30V} and {-6V,48V} should differ.
However, a comparison of this data validates the assumption that surface trapping is
negligible since the differences in I ds are undetectable.
159
SiC MESFET
1.6
1.4
Ids (A)
1.2
Vgsq=0V
Vdsq=0V
Vgs=[-15:1:-2]V
Vds=[0:2:50]V
1.0
0.8
0.6
0.4
0.2
0.0
0
5
10
15
20
25
30
35
40
45
50
30
35
40
45
50
30
35
40
45
50
Vds (V)
(a)
1.6
Vgsq=-3V
Vdsq=30V
Vgs=[-15:1:0]V
Vds=[0:2:50]V
1.4
Ids (A)
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
5
10
15
20
25
Vds (V)
(b)
1.6
1.4
Ids (A)
1.2
Vgsq=-6V
Vdsq=48V
Vgs=[-15:1:0]V
Vds=[0:2:50]V
1.0
0.8
0.6
0.4
0.2
0.0
0
5
10
15
20
25
Vds (V)
(c)
Fig. 2-66
PIV characteristics measured and modeled at (a) {0V,0V} (b) {-3V,30V}
and (c) {-6V,48V}. (SiC)
(DISS_Tran_ls_thermal_xtr3633_IV_PGDIV_ultimate_three_biases_opt.dds)
160
GaN HEMT
The substrate and surface model parameter extraction algorithm used for the GaN
HEMT is shown in Fig. 2-67.
ρ subs
ρ subs
ρ subs
ρ subs
ρ subs1
Simulated PIV
ρ subs1 Vsubs 0
Initial parameter set
Measured PIV
Vsubs0
Vgs ,eff = Vgs + Voff , subs
Voff ,subs = ρ subs (Vds − Vdsq )
ρ subs = ρ subs1 (Vdsq + Vsubs0 )
ρ subs1 Vsubs0
Vgs,eff = Vgs + Voff ,subs + Voff , surf
Voff ,subs = ρ subs (Vds − Vdsq )
Simulated PIV
ρ surf 1
Initial parameter set
Measured PIV
ρ subs1 Vsubs0
ρ subs = ρ subs1 (Vdsq + Vsubs0 )
Voff ,surf = ρ surf (Vgs − V p )
ρsurf = ρsurf 1 (Vgsq − Vp )
ρ surf 1
ρ surf 1
Fig. 2-67
Algorithm for substrate- and surface-trapping extraction. (GaN)
161
In the case of the SiC MESFET, only a substrate trapping model is employed. Here,
the surface trapping is added since GaN HEMTs are less mature and also possess an
increased channel sensitivity to gate potential variations resulting from surface traps.
Both surface and substrate trapping extraction for the GaN HEMT is described next. The
GaN HEMT has been characterized under PIV at more quiescent points than the SiC
MESFET. Therefore, direct comparisons between the PGIV-based model and the PIV
data can be made and the proper extraction procedure can be executed.
For the substrate trapping extraction, comparisons between measured and modeled
PIV under Vgsq = V p are performed. By isolating Vgsq under zero-self-heating conditions,
the substrate-trapping created by nonzero Vdsq can be identified.
The I ds -vs- Vgs data and model output under PIV excitation at {-3V,14V} for four
pulsed Vds are shown in Fig. 2-68. The output of the model under PIV excitation will
resemble the PGIV at Vgsq =-3V. The Voff , subs is extracted and the corresponding ρ subs at
each Vds are computed as provided in Table 2-18.
162
1.5
1.5
Vgsq=-3V, Vdsq=14V, Idsq=0mA
Vds=12V
Voff,subs=-0.06V
Vgsq=-3V, Vdsq=14V, Idsq=0mA
Vds=24V
Voff,subs=0.03V
Ids (A)
1.0
Ids (A)
1.0
Model
0.5
0.5
Data
0.0
-3.0
Data
Model
0.0
-2.5
-2.0
-1.5
-1.0
-3.0
-2.5
Vgs (V)
1.5
-2.0
1.5
Vgsq=-3V, Vdsq=14V, Idsq=0mA
Vds=36V
-1.0
Vgsq=-3V, Vdsq=14V, Idsq=0mA
Vds=48V
Voff,subs=0.05V
Voff,subs=0.06V
1.0
Ids (A)
Ids (A)
1.0
Data
0.5
0.5
Data
Model
0.0
-3.0
-2.5
-2.0
-1.5
Model
-1.0
Vgs (V)
Fig. 2-68
-1.5
Vgs (V)
0.0
-3.0
-2.5
-2.0
-1.5
-1.0
Vgs (V)
Substrate trapping extraction from PIV at {-3V,14V} for (a)
Vds =[12,24,36,48]V. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGDIV_vgsq30_vdsq14_trap_extract.dds)
Table 2-18 PIV model and data comparison at {-3V,14V} (GaN)
Vds (V)
Voff , subs (V)
ρ subs
Average ρ subs
12
24
36
48
-0.06
0.03
0.06
0.05
0.030
0.003
0.003
0.001
0.003
Next, the extraction procedure is repeated at a higher Vdsq while maintaining
Vgsq = V p . The I ds -vs- Vgs data and model output under PIV excitation at {-3V,56V} for
four pulsed Vds are shown in Fig. 2-69. The output of the model under PIV excitation
163
still resembles the PGIV at Vgsq =-3V as in the previous case. However, now that Vdsq has
increased, Voff , subs is re-evaluated. The corresponding α trap, subs at each Vds are computed
and provided in Table 2-19.
1.5
1.5
Vgsq=-3V, Vdsq=56V, Idsq=0mA
Vds=12V
Voff,subs=-0.30V
Vgsq=-3V, Vdsq=56V, Idsq=0mA
Vds=24V
Voff,subs=-0.22V
Ids (A)
1.0
Ids (A)
1.0
Model
0.5
Model
0.5
Data
Data
0.0
-3.0
0.0
-2.5
-2.0
-1.5
-1.0
-3.0
-2.5
Vgs (V)
1.5
-2.0
1.5
Vgsq=-3V, Vdsq=56V, Idsq=0mA
Vds=36V
-1.0
Vgsq=-3V, Vdsq=56V, Idsq=0mA
Vds=48V
Voff,subs=-0.05V
Voff,subs=-0.12V
1.0
Ids (A)
Ids (A)
1.0
Model
0.5
0.5
Model
Data
0.0
-3.0
-2.5
-2.0
Vgs (V)
Fig. 2-69
-1.5
Vgs (V)
-1.5
Data
-1.0
0.0
-3.0
-2.5
-2.0
-1.5
Vgs (V)
Substrate trapping extraction from PIV at {-3V,56V} for
Vds =[12,24,36,48]V. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGDIV_vgsq30_vdsq56_trap_extract.dds)
-1.0
164
Table 2-19 PIV model and data comparison at {-3V,56V} (GaN)
Vds (V)
Voff , subs (V)
ρ subs
Average ρ subs
12
24
36
48
-0.30
-0.22
-0.12
-0.05
0.007
0.007
0.006
0.006
0.006
After the extraction of ρ subs at under pinchoff at two Vdsq , the linear fit parameters
ρ subs1 and Vsubs 0 of (2-59) are computed and tabulated in Table 2-20. The offset voltage
of (2-58) is then implemented into the complete large-signal model and its parameters are
optimized until a good fit with PIV datasets at {-3V,14V}, {-3V,28V} and {-3V,56V} is
achieved.
Table 2-20 Substrate- and surface-trapping model parameters (GaN)
Parameter
Extracted
Tuned/Optimized
7.14e-5
10.564e-5
ρ subs1
Vsubs 0
28.016
14.056
ρ surf 1
—
0.012879
Although the surface trapping extraction can be performed using I ds -vs- Vgs curves in
a similar manner to substrate trapping, the power limitations of PIV measurements lack
the data points needed to clearly exploit a deviation in I ds as Vgs increases. Instead, the
surface trapping parameters are most easily obtained under the graphical observation of
entire PIV datasets biased without self-heating at Vdsq =0V, but at different Vgsq .
The large-signal model without surface trapping model is simulated under PIV
excitation and compared with measured data at {0V,0V}, {-1.4V,0V} and {-3V,0V} as
shown in Fig. 2-70a, Fig. 2-70b, Fig. 2-70c, respectively. With a complete substrate
165
trapping induced Voff , subs term, the large-signal model accurately predicts the PIV at
Vgsq = V p for any Vds as shown in Fig. 2-70c for {-3V,0V}. However, the large-signal
model cannot differentiate between different levels of surface trapping due to Vgsq and
fails to predict the other two cases shown in Fig. 2-70a and Fig. 2-70b where Vgsq
deviates above -3V.
The Vgs ,eff of the large-signal model is modified with the surface-trapping induced
Voff , surf term and ρ surf 1 is determined under PIV at {0V,0V} using optimization. The
value is included in Table 2-20. Inspection of the updated PIV at {0V,0V}, {-1.4V,0V}
and {-3V,0V} shown in Fig. 2-70d, Fig. 2-70e, Fig. 2-70f, respectively, validates the
efficacy of the surface trapping model of (2-61)-(2-62) over the wide Vgsq range.
166
GaN HEMT: Vgs=[-3:0.25:-0.75]V, Vds=[0:2:56]V
No surface trapping model
With surface trapping model
1.6
1.4
Vgsq=0V
Vdsq=0V
Idsq=0mA
PD=0W
1.0
Ids (A)
Ids (A)
1.6
1.4
1.2
0.8
0.6
0.4
0.2
0.0
Vgsq=0V
Vdsq=0V
Idsq=0mA
PD=0W
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
50 56
0
10
Vds (V)
(a)
1.6
1.6
0.8
0.6
0.4
0.2
1.2
1.0
0.8
0.6
0.4
0.0
0
10
20
30
40
50 56
0
10
Vds (V)
(b)
1.6
0.8
0.6
1.0
0.2
0.0
0.2
0.0
20
30
Vds (V)
(c)
50 56
0.8
0.6
0.4
10
40
40
50 56
Vgsq=-3V
Vdsq=0V
Idsq=0mA
PD=0W
1.4
1.2
0.4
0
30
1.6
Ids (A)
1.0
20
Vds (V)
(e)
Vgsq=-3V
Vdsq=0V
Idsq=0mA
PD=0W
1.4
1.2
Ids (A)
50 56
0.2
0.0
Fig. 2-70
40
Vgsq=-1.4V
Vdsq=0V
Idsq=0mA
PD=0W
1.4
Ids (A)
Ids (A)
1.2
1.0
30
Vds (V)
(d)
Vgsq=-1.4V
Vdsq=0V
Idsq=0mA
PD=0W
1.4
20
0
10
20
30
40
50 56
Vds (V)
(f)
PIV for (a) {0V,0V} (b) {-1.4V,0V} (c) {-3V,0V} with no surface trapping
model and (d) {0V,0V} (e) {-1.4V,0V} (f) {-3V,0V} with surface trapping
model. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGDIV_MTTpaperbias_opt.dds/DISS2)
167
The efficacy of the substrate trapping modification is illustrated by comparing PIV
characteristics biased in the absence of self-heating at V p , but at different Vdsq .
Inspection of the PIV characteristics at {-3.0V,0V} (Fig. 2-70c), {-3.0V,14V} (Fig.
2-71a), at {-3.0V,28V} (Fig. 2-71b) and {-3.0V,56V} (Fig. 2-71c) show the expansive
region of validity using the substrate trapping model of (2-58)-(2-59).
The accurate simultaneous operation of surface trapping, substrate trapping and selfheating models is demonstrated by the PIV characteristics at quasi-isothermal quiescent
points of {-1.1V,14V} (Fig. 2-71d), {-1.7V,28V} (Fig. 2-71e) and {-2.1V,56V} (Fig.
2-71f). The effects of surface trapping and self-heating can be observed at Vdsq =14V,
28V and 56V using the three corresponding pairs of PIV characteristics at
{-3.0V,14V}/{-1.1V,14V}, {-3.0V,28V}/{-1.7V,28V} and {-3.0V,56V}/{-2.1V,56V}.
Additionally, select g ds -vs- Vds of the PIV characteristics at Vds =28V are also shown in
Fig. 2-72 to verify the model fidelity.
Re-evaluation of the self-heating model
With the surface trapping modification in place, it may be necessary to re-evaluate the
self-heating model. Since nonzero Vgsq also causes surface trapping, the differences
between the PGIV data shown in Fig. 2-56b, Fig. 2-56d, Fig. 2-56f cannot be attributed
solely to self-heating. The self-heating model defined by comparing PGIV at Vgsq > V p
versus PGIV at Vgsq = V p prior to the deembedding of surface trapping may have absorbed
the effect of the surface trapping.
168
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vgsq=-3V
Vdsq=14V
Idsq=0mA
PD=0W
0
10
20
30
40
Ids (A)
Ids (A)
GaN HEMT: Vgs=[-3:0.25:0]V, Vds=[0:2:56]V
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
50 56
Vgsq=-1.1V
Vdsq=14V
Idsq=1018mA
PD=14.25W
0
10
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vgsq=-3V
Vdsq=28V
Idsq=0mA
PD=0W
0
10
20
30
40
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
50 56
10
20
30
0
Fig. 2-71
40
50 56
Ids (A)
Ids (A)
Vds (V)
(c)
50 56
10
20
30
40
50 56
Vds (V)
(e)
Vgsq=-3V
Vdsq=56V
Idsq=0mA
PD=0W
0
40
Vgsq=-1.7V
Vdsq=28V
Idsq=508mA
Pdiss=14.23W
Vds (V)
(b)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
30
Vds (V)
(d)
Ids (A)
Ids (A)
Vds (V)
(a)
20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
Vgsq=-2.1V
Vdsq=56V
Idsq=248mA
Pdiss=13.91W
0
10
20
30
40
50 56
Vds (V)
(f)
PIV modeled and measured at (a) {-3V,14V} (b) {-3V, 28V} (c) {-3V,56V}
(d) {-1.1V,14V} (e) {-1.7V,28V} (f) {-2.1V,56V}. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGDIV_MTTpaperbias_opt.dds/DISS3)
169
GaN HEMT: Vds=[0:2:56]V
0.10
0.06
0.04
0.06
0.04
0.02
0.02
0.00
0.00
0
10
20
30
40
Vgsq=-1.7V, Vdsq=28V
Vgs=-0.75V
0.08
gds (A/V)
0.08
gds (A/V)
0.10
Vgsq=-3.0V, Vdsq=28V
Vgs=-0.75V
50 56
0
10
Vds (V)
(a)
0.10
0.10
0.04
0.02
50 56
0.06
0.04
0.02
0.00
0.00
0
10
20
30
40
50 56
0
10
Vds (V)
(b)
0.10
0.10
0.04
0.00
0.00
30
Vds (V)
(c)
50 56
0.04
0.02
20
40
0.06
0.02
10
30
40
50 56
Vgsq=-1.7V, Vdsq=28V
Vgs=-1.75V
0.08
gds (A/V)
0.06
0
20
Vds (V)
(e)
Vgsq=-3.0V, Vdsq=28V
Vgs=-1.75V
0.08
gds (A/V)
40
Vgsq=-1.7V, Vdsq=28V
Vgs=-1.25V
0.08
gds (A/V)
gds (A/V)
0.06
Fig. 2-72
30
Vds (V)
(d)
Vgsq=-3.0V, Vdsq=28V
Vgs=-1.25V
0.08
20
0
10
20
30
40
50 56
Vds (V)
(f)
Output conductance g ds -vs- Vds from PIV at (a)-(c) {-3.0V,28V} and at
(d)-(f) {-1.7V,28V} for Vgs = [-1.75:0.5:-0.75]V. (GaN)
(DISS_Tran_lsmodel_xtr09_IV_PGDIV_MTTpaperbias_opt.dds/DISS4)
170
As a consequence, the PGIV output of the large-signal model at Vgsq =-1.7V may
overpredict I ds after integrating the surface trapping model.
Compensation can be
performed by incrementally increasing the I ds degradation caused by the self-heating
model using optimization. In most cases, however, the degradation due to self-heating at
Vgsq =-1.7V is much more pronounced than surface trapping and the correction may be
ignored.
The PIV results of Fig. 2-70, Fig. 2-71, Fig. 2-72 represent the final,
compensated I ds model.
2.2.3.8.
Static IV Characterization
With the thermal and trapping models properly implemented, the complete I ds model
will also be able to predict traditional static IV behavior which exhibits the maximum
amount of current dispersion.
Each PGIV dataset contains a quiescent trace which
corresponds to one trace of the static IV characteristic. Therefore an I ds model valid
over PGIV at multiple Vgsq will have the capacity to accurately predict static IV
characteristics as well.
SiC MESFET
The measured and modeled static IV characteristics for the SiC MESFET are shown
in Fig. 2-73 and demonstrates good agreement up to ~40W of DC power.
171
SiC MESFET Static IV: Vgsq=[-11:0.5:2]V, Vdsq=[0:2:58]V
1.0
Idsq (A)
0.8
0.6
0.4
0.2
0.0
0
10
20
30
40
50
60
Vdsq (V)
Fig. 2-73
Static IV curves, measured (symbols) and modeled (solid). (SiC)
(DISS_Tran_ls_thermal_xtr3633_IV_PGIV_ultimate_static.dds)
GaN HEMT
The measured and modeled static IV characteristics for the GaN HEMT are shown in
Fig. 2-74.
For the high Vdsq range, the model demonstrates good agreement with
measured data up to ~33W of DC power. However, an anomaly can be observed at low
Vdsq in which I dsq abruptly increases around the knee region. This phenomenon is
referred to as the “kink effect” and also appears to a lesser degree in the PGIV curves of
Fig. 2-56b, Fig. 2-56d, Fig. 2-56f. However, it does not appear under PIV (Fig. 2-70,
Fig. 2-71, Fig. 2-72), thereby undermining its influence under microwave drive. The
kink effect is a function of trapping in the device [103][104][105]. Therefore, it is not
investigated since it may be irrelevant considering the pulsed characterization of trapping
already applied in this work [103][104].
172
GaN HEMT Static IV: Vgsq=[-2.5:0.1:1.9]V, Vdsq=[0:1:35]V
1.0
0.8
Ids (A)
0.6
0.4
0.2
0.0
0
10
20
30
40
50
60
Vds (V)
Fig. 2-74
Static IV curves, measured (symbols) and modeled (solid). (GaN)
(DISS_DC_lsmodel_IV_static.dds)
2.2.4. Diodes and Parasitic Resistances Using the Fukui Method
Extraction of parasitic resistances
The parasitics Rg , Rd and Rs arise due to the finite resistances between the
semiconductor active area and external device terminals. Although their exact locations
vary between FET devices, these parasitics represent the cumulative effect of the
resistances in the gate, drain and source contact regions, metal routing, bond pads, bond
wires, package pads and packaging terminals.
Parasitics Rg , Rd and Rs are not
attributed to the internal device mechanics and are therefore linear components.
Characterization of the parasitic resistances is vital since they affect all aspects of the
device performance under small- and large-signal excitation and over all frequencies
from DC to RF. Two methods of extracting Rg , Rd and Rs are pursued in this work: a
classical DC method using forward bias diode IV measurements [106], described in this
173
section, and an RF S-parameter method, described in Chapter 2.2.5.1.2. The results of
both methods serve as input to the final determined value.
Consider a static IV characteristic of a diode, D x , with equivalent series resistance,
R x , as shown in Fig. 2-75a. Assuming that D x and R x are not separable, a voltage Vx
applied across the network creates a current I x . At low Vx , I x is dominated by the
nonlinear characteristics of D x . At high Vx , the equivalent diode impedance resembles a
short and the gate current characteristic is dictated by R x .
Therefore, R x can be
extracted from the finite slope of the I x -vs- Vx characteristic at high Vx regardless of the
traits of D x .
The Schottky contact of the MESFET or HEMT device gives rise to a distributed
diode between the contact and active region of the device. This distributed diode region
is typically treated as two distinct diodes in the large-signal FET topology: a gate-source
diode, Dgs , and a gate-drain diode, D gd . The associated current paths can be activated
and deactivated based on the terminal configuration of the device, allowing for the
exploitation of specified diodes and resistances of interest.
The Fukui technique consists of measuring the DC forward bias gate current of the
FET device under three different terminal configurations with the following equivalences
to Fig. 2-75a:
1. Drain open, source short ( Vx ≡ Vg ,a , I x ≡ I g , a , R x ≡ Ra , D x ≡ Dgs )
2. Drain short, source open ( Vx ≡ Vg ,b , I x ≡ I g , b , R x ≡ Rb , D x ≡ D gd )
3. Drain short, source short ( Vx ≡ Vg ,c , I x ≡ I g , c , R x ≡ Rc , D x ≡ Dgs || D gd *)
174
(* Dgs and D gd can be treated as an equivalent diode as long as the thermal
voltages are the same, which is a fair assumption as shown in the ensuing
paragraphs and Appendix A.4)
The parasitic resistances can be extracted from the resulting IV characteristics. When
the drain is open and the source is shorted, the entire drain branch becomes open-circuit,
deactivating D gd as shown in Fig. 2-75b. Current flow arising from an applied Vg ,a will
enter into the gate, pass through Rg , Dgs and Rs and exit out of the source. Extraction
of the equivalent resistance from the measured IV slope will give the value of Ra .
Ra = R g + R s
(2-64)
Similarly, when the drain is short and the source is open, the source branch is
deactivated and the current path leads from gate to drain as shown in Fig. 2-75c.
Applying Vg ,b creates a current that passes from the gate to the drain through Rg , D gd
and Rs . The extraction of the equivalent resistance will give the value for Rb .
Rb = R g + Rd
(2-65)
Finally, when both the drain and source are shorted, both diode paths remain active as
shown in Fig. 2-75d. Application of Vg ,c creates current flow in both paths. Assuming
Dgs and D gd are equal and shorted, the equivalent resistance Rc can be found.
Rc = R g + Rd || Rs
(2-66)
With three equations and three unknowns, Rg , Rd and Rs using the following
relationships (See Appendix A.4 for derivation of formulas):
R s = Ra − R g
(2-67)
175
(2-68)
Rd = Rb − Rg
[
Rg = Rc − Ra Rb − Rc ( Ra + Rb ) + Rc
Fig. 2-75
1
2 2
]
(2-69)
Fukui measurement. (a) IV curve of diode and series R. DC FET models
with (b) drain-open/source-short (c) drain-short/source-open and (d) drainshort/source-short.
Extraction of diode parameters
The diodes Dgs and D gd have a large influence on the nonlinear behavior of the
device, especially under large-signal when Dgs may be driven into forward conduction,
creating nonzero gate current and clipping of the gate voltage waveform (this discussed
176
in Chapter 3). Conveniently, the model parameters of Dgs and D gd can be determined
using data obtained during the execution of the Fukui measurement.
The two diodes, Dgs and D gd , are each modeled using the Shockley ideal diode
formula as defined by Fig. 2-76:
I = I S (e V /( nVT ) − 1) ≈ I S eV /( nVT )
(2-70)
with the parameters of V gs , I S , gs and (nVT ) gs for Dgs and Vgd , I S , gd and (nVT ) gd for
D gd .
I = I S (eV /( nVT ) − 1)
Fig. 2-76
Shockley diode model.
Taking the ln (
)
on both sides of (2-70), the formula reduces to a form from which
I S and (nVT ) can be extracted
ln( I ) = ln( I S ) +
ln( I ) = A0 + VA1
V
nVT
(2-71)
(2-72)
As stated previously, the gate current of the circuit in Fig. 2-75a is dominated by the
exponential term of the diode at low applied voltage. Therefore, by performing a linear
fit to the ln( I ) -vs- V curve at low V , both A1 = 1 / nVT and A0 = ln( I S ) can be obtained.
The algorithm for the complete, computer-aided parameter extraction, optimization
and verification method is shown in Fig. 2-77. The first step consists of performing the
Fukui measurements to obtain the three I g -vs- V g curves. Parasitics R g , Rd and Rs are
177
extracted from these curves. At the same time, the diode parameters I S and nVT can be
extracted from the I g -vs- V g curves. This entire parameter set is collected and placed
through an optimizer which adjusts the parameter set until the simulated IV response
matches with the measured data.
Perform Fukui diode
measurements
Generate Ig-vs-Vg curves
from complete DC model
Ig
Extract Dgs, Dgd
parameters
Extract Ra, Rb, Rc
Vg
Compute Rg, Rd, Rs
Collect
Ig
Ig
Vg
Vg
Parameter Optimizer
Rg, Rd, Rs, Is,gs, (nVT)gs, Is,gd, (nVT)gd
Final parameter set
Fig. 2-77
Algorithm for the application of Fukui measurement.
178
SiC MESFET
The I g -vs- V g and ∂V g ∂I g -vs- V g curves for the SiC MESFET are shown in Fig.
2-78a and Fig. 2-78b, respectively. Resistances Ra , Rb and Rc are extracted from
flattest portion of Fig. 2-78b and tabulated in Table 2-21. The computed R g , Rd and Rs
are also tabulated in Table 2-21.
SiC MESFET Fukui
Ig (mA)
700
600
Ig,c
500
Ig,a
400
Ig,b
300
200
100
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
1.8
2.0
Vg (V)
3.0
2.5
dVg/dIg
2.0
Rb
1.5
Ra
Rc
1.0
0.5
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Vg (V)
Fig. 2-78
Extraction of Fukui resistances from measured data (a) I g -vs- V g and (b)
∂V g ∂I g -vs- V g . (SiC)
(DISS_DC_data_Fukui.dsn)
179
Table 2-21 Extracted Fukui R’s and computed parasitic R’s. (SiC)
Parameter
Extracted
Optimized
—
1.117 Ω
Ra
1.836 Ω
—
Rb
Rc
0.887 Ω
—
Rg
0.420 Ω
0.410464 Ω
Rd
1.417 Ω
1.33121 Ω
Rs
0.697 Ω
0.644433 Ω
The log plot of the Fukui gate currents are shown in Fig. 2-79 for I g , a , I g ,b and I g ,c .
A linear curve fit at low V g is performed to assist the diode parameter extraction.
ln(Ig ) - D open, S short
ln(Ig ) - D short, S open
ln(Ig ) - D short, S short
b
c
0
0
-2
-2
-2
-4
-4
-4
-6
-8
-10
ln(Igc )
0
ln(Igb)
ln(Iga)
a
-6
-8
0
0.5
1
1.5
Vg
a
Fig. 2-79
-10
-6
-8
0
0.5
1
1.5
-10
0
0.5
Vg
b
1
1.5
Vg
c
Extraction of diode parameters from I g , a , I g ,b and I g ,c . (SiC)
(diode_all_DISS.m)
The diode model parameters extracted from each of the curve and the equivalent Dgs
and D gd parameters are tabulated in Table 2-22.
180
Table 2-22 Extracted and optimized diode parameters (SiC)
Parameter
Equivalent
Extracted
Optimized
parameter
3.0169e-13 6.03374e-13
I S ,a
I S , gs
(nVT )a
(nVT )gs
0.0327
0.0334309
I S ,b
I S , gd
4.9735e-13
5.35565e-13
(nVT )b
(nVT )gd
0.0336
0.0332559
I S ,c
—
1.6922e-13
—
(nVT )c
—
0.0320
—
It is shown that the values for
(nVT )a
and
(nVT )b
are similar, validating the
assumption that the gate current I g ,c can be modeled using a single equivalent diode
formula.
The extracted diode and resistance parameters are further refined by optimization
such that I g , a and I g ,b match the measured data. Since the I g ,c is a composite of two
diode paths, ensuring its validity is a secondary criteria. The measured and simulated
curves after optimization are shown in Fig. 2-80 and the optimized parameter values are
provided in Table 2-22. The match for I g , a and I g ,b are very close and I g ,c still fits
reasonable well despite its exclusion from optimization.
181
SiC MESFET Fukui IV curves
700
Ig,c
600
Ig,a
Ig (mA)
500
400
Ig,b
300
200
100
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Vg (V)
Fig. 2-80
Fukui I g -vs- V g curves, measured and simulated. (SiC)
(DISS_DC_data_Fukui_3.dsn)
GaN HEMT
The forward bias I gs -vs- V gs and I gd -vs- V gd curves for the GaN HEMT are shown in
Fig. 2-81a and Fig. 2-81b, respectively. In the case of the GaN HEMT, Fukui-based
parasitic resistance extraction is not performed due to the limited gate current produced
under forward bias. In comparison to the SiC MESFET, the HEMT will have to be
biased much higher in order to achieve a current characteristic dominated by the parasitic
resistances. However, this is not performed to prevent overdriving the gate beyond the
maximum allowed voltage specified in the datasheet [79].
Instead the parasitic
resistances are determined using optimization after extraction of the diode parameters.
182
1.2
1.2
1.0
1.0
0.8
0.8
Igd (mA)
Igs (mA)
GaN HEMT: Diode characteristics Vgs=[0:0.05:1.5]V
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0.0
0.5
1.0
1.5
0.0
0.5
1.0
Vgs (V)
Vgd (V)
(a)
(b)
1.5
Forward bias gate current (a) I gs -vs- V gs and (b) I gd -vs- V gd . (GaN)
Fig. 2-81
(DISS_DC_equation_Igs_model_opt.dsn)
(DISS_DC_equation_Igd_model_opt.dsn)
The parameters of Dgs and D gd extracted from the log plot of I g , a and I g ,b ,
respectively are shown in Fig. 2-82 and tabulated in Table 2-23.
-5
-5
-10
-10
-15
-20
-25
-15
-20
0
0.5
1
Vga
Fig. 2-82
ln(Igb) - D short, S open
ln(Igb)
ln(Iga)
ln(Iga) - D open, S short
1.5
-25
0
0.5
1
Vgb
Extraction of diode parameters from I g , a and I g ,b . (GaN)
(diode_all_DISS.m)
1.5
183
Table 2-23
Parameter
I S ,a
Extracted and optimized diode parameters (GaN)
Equivalent
Extracted
Optimized
Parameter
2.4269e-016 2.67405e-8
I S , gs
(nVT )a
(nVT )gs
0.0360
0.140136
I S ,b
I S , gd
2.7087e-016
2.67405e-8
(nVT )b
(nVT )gd
0.0362
0.140351
To achieve a match of the DC diode characteristics of Fig. 2-81 using the Shockley
model, parasitic resistances are integrated in series with Dgs and D gd .
Since the
resistances are unobtainable using Fukui measurements, optimization under two
approximations is used instead:
R g ≈ R d and Rs ≈ 0 . The bonding from wafer to
package is similar at the input (gate) and output (drain) ports, justifying that R g ≈ R d .
The bonding of the source to package base plate is abundant to reduce parasitic
resistances such that Rs ≈ 0 . The values for I S , gs , (nVT ) gs , I S , gd (nVT ) gd optimized
under these assumptions are tabulated in Table 2-23. Note that they have changed
significantly once parasitic resistances are considered. The values for the parasitic R g ,
Rd and Rs determined during this DC optimization to satisfy I gs and I gd are provided in
Table 2-24. The modeled currents show a close match to measured data under these
assumptions as shown in Fig. 2-81.
184
Table 2-24 Parasitic R’s determined under DC optimization (GaN)
Parameter
Optimized
1.46 Ω
Rg
Rd
1.46097 Ω
Rs
0.0168449 Ω
2.2.5. Small-signal Model Identification
Accurate characterization of the frequency dependent elements is vital to the accuracy
of the large-signal model at RF. Determination of these elements has been founded using
S-parameter microwave characterization techniques assuming linear small-signal models
[107][108][109].
Therefore, generating accurate small-signal models is an essential
stepping stone in developing the large-signal model.
Cpgd
Gate
Lg
Cpg
Intrinsic FET
Rg
Cgd
+
vgs
- Cgs
Rds
Rd
Cds
ids
Rgs
Rs
Extrinsic FET
Ls
Source
Fig. 2-83
Small-signal model for FETs.
ids=gme-jωτvgs
Ld
Cpd
Drain
185
The complete, general small-signal model is shown in Fig. 2-83 and can be divided
into two major sections: an extrinsic and an intrinsic network. The extrinsic network
consists of the linear package capacitances ( C pg , C pd , C pgd ), inductances ( Lg , Ld , Ls ) and
resistances ( R g , Rd , Rs ) that do not vary with bias or drive level. The intrinsic network
consists of components in the interior of the device which may vary based on bias or
drive level. These include the capacitances C gs , C gd , C ds , resistance R gs , small-signal
current generator, ids , and output conductance, g ds . The small-signal current generator is
defined by a transconductance parameter, g m , where ids = g m e − jωτ vgs .
Since the extrinsic, package-related parasitics do not vary significantly based on drive
conditions, their values are common between large- and small-signal models can be
directly extracted using S-parameters.
However, the intrinsic network consists of linearized representations of their largesignal counterparts. Small-signal extraction of the intrinsic parameters gives rise to a
network which is only valid for a single operating point. Therefore, multiple S-parameter
datasets covering an expansive bias range are typically required to build a composite
representation of the nonlinear components.
Extraction of the network parameters is performed in a piecewise manner, under a
variety of different bias configurations. The three major types of parasitic extraction
techniques used in this work are:
1. Pinched FET S-parameters [107] - for extrinsic capacitance extraction
2. Cold FET S-parameters [108][109] - for extrinsic inductance and resistance
extraction
3. Hot FET S-parameters [108] – for intrinsic parameters
186
This section describes the extraction procedure and computer-aided algorithms to
improve accuracy and retain consistency with other parts of the model. Once determined,
the components will be integrated into the large-signal model.
In this work, the SiC MESFET S-parameters were measured on an HP 8510B VNA
from 0.1 to 4.0 GHz and the GaN MESFET S-parameters were measured on an Agilent
8364B PNA from 0.1 to 10.0 GHz. Both measurements setups employed a microstrip
thru-reflect-line (TRL) calibration for their respective frequency ranges (see Appendix
C.3 for more information on TRL calibration).
2.2.5.1.
Extrinsic FET Modeling
The algorithm for the extrinsic FET modeling, parameter extraction and optimization
routine is shown in Fig. 2-84.
Measured pinched FET
S-parameters
Measured cold FET Sparameters
Extract Cpg, Cpd, Cpgd,
Cgs, Cgd, Cds
Extract Lg, Ld, Ls
Cpg, Cpd, Cpgd
Cgs, Cgd, Cds
From Hower-Bechtel
Measure cold FET Sparameters
(various Vgs-Igs biases)
Measure pinched FET Sparameters
From Fukui
187
Extract Rg, Rd, Rs, Rch
Lg, Ld, Ls
Rg, Rd, Rs, Rch
Computed pinched
FET S-parameters
Initial parameter set
Lg, Ld, Ls, Rg, Rd, Rs
Cpg, Cpd, Cpgd, Cgs, Cgd, Cds
Measured pinched
FET S-parameters
Collect
Simulate Sparameters from
wideband pinched
FET model
Parameter Optimizer
Cpg, Cpd, Cpgd, Cgs, Cgd, Cds, Lg, Ld, Ls, Rg, Rd, Rs
Final parameter set
Fig. 2-84
Algorithm for determining extrinsic FET parameters.
2.2.5.1.1. Pinched-FET S-parameters for Extrinsic C’s
The extrinsic parasitic capacitances can be extracted from S-parameters measured
under pinched-FET operation in which the drain-source is biased at zero and the gatesource is biased at pinchoff (Pinched FET: { Vgs = V p , Vds =0V}) [107]. Under this
condition, the channel is completely off ( g m =0) and the effect of the parasitic R ’s and
L ’s become negligible to that of the parasitic C ’s. The complete small-signal model
reduces to a pinched-FET model as shown in Fig. 2-85 [107] consisting of the package
188
parasitics C pg , C pd , C pgd and the intrinsic capacitances C gs , C gd and C ds .
This
representation is modified from [107] to connect the elements of this model to those of
the complete topology.
Cpgd
Gate
Drain
Cgd
Cds
Cgs
Cpg
Cpd
Source
(a)
I1
I2
Cf
+
V1
C1
C2
-
+
C1=Cpg+Cgs
V2
C2=Cpd+Cds
-
Cf=Cpgd+Cgd
(b)
Fig. 2-85
(a) Pinched-FET model (b) equivalent pinched-FET model.
The Y-parameters of the equivalent pinched-FET model of Fig. 2-85b (see Appendix
A.5 for derivation) are
Y11 = jω (C1 + C f )
(2-73)
Y12 = Y21 = − jωC f
(2-74)
Y22 = jω (C 2 + C f )
(2-75)
189
Note that Y12 = Y21 since the device is assumed to be symmetric under pinched-FET.
Plugging back the actual capacitances gives
Y11 = jω (C pg + C pgd + C gs + C gd )
(2-76)
Y12 = Y21 = − jω (C pgd + C gd )
(2-77)
Y22 = jω (C pd + C pgd + C ds + C gd )
(2-78)
Several assumptions are made to extract of the parasitic capacitances from the measured
Y-parameters:
Assumption 1: C pgd =0
The gate-drain package parasitic is usually very small and much smaller than the
gate-drain junction capacitance. Therefore it can be approximated to zero.
Assumption 2: C gs = C gd
Under pinchoff bias and Vds =0V, the gate-source and gate-drain capacitances are
approximately the same since the terminal biases are the same and they somewhat share
the same physical mechanism.
Assumption 3: C pd = C pg
The input and output terminal of the packaged device are the gate and drain terminals,
respectively. Therefore, the capacitance due to the periphery of the bonding contact at
the package terminals are approximately the same between the input and output ports for
these devices [78][79].
Under these assumptions, the capacitances become
190
(2-79)
C pgd ≈ 0
C gd ≈ −
C pg ≈
Cds ≈
Im{Y12 }
(2-80)
ω
Im{Y11}
ω
Im{Y22 }
ω
− 2C gd
(2-81)
− C pg − C gd
(2-82)
According to (2-80)-(2-82), the capacitances can be found by performing a linear
approximation of the measured Y-parameter data at low frequency and taking the slope to
compute the capacitances.
SiC MESFET
The Y-parameters of the pinched-FET SiC MESFET are shown in Fig. 2-86 and the
extracted capacitance values are tabulated in Table 2-25.
The Y-parameters are
interpolated using a straight line up to about 1GHz. Beyond 1GHz, the approximation
using the pinched-FET network begins to diverge from the measured data.
191
SiC MESFET: Vgsq=-10V, Vdsq=0V
0.1
Im{Y12}
Im{Y11}
0.1
0.0
-0.1
0.0
-0.1
0.0
0.5
1.0
1.5
2.0
0.0
0.5
freq, GHz
2.0
1.5
2.0
0.1
Im{Y22}
Im{Y21}
1.5
freq, GHz
0.1
0.0
-0.1
0.0
-0.1
0.0
0.5
1.0
1.5
2.0
0.0
freq, GHz
Fig. 2-86
1.0
0.5
1.0
freq, GHz
Pinched FET Im{Y } -parameters. (SiC)
(pinched_DISS.m) (DISS_S_extract_pinched.dsn)
Table 2-25 Extracted parasitic capacitances (SiC)
Parameter
Extracted
0 pF
C pgd
C pg , C pd
1.0066 pF
C gd , C gs
1.8860 pF
Cds
1.1335 pF
GaN HEMT
The Y-parameters of the pinched-FET GaN HEMT are shown in Fig. 2-87 and the
extracted capacitance values are tabulated in Table 2-26. Like the SiC MESFET, the
GaN HEMT Y-parameters are interpolated using a straight line up to about 1GHz.
192
GaN HEMT: Vgsq=-3V, Vdsq=0V
0.1
Im{Y12}
Im{Y11}
0.1
0.0
-0.1
0.0
-0.1
0
1
2
0
freq, GHz
0.1
Im{Y22}
Im{Y21}
2
freq, GHz
0.1
0.0
-0.1
0.0
-0.1
0
1
2
freq, GHz
Fig. 2-87
1
Pinched-FET Im{Y } -parameters. (GaN)
(DISS_S_extract_pinched_MTT.dsn)
Table 2-26 Extracted parasitic capacitances (GaN)
Parameter
Extracted
0 pF
C pgd
C pg , C pd
0.651 pF
C gd , C gs
1.79198 pF
Cds
0.80411 pF
0
1
freq, GHz
2
193
2.2.5.1.2. Cold-FET S-parameters and Hower-Bechtel for Extrinsic L’s and R’s
The extrinsic inductances and resistances can be extracted using cold-FET Sparameter measurements [108][109]. Cold-FET biasing condition is achieved when the
drain-source is biased to 0V and the gate-source is biased into forward conduction, such
that I g >0. (Cold FET: { Vgs > V f , Vds =0V }). Under the cold-FET condition, the
depletion region is minimized but there is no drain current ( g m =0 A/V) since Vds =0V.
Therefore, the device behavior is largely dominated by the resistors and inductors, and
unaffected by the capacitances. The channel exhibits a resistor-like behavior and the
device can be modeled using a distributed channel representation as shown in Fig. 2-88.
Fig. 2-88
Cold-FET circuit model [108].
As described in [108] and [110], the distributed model for the forward conduction
gate diode is represented by the elemental ∆Rdy and ∆C dy elements. The channel is
represented by the distributed ∆Rch elements.
194
The Z-parameters of the cold-FET small signal model are (see Appendix A.6 for
analysis):
Z11 = Rs + Rg +
Rch nkT
+
+ jω ( Ls + Lg )
qI g
3
Z 12 = Z 21 = Rs +
Rch
+ jω L s
2
Z 22 = Rs + Rd + Rch + jω ( Ls + Ld )
(2-83)
(2-84)
(2-85)
Based on the above equations, the extrinsic parasitic inductances Lg , Ls and Ld can
be extracted from the following expressions
Lg =
Ls =
Ld =
Im{Z11}
ω
(2-86)
− Ls
Im{Z12 }
(2-87)
ω
Im{Z 22 }
ω
(2-88)
− Ls
Additionally, using the extrapolation technique described in [108], the parasitic
resistances can be represented using the following equations
Re{Z11 } ≈ R s + R g +
Rch
3
(2-89)
Re{Z12 } = R s +
Rch
2
(2-90)
Re{Z 21 } = R s +
Rch
2
(2-91)
Re{Z 22 } = Rs + Rd + Rch
(2-92)
As pointed out by [108], examining these equations shows that there exists three
equations for four unknowns. Therefore, a fourth equation is needed to compute all four
195
resistances. Once possibility is the use of Fukui DC measurements, as described in
Chapter 2.2.4 to satisfy this requirement. Another option is the use of extrapolation to
eliminate the channel resistance term as described in [109].
The Hower-Bechtel method [109] provides a fourth equation to be used in companion
with (2-89)-(2-92) for approximating the parasitic resistances under zero volt drain and
source bias operation { Vd =0V, Vs =0V}. The concept behind [109] is to reduce (2-92)
into a form which approximates Rs + Rd by eliminating the channel resistance term, Rch .
From [109] and [111], the channel resistance can be approximated as a function of
gate bias (Note that the [109] uses a positive pinchoff value while [111] uses the actual
negative pinchoff voltage. The formula presented here follows [111] but the technique is
the same). The channel resistance is given by
Rch 0
Rch =
1−
VGS − Vbi
Vp
(2-93)
where Rch 0 is the minimum channel resistance, Vbi is the built-in voltage of the gate
diode and V p is the pinchoff voltage of the FET device and VGS is the gate-source bias.
Substituting into (2-92) results in
Re{Z 22 } = Rs + Rd +
Rch0
V − Vbi
1 − GS
Vp
(2-94)
In order to isolate Rs + Rd , the channel resistance term needs to be eliminated.
However since the minimum value of Rch = Rch 0 (at VGS = Vbi ), it is not possible to zero it
out. Instead the Rch term can be eliminated by mathematically forcing it to zero through
196
extrapolation. Linear extrapolation provides the most straightforward analysis, therefore
although (2-94) is a nonlinear function, it can be made to resemble a linear curve where
Re{Z 22 } = Rs + Rd + Rch0 x = A0 + A1 x , where x =
1
V − Vbi
1 − GS
Vp
(2-95)
Once the entire equation ( Rs + Rd + Rch 0 x ) is assumed to be a linear function, it can be
extrapolated to provide a response beyond physically measurable data, such that x goes
to zero, revealing approximations for Rs + Rd .
The procedure for applying Hower-Bechtel is to
1. Find the built-in potential Vbi through forward conduction gate measurements.
2. Measure the Vd = Vs =0V S-parameters over varying gate biases to obtain Z 22 .
3. Plot the Hower-Bechtel model response and data Re{Z 22 } as a function of x .
4. Extrapolate the fit down to x =0 to obtain Rs + Rd value (plot the data along
with it to verify the validity).
The algorithm for computer-aided determination of the parasitic L g , Ls and Ld are
shown in Fig. 2-84.
SiC MESFET
The cold-FET extraction was performed on the SiC MESFET device.
The
Im{Z } -parameters are shown in Fig. 2-89 as a function of frequency. A linear curve fit is
applied to the low frequency (< 1 GHz) portions of the curves to compute values for L g ,
197
Ld and Ls using (2-86)-(2-88). The extracted inductance values are tabulated in Table
2-27.
SiC MESFET: Vgsq=1.2V, Vdsq=0V
10
1.0
Im{Z12}
Im{Z11}
8
6
4
0.5
2
0
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
10
0.8
8
0.6
0.4
0.2
2.0
1.5
2.0
6
4
2
0.0
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
freq, GHz
Fig. 2-89
1.5
freq, GHz
Im{Z22}
Im{Z21}
freq, GHz
1.0
1.0
freq, GHz
Cold-FET Z-parameters for L extraction. (SiC)
(DISS_S_extract_cold.dsn) (also cold_DISS.m)
Table 2-27 Extracted parasitic inductances using cold-FET (SiC)
Parameter
Value
0.56757 nH
Lg
Ld
0.48097 nH
Ls
0.044738 nH
198
One of the assumptions required for reducing (2-83) into (2-89) is that I g is large
such that the diode resistance goes to zero. Cold-FET measurements for several I g
values were taken so that an extrapolation technique can be applied to simulate the effect
of 1 / I g 0. The Re{Z }-parameters are plotted versus 1 / I g as shown in Fig. 2-90. The
data points are then interpolated and extrapolated to obtain Re{Z } at 1 / I g 0.
As seen from Fig. 2-90, Re{Z11 } is the only parameter which exhibits a significant
dependence on I g , which is consistent with (2-83). The Re{Z12 } , Re{Z 21 }, Re{Z 22 } are
fairly insensitive to I g . Nevertheless, all of the Re{Z } values are taken at 1 / I g 0 to
retain a good consistency between values. The extracted values are highlighted on Fig.
2-90.
199
2
Re(Z12) (Ω )
Re(Z11) (Ω )
3
2
1
1.4292
0
0
5
10
1.5
1
0.5
0.86278
15
0
20
0
5
-1
1.5
3
Re(Z22) (Ω )
Re(Z21) (Ω )
4
1
0.85886
0
5
10
15
20
15
20
2
2.9806
1
0
-1
0
5
10
-1
1/Igs (A )
Fig. 2-90
20
1/Igs (A )
2
0
15
-1
1/Igs (A )
0.5
10
1/Igs (A )
Extraction of parasitic R ’s using cold-FET [108]. (SiC)
(dambrine_parasitic_R_extrapolation_DISS.m)
The Hower-Bechtel technique is performed on the SiC MESFET to assist the
resistance extraction process.
First, the built-in potential Vbi is obtained through
I gs -vs- V gs measurements as shown in Fig. 2-91a by extrapolating the linear portion of
the curve to obtain the V gs -intercept point. Then, Re{Z 22 } -vs- x from (2-95) is obtained
from the available cold-FET datasets and plotted in Fig. 2-91b. A pinchoff value of
V p =-10V, gives a fairly linear response.
200
Igs vs Vgs, Vbi=0.8741V
Re(Z22) vs x, Rs+Rd=1.885
14
0.7
12
0.6
10
Re(Z22)
Igs
0.5
0.4
0.3
0.2
6
4
0.1
Vbi
2
0
-0.1
8
0
0.5
1
1.5
Vgs
Fig. 2-91
0
Rs+Rd
0
2
4
6
8
10
x
Hower-Bechtel technique with (a) extraction of the built-in potential Vbi (b)
extrapolation of Re{Z 22 } to extract Rs + Rd . (SiC)
(hower_bechtel_DISS.m)
Extrapolation of the Re{Z 22 } -vs- x curve results in a value of 1.88492 Ω . At this
point, there are four equations for four unknowns
Rs + Rg +
Rs +
Rch
= 1.429204 Ω
3
Rch
= 0.8588580 Ω
2
(2-96)
(2-97)
Rs + Rd + Rch = 2.980559 Ω
(2-98)
Rs + Rd = 1.88492 Ω
(2-99)
Solving the four equations gives the R g , Rd , Rs and Rch values shown in Table
2-28.
201
Table 2-28 Extracted parasitic resistances using cold-FET (SiC)
Parameter
Value
0.752949
Ω
Rg
Rd
1.57388 Ω
Rs
0.311038 Ω
Rch
1.09564 Ω
GaN HEMT
A cold-FET S-parameter measurement was performed on the GaN HEMT at a single
bias of {-1.2V,0V}. The resulting Im{Z } -vs-frequency are shown in Fig. 2-92. A linear
curve fit is performed on each Im{Z } -parameter to allow computation of L g , Ld and Ls
using (2-86)-(2-88). For Im{Z 12 } , Im{Z 12 } and Im{Z 12 } , the linear fit performs well,
even up to 3GHz. However, some sort of measurement error appears in Im{Z 11 } and a
clean linear fit cannot be obtained. Instead, a value is approximated as shown in Fig.
2-92. The wideband pinched-FET comparisons of Chapter 2.2.5.1.3 will validate this
approximation. The extracted inductance values are tabulated in Table 2-29.
202
20
1.0
10
0.5
Im{Z12}
Im{Z11}
GaN HEMT: Vgsq=1.2V, Vdsq=0V
0
0.0
-10
-0.5
-20
-1.0
0
1
2
3
4
0
1
1.0
20
0.5
10
0.0
-0.5
4
3
4
0
-10
-1.0
-20
0
1
2
3
4
0
1
freq, GHz
Fig. 2-92
3
freq, GHz
Im{Z22}
Im{Z21}
freq, GHz
2
2
freq, GHz
Cold-FET Z-parameters for L extraction. (GaN)
(cold_DISS.m) (DISS_S_extract_cold_MTT.dsn)
Table 2-29 Extracted parasitic inductances using cold-FET (GaN)
Parameter
Value
0.54757
nH
Lg
Ld
0.67000 nH
Ls
0.03030 nH
For the GaN HEMT, the Hower-Bechtel method was not used to solve for the
parasitic resistances.
Instead, the resistances are approximated from the cold-FET
Re{Z }-parameters under assumption that Rch is near 0. Under cold-FET bias, Vgs is
203
positive and the channel will be completely undepleted. Therefore Rch will be at its
minimum resistance. As a result, (2-89)-(2-92) reduces to three equations and three
unknowns. The Re{Z }-parameters are plotted in Fig. 2-93 illustrating the constant value
resistance approximations made under the Rch ~0 assumption.
Unlike the SiC case,
multiple cold-FET S-parameters were not available for the GaN HEMT. Therefore the
extrapolation of Re{Z } under 1 / I g 0 was not performed. From the plot, it can be
observed that Re{Z11 }, Re{Z12 } and Re{Z 21 } are relatively flat versus frequency, which
is representative of a resistance. However, Re{Z 22 } exhibits some ripple which is most
likely due to measurement error. The computed resistances are tabulated in Table 2-30.
204
GaN HEMT: Vgsq=1.2V, Vdsq=0V
5
1.0
Re{Z12}
Re{Z11}
4
3
2
Rs if Rch~0
0.5
1
Rs+Rg if Rch~0
0
0
1
2
3
0.0
4
0
1
freq, GHz
2
3
4
freq, GHz
1.0
2.0
Re{Z22}
Re{Z21}
1.5
Rs if Rch~0
0.5
1.0
0.5
Rs+Rd if Rch~0
0.0
0.0
0
1
2
3
4
freq, GHz
Fig. 2-93
0
1
2
3
freq, GHz
Extraction of parasitic R ’s using the real part of the cold-FET Zparameters. (GaN)
(DISS_S_extract_cold_MTT.m)
Table 2-30 Extracted parasitic resistances using cold-FET (GaN)
Parameter
Value
0.59175
Ω
Rg
Rd
0.5602 Ω
Rs
0.3664 Ω
Rch
0.01 Ω
4
205
Although this method is less accurate, it provides reasonable initial values for R g , Rd
and Rs which can be refined using the wideband pinched-/cold-FET optimization
technique described next.
2.2.5.1.3. Wideband Pinched-FET S-parameters
An enhanced, wideband pinched-FET model is simulated to refine the parameters
extracted from pinched-FET and cold-FET measurements.
The initial pinched-FET
model of Fig. 2-85 ignores all parasitic R ’s and L ’s, solely exploiting the parasitic C ’s.
However, this simplified, band-limited pinched-FET model is valid only up to ~1GHz as
shown in Fig. 2-86 and Fig. 2-87. Increasing the model’s validity over the entire band
requires the re-integration of the parasitics L ’s and R ’s extracted from cold-FET
measurements as shown in Fig. 2-94. The enhanced model can then be evaluated against
pinched-FET data to obtain an improved match over all frequencies.
206
Fig. 2-94
Wideband pinched-FET small-signal model.
Verification with Y- and Z-parameters is a useful step in the initial parameter
extraction phase. Ultimately, though, an accurate S-parameter match over the frequency
band of interest is sought. This requires that the parameter tuning and optimization be
performed under the observation of S-parameters.
SiC MESFET
The wideband pinched-FET S-parameters for the SiC MESFET are shown in Fig.
2-95. The plot shows that the S-parameters match fairly well over the 0.1 to 4GHz band
range.
207
S(1,2)
S(1,1)
SiC MESFET: Vgsq=-10.0V
freq (100.0MHz to 4.000GHz)
Fig. 2-95
freq (100.0MHz to 4.000GHz)
S(2,2)
S(2,1)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
Wideband pinched-FET model for parameter verification and tuning. (SiC)
(DISS_S_extract_pinched_cold.dsn)
The measured, unoptimized and optimized Y-parameters over the entire band range
are shown in Fig. 2-96 to further illustrate the improvement achieved after tuning the
wideband pinched-FET model.
Whereas the basic pinched-FET model can only reproduce the Y-parameters at low
frequency, the wideband pinched-FET model can now predict the high frequency
behavior which is influenced by the interaction between parasitic C ’s, L ’s and R ’s.
208
SiC MESFET: Vgsq=-10.0V
0.6
0.4
Im{Y11}
Re{Y11}
0.2
0.4
Measured
Extracted
Optimized
0.2
0.0
Measured
Extracted
Optimized
-0.2
0.0
-0.4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
f req, GHz
2.0
2.5
3.0
3.5
4.0
f req, GHz
0.0
0.4
Im{Y12}
Re{Y12}
0.2
-0.2
Measured
Extracted
Optimized
-0.4
0.0
Measured
Extracted
Optimized
-0.2
-0.6
-0.4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
f req, GHz
2.5
3.0
3.5
4.0
3.0
3.5
4.0
f req, GHz
0.0
0.4
-0.4
Im{Y21}
Re{Y21}
0.2
-0.2
Measured
Extracted
Optimized
0.0
Measured
Extracted
Optimized
-0.2
-0.6
-0.4
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
f req, GHz
1.5
2.0
2.5
f req, GHz
0.6
0.4
0.2
0.0
Im{Y22}
Re{Y22}
0.2
0.4
Measured
Extracted
Optimized
0.0
0.5
1.0
-0.2
-0.4
1.5
2.0
2.5
3.0
3.5
4.0
f req, GHz
Fig. 2-96
0.0
Measured
Extracted
Optimized
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
f req, GHz
Comparison of Y-parameters for the wideband pinched-FET model. (SiC)
(DISS_S_extract_pinched_cold.dsn)
The extracted and optimized values for C pgd , C pg , C pd , C gs , C gd , C ds , L g , Ld , Ls ,
R g , Rd and Rs used to achieve this fit are provided in Table 2-31.
209
Table 2-31 Extracted and optimized parasitics using wideband pinched-FET (SiC)
Parameter
Extracted Value
Optimized Value
0
pF
0 pF
C pgd
C pg
1.0066 pF
0.76778 pF
C pd
1.0066 pF
0.76778 pF
C gs
1.8860 pF
1.5088 pF
C gd
1.8860 pF
1.5088 pF
Cds
1.1335 pF
1.7003 pF
Lg
0.56757 nH
0.73784 nH
Ld
0.48097 nH
0.67336 nH
Ls
0.044738 nH
0.044700 nH
Rg
0.752949 Ω
0.5978 Ω
Rd
1.57388 Ω
0.94375 Ω
Rs
0.311038 Ω
0.9842 Ω
GaN HEMT
The wideband pinched-FET S-parameters for the GaN HEMT are shown in Fig. 2-97.
The plot shows that the S-parameters match fairly well over the 0.1 to 12 GHz band
range.
The measured and simulated Y-parameters over the 0.1 to 12 GHz band range are
shown in Fig. 2-98 and show an excellent match after optimizing the linear elements
under wideband pinched-FET model S-parameters.
The extracted and optimized C pgd , C pg , C pd , C gs , C gd , Cds , L g , Ld , Ls , R g , Rd
and Rs for the GaN HEMT are provided in Table 2-32.
210
S11
S12
GaN HEMT: Pinched-/cold-FET model Vgsq=-3V, Vdsq=0V
freq (100.0MHz to 12.00GHz)
S21
S22
freq (100.0MHz to 12.00GHz)
freq (100.0MHz to 12.00GHz)
Fig. 2-97
freq (100.0MHz to 12.00GHz)
Wideband pinched-FET model for parameter verification and tuning. (GaN)
(DISS_S_extract_pinched_cold_opt_MTT.dsn)
211
0.8
0.6
0.6
0.4
Im{Y11}
Re{Y11}
GaN HEMT: Pinched-/cold-FET model Vgsq=-3V, Vdsq=0V
0.4
0.2
0.0
0.2
0.0
-0.2
-0.2
-0.4
0
2
4
6
8
10
12
0
2
4
f req, GHz
12
8
10
12
8
10
12
8
10
12
0.4
Im{Y12}
Re{Y12}
10
0.6
0.5
0.0
-0.5
0.2
0.0
-0.2
-1.0
-0.4
0
2
4
6
8
10
12
0
2
4
f req, GHz
6
f req, GHz
1.0
0.6
0.4
Im{Y21}
0.5
Re{Y21}
8
f req, GHz
1.0
0.0
-0.5
0.2
0.0
-0.2
-1.0
-0.4
0
2
4
6
8
10
12
0
2
4
f req, GHz
6
f req, GHz
1.2
0.6
1.0
0.4
Im{Y22}
0.8
Re{Y22}
6
0.6
0.4
0.2
0.2
0.0
-0.2
-0.4
0.0
-0.2
-0.6
0
2
4
6
8
10
12
0
f req, GHz
Fig. 2-98
2
4
6
f req, GHz
Comparison of Y-parameters for the wideband pinched-FET model. (GaN)
(DISS_S_extract_pinched_cold_opt_MTT.dsn)
212
Table 2-32 Extracted and optimized parasitics using wideband pinched-FET (GaN)
Parameter
Extracted Value
Optimized Value
0
pF
0 pF
C pgd
2.2.5.2.
C pg
0.651 pF
0.650545 pF
C pd
0.651 pF
0.650545 pF
C gs
1.79198 pF
1.6956 pF
C gd
1.79198 pF
1.6956 pF
Cds
0.80411 pF
0.858255 pF
Lg
0.54757 nH
0.577785 nH
Ld
0.67000 nH
0.558421 nH
Ls
0.03030 nH
2.56579e-12 nH
Rg
0.59175 Ω
0.974681 Ω
Rd
0.5602 Ω
0.650339 Ω
Rs
0.3664 Ω
1.9677e-5 Ω
Intrinsic FET Modeling Using Hot-FET S-parameters
2.2.5.2.1. Hot-FET S-parameters
With the extrinsic parameters extraction complete, the intrinsic FET parameters can
be extracted using “hot” FET S-parameters which are taken with the device biased in its
active region. The transistor is “hot” because it is conducting current and dissipating DC
power, resulting in a literal increase in device temperature.
Hot-FET operation is the standard mode in which active devices are biased to
produce small-signal gain at microwave frequencies. However, for any FET device,
there exist many possible active region operating points and corresponding S-parameter
datasets. Each hot-FET S-parameter dataset has a unique solution to the equivalent
intrinsic network since the nonlinear components such as C gs , C gd , C ds , g ds and g m can
be linearized at a given bias. In order to characterize the small-signal behavior over the
213
entire bias range of the nonlinear FET device, a comprehensive characterization requiring
many hot-FET measurements is required.
The hot-FET small-signal model comprises the complete small-signal FET model
shown in Fig. 2-83. Assuming that this model is valid for any hot-FET S-parameter
dataset, the intrinsic parameters C gs , C gd , C ds , g ds , g m , τ and Rgs can be extracted
provided that the extrinsic parasitic elements have been previously determined (using
pinched-/cold-FET techniques). The effect of the extrinsic parasitics can be stripped
away from the terminal-measured hot-FET S-parameters, leaving behind a dataset
representative of the intrinsic network only. From this intrinsic S-parameter dataset, the
intrinsic network values can be extracted.
The small-signal network reduction process is illustrated in Fig. 2-99 and is derived in
Appendix A.7.
214
Cpgd
Lg
Rg
Rd
Intrinsic
FET
Cpg
Ld
Cpd
 S11
S
 21
S12 
S 22 
Rs
Ls
Lg
Rg
S ⇒Y
Rd
Intrinsic
FET
Ld
Y12 + jωC pgd
Y11 − jω (C pg + C pgd )

= Y'

Y21 + jωC pgd
Y22 − jω (C pd + C pgd )

Rs
Ls
Y '⇒ Z'
Z12 '−( Rs + jωLs )
 Z11'−( Rg + Rs + jω ( Lg + Ls ))

= Z"

Z 21'−( Rs + jωLs )
Z 22 '−( Rd + Rs + jω ( Ld + Ls )) 

Intrinsic
FET
Z "⇒ Y "
Intrinsic FET
Cgd
Rds
Cgs
ids
Cds
Y11" Y12 "
Y " Y "
 21
22 
Rgs
Fig. 2-99
Reduction of complete small-signal network into intrinsic FET network.
First, the measured S-matrix of the device, S , is convert into a Y-matrix.
S ⇒Y
(2-100)
Then the admittances of the package capacitances are subtracted
Y12 + jωC pgd
Y11 − jω (C pg + C pgd )

=Y'
 Y + jω C
Y22 − jω (C pd + C pgd )
21
pgd

Following that, the Y-matrix is converted into a Z-matrix
(2-101)
215
(2-102)
Y '⇒ Z '
from which the impedances of the parasitic resistances and inductances are subtracted
Z12 '− ( Rs + jωLs )
 Z11 '−( Rg + Rs + jω ( Lg + Ls ))

= Z"

Z 21 '−( Rs + jωLs )
Z 22 '− ( Rd + Rs + jω ( Ld + Ls ))

(2-103)
Finally, the remaining Z-matrix is converted back into a Y-matrix
(2-104)
Z "⇒ Y "
Analyzing the intrinsic circuit network, the Y-parameters of the network can be
formulated
Y11 " =
1
+ jωC gd
Rgs + 1 / jωC gs
(2-105)
(2-106)
Y12 " = − jωC gd
Y21 " =
g m exp( − jωτ )
− jωC gd
1 + jωR gs C gs
(2-107)
Y22 " =
1
+ jω (C gd + C ds )
Rds
(2-108)
From these equations, the intrinsic parameter values can be computed
C gd = −
C ds =
C gs ≅
Im{Y12 "}
ω
Im{Y22 "}
ω
Im{Y11 "}
ω
− C gd
− C gd
g m ≅ Re{Y21"}
Rds =
1
1
=
Re{Y22 "} g ds
(2-109)
(2-110)
(2-111)
(2-112)
(2-113)
216
2
Rgs =
τ ≅−
4(Re{Y11"})
1± 1−
ω 2C gs 2
2 Re{Y11"}
 Im{Y21"} − Im{Y12 "} 

tan −1 
ω
Re{Y21"}


1
(2-114)
(2-115)
Since the extrinsic elements do not change, this process can be repeated for any hotFET S-parameter dataset.
2.2.5.2.2. Nonlinear Capacitance Models
Under large-signal, the intrinsic capacitors C gs , C gd and C ds behave nonlinearly
since they represent the charge displacement of the depletion region in the FET. The
applied voltages alter the shape of this space-charge region, thereby changing the
effective capacitance values.
The nonlinear C gs , C gd and C ds strongly influence the large-signal RF input and
output behavior.
Therefore, properly characterizing and modeling their bias
dependencies are important.
The characterization method applied here consists of
extracting capacitances using hot-FET extraction over a wide range of biases.
The
composite bias-dependent capacitances can then be modeled using a nonlinear
capacitance equation. Some of the major capacitance models that have been developed
are found in [83][86] and [91].
In this work, the nonlinear capacitance equations used to model C gs , C gd and C ds are
[91]:
C gs = C gsp + C gs 0 (1 + tanh( P20 gs + P21 gsVds ) )(1 + tanh( P10 gs + P11gsVgs ) )
(2-116)
217
C gd = C gdp + C gd 0 (1 + tanh( P20 gd + P21 gdVds ) )(1 + tanh( P10 gd + P11gdVgd ) )
(2-117)
C ds = C dsp + C ds 0 (1 + tanh( P20 ds + P21dsVgs ))(1 + tanh( P10 ds + P11dsVds ) )
(2-118)
The capacitance models are implemented in the form of charge equations in Agilent
ADS [91]
Qgs = ∫ C gs (Vgs ,Vds )dVgs
(2-119)
Qgs = C gspVgs + C gs 0 (Vgs + Lcgs + VgsThgs + LcgsThgs )
(2-120)
Lcgs = (log (cosh( P10 gs + P11 gsVgs ) )) / P11 gs
(2-121)
Thgs = tanh( P20 gs + P21 gsVds )
(2-122)
Q gd = ∫ C gd (Vgd ,Vds )dV gd
(2-123)
Qgd = C gdpVgd + C gd 0 (Vgd + Lcgd + Vgd Thgd + LcgdThgd )
(2-124)
Lcgd = (log (cosh( P10 gd + P11gdVgd ))) / P11 gd
(2-125)
Thgd = tanh( P20 gd + P21gdVds )
(2-126)
Qds = ∫ C ds (Vds ,Vgs )dVds
(2-127)
Qds = C dspVds + C ds 0 (Vds + Lcds + Vds Thds + LcdsThds )
(2-128)
Lcds = (log(cosh( P10 ds + P11dsVds ))) / P11ds
(2-129)
Thds = tanh( P20 ds + P21dsV gs )
(2-130)
In most cases C ds is weakly nonlinear and can be represented using a linear capacitor
instead of with (2-118).
218
2.2.5.2.3. Extraction of Intrinsic FET and Capacitance Model Parameters
The hot-FET extraction algorithm is shown in Fig. 2-100 and consists of an
S-parameter measurement, a reduction into the intrinsic S-parameter set, followed by a
graphical extraction of the intrinsic parameters. The entire process is represented by a
single hot-FET extraction block shown in Fig. 2-100.
Intrinsic FET
Y-matrix
Fig. 2-100
Cgs1, Cgd1, Cds1
Rgs1, gm1, Rds1
(Hot S-data)1
Manually Extract Cgs,
Cgd, Cds, Rgs, gm, Rds
Cpg, Cpd, Cpgd
Lg, Ld, Ls, Rg, Rd, Rs
Hot FET
extraction
{Vgs,Vds}n
Cgs1, Cgd1, Cds1
Rgs1, g m1, Rds1
Convert S matrix/subtract
extrinsic parameters
(Hot S-data)1
Measure hot FET Sparameters
From pinched-/coldFET extraction
Cpg, Cpd, Cpgd
Bias {Vgs,Vds}n
Lg, Ld, Ls, Rg, Rd, Rs
From pinched-/coldFET extraction
Algorithm for hot-FET extraction of intrinsic network elements.
The complete multibias hot-FET small-signal characterization algorithm is shown in
Fig. 2-101. Hot-FET intrinsic extraction is performed for a comprehensive set of biases
and the resulting parameters are collected and sorted, creating a matrix of values for each
intrinsic network component.
219
In practice, τ and R gs are usually small and assumed to be zero, leaving five
remaining parameters under examination: g m , g ds , C gd , C gs and C ds . Multi-bias tablebased models for g m and g ds are created from their respective matrices. The extracted
matrices for C gs , C gd and C ds are each curve fit using the respective nonlinear
capacitance equations of (2-116)-(2-118). The capacitance equations are then used in
hybrid with the table-based g m , g ds models to evaluate the complete small-signal model
over the multibias range. During this evaluation, the capacitance equation parameters are
optimized to achieve a good S-parameter fit over the biases of interest. The finalized
capacitance models will eventually be implemented into the large-signal model topology.
Note that no modeling is performed on g m and g ds since their effect will be represented
by the I ds formula in the large-signal model.
Fig. 2-101
Computed
Multibias
Hot S-parameters
Initial parameter set for
optimizer
gm-vs-bias
gds-vs-bias
gds table
Cds-vs-bias
Cgd-vs-bias
Cgs-vs-bias
gm table
Cdsp Cds0 P20ds
P21ds P10ds P11ds
Cgdp Cgd0 P20gd
P21gd P10gd P11gd
Cgsp Cgs0 P20gs
P21gs P10gs P11gs
Measured Multibias Hot S-parameters
CgsN, CgdN, CdsN
gmN, gdsN
(Hot S-data)N
Cgs3, Cgd3, Cds3
gm3, gds3
(Hot S-data)3
Cgs2, Cgd2, Cds2
gm2, gds2
(Hot S-data)2
Cgs1, Cgd1, Cds1
gm1, gds1
(Hot S-data)1
220
Multibias hot-FET extraction and nonlinear capacitance modeling
algorithm.
221
SiC MESFET
Hot-FET S-parameter measurements were performed on the SiC MESFET biased
from Vgsq =[-10:1:-5]V and Vdsq =[0:2:58]V. The intrinsic network parameters g m , g ds ,
C gd , C gs and C ds are extracted from Re{Y21"} , Re{Y22 "}, Im{Y12 "}, Im{Y11"} and
Im{Y22 "}, respectively, as described by (2-109)-(2-113).
The Y”-parameters for an
example hot-FET bias of Vgsq =-6V, Vdsq =48V are shown in Fig. 2-102.
SiC MESFET: Vgsq=-6V, Vdsq=48V
0.05
0.25
0.20
Re{Y21"}
0.15
0.10
0.05
0.00
Re{Y22"}
Im{Y12"}, Im{Y11"} and Im{Y22"} (Ohm)
Re{Y21"} and Re{Y22"} (Ohm)
0.30
-0.05
Im{Y11"}
0.04
0.03
0.02
Im{Y22"}
0.01
0.00
Im{Y12"}
-0.01
0.0
0.5
1.0
1.5
2.0
0.0
0.5
f req, GHz
Fig. 2-102
1.0
1.5
2.0
f req, GHz
Hot-FET Y”-parameters intrinsic extraction. (SiC)
(DISS_model_hot_vgs06_vds48.dsn)
It can be observed from Fig. 2-102 that the extraction of the intrinsic parameters is
not trivial since the responses deviate from the ideal. According to (2-112) and (2-113),
g m and g ds can be extracted from constant values of Re{Y21"} and Re{Y22 "},
respectively. However, Fig. 2-102 shows both Re{Y21"} and Re{Y22 "} changing with
frequency. Likewise, (2-109)-(2-111) state that C gd , C gs and C ds are extracted from the
222
constant slope of Im{Y12 "}, Im{Y11"} and Im{Y22 "}, respectively. However, it is apparent
from Fig. 2-102 that the responses do not resemble the linear characteristics which would
make this extraction straightforward.
Therefore, a compromise is made in which only the frequency range of 0.1GHz to
0.831 GHz is considered under the extraction. An averaged value between this frequency
range is utilized for g m and g ds . Similarly, a best-fit constant slope is determined within
this range for C gd , C gs and C ds .
A complete small-signal model is constructed for each available S-parameter bias.
Comparisons between the simulated and measured S-parameters at six representative
biases are shown in Fig. 2-103. Although not perfect, the small-signal models show
reasonably good matches to S-parameters data. This reinforces the validity of the smallsignal extraction process employed in this work.
One noticeable deviation is S12 .
However, S12 is scaled by 100 in the plot and deviations will later be proven negligible.
223
S21
S21
S22
S22
S11
-15
-10
-5
0
5
10
S11
15
-20
-15
-10
-5
0
5
10
15
20
S12*100
S12*100
Vgs=-6V
Vds=48V
freq (100.0MHz to 4.000GHz)
Vgs=-8V
Vds=12V
freq (100.0MHz to 4.000GHz)
(a)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
(d)
S21
S22
S22
S11
-15
-10
-5
0
5
10
S21
S11
15
-25 -20 -15 -10
S12*100
freq (100.0MHz to 4.000GHz)
(b)
freq (100.0MHz to 4.000GHz)
-15
-10
-5
0
5
10
15
Fig. 2-103
25
S11
-30 -25 -20 -15 -10 -5
0
5 10 15 20 25 30
S12*100
S12*100
(c)
15 20
freq (100.0MHz to 4.000GHz)
(e)
20
Vgs=-10V
Vds=48V
freq (100.0MHz to 4.000GHz)
10
S21
S22
S11
-20
5
Vgs=-8V
Vds=4V
S21
S22
0
S12*100
Vgs=-8V
Vds=48V
freq (100.0MHz to 4.000GHz)
-5
Vgs=-8V
Vds=2V
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
(f)
freq (100.0MHz to 4.000GHz)
Hot-FET S-parameters evaluation for the { Vgsq , Vdsq } biases of (a)
{-6V,48V} (b) {-8V,48V} (c) {-10V,48V} (d) {-8V,12V} (e) {-8V,4V} (f)
{-8V,2V}. (SiC)
(DISS_model_hot_vgs06_vds48.dsn),(DISS_model_hot_vgs08_vds48.dsn)
(DISS_model_hot_vgs10_vds48.dsn),(DISS_model_hot_vgs08_vds12.dsn)
(DISS_model_hot_vgs08_vds04.dsn),(DISS_model_hot_vgs08_vds02.dsn)
The extracted g m , g ds , C gd , C gs and C ds parameters are plotted as functions of bias
in Fig. 2-104. Observation of the curves show that g m , g ds and C gs are the most heavily
nonlinear, while C gd varies mainly with Vdsq and C ds does not appear to vary much with
bias at all. Another thing to note is that g m begins to decrease with increasing Vdsq . This
is due to self-heating, which occurs as the bias is increased. Since the hot-FET Sparameters are measured under quiescent conditions, self-heating will manifest itself in
224
g m . This observation is in agreement with the collapse of the static IV characteristics
shown in Chapter 2.2.3.8.
225
SiC MESFET: Vgsq=[-10:1:05]V, Vdsq=[0:2:58]V
250
20
150
gds (A/V)
gm (A/V)
200
100
10
50
0
0
0
10
20
30
40
50
60
0
10
20
Vds (V)
2.5
40
50
60
40
50
60
4.0
3.5
Cgs (pF)
2.0
Cgd (pF)
30
Vds (V)
1.5
1.0
3.0
2.5
2.0
0.5
1.5
0
10
20
30
40
50
60
0
10
20
Vds (V)
30
Vds (V)
4
Cds (pF)
3
2
1
0
0
10
20
30
40
50
60
Vds (V)
Fig. 2-104
Multibias intrinsic parameters g m , g ds , C gd , C gs and C ds for
Vgsq =[-10:1:-5]V, Vdsq =[0:2:58]V. Modeled C gd , C gs and C ds are also
shown. (SiC)
(DISS_param_extract_program_plot.dsn)(DISS_Cgd_tune_opt.dsn),
(DISS_Cgs_tune_opt.dsn)(DISS_Cds_tune_opt.dsn)
226
The extracted, multi-bias small-signal models are further verified against measured
S-parameters across Vdsq in Fig. 2-105 and across Vgsq in Fig. 2-106. As shown in these
curves, S12 is actually very small does not deviate far from the measured responses. The
determined parameter sets are valid for a very expansive bias range.
S(1,2)
S(1,1)
SiC MESFET: Vgsq=-6V, Vdsq=[0:4:48]V
freq (100.0MHz to 4.000GHz)
Fig. 2-105
freq (100.0MHz to 4.000GHz)
S(2,2)
S(2,1)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
S-parameters of the multibias, Vgsq =-6V, Vdsq =[0:4:48]V. (SiC)
(DISS_S_multibias_plot.dsn)
227
S(1,2)
S(1,1)
SiC MESFET: Vgsq=[-10:1:-5]V, Vdsq=48V
freq (100.0MHz to 4.000GHz)
S(2,2)
S(2,1)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
Fig. 2-106
freq (100.0MHz to 4.000GHz)
S-parameters of the multibias sweep , Vgsq =[-10:1:-5]V, Vdsq =48V. (SiC)
(DISS_S_multibias_plot.dsn)
The bias-dependent characteristics of C gs and C gd are curve-fit to (2-116) and
(2-117), respectively, and the capacitance model parameters are extracted. The curvefitting of C gs is straightforward since the Vgs and Vds dependencies of the model directly
correlate to the applied biases used in Fig. 2-104. However, the C gd model depends on
Vgd rather than Vgs . Since, Vgd is not a directly controlled bias parameter, only a limited
range of characterization of C gd is available.
Fortunately, computing Vgd as the
difference between the available Vgs and Vds ranges provides sufficient data for modeling
228
C gd . Since C ds appears to be insensitive to bias, it is approximated with a constant value
of 1.1893 pF.
The extracted capacitance model parameters are presented in Table 2-33. The modelgenerated bias-dependent capacitor values are superimposed in Fig. 2-104 and
demonstrate a good fit to the discrete capacitance points. The fluctuations exhibited by
the imperfect extraction process can be smoothed over by modeling the capacitances
using the continuous functions of (2-116)-(2-118). This is an advantage of analytic
models as they possess the ability reduce uncertainties introduced during measurement.
Table 2-33 Extracted and optimized C gs , C gd and C ds model parameters (SiC)
Parameter
C gsp
Extracted under
curve-fitting
-14.538 pF
Optimized under
large-signal
0 pF
C gs 0
4.70795 pF
1.20857 pF
P20 gs
1.54558
0.233571
P21gs
0.0531739
0.107024
P10 gs
2.18481
0.632616
P11 gs
0.110654
0.110295
C gdp
0.560072 pF
0.377673 pF
C gd 0
7696.13 pF
0.985614 pF
P20 gd
-2.5304
-0.000843969
P21gd
-0.0416782
-0.00598528
P10 gd
-2.24637
0.00505133
P11gd
0.0224002
0.146924
C ds
1.1893 pF
0.77328 pF
A multibias, small-signal network utilizing a hybrid of table-based g m , g ds models
and equation-based C gs , C gd and C ds models is employed and compared against
229
measured multi-bias S-parameters.
The resulting comparisons with measured S-
parameter data show a very good agreement in Fig. 2-107 and Fig. 2-108. The fit using
the C gs , C gd and C ds models can be compared with the fit using tabulated values shown
in Fig. 2-105 and Fig. 2-106. There is no need to optimize the C gs , C gd and C ds model
parameters under S-parameters since the fit is already very good.
S(1,2)
S(1,1)
SiC MESFET: Vgsq=-6V, Vdsq=[0:4:48]V
freq (100.0MHz to 4.000GHz)
Fig. 2-107
freq (100.0MHz to 4.000GHz)
S(2,2)
S(2,1)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
S-parameters of the multibias small-signal model with nonlinear capacitance
models at Vgsq =-6V, Vdsq =[0:4:48]V. (SiC)
(DISS_S_multibias_Cmodel_opt.dsn)
230
S(1,2)
S(1,1)
SiC MESFET: Vgsq=[-10:1:-5]V, Vdsq=48V
freq (100.0MHz to 4.000GHz)
Fig. 2-108
freq (100.0MHz to 4.000GHz)
S(2,2)
S(2,1)
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
S-parameters of the multibias small-signal model with nonlinear capacitance
models at Vgsq =[-10:1:-5]V, Vdsq =48V. (SiC)
(DISS_S_multibias_Cmodel_opt.dsn)
GaN HEMT
Like the SiC MESFET, hot-FET S-parameter measurements were performed on the
GaN HEMT under a wide range of Vgsq and Vdsq . The g m , g ds , C gd , C gs and C ds are
extracted from Re{Y21"} , Re{Y22 "}, Im{Y12 "}, Im{Y11"} and Im{Y22 "}, respectively. An
example at Vgsq =-1.9V, Vdsq =28V is shown in Fig. 2-109.
Similar to the SiC MESFET case, the intrinsic small-signal model holds true for only
a limited frequency range as shown in Fig. 2-109. The model does not appear to stay
231
valid beyond 1GHz.
Therefore, Y”-parameters up 1 GHz are considered for the
extraction of g m , g ds , C gd , C gs and C ds .
Small-signal models are created for all available S-parameter datasets from the
extracted intrinsic parameters.
The simulated and measured S-parameters at six
representative biases are compared in Fig. 2-110. Some discrepancies appear in S 22 but
the overall extraction yields good agreement.
GaN HEMT: Vgs=-1.9V, Vds=28V
0.05
Im{Y12"}, Im{Y11"} and Im{Y22"} (Ohm)
Re{Y21"} and Re{Y22"} (Ohm)
2.5
2.0
1.5
1.0
Re{Y21"}
0.5
0.0
Re{Y22"}
-0.5
0.04
Im{Y11"}
0.03
0.02
Im{Y22"}
0.01
0.00
Im{Y12"}
-0.01
0.0
0.5
1.0
1.5
2.0
0.0
f req, GHz
Fig. 2-109
0.5
1.0
f req, GHz
Hot-FET Y”-parameters for intrinsic extraction. (GaN)
(DISS_S_ssmodel_vgs019_vds280_opt.dsn)
1.5
2.0
232
S11
S11
S21
S22
S21
-50 -40 -30 -20 -10
0
10 20
30 40
50
-50 -40 -30 -20 -10
S22
S12*100
10 20
30 40
50
S12*100
Vgs=-1.9V
Vds=28V
freq (50.00MHz to 10.05GHz)
0
Vgs=-2.2V
Vds=16V
(a)
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
S11
freq (50.00MHz to 10.05GHz)
(d)
S11
S21
S21
-50 -40 -30 -20 -10
S22
0
10 20
30 40
50
-40
-30
-20
-10
0
10
20
30
40
S22
S12*100
S12*100
Vgs=-2.2V
Vds=28V
freq (50.00MHz to 10.05GHz)
Vgs=-2.2V
Vds=8V
freq (50.00MHz to 10.05GHz)
(b)
freq (50.00MHz to 10.05GHz)
S11
freq (50.00MHz to 10.05GHz)
(e)
S11
S21
-20
S22
-15
-10
S21
-5
0
5
10
15
20
-30
-20
-10
0
10
20
30
S22
S12*100
S12*100
Vgs=-2.5V
Vds=28V
freq (50.00MHz to 10.05GHz)
Fig. 2-110
(c)
Vgs=-2.2V
Vds=1V
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
(f)
freq (50.00MHz to 10.05GHz)
Hot-FET S-parameters evaluation for the { Vgsq , Vdsq } biases of (a)
{-1.9V,28V} (b) {-2.2V,28V} (c) {-2.5V,28V} (d) {-2.2V,16V} (e)
{-2.2V,8V} (f) {-2.2V,1V}. (GaN)
(DISS_S_ssmodel_vgs019_vds280_opt.dsn),(DISS_S_ssmodel_vgs022_vds280_opt.dsn)
(DISS_S_ssmodel_vgs025_vds280_opt.dsn),(DISS_S_ssmodel_vgs022_vds160_opt.dsn)
(DISS_S_ssmodel_vgs022_vds080_opt.dsn),(DISS_S_ssmodel_vgs022_vds010_opt.dsn)
The extracted g m , g ds , C gd , C gs and C ds parameters for the GaN HEMT are plotted
as functions of bias in Fig. 2-111. The g m , g ds and C gs exhibit heavy two-dimensional
nonlinearity and C gd varies mainly with Vdsq much like in the case of the SiC MESFET.
However, contrary to the SiC MESFET, C ds of the GaN HEMT exhibits strong
dependencies on Vgsq and Vdsq . Self-heating can also be detected in the g m of the GaN
233
HEMT. However, it is less apparent since the GaN HEMT was characterized under a
smaller bias range with less DC power dissipation.
234
GaN HEMT: Vgsq=[-2.6:0.1:-1.9]V, Vdsq=[0:variable:28]V
800
50
40
gds (A/V)
gm (A/V)
600
400
200
30
20
10
0
0
0
5
10
15
20
25
30
0
5
10
Vds (V)
15
20
25
30
20
25
30
Vds (V)
2
5
Cgs (pF)
Cgd (pF)
4
3
2
1
0
0
0
5
10
15
20
25
30
0
5
10
Vds (V)
15
Vds (V)
Cds (pF)
2
0
0
5
10
15
20
25
30
Vds (V)
Fig. 2-111
Multibias intrinsic parameters g m , g ds , C gd , C gs and C ds for
Vgs =[-2.6:0.1:-1.9]V, Vds =[0:variable:28]V. The modeled C gd , C gs and C ds
are also shown. (GaN)
(DISS_param_extract_program_plot.dsn)(CGH40010_1_intrinsic_100708.xls)
(DISS_DC_Cgdmodel_opt.dsn)(DISS_DC_Cgsmodel_opt.dsn)
(DISS_DC_Cdsmodel_opt.dsn)
235
Additional comparisons between measured and simulated multibias S-parameters data
are provided across Vdsq in Fig. 2-112 and across Vgsq in Fig. 2-113. These curves show
that the S 22 accuracy suffers slightly. However, the general accuracy and overall bias
dependency are reasonably good for such an expansive bias range.
S12
S11
GaN HEMT: Vgs=-1.9V, Vds=[1 8 16 28]V
freq (50.00MHz to 10.05GHz)
S22
S21
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
Fig. 2-112
freq (50.00MHz to 10.05GHz)
S-parameters of the multibias sweep , Vgsq =-1.9V, Vdsq =[1,8,16,28]V.
(GaN)
(DISS_S_ssmodel_multibias_plot.dsn)
236
S12
S11
GaN HEMT: Vgs=[-2.6:0.1:-1.9]V, Vds=28V
freq (50.00MHz to 10.05GHz)
S22
S21
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
Fig. 2-113
freq (50.00MHz to 10.05GHz)
S-parameters of the multibias sweep , Vgsq =[-2.6:0.1:-1.9]V, Vdsq =28V.
(GaN)
(DISS_S_ssmodel_multibias_plot.dsn)
The bias-dependent C gs and C gd are fit using optimization to the models of (2-116)
and (2-117), respectively. However, it turns out the nonlinear behavior of C ds shown in
Fig. 2-111 cannot be completely modeled using (2-118). Since the mathematical form of
(2-118) is limited, an approximate fit for C gs is performed over a subset of the bias range
instead.
This deficiency reveals that the GaN HEMT model can benefit from an
improved nonlinear C ds model.
237
The extracted capacitance model parameters using curve-fitting are tabulated in Table
2-34 and the modeled curves are shown in the overlays of Fig. 2-111. These parameters
are further optimized under comparisons with multibias S-parameter datasets. The values
optimized under S-parameters are included in Table 2-34 and their fidelity is illustrated in
Fig. 2-114 and Fig. 2-115. Comparison of these two plots with Fig. 2-112 and Fig.
2-113, which use the tabulated component parameters, shows that the general fit is still
retained after implementing the nonlinear capacitance equations.
However, due to
limitations in the C ds model, deviations in S 22 appear, reducing the range of Vgsq validity
from -2.6V to -2.4V.
238
Table 2-34 Extracted and optimized C gs , C gd and C ds model parameters (GaN)
Parameter
C gsp
Extracted under
curve-fitting
0.0152946 pF
Optimized under Sparams
0.0152293 pF
Optimized under
Large-Signal
0.00239055 pF
C gs 0
1.19338 pF
1.18772 pF
1.28257 pF
P20 gs
8.1902e-009
8.18673e-9
5.00918e-009
P21gs
0.0570572
0.0565182
0.0800302
P10 gs
17.0664
17.6038
8.48047
P11 gs
6.75537
6.96803
3.31209
C gdp
0.329945 pF
0.380228 pF
0.947349 pF
C gd 0
1.60278 pF
2.09477 pF
2.44562 pF
P20 gd
-1.84818e-005
-2.01776e-5
-2.93138e-005
P21gd
0.000363127
3.54608e-4
-0.0365629
P10 gd
0.0759386
6.05037e-2
-0.0395367
P11gd
0.0574619
7.02186e-2
0.0116529
C dsp
0 pF
0.914651 fF
0.807795 pF
C ds 0
1.42269 pF
1.38989 pF
-0.00211364 pF
P20 ds
-1.14434
-1.07501
0.00667992
P21ds
0.111869
0.0937089
0.00232156
P10 ds
-2.04529
-1.60385
0.00757462
P11ds
-0.405092
-0.218372
0.000524274
239
S12
S11
GaN HEMT: Vgs=-1.9V, Vds=[1 8 16 28]V
freq (50.00MHz to 10.05GHz)
S22
S21
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
Fig. 2-114
freq (50.00MHz to 10.05GHz)
Multibias S-parameters of the multibias with the capacitance models,
Vgsq =-1.9V, Vdsq =[1,8,16,28]V. (GaN)
(DISS_S_ssmodel_Cmodel_multibias_plot.dds)
240
S12
S11
GaN HEMT: Vgs=[-2.6:0.1:-1.9]V, Vds=28V
freq (50.00MHz to 10.05GHz)
S22
S21
freq (50.00MHz to 10.05GHz)
freq (50.00MHz to 10.05GHz)
Fig. 2-115
freq (50.00MHz to 10.05GHz)
S-parameters of the multibias with capacitance model,
Vgsq =[-2.6:0.1:-1.9]V, Vdsq =28V. (GaN)
(DISS_S_ssmodel_Cmodel_multibias_plot.dds)
2.2.6. Assembly of the Complete Large-signal Model
The large-signal model is assembled by integrating the I ds model, extrinsic package
parasitics and nonlinear capacitance models into the complete large-signal network of
Fig. 2-5. The large-signal model is then finalized by optimizing the model parameters to
simultaneously satisfy small-signal and large-signal behavior. (Large-signal harmonic
power test setup is described in Appendix C.4). While some of the diode and linear
parameters are incorporated in the final optimization routine, it is mainly directly toward
refining the nonlinear capacitance model parameters.
241
Small-/Large-signal assumption of C’s
One assumption previously made is that the bias-sensitivity of the small-signal
behavior is purely due to electrical effects. However, due to the dispersion inherent in
III-V devices, S-parameters taken under quiescent bias will exhibit some level of selfheating and trapping, thereby embedding these effects in the extracted parameters. The
parameters most heavily affected are the bias-dependent intrinsic elements extracted
under hot-FET operation, as is apparent in Fig. 2-104 and Fig. 2-111. To a much lesser
extent, the extrinsic parameters may be affected by charge-trapping under the pinchedFET and cold-FET biases.
The presented characterization technique assumes that the capacitances are valid
under large-signal RF. This means that the capacitance equations (2-116)-(2-118) need
to be dependent on the instantaneous Vgs and Vds rather than the quiescent Vgsq and Vdsq
under which they are extracted. If the models were dependent on the quiescent biases,
they would not be able to track large voltage swings at RF. Large-signal RF excitation
may also cause shifts in the quiescent point, creating another source of uncertainty for the
capacitance predictions.
Furthermore, the capacitance models are fit under the externally applied gate-source
and drain-source biases.
Once integrated into the large-signal model, their bias
dependencies will have to be shifted to Vgsi and Vdsi as was done for the I ds model. The
most appropriate way to address this issue is through optimization.
242
Small-/Large-signal assumption of I ds
The integration of the frequency dependent small-signal components and the I ds
model will alter the completed large-signal model’s ability to precisely predict Sparameters. Substituting the multibias g m and g ds extracted under small-signal with the
I ds formula assumes that I ds is valid under small- and large-signal RF. In other work,
significant S-parameter discrepancies caused by the use of a static-based I ds are
compensated by adding an RF current generator that supplements differences in smallsignal g m and g ds [91].
Fortunately, I ds models based on pulsed characteristics provide improved predictions
of g m and g ds at RF and create only minor S-parameter discrepancies which can be
compensated through optimization. It turns out that optimizing the capacitance model
parameters alone will sufficiently compensate these differences without modifying I ds .
This preserves the validity of the pulsed IV fit and results in a model that is consistent
across large-signal, small-small, DC, pulsed and RF excitation.
In conclusion, significant assumptions of small-/large-signal validity are made by
utilizing the multibias quiescent capacitance extraction method and by substituting g m
and g ds with a pulsed-derived I ds .
Fortunately, optimizing the capacitance model
parameters under simultaneous small-/large-signal can reduce these uncertainties and
strike a compromise within the mathematical limits of the formulas.
The optimized capacitance model parameters under large-signal are given in Table
2-33 and Table 2-34 for the SiC MESFET and GaN HEMT models, respectively.
Validation of the completed large-signal models is demonstrated next.
243
2.3.
Model Performance Under Small- and Large-signal RF Drive
In this section, the RF performances of the completed SiC MESFET and GaN HEMT
models are evaluated.
2.3.1. SiC MESFET Large-signal Model
The performance of the SiC MESFET model is evaluated under small- and largesignal RF drive. Two representative { Vgsq , Vdsq } biases are used to demonstrate the
model performance:
{-10V,55V} and {-7V,55V}.
Comparisons with wideband S-
parameters and large-signal output ( Pout ) and input reflected ( Prefl ) single-tone harmonic
power measurements demonstrate the broad validity of the general-purpose nonlinear
model with respect to incident power level ( Pavs ), bias and frequency. Additionally,
third-order intermodulation products obtained using two-tone power measurements
further confirm the nonlinear fidelity of the model.
2.3.1.1.
Small-signal S-parameters
Simulated and measured S-parameters for the two representative biases are shown in
Fig. 2-116.
An examination of these plots reveals a close agreement between the
measured and modeled data, thus verifying the functionality of the model when employed
in a small-signal mode.
The close match establishes that, when used in conjunction with the appropriately
modeled intrinsic and extrinsic parasitics, the I ds source developed under pulsed
244
characterization can accurately predict the small-signal behavior of the device without
using a supplementary RF current generator.
SiC MESFET
S(2,1)
S(1,1)
-15
-10
-5
0
S(2,2)
5
10
15
S(1,2)*50
Vgsq=-10.0V
Vdsq=55V
Idsq=50mA
PD=2.75W
freq (100.0MHz to 4.000GHz)
freq (100.0MHz to 4.000GHz)
(a)
S(2,1)
S(1,1)
-15
-10
-5
0
5
10
15
S(2,2)
S(1,2)*50
Vgsq=-7.0V
Vdsq=55V
Idsq=332mA
PD=18.26W
freq (100.0MHz to 4.000GHz)
Fig. 2-116
2.3.1.2.
(b)
freq (100.0MHz to 4.000GHz)
S-parameters at (a) {-10V,55V} and (b) {-7V,55V}. (SiC)
(DISS_HB_S_ls_thermal_xtr3633_multibias_opt.dds)
Single-tone Harmonic Power
Single-tone harmonic power vs incident power
The large-signal fidelity of the model is verified by comparing the Pout and Prefl
harmonic predictions with measured data for three harmonics as shown in Fig. 2-117.
245
According to the power characteristics, the model closely matches the measured data at
f o =2GHz over a range of Pavs =[21:1:40]dBm and for both representative biases.
The power measurements provided are of the unmatched device and not of a
particular amplifier implementation, which further establishes this as a general-purpose
device model. The model will allow exploration of many linear and nonlinear circuit
applications.
Power characterization at both ports provides a heightened understanding of the
terminal nonlinearities which are responsible for harmonic generation under large-signal
RF excitation. For example, the Prefl characteristics can be used to compute the actual
power delivered into the device, which may be helpful in understanding and improving
the efficiency of power amplifiers.
Another application is in the development of
frequency multipliers which benefit from the exploitation of device nonlinearities.
246
40
SiC MESFET: Vgsq=-10.0V, Vdsq=55V, Pavs=[21:1:40]dBm, fo=2.00GHz
45
30
35
fo
25
Pout (dBm)
Prefl (dBm)
20
10
0
2fo
15
-20
-5
-25
20
25
30
35
40
Pavs (dBm)
20
35
40
SiC MESFET: Vgsq=-7.0V, Vdsq=55V, Pavs=[21:1:40]dBm, fo=2.00GHz
45
35
fo
25
Pout (dBm)
20
Prefl (dBm)
30
Pavs (dBm)
fo
10
0
2fo
15
5
-10
2fo
-5
-15
3fo
3fo
-30
-25
20
25
30
Pavs (dBm)
Fig. 2-117
25
(a)
30
-20
3fo
-15
-30
40
2fo
5
-10
3fo
fo
35
40
20
25
(b)
30
35
40
Pavs (dBm)
Harmonic Prefl and Pout versus Pavs at (a) {-10V,55V} and (b) {-7V,55V}.
(SiC)
(DISS_HB_S_ls_thermal_xtr3633_multibias_opt.dds)
DC current shift vs incident power
Under large-signal continuous drive, the device will experience an increased static
drain-current I dsq due to clipping of the output current waveform. As a result, I dsq rises
247
with increasing Pavs . This effect leads to changes in the static PD , and thus, device
temperature. A well-developed thermal model is necessary to predict this operating point
shift. The modeled and measured I dsq versus Pavs =[21:1:40]dBm is shown in Fig. 2-118
for the two representative biases. The model shows good agreement with measured data
demonstrating the efficacy of the model in translating nonlinear RF effects into DC drain
current.
SiC MESFET: Vdsq=55V, Pavs=[21:1:40]dBm, fo=2.00GHz
0.8
Vgsq=-7.0V
Idsq (A)
0.6
0.4
0.2
Vgsq=-10.0V
0.0
20
22
24
26
28
30
32
34
36
38
40
Pavs (dBm)
Fig. 2-118
Static I dsq -vs- Pavs at two biases. (SiC)
(DISS_HB_S_ls_thermal_xtr3633_multibias_opt.dds)
Single-tone harmonic power vs bias
Additional characterization of the large-signal behavior across gate-source and drainsource bias is investigated. The Prefl and Pout over swept Vgsq and Vdsq are shown in Fig.
2-119 and Fig. 2-120, respectively. The model shows good agreement with the measured
data for three harmonics.
248
40
SiC MESFET: Vgsq=[-10:0.5:0]V, Vdsq=55V, Pavs=33dBm, fo=2.00GHz
40
fo
30
fo
30
2fo
10
Pout (dBm)
Prefl (dBm)
20
2fo
0
3fo
-10
20
10
3fo
0
-20
-10
-30
-10
-8
-6
-4
-2
0
-10
-8
Vgsq (V)
Fig. 2-119
-6
-4
-2
0
Vgsq (V)
Harmonic Prefl and Pout versus Vgsq at Vdsq =55V with an incident power of
Pavs =33dBm. (SiC)
(DISS_HB_ls_thermal_xtr3633_PinPout_vgssweep_vds550.dds)
40
SiC MESFET: Vgsq=-7V, Vdsq=[0:5:55]V, Pavs=33dBm, fo=2.00GHz
40
30
2fo
2fo
0
3fo
-10
20
10
-10
-30
-20
10
20
30
40
Vdsq (V)
50
60
3fo
0
-20
0
Fig. 2-120
Pout (dBm)
Prefl (dBm)
20
10
fo
30
fo
0
10
20
30
40
50
60
Vdsq (V)
Harmonic Prefl and Pout versus Vdsq at Vgsq =-7V with an incident power of
Pavs =33dBm. (SiC)
(DISS_HB_ls_thermal_xtr3633_PinPout_vgs070_vdssweep.dds)
249
Single-tone harmonic power vs frequency
The large-signal performance of the model versus frequency has been assessed over a
moderate band of frequencies. The modeled and measured data over a frequency range
covering the GSM 1800, GSM 1900, CDMA 1900, WCDMA 1900, and WCDMA 2100
commercial communications bands is shown in Fig. 2-121. This represents a range of
20% fractional bandwidth centered around f o =2.00GHz with the device biased at
Vgsq =-8V and Vdsq =55V. A perusal of the data and simulations demonstrates the model’s
efficacy in predicting Prefl and Pout for three harmonics over frequency.
SiC MESFET: Vgsq=-8V, Vdsq=55V, Pavs=37dBm, fo=[1.80:0.01:2.20]GHz
45
fo
Prefl (dBm)
30
20
2fo
10
fo
35
Pout (dBm)
40
0
2fo
25
15
3fo
5
3fo
-10
-5
1.8
1.9
2.0
2.1
2.2
freq (GHz)
Fig. 2-121
1.8
1.9
2.0
2.1
2.2
freq (GHz)
Harmonic Prefl and Pout versus frequency over a 20% fractional bandwidth
centered at f o =2.00GHz. (SiC)
(DISS_HB_ls_thermal_xtr3633_broadband_multibias.dds)
250
2.3.1.3.
Third-order Intermodulation Distortion (IM3)
The third-order intermodulation distortion of the SiC MESFET has been
characterized using a two-tone test conducted at f1 =2GHz, f 2 = f1 +100kHz with
Pavs =[10:1:27]dBm per tone and a bias of Vgsq =-8V, Vdsq =55V. Since the device is
unmatched, significant IM3 products will be generated at both the output and input
reflected ports. According to the measured and modeled IM3 power shown in Fig. 2-122,
the model is reasonably accurate in predicting both output and input reflected IM3
products.
SiC MESFET: Vgsq=-8V, Vdsq=55V, Pavs=[10:1:27]dBm, f1=2GHz, f2=f1+100kHz
40
40
20
0
-20
IM3
Pout per tone (dBm)
20
Prefl per tone (dBm)
fund
fund
0
IM3
-20
-40
-40
-60
-60
10
15
20
25
30
Pavs per tone (dBm)
Fig. 2-122
10
15
20
25
30
Pavs per tone (dBm)
Input reflected and output IM3 and fundamental products. (SiC)
(DISS_HB_ ls_thermal_xtr3633_IM3.dds)
2.3.2. GaN HEMT Large-signal Model
The RF performance of the model compared with measured data is presented next.
To demonstrate the efficacy of the modeling process detailed in this work, small-signal
251
RF comparisons followed by harmonic single-tone and wideband large-signal RF
comparisons will be made for two representative biases: {-2.5V,28V} and {-1.9V,28V}.
Model predictions of IM3 are also provided. Finally, the model will be verified at largesignal under an optimum load for producing the maximum f o output power.
2.3.2.1.
Small-signal S-Parameters
S-parameter simulations of the GaN HEMT model for the two representative biases
are performed over a frequency range of 0.2 to 10GHz and show close agreement with
measured data as shown in Fig. 2-123. Since the two representative biases exhibit
different power levels and quiescent terminal voltages, proper representations of the
device at RF require correctly derived self-heating and trapping models. Validation of
the model for small-signal operation suggests that the PGIV- and PIV-based drain current
implementation provides accurate prediction of g m and g ds at RF and under various selfheating and charge-trapping conditions. Furthermore, the extraction and modeling of the
parasitic extrinsic and intrinsic elements is also validated.
252
GaN HEMT
S(1,1)
S(2,1)
S(2,2)
-40
-30
-20
-10
0
20
30
40
S(1,2)*100
Vgsq=-2.5V
Vdsq=28V
Idsq=14m A
Pdiss=0.4W
freq (200.0MHz to 10.00GHz)
10
freq (200.0MHz to 10.00GHz)
(a)
S(1,1)
S(2,1)
-40
S(2,2)
-30
-20
-10
0
10
20
30
40
S(1,2)*100
freq (200.0MHz to 10.00GHz)
Fig. 2-123
2.3.2.2.
Vgsq=-1.9V
Vdsq=28V
Idsq=386mA
Pdiss=10.8W
(b)
freq (200.0MHz to 10.00GHz)
S-parameters at (a) {-2.5V,28V} and (b) {-1.9V,28V}. (GaN)
(DISS_HB_S_lsmodel_MTT_opt.dds)
Single-tone Harmonic Power
Single-tone harmonic power vs incident power
Under large signal drive, I ds and Vds become distorted, causing the output to saturate
and generate harmonics. Concurrently, the unmatched gate generates significant Prefl due
to input limiting nonlinearities. Therefore, it is important for a general nonlinear model
to accurately predict both Prefl and Pout harmonics. Also, computations of Prefl can aid in
improving power added efficiency (PAE) in high-efficiency power amplifier applications.
253
The model is assessed under large signal excitations over Pavs =[10:1:39]dBm at
f o =3.333GHz in a 50 Ω system. The Prefl and Pout are measured for three harmonics
and for the two representative biases as shown in Fig. 2-124a and Fig. 2-124b,
respectively. A comparison of these measured and modeled results demonstrates the
model’s capability to accurately predict the large-signal harmonic behavior.
254
GaN HEMT: Vgsq=-2.5V, Vdsq=28V, Pavs=[10:1:39]dBm, fo=3.333GHz
45
40
30
30
20
20
Pout (dBm)
Prefl (dBm)
45
40
fo
10
0
2fo
-20
10
20
30
10
40
30
40
GaN HEMT: Vgsq=-1.9V, Vdsq=28V, Pavs=[10:1:39]dBm, fo=3.333GHz
45
40
30
fo
Pout (dBm)
Prefl (dBm)
20
Pavs (dBm)
(a)
30
10
0
-10
fo
20
10
0
2fo
-10
-20
2fo
3fo
-30
10
20
3fo
-30
30
Pavs (dBm)
Fig. 2-124
3fo
-30
Pavs (dBm)
-20
0
-20
3fo
-30
20
2fo
-10
-10
45
40
10
fo
40
10
(b)
20
30
40
Pavs (dBm)
Harmonic Prefl and Pout versus Pavs for f o =3.333GHz at (a) {-2.5V,28V}
and (b) {-1.9V,28V}. (GaN)
(DISS_HB_S_lsmodel_MTT_opt.dds)
A perusal of the harmonic data at these two quiescent biases provides an assessment
of harmonic generation as a function of Pavs .
Starting at low Pavs , the harmonic
generation at the input and output differ greatly between the two biases. At Vgsq =-2.5V,
there is generally more second- and third-order Prefl and Pout while at Vgsq =-1.9V, there is
255
generally more fundamental Pout . Beyond Pavs =33dBm the device output saturates and
the Prefl and Pout harmonic power levels are similar for both biases. At these levels, the
quiescent operating points converge regardless of the applied DC bias due to the shift in
I dsq that occurs under large signal RF drive as shown in Fig. 2-125. Current I dsq
increases until Pavs =36dBm at which Dgs is pushed into forward conduction, causing
I dsq to saturate. The ability to track this I dsq behavior is made possible by the accurate
self-heating model which continuously adapts I ds with increasing PD and by the
correctly implemented hard clipping mechanisms of Dgs .
GaN HEMT: Vdsq=28V, Pavs=[10:1:39]dBm, f=3.333GHz
1.0
0.8
Idsq (A)
Vgsq=-1.9V
0.6
0.4
0.2
Vgsq=-2.5V
0.0
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
Pavs (dBm)
Fig. 2-125
Static I dsq -vs- Pavs at two biases. (GaN)
(DISS_HB_S_lsmodel_MTT_opt.dds)
256
Single-tone harmonic power vs frequency
One of the main advantages of GaN HEMTs is their ability to operate over wide
frequency ranges.
The broadband large-signal performance of the model has been
examined over a frequency range of 1.8 to 3.9GHz which corresponds to 73% fractional
bandwidth centered at f o =2.85GHz. This is over an octave of bandwidth and covers a
majority of the S-band. The large-signal wideband Prefl and Pout harmonic predictions
are compared with measured data in Fig. 2-126a and Fig. 2-126b for the two
representative biases, respectively. The wide frequency coverage of the model highlights
its use as a high-precision, broadband nonlinear model with the ability to predict up to
three harmonics.
257
GaN HEMT: Vgsq=-2.5, Vdsq=28V, Pavs=30dBm, fo=[1.8:0.1:3.9]GHz
45
45
fo
35
fo
Pout (dBm)
Prefl (dBm)
35
25
2fo
15
3fo
-5
1.5
15
3fo
2.0
2.5
3.0
3.5
-5
1.5
4.0
freq (GHz)
2.0
2.5
3.0
3.5
4.0
freq (GHz)
(a)
GaN HEMT: Vgsq=-1.9, Vdsq=28V, Pavs=30dBm, fo=[1.8:0.1:3.9]GHz
45
fo
45
35
35
fo
25
2fo
15
Pout (dBm)
Prefl (dBm)
2fo
5
5
5
25
2fo
15
3fo
5
3fo
-5
1.5
2.0
2.5
3.0
3.5
freq (GHz)
Fig. 2-126
25
-5
4.0
1.5
2.0
2.5
3.0
3.5
4.0
freq (GHz)
(b)
Harmonic Prefl and Pout versus f o from 1.8 to 3.9 GHz at (a) {-2.5V,8V}
and (b) {-1.9V,28V}. (GaN)
(DISS_HB_lsmodel_broadband_vdsq28_MTT.dds)
2.3.2.3.
Third-order Intermodulation Distortion (IM3)
The IM3 products at the input reflected and output ports has been measured using a
two-tone
test
conducted
with
f1 =3.3333GHz
and
f 2 = f1 +100kHz
Pavs =[20:1:29]dBm per tone and device biased at {-1.3V,28V}.
over
Since this is an
258
unmatched device, significant IM3 products will be generated due to nonlinear input
reflection at the gate in addition to the nonlinear output at the drain. According to the
swept IM3 characteristics shown in Fig. 2-127, the large-signal model closely matches
the distortion behavior over the high two-tone power levels.
Pout per tone (dBm)
Prefl per tone (dBm)
GaN HEMT: Vgsq=-1.3V, Vdsq=28V, Pavs=[20:1:29]dBm, f1=3.3333GHz, f2=f1+100kHz
40
40
fund
fund
20
20
0
-20
-40
IM3
-60
IM3
-20
-40
-60
20
22
24
26
28
Pavs per tone (dBm)
Fig. 2-127
0
30
20
22
24
26
28
30
Pavs per tone (dBm)
Input reflected and output IM3 and fundamental power per tone with
f1 =3.3333GHz and f 2 = f1 +100kHz at {-1.3V,28V}. (GaN)
(DISS_HB_lsmodel_IM3.dds)
2.3.2.4.
Fundamental Output Power Under Optimal Load
The large-signal accuracy of the device model is further evaluated for its ability to
predict the Pout under an optimum load termination.
The impedance delivering
maximum fundamental Pout at f o =3.333GHz and Pavs =+36dBm is determined using
load-pull simulations of the model biased at {-2.5V,28V}. This optimal impedance is
realized using a distributed binomial impedance transformer. The impedance looking out
of the drain and into the transformer network is frequency dependent and equal to Z d ( f )
259
and Z dn = Z d (nf o ) . The measured values of Z d 1 , Z d 2 , Z d 3 at f o , 2 f o , 3 f o , respectively,
are shown in Fig. 2-128 along with the simulated load-pull power contours produced in
ADS.
Zd3
S(1,1)
Zd2
Zd1
Zd1 =11.428+j2.725 Ohm
Z d2=46.502+j4.173 Ohm
Z d3=13.925+j7.106 Ohm
Fig. 2-128
Measured Z d 1 (X), Z d 2 (circle) and Z d 3 (triangle) and load-pull contours
(1dB per contour) at Pavs =36dBm and {-2.5V,28V}. Max predicted
Pout =41.77dBm. (GaN)
(DISS_HB1Tone_LoadPull.dds)
The measured and modeled Pout sweep of the device terminated in the realized
network is shown in Fig. 2-129 for both representative biases over Pavs =[10:1:39]dBm.
At Pavs =37 dBm, the peak fundamental Pout =41.17dBm (13.09W) for Vgsq =-2.5V and
Pout =41.06dBm (12.78W) for Vgsq =-1.9 V are predicted closely by the model. The gain
and PAE are also provided in Fig. 2-129a and Fig. 2-129b. These results show that the
260
model can predict the very high output power levels under an optimum f o load
impedance with good accuracy.
GaN HEMT: Vgsq=-2.5V, Vdsq=28V, Pavs=[10:1:39]dBm, fo=3.333GHz
100
90
40
Pout
35
80
70
60
50
40
30
20
30
25
PAE
20
15
Gain
10
5
PAE (%)
Pout (dBm), Gain (dB)
45
10
0
0
10
15
20
25
30
35
40
Pavs
(a)
GaN HEMT: Vgsq=-1.9V, Vdsq=28V, Pavs=[10:1:39]dBm, fo=3.333GHz
Pout (dBm), Gain (dB)
40
Pout
35
30
25
50
40
30
20
10
0
PAE
20
Gain
15
10
5
0
10
15
20
25
30
35
PAE (%)
100
90
80
70
60
45
40
Pavs
(b)
Fig. 2-129
Pout (X’s), Gain (triangles), and PAE (circles) under optimum f o load
termination at (a) {-2.5V,28V} and at (b) {-1.9V,28V}. Measured
(symbols), modeled (solid lines). (GaN)
(DISS_HB_S_lsmodel_MTT_opt.dds)
2.3.3. Model Performance Comparison
A comparison table summarizing the capabilities of the SiC and GaN models is given
in Table 2-35.
261
Table 2-35 Comparison of SiC MESFET and GaN HEMT models
Ref.
Device
IV model
basis
DC
Max
Reported#
Ids/Vds
1.2A / 60V
Small-signal
freq. ranges
At {Vgs,Vds}
N/A
[58]
SiC
MESFET
[49]
GaN
HEMT
DC
0.14A / 20V
1-30GHz
{multibias}
SiC
MESFET
DC
0.06A / 40V
0.05-14.05GHz
{multibias}
[53]
FET
DC
0.27A / 20V
1-39GHz
{multibias}
[54]
GaN
HEMT
DC
0.12A / 20V
1-30GHz
{multibias}
SiC
MESFET
DC
0.32A / 40V
0.05-14.05GHz
{multibias}
[50]
GaN
HEMT
PIV
(4 bias)
0.63A / 40V
[51]
GaN
HEMT
DC
PIV
(2 bias)
0.5-20.1GHz
{-5V,20V}
{-8V,20V}
0.72A / 38V
0.2-35GHz
{-4V,25V}
[72]*
SiC
MESFET
DC
PGIV
(4 bias)
2A / 56V
0.1-4GHz
{-10V,55V}
{-7V,55V}
2.4A / 56V
0.2-10GHz
{-2.5V,28V}
{-1.9V,28V}
PIV
(3 bias)
DC
[74]*
GaN
HEMT
PGIV
(2 bias)
PIV
(8 bias)
#
not simultaneous, *included in this work
Large-signal ranges
N=number of harmonics
{operating conditions}
Single-tone:
fo=1GHz, N=1, Pin=17 to 34dBm
{Vds=30V, Ids=500mA}
Single-tone:
fo =3GHz, N=1, Pin=-10 to 12dBm, Pout=9 to 25dBm
{Vgs=-4V, Vds=40V}
Single-tone:
fo =3GHz, N=1, Pin=-5 to 20dBm, Pout=0 to 22dBm
{Vgs=-8V, Vds=40V}
Single-tone:
fo =2GHz, N=1, Pin=2 to 12dBm, Pout=21 to 27dBm
fo =12GHz, N=1, Pin=2 to 20dBm, Pout=8 to 23dBm
fo =18GHz, N=1, Pin=7 to 23dBm, Pout=10 to 23dBm
Single-tone:
fo =3GHz, N=1, Pin=-10 to 12dBm, Pout=9 to 25dBm
{Vgs=-4V, Vds=40V}
fo =1GHz, N=3, Pin=10dBm, Pout=up to 13dBm
{Vds=20V}
Single-tone:
fo =3GHz, N=1, Pin=0 to 25dBm, Pout=12 to 35dBm
{Vgs=-8V, Vds=40V}
Single-tone:
fo =4GHz, N=1, Pin=0 to 23dBm, Pout=up to 35dBm
{Id=166mA, Vd=30V}
Two load impedances
Single-tone:
fo =10GHz, N=1, Pin=-5 to 25dBm, Pout=10 to 34dBm,
{Vds=25V}
Six load impedances
Single-tone:
fo =2GHz, N=3, Pavs=21dBm to 40dBm
Pout=up to 40dBm, Prefl=up to 37dBm
{Vgs=-10V, Vds=55V} and {Vgs=-7V, Vds=55V}
Single-tone:
fo =2GHz, N=3, Pavs=33dB
{Vds=55V, Vgs=-10 to 0V sweep}
fo =2GHz, N=3, Pavs=33dB
{Vgs=-7.0V, Vds=0 to 56V sweep}
fo =1.8 to 2.2GHz sweep, N=3, Pavs=37dBm
Pout=up to 34dBm, Prefl=up to 40dBm
{Vgs=-8V, Vds=55V}
Two-tone:
f1=2.0GHz, f2=f1+100kHz, Pavs=10 to 27dBm/tone
{Vgs=-8V, Vds=55V}
Single-tone:
fo=3.33GHz, N=3, Pavs=10 to 39dBm
Pout=up to 38dBm, Prefl=up to 37dBm
{Vgsq=-2.5V, Vds=28V}, {Vgsq=-1.9V, Vds=28V}
fo =1.8 to 3.9GHz sweep, N=3, Pavs=30dBm
Pout=up to 38dBm, Prefl=up to 29dBm
{Vgsq=-2.5V, Vds=28V}, {Vgsq=-1.9V, Vds=28V}
Two-tone:
f1=3.333GHz, f2=f1+100kHz, Pavs=20 to 29dBm/tone
{Vgs=-1.3V, Vds=28V}
Single-tone, Optimal ZL:
fo=3.333GHz, N=1, Pavs=10 to 39 dBm
Pout=up to 41.17dBm
{Vgsq=-2.5V, Vds=28V}, {Vgsq=-1.9V, Vds=28V}
262
2.4.
Summary
The harmonically accurate models are valuable in studying the manipulation of twoterminal harmonic generation in high-power microwave SiC MESFET and GaN HEMT
circuits. In the next chapter, the application of these models for high power frequency
multiplier design will be presented.
263
CHAPTER 3. HIGH POWER ACTIVE FREQUENCY
MULTIPLIER DESIGN
3.1.
Overview
While high-order harmonic manipulation is a frequently employed performanceenhancing technique in power amplifier design [112][113][114], it is scarce in the
development of III-V-based frequency multipliers [70][75][76]. CAD-based frequency
multiplier design approaches are preferred [115][116][117], but are sometimes not
feasible due to the limited availability of models which accurately predict high-order
harmonics and dispersive phenomena. Dispersive phenomena such as self-heating and
charge-trapping are prominent in developing solid-state technologies and complicate
device characterization and modeling.
Instead, frequency multipliers are often designed using Fourier-analysis-based
techniques [118] and measurement-based approaches [119][120]. Fourier-analysis-based
design is not well-developed enough and does not consider all the possible nonlinearities
affecting harmonic generation to be employed effectively. Frequency multiplier design
using harmonic load- and source-pull-based techniques can lead to an optimal bias and
circuit realization [121][122].
However, the exhaustive nature, complexity of the
measurement, acquisition time and post-processing intensity makes such an approach an
expensive option.
Recent work on active frequency doublers report high conversion gain and moderate
power levels [70][120][123][124][125]. However, few single-transistor active doublers
264
have been shown to produce greater than 1W at 2 f o . Similarly, frequency triplers found
in
literature
produce
only
marginal
amounts
of
power
[126][127][128][129][130][131][118][132][133][134]. High power doublers in GaN and
SiC technology have been demonstrated [75], but higher order frequency multipliers
using wide band-gap technology have rarely been reported [76].
The work presented here, a detailed theoretical analysis of harmonic generation
expanding on the principles of [135] is given in Chapter 3.2. A complete, systematic
procedure for designing high power frequency multipliers using biasing, CAD-based
harmonic load-/source-pull simulations and straightforward synthesis of high-efficacy
networks is presented in Chapter 3.3. The design of high power SiC MESFET and GaN
HEMT C-band frequency doublers producing >5W (Chapter 3.4) and a GaN HEMT Xband tripler producing 1W (Chapter 3.5) are demonstrated [75][76]. The doublers and
tripler shown here provide the highest output power known. The design of these circuits
is made possible by the availability of high-precision multi-harmonic SiC and GaN
device models [72][74].
3.2.
Active Microwave Frequency Multiplier Theory
All frequency multipliers principally operate by the exploitation of waveform
distortion created by IV nonlinearities. Any nonlinearity will create harmonics, but
distortion is most appreciable when a device is driven across distinct regimes of
operation.
Since the generation of harmonic power is the core of all performance
considerations, it is the most crucial facet of frequency multiplier analysis and design.
265
In this section, a generalized investigation of harmonic power of a nonlinear device is
described. This consists of defining the harmonic power in a FET, introducing ideal,
piecewise-linear models and investigating waveform distortion using Fourier Analysis.
Although Fourier analysis lacks realism, it can serve as a precursor to a practical design
by providing an analytical understanding of harmonic generation with respect to drive,
bias and operating region.
The unified, general Fourier analysis approach to nonlinear circuit design developed
here consists of integrated single- and double-sided clipped waveform analyses that are
consistent
with
widely
accepted
power
amplifier
conduction
classifications.
Conventional single-sided conduction angle analysis alone provides only a limited view
of nonlinear circuit design. Here, it serves as a building block for exploring clipped
waveforms for any given device characteristics, input and load. The unified formulation
can be applied over all operating regions and enables the exploration of linear to
extremely nonlinear operating mode transitions. Never before has frequency multiplier
design been so extensively studied using analytical formulation.
3.2.1. Harmonic Power of a Nonlinear FET Device
Harmonic power is the most important parameter in the development of power
amplifiers and frequency multipliers. By analyzing harmonic power generation and its
relationship to transistor operation, the performance parameters such as conversion gain,
efficiency and input linearity can be investigated.
Fundamental analysis begins by considering a transistor under generalized two-port
analysis. In Fig. 3-1a, a generalized two-port connection is shown and consists of the
266
transistor with each terminal driven by a DC and an RF generator. A full two-port
investigation of this device yields the most comprehensive understanding of harmonic
generation at both ports. However, for most practical cases, unilateral RF excitation and
the generation of output harmonic power is the main focus. Therefore, only port 1 is
driven with RF and will serve as the input of the circuit. No RF generator is required at
port 2, which will serve as the output RF port. The resulting circuit under consideration
is shown in Fig. 3-1b. In the figure, the input of the transistor is connected to a gatesource bias supply VGG and an RF generator v S , through a generator impedance Z S . The
output of the transistor is connected to a drain-source bias supply VDD through a
generator impedance Z L . The current and voltage pairs at the gate-source and drainsource terminals of the device are ( I gs , V gs ) and ( I ds , Vds ), respectively. It is important to
differentiate between the terminal currents and voltages and those of the generator due to
the ensuing nonlinearities which cause variations between the two.
267
Fig. 3-1
(a) Generalized and (b) unilateral large-signal two-port configurations for
analysis of a nonlinear circuit or device.
The complete gate excitations is
V g = VGG + v s = VGG + V A cos(ωt )
(3-1)
and the complete drain excitation is
(3-2)
Vd = VDD
since the there is zero AC drive at the drain.
The available RF power from the source or Pavs (See Appendix B.1 for derivation)
2
Pavs =
VA
8Z S
(3-3)
268
All nonlinear current, voltage, and power waveforms considered in this treatment will
be represented as a Fourier series. Under a cosine excitation, the power dissipated across
the drain-source terminal of the transistor can be represented by
∞
PD (t ) = PD 0 + PD1 cos(ω o t ) + PD 2 cos(2ω o t ) + K = ∑ PDn cos(nω o t )
(3-4)
n =0
and the power dissipated across the load resistor is
PL (t )
∞
= PL 0 + PL1 cos(ω o t ) + PL 2 cos(2ω o t ) + K = ∑ PLn cos(nω o t )
(3-5)
n =0
where PDn and PLn are the Fourier series coefficients for PD (t ) and PL (t ) , respectively,
for the n th harmonic. Similarly, the transient terminal waveforms of the transistor are
∞
I gs (t ) = ∑ I gsn cos(nω o t )
(3-6)
n =0
∞
Vgs (t ) = ∑ Vgsn cos(nω ot )
(3-7)
n =0
∞
I ds (t ) = ∑ I dsn cos(nω ot )
(3-8)
n =0
∞
Vds (t ) = ∑ Vdsn cos(nω ot )
(3-9)
n =0
where I gsn , Vgsn , I dsn , Vdsn are the Fourier series coefficients of I gs (t ) , Vgs (t ) , I ds (t ) , and
Vds (t ) , respectively.
The harmonic power, PL , delivered to the load, Z L , is of prime importance. First, the
power delivered across the drain-source terminal, PD , can be expressed in terms of I dsn
and Vdsn :
269
Vds 0 I ds 0

PDn = 
*
(1 / 2) Re Vdsn I dsn
{
}
n=0
(3-10)
n ≥1
The I dsn and Vdsn coefficients are related by
VDD − I ds 0 Z L 0
Vdsn = 
 − I dsn Z Ln
n=0
(3-11)
n ≥1
where Z Ln = Z L (nf o ) is the load impedance at the harmonic frequency nf o . The drain
harmonic power PDn can then be written as a function of I dsn and Z Ln only.
For n=0 (or DC power):
PD 0 = Vds 0 I ds 0 = (VDD − I ds 0 Z L 0 ) I ds 0
(3-12)
2
= VDD I ds 0 − I ds 0 Z L 0
2
where VDD I ds 0 is the DC power from supply and I ds 0 Z L 0 is the DC power dissipated
across Z Ln . Therefore, the DC power relationship is simply
DC power dissipated across transistor drain
= DC power from s upply − DC power dissipated across load
For n≥1
PDn
1
1
1
*
*
*
Re Vdsn I dsn = Re (− I dsn Z Ln ) * I dsn = Re − I dsn Z Ln I dsn
2
2
2
1
*
*
= − Re I dsn I dsn Z Ln
2
1
2
*
= − Re I dsn Z Ln
2
=
{
}
{
{
{
}
{
}
}
(3-13)
}
Similarly, solving for harmonic power delivered to the load, PDn
For n=0
2
PL 0 = (VDD − Vds 0 )( I ds 0 ) = VDD I ds 0 − Vds 0 I ds 0 = VDD I ds 0 − PD 0 = I ds 0 Z L 0
For n≥1
(3-14)
270
PLn
1
1
1
*
*
*
Re Vdsn (− I dsn ) = Re − (− I dsn Z Ln ) * I dsn = Re I dsn Z Ln I dsn
2
2
2
1
*
*
= Re I dsn I dsn Z Ln
2
1
2
*
= Re I dsn Z Ln
2
= − PDn
=
{
}
{
}
{
{
{
}
}
(3-15)
}
Therefore, it can be observed from (3-15) that the magnitude of the output power at
the desired harmonic frequency can be varied by controlling the magnitudes of I dsn and
Z Ln according to the desired design application (power amplifiers or frequency
multipliers). The device can be thought of as a nonlinear current generator whose output
nonlinearity can be design to exploit specific harmonics of interest.
3.2.2. Limitations on Standard Conduction Angle-based Design
Clarke and Hess [135] were one of the first to investigate harmonic generation using
Fourier analysis. The conduction angle analysis theory that they developed serves as a
groundwork in analyzing nonlinear behavior in circuits.
The resulting single-sided
clipped waveform analysis is founded on a piecewise linear model that considers only
one hard nonlinearity among the many nonlinear mechanisms of an active device. This
nonlinearity is created by the transition between the active and pinchoff or cutoff
regimes.
The intersection between these two regimes define the minimum voltage
required to create conduction of the voltage-controlled drain current source.
The conduction angle analysis theory reveals the sensitivity of I dsn to the bias and
drive parameters of the device. Moreover, optimal values of Z Ln are determined using
load-line techniques to improve the output power at the desired frequency, while
271
rejecting unwanted harmonics. Single-sided clipped-waveform conduction angle analysis
is the fundamental basis for many frequency doubler and tripler designs [118].
Although pinchoff is the primary nonlinearity of the device, frequency multiplier
designs based on the results of this analysis are gross approximations of a practical design
which must take into account excitations that can potentially excite other nonlinearities.
This assumption losses relevance when considering high power frequency multiplier
design, where extremely large signal excitations and widely varying harmonic
impedances may be required to maximize the harmonics of interest.
However, the mathematical result of the single-sided clipped waveform analysis is
vital and can be used to solve the Fourier coefficients of several other clipping
conditions, particularly, double-sided clipped waveforms.
The normalized Fourier coefficients of [135] are extremely versatile and can be
applied to any single sided-clipped waveform regardless of magnitude for analyzing its
the harmonic components. Typically, the normalized harmonic coefficient characteristic
of I dsn / I p -vs- 2φ is used as a design tool for selecting the conduction angle which
produces optimum power and conversion gain of a desired harmonic. Though useful, this
technique falls short in several ways.
First, the assumed ideal model is based on a simple linear IV characteristic void of
frequency dependent elements; a considerable simplification of a realistic device
operating at microwave frequencies.
Second, the normalized Fourier coefficients are only good for a single power output
optimum. It is not often stated that the application of the normalized I dsn / I p -vs- 2φ
characteristic only gives the absolute optimum assuming that the peak-to-peak amplitude
272
of the single-sided clipped waveform occupies the full output swing of the device. Once
this assumption is relinquished, the optimality of the conduction angle selection
deteriorates. Furthermore, unless the input power of the device is exact at all times, a
multiplier designed using this conduction angle approach will rarely operate at its
optimum. Achieving a certain conduction angle relies on the device having a specific
input bias and amplitude swing. While the biasing can be well controlled in practice, the
input excitation level may deviate from the required level. On one hand, this may cause
the peak-to-peak output to be smaller than I DSS . On the other hand it may even cause
double-sided clipping, requiring a new set of analysis equations.
Third, the conduction angles often require very specific drive conditions, some of
which cannot be obtained practically.
In order to achieve conduction angles
2φ1 =[ π , π / 2, π / 3 ] (rad/sec) while occupying the full output swing of I DSS , significantly
diverse V A and VB (and subsequent VGG ) are required as shown in Fig. 3-2. These
values may not be realizable in practice, especially for low 2φ1 . Specifically, 2φ1 ' ' '
requires a VGS ' ' ' bias which is twice that of the pinchoff voltage V p . Combined with a
large negative swing, this excitation may even cause reverse breakdown of Dgs .
273
 VB ' 
 = cos −1 (− 1) = π
VA ' 
φ1 ' = cos −1 
 VB ' ' 
π
 = cos −1 (0 ) =
V
'
'
2
 A 
φ1 ' ' = cos −1 
 VB ' ' ' 
π
 = cos −1 (0.5 ) =
V
'
'
'
3
 A 
φ1 ' ' ' = cos −1 
Fig. 3-2
Illustration of the voltage requirements to achieve certain conduction angles.
The performance criteria under consideration determines the efficacy of the
conduction angle-based design technique. Absolute output power will depend on the
harmonic component I dsn rather than the normalized I dsn / I p when the output does not
occupy the full swing. Therefore, conduction angle-based design can mislead as it may
not provide a global optimum over all bias and drive levels, especially when considering
other performance criteria for power amplifiers and frequency multipliers.
274
3.2.3. Ideal FET Models
In order to develop a complete, unified theory considering all operating regions of an
active device, an idealized model embodying the fundamental operation and nonlinear
mechanisms is necessary. Piecewise linear models can provide the generality needed to
derive these Fourier concepts.
In single-sided clipped waveform analysis, a model employing a single, hard
nonlinearity of the pinchoff regime is typically used [42][135].
Double-sided clipped waveforms created by pinchoff and the forward conduction of
Dgs have been investigated for tripler design [130] and analyzed in detail using Fourier
analysis [136]. While the double-sided clipped waveform analysis of [136] is accurate
and insightful, the time-domain parameters of [136] are often difficult to relate to the
conduction-angle-based power amplifier notation.
The development of high power
frequency multipliers can benefit from a unification of frequency multiplier theory and
power amplifier theory.
There are two additional drain-related hard nonlinearities, knee and breakdown,
which can contribute significantly to harmonic generation and distortion. Unlike power
amplifiers designed to avoid these regimes that prematurely saturate the linear output
power, frequency multipliers may benefit from exploiting them. However, little work has
been done to incorporate the knee and breakdown regimes into Fourier analysis due to the
added mathematical complexity.
Instead, harmonic balance simulations of idealized models employing all four hard
nonlinearities are used. However, these simulations are somewhat application specific
and require model descriptions which are approximate to the actual device operating
275
characteristics [137][138]. Furthermore, without the use of analytical expressions, it is
difficult to develop insight into the generation of harmonic power and develop techniques
for improving harmonic generation over a range of power input.
Here, the Fourier analysis concepts are expanded to encompass the idealized model
implementing four hard-nonlinearities: pinchoff, forward conduction, knee and
breakdown; which enclose the entire operation region of the transistor. This allows the
full exploration of nonlinear behavior for any drive level, bias or load regardless of the
device’s electrical limits.
For this treatment, only real values of Z S and Z L are considered.
A more
complicated analysis for complex values for Z S and Z L is more suited for harmonic
balance.
The idealized transistor models possessing one, two, three and four hard
nonlinearities are described next.
Model A: One hard nonlinearity (pinchoff)
Fig. 3-3
Model A with one hard nonlinearity: pinchoff.
Model A is a piecewise linear transistor model which possesses one hard nonlinearity:
pinchoff.
The model shown in Fig. 3-3 consists of a single drain-source current
component, I ds , described by the formula:
276
0
Vgs < V p

I ds (V gs ) = 
G (V gs − V p ) V p ≤ Vgs
(3-16)
where G is the constant transconductance parameter. The I ds component is a function
of Vgs only and has no Vds dependency. Since the gate of the model is open circuit and
I gs =0, it is always true that V g = V gs and the overall output current of the model I dsA is
equal to the current source I ds :
0
Vg < V p

I dsA = I ds = 
G (V g − V p ) V p ≤ V g
(3-17)
Conduction occurs only when V g is greater than V p , and I ds is equal to the difference
multiplied by G . The IV transfer characteristic of Model A is shown versus V g and
versus Vds , in Fig. 3-4a and Fig. 3-4b, respectively.
Fig. 3-4
Model A IV characteristic versus (a) V g and versus (b) Vds .
277
As shown in the IV characteristics, Model A is narrow in realism since it has no
limitation on the maximum current and is insensitive to Z S and Z L . Model A cannot
differentiate between negative and positive drain voltage and will predict positive current
flow even where there will be none in a physical device, a violation of ohms law.
Therefore it should only be used with care assuming that the device stays within the
pinchoff and active region operation.
Model B: Two hard nonlinearities (pinchoff, forward conduction)
Fig. 3-5
Model B with two hard nonlinearities: pinchoff and forward conduction.
Model B is shown in Fig. 3-5 and possesses two hard nonlinearities: pinchoff and
forward conduction of Dgs . A real-valued source impedance, Z S , which is required to
correctly facilitate the gate clipping mechanism is also shown. The drain current source
I ds implements the pinchoff nonlinearity and is the same as the one used in Model A
described by (3-16). However, unlike Model A, V gs is no longer free to rise to any value
due to the implementation of Dgs , which imposes a maximum limit on Vgs and
278
subsequently forces an upper bound on I ds . Physically, the limiting effects of Vgs and
I ds are related and coincide at around the same Vgs value.
The forward conduction characteristics of Dgs can be modeled using an idealized,
piecewise linear IV shown in Fig. 3-6a and with a corresponding nonlinear impedance
Z Dgs shown in Fig. 3-6b.
Fig. 3-6
Piecewise (a) I gs -vs- Vgs and (b) Z Dgs -vs- Vgs characteristics.
A circuit analog to this idealized characteristic consists of three subcomponents
shown in Fig. 3-7: an ideal diode that provides the rectification behavior, a resistor RD
that dictates the on-state current flow and a battery that defines the turn-on voltage, V f .
Fig. 3-7
Circuit analogue of the ideal gate-source diode.
279
Using the circuit analogue model, the gate-source voltage of the device is
Vgs = V f + (Vg − V f )
Z D + RD
Z D + RD + Z S
(3-18)
The nonlinear relationship between V g and V gs can be determined by investigating
several cases.
For V g < V f , the ideal diode is reverse biased and open circuit, or
Z D >> ( RD + Z S ) :
⇒ V gs = V f + (V g − V f ) = V g
(3-19)
For V g = V f
(3-20)
⇒ V gs = V f
For V g > V f , the ideal diode is forward biased and Z D → 0 . In the case that RD = 0 ,
(3-21)
⇒ V gs = V f
Therefore, the forward biasing of Dgs creates hard clipping which forces a limit of
V gs = V f :
V g
V gs = 
V f
Vg < V f
Vg ≥ V f
(3-22)
280
Fig. 3-8
V gs -vs- V g voltage transfer characteristic.
The V gs -vs- V g voltage transfer characteristic is shown in Fig. 3-8. Applying this
transfer characteristic to clipped waveform analysis, gives a clear understanding of the
mechanism responsible for clipping I ds to a maximum value of I DSS . The translation of
a V g sine wave into a double-sided clipped I ds wave is shown in Fig. 3-9. First, V g is
passed through the V gs -vs- V g characteristic, resulting in a V f -clipped V gs wave. This
V gs wave producing clipping due to V p when passed through the I ds -vs- V gs gain
characteristic. The outgoing I ds waveform is clipped on the bottom and top, by the V p
and V f mechanisms, respectively. Note that the presence of Z S is vital in order to allow
V gs to clip. Without it, V gs will always be equal to V g .
281
Fig. 3-9
Transformation of V g into V gs into I ds due to forward conduction.
Since the forward conduction clipping of the V gs waveform manifests itself at the
output as an upper bound on I ds , it is convenient to assimilate its effect directly into the
overall I dsB formulation.
The overall IV characteristic bounded by V p and V f , is
represented by the formula
I dsB

0
Vg < V p

= G (V g − V p ) V p ≤ V g < V f
 I
V f ≤ Vg
DSS

(3-23)
282
where
I DSS = G (V f − V p )
(3-24)
The IV transfer characteristic of Model B is shown versus V g and versus Vds , in Fig.
3-10a and Fig. 3-10b, respectively. Note that despite the established drain current limit
of I DSS , the model is still insensitive to Vds and produces inaccuracies at very high and
very low or negative drain-source voltages. Model B provides the basic requirements for
analyzing double-sided clipped waveforms.
Fig. 3-10
Model B IV characteristic versus (a) V g and versus (b) Vds .
Finally, although the effect of forward conduction on I ds appears similar to pinchoff,
the mechanism is much different in that it does not allow overdriving of the gate. In the
case of pinchoff, the gate of the FET device can be driven below V p (to some extent)
without causing gate distortion or damage to the device. However, it may be detrimental
to drive the gate above V f as it may create a large I gs when clipping Vgs . Furthermore,
283
gate distortion, desirable or not, will arise due to Vgs clipping. When investigating gatesource-generated harmonics, the full gate transfer characteristic should be used.
Model C: Three hard nonlinearities (pinchoff, forward conduction, knee)
Fig. 3-11
Model C with three hard nonlinearities: pinchoff, forward conduction, knee
Model C, as shown in Fig. 3-11, consists of a gate-source diode Dgs and drain current
I ds similar to Model B and adds a third nonlinear mechanism created by the
Vds -dependent knee voltage, Vk . A real valued load impedance, Z L , will influence the
current output when considering Vds .
Physically, when the channel is open, a lateral electric field is required to create
charge transport between the source and drain.
When Vds <0V, no current exists.
Between Vds =0V and Vds = Vk , the FET operates in a linear mode and I ds is nearly
proportional to Vds . However, once Vds > Vk , the I ds saturates and becomes less sensitive
to Vds variations. The transition between the linear and saturation regime creates the
knee nonlinearity.
284
Until now, the I ds component has been described as a function of V gs assuming a
saturation mode operation insensitive to Vds . However, it is an important realism to
implement the knee mechanism which defines the Vk that places the FET in saturation.
Under large-signal excitation, Vk defines a Vds boundary for which I ds provides linear
current. One way to model the knee is to use a simple scaling factor on I ds .
The I ds component can be described over three ranges of Vds :
For Vds < 0
(3-25)
I ds (V gs , Vds ) = 0
For 0 ≤ Vds < Vk
0
V gs < V p

I ds (V gs ,Vds ) = 
µ k G (V gs − V p ) V p ≤ V gs
where the scaling factor µ k =
(3-26)
Vds
is the ratio of Vds to the knee voltage.
Vk
For Vk ≤ Vds
0
Vgs < V p

I ds (V gs ,Vds ) = 
G (V gs − V p ) V p ≤ V gs
(3-27)
Integrating the knee effect into the overall drain formulation of Model C gives
I dsC
 0

= µ k I dsB
 I
 dsB
Vds < 0
0 ≤ Vds < Vk
(3-28)
Vk ≤ Vds
where I dsB is the overall drain current of Model B which also contains the V f -clipping
mechanism. The IV characteristics of Model C are shown versus V g and versus Vds , in
285
Fig. 3-12a and Fig. 3-12b, respectively. The figure shows the effect of the scaling factor
µ k between Vds =0V and Vds = Vk to produce the linear operating regime.
Fig. 3-12
Model C IV characteristic versus (a) V g and versus (b) Vds .
Consider the graphical translation of Vg -to- I ds -to- Vds shown in Fig. 3-13 of Model C
under large-signal, clipped operation. In the case shown, the bias, amplitude and Z L
have been selected such that under high Vg , I ds swings high and Vds swings along the
loadline until it hits the knee region. The Vds waveform can only go slightly below Vk
before clipping.
Simultaneously, I ds soft-clips since it is bound to Vds by Z L as
described in (3-11). While it may not obvious, clipping at the knee is actually due to the
transformation of the forward conduction mechanism to a value below I DSS which is
determined by Vds and Vk . This can be seen in the case that the upper curve of the IV
characteristics corresponds to Vg = V f , which slopes downward in the knee regime as
286
shown in Fig. 3-13.
Therefore, the I ds waveform distorted by the knee can be
approximated using single-sided clipped waveform analysis.
Fig. 3-13
Waveform of I ds clipped by knee region.
In cases where Z L is not real, the loadline may bend downward along the slope of the
knee. When this occurs, the I ds magnitude may ride into the knee causing a momentary
dip in the waveform, rather than simply clipping at Vds ≈ Vk . This is a principle that may
be exploited for frequency tripler development [137].
For purely real Z L , a high Vk and prolonged knee region results in a softening of the
clipping effect on I ds . Since this effect further complicates the Fourier analysis, an
important simplification is adopted to achieve a highly idealized condition in which
287
Vk → 0 . This effectively ignores the taper of the knee, and converts it into a hardclipping mechanism for I ds .
Under this circumstance, the Model C IV characteristics transform into those shown
in Fig. 3-14.
Fig. 3-14
Model C highly idealized IV characteristic versus (a) V g and versus (b) Vds .
The equivalent excitation and Z L of Fig. 3-13 applied to the model of Fig. 3-14 gives
the response shown in Fig. 3-15. The cumulative effect on I ds is a more abrupt clipping
at a slightly higher current level.
288
Fig. 3-15
Waveform of I ds clipped by high ideal knee.
In summary, under large-signal drive, Vk translates into a hard nonlinearity on Vds
and I ds which are bound together by Z L .
Model D: Four hard nonlinearities (pinchoff, forward conduction, knee, breakdown)
Model D, the complete idealized model possessing four hard nonlinearities of
pinchoff, forward conduction, knee and breakdown is shown in Fig. 3-16 and consists of
a gate-source diode, Dgs , a gate-drain diode, D gd , and drain source voltage, I ds . Realvalued Z S and Z L for allowing gate and drain voltage clipping, respectively, are also
included in the figure.
289
Fig. 3-16
Model D with four hard nonlinearities: pinchoff, forward conduction, knee,
breakdown.
As described previously, I ds is responsible for both the pinchoff and knee
mechanisms while the Dgs is responsible for forward-conduction clipping.
The
breakdown mechanism of the newly added D gd is responsible for the drain-source
breakdown regime of the overall FET.
During normal operation of the FET device, D gd will never turn on in the forward
direction since Vds > V gs and Vgd is always negative.
However, for a large enough
negative Vgd , the D gd can be pushed into reverse breakdown operation.
The IV
characteristic of D gd illustrating only cutoff and reverse breakdown is illustrated in Fig.
3-17.
Fig. 3-17
Ideal piecewise gate-drain diode reverse breakdown characteristic.
290
The I gd implementing only cutoff and the reverse breakdown mechanism can be
described by the formula
Gr (Vgd − Vr ) Vgd < Vr
I gd = 
0
Vr ≤ Vgd

(3-29)
where Vgd = Vgs − Vds and Vr is the negative-valued reverse breakdown voltage.
Inspecting Fig. 3-16, the overall drain current
I dsD = I ds − I gd
(3-30)
Therefore, the IV characteristics of Model D are the same as Model C until the transistor
is biased such that the breakdown condition of Vgd < Vr is satisfied. Once breakdown
occurs, I dsD will increase sharply with Vds .
In Fig. 3-18a, the Vgd = Vr instances are identified as corner points marked on the IV
characteristics of Model D. These points are staggered with respect to each IV trace
shown since each trace corresponds to a different Vgs . For example, the IV trace at
Vgs = V p is significantly negative. Therefore, a lower Vds is needed to cause the gate-
drain diode to break down, since Vgd = Vgs − Vds . On the other hand, for the IV trace at
Vgs = V f , under the assumption that V f =0V, a higher Vds is needed to break down the
gate-drain diode.
The behavior of this nonlinearity is somewhat complex and cannot be easily lumped
into an overall drain current equation as is done for the additive nonlinearities of Model B
and Model C. Therefore, a simplification of this breakdown effect on IV behavior is
adopted. Let the IV characteristics with breakdown be approximated by the IV curves
291
shown in Fig. 3-18b.
The breakdown region has now been defined to resemble a
response similar in geometry to the knee nonlinearity. Despite the visual difference
between Fig. 3-18a and Fig. 3-18b, the behavior described in Fig. 3-18b is not a large
departure from the real breakdown characteristics of FET devices.
The benefit of this approximation is that the overall drain current can now be
expressed more concisely with respect to Vds . First, two important points are defined on
Fig. 3-18b. The Vds at the onset of breakdown is the FET breakdown voltage of VBV .
The Vds at which I ds = I DSS for all Vgs values under breakdown is equal to VDSS . One
more thing to note about this plot is that the point VDSS = −Vr of the D gd IV characteristic
if V f =0V is assumed.
Fig. 3-18
IV characteristics employing (a) the gate-drain diode breakdown model and
(b) approximation of the breakdown effect.
The overall drain current of Model D can be defined under this abstraction of the IV
characteristics
292
I dsD
where µ BV =
0


µ k I dsB

=
I dsB
(1 − µ ) I + µ I
BV
dsB
BV DSS


I DSS
Vds ≤ 0
0 ≤ Vds < Vk
Vk ≤ Vds < VBV
(3-31)
VBV ≤ Vds < VDSS
VDSS < Vds
Vds − VBV
is the ratio of Vds in between VDSS and VBV .
VDSS − VBV
The four-nonlinearity Model D behaves exactly the same as Model A and Model B
when the entire swing of Vg does not cause the Vds swing to impinge on the knee or
breakdown regions as shown in Fig. 3-19 (black colored trace). However, consider
Model D under large signal drive (red-colored trace) also shown in Fig. 3-19. The bias,
amplitude and Z L has been set such that as Vg swings low and I ds swings low, Vds
swings high along the loadline and soft-clips as it rises above Vk . At the same time I ds
also soft-clips due to its Z L -defined relationship with Vds . Therefore, the resulting I ds
may be interpreted and analyzed as a prematurely clipped single-sided waveform with a
minimum clipped level above zero.
293
Fig. 3-19
Waveform of I ds clipped by breakdown region.
Much like the case with the knee region, it is desirable for the sake of Fourier analysis
to simplify the breakdown regime of the model by converting it into a hard nonlinearity.
This is done by adopting the condition in which VDSS → VBV . Coupling this with the
prior simplification that Vk → 0 results in the highly idealized IV characteristics for
Model D shown in Fig. 3-20.
294
Fig. 3-20
Model D highly idealized IV characteristic versus (a) V g and versus (b) Vds .
Applying the large signal excitation of Fig. 3-19 on the highly idealized Model D of
Fig. 3-20 gives the transient responses shown in Fig. 3-21. Although different from the
less idealized one, the results are not a major departure in terms of the main clipping
behavior.
295
Fig. 3-21
Waveform of I ds clipped by high ideal breakdown region.
In summary, the drain source nonlinearities of the knee and breakdown result in
clipping of the Vds waveform, that, when referred to I ds through a real load impedance,
Z L , creates modified clipping mechanisms for I ds . This is similar to how the clipped Vgs
waveform due to the gate-source diode is manifested onto I ds in the form of an upper
limit I DSS .
3.2.4. Fourier Analysis of Ideal Operating Modes
For the purposes of this analysis, the highly idealized Model D is considered the
complete model used for the ensuing Fourier analyses, since it encapsulates the entire
operation of the transistor.
296
The four hard nonlinearities defined by Model D consisting of V p , V f , Vk and VBV
are identified in Fig. 3-22 can either be excited individually or in combinations by
configuration of the amplitude, bias and impedance to exploit a specific operating
condition.
Fig. 3-22
Four hard nonlinearities of Model D and the associated double-sided clipped
waveform pairs using real Z L .
This work proceeds by analyzing each operation mode. The possible operation cases are:
Single-sided clipped:
V p -clipped
V f -clipped
Vk -clipped
VBV -clipped
Double-sided clipped:
V p / V f -clipped
297
Vk / V p -clipped
VBV / V f -clipped
Vk / VBV -clipped
Unclipped:
Linear
Complete pinchoff
Complete forward conduction
Complete knee
Complete breakdown
Also, the ensuing analysis assumes that the models have no electrical limits and V gs
and Vds can be driven to any voltage level without causing catastrophic damage to the
device.
3.2.4.1.
Single-sided Clipped
V p -clipped
When the input sinusoid causes the device to cross between the pinchoff and linear
operating region, creating partial conduction over the waveform cycle, it is V p -clipped.
This condition can be characterized using single-sided clipped waveform analysis. The
definitions for the single-sided V p -clipped waveform are provided in Fig. 3-23.
298
Vp ≤ (VGG + VA) ≤ Vf
Ids
Ids
(VGG - VA) ≤ Vp
0 ≤ 2φ1 ≤ 2π
IDSS
slope G
2φ1
VB
Ip1
VGG
Vp
Vf
Vg
-π
0
π
Ip
2π
ωt
I DSS = G (V f − V p )
φ1
Vg
VA
V g = VGG + V A cos ωt
I p1 = G(V A − VB )
φ1 = cos −1 (VB V A )
VB = V p − VGG
ωt
Fig. 3-23
V p -clipped waveform analysis.
The conditions for the V p -clipped operation are V p ≤ (VGG + V A ) ≤ V f
and
(VGG − V A ) ≤ V p . The key definitions for the single-sided clipped wave are
I p1 = G (V A − VB )
(3-32)
φ1 = cos −1 
 VB 

 VA 
(3-33)
VB = (V p − VGG )
(3-34)
where I p1 is the peak amplitude of the Fourier tips and 2φ1 is the conduction angle.
299
The derivation of the single-sided Fourier coefficients is described in Appendix B.2.
The resulting Fourier series coefficients of the single-sided clipped waveform are
I dsn
 I p1 sin φ1 − φ1 cos φ1

1 − cos φ1
π
 I p1 φ1 − cos φ1 sin φ1
=
1 − cos φ1
π
 2 I p1 cos φ1 sin( nφ1 ) − n sin φ1 cos(nφ1 )

n(n 2 − 1)(1 − cos φ1 )
 π
n=0
n =1
(3-35)
n≥2
These Fourier coefficients serve as a building block for the analysis of several other
operating modes. The formulas are implemented in Matlab to investigate the normalized
magnitude versus conduction angle.
The I dsn / I p -vs- 2φ1 characteristics for four
harmonics are shown in Fig. 3-24 where I p = I p1 , the peak-to-peak amplitude of I ds .
These plots are the standard conduction angle curves provided in [42] and [135].
As done in [135], the derivation of these Fourier coefficients is performed using a
constant V A = (V f − V p ) / 2 amplitude and passing the device into various conduction
angles by sweeping VB = V A to VB = − V A . The normalized coefficients are then solved
by dividing the Fourier coefficients by I p .
The unnormalized Fourier coefficients corresponding to this technique may also
prove useful in determining the output magnitude of I dsn when the I ds waveform does
not occupy the full output swing. However, the maximum current level I DSS is extremely
device specific.
Therefore, to generalize the meaning of the unnormalized Fourier
coefficients, they are instead normalized to the device specific parameter I DSS . The
Fourier coefficients I dsn / I DSS removes the full swing condition but allows applicability
to any device.
300
The I dsn / I DSS -vs- 2φ1 curves using V A = (V f − V p ) / 2 as VB is swept into different
conduction angles are shown in Fig. 3-24. The plot also includes the DC component,
I ds 0 , which may provide insight in investigating harmonic conversion efficiency.
Application of these curves is performed by multiplying them by the I DSS of the device
under study. These curves also show that an optimum conduction angle observed under
I dsn / I p may not be optimal without the full-swing condition. For example, I ds 3 / I p
appears to maximum at 2φ1 =1.4 (rad/sec). However, under a fixed V A = (V f − V p ) / 2
condition, there are two conduction angles which provide equivalent, and rather low,
third harmonic I ds 3 / I DSS : 2φ1 =2.1 and 4.2 (rad/sec).
301
n=1
n=2
n=3
n=4
(a)
n=1
n=0
n=2 n=3
n=4
(b)
Fig. 3-24
V p -clipped Fourier coefficients for four harmonics (a) I dsn / I p1 -vs- 2φ1 and
(b) I dsn / I DSS -vs- 2φ1 .
302
V f -clipped
When device driven with a sine wave is pushed between linear and forward
conduction operation, it will partially saturate at a maximum value of I DSS . The result is
a single-sided V f -clipped waveform which can be analyzed using (3-35) when employed
as an expression describing Fourier tips. The generation of the V f -clipped waveform is
illustrated in Fig. 3-25.
Vp ≤ (VGG - VA) ≤ Vf
Ids
Vf ≤ (VGG + VA)
0 ≤ 2φ2 ≤ 2π
Ip2
Ids
VC
IDSS
2φ2
Ip
slope G
Vp
Vf
VGG
Vg
-π
0
π
2π
I DSS = G (V f − V p )
φ2
Vg
VA
Vg = VGG + VA cos ωt
I p 2 = G (VA − VC )
φ2 = cos −1 (VC VA )
VC = V f − VGG
I p = G (V A + VC )
ωt
Fig. 3-25
V f -clipped waveform analysis.
ωt
303
The conditions for the V f -clipped operation are that V p ≤ (VGG − V A ) ≤ V f and
V p ≤ (VGG − V A ) .
One way to represent the forward-conduction clipped waveform using Fourier series
is to interpret it as a linear waveform minus the Fourier tips of a single-sided clipped
waveform. This allows the application of (3-35) in determining the coefficients for this
case.
First, the “overdrive” angle, 2φ 2 , is defined as the fraction of the waveform period
during which the Dgs is pushed into forward conduction operation, thus overdriving the
transistor. The parameter φ 2 is identified in Fig. 3-25 and is defined by
 VC 

V
 A
φ2 = cos−1 
(3-36)
VC = V f − VGG ⇒ VGG = V f − VC
(3-37)
where
Additionally, an overdrive current I p 2 is defined as the amplitude of the imaginary
clipped Fourier tips that occur during the overdrive interval and is also shown in Fig.
3-25.
I p 2 = G (VA − VC )
(3-38)
By introducing these definitions, the resulting waveform for the single-sided V f -clipped
waveform can be written as
I ds (t ) = I ds ' (t ) − I ds " (t )
(3-39)
where I ds ' (t ) represents the linear drain current assuming no clipping and I ds " (t )
represents the clipped Fourier tips above V f .
304
The linear drain current can be written as
I ds ' (t ) = G (VGG − V p + VA cos ωt ) = G (VGG − V p ) + GVA cos ωt
(3-40)
1
= ∑ I dsn ' cos(nωt )
n =0
with the Fourier coefficients (See Chapter 3.2.4.3)
I ds 0 ' = G (VGG − V p )
(3-41)
I ds1 ' = GVA
(3-42)
I dsn ' = 0
n≥2
(3-43)
The clipped Fourier waveform tips follow from the single-sided clipped waveform
coefficients but defined using the φ2 and I p 2 current:
∞
I ds " (t ) = ∑ I dsn " cos(nωt )
(3-44)
n= 0
I ds 0 "
=
I p 2 sin φ2 − φ2 cos φ2
π
1 − cosφ2
(3-45)
I ds1"
=
I p 2 φ2 − cos φ2 sin φ2
1 − cosφ2
π
(3-46)
I dsn "
=
2 I p 2 cosφ2 sin(nφ2 ) − n sin φ2 cos(nφ2 )
π
n(n 2 − 1)(1 − cosφ2 )
n≥2
(3-47)
Therefore, total waveform becomes the subtraction of I ds " (t ) from I ds ' (t )
I ds (t ) = I ds ' (t ) − I ds " (t )
1
∞
n =0
n =0
= ∑ I dsn ' cos(nωt ) − ∑ I dsn " cos(nωt )
∞
= I ds 0 '+ I ds1 ' cos ωt − I ds 0 "− I ds1" cos ωt − ∑ I dsn " cos(nωt )
n= 2
∞
= ( I ds 0 '− I ds 0 " ) + ( I ds1 '− I ds1" ) cos ωt − ∑ I dsn " cos(nωt )
n =2
(3-48)
305
and the Fourier series coefficients for I ds are
I ds 0
= I ds 0 '− I ds 0 "
(3-49)
I ds1
= I ds1 '− I ds1"
(3-50)
I dsn
= − I dsn "
(3-51)
Before proceeding with solving for these coefficients, it is convenient to make the
following definitions as is done for the V p -clipped case. First, VC can be expressed in
terms of VA and vice-versa
 VC 
V
 ⇒ cosφ2 = C
VA
 VA 
φ2 = cos−1
⇒ VC = VA cosφ2
⇒ VA =
VC
cosφ2
(3-52)
(3-53)
Then, GVA can be expressed in terms of I p 2 and φ2 .
I p 2 = G (VA − VC ) = G (VA − V A cos φ2 ) = GVA (1 − cos φ2 )
⇒ GVA =
I p2
1 − cosφ2
(3-54)
and similarly for GVC
 V

 1

 1 − cos φ2 

I p 2 = G (VA − VC ) = G  C − VC  = GVC 
− 1 = GVC 
 cos φ2

 cos φ2

 cos φ2 
 cos φ2 

⇒ GVC = I p 2 
 1 − cos φ2 
(3-55)
Also, note that
I DSS = G (V f − V p )
(3-56)
306
For n=0,
I ds 0
= I ds 0 '− I ds 0 "
I p 2 sin φ 2 − φ 2 cosφ2
1 − cosφ 2
π
I p 2 sin φ 2 − φ 2 cosφ 2
= G (V f − VC − V p ) −
1 − cosφ 2
π
= G (VGG − V p ) −
= G (V f − V p ) − GVC −
I p 2 sin φ2 − φ 2 cosφ 2
1 − cosφ 2
π
 cosφ 2  I p 2 sin φ2 − φ 2 cosφ 2
 −
= I DSS − I p 2 
1 − cosφ 2
 1 − cosφ 2  π
I p 2  π cosφ2 sin φ 2 − φ2 cosφ 2 


= I DSS −
+
1 − cosφ2
π  1 − cosφ2

I p 2  π cosφ 2 + sin φ2 − φ 2 cosφ 2 


1 − cosφ 2
π 

I p 2  sin φ2 − (φ2 − π ) cosφ 2 


−
π 
1 − cosφ 2

= I DSS −
= I DSS
(3-57)
For n=1,
I ds1
= I ds1 '− I ds1"
= GV A −
=
I p 2 φ 2 − cos φ 2 sin φ 2
π
1 − cos φ 2
I p2
1 − cosφ 2
−
I p 2 φ2 − cosφ 2 sin φ 2
π
1 − cosφ 2
I p2 
π
φ − cosφ 2 sin φ 2 


− 2
π  1 − cosφ 2
1 − cos φ 2

I p 2  π − φ 2 + cos φ 2 sin φ 2 


=
π 
1 − cos φ 2

I p 2  (φ 2 − π ) − cos φ 2 sin φ2 


=−
π 
1 − cos φ2

=
Finally, for n>1
(3-58)
307
= − I dsn "
I dsn
=−
(3-59)
2 I p 2 cosφ2 sin( nφ2 ) − n sin φ2 cos(nφ2 )
π
n(n 2 − 1)(1 − cos φ2 )
In summary,
I dsn

I p 2  sin φ2 − (φ2 − π ) cos φ2 


 I DSS −
π 
1 − cos φ2


 I  (φ − π ) − cos φ sin φ 
 p2
2
2
 2

= −
π
φ
1
−
cos

2


 2 I cos φ sin( nφ ) − n sin φ cos(nφ )
2
2
2
2
− p 2
2
π
(
1
)(
1
cos
φ
)
n
n
−
−

2
n=0
n =1
(3-60)
n≥2
It is extremely important to note that the peak-to-peak amplitude of the conducting
waveform is equal to
I p = G (VA + VC )
(3-61)
This is necessary to retain continuity with the other waveform cases (single-sided,
pinchoff waveform case).
The V p -clipped Fourier coefficients are plotted using Matlab across overdrive angle.
The I dsn / I p -vs- 2φ 2 and I dsn / I DSS -vs- 2φ 2 characteristics for four harmonics is shown in
Fig. 3-26a and Fig. 3-26b, respectively. The coefficient characteristics of Fig. 3-26 are a
mirror images of the single-sided V p -clipped characteristics of Fig. 3-24, which provide
several other options for biasing the device to achieve optimum output of a particular
harmonic. The one important difference is the DC component, or I ds 0 / I DSS , which
continually increases for increasing 2φ 2 as shown in Fig. 3-26b.
308
n=1
n=2
n=3
n=4
(a)
n=0
n=1
n=2
n=3
n=4
(b)
Fig. 3-26
V f -clipped Fourier coefficients for four harmonics (a) I dsn / I p -vs- 2φ 2 and
(b) I dsn / I DSS -vs- 2φ 2 .
309
Vk -clipped
Knee clipping occurs when the a combination of the bias, gate amplitude and load
impedance causes the drain-source voltage waveform to coincide with the knee region
when swinging along the loadline. Under this Vk -clipped condition, Vds cannot pass
below Vk (zero for high ideal Model D) and I ds reaches a maximum current less than
I DSS .
The generation of the single-sided Vk -clipped waveform is illustrated in Fig. 3-27. In
this example, the gate is biased midway between V p and V f and the large V A causes Vds
to clip at the ideal knee.
I DSS ,eff = VDD Z L
Vg = VGG + V A cos ωt
I p 2,eff = G (V A − VC ,eff )
φ2,eff = cos−1 (VC ,eff V A )
VC ,eff = V f ,eff − VGG
I p = G (V A + VC ,eff )
Fig. 3-27
Vk -clipped waveform analysis.
310
Examination of I ds suggests that this single-sided upper-clipped waveform resembles
the V f -clipped case. Therefore, by making the proper definitions for the Vk -clipped
waveform, the Fourier coefficient equations of (3-60) can be applied here.
First, the reduced I ds upper bound, I DSS ,eff , is defined at the point where the loadline
coincides with the ideal or “hard” knee as shown in Fig. 3-27 giving
I DSS ,eff =
VDD − Vk VDD
=
ZL
ZL
(3-62)
Then, this I DSS ,eff point can be mapped back to the gate voltage to define an effective
forward conduction voltage, V f ,eff .
I DSS ,eff = G (V f ,eff − V p )
⇒ V f ,eff =
I DSS ,eff
G
+ Vp =
VDD
+Vp
GZ L
(3-63)
Although the drain-source referred condition for any type of Vk clipping is
(VDD − G(VGG + VA )Z L ) ≤ Vk , it
reference to V f ,eff .
is convenient to define the gate excitation conditions in
Therefore, the two conditions for single-sided Vk -clipping are
V f ,eff ≤ (VGG + VA ) and V p ≤ (VGG − V A ) ≤ V f ,eff .
The properties of the Vk -clipped
waveform can now be defined as
I p 2, eff = G (VA − VC , eff )
 VC , eff
 VA
φ2, eff = cos−1 
VC ,eff = V f ,eff − VGG



(3-64)
(3-65)
(3-66)
311
Applying (3-60) with the appropriate substitutions gives the Fourier coefficients for the
single-sided Vk -clipped condition:
I dsn

I p 2,eff  sin φ2,eff − (φ2,eff − π ) cos φ 2,eff 


I DSS ,eff −

1 − cos φ 2,eff
π 


 I


 p 2,eff  (φ 2,eff − π ) − cos φ 2,eff sin φ2,eff 
= −

1 − cos φ2,eff
π 


 2I
cosφ 2,eff sin( nφ 2,eff ) − n sin φ 2,eff cos(nφ 2,eff )
− p 2,eff
π
n(n 2 − 1)(1 − cos φ 2,eff )

n=0
n =1
(3-67)
n≥2
Note that the main difference between the Vk -clipped case and the V f -clipped case is
the reduced available swing range of I DSS ,eff which leads to comparatively lower
harmonic output. Similar to the V f -clipping case, it is important to maintain that
I p = G (V A + VC ,eff )
(3-68)
by definition of the peak-to-peak I ds amplitude. Using (3-65), (3-67) and (3-68) allows
the application of Fig. 3-26 for the Vk -clipped case.
VBV -clipped
Breakdown clipping occurs when the device bias, amplitude and load are configured
in such a way that the drain source waveform coincides with the breakdown region of the
device defined by VBV . The waveform Vds is not allowed to swing above VBV and
therefore causes it to clip at that value. At the same time, I ds experiences an unexpected
minimum limit above zero.
An example of a single-sided VBV -clipped waveform generation is shown in Fig.
3-28. In this example, the device gate is biased midway between V p and V f . Under
312
large V A , Vds swings high but is confronted by the limitation imposed by VBV . This
translates into a lower clipped I ds waveform.
I DSS = G (V f − V p )
V g = VGG + V A cos ωt
I p1,eff = G (VA − VB ,eff )
φ1,eff = cos −1 (VB ,eff V A )
VB ,eff = V p ,eff − VGG
I 0 = (VDD − VBV ) Z L
Fig. 3-28
VBV -clipped waveform analysis.
Investigation of the VBV -clipped case reveals that the resulting single-sided clipped
I ds waveform resembles a V p -clipped waveform that has been shifted up by a new
minimum I ds value of I 0 :
I ds = I ds (V p clipped ) + I 0
(3-69)
Therefore, by defining I 0 and establishing the proper definitions based on this revised
lower bound of I ds , equation (3-35) can be modified and applied here.
The value of I 0 is determined by inspecting the point where loadline intersects the
ideal or “hard” breakdown mechanism shown in the IV characteristics of Fig. 3-28.
313
I0 =
VDD − VBV
ZL
(3-70)
The I 0 point can then be mapped back to the I ds -vs- Vg characteristic to find a
corresponding gate voltage, indicative of VBV -clipped operation. This effective pinchoff
voltage, V p ,eff is
I 0 = G (V p ,eff − V p )
⇒ V p,eff =
I0
V − VBV
+ V p = DD
+Vp
G
GZ L
(3-71)
The drain-source referred condition for any clipping due to breakdown is
VBV ≤ (VDD − G (VGG − V A ) Z L ) . However, this condition can be defined based on the
gate-referred voltage V p ,eff .
Therefore, single-sided VBV -clipping occurs when
(VGG − V A ) ≤ V p, eff and V p,eff ≤ (VGG + V A ) ≤ V f . Now, the properties of the VBV -clipped
waveform can be defined as
I p1, eff = G (V A − VB ,eff )
 VB ,eff
 VA
φ1,eff = cos −1 
VB ,eff = V p ,eff − VGG



(3-72)
(3-73)
(3-74)
Applying the Fourier coefficient equations of (3-35) for the VBV -clipped case using the
above definitions gives
314
I dsn

I p1,eff sin φ1,eff − φ1,eff cos φ1,eff
I 0 +
π
1 − cos φ1,eff

 I p1,eff φ1,eff − cos φ1,eff sin φ1,eff
=
1 − cos φ1,eff
 π
 2 I p1,eff cos φ1,eff sin( nφ1,eff ) − n sin φ1,eff cos(nφ1,eff )

n(n 2 − 1)(1 − cos φ1,eff )
 π
n=0
n =1
(3-75)
n≥2
Note that the main difference in these Fourier coefficients is the addition of I 0 to
I ds 0 , since I 0 is a DC value. However, in comparison with the V p -clipped case, the
VBV -clipped case has less swing is available for I ds to occupy, thus reducing the
maximum harmonic output capability. Importantly, the modified peak-to-peak amplitude
of I ds is simply
I p = I p1,eff
(3-76)
Using (3-73), (3-75) and (3-76) allows the application of Fig. 3-24 for the VBV -clipped
case.
3.2.4.2.
Double-sided Clipped
V p / V f -clipped
If the device conducts current for a portion of the input waveform cycle, and during
that duration, D gs is pushed into forward conduction, a double-sided clipped waveform
condition will arise. This V p / V f -clipped waveform case can be caused by a combination
of input amplitude, bias and load impedance.
To aid in the analysis, it is helpful to imagine that a double sided-clipped I ds
waveform, that is, a waveform clipped at its top and bottom, is a construct of a single-
315
sided clipped waveform subtracted from another single-sided clipped waveform as shown
in Fig. 3-29.
Fig. 3-29
Composition of a double sided clipped waveform using two single-sided
clipped waveforms.
By disassembling the double-sided sided clipped waveform into two constituent parts,
its Fourier components can be analyzed using the pre-existing formulas for single-sided
clipped waveform analysis.
The illustration of the V p / V f -clipped waveform excitation is shown in Fig. 3-30. It
can be observed that φ1 and φ2 are not completely independent and that φ 2 ≤ φ1 . Also,
note that the double-sided clipped condition requires that the peak-to-peak amplitude of
I ds always fits the full swing transistor output characteristics, or I p = I DSS .
316
I DSS = G (V f − V p )
Vg = VGG + VA cos ωt
I p1 = G (V A − VB )
φ1 = cos −1 (VB VA )
VB = V p − VGG
I p 2 = G (VA − VC )
φ2 = cos −1 (VC VA )
VC = V f − VGG
I p = I p1 − I p 2
Fig. 3-30
V p / V f -clipped waveform analysis.
The V p / V f -clipped waveform can be expressed as a difference between two singlesided clipped waveforms
I ds (t ) = I ds ' (t ) − I ds " (t )
where
I ds ' (t ) is the single-sided clipped waveform above V p
I ds " (t ) is the single-sided clipped waveform Fourier tips above V f
The waveforms of I ds ' (t ) and I ds " (t ) are
(3-77)
317
∞
I ds ' (t ) = ∑ I dsn ' cos nωt
(3-78)
n= 0
and
∞
I ds " (t ) = ∑ I dsn " cos nωt
(3-79)
n =0
where the Fourier coefficients can be represented by the single-sided analysis of (3-35).
The total double-sided clipped waveform is therefore equal to
∞
∞
∞
n= 0
n =0
n= 0
I ds (t ) = ∑ I dsn ' cos nωt − ∑ I dsn " cos nωt = ∑ ( I dsn '− I dsn " ) cos nωt
(3-80)
The relationships of (3-32), (3-33), (3-34), (3-38), (3-36), (3-37) and can be defined for
conduction and overdrive modes of the double-sided clipped waveform and are identified
in Fig. 3-30.
In previous analyses, there exists either 2φ1 conduction angle or 2φ 2 overdrive angle,
not both. However, for the double-sided clipped waveform case, both φ1 and φ2 are
present simultaneously and can be defined in terms of V A , VB and VC :
 VB 

V
 A
φ1 = cos−1 
⇒ VB = VA cos φ1
⇒ VA =
VB
cos φ1
(3-81)
(3-82)
and
 VC 

 VA 
φ2 = cos−1 
⇒ VC = VA cos φ2
(3-83)
318
⇒ VA =
VC
cos φ2
(3-84)
The voltages VB and VC can also be related to the transistor parameters V f and V p .
VB = V p − VGG ⇒ VGG = V p − VB
⇒ VC = V f − VGG = V f − Vp + VB
(3-85)
The objective of this analysis, much like the single-sided clipped waveform case, is to
produce a three dimensional characteristic which portrays the Fourier coefficients as
functions of the conduction and overdrive angles, or I dsn -vs-{ φ1 , φ2 }. Together { φ1 , φ2 }
will be called the “operating angle.” From this characteristic, the optimal { φ1 , φ2 } that
induce the maximum production of the desired harmonic power can be selected.
In order to explore all combinations of φ1 and φ2 , their values need to be translated
into VA and VB ( VC optional) excitations for the ideal model, giving rise to two
possibilities:
Method 1: VA is constant, I p and VB are variable functions of φ1 and φ2 . This
assumption requires that I p changes to accommodate a desired { φ1 , φ2 }
combination.
This is like the derivation for single-sided clipped Fourier
coefficients but slightly awkward since the model parameters are not modifiable
in practice.
Method 2: I p is constant, VA and VB are variable functions of φ1 and φ2 . This
method is a more natural approach and is analogous to the designation of an
amplitude ( VA ) and bias level ( VB ) combination, rather than the modification of
the device parameter I DSS .
319
Both methods produce the correct mathematical result.
Method 1: VA constant, I p and VB (or VC ) vary with { φ1 , φ2 }
The constant VA case is important because this is the method by which the standard
single-sided Fourier analysis is first developed [135].
In the single-sided clipped
waveform derivation, VA is constant, and the bias level VB is swept to push the drain
current into different angles of conduction. At the same time, I p increases and serves as
normalizing parameter so that the optimal conduction angle can be found regardless of
transistor characteristics.
Similarly, use of a fixed VA to achieve a double-sided clipped waveform assumes that
I p = I DSS is changing to accommodate a specific { φ1 , φ2 }, since the I DSS level is
responsible for clipping the upper portion of the waveform. The approach using the
constant VA assumption is illustrated in Fig. 3-31 for four different operating angles
{ φ1 , φ2 }.
These four cases illustrate how I p = I DSS is varied for a constant VA to
accommodate the desired operating angles of { π / 2 , 0 }, { π , 0 },{ π , π / 2 } and { π , π }
as shown in Fig. 3-31a, b, c, d, respectively.
320
Ids
φ1=π/2
φ2=0
Ids
φ1=π
φ2=0
2φ1
2φ2
2φ1
Ip
Ip
2φ2
-π
0
π
2π
3π ωt
-π
0
(a)
φ1=π
φ2=π/2
φ1=π
φ2=π
2φ1
Ip
2φ2
π
2π
3π ωt
(c)
Fig. 3-31
3π ωt
Ids
2φ1
0
2π
(b)
Ids
-π
π
2φ2
-π
0
Ip
π
2π
3π ωt
(d)
Generation of operating angles { φ1 , φ 2 } using the constant V A derivation (a)
{ π / 2 , 0 } (b) { π , 0 } (c) { π , π / 2 } (d) { π , π }.
Letting VA = 1 and solving I p1 and I p 2 using (3-32) and (3-81), (3-38) and (3-83)
gives
I p1 = G (V A − VB ) = G (1 − cos φ1 )
(3-86)
I p 2 = G (VA − VC ) = G (1 − cos φ2 )
(3-87)
By definition
I p = I p1 − I p 2 = G (1 − cos φ1 ) − G (1 − cos φ2 ) = G (cos φ2 − cos φ1 ) = I DSS
⇒G=
I DSS
cos φ2 − cos φ1
Therefore, using (3-86), (3-87), (3-88) gives
(3-88)
321
I p1 = I DSS
1 − cos φ1
cos φ 2 − cos φ1
(3-89)
I p 2 = I DSS
1 − cos φ 2
cos φ 2 − cos φ1
(3-90)
The Fourier coefficients of the V p / V f -clipped waveform can be solved from (3-80).
For n=0
I ds 0 = I ds 0 '− I ds 0 "
 I sin φ1 − φ1 cos φ1   I p 2 sin φ2 − φ2 cos φ2 
 − 

=  p1
1 − cos φ1
1 − cos φ2
π
  π

I
1 − cos φ1 sin φ1 − φ1 cos φ1
= DSS
π cos φ2 − cosφ1 1 − cosφ1
−
=
(3-91)
1 − cos φ2 sin φ2 − φ2 cos φ2
π cos φ2 − cosφ1
1 − cos φ2
I DSS
I DSS sin φ1 − φ1 cos φ1 − sin φ2 + φ2 cos φ2
π
cos φ2 − cos φ1
For n=1
I ds1
= I ds1 '− I ds1"
 I φ − cos φ1 sin φ1   I p 2 φ2 − cos φ2 sin φ2 
 − 

=  p1 1
1 − cos φ1
1 − cos φ2
π
  π

I
1 − cos φ1 φ1 − cos φ1 sin φ1
= DSS
π cos φ2 − cosφ1 1 − cosφ1
−
=
For n≥2
1 − cos φ2 φ2 − cos φ2 sin φ2
π cos φ2 − cosφ1
1 − cos φ2
I DSS
I DSS φ1 − cos φ1 sin φ1 − φ2 + cos φ2 sin φ2
π
cos φ2 − cos φ1
(3-92)
322
= I dsn '− I dsn "
I dsn
=
2 I p1 cos φ1 sin nφ1 − n sin φ1 cos nφ1
π
n(n 2 − 1)(1 − cos φ1 )
−
=
2 I DSS
π
1 − cos φ1 cos φ1 sin nφ1 − n sin φ1 cos nφ1
cos φ2 − cos φ1
n(n 2 − 1)(1 − cos φ1 )
−
=
2 I DSS
π
2 I p 2 cos φ2 sin nφ2 − n sin φ2 cos nφ2
π
n(n 2 − 1)(1 − cos φ2 )
2 I DSS
(3-93)
1 − cos φ2 cos φ2 sin nφ2 − n sin φ2 cos nφ2
cos φ2 − cos φ1
n(n 2 − 1)(1 − cos φ2 )
π
cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ2 sin nφ2 + n sin φ2 cos nφ2
n(n 2 − 1)(cosφ2 − cos φ1 )
Although mathematically sound, this derivation may feel unrealistic since I DSS has been
manipulated to achieve a double-sided clipped waveform of interest. For a specific
device, I DSS is a determined by the physical properties and cannot be altered.
Method 2: I p constant, VA and VB (or VC ) vary with { φ1 , φ2 }
The second method for deriving the Fourier coefficients of the double-sided clipped
waveform is performed here. In this method, I p = I DSS is a fixed parameter and drive
voltages VA and VB are identified for desired operating angles of interest, { φ1 , φ2 }. The
approach using the constant I p assumption is illustrated in Fig. 3-32 for four different
bias angles { φ1 , φ2 }. Drive angles of { π / 2 , 0 }, { π , 0 },{ π , π / 2 } and { π , π } are
shown in Fig. 3-32a, b, c, d, respectively, and can be compared to the illustrations of Fig.
3-31.
323
Ids
Ids
φ1=π/2
φ2=0
2φ1
2φ1
Ip
2φ2
-π
0
φ1=π
φ2=0
π
2π
3π ωt
-π
0
(a)
2φ1
3π ωt
φ1=π
φ2=π
2φ1
Ip
2φ2
π
2π
Ip
2φ2
3π ωt
(c)
Fig. 3-32
2π
Ids
φ1=π
φ2=π/2
0
π
(b)
Ids
-π
Ip
2φ2
-π
0
π
2π
3π ωt
(d)
Generation of operating angles { φ1 , φ 2 } using the constant Ip derivation (a)
{ π / 2 , 0 } (b) { π , 0 } (c) { π , π / 2 } (d) { π , π }.
The first objective is to express VA , VB and VC in terms of φ1 , φ2 and the known
device parameters without any prior assumptions. This is done so that for a given
{ φ1 , φ2 }, VA and VB can be computed rather than requiring a change in I DSS .
First, expressing V f − V p as a function of I DSS
I DSS = G (V f − V p ) ⇒ V f − V p =
I DSS
G
Next VA is expressed as a function of VB and φ2 using (3-84), (3-85) and (3-94)
(3-94)
324
⇒ VA =
V f − VGS V f − (V p − VB ) V f − V p + VB
VC
=
=
=
cosφ 2
cos φ2
cos φ2
cos φ2
(3-95)
I
 1
=  DSS + VB 
 G
 cosφ2
Then VB can be expressed as a function of φ1 and φ2 using (3-81) and (3-95)
 cos φ1
I
 cos φ1 
 ⇒ VB 1 −
VB = V A cos φ1 =  DSS + VB 
 G
 cos φ 2 
 cos φ 2
VB =
 I DSS  cos φ1
 =

G  cos φ 2




I DSS cosφ1
cos φ2
G cosφ 2 cos φ2 − cos φ2
⇒ VB =
I DSS
cos φ1
G cos φ 2 − cos φ1
(3-96)
Following this, V A is also expressed as a function of φ1 and φ2 using (3-95) and (3-96)
VA
I
 1
cos φ1
I

=  DSS + DSS
G cos φ 2 − cos φ1  cos φ 2
 G
 1

cos φ1
I

= DSS 1 +
G  cos φ 2 − cos φ1  cos φ 2
 cos φ 2 − cos φ1 + cos φ1  1


cos φ 2 − cos φ1

 cos φ 2

 1
cos φ 2
I

= DSS 
G  cos φ 2 − cos φ1  cos φ 2
=
⇒ VA =
I DSS
G
I DSS
1
G cos φ 2 − cos φ1
(3-97)
Finally, VC is also expressed as a function of φ1 and φ2 using (3-83), (3-97)
⇒ VC = V A cos φ 2 =
I DSS
cos φ 2
G cos φ 2 − cos φ1
Now, solving for I p1 in terms of φ1 and φ2 using (3-32), (3-96), (3-97) gives
(3-98)
325
I

I
cos φ1
1

I p1 = G (V A − VB ) = G  DSS
− DSS
G cos φ 2 − cos φ1 
 G cos φ 2 − cos φ1
1 − cos φ1
= I DSS
cos φ 2 − cos φ1
(3-99)
and I p 2 in terms of φ1 and φ2 using (3-38), (3-97) and (3-98) gives
I

I
cos φ 2
1

I p 2 = G (V A − VC ) = G DSS
− DSS
G cos φ 2 − cos φ1 
 G cos φ 2 − cos φ1
1 − cos φ 2
= I DSS
cos φ 2 − cos φ1
(3-100)
Using these relationships for I p1 and I p 2 in terms of φ1 and φ2 will give the same
Fourier coefficients as computed previously in (3-91), (3-92), (3-93).
In either case, both methods produce the Fourier coefficients for the double-sided
clipped waveform
I dsn
 I DSS sin φ1 − φ1 cos φ1 − sin φ2 + φ2 cos φ2

cos φ2 − cos φ1
 π
I
φ − cos φ1 sin φ1 − φ2 + cos φ2 sin φ2
=  DSS 1
cos φ2 − cos φ1
 π
 2 I DSS cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ2 sin nφ2 + n sin φ2 cos nφ2

n( n 2 − 1)(cos φ2 − cos φ1 )
 π
n=0
n = 1 (3-101)
n≥2
These Fourier coefficients are implemented in Matlab to investigate the harmonic
magnitude of I dsn / I p over 2φ1 and 2φ 2 for sweep ranges 0 ≤ 2φ1 ≤ 2π
and
0 ≤ 2φ 2 ≤ 2φ1 . Since a double-sided clipped waveform requires that the output fills the
entire swing of the drain current, that is, I p = I DSS , there is no difference between the
I dsn / I p and I dsn / I DSS normalized plots. Therefore I dsn / I DSS plots are not shown.
The contour plots for I dsn / I p -vs-{ 2φ1 , 2φ 2 } are shown in Fig. 3-33 for four
harmonics.
Like the single-sided clipped conduction angle plots, this double-sided
326
clipped characteristic can be used as a tool to identify the drive angles that produce the
maximum amplitude for a specific harmonic. This figure is similar to the one in [139]
except that it is in a notation which is consistent with power amplifier conduction anglebased classification. The exact same characteristics are illustrated in 3-D in Fig. 3-34.
Note that the values of I dsn / I p -vs- 2φ1 along the 2φ 2 =0 axis are the same as the
I dsn / I p plots of the single-sided V p -clipped case (Fig. 3-24) and the values of
I dsn / I p -vs- 2φ 2 along the 2φ1 = 2π axis are the same as the I dsn / I p plots of the single-
sided V f -clipped case (Fig. 3-26).
The DC component of the double-sided clipped waveform, I ds 0 / I p -vs-{ 2φ1 , 2φ 2 }, is
provided in contour and 3D format in Fig. 3-35. Note that the values of I ds 0 / I p -vs- 2φ1
along the 2φ 2 =0 axis are the same as the I ds 0 / I DSS plot of the single-sided V p -clipped
case (Fig. 3-24) and the values of I ds 0 / I DSS -vs- 2φ 2 along the 2φ1 = 2π axis are the same
as the I ds 0 / I p plot of the single-sided V f -clipped case (Fig. 3-26).
327
Fig. 3-33
Contour plots of I dsn / I p -vs-{ 2φ1 , 2φ 2 } for n = 1,2,3,4 .
328
Fig. 3-34
Three-dimensional plots of I dsn / I p -vs-{ 2φ1 , 2φ 2 } for n = 1,2,3,4 .
Fig. 3-35
I ds 0 / I p -vs-{ 2φ1 , 2φ 2 } (a) contour plot and (b) 3D plot.
329
Vk / V p -clipped
The knee clipping mechanism gives rise to another double-sided clipped waveform
case, the Vk / V p -clipped waveform. Double-sided Vk / V p clipped waveform arises when
the bias, amplitude and load impedance cause the I ds waveform to be clipped by both the
knee and pinchoff mechanisms.
The generation of the Vk / V p -clipped waveform is
illustrated in Fig. 3-36.
I DSS = G (V f − V p )
Vg = VGG + V A cos ωt
I p1 = G (V A − VB )
φ1 = cos −1 (VB V A )
VB = V p − VGG
I p 2 ,eff = G (V A − VC ,eff )
φ2 ,eff = cos−1 (VC ,eff V A )
VC ,eff = V f ,eff − VGG
I p = I p1 − I p 2 ,eff
Fig. 3-36
Vk / V p -clipped waveform analysis.
This case resembles the V p / V f -clipped double-sided clipped waveform case.
Therefore, by making the appropriate definitions, (3-101) can be modified to solve for the
Vk / V p -clipped Fourier coefficients.
330
Using a similar method as in the Vk -clipped case, I DSS ,eff and V f ,eff are defined using
(3-62) and (3-63), respectively, which are identified in Fig. 3-36.
The conditions for the Vk / V p -clipped waveform are that V f ,eff ≤ (VGG + V A ) and
(VGG − V A ) ≤ V p and the waveform definitions of (3-32), (3-33), (3-34) and (3-64),
(3-65), (3-66), identified in Fig. 3-36, are used for this case.
By applying these
definitions to (3-101), it follows that the Fourier coefficients for the Vk / V p -clipped
waveform are
I dsn
 I DSS , eff sin φ1 − φ1 cos φ1 − sin φ2, eff + φ2, eff cos φ2, eff

cos φ2, eff − cos φ1
 π
 I DSS , eff φ1 − cos φ1 sin φ1 − φ2, eff + cos φ2,eff sin φ2, eff
=
cos φ2, eff − cos φ1
 π
 2 I DSS ,eff cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ2,eff sin nφ2, eff + n sin φ2,eff cos nφ2, eff

n(n 2 − 1)(cos φ2, eff − cos φ1 )
 π
n=0
n =1
(3-102)
n≥2
Using I p = I DSS ,eff and φ2,eff , the operating angle plots of Fig. 3-33, Fig. 3-34 and Fig.
3-35 can be applied for the Vk / V p -clipped case.
VBV / V f -clipped
The breakdown region also gives rise to another double-sided clipped waveform case,
the VBV / V f -clipped waveform.
This double-sided VBV / V f -clipped waveform is
generated when the bias, amplitude and load circumstances causes I ds to be clipped by
both breakdown and forward conduction mechanism. An illustration of VBV / V f -clipped
waveform generation is shown in Fig. 3-37.
331
(VGG - VA) ≤ Vp,eff
Ids
Vf ≤ (VGG + VA)
VC
0 ≤ 2φ1,eff ≤ 2π
0 ≤ 2φ2 ≤ 2φ1,eff
Ids
2φ2
2φ1,eff
Ids
I p2
IDSS
VB,eff
IDSS
Ip1,eff
slope=-1/ZL
Ip
I0
Vp
Vp,eff
VGG
Vf
Vg -π
0
π
2π
ωt
Vk
VBV
VDD Vds
I DSS = G (V f − V p )
Vg = VGG + VA cos ωt
Vg
VA
I p1,eff = G (VA − VB ,eff )
Vds
φ1,eff = cos −1 (VB,eff V A )
VB ,eff = V p ,eff − VGG
I p 2 = G (VA − VC )
φ2 = cos −1 (VC VA )
VC = V f − VGG
I p = I p1,eff − I p 2
ωt
Fig. 3-37
I 0 = (VDD − VBV ) Z L
ωt
VBV / V f -clipped waveform analysis.
It is important to recognize that this case resembles the doubled-sided V p / V f -clipped
waveform case with the addition of the DC term I 0 and a peak-to-peak current of
I p = I DSS − I 0 .
Therefore, (3-101) can be applied by making the appropriate
modifications. Similar to the VBV case, a minimum current boundary I 0 and respective
V p ,eff are defined by (3-70) and (3-71), respectively.
In reference to
V p ,eff , the conditions for the
VBV / V f -clipped case are
(VGG − V A ) ≤ V p, eff and V f ≤ (VGG + V A ) . Using the definitions (3-72), (3-73), (3-74) and
(3-38), (3-36), (3-37) identified in Fig. 3-37, the Fourier coefficients for the VBV / V f clipped waveform can be written by modifying (3-101) with I 0 and I p = I DSS − I 0 to
produce
332
I dsn

I DSS − I 0 sin φ1,eff − φ1,eff cos φ1,eff − sin φ2 + φ2 cos φ 2
I 0 +
cos φ2 − cos φ1,eff
π

 I DSS − I 0 φ1,eff − cos φ1,eff sin φ1,eff − φ 2 + cos φ 2 sin φ 2
=
cos φ 2 − cos φ1,eff
 π
 2( I DSS − I 0) cos φ1,eff sin nφ1,eff − n sin φ1,eff cos nφ1,eff − cos φ 2 sin nφ 2 + n sin φ 2 cos nφ 2

n(n 2 − 1)(cos φ 2 − cos φ1,eff )
π

n=0
n =1
(3-103)
n≥2
Using I p = I DSS − I 0 and φ1,eff , the operating angle plots of Fig. 3-33, Fig. 3-34 and Fig.
3-35 can be applied.
Vk / VBV clipped
The final double-sided clipped combination is Vk / VBV -clipped case in which the bias,
amplitude and load impedance has placed the device in a mode where both the knee and
breakdown mechanisms have caused I ds waveform to clip on top and bottom. An
illustration of the double-sided Vk / VBV -clipped waveform case is shown in Fig. 3-38.
333
I DSS ,eff = VDD Z L
Vg = VGG + VA cos ωt
I p1,eff = G (VA − VB ,eff )
φ1,eff = cos −1 (VB,eff V A )
VB ,eff = V p ,eff − VGG
I p 2,eff = G (VA − VC ,eff )
φ2,eff = cos−1 (VC ,eff VA )
VC ,eff = V f ,eff − VGG
I p = I p1,eff − I p 2,eff
I 0 = (VDD − VBV ) Z L
Fig. 3-38
Vk / VBV -clipped waveform analysis.
Analysis of this case proceeds by recognizing that it resembles a double-sided
V p / V f -clipped waveform with hard limits defined by the upper and lower current limits,
I DSS ,eff and I 0 , respectively. As a result, the double-sided Fourier coefficients can be
formed from (3-101) by using I p = I DSS ,eff − I 0 and shifting by I 0 . The modified hard
limits of (3-62), (3-63) and (3-70), (3-71) imposed under the Vk -clipped and VBV -clipped
cases, respectively, are used in this case.
Thus, Vk / VBV -clipped case will occur under the condition that that V f ,eff ≤ (VGG + V A )
and (VGG − V A ) ≤ V p, eff . The definitions of (3-72), (3-73), (3-74) and (3-64), (3-65),
(3-66) identified for the V f / VBV -clipped waveform are shown in Fig. 3-38.
By applying these definitions, I p = I DSS ,eff − I 0 and the I 0 -shift to (3-101), the
double-sided Vk / VBV -clipped Fourier coefficients are
334
I dsn

I DSS ,eff − I 0 sin φ1,eff − φ1,eff cos φ1,eff − sin φ 2,eff + φ2 ,eff cos φ2 ,eff
I 0 +
cos φ 2,eff − cos φ1,eff
π

 I DSS ,eff − I 0 φ1,eff − cos φ1,eff sin φ1,eff − φ2 ,eff + cos φ2 ,eff sin φ 2 ,eff
=
cos φ 2,eff − cos φ1,eff
π

 2( I DSS ,eff − I 0 ) cos φ1,eff sin nφ1,eff − n sin φ1,eff cos nφ1,eff − cos φ 2,eff sin nφ 2,eff + n sin φ2 ,eff cos nφ2 ,eff

π
n(n 2 − 1)(cos φ 2,eff − cos φ1,eff )

n=0
(3-104)
n =1
n≥2
Using the reduced range of the peak-to-peak I p = I DSS − I 0 and φ1,eff , the operating angle
plots of Fig. 3-33, Fig. 3-34 and Fig. 3-35 can be applied to the Vk / VBV -clipped case.
3.2.4.3.
Unclipped
Linear
When the device operation resides entirely in its linear operating range, the output I ds
waveform is linear as shown in Fig. 3-39.
335
I DSS = G (V f − V p )
Vg = VGG + V A cos ωt
I p = 2GV A
VB = V p − VGG
VC = V f − VGG
Linear waveform analysis, general case.
Fig. 3-39
The
conditions
required
for
linear
operation
(VGG − V A ) ≤ V f , or simply V B ≤ −V A and V A ≤ VC .
are
V p ≤ (VGG − V A )
and
For an input excitation of
Vg = VGG + V A cos ωt the time-varying drain current for the linear waveform is
I ds (t )
= G (Vg − V p )
= G (VGG + VA cos ωt − V p )
= G (VGG − V p + VA cos ωt )
= G (−VB + VA cos ωt )
= −GVB + GVA cos ωt
where
(3-105)
336
(3-106)
VB = V p − VGG
By inspection, the linear waveform Fourier coefficients are
I dsn
− GVB

=  GVA
 0

n=0
(3-107)
n =1
n≥2
Under the specific case that V A = −VB , the conduction angle which is consistent with the
V p -clipped waveform formula (3-35) is 2φ1 = 2π as shown in Fig. 3-40.
I DSS = G (V f − V p )
Vg = VGG + VA cos ωt
I p1 = G (V A − VB )
φ1 = cos −1 (VB VA )
VB = V p − VGG
Fig. 3-40
Linear waveform analysis, specific case V A = −V B .
337
Similarly, the linear case where V A = −V B = VC is equivalent to the V f -clipped
analysis with 2φ 2 = 0 and the V p / V f -clipped analysis with 2φ1 = 2π and 2φ 2 = 0 .
Complete pinchoff
When the gate excitation, regardless of bias and amplitude, does not rise above V p
and therefore does not turn on the device, the output I ds is completely pinched off. The
waveforms for the complete pinchoff condition are shown in Fig. 3-41.
(VGG + VA) ≤ Vp
Ids
Ids
IDSS
slope G
VB
Ip=0
VGG
Vp
Vf
Vg
-π
0
π
2π
I DSS = G (V f − V p )
Vg
VA
Vg = VGG + V A cos ωt
VB = V p − VGG
Ip = 0
ωt
Fig. 3-41
Complete pinchoff waveform analysis, general case.
ωt
338
The complete pinchoff case occurs under the condition that (VGG + V A ) ≤ V p or
simply V A ≤ VB . Since the device does not turn on, the Fourier coefficients for the
complete pinchoff case are
I dsn = 0,
n≥0
(3-108)
Under the specific case that V A = VB , the conduction angle which is consistent with
single-sided V p -clipped waveform analysis is 2φ1 = 0 as shown in Fig. 3-42.
I DSS = G (V f − V p )
Vg = VGG + V A cos ωt
I p1 = G (V A − VB )
φ1 = cos −1 (VB V A )
VB = V p − VGG
Fig. 3-42
Complete pinchoff waveform analysis, specific case V A = VB .
339
Complete forward conduction
When the entire V g excitation resides above V f , the device is driven into forward
conduction over the entire waveform cycle and a complete forward conduction operation
mode is achieved. The complete forward conduction waveform is illustrated in Fig. 3-43.
I DSS = G(V f − V p )
V g = VGG + V A cos ωt
VC = V f − VGG
Ip =0
Fig. 3-43
Complete forward conduction waveform analysis, general case.
The condition for complete forward conduction is V p ≤ (VGG − V A ) or simply
VC ≤ −VA . By inspection, a complete forward conduction operation causes the output
340
current to saturate at the maximum value, I DSS . Therefore, the Fourier series coefficients
are
I
I dsn =  DSS
 0
n=0
n ≥1
(3-109)
Under the specific case that VC = −V A , the overdrive angle which is consistent with
single-sided V f -clipped waveform analysis is 2φ 2 = 2π . This case is shown in Fig.
3-44.
I DSS = G(V f − V p )
V g = VGG + V A cos ωt
I p 2 = G (VA − VC )
φ2 = cos −1 (VC V A )
VC = V f − VGS
Fig. 3-44
Complete forward conduction waveform analysis, specific case V A = −VC .
341
Complete knee and complete breakdown operation
By the definition of Model D, there are two additional cases: complete knee and
complete breakdown operation. However, a serious warning must be given regarding the
validity of these cases.
In the high ideal Model D, Vk 0 to simplify the analysis due to knee clipping.
However, Vk cannot actually be equal to zero or the complete knee case will not exist. If
Vk =0, by the definition of Model D, Vds =0 and I ds =0. It is only under the assumption
that Vk is small and nonzero that loadline analysis provides that I ds ≈ I DSSeff at the knee.
In the high ideal Model D, it is also assumed that VDSS VBV and by loadline analysis
at Vds = VBV , I ds will saturate at I 0 . However, it is uncertain what the device will actually
do when Vds > VDSS and deep into the breakdown operation. Operating the device for
prolonged periods in the breakdown region may be harmful and I ds is unlikely to remain
at I 0 . Operating completely in breakdown will make I ds potentially much higher than
I DSS and may damage the device in the process. In fact, prolonged operation in the
forward conduction or breakdown modes where this is large DC power dissipation may
damage a real device.
For completeness, the two analyses are correct in the strict sense of the model
definition but care must be taken as these operation modes may be highly unrealistic due
to the highly idealized assumptions
342
Complete knee
The knee nonlinearity gives rise to another condition in which a combination of the
bias, amplitude and load place the device under complete operation at the knee and Vds
does not rise about Vk at any time. The complete knee condition is shown in Fig. 3-45.
I DSS ,eff = VDD Z L
Vg = VGG + VA cos ωt
VC ,eff = V f ,eff − VGG
Ip = 0
Fig. 3-45
Complete knee waveform analysis, general case.
The complete knee case occurs under the condition that V f ,eff < (VGG − V A ) or simply
VC ,eff ≤ −V A , where V f , eff and VC , eff are defined by (3-63) and (3-66), respectively. The
device is on but the load impedance causes Vds to clip at Vk , forcing I ds to saturate at
I DSS ,eff defined by (3-62). The Fourier coefficients of the complete knee waveform are
I
I dsn =  DSS ,eff
 0
n=0
n ≥1
(3-110)
343
There is a connection with the Vk -clipped analysis formulas at the specific case
where VC ,eff = −V A and 2φ 2,eff = 2π . This case is shown in Fig. 3-46. Note that I p = 0 .
I DSS ,eff = VDD Z L
Vg = VGG + VA cos ωt
I p 2,eff = G (V A − VC ,eff )
φ 2 ,eff = π
VC ,eff = V f ,eff − VGG
Ip = 0
Fig. 3-46
Complete knee waveform analysis, specific case V A = −VC ,eff .
Complete breakdown
The complete breakdown operation occurs when the combination of bias, amplitude
and load places the device under complete operation at breakdown and no changes in the
sinusoidal input cause Vds to go below VBV . The complete breakdown condition is
illustrated in Fig. 3-47.
344
I DSS = G (V f − V p )
V g = VGG + V A cos ωt
Ip = 0
VB ,eff = V p ,eff − VGG
I 0 = (VDD − VBV ) Z L
Fig. 3-47
Complete breakdown waveform analysis, general case.
When referred to the gate voltage, the condition for the complete breakdown
operation is (VGG + V A ) ≤ V p,eff , or simply V A ≤ V B ,eff . This operation causes VDD to stay
at VBV with I 0 and V p,eff defined by (3-70) and (3-71), respectively.
The Fourier
coefficients are
I
I dsn =  0
0
n=0
n ≥1
(3-111)
The specific case of V A = V B ,eff creates continuity with the VBV -clipped analysis formulas
where 2φ1,eff = 0 . This case is shown in Fig. 3-48. Note that I p = 0 .
345
I DSS = G (V f − V p )
V g = VGG + V A cos ωt
I p1,eff = 0
φ1,eff = 0
VB ,eff = V p ,eff − VGG
I 0 = (VDD − VBV ) Z L
Fig. 3-48
Complete breakdown waveform analysis, specific case V A = VB .
3.2.5. Harmonic Progression Analysis
The four hard nonlinearities of Model D give rise to mechanisms which can lead to
waveform distortion, and therefore, harmonic generation.
The Fourier coefficient
formulas generated in the previous analysis can be applied for the investigation of
harmonic generation as the function of an excitation or circuit parameter. The ensuing
evolution of a harmonic output can be described as a “harmonic progression” which
establishes a continuity between several conduction modes.
It is important to track the nonlinear behavior of the circuit as it traverses across
operating regimes. The basic parameters which will cause these transitions between
conduction modes are the applied bias ( VGG or VDD ), amplitude VA and Z L .
In most cases, VGG , VDD and Z L do not vary during real-time operation of the device.
Circuit design usually begins with the fixed selection of an operating point. Therefore,
346
the sweeping of VGG or VDD may be performed as a design step by not necessarily while
deployed under operation. Similarly, a real-valued, linear, frequency independent load
impedance Z L can be selected during the design process but will not change under RF
drive. However, there are circumstances in which neither of these assumptions are true.
Investigating the harmonic components of I ds as a function of the input amplitude VA
is synonymous with the circuit receiving different levels or modulated power at the input.
This can be useful for studying the gain characteristic of a particular harmonic of interest
over the available input power range.
The harmonic progression with respect to amplitude VA tracks growth, saturation or
decay of the harmonic output as the circuit transitions from small-signal to increasingly
large-signal operation. Consider the harmonic progression waveform generation shown
in Fig. 3-49.
347
2φ1'
2φ1''
2φ2'''
Vp < VGG < (Vp-Vf)/2
Ids
2φ1'''
Ids
Ip2'''
VC
Ip1'''
IDSS
Ip1''
VB
Ip1'
Vf
Vg -π
Vg
0
π
VA''
VA'''
ωt
Vp/Vf-clipped
Vp-clipped
VA'
2π
VA increasing
Vp VGG
Linear
ωt
Fig. 3-49
Harmonic progression analysis example.
The example shown in Fig. 3-49 has a gate bias of V p < VGG < (V p − V f ) / 2 . As the
amplitude is increased from V A ' to V A ' ' to V A ' ' ' , the operation mode transitions from
linear to V p -clipped to V p / V f -clipped with the decrease of 2φ1 and the emergence of
2φ 2 . Once the operating modes are identified, explicit formulas can be written for each
harmonic. In this case,
348
I ds 0

− GVB

 I sin φ1 − φ1 cos φ1
=  p1
1 − cos φ1
π
 I DSS sin φ1 − φ1 cos φ1 − sin φ2 + φ2 cos φ2
 π
cos φ2 − cos φ1


GVA

 I φ − cos φ1 sin φ1
I ds1 =  p1 1
1 − cos φ1
π
 I DSS φ1 − cos φ1 sin φ1 − φ2 + cos φ2 sin φ2
 π
cos φ2 − cos φ1

I dsn
Linear
(3-112)
V p clipped
V p / V f clipped
Linear
(3-113)
V p clipped
V p / V f clipped

0

 2I p1 cos φ1 sin( nφ1 ) − n sin φ1 cos( nφ1 )
=
n( n 2 − 1)(1 − cos φ1 )
 π
 2I DSS cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ 2 sin nφ2 + n sin φ2 cos nφ 2
 π
n( n 2 − 1)(cos φ 2 − cos φ1 )

Linear
V p clipped
(3-114)
V p / V f clipped
This formulation allows a harmonic of interest to be investigated directly as a
function of V A (or versus 2φ1 or 2φ 2 in other sweep cases) while simultaneously
observing the passage of the other harmonics.
This allows the explicit analytical
investigation of effects such as input linearity, output power saturation, gain, and
efficiency.
However, there are many operating possibilities and investigation requires the
exploration over all possible quiescent operating modes with the goal of selecting the
harmonic progression which best embellishes each performance criteria over the entire
power range. This analysis may also be useful in characterizing the harmonic sensitivity
to bias level when the exact value is not achieved in practice.
349
Under a large enough excitation, all transistor operation (except for when Vds ≤ 0 )
eventually results in double-sided clipped waveforms by two nonlinear mechanisms
regardless of operating point. Therefore cases of this harmonic progression can be
classified based on double-sided clipping mechanism pairs of Fig. 3-22.
possible double-sided clipped waveform pairs which are:
Vk / V p ,
The four
V f / VBV , V f / V p ,
Vk / VBV . Because of the nature of the real loads, transistor operation in which more than
two clipping mechanisms are activated cannot be realized. For this same reason, Vk / V f
and V p / VBV are not considered double-sided clipping mechanism pairs in this analysis.
Identification of these pairs allows the mapping of all harmonic progression cases for
swept V A . Mapping of the harmonic progression cases can be performed for any other
swept parameter including VGG or VDD or Z L . As stated previously, the unrealistic
complete knee and complete breakdown cases, are identified but not included in this
analysis.
The flow map of all harmonic progression cases is shown in Fig. 3-50 for the four
double-sided clipping mechanism pairs. The chart allows the formulation of the Fourier
expression specific to each harmonic for all cases. Other possibilities exist as subsets of
the cases shown here. For example, for the Vk / V p clipped pair in Fig. 3-50b, the device
can be biased to begin under the V p -clipped case, essentially bypassing the need for
complete pinchoff or linear case.
350
Fig. 3-50
Flow map of harmonic progression for amplitude.
The following pages are illustrations of each progression case. The Fourier formulas
can be put together to form explicit expressions for a particular harmonic of interest but
are not shown in the ensuing section.
351
(a) V p / V f -clipped
Fig. 3-51
Case (a.1) Complete pinchoff V p -clipped V p / V f -clipped.
352
Ids
Ids
Ids
VC
VB
Vp VGG
Vf
Vg -π
0
π
2π
ωt
Vk
Vg
VBV
Vds
Vds
VA
ωt
ωt
(a.2) Vp/Vf clipped
Complete
pinchoff
Vp clipped
Vp/Vf
clipped
Linear
Vf clipped
Complete
fwd cond.
VA
Fig. 3-52
VDD
Case (a.2) Linear V p -clipped V p / V f -clipped.
353
Fig. 3-53
Case (a.3) Linear V p / V f -clipped.
354
Fig. 3-54
Case (a.4) Linear V f -clipped V p / V f -clipped.
355
VB
Vp
Ids
VC
Vf VGG
Ids
Vg
-π
Ids
0
π
2π
ωt
Vk
VDD
Vg
Vds
VA
ωt
ωt
(a.5) Vp/Vf clipped
Complete
pinchoff
Vp clipped
Vp/Vf
clipped
Linear
Vf clipped
Complete
fwd cond.
VA
Fig. 3-55
VBV Vds
Case (a.5) Complete fwd. cond. V f -clipped V p / V f -clipped.
356
(b) Vk / V p -clipped
Ids
Ids
Ids
VC
VB
Vf,eff
VGG Vp
Vf
Vg -π
0
π
2π
ωt
Vk
VDD
Vg
Vds
Vds
VA
ωt
ωt
(b.1) Vk/Vp clipped
Complete
pinchoff
Vp clipped
Vk/Vp
clipped
Linear
Vk clipped
Complete
knee
VA
Fig. 3-56
VBV
Case (b.1) Complete pinchoff V p -clipped Vk / V p -clipped.
357
Fig. 3-57
Case (b.2) Linear V p -clipped Vk / V p -clipped.
358
Fig. 3-58
Case (b.3) Linear Vk / V p -clipped.
359
Ids
Ids
Ids
VC
VB
Vp
Vf,eff
Vf
Vg -π
0
π
2π
ωt
Vk
VDD
VBV
Vds
VGG
Vg
Vds
VA
ωt
ωt
(b.4) Vk/Vp clipped
Complete
pinchoff
Vp clipped
Vk/Vp
clipped
Linear
Vk clipped
Complete
knee
VA
Fig. 3-59
Case (b.4) Linear Vk -clipped Vk / V p -clipped.
360
(c) VBV / V f -clipped
Fig. 3-60
Case (c.1) Linear VBV -clipped VBV / V f -clipped.
361
Fig. 3-61
Case (c.2) Linear VBV / V f -clipped.
362
Ids
Ids
Ids
VC
VB
Vp
Vp,eff
VGG Vf
Vg -π
0
π
2π
ωt
Vk
Vg
VDDVds
Vds
VA
ωt
ωt
(c.3) VBV/Vf clipped
Complete
breakdown
VBV clipped
VBV/Vf
clipped
Linear
Vf clipped
Complete
fwd cond.
VA
Fig. 3-62
VBV
Case (c.3) Linear V f -clipped VBV / V f -clipped.
363
Ids
Ids
VC
Ids
VB
Vp
Vp,eff
Vf VGG
Vg -π
0
π
2π
ωt
Vk
VBV
Vg
Vds
VA
ωt
ωt
(c.4) VBV/Vf clipped
Complete
breakdown
VBV clipped
VBV/Vf
clipped
Linear
Vf clipped
Complete
fwd cond.
VA
Fig. 3-63
VDDVds
Case (c.4) Complete fwd. cond. V f -clipped VBV / V f -clipped.
364
(d) Vk / VBV -clipped
Fig. 3-64
Case (d.1) Linear Vk -clipped Vk / VBV -clipped.
365
Fig. 3-65
Case (d.2) Linear Vk / VBV -clipped.
366
Fig. 3-66
Case (d.1) Linear VBV -clipped Vk / VBV -clipped.
3.2.6. Generic Analytical Case-based Model
A generic, analytical case-based model can be formed from the derived Fourier
coefficient equations of (3-35), (3-60), (3-67), (3-75), (3-101), (3-102), (3-103), (3-104),
(3-107), (3-108), (3-109), (3-110) and (3-111). Generalized forms of the various possible
waveform cases are defined for the following operating modes: lower-clipped, upperclipped and double-sided clipped, linear, lower saturated, upper saturated.
367
Linear
The linear case and its Fourier coefficients remain the same as (3-107).
Lower saturated
The general lower saturated case occurs for two cases:
complete pinchoff and
complete breakdown. The Fourier coefficients of a lower saturated I ds are
I
I dsn =  min
 0
n=0
n ≥1
(3-115)
where I min is the minimum current level. The parameters of the lower saturated cases are
shown in Table 3-1.
Table 3-1
I min
Lower saturated parameter assignments
Complete pinchoff
Complete breakdown
0
I0
Upper saturated
The general upper saturated case occurs for two cases: complete forward conduction
and complete knee. Therefore, the Fourier coefficients of an upper saturated I ds is
I
I dsn =  max
 0
n=0
n ≥1
where I max is the maximum saturated current level.
saturated cases are shown in Table 3-2.
(3-116)
The parameters of the upper
368
Table 3-2
I max
Upper saturated parameter assignments
Complete forward
Complete knee
I DSS
I DSS ,eff
Lower clipped
The general lower clipped case occurs for two cases: V p -clipped and VBV -clipped.
The Fourier coefficients of the lower clipped I ds is
I dsn
I p1 ' sin φ1 '−φ1 ' cos φ1 '

 I min + π
1 − cos φ1 '

 I ' φ '− cos φ1 ' sin φ1 '
=  p1 1
1 − cos φ1 '
π
 2 I p1 ' cos φ1 ' sin( nφ1 ' ) − n sin φ1 ' cos(nφ1 ' )
 π
n(n 2 − 1)(1 − cos φ1 ' )

n=0
n =1
(3-117)
n≥2
where I min is the minimum current level, φ1 ' is the conduction angle referenced to the
Fourier tips above I min and I p1 ' is the peak-to-peak current of the Fourier tips. The
parameter assignments for the lower-clipped cases are provided in Table 3-3.
Table 3-3
Lower clipped parameter assignments
V p -clipped
VBV -clipped
I min
0
I0
φ1 '
φ1
φ1,eff
I p1 '
I p1
I p1,eff
Upper clipped
The general upper clipped case occurs for two cases: V f -clipped and Vk -clipped.
The Fourier coefficients of the upper clipped I ds is
369
I dsn

I p 2 '  sin φ2 '−(φ2 '−π ) cos φ2 ' 


 I max −
π 
1 − cos φ2 '


 I '
 p 2 (φ2 '−π ) − cos φ2 ' sin φ2 ' 


= −
1 − cos φ2 '

 π 
 2 I ' cos φ ' sin( nφ ' ) − n sin φ ' cos(nφ ' )
2
2
2
2
− p 2
2
π
(
1
)(
1
cos
φ
'
)
n
n
−
−

2
n=0
n =1
(3-118)
n≥2
where I max is the maximum current level, φ 2 ' is the overdrive angle in referenced to the
Fourier tips above I max and I p 2 ' is the peak-to-peak current of the Fourier tips. The
parameter assignments for the upper-clipped cases are provided in Table 3-4.
Table 3-4
Upper clipped saturated parameter assignments
V f -clipped
Vk -clipped
I max
I DSS
I DSS ,eff
φ2 '
φ2
φ 2,eff
I p2 '
I p2
I p 2,eff
Double-clipped
The general double-clipped case occurs for four cases: V p / V f -clipped and Vk / V p clipped, VBV / V f -clipped and Vk / VBV clipped. The Fourier coefficients of the doubleclipped I ds is
I dsn

I max − I min sin φ1 '−φ1 ' cos φ1 '− sin φ2 '+φ 2 ' cos φ2 '
n=0
 I min +
cos φ2 '− cos φ1 '
π

 I − I φ '− cos φ1 ' sin φ1 '−φ2 '+ cos φ2 ' sin φ2 '
=  max min 1
n =1
cos φ2 '− cos φ1 '
π

 2( I max − I min ) cos φ1 ' sin nφ1 '− n sin φ1 ' cos nφ1 '− cos φ2 ' sin nφ2 '+ n sin φ2 ' cos nφ2 '
n≥2

π
n(n 2 − 1)(cos φ2 '− cos φ1 ' )

(3-119)
370
where I max is the maximum current level, φ 2 ' is the overdrive angle in referenced to the
Fourier tips above I max , I min is the minimum current level and φ1 ' is the conduction
angle referenced to the Fourier tips above I min . The parameter assignments for the
double-clipped cases are provided in Table 3-5.
Table 3-5
Double-clipped parameter assignments
V p / V f -clipped
Vk / V p -clipped
VBV / V f -clipped
Vk / VBV -clipped
I max
I DSS
I DSS ,eff
I DSS
I DSS ,eff
φ2 '
φ2
φ 2,eff
φ2
φ 2,eff
I min
0
0
I0
I0
φ1 '
φ1
φ1
φ1,eff
φ1,eff
Program Flowchart
The program is composed of two stages: (1) the determination of the upper and lower
I ds limits and (2) determination of the operating mode and Fourier coefficients. The
upper and lower I ds limits are found by checking which IV nonlinearities the loadline,
set by Z L and VDD , intersect. This can be done by computing I DSSeff and I 0 from (3-62)
and (3-70), respectively, and checking for premature clipping levels. If the computed
I DSSeff < I DSS , the loadline crosses the knee boundary and I max = I DSSeff . Otherwise, the
loadline crosses the forward conduction boundary and I max = I DSS . If the computed
I 0 > 0 , the loadline crosses the breakdown boundary and I min = I 0 . Otherwise, the
loadline crosses the pinchoff boundary and I min = 0 . The flow diagram for assigning the
upper and lower I ds parameters is shown in Fig. 3-67. In order to apply the general
371
Fourier formulas, the parameters I p 2 ' , φ 2 ' , VC ' , I p1 ' , φ1 ' and VB ' need to be defined for
the appropriate operating case.
I0 > 0
I DSSeff < I DSS
I max = I DSS ,eff
I max = I DSS
I min = I 0
I min = 0
I p 2 '= I p 2,eff
I p2 ' = I p2
I p1 '= I p1,eff
I p1 ' = I p1
φ2 ' = φ2,eff
φ 2 ' = φ2
φ1 ' = φ1,eff
φ1 ' = φ1
VC '= VC ,eff
VC ' = VC
VB '= VB ,eff
VB ' = VB
Fig. 3-67
Flow chart for setting of the upper and lower I ds parameters.
Once the appropriate generic-model parameter assignments are made in accordance
with I max and I min , the operating mode is determined using the flow chart of Fig. 3-68.
This allows the selection and computation using the relevant Fourier coefficient formulas.
372
VA ≤ VB '
VC ' ≤ −VA
VA ≤ VC '
VB ' ≤ −VA
VB ' ≤ −VA
Fig. 3-68
Flow chart determining the generic operating mode.
3.2.7. Effect of Dispersive Phenomena on Model D
The two main dispersive phenomena found in SiC and GaN devices are self-heating
and charge-trapping, both of which can be incorporated into the Fourier analysis by
appropriately modifying the ideal model.
Although self-heating and charge-trapping can be modeled using the techniques
described in Chapter 2.2.3.6 and Chapter 2.2.3.7, due to the simplicity of the ideal models
which lack intricate soft nonlinearities, both effects can be modeled in the form of an
I DSS reduction. Reducing I DSS according to the level of quiescent dispersion will scale
the maximum current and transconductance; an effect synonymous with the compression
of the IV characteristics due to charge-trapping and self-heating. The modified I DSS
parameters can be tabulated according to the quiescent bias and applied during Fourier
analysis.
373
Assuming that the ideal model is based on dispersion-free PIV characteristics (Fig.
3-69a), examples of surface-trapping, substrate-trapping and self-heating on Model D are
shown in Fig. 3-69b, Fig. 3-69c and Fig. 3-69d, respectively.
Fig. 3-69
Application of self-heating and charge-trapping on Model D by modifying
I DSS .
For an ideal model based on PGIV measurements like those developed Chapter 2,
self-heating can be implemented as a function of I DSS as described above. However,
374
charge-trapping, particularly, substrate-trapping needs to be deembedded using a
modified I DSS as a function of pulsed bias.
3.2.8. Harmonic Termination Analysis Using Ideal Frequency Multiplexers
Ideal multiplexers can be used to investigate how transmission and reflection between
the device and termination can aid or detract from the generation of a desired harmonic.
They also allow the application of independent allocation of isolated harmonic
impedances.
to ZL1
1fo
2fo
to ZL2
3fo
to ZL3
1fo, 2fo, 3fo, 4fo
4fo
to ZL4
To Nonlinear
Device
Fig. 3-70
Conceptual operation of an ideal multiplexer with N=4.
The concept of a triplexer can be analogized to some extent by a river that is divided
in several streams as shown in the multiplexer with N=4 of Fig. 3-70. At the input port,
all frequencies can pass through back and forth from the nonlinear device drain, for
example.
Importantly, a harmonic signal only flows in and out of the stream designated to
operate at that particular frequency. There is no cross coupling between the flow of one
stream to that of another. Therefore, both output and reflected waves of a particular
375
harmonic are isolated between the device and the corresponding termination.
This
concept allows a designer to see study how one harmonic may be converted into others
through harmonic reflection and re-mixing at the drain.
Bias T
It is a common technique in RF and microwave active circuits to implement the DC
biasing using a bias T component, especially for diagnostic and characterization
purposes. The bias T is essentially a frequency diplexer which separates the signals at the
active device terminal into separate DC and RF paths. This allows for the independent
allocation of the DC terminations, RGG and RDD , from the RF terminations, Z S and Z L .
Although the bias T is typically represented as an inductor and a capacitor as shown
in Fig. 3-71, in its ideal operation, it should not produce a phase offset in either path (a
phase offset in the DC path does not affect the DC signal as there is no transmission line
effect).
VGG
VDD
RGG
ZS
vS
Fig. 3-71
RDD
Igs
Ids
+
+
Vgs
Vds
-
-
Transistor operation with bias T.
ZL
376
Therefore, the ideal bias T can be more appropriately modeled as a user-defined
component with S-matrices defined at f=0GHz (DC) and f>0GHz (>DC) shown in Fig.
3-72.
Fig. 3-72
S-matrix of an ideal bias T.
In the S-matrix at DC, the sub-matrix formed by the circle-highlighted values
represents the relationship defined between port 1 (DC+RF) and port 2 (DC). The submatrix shows S11 = S 22 =0 and S12 = S 21 =1, representing perfect match and lossless
transmission between port 1 and port 2 at DC. The hexagon highlighted value, S 33 =1,
signifies that DC values applied to port 3 (RF) are rejected by the bias T. Values that are
not encircled in any way represent the zero transfer of power between port 3 and port
1/port 2 at DC.
In the S-matrix for frequencies >DC or RF, the circle-highlighted values represent the
well-defined relationship between the port 1 and port 3. The sub-matrix shows that
S11 = S 33 =0 and S13 = S 31 =1, representing the perfect match and lossless transmission
between port 1 and port 3 at RF. The hexagon-highlighted value, S 22 =1, defines the
complete rejection of RF at the DC feed of port 2. The non-highlighted values define the
zero-transmission characteristics between port 2 and port 1/port 3 at RF.
377
Triplexer with DC and high order harmonic discharge
The concept of frequency separation can be extended to explore the effect of
terminations at DC and individual harmonic frequencies.
If a multiplexer is implemented at the gate and drain terminals of the device, a
different impedance value can be designated at each harmonic frequency as shown in Fig.
3-73. The figure shows each branch of the multiplier implemented using a tuned circuit
at the frequency of interest. However, like the bias T, the ideal multiplexer should not
have any phase offset for any given path.
VGG
VDD
ZS0=RGG
ZS1
fo
vS
ZS2
2fo
ZL0=RDD
Igs
Ids
+
+
Vgs
Vds
-
-
ZL1
2fo
ZL2
ZS3
3fo
3fo
ZL3
ZSN
Nfo
Nfo
ZLN
Source
Multiplexer
Fig. 3-73
fo
Load
Multiplexer
Transistor operation with multiplexer.
The multiplexer can be tailored to navigate any maximum number of harmonics of
interest. In the example shown here, a harmonic multiplexer of N=3, or triplexer which
implements DC and three individual harmonics is implemented. Furthermore, since
378
higher order harmonics require a proper termination, the triplexer is designed to
collectively feed those higher order harmonics into a unified port.
The resulting triplexer with DC and high order harmonic discharge can be defined
using a discrete set of S-matrices since the harmonic frequencies of interest are known
and finite. The S-matrices and port designation are shown in Fig. 3-74. There are five Smatrices for describing the triplexer behavior at DC, f o , 2 f o , 3 f o and > 3 f o frequencies.
The S-parameter assignment closely follows the strategy previously described for the
bias T, except it has been extended to 6 ports. Port 1 is the port incident on the transistor
and accepts DC and all harmonic frequencies. Port 2 is the DC bias port. Ports 3, 4, 5
are the pathways for f o , 2 f o and 3 f o , respectively. All higher order harmonics are
collectively discharged into port 6 where it can be terminated by a 50 ohm load. A
similar encircling concept from the bias T definition is employed in this triplexer
component where circled values represent the lossless transmission between two ports,
hexagon-highlighted values represent the rejection of certain frequencies from those ports
and un-highlighted values represent the zero transmission between isolated ports.
Multiplexers of any order can follow this basic concept for describing the triplexer.
379
Fig. 3-74
3.3.
S-matrices of the triplexer with DC and high order harmonic discharge.
Frequency Multiplier Design Using High-Precision Nonlinear
Models
The active frequency multiplier design strategy is described next. A description of
the nonlinear model, topology, design issues and performance criteria are given, followed
by a general argument for the selection of biasing, determination of harmonic terminating
networks and synthesis.
3.3.1. Harmonically-Accurate Nonlinear Models
Substantial self-heating and charge-trapping effects are present in SiC MESFETs and
GaN HEMTs due to the high power density and relative immaturity of their respective
technologies. These dispersive effects on IV behavior can lead to poor predictions of
380
harmonic generation if not properly considered. Fortunately, a substantial effort has been
made to develop high-accuracy nonlinear models for both the SiC MESFET [72] and
GaN HEMT devices [74] allowing for close performance predictions by the use of
computerized design methods. The detailed development of these models are presented
in Chapter 2. The availability of nonlinear models for devices such as SiC MESFET and
GaN HEMTs is the central component to the successful doubler and tripler
demonstrations shown here.
Simulations closely matching the measured data will
illuminate the accuracy of these models in predicting harmonic behavior under tailored
biasing, harmonic terminating networks and varying drive levels. The generalized circuit
representation of the large-signal model for both devices is illustrated in Fig. 2-5.
The main nonlinear elements capable of contributing to the harmonic generation are
the drain-current source I ds , the gate-source diode Dgs , the gate-drain diode Dgd and the
bias-dependent capacitors C gs , C gd and C ds .
The IV characteristics will change
depending on the quiescent operating point in terms of the applied voltage, dissipated
power and subsequent temperature. The dynamic behavior of the IV characteristics
creates complex nonlinearities that can lead to inaccurate predictions of harmonics if not
properly accounted for in the modeling process.
3.3.2. Single-ended Frequency Multiplier Topology
Due to simplicity and cost, a single-ended, single-transistor topology is the most
practical and feasible for high-power active frequency multiplier realization [42]. A
canonic realization is shown in Fig. 3-75 consisting of a nonlinear transistor and passive
harmonic terminating networks, M g and M d , at the gate and drain, respectively. The
381
frequency dependent impedances looking out of the gate and drain and into these
networks are Z g and Z d , respectively. These gate and drain networks provide the DC
bias, enhance the desired k th -order output harmonic and reject the unwanted harmonics.
Fig. 3-75
Canonic realization of a single-ended active, k th -order frequency multiplier.
The primary design objectives are to maximize the following:
1. Power output at the desired k th harmonic, Poutk
2. Fundamental input-to- k th harmonic output conversion gain, CGk =
3. DC-to- k th -harmonic output drain efficiency, η k =
4. Power added efficiency, PAE k =
Poutk
Pavs
Poutk
PD 0
Poutk − Pavs
PD 0
5. Suppression of power at the unwanted harmonics, Poutn , where n ≠ k .
6. Fractional bandwidth, FBW
3.3.3. Design Procedure
The general design algorithm for the doubler and tripler designs presented here is
shown in Fig. 3-76. The algorithm is executed to maximize the performance criteria. In
382
the case of the frequency multipliers developed here, the primary objective is to
maximize Poutk , followed by the secondary performance goals listed above.
Fig. 3-76
3.3.3.1.
Generalized frequency multiplier design algorithm.
Device Biasing
First, the device bias is determined such that Poutk and CG k are maximized. Since
both bias and drive level affect the conduction characteristics of the device, investigation
over an appropriate input power range is necessary. Strategies on how to determine the
best bias are dependent on the desired multiplication order and will be discussed on an
individual basis. In general conduction angle analysis will give some insight on a good
biasing point.
Proper biasing provides performance advantages but will not result in maximum Poutk
and CG k in a practical frequency multipliers. Once frequency-dependent parasitics,
383
nonlinear junction capacitances and a realistic drain-current model are considered,
harmonic predictions become too complex for conduction angle analysis. Therefore,
computerized simulations using harmonic balance and nonlinear microwave models are
necessary.
3.3.3.2.
Determination of Optimal Harmonic Terminations
Gate and drain terminating networks will be necessary to further exploit the
harmonic-generating capabilities of the high-power device. After selection of the DC
operating point, the next step is to determine optimal harmonic impedances for the
eventual realization of M g and M d .
Using the input power ranges and selected bias, the optimal harmonic impedances are
found by conducting extensive analysis of the nonlinear model through CAD-based
harmonic load-/source-pull simulations. Analyzing device performance in simulation is
significantly less expensive, simpler and faster than constructing and operating a
hardware-based impedance-pull system.
The conceptual setup for the harmonic impedance simulation is detailed in Fig. 3-77.
The configuration consists of a fundamental signal source, vs ( f o ) , followed by a network
consisting of an ideal multiplexer/harmonic tuner bank/ideal multiplexer combination.
This composite structure is connected to the gate of the nonlinear device model. The
multiplexers are employed to divide the gate-reflected waves according to frequency so
that fundamental and harmonic signals are constrained to pass through individual
branches. Each branch is equipped with a tuner, which permits the adjustment of the port
impedance seen by the device at the specific harmonic frequency of interest. In this way,
384
for the purposes of the analyses, the specific harmonic signal can be tuned without its
tuning network affecting other harmonics.
Fig. 3-77
Generalized harmonic load-/source-pull analysis simulation.
Employing this structure, each harmonic may be tuned independently to optimize an
overall metric (e.g. Poutk , CG k , etc). Subsequent to the completion of the tuning process,
an impedance function Z gn ' = Z g ' (nf o ) that optimizes the desired multiplier metric is
obtained, where n = 1K N and N is the maximum number of harmonics explicitly
considered. A similar embodiment at the drain provides the impedance function Z dn ' .
As this method completely separates synthesis from analysis, the designer can perform
the analysis without being constrained by network topology and can later select the
desired technique for procuring a realizable circuit from these impedance values.
385
The ideal multiplexer is lossless and contributes no phase offset. Therefore, it does
not obstruct the large-signal RF analysis of the device and additionally, provides a DC
path for biasing the device. The simulation using the ideal multiplexer is superior to the
hardware-based analogy from which it originates, in that it does not require a time-
consuming routine for calibration and de-embedding at each harmonic frequency. The
setup permits the tuning of each harmonic path to any impedance, thus providing
maximum generality in the analysis. The one essential requirement for success of this
approach is that an accurate, large-signal transistor model is available to provide
meaningful results.
Theoretically, progressively improving frequency doubler performance can be
attained as the number of optimally-terminated harmonic paths increases. However,
practically, no more than three harmonics will be manipulated since the drawbacks of an
increasingly complex circuit outweigh the incremental benefits of higher-order harmonic
control.
3.3.3.3.
Network Synthesis
The networks are synthesized into microstrip implementation and fabricated using
Rogers RT/duroid 5880 microwave laminate.
The synthesis and structure of the
microstrip networks highly depends on whether the circuit of interest is a doubler or
tripler. Therefore, the networks will be discussed in the corresponding sections.
386
3.4.
High Power C-Band Frequency Doublers Using SiC and GaN
FETs
The design and implementation of the frequency doublers is described in this section
[75]. Under the consideration of one or more performance objectives, this design process
consists of selecting the DC bias of the device, determining the harmonic load and source
impedances which provide optimal performance, and synthesizing those impedances into
realizable networks.
Fundamental frequencies of f o =2.00GHz and 3.33GHz are
employed for the SiC MESFET and GaN HEMT, respectively.
3.4.1. Device Biasing
Fourier analysis reveals that the theoretically optimal conduction angle for an ideal
piecewise linear I ds model is 2φ =120 degrees. However, it is difficult to achieve this
exact conduction angle in practice. Furthermore, third-harmonic distortion is not zero at
2φ =120 degrees and will give rise to unwanted Pout 3 . As an alternative, pinchoff bias is
chosen as the operating point of both doubler designs presented here for its numerous
advantages.
achieved.
Since it is well-defined, the device pinchoff state can be confidently
The subsequent 180-degree conduction angle gives rise to a half-wave
rectified I ds response which is still rich in second but extremely low in third-harmonic
content. At this operating point, the transistor produces zero quiescent power dissipation
and low small-signal gain for improved stability; both of which are important for pulsed
or modulated operation. A bias of Vgsq =-11V, Vdsq =55V for the SiC MESFET and
Vgsq =-3.0V, Vdsq =28V for the GaN HEMT is selected.
387
Representative sets of simulated PIV characteristics of the SiC [72] and GaN [74]
models are shown in Fig. 3-78a and Fig. 3-78b, respectively, with each biased at
pinchoff.
2.5
Vgsq=-11.0V, Vdsq=55V
2.0
2.0
1.5
1.5
Ids (A)
Ids (A)
2.5
1.0
1.0
0.5
0.5
0.0
0.0
0
Fig. 3-78
Vgsq=-3.0V, Vdsq=28V
10
20
30
40
50 56
0
10
20
30
Vds (V)
Vds (V)
(a)
(b)
40
50 56
Simulated PIV characteristics of the (a) SiC MESFET model and (b) GaN
HEMT model.
(DISS_Tran_sic_IV_PIV.dds)
(DISS_Tran_gan_IV_PIV.dds)
3.4.2. Harmonic Terminations
In the doubler designs presented here, only the impedances Z g1 ' and Z g 2 ' seen at the
gate, and Z d 1 ' and Z d 2 ' seen at the drain are systematically swept about an a priori
optimum in order to obtain the optimum Pout 2 . The other harmonics are terminated in
50 Ω by default.
Although the harmonic load-/source-pull is a general method, knowledge of
multiplier design declares that an input impedance match at f o increases CG2 and η 2 , an
output impedance match at 2 f o improves Pout 2 , and harmonic shorts at both device ports
388
further increase performance through the constructive recycling of unwanted harmonics
[140][141].
At the output, an f o reflector at an optimal phase offset from the drain can heavily
suppress unwanted Pout1 and improve both Pout 2 and CG 2 through harmonic mixing via
the drain.
Likewise, high-order harmonic power generated at the gate by soft
nonlinearities such as C gs or by hard clipping due to the forward conduction of Dgs can
be utilized similarly. A 2 f o reflector placed at an optimal phase offset from the device
gate may improve CG 2 through linear 2 f o amplification, as well. Additionally, it is
found that the near-zero values of the DC supply impedances, RGG and RDD , produce
increased performance.
The optimal harmonic impedance values for the SiC MESFET and GaN HEMT
designs determined from the load-/source-pull simulations are shown in Fig. 3-79 for the
high power designs.
These values serve as the target impedances for the desired
networks, M g and M d (Fig. 3-75).
389
Zg1'
Zd1'
Zg1'
Zd2'
Zg2'
Zd1'
Zg2'
Fig. 3-79
Zd2'
Derived harmonic load and source impedances for the (a) SiC MESFET and
(b) GaN HEMT.
(DISS_S_sic_doubler_triplexerDCv2_Nov09_2Stability_sourcenetwork_MLIN.dds)
(DISS_S_gan_doubler_triplexerDCv2_Nov09_2Stability_sourcenetwork_MLIN.dds)
3.4.3. Synthesis of Harmonic Terminating Networks
For the doubler development presented here, external bias tees are used to feed the
DC bias to the device through the realized M g and M d networks (Fig. 3-75). Therefore,
for the synthesis of networks M g and M d , aside from providing a DC path, attention
will be largely focused on achieving the proper RF response of Z g ( f ) and Z d ( f ) ,
respectively.
The circuit topology is shown in Fig. 3-80 where the gate and drain
networks (as viewed from the active device ports) each consist of two cascaded stages: a
harmonic reflector network and a matching network.
This topology provides the
simplest, most effective means of realizing the desired impedances while minimizing loss
and reducing complexity. This is especially important in the case of Z d1 , in which a
complete power reflection of the fundamental back to the device’s drain terminal is
desired.
Fig. 3-80
θd4
50Ω
θd2=90o
50Ω
θg2=45o
50Ω
θg4
50Ω
390
Topology of the prototype SiC MESFET and GaN HEMT-based frequency
doublers.
In the case of the output network, M d , the first step is to realize the impedance
Z d1 = Z d 1 ' as viewed from the drain. This impedance is realized by the use of an f o
reflector network consisting of a λo 4 open stub separated from the drain by a series
transmission line with length θ d1 as shown in Fig. 3-80. The λo 4 stub will provide an
f o short circuit impedance with phase offset of 2θ d 1 . The second step is to perform
matching at 2 f o such that Z d 2 = Z d 2 ' . This can be achieved by applying a single-stub
matching network as shown in Fig. 3-80.
Synthesis of the input network, M g , is
performed in a similar manner, except that a λo 8 reflector for 2 f o is placed closest to
the gate to achieve Z g 2 = Z g 2 ' followed by a single-stub matching network to achieve
Z g1 = Z g1 ' .
The parameters of the input and output networks with respect to f o in degrees are
tabulated in Table 3-6 for both the SiC MESFET and GaN HEMT designs. The reflector
and matching network impedances are 50 Ω which allow for safe reflection of high power
391
levels. The generation of excessive heat due to reflecting high power f o signal back into
the drain of the device prevents the use of higher impedance lines of higher Q. Photos of
the prototype SiC MESFET- and GaN HEMT-based frequency doublers are shown in
Fig. 3-81a and Fig. 3-81b, respectively.
Fig. 3-81
Photo of high power frequency doublers based on the (a) SiC MESFET and
(b) GaN HEMT.
Table 3-6
SiC- and GaN-based doubler network electrical lengths
Device
SiC
GaN
θ g1
θg2
θg3
θg4
θ d1
θd 2
θd3
θd 4
80.00
56.16
45.00
45.00
73.47
50.21
83.60
109.74
175.00
179.33
90.00
90.00
15.25
7.45
37.50
24.03
3.4.4. Measurement and Performance
The performance of the SiC MESFET- and GaN HEMT-based doublers are measured
under a wide range of large-signal drive conditions and compared with simulated results.
Harmonic output power
The large-signal harmonic output power of the SiC MESFET and GaN HEMT-based
doublers are shown in Fig. 3-82a and Fig. 3-82b, respectively. Additionally, CG 2 , η 2
and PAE 2 are shown for both designs in Fig. 3-83a and Fig. 3-83b, respectively. A
392
perusal of these results reveals that a maximum Pout 2 =38.50dBm (7.08W) has been
achieved for the SiC MESFET doubler. Similarly, a maximum Pout 2 =37.17dBm (5.21W)
has been achieved for the GaN HEMT doubler. A positive outcome of the λo 4 reflector
at the output is that it also rejects 3 f o output harmonic due to the periodic response of the
structure. As a result, an examination of these curves determines that a good suppression
of Pout1 as well as Pout 3 is achieved. These measurements show good agreement with the
simulations.
Table 3-7 compares the doublers’ maximum performance with that of
recently published work.
45
40
45
40
30
20
20
Pout (dBm)
Pout (dBm)
2fo
30
10
0
fo
-10
10
fo
0
-10
-20
3fo
-20
3fo
-30
-30
15
Fig. 3-82
2fo
20
25
30
35
40
15
20
25
30
Pavs (dBm)
Pavs (dBm)
(a)
(b)
35
Harmonic Pout for the (a) SiC MESFET and (b) GaN HEMT doublers.
Measured (symbols), simulated (solid lines).
40
(DISS_HB_sic_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple.dds)
(DISS_HB_gan_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple.dds)
393
15
50
15
10
40
10
Eta
20
-5
-10
5
CG (dB)
CG (dB)
0
40
CG
30
0
Eta
20
-5
10
-10
0
-15
10
PAE
-15
15
Fig. 3-83
20
25
30
35
40
Eta(%), PAE (%)
30
Eta(%), PAE (%)
CG
5
50
PAE
10
20
30
Pavs (dBm)
Pavs (dBm)
(a)
(b)
0
40
CG 2 , η 2 and PAE 2 for the (a) SiC MESFET and (b) GaN HEMT doublers.
Measured (symbols), simulated (solid lines).
(DISS_HB_sic_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple.dds)
(DISS_HB_gan_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple.dds)
High power frequency doubler performance summary and comparison
Pout1 / Pout 3 at max
2 fo
Pout 2
CG 2
η2
PAE 2
Work
Pout 2 (-dBc)
(dB)
(%)
(%)
(GHz)
(dBm)
SiC*
4
11.56
38.50
19.96
13.45
-38.67/-54.83
GaN*
6.66
9.17
37.17
36.88
15.11
-34.84/-31.84
[70]
8
3.00
25.00
—
—
-11/-27
[120]
2.4
11.18
21.85
—
—
—/—
[123]
28-30
18.00
22.00
—
—
-50 to -70/-60
[124]
30
16.00
18.00
5.00
—
-23/—
[125]
10
11.67
10.34
—
—
-7/-23
*This work
Table 3-7
Output power bandwidth
Although bandwidth is not a design consideration, the output power characteristics of
the SiC MESFET and GaN HEMT doublers are assessed over a 5% FBW around f o
and provided in Fig. 3-84a and Fig. 3-84b, respectively. The SiC MESFET doubler is
evaluated at Pavs =36dBm while the GaN HEMT doubler is evaluated at Pavs =33dBm.
394
Simulations of the high-power doublers are extremely close for the first and second
harmonics. For the SiC MESFET doubler, the third harmonic falls over 50dB below the
second at the center frequency and consequently is more difficult to predict over a
frequency range of interest. The 3dB FBW of the SiC MESFET and GaN HEMT
doublers are 4.2% and 4.0%, respectively, due to the narrowband nature of the realized
networks.
45
40
2fo
30
30
20
20
10
Pout (dBm)
Pout (dBm)
45
40
fo
0
-10
-20
0
3fo
-20
-30
Fig. 3-84
fo
10
-10
3fo
2fo
-30
1.94 1.96 1.98 2.00 2.02 2.04 2.06
3.24 3.28 3.32 3.36 3.40 3.44
fo freq (GHz)
fo freq (GHz)
(a)
(b)
Harmonic Pout over a 5% FBW for the (a) SiC MESFET and (b) GaN
HEMT doublers. Measured (symbols), simulated (solid lines).
(DISS_HB_sic_doubler_triplexerDCv2_Nov09_2Stability_synthesized_broadband.dds)
(DISS_HB_gan_doubler_triplexerDCv2_Nov09_2Stability_synthesized_broadband.dds)
Variation of output power due to drain bias
In order to further improve the output performance of the frequency doublers, the
effect of VDD on the Pout 2 is investigated. The measured Pout 2 of both doublers versus
VDD for Pavs =[23,27,31,35]dBm is shown in Fig. 3-85. According to the plot, while the
trend seen in Pout 2 -vs- VDD for the SiC doubler is similar at different drive powers (Fig.
395
3-85a), that relationship in the case of the GaN doubler varies significantly with Pavs
(Fig. 3-85b). For the SiC doubler, Pout 2 (Fig. 3-85a) gradually increases as a function of
VDD , and then levels off at high VDD values starting at about VDD =50V. This trend can
be observed for the several input power levels shown. As a result, it can be concluded
that the VDD =55V selected for the design process provides near-optimal output power
performance. In the case of the GaN doubler (Fig. 3-85b), however, the optimal VDD for
maximum Pout 2 appears to increase with the incident RF power. For Pavs =23dBm and
Pavs =27dBm, the optimal VDD value is hardly noticeable for the range of VDD tested. At
Pavs =31dBm, the design bias of VDD =28V provides a near optimum output power.
However, at Pavs =35dBm, the drain bias displaying the maximum Pout 2 increases to
VDD =39V.
39
38
39
35dBm
35dBm
38
36
27dBm
34
32
23dBm
31dBm
36
27dBm
34
32
23dBm
30
30
20 25 30 35 40 45 50 55 60
Fig. 3-85
Pout2 (dBm)
Pout2 (dBm)
31dBm
20
25
30
35
Vdd (V)
Vdd (V)
(a)
(b)
40
45
Pout 2 -vs- VDD at Pavs =[23,27,31,36]dBm for the (a) SiC MESFET and (b)
GaN HEMT doublers. Measured (symbols).
(DISS_HB_sic_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple_vdssweep)
(DISS_HB_gan_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple_vdssweep)
396
A comparison of the measured GaN doubler data for VDD =28V and 39V showing
Pout 2 -vs- Pavs is shown in Fig. 3-86a.
The increase of the drain bias improves the
maximum Pout 2 from 37.17dBm (5.21W) to 38.33dBm (6.81W) corresponding to an
increase of 1.6W,. This is a significant increase if maximum power is the main objective.
However, this increase comes at the expense of some conversion gain at the lower power
range as shown in Fig. 3-86b.
40
10
9
Vdd=28V
8
7
35
Vdd=28V
30
CG (dB)
Pout2 (dBm)
Vdd=39V
6
5
4
Vdd=39V
3
2
1
0
25
15
Fig. 3-86
20
25
30
35
15
20
25
30
Pavs (dBm)
Pavs (dBm)
(a)
(b)
35
(a) Pout 2 -vs- Pavs and (b) CG2 -vs- Pavs comparing GaN doubler at VDD =28V
and VDD =39V. Measured (symbols).
(DISS_HB_gan_doubler_triplexerDCv2_Nov09_2Stability_synthesized_simple.dds)
3.5.
High Power X-band Frequency Tripler Using a GaN HEMT
An active microwave, X-band frequency tripler using the AlGaN/GaN HEMT device
is also developed and described in this section. This is the first reported frequency tripler
implemented in GaN technology. The design technique of Chapter 3.3.3 consisting of
device bias selection, optimal harmonic impedance selection and network synthesis is
397
performed.
The tripler converts f o =3.33GHz to 10GHz to achieve a maximum
Pout 3 =30.0dBm (1.0W). As such, it provides multiplied powers which are approximately
50 times greater than those previously reported [76].
3.5.1. Device Biasing
The fundamental concept of harmonic generation is to drive the device such that its
output drain current waveform becomes clipped due to the transition between operating
regimes. According to Fourier analysis, a symmetrically-clipped drain current waveform
is desirable in the case of a frequency tripler due to its rich odd harmonic content. The
two hard nonlinearities which create this clipping effect are delineated by the pinchoff
regime and the forward conduction of Dgs . The ease with which the waveform is clipped
and the amount of symmetry is determined primarily by the device bias, drive level and
terminating impedances at each harmonic.
Double-sided clipped waveform analysis has shown that the optimum bias condition
for third harmonic generation is midway between forward conduction and pinchoff [130].
Low power devices which do not suffer from significant self-heating can be conveniently
biased in this manner; however, in the case of the GaN HEMT device, the IV
characteristics change as a function of the dissipated power.
This varies with the
quiescent bias and dissipated power level as shown in the PIV characteristics of Fig.
3-87. Therefore, selection of the gate bias is not a trivial choice and should be chosen
utilizing extensive simulations of the output power level with respect to the gate-biasing.
The bias which provides the maximum 3 f o output power has been determined to be
Vgsq =-2.3V with a drain bias of Vdsq =28V.
398
GaN HEMT devices are particularly well suited for third harmonic generation at the
higher frequencies because they possess (1) a relatively high (less negative) pinchoff
voltage of around V p =-3.0V as compared with SiC MESFET devices and (2) a high f T
unity gain frequency. A high pinchoff voltage allows the drain current to clip with less
voltage swing at the gate. A high f T allows the 3 f o harmonic generated at the input to
2.2
2.0 Pdiss=0W
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10
20
Fig. 3-87
Ids (A)
Ids (A)
be delivered to the output.
30
40
50 56
2.2
2.0 Pdiss=2.632W
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
10 20
30
Vds (V)
Vds (V)
(a)
(b)
40
50 56
Simulated PIV characteristics of the GaN HEMT model at a bias of (a)
Vgsq =-3.0V, Vdsq =28V and (b) Vgsq =-2.3V, Vdsq =28V.
3.5.2. Harmonic Terminations
Once the application of the optimal bias level is established, proper load and source
impedances are applied to achieve increased gain and output power. Harmonic load and
source-pull simulations are performed on the nonlinear model to determine the optimal
impedances for maximum 3 f o generation. This is an extension of the concept employed
in [75] in that three harmonics are now considered instead of two.
399
This generalized method is advantageous in that the effect of each harmonic load can
be explored independently since the configuration assumes no particular topology. Once
the harmonic impedances are determined, the designer can choose one of many possible
realizations of the networks.
For the source network, an impedance match at f o and harmonic reflectors for 2 f o
and 3 f o are desirable for increasing CG3 and Pout 3 . Likewise, for the load network, an
output match at 3 f o provides increased Pout 3 while harmonic reflectors for f o and 2 f o
provide increased CG3 , Pout 3 and suppression of the undesirable harmonics.
The harmonic impedance values determined from this analysis that result in
producing the maximum 3 f o power are plotted in Fig. 3-88.
Zg3 '
Zd1 '
Zd2 '
Zg1'
Fig. 3-88
Zd3 '
Zg2 '
Harmonic load and source impedances from GaN tripler simulation.
(DISS_S_gan_tripler_triplexerDCv2_Jan10_loadnetwork_v2.dds)
400
3.5.3. Synthesis of Harmonic Terminating Networks
The frequency tripler design with synthesized networks is shown in Fig. 3-89. One
goal in the realization of the harmonic treatment networks is to minimize circuit and
substrate losses. Thus the resulting topology is kept as simple as possible.
The frequency tripler network M g can be synthesized directly from the determined
impedances in a similar manner as performed for the frequency doublers. Looking out of
the gate of the GaN HEMT, M g consists of one λo 12 open stub that reflects 3 f o , one
λo 8 open stub that reflects 2 f o , followed by an f o impedance matching stub. The
phase offsets of the harmonic reflectors, θ g1 and θ g 3 , are designed to achieve Z g 3 = Z g 3 '
and Z g 2 = Z g 2 ' , respectively. The f o stub network is designed such to achieve the
optimal impedance match of Z g1 = Z g1 ' . Since M g is continuous trace, an external bias T
(not shown in Fig. 3-89) is used to supply the DC gate voltage
The major challenge in building a frequency tripler is realizing an output network
such that a short circuited f o reflector does not inadvertently short circuit the desired
Pout 3 . Several authors have used combinations of transmission line (TL) and lumped
elements [118][133][134], filters [126], coupled lines [122] and novel composite righthand/left-hand TLs [128] to solve this problem. In this work, a coupled-line section
designed to pass 3 f o while adequately rejecting f o is used within M d to address this
problem. Looking out of the device drain, the complete M d network is designed using a
λo 8 stub that reflects 2 f o , followed by an f o -rejecting coupled line section and 3 f o
matching stub in an attempt to satisfy the Z dn = Z dn ' conditions. This structure works
401
reasonably well but makes the DC biasing at the drain more difficult since DC cannot
pass through the coupled section. To circumvent this limitation, a hand-wound RF choke
connected to M d at a strategic location along the TL length θ d 4 (not shown in Fig. 3-89)
is employed.
The location is selected to minimize the interaction with the RF
characteristics of M d . The other end of the RF choke is connected to an external bias T
through which VDD is supplied.
Zg(f)
θg5
50Ω
θg3
50Ω
θg1
50Ω
Zd(f)
θd4
θd1
50Ω
θd3
50Ω
θd5
50Ω
Zoe=78Ω
Zoo=48Ω
fo Matching
Fig. 3-89
2fo Reflector 3fo Reflector
2fo Reflector
fo Reflecting
Coupled Line
3fo Matching
Circuit topology of GaN frequency tripler prototype.
The electrical lengths of the TL elements used in M g and M d are provided in Table
3-8.
The use of 50 ohm lines for all the TL elements with the exception of the
f o -reflecting coupled line is dictated by the necessity to avoid excessive heating of the
microstrip traces resulting from high power reflection. A photograph of the GaN HEMTbased frequency tripler is shown in Fig. 3-90 and shows the fabricated networks with the
hand-wound RF choke.
402
Fig. 3-90
Photo of high power frequency GaN HEMT tripler.
Table 3-8
GaN-based tripler network electrical lengths
θ g1
θg2
θg3
θg4
θg5
θg6
24.43
30.00
11.67
45.00
85.59
62.91
θd1
θd 2
θd 3
θd 4
θd 5
θd 6
90.07
45.00
107.19
33.62
0.48
83.04
3.5.4. Measurement and Performance
The output power of the frequency tripler is measured in a large-signal test setup
capable of delivering up to Pavs =39dBm. The harmonic output power and conversion
gain of the GaN HEMT frequency tripler is shown in Fig. 3-91 and Fig. 3-92,
respectively. The measured output shows that the realized circuit is capable of producing
Pout 3 =30.0dBm (1.0W) output power and CG3 =-2.9dB (or 2.9 dB conversion loss). The
simulated output closely predicts the measured Pout 3 over a good range of available
powers (Fig. 3-91). The conversion gain (Fig. 3-92) is also estimated closely over a
useful range of available powers.
403
35
3fo
30
fo
Pout (dBm)
20
10
2fo
0
-10
20
25
30
35
40
Pavs (dBm)
Fig. 3-91
Harmonic Pout of the GaN tripler for three harmonics. Measured (symbols),
simulated (solid lines).
(HB_gan_tripler_triplexerDCv2_Jan10_synthesized.dds)
0
10
-5
CG (dB)
5
-10
Eta(%)
CG
Eta
0
-15
20
25
30
35
40
Pavs (dBm)
Fig. 3-92
CG3 and η3 of GaN tripler. Measured (symbols), simulated (solid lines).
(HB_gan_tripler_triplexerDCv2_Jan10_synthesized.dds)
A comparison table between this work and recently published frequency triplers is
shown in Table 3-9. The table summarizes the maximum performance reported in each
of the publications. According to the table, the frequency tripler design presented here
404
represents the highest output power, single-transistor tripler available to date producing
over 50 times more power than that of the next highest.
High power frequency tripler performance summary and comparison
Pout1 / Pout 2 at max
3 fo
CG3
Pout 3
η3
Work
Pout 3 (-dBc)
(GHz)
(dB)
(dBm)
(%)
GaN*
10
-2.9
30.0
3.14
-11.2/-21.8
[122]
7.5
-2.4
1.6
13
-33.6/-29.6
[116]
38.64
-2.7
4.7
11
-38/-23
[117]
140
-11
-1.5
—
—/—
[126]
34.5
-6.5
-6.5
—
—/—
[127]
3
5.5
6
57
<-25/<-25
[128]
3
-5.67
-5.67
—
-62.72/-53.6
[129]
9
2.9
12.9
7.5
-28/-28
[130]
42-51
—
12.5
—
-40/-20
[131]
6
0.5
6
—
-50/-19
[118]
2.475
9
12
22.5
—/—
[132]
30
-5
12
5
<-50/<-40
[133]
8.85
2.9
7.9
—
<-35/<-50
[134]
8.82
3.67
9.17
—
-28.67/-26.87
*This work
Table 3-9
405
CHAPTER 4. CONCLUSION
4.1.
Technology
Wide bandgap III-V SiC and GaN technology will become the standard for solidstate, microwave power devices over the next few years as they displace older, mature
technologies in hybrid circuit applications. The bandwidth, output power and efficiency
performance of these devices will continue to improve as the technology is adopted into
widespread commercial systems. Many of the techniques presented in this work are
applicable for all types devices in which self-heating and charge-trapping pose
performance limitations.
4.2.
Nonlinear Modeling
High accuracy, large-signal, multibias and multi-harmonic models for high power,
microwave SiC MESFET and GaN HEMT devices have been developed. A generalized
large-signal model topology has been modified with important improvements for
application to these high power devices.
Drain current models employing modifications to the Angelov model that cater
specifically to each FET have been developed for use over high drain source currents
beyond 2A and voltage ranges greater than 50V. A methodology of using pulsed IV
characterization been presented for modeling I ds and associated dispersive effects.
A multi-order self-heating thermal model that can track the device temperature under
a wide array of operating conditions has been developed. Thermal effects on I ds have
406
been carefully characterized such that the I ds predictions accurately reflect the selfheating generated within the device.
The model which relates self-heating on I ds
performance has been verified through the use of transient, long-duration PGIV
measurements for both devices.
Charge-trapping has been investigated using PIV measurements at various quiescent
points to quantify their influence across the IV plane. These static substrate and surface
trapping effects have been modeled in the form of back-gate and forward-gate voltage
modifications, respectively. The surface trapping of SiC MESFETs is minimal compared
to the substrate and thermal effects in the device. The GaN HEMT possesses both
substrate and surface charge-trapping in addition to self-heating.
The implemented drain-current model with dispersion demonstrates the ability to
accurately predict PGIV and PIV characteristics under various quiescent biases, as well
as static IV characteristics for both the SiC MESFET and GaN HEMT. This validates the
versatility, capability and applicability of the I ds model and structured extraction and
modeling methods.
The DC characterization and extraction procedures of the nonlinear junction diodes
have been thoroughly described. They serve as limiting factors in the devices electrical
characteristics and serve an important role in hard-limiting and harmonic generation at
high power levels.
Small-signal models and extraction procedures for extrinsic and intrinsic elements
have been described in detail.
Algorithms for parasitic extraction, integration and
verification have been developed for the multibias nonlinear capacitance models.
407
Under RF drive, the complete model has demonstrated the ability to accurately
predict the S-parameters over wide bandwidths up to 4.0 GHz for the SiC MESFET and
up to 10GHz for the GaN HEMT. The models can also accurately predict large-signal
single-tone output and input reflected harmonic power up to 39dBm incident power for
three harmonics and two-tone third-order intermodulation distortion products over
multiple biases and frequencies.
The combined effort in these models allow them to track the shifts in self-heating,
charge-trapping and self-biasing which occur under large-signal RF drive. Additionally,
the GaN HEMT model can accurately predict large-signal output of the device under load
conditions optimized for maximum fo output power.
4.3.
Active Frequency Multipliers
Harmonic generation in FETs has been investigated and expanded using Fourier
series analysis. New regions of operation have been explored using an ideal model
exhibiting four IV nonlinearities. A general analytical model has been developed to
provide insight into the harmonic generation over all regions of FET operation and under
any bias and drive level.
The concept of a “harmonic progression” or shift and
emergence of harmonics as a function of input amplitude has been investigated in an
effort to determine the optimal operating conditions for the application of interest. The
analysis can serve as a means to identify nonlinear mechanisms responsible for limiting
the output of the desired harmonic. Once identified, harmonic treatment circuits can be
designed to enhance the desired harmonic while suppressing unwanted harmonics.
408
However, active frequency multiplier design using idealized transistor models and
Fourier analysis is at most an approximate endeavor once parasitics, soft nonlinearities
and frequency-dependent terminations are considered.
The development of accurate, large-signal models allows the application of powerful
CAD programs for designing high power, high conversion gain frequency multipliers. A
design method of using software-based harmonic load- and source-pull simulations has
been described. The successful use of this design technique is made possible by the
development of wideband, multi-harmonic models for SiC MESFETs and GaN HEMTs.
Several frequency multipliers using SiC MESFET and GaN HEMT devices have
been designed through a combination of conduction-angle sensitive device biasing,
harmonic load- and source-pull simulation and straightforward low-loss network
synthesis techniques. Issues pertaining to the output network of a frequency tripler have
been addressed using a coupled structure and a hand-wound DC feed.
The design objective is to maximally exploit the output power capabilities of III-V
devices using reflection at unwanted harmonics and impedance matching at desired
harmonics. High power, high conversion gain SiC MESFET and GaN HEMT frequency
doublers producing >5W at C-band and a GaN HEMT frequency tripler producing ~1W
at X-band have been demonstrated. The measured harmonic output power performance
has been closely predicted by the large-signal models. The performance displayed in this
work appears to provide the highest output power for active microwave frequency
multipliers of the reported harmonic order.
409
APPENDIX A. MODELING
A.1. SiC MESFET Drain Current Parameters
Table A-1
Vgsq ⇒
Q40
SiC MESFET Ids parameters post optimization for all PGIV datasets
-12.0
-11.5
-11.0
-10.5
-10.0
-9.5
-9.0
α P4
-1.660E-04
9.454E-07
4.784E-02
-1.369E-04
8.451E-07
4.062E-02
-1.538E-04
8.032E-07
3.764E-02
-1.551E-04
8.384E-07
3.745E-02
-1.893E-04
1.320E-06
6.125E-02
-1.947E-04
1.300E-06
6.260E-02
-1.859E-04
1.304E-06
6.973E-02
Q41
P4 o
-1.710E-04
-1.298E-04
-1.614E-04
-1.557E-04
-1.483E-04
-1.492E-04
-1.478E-04
Q30
-4.851E-04
-2.316E-04
-4.698E-04
-4.842E-04
-7.420E-04
-8.158E-04
-7.429E-04
Q31
-7.262E-07
1.003E-01
-7.582E-07
8.982E-02
-6.020E-07
9.825E-02
-5.770E-07
9.337E-02
2.777E-06
9.073E-02
2.767E-06
8.949E-02
2.866E-06
9.259E-02
α
P3
P3 o
9.947E-04
1.241E-03
1.100E-03
1.008E-03
1.079E-03
1.121E-03
1.142E-03
Q10
1.462E-01
-2.404E-04
1.324E-01
1.435E-01
-2.685E-04
1.290E-01
1.483E-01
-2.788E-04
1.338E-01
1.476E-01
-2.568E-04
1.336E-01
1.515E-01
-3.091E-04
1.309E-01
1.533E-01
-3.267E-04
1.290E-01
1.524E-01
-3.291E-04
1.291E-01
1.993E-02
-8.5
2.412E-02
-8.0
1.981E-02
-7.5
2.446E-02
-7.0
2.356E-02
-6.5
2.113E-02
-6.0
2.132E-02
-5.5
α P4
-1.788E-04
1.381E-06
7.643E-02
-1.949E-04
1.390E-06
8.958E-02
-1.848E-04
1.423E-06
8.025E-02
-1.926E-04
1.351E-06
6.756E-02
-1.930E-04
1.540E-06
7.913E-02
-1.965E-04
1.488E-06
7.620E-02
-1.741E-04
1.486E-06
7.489E-02
Q11
α P1
P1o
Vgsq ⇒
Q40
Q41
P4 o
-1.313E-04
-1.428E-04
-1.367E-04
-1.287E-04
-1.052E-04
-1.094E-04
-1.094E-04
Q30
-6.743E-04
-8.374E-04
-7.436E-04
-8.646E-04
-8.729E-04
-9.404E-04
-7.320E-04
Q31
3.543E-06
9.248E-02
3.479E-06
9.321E-02
3.594E-06
8.598E-02
3.550E-06
8.276E-02
5.276E-06
8.323E-02
5.251E-06
8.266E-02
5.619E-06
8.117E-02
α
P3
P3 o
1.172E-03
1.055E-03
1.087E-03
1.125E-03
1.311E-03
1.272E-03
1.305E-03
Q10
1.509E-01
-3.271E-04
1.311E-01
1.525E-01
-3.192E-04
1.311E-01
1.473E-01
-2.333E-04
1.293E-01
1.501E-01
-2.520E-04
1.308E-01
1.486E-01
-2.418E-04
1.249E-01
1.498E-01
-2.408E-04
1.285E-01
1.458E-01
-2.262E-04
1.305E-01
2.390E-02
-5.0
2.743E-02
-4.5
2.613E-02
-4.0
2.615E-02
-3.5
2.974E-02
-3.0
2.736E-02
2.653E-02
α P4
-2.108E-04
1.543E-06
7.909E-02
-2.156E-04
1.661E-06
8.969E-02
-2.030E-04
1.616E-06
6.048E-02
-1.792E-04
8.604E-07
9.437E-02
-1.532E-04
7.958E-07
9.661E-02
Q11
α P1
P1o
Vgsq ⇒
Q40
Q41
P4 o
-1.122E-04
-1.561E-04
-1.371E-04
-1.317E-04
-1.269E-04
Q30
-1.048E-03
-1.123E-03
-1.019E-03
-7.645E-04
-5.205E-04
Q31
4.981E-06
8.521E-02
6.309E-06
8.932E-02
6.480E-06
8.092E-02
-1.667E-06
9.667E-02
-1.757E-06
9.731E-02
α
P3
P3 o
1.271E-03
7.163E-04
1.003E-03
1.139E-03
1.152E-03
Q10
Q11
1.495E-01
-1.885E-04
1.520E-01
-2.297E-04
1.496E-01
-2.177E-04
1.489E-01
-1.385E-04
1.460E-01
-1.627E-04
α P1
1.339E-01
1.429E-01
1.371E-01
1.445E-01
1.440E-01
P1o
2.842E-02
3.777E-02
3.011E-02
2.635E-02
2.818E-02
(IV_equation_xtr3633_IV_PGIV_vgsqALL_dec07_opt_P_parameters_table.xls)
(also see DISS_thermal_IV_relation_Pn.m)
410
A.2. Self-Heating Thermal Model Analysis
The thermal model consists of an analogous electrical circuit which exhibits the
charging and discharging thermal behavior of the device as a function of self heating
from dissipated power. Analysis of the first-order model (Fig. A-1) and K-order model
(Fig. A-2) are presented here.
First order thermal model
Fig. A-1
Electrical circuit analogue for first order thermal model.
First, electrical notation of voltages and currents are used for the analysis followed by
a substitution of the thermal model notation. First, we solve for the voltage v1 across a
single RC pair.
iC = C
∂v1
v
and iR = 1
∂t
R
i = iC + iR = C
∂v1 v1
+
∂t R
411
iR = RC
∂v1
+ v1
∂t
We let the solution for v1 be
v1 = Ae st + B
(A-1)
∂v1
= Ase st
∂t
(A-2)
Then substituting, we have
iR = RCAse st + Ae st + B
iR = Ae st (sRC + 1) + B
(A-3)
iR e − st = A( sRC + 1) + Be − st
(A-4)
At t → ∞ , (A-4) becomes
0 = A( sRC + 1)
sRC = −1
s=−
1
RC
(A-5)
Applying to (A-1) the initial conditions t = 0 , v1 = Vi , where Vi is the initial voltage.
Vi = Ae s 0 + B
Vi = A + B
B = Vi − A
Also at t = 0 , plugging (A-5) and (A-6) into (A-3)
iR = Ae s 0 (sRC + 1) + B
iR = A( sRC + 1) + B
iR = A( sRC + 1) + Vi − A
(A-6)
412
iR = AsRC + Vi
iR = − A + Vi
(A-7)
A = Vi − iR
B = iR
Therefore, the solution for v1 is
v1 = Ae st + B = (Vi − iR )e − t /( RC ) + iR
and the total voltage at the output of the model is
v = v0 + v1 = v0 + (Vi − iR )e −t /( RC ) + iR
During the charging cycle of the circuit, the initial voltage Vi = 0 and i is stepped
from 0 to I then v1 will be
v = v0 + (0 − IR)e −t /( RC ) + IR
(
v = v0 + IR 1 − e −t /( RC )
(
v = v0 + IR 1 − e −t / τ
)
(A-8)
)
τ = RC
After a long time, voltage across the RC circuit will be Vi = IR . During the discharge
cycle of the circuit, the current i is stepped down from I to 0 and we obtain
v = v0 + ( IR − 0)e − t /( RC ) + 0
v = v0 + IR e − t /( RC )
413
Converting these results to the thermal model notation is done by substituting the
representative temperature and dissipated power variables:
v = T , v0 = T0 , v1 = ∆T ' ,
I = PD , R = Rth and C = Cth .
Therefore, we obtain for the self-heating thermal charging of the device from room
temperature to a raised temperature we have
(
T = T0 + ∆T ' = T0 + PD Rth 1 − e − t /( Rth C th )
(
T = T0 + ∆T 1 − e −t / τ
)
)
(A-9)
where ∆T = PD Rth = ( I ds ⋅ Vds ) Rth and τ = RthCth .
For a discharging of the self-heating thermal state back from a raised temperature
back down to room temperature, we have
T = T0 + ∆Te − t / τ
(A-10)
K-order thermal model
More complex thermal charging and discharging behavior can be modeled using a
multi-order model. A K-order, multiple-time constant thermal model can be analyzed in
a similar fashion as the first order model. Consider the electrical circuit analogue of the
K-order model shown in Fig. A-2.
Again, the electrical notation of voltages and currents are used for the analysis
followed by a substitution with the thermal model notation.
414
Fig. A-2
Electrical circuit analogue for K-order thermal model.
Now, performing KVL on the Nth order thermal model and applying the solution of
the voltage across a single RC pair (A-8), we have
v = v0 + v1 + v2 + L + vK
(
) (
)
v = v0 + (Vi1 − iR1 )e − t /( R1C1 ) + iR1 + (Vi 2 − iR2 )e − t /( R2 C 2 ) + iR2 + L
(
+ iRK
)
v = v0 + ∑ (Vik − iRk )e − t /( Rk C k ) + iRk
]
+ (ViK − iRK )e
K
− t /( R K C K )
[
k =1
During the charging cycle in which Vik = 0 for k = 1,2,..., K and i = I we have
K
[
v = v0 + ∑ IRk − IRk e − t /( Rk C k )
k =1
]
415
K
K

v = v0 + I ∑ Rk − ∑ Rk e − t /( Rk Ck ) 
k =1
 k =1

K
Defining Req = ∑ Rk , this simplifies to
k =1
K


v = v0 + I  Req − ∑ Rk e − t /( Rk C k ) 
k =1


K


R
v = v0 + IReq 1 − ∑ k e − t /( Rk C k ) 
 k =1 Req

K


v = v0 + IReq 1 − ∑ Rˆ k e − t / τ k 
 k =1

(A-11)
R
where Rˆ k = k and τ k = Rk Ck .
Req
For the discharging cycle, in which Vik = IRk for k = 1,2,..., K and i = 0 we have
K
v = v0 + ∑ IRk e − t /( Rk C k )
k =1
K
v = v0 + IReq ∑ Rˆk e − t / τ k
(A-12)
k =1
Converting the voltages and currents into temperature and power notations ( v = T ,
v0 = T0 , i = PD , R = Rth and C = Cth ) to create the analogous circuit, we have for the
charging case
K


T = T0 + PD Rth, eq 1 − ∑ Rˆth , k e − t / τ k 
 k =1

K


T = T0 + ∆T 1 − ∑ Rˆth , k e − t / τ k 
 k =1

where ∆T = PD Rth , eq and τ k = Rth, k Cth, k .
416
For the discharging case
K
T = T0 + ∆T ∑ Rˆth , k e − t / τ k
k =1
In general, for a K-order model,
K


−t / τ k 
CHARGING
T0 + ∆T 1 − ∑ Rˆ th ,k e

k =1


T = T0 + ∆T ' = 
K
 T0 + ∆T ∑ Rˆ th, k e −t / τ k
DISCHARGING

k =1
(A-13)
∆T = PD Rth,eq = ( I ds ⋅ Vds ) Rth,eq
(A-14)
K
Rth,eq = ∑ Rth,k
(A-15)
k =i
R
Rˆth,k = th,k
Rth,eq
(A-16)
τ k = Rth , k Cth , k
(A-17)
Thermal resistance measurement technique explained
Fig. A-3
Internals of the DC model under DC power dissipation (a) applied terminal
excitation (b) schematic (c) ln( I gs ) -vs- V gs curve for extraction.
417
Under power drive, I ds is non zero and causes a voltage drop across Rs . This raises
the value of the applied gate voltage V gs necessary to turn on the gate-source diode. As a
result, the ln( I gs ) curve is shifted to the right for device states under which power is
dissipated ( I ds >0). However, the ability to extract the thermal voltage (nVT ) remains
unchanged.
The gate side of the DC FET model is shown in Fig. A-3b showing the gate diode and
parasitic gate and source resistances. Performing KVL, we have
Vgs = I gs Rg + V D + V Rs
where VRs = ( I gs + I ds ) Rs .
Under power-dissipative conditions in the watts, I ds >> I gs and ( I gs + I ds ) Rs >> I gs R g
which simplifies the expression
Vgs ≈ VD + I ds Rs
⇒ VD ≈ V gs − I ds Rs
In the case of our FET device, the diode current is the incoming gate current
I gs = I D . However, the voltage across the internal diode is smaller than the applied V gs
due to the parasitic voltage drop caused by I ds Rs . The diode current is therefore
I gs = I D ≈ I S e VD /( nVT )
ln( I gs ) ≈ ln( I S ) +
1
VD
nVT
ln( I gs ) ≈ ln( I S ) +
1
(V gs − I ds Rs )
nVT
(A-18)
(A-19)
418
∂ ln( I gs )
∂V gs
≈
1
nVT
From this, we see that despite the shift in the Igs curve, taking the derivative with respect
to V gs will still yield the correct (nVT ) term.
A.3. Substrate Trapping Model Analysis
Complete Substrate Trapping Model
An accepted interpretation of substrate trapping on electrical behavior is that trapped
charges alter the voltage measured at the bulk interface between the drain and source.
Although trapping may occur anywhere, this bulk voltage is usually manifested at a
single point, a fourth terminal called the back-gate. As a function of the drain-source
voltage and trapping state, the backgate voltage, VB , is computed using a substrate
charge-trapping model implemented between the intrinsic drain and source terminals of
the large-signal model as shown in Fig. A-4. This backgate potential influences the
efficacy of the space-charge created by the applied gate voltage.
419
Rd
Ld
Drain
Cds
Ids
VB
Charge
Trapping
Model
Vdsi
Rs
Ls
Source
Fig. A-4
Implementation of substrate trapping model.
The backgate voltage can then be implemented as an offset to the applied gate voltage
Voff , subs = ρ BV B
(A-20)
where and ρ B is a proportionality constant representing the influence of the backgate
voltage to the effective forward-gate voltage.
420
Vds
Vds1
Vds2
Vds0
t0
t1
time
t2
τ capture
VB
ρRVds1
ρC(Vds2-Vds1)
ρC(Vds1-Vds0)
ρRVds2
ρRVds0
t0
τ release
t1
t2
time
t1
t2
time
Voff,subs
ρBVB1
ρBVB2
ρBVB0
t0
Fig. A-5
Transient diagram of the full substrate trapping model.
(see DISS_Tran_charge_trap_model.dsn).
The charge trapping behavior according to the model introduced by [55] and used in
nonlinear FET models of [56] is described next [57]. The capture and emission behavior
of substrate traps can be illustrated using stepped or long-duration pulse responses at the
drain of the device as shown in Fig. A-5. The figure shows a transient backgate voltage,
VB , in response to a stepped Vds excitation.
421
Charge capture occurs when the pulsed voltage is higher than the static voltage
( Vds1 > Vds 0 ) and the pulse duration is larger than the capture constant, or τ pulse > τ capture .
In Fig. A-5, at time t = t 0 , Vds = Vds 0 = 0 , VB = ρ RVds 0 = 0 and there is no static trapping.
At t = t1 , Vds steps high from Vds 0 to Vds1 , and the backgate voltage VB increases nearly
instantaneously by ρ C (Vds1 − Vds 0 ) followed by an exponential approach toward ρ RVds1 as
traps are slowly filled.
Charge emission occurs when the pulsed voltage is lower than the static voltage
( Vds 2 < Vds1 ) and the pulse duration is larger than the emission constant τ pulse > τ release ,.
Continuing the analysis of Fig. A-5, at t = t 2 , Vds steps low from Vds1 to Vds 2 , causing VB
to decreases nearly instantaneously by ρ C (Vds 2 − Vds1 ) followed by an exponential
approach toward ρ RVds 2 as a portion of traps are slowly emptied. Some trapping still
remains, however, since Vds 2 > 0 .
Note that in the example above, τ capture < τ release , but τ capture > τ release can also be true
in practice. The transient offset voltage Voff , subs is also shown in Fig. A-5 and is equal to
VB scaled by ρ B .
Complete substrate trapping circuit
422
Fig. A-6
(a) Complete dynamic trapping model from [55][56][57] with τ capture < τ release
and (b) reversed submodel with τ capture > τ release .
The dynamic substrate charge-trapping model which computes the behavior described
in Fig. A-5 is shown in Fig. A-6 [55] [56]. The model consists of two series capacitors,
C SB and C BD , which store the charges associated with captured carriers between the
source-backgate and backgate-drain terminals, respectively. These capacitors form a
capacitive divider characterized by
ρC =
C BD
C BD
=
.
CB
C BD + C SB
(A-21)
The near instantaneous transitions at t = t 2 and t = t 2 in Fig. A-4 are due to the
charging of the series C BD and C SB with a very small time constant through the parasitic
resistances Rs , Rd and the pulse generator resistance.
423
Additionally, two resistors, RSB and RBD , divide the drain-source voltage into a static
backgate voltage representative of the static trap state. The static backgate voltage is
computed from the resistive divider
ρR =
RSB
.
RSB + RBD
(A-22)
Finally, a diode D B and resistor RB shunt pair connects the resistive and capacitive
dividers and dictates the time constants of the capture and release mechanisms. In other
words, the pair controls the charging and discharging of VB . The current of D B is
characterized by
I DB = I s (e VB / VT − 1)
(A-23)
from which the forward bias resistance can be computed as
RDB = VT / I DB
(A-24)
The orientation of D B shown in Fig. A-6a applies for case in which the capture time
constant is smaller than the release time constant, or τ capture < τ release , as assumed in the
transient plot of Fig. A-5. This results in the respective time constants of
τ capture = RDBCB
(A-25)
τ release = RBC B
(A-26)
However, the orientation of D B can be reversed in the case where τ capture > τ release as
shown in Fig. A-6b, allowing a versatile design of the charge capture and release.
Furthermore, as a peripheral circuit, the charge-trapping model must not disrupt the
output impedance of the overall FET model. Therefore, the resistances must be large and
capacitances must be small such that the impedance is relatively large.
Also, it is
424
necessary that RB >> RBD and RB >> RSB such that the ρ R voltage divider holds and the
time constant is dominated by RB .
Simplified Trapping Model
Although the Ouarch model provides an accurate description of the dynamic trapping
behavior, its implementation requires PIV of various pulse durations to determine the
behavior of VB as well as a means to compute ρ B ,. This leads to an unnecessarily
arduous process of modeling the transient trapping effect which provides only minimally
improved predictions of PIV and large-signal RF output.
As shown in (A-20), the end-product is the model which computes the chargetrapping effect on the forward-gate voltage. Therefore the trapping effect is a direct
function of Vds , which allows the computation of VB to be bypassed.
Instead, a model which computes the direct influence of substrate trapping on the
forward gate voltage is developed yielding an effective, yet straightforward
characterization strategy.
The trapping model stores the quiescent trapping state as
determined by the terminals biases and computes the proper gate-source offset voltage
modification. This model also uses only one time constant for both capture and release.
425
Vds
Vds1
Vds2
Vds0
t0
t1
t2
time
τ trap
Voff,trap
ρtrapVds1
τ trap
ρtrapVds2
ρtrapVds0
t0
Fig. A-7
t1
t2
time
Transient diagram of the simplified substrate trapping model.
In the simplified charge-trapping model, only one time constant is used for both
capture and release and the instantaneous stepped behavior of the charge traps has been
eliminated. A transient diagram for the simplified model is shown in Fig. A-7 where the
offset voltage is directly defined as
Voff ,trap = ρ trapVds
(A-27)
At time t = t 0 , Vds = Vds 0 = 0 , the device experiences no trapping effects and
Voff ,trap = 0 .
At t = t1 , Vds is stepped up from Vds 0 to Vds1 causing Voff ,trap to rise
exponentially towards the saturation level of ρ trapVds1 as the traps are slowly filled. At
this point the trapping level is in steady state with Vds1 . Then at t = t 2 , Vds is stepped
426
down from Vds1 to Vds 2 causing Voff ,trap to decay exponentially to ρ trapVds 2 as a portion of
the traps are slowly emptied.
Note that despite the differences in the two models, the Voff ,trap responses of Fig. A-5
and Fig. A-7 are not vastly different and the basic behavior is preserved despite the
applied simplifications.
Vds
Rtrap1
iRtrap1
Voff,trap
Rtrap2
Fig. A-8
iRtrap2
iCtrap
Ctrap
Charge-trapping model used in the SiC MESFET and GaN HEMT models.
The simplified charge-trapping model used in this modeling work is shown in Fig.
A-8.
The model consists of a resistive divider formed by Rtrap1 and Rtrap 2 which
produces the proportionality constant that combines ρ R and ρ B into a single parameter:
ρ trap =
Rtrap 2
Rtrap 2 + Rtrap1
(A-28)
The single capacitor C trap stores the cumulative effect of the trapping state on the
forward-gate voltage. The shared capture and release trapping time constant is equal to
427
(A-29)
τ trap = ( Rtrap1 || Rtrap 2 )C trap
and the solution for the voltage Voff ,trap under charging conditions is
[
Voff ,trap = ρ trap (Vdsi − Vdsf )e
− t / τ trap
+ Vdsf
]
(A-30)
where Vdsi and Vdsf are the initial and final value for the stepped Vds response,
respectively.
Like the complete trapping model [56], the component values of the simplified model
need to be scaled appropriately so that its impedance is large and does not interfere with
the electrical output impedance of the overall model.
Transient trapping effects, in general, do not appear under microwave excitation and
will only arise at certain intermediate frequencies. Therefore, the trapping model can be
further simplified by forgoing the detailed characterization of the transient behavior. It is
still required that the trapping model distinguish between quiescent and short-duration
pulsed behavior. However, this can be achieved by assuming a relatively large τ trap as
done during the development of the thermal model (Chapter 2.2.3.6).
Under this
assumption, (A-30) simplifies to a function of the quiescent drain-source voltage only:
Voff ,trap = ρ trapVdsi = ρ trapVdsq
(A-31)
assuming that the initial drain source has been set for a long time.
Therefore, defining the trapping-induced offset voltages as a function of the quiescent
bias will emulate the effect of the RC charge-trapping model. As a result, no circuit
model is needed for modeling the charge-trapping phenomena and τ trap will
automatically share the same value as the time constant used to compute Vdsq .
428
Since the simplified model computes the influence of the trap state rather than the
trap state itself, it can be used for any number of trapping phenomena that affects the
forward-gate voltage. This model can be employed for both substrate and surface traps.
A.4. Fukui-related Analyses
Derivation of explicit Fukui R g equation
Prove the following relationship is true:
Rg
= R − [R R
c
a
b
− Rc ( Ra + Rb ) + Rc
1
2 2
]
From Chapter 2.2.4:
Ra = Rg + Rs
Rb = R g + Rd
Rc = R g + Rd || Rs
Expanding Rd || Rs
Rd Rs
Rd + Rs
Rd || Rs =
0
= Rd Rs − ( Rd || Rs )( Rd + Rs )
( Rd || Rs ) 2
= Rd Rs − ( Rd || Rs )( Rd + Rs ) + ( Rd || Rs ) 2
( Rd || Rs ) 2
= ( Rd − Rd || Rs )(Rs − Rd || Rs )
( Rd || Rs )
2
( Rd || Rs ) 2
= ( Rb − Rc )( Ra − Rc )
= Ra Rb − Rc ( Ra + Rb ) + Rc
[
Rd || Rs = Ra Rb − Rc ( Ra + Rb ) + Rc
Therefore,
Rc = R g + Rd || Rs
1
2 2
]
2
429
R g = Rc − Rd || Rs
[
Rg = Rc − Ra Rb − Rc ( Ra + Rb ) + Rc
1
2 2
]
Derivation of parallel diodes
Fig. A-9
Equivalent model for Fukui measurement with drain short and source short.
From the Shockley diode model, an expression for the diode impedance can be
written.
I D ≈ I S e VD /( nVT )
 1
∂I D
= I S e VD /( nVT ) 
∂V D
 nVT
ZD =
 ID
 =
 nVT
∂VD nVT
=
∂I D
ID
Therefore
Z gs =
(nVT )gs
I gs
and Z gd =
The equivalent impedance is
(nVT )gd
I gd
430
Z eq = ( Z gs + Rs ) || ( Z gd

1
1
+ Rd ) = 
+
Z +R Z +R
s
gd
d
 gs




−1



1
1
=
+
(nVT )gs
(nVT )gd

+ Rd
+ Rs
 I
I gd
gs








−1
At small I gs and I gd , the Z eq becomes the impedance of the two diodes in parallel
 I gs
I gd
Z eq ≈ 
+
 (nVT )gs (nVT )gd

−1

(nVT )gs (nVT )gd
 ≈

I gs (nVT )gd + I gd (nVT )gs

If (nVT )gs = (nVT )gd = (nVT ) then
Z eq ≈
(nVT )2
(nVT ) = ∂VDeq
=
(nVT )( I gs + I gd ) I g ,c ∂I Deq
This result shows that if we assume that the thermal voltage is the same then the
impedance of the two parallel diodes resembles another single diode which can be
represented using a single diode characteristic.
Additionally, we can see that when I gs and I gd are large (and thus I g is large), the
equivalent Z becomes
Z eq
 1
1 

≈ 
+
R
R
s
d


−1
≈ Rs || Rd
which is consistent with the Fukui extraction at high I g .
431
A.5. Pinched-FET Model Analysis and Parameter Extraction
The parasitic capacitances C pg , C pgd and C pd can be approximated from the Yparameters of the device under pinchoff bias. The pinched-FET model analysis is shown
here.
Fig. A-10
Equivalent pinched-FET model.
From the equivalent two port pinched-FET model is shown in Fig. A-10, the Yparameters are
Y11 =
I1
V1
Y12 =
V2 = 0
I1
V2
Y21 =
V1 = 0
I2
V1
Y22 =
V2 = 0
I2
V2
V1 = 0
KCL gives
I1 =V 1( jωC1 ) + (V1 − V2 )( jωC f )
(A-32)
I 2 =V 2( jωC2 ) + (V2 − V1 )( jωC f )
(A-33)
Solving for Y11 , V2 =0 and (A-32) becomes
I 1 =V 1( jω (C1 + C f ))
⇒ Y11 =
I1
= jω (C1 + C f ) = jω (C pg + C pgd + C gs + C gd )
V1
Solving for Y12 , V1 =0 and (A-32) becomes
432
I 1 = −V2 ( jωC f )
⇒ Y12 =
I1
= − jωC f = − jω (C pgd + C gd )
V2
Solving for Y21 , V2 =0 and (A-33) becomes
I 2 = −V1 ( jωC f )
⇒ Y21 =
I2
= − jωC f = − jω (C pgd + C gd )
V1
Solve for Y22 , V1 =0 and (A-33) becomes
I 2 =V 2( jω (C 2 + C f ))
⇒ Y22 =
I2
= jω (C 2 + C f ) = jω (C pd + C pgd + C ds + C gd )
V2
In summary
Y11 = jω (C pg + C pgd + C gs + C gd )
(A-34)
Y12 = − jω (C pgd + C gd )
(A-35)
Y21 = − jω (C pgd + C gd )
(A-36)
Y22 = jω (C pd + C pgd + C ds + C gd )
(A-37)
Assuming the following (see Chapter 2.2.5.1.1): C pgd =0, C gs = C gd , C pg = C pd ,
Extracting C pgd from the above assumption,
⇒ C pgd ≈ 0
Extracting C gd from Im{Y12 } of (A-35) and assuming C pgd =0
Im{Y12 } = −ω (C pgd + C gd ) ≈ −ωC gd
⇒ C gd ≈ −
Im{Y12 }
ω
Also, C gd can be extracted from Im{Y21 } of (A-36) instead
433
Im{Y21 } = −ω (C pgd + C gd ) ≈ −ωC gd
⇒ C gd ≈ −
Im{Y21 }
ω
Extracting C gs from Im{Y11 } of (A-34) and assuming C pgd =0 and C gs = C gd
Im{Y11 } = ω (C pg + C pgd + C gs + C gd ) ≈ ω (C pg + 2C gd )
⇒ C pg ≈
Im{Y11 }
ω
− 2C gd
Extracting C ds from Im{Y22 } of (A-37) and assuming C pgd =0 and C pg = C pd
Im{Y22 } = ω (C pd + C pgd + C ds + C gd ) ≈ ω (C pg + C ds + C gd )
⇒ C ds ≈
Im{Y22 }
ω
− C pg − C gd
In summary
C pgd ≈ 0
C gd ≈ −
C pg ≈
Cds ≈
Im{Y12 }
ω
Im{Y11}
ω
Im{Y22 }
ω
− 2C gd
− C pg − C gd
A.6. Cold-FET Model Analysis and Parameter Extraction
According to Dambrine, under cold-FET excitation ( V gs into forward conduction,
Vds =0), the model for the device is resistive channel model. The cold-FET model can be
represented by Fig. A-11 for two-port analysis.
434
Fig. A-11
Two-port circuit definitions for cold-FET model.
Since the channel is represented by a distributed network, the analysis of it is beyond
the scope of this work and can be found through the derivations in [108] and [110].
The Z-parameters of the network using the formulas obtained from [108] for the
channel network can still be computed.
According to Dambrine
Z11 ' =
where
Rch
+ Z dy
3
(A-38)
435
Z dy
 1

=
+ jωC dy 
R

 dy

−1
=
Rdy
(A-39)
1 + jωC dy Rdy
Rdy is actually the representation of the diode resistance when biased into forward
conduction (as is done for cold-FET measurements) and can be found by taking the
inverse of the derivative of the gate-source diode current, I g
 ∂I
Rdy =  g
 ∂Vg

−1
−1
−1
Vg
−1


 Vg


 I 
 =  ∂ ( I s e nVT )  =  I s e nVT 1  =  g  = nVT
 nV 

 ∂Vg


nVT 
Ig
 T





Plugging this into (A-39)
Z dy =
Rdy
1 + jωCdy Rdy
=
1
1
+ jωCdy
Rdy
=
1
Ig
nVT
+ jωCdy
≈
nVT nkT
≈
Ig
qI g
and plugging this into (A-38)
Z 11 ' ≈
Rch nkT
+
3
qI g
(A-40)
Also, according to [108]
Z12 ' =
Rch
2
(A-41)
Z 21 ' =
Rch
2
(A-42)
Z 22 ' = Rch
(A-43)
Now, applying KVL to the two-port network of Fig. A-11.
V1 = I1 ( Rg + jωLg ) + V1 '+ ( I1 + I 2 )( Rs + jωLs )
(A-44)
V2 = I 2 ( Rd + jωLd ) + V2 '+ ( I1 + I 2 )( Rs + jωLs )
(A-45)
Now, solve for Z ' parameters in terms of Z parameters. The Z parameters are
436
Z 11 =
V1
I1
Z 12 =
I 2 =0
V1
I2
Z 21 =
I1 = 0
V2
I1
Z 22 =
I 2 =0
V2
I2
I1 = 0
Computing Z 11 by using (A-40) and I 2 =0, (A-44) becomes
V1
V'
= R s + R g + 1 + jω ( L s + L g )
I1
I1
R
nkT
⇒ Z 11 = Rs + R g + Z 11 '+ jω ( Ls + Lg ) ≈ Rs + Rg + ch +
+ jω ( L s + L g )
3
qI g
V1 = I 1 ( Rg + jωLg ) + V1 '+ I 1 ( Rs + jωLs ) ⇒
Computing Z 12 by using (A-41) and I 1 =0, (A-44) becomes
V1 V1 '
=
+ Rs + jωLs
I2 I2
R
= Z 12 '+ Rs + jωLs = ch + Rs + jωLs
2
V1 = V1 '+ I 2 ( Rs + jωLs ) ⇒
⇒ Z 12
Computing Z 21 by using (A-42) and I 2 =0, (A-45) becomes
V2 V 2 '
=
+ Rs + jωLs
I1
I1
R
= Z 21 '+ Rs + jωLs = ch + Rs + jωLs
2
V2 = V2 '+ I 1 ( Rs + jωLs ) ⇒
⇒ Z 21
Computing Z 22 by using (A-43) and I 1 =0, (A-45) becomes
V2 = I 2 ( Rd + jωLd ) + V2 '+ I 2 ( Rs + jωLs ) ⇒
V2
V '
= R s + R d + 2 + jω ( L s + L d )
I2
I2
⇒ Z 22 = Rs + Rd + Z 22 '+ jω ( Ls + Ld ) = Rs + Rd + Rch + jω ( Ls + Ld )
In summary for the cold-FET model
Z11 = Rs + Rg +
Rch nkT
+
+ jω ( Ls + Lg )
3
qI g
(A-46)
Z 12 = Rs +
Rch
+ jωLs
2
(A-47)
Z 21 = Rs +
Rch
+ jωLs
2
(A-48)
437
Z 22 = Rs + Rd + Rch + jω ( Ls + Ld )
Now, extracting the inductances from the Z equations is straightforward.
Extracting Ls from Im{Z12 } of (A-47) gives
Im{Z12 } = ωLs
⇒ Ls =
Im{Z12 }
ω
Also, extracting Ls from Im{Z 21 } of (A-48) gives
Im{Z 21 } = ωLs
⇒ Ls =
Im{Z 21 }
ω
Extracting Lg from Im{Z11 } of (A-46) gives
Im{Z11 } = ω ( Ls + L g )
⇒ Lg =
Im{Z11 }
ω
− Ls
Extracting Ld from Im{Z 22 } of (A-49) gives
Im{Z 22 } = ω ( Ls + Ld )
⇒ Ld =
Im{Z 22 }
ω
− Ls
In summary
Ls =
Lg =
Ld =
Im{Z12 }
ω
Im{Z11}
ω
Im{Z 22 }
ω
=
Im{Z 21 }
− Ls
− Ls
ω
(A-49)
438
Also, the parasitic resistances can be extracted in part using the real part of the Zparameters. From Re{Z11 }, if I g is large
Re{Z11 } = Rs + Rg +
Rch nkT
R
+
≈ Rs + Rg + ch
3
qI g
3
However, it may not be practical to use a large I g since it may damage the Schottky
gate. Therefore, rather than measuring cold-FET Z-parameters using a large I g , several
sets cold-FET Z-parameters at different I g are used. Plotting Re{Z11 }-vs- 1 / I g and
extrapolating the line down to 1 / I g ~0 will reduce Re{Z11 } as shown in [108].
The real part of the remaining Z-parameters are
Re{Z12 } = R s +
Rch
2
Re{Z 21 } = R s +
Rch
2
Re{Z 22 } = Rs + Rd + Rch
With three equations and four unknowns ( Rs , R g , Rch , Rd ), the parasitic resistances
can be approximated with the help of by obtaining an additional equation using the
Hower-Bechtel method or by using the parasitic resistances extracted from the Fukui
measurements.
A.7. Hot-FET Model Analysis and Parameter Extraction
Extrinsic-to-intrinsic network reduction
The reduction of the 2-port small signal network starts by subtracting out the parasitic
capacitances explicitly shown in Fig. A-12.
439
Fig. A-12
Two-port network subtracting parasitic capacitances.
Performing KCL at both ports
I 1 = V1 ( jωC pg ) + I 1 '+ (V1 − V2 )( jωC pgd )
(A-50)
I 2 = V2 ( jωC pd ) + I 2 '+ (V2 − V1 )( jωC pgd )
(A-51)
Now, solve for Y’ parameters in terms of Y parameters
Y11 =
I1
V1
Y12 =
V2 = 0
I1
V2
Y21 =
V1 = 0
I2
V1
Y22 =
V2 = 0
I2
V2
V1 = 0
Solving for Y11 , since V2 =0, (A-50) becomes
I 1 = I 1 '+V1 ( jω (C pg + C pgd )) ⇒
I1 I1 '
=
+ jω (C pg + C pgd )
V1 V1
⇒ Y11 = Y11 '+ jω (C pg + C pgd )
⇒ Y11 ' = Y11 − jω (C pg + C pgd )
Solve for Y12 , since V1 =0, (A-50) becomes
I 1 = I 1 '−V2 ( jωC pgd ) ⇒
⇒ Y12 = Y12 '− jωC pgd
⇒ Y12 ' = Y12 + jωC pgd
I 1 I1 '
=
− jωC pgd
V 2 V2
440
Solve for Y21 (similar to Y12 ), since V2 =0, (A-51) becomes
I 2 = I 2 '−V1 ( jωC pgd ) ⇒
I2 I2 '
=
− jωC pgd
V1 V1
⇒ Y21 = Y21 '− jωC pgd
⇒ Y21 ' = Y21 + jωC pgd
Solve for Y22 (similar to Y11 ), since V1 =0, (A-51) becomes
I 2 = I 2 '+V2 ( jω (C pd + C pgd )) ⇒
I2 I2 '
=
+ jω (C pd + C pgd )
V2 V2
⇒ Y22 = Y22 '+ jω (C pd + C pgd )
⇒ Y22 ' = Y22 − jω (C pd + C pgd )
Therefore, in summary
Y12 + jωC pgd

Y11 ' Y12 ' Y11 − jω (C pg + C pgd )
Y ' Y ' =  Y + jωC
Y22 − jω (C pd + C pgd )
21
pgd
 21
22 

The next step in the reduction process is to subtract out the parasitic inductances and
resistances which are explicitly shown in Fig. A-13.
I1'
+
V1'
I1"
Lg
Z"
Rg +
V1" Rs
I2"
+ Rd
- V2"
I2'
Ld
+
I1'=I1”
V2'
I1'+I2'
Ls
Fig. A-13
I2'=I2"
-
Two-port network subtracting parasitic inductances and resistances.
Write KVL at both ports
441
V1 ' = I1 ' ( R g + jωLg ) + V1 "+( I 1 '+ I 2 ' )( R s + jωLs )
(A-52)
V2 ' = I 2 ' ( Rd + jωLd ) + V2 "+ ( I 1 '+ I 2 ' )( Rs + jωLs )
(A-53)
Now, solve for Z” parameters in terms of Z’ parameters.
Z 11 ' =
V1 '
I1 ' I
Z 12 ' =
2 '=0
V1 '
V '
Z 21 ' = 2
I 2 ' I '=0
I1 ' I
1
Z 22 ' =
2 '=0
V2 '
I 2 ' I '=0
1
Solving for Z 11 ' , since I 2 ' =0, (A-52) becomes
V1 ' = V1 "+ I1 ' ( R g + R s + jω ( Lg + Ls )) ⇒
V1 ' V1 "
=
+ ( R g + R s + jω ( Lg + Ls ))
I1 ' I1 '
⇒ Z 11 ' = Z 11 "+ ( R g + Rs + jω ( Lg + Ls ))
⇒ Z 11 " = Z 11 '− ( R g + R s + jω ( L g + Ls ))
Solve for Z 12 ' , since I 1 ' =0, (A-52) becomes
V1 ' = V1 "+ I 2 ' ( Rs + jωLs ) ⇒
V1 ' V1 "
=
+ ( Rs + jωLs )
I2 ' I2 '
⇒ Z 12 ' = Z12 "+ ( Rs + jωLs )
⇒ Z 12 " = Z 12 '−( Rs + jωLs )
Solve for Z 21 ' , since I 2 ' =0, (A-53) becomes
V 2 ' = V 2 "+ I 1 ' ( R s + jω Ls ) ⇒
V2 ' V2 "
=
+ ( R s + jωL s )
I1 '
I1 '
⇒ Z 21 ' = Z 21 "+ ( R s + jω Ls )
⇒ Z 21 " = Z 21 '− ( R s + jω Ls )
Solve for Z 22 ' , since I 1 ' =0, (A-53) becomes
V2 ' = V2 "+ I 2 ' ( Rd + Rs + jω ( Ld + Ls )) ⇒
⇒ Z 22 ' = Z 22 "+ ( Rd + Rs + jω ( Ld + Ls ))
⇒ Z 22 " = Z 22 '− ( Rd + Rs + jω ( Ld + Ls ))
Therefore, in summary
V 2 ' V2 "
=
+ ( Rd + Rs + jω ( Ld + Ls ))
I2 ' I2'
442
Z12 '−( Rs + jωLs )
 Z11" Z12 "  Z11 '−( Rg + Rs + jω ( Lg + Ls ))

 Z " Z " = 
Z 21 '−( Rs + jωLs )
Z 22 '−( Rd + Rs + jω ( Ld + Ls ))
 21
22 

Intrinsic network Y-parameters
The next step is to analyze the Y”-parameters of the intrinsic network shown in Fig.
A-14.
Fig. A-14
Intrinsic small signal network.
First, expanding ids with respect to V1 " gives
ids = g m e − jωτ vgs
1


jωC gs

ids = g m e − jωτ 
1
+ R gs

 jωC gs


g m e − jωτ

V1 " = V1 " 1 + jωC R
gs gs


(A-54)
Performing KCL at port 1


1
 + (V1 "−V2 " ) jωC gd
I 1 " = V1 " 
 R + 1 /( jωC ) 
gs
gs


Performing KCL at port 2
I 2 " = ids + V2 " ( jωC ds + 1 / Rds ) + (V2 "−V1 " ) jωC gd
(A-55)
443
Insert (A-54) to obtain
g m e − jωτ
I 2 " = V1 "
+ V2 " ( jωC ds + 1 / Rds ) + (V2 "−V1 " ) jωC gd
1 + jωC gs R gs
By definition, the Y”-parameters are
Y11 " =
I"
I "
I "
I1"
Y12 " = 1
Y21 " = 2
Y22 " = 2
V1 " V "=0
V 2 " V "= 0
V1 " V "=0
V 2 " V "= 0
2
1
2
1
Solving for Y11 " , since V2 " =0, (A-55) becomes


1
1
 + V1 " jωC gd ⇒ I 1 " =
I 1 " = V1 " 
+ jωC gd
 Rgs + 1 /( jωC gs ) 
ω
V
"
R
+
1
/(
j
C
)
1
gs
gs


1
⇒ Y11 " =
+ jωC gd
Rgs + 1 /( jωC gs )
Solving for Y12 " , since V1 " =0, (A-55) becomes
I 1 " = −V2 " jωC gd ⇒
I1 "
= − jωC gd
V2 "
⇒ Y12 " = − jωC gd
Solve for Y21 " , since V2 " =0, (A-56) becomes
g m e − jωτ
I2"
g m e − jωτ
I 2 " = V1 "
− V1 " jωC gd ⇒
=
− jωC gd
1 + jωC gs R gs
V1 " 1 + jωC gs R gs
⇒ Y21 " =
g m e − jωτ
− jωC gd
1 + jωC gs Rgs
Solve for Y22 " , since V1 " =0, (A-56) becomes
I 2 " = V2 " (1 / Rds + jω (C gd + C ds )) ⇒
⇒ Y22 " = 1 / Rds + jω (C gd + C ds )
In summary
I2"
= 1 / Rds + jω (C gd + C ds )
V2 "
(A-56)
444
Y11 " =
1
+ jωC gd
Rgs + 1 /( jωC gs )
(A-57)
(A-58)
Y12 " = − jωC gd
g m e − jωτ
− jωC gd
1 + jωC gs R gs
(A-59)
Y22 " = 1 / Rds + jω (C gd + C ds )
(A-60)
Y21 " =
Intrinsic network parameter extraction
The intrinsic network parameters can be extracted from the Y”-parameter equations.
Extracting C gd from Im{Y12 "} of (A-58) gives
Im{Y12 "} = −ωC gd
⇒ C gd = −
Im{Y12 "}
ω
Capacitance C gd can also be extracted from Im{Y21 "} of (A-59) at ω → ∞ , which zeroes
the first term and gives
Im{Y21 "} ≈ −ωC gd
⇒ C gd ≈ −
Im{Y21 "}
ω
Extracting Cds from Im{Y22 "} of (A-60) in terms of C gd
Im{Y22 "} = ω (C gd + C ds )
⇒ C ds =
Im{Y22 "}
ω
− C gd
Extracting C gd can be performed by converting (A-57) into real and imaginary parts
445
Y11 "
=
1
+ jωC gd
Rgs + 1 / jωC gs
jωC gs
=
=
=
=
=
=
jωC gs R gs + 1
+ jωC gd
1 − jωC gs Rgs
jωC gs
1 + jωC gs R gs 1 − jωC gs Rgs
ω 2 C gs 2 R gs + jωC gs
2
1 + ω 2 C gs Rgs
ω 2 C gs 2 R gs
2
1 + ω 2 C gs R gs
2
ω 2 C gs 2 R gs
2
1 + ω 2 C gs R gs
ω 2 C gs 2 R gs
D
2
2
2
+
+ jωC gd
+ jωC gd
jωC gs
2
1 + ω 2 C gs Rgs
2
+ jωC gd


C gs

+ jω 
+
C
gd
 1 + ω 2 C gs 2 R gs 2



 C gs

+ jω 
+ C gd 
 D

(A-61)
2
where D = 1 + ω 2 C gs Rgs .
Then, C gs can be solved from Im{Y11 "} of (A-61) giving
 C gs

Im{Y11 "} = ω 
+ C gd 
 D

 Im{Y11 "}


2
2  Im{Y11 "}
⇒ C gs = D
− C gd  = 1 + ω 2 C gs R gs 
− C gd 
 ω

 ω

(
2
)
2
At low frequency, ω 2 C gs R gs << 1 and this simplifies to
C gs ≅
Im{Y11"}
ω
− C gd
Extraction of Rds can be performed from Re{Y22 "} of (A-60) giving
Re{Y22 "} =
1
= g ds
Rds
446
Extracting the g m is performed using Y21 " (A-59). First, define g m and exponential term
as vector, that is
g m = g m e − jωτ and also g m = g m constant
Expanding Y21" gives
g m e − jωτ
= (Y21 "+ jωC gd )(1 + jωC gs Rgs )
= Y21 "+ jωC gd + jωC gs R gs Y21 "−ω 2 C gs R gs C gd
= (Re{Y21 "} + j Im{Y21 "}) + jωC gd
+ jωC gs Rgs (Re{Y21 "} + j Im{Y21 "}) − ω 2 C gs R gs C gd
= Re{Y21 "} − Im{Y21 "}ωRgs C gs − ω 2 R gs C gs C gd
+ j (Im{Y21 "} + ωC gd + ωR gs C gs Re{Y21 "})
= g mr + jg mi
where
g mr = Re{Y21 "} − Im{Y21 "}ωR gs C gs − ω 2 R gs C gs C gd
and
g mi = Im{Y21"} + ωC gd + ωRgs C gs Re{Y21"}
Observe that the magnitude of the left term is equal to g m , therefore, the same must be
true for the entire right hand term.
g m e − jωτ = g m
⇒ g m = g mr + jg mi
Assuming R gs =0, which is true in most cases, g mr , g mi and g m can be approximated
g mr ≈ Re{Y21"}
g mi ≈ Im{Y21"} + ωC gd
and
447
2
(Re{Y21"})2 + (Im{Y21"} + ωC gd )2
2
g m ≅ g mr + jg mi = g mr + g mi =
Also notice that
ωC gd = − Im{Y12 "}
Therefore, g m can be written as
≅
gm
(Re{Y21"})2 + (Im{Y21"} − Im{Y12 "})2
For low freq, low noise, all terms are small except for Re{Y21"} . Therefore,
≅ Re{Y21 "}
gm
Extraction of R gs is performed from Re{Y11 "} from (A-61)
Re{Y11 "} =
(
ω 2 C gs 2 Rgs
D
2
Re{Y11 "}1 + ω 2 C gs Rgs
=
2
ω 2 C gs 2 Rgs
2
1 + ω 2 C gs R gs
)= ω C
2
2
2
gs
2
2
Rgs
2
Re{Y11 "} + Re{Y11 "}ω 2 C gs R gs = ω 2 C gs Rgs
2
2
2
R gs Re{Y11 "}ω 2 C gs − Rgs ω 2 C gs + Re{Y11 "} = 0
Applying the quadratic formula gives
448
=
R gs
=
2
)
ω 2 C gs 2 ± ω 2 C gs 2 ω 2 C gs 2 − 4(Re{Y11 "})2
)
ω 2 C gs 2 ±
(ω C )
(
2 2
2
− 4 Re{Y11 "}ω 2 C gs Re{Y11 "}
gs
2 Re{Y11 "}ω 2 C gs
2
(
2 Re{Y11 "}ω 2 C gs
ω 2 C gs 2 ±
=

{Y
(ω C ) 1 − 4(Re
ω C
2 2
2
gs
2
2
ω C gs ± ω C gs
=
2
2

=
2
2
1−
4(Re{Y11 "})
ω 2 C gs 2
2 Re{Y11 "}ω 2 C gs
1± 1−
2
"}) 
2

gs

11
2 Re{Y11 "}ω 2 C gs
2
2
4(Re{Y11 "})
2
2
ω 2 C gs 2
2 Re{Y11 "}
Extraction of τ is performed from the expression for g m
g m = g m e − jωτ = g mr + jg mi
And in phasor form, this is
gm = gm ∠g m
where
g 
∠ g m = tan −1  mi 
 g mr 
g 
− ωτ = tan −1  mi 
 g mr 
τ =−
g 
tan −1  mi 
ω
 g mr 
1
Again, assuming R gs small or near zero gives
449
τ ≅−
 Im{Y21"} − Im{Y12 "} 

tan −1 
ω
Re{Y21"}


1
In summary
C gd = −
C ds =
C gs ≅
Im{Y12 "}
ω
Im{Y22 "}
ω
Im{Y11"}
ω
− C gd
− C gd
g m ≅ Re{Y21"}
Rds =
1
1
=
Re{Y22 "} g ds
1± 1−
Rgs =
τ ≅−
2
4(Re{Y11"})
ω 2C gs 2
2 Re{Y11"}
 Im{Y21"} − Im{Y12 "} 

tan −1 
ω
Re{Y21"}


1
450
APPENDIX B. FREQUENCY MULTIPLIER
B.1. Power Available from an RF Source
An RF power generator is shown in Fig. B-1.
Fig. B-1
Power available from the source.
For maximum power delivered, a matched load is assumed Z S = Z L = Z o
Instantaneous power
V1 = V A
Zo
V
= A
Zo + Zo
2
2
2
V1
V1
(V A / 2) 2 V A
P1 = I 1V1 =
V1 =
=
=
Zo
Zo
Zo
4Z o
V A = 4Z o P1
RMS power
Converting the output into RMS (root-mean-squared) voltage will allow the computation
of the average available RF power from the source, Pavs :
2
Pavs = P1rms
2
2
V
 V  1 VA
= 1rms =  A 
=
Zo
 2 2  Z o 8Z o
451
Explanation of RMS power
From Joule’s and Ohm’s law
V2
P=
= I 2R
R
The bracket operator
means “average” or “mean”
2
P = I 2 R = I 2 R = I rms R
=
I rms
I rms
I rms
2
τ2
1
[ I (t )]2 dt
∫
τ
τ 2 − τ1 1
=
lim
1
τ → ∞ 2τ
=
I (t ) 2
τ
∫ τ [ I (t )] dt
2
−
= I (t ) 2
=
lim
τ →∞
1 τ
[ I (t )]2 dt
∫
23
−
τ
2τ 1
squared
144244
3
mean of a squared
1442443
root of a mean of a squared
Consider a sine wave excitation. Show how y = a sin ωt ⇒
I rms
1
=
T
∫
0
2
( I A cos ωt ) dt =
sin 2ωT 

T +

2ω 

( where ωT = 2π )
=
IA
2T
=
IA
T
2T
2
=
IA
2
2
IA
T
T
2
∫
T
0
2
a
rms .
2
(cos ωt )dt =
2
IA
2T
∫
T
0
(1 + cos 2ωt )dt
452
Vrms
=
1
T
=
VA 
sin 2ωT 
T +

2T 
2ω 
T
∫
0
(V A cos ωt ) 2 dt =
VA
T
2
∫
T
0
(cos 2 ωt )dt =
2
VA
2T
T
∫
0
(1 + cos 2ωt )dt
2
( where ωT = 2π )
2
=
=
VA
T
2T
VA
2
B.2. Fourier Series of a Periodic Waveform
The a periodic waveform can be expressed in terms of it Fourier series coefficients:
∞
f (t ) = a0 + a1 cos ωt + a2 cos 2ωt + K = a0 + ∑ an cos nωt
n =1
where
a0 =
1
T
an =
2 T2
f (t ) cos(nωt )dt
T ∫−T 2
∫
T 2
−T 2
f (t )dt
and
A change of the integration variable from t into θ is applied.
This consists of a
substituting t as a function of θ and a modification of the integration limits.
Since θ = ωt , this gives
t=
θ
ω
and
dt =
1
ω
dθ .
453
The time-domain limits of integration are performed over an entire period T from
t0 = −
T
T
2π
to t1 = . Since θ = ωt and ωT = 2π ⇒ ω =
, this gives
2
2
T
θ 0 = ωt 0 =
2π  T 
 −  = −π
T  2
θ1 = ωt1 =
2π  T 
 =π
T 2
and
This gives
a0
=
1 T2
1
f (t )dt =
∫
−
2
T
T
ωT
=
1 π
2
2π ∫0
1
π
π
−
π
θ 
−
θ 
f  dθ
ω 
θ 
f  dθ
ω 
=
π∫
=
2 T2
2
f (t ) cos(nωt )dt =
∫
T −T 2
ωT
=
2
2π
∫ π f  ω  cos(nθ )dθ
2
π
0
1
θ 
∫ π f  ω dθ = 2π ∫ π f  ω dθ
Similarly,
an
=
π
π
θ 
∫ π f  ω  cos(nθ )dθ
−
θ 
−
π∫
0
θ 
f   cos(nθ )dθ
ω 
Single-sided Vp clipped waveform analysis [135]
The generic one nonlinearity model used to derive the single-sided Vp-clipped
Fourier coefficients is
0
Vg < V p

I ds = 
G (Vg − V p ) V p ≤ Vg
454
Vp ≤ (VGG + VA) ≤ Vf
Ids
Ids
(VGG - VA) ≤ Vp
0 ≤ 2φ ≤ 2π
IDSS
slope G
2φ
VB
Ip
VGG
Vp
Vf
Vg
-π
0
π
2π
ωt
I DSS = G (V f − V p )
φ
Vg
VA
V g = VGG + V A cos ωt
I p = G(V A − VB )
φ = cos −1 (VB VA )
VB = V p − VGG
ωt
Fig. B-2
Single-sided clipped waveform analysis of Clarke and Hess.
For a single-sided clipped drain current waveform, the Fourier coefficients I dsn are
synonymous with the above analysis:
I ds 0 =
I dsn =
1
π∫
π
0
2
π
π∫
0
θ 
I ds  dθ
ω 
θ 
I ds   cos nθdθ
ω 
This is synonymous to saying that when the gate voltage passes above Vp and the device
is driven in to conduction, As a function of conduction angle, the drain current model
becomes
455
 θ  G (Vg − V p ) 0 ≤ θ ≤ φ
I ds (t ) = I ds   = 
0
φ <θ ≤ π
ω  
For φ < θ ≤ π , I ds = 0 and is therefore dropped out of the integration, resulting in a
change of limits of integration from π to φ .
For 0 ≤ θ ≤ φ , using Vg = VGG + VA cos(ωt ) = VGG + V A cosθ gives
I ds = G (VGG + V A cosθ − V p ) = G (V A cosθ − (V p − VGG )) = G (V A cosθ − VB )
Using the relationships defined in Fig. B-2
I p = G (V A − VB )
VB = (V p − VGG )
 VB 

V
 A
φ = cos−1
Express VB in terms of VA
 VB 
 ⇒ VB = VA cos φ
 VA 
φ = cos−1
Express VA in terms of VB
 VB 
V
 ⇒ VA = B
cosφ
 VA 
φ = cos−1
Express GVA in terms of φ and I p
I p = G (V A − V B ) = G (V A − V A cos φ ) = GV A (1 − cos φ )
⇒ GV A =
Ip
1 − cos φ
456
Express GVB in terms of φ and I p
 V

 1

 1 − cosφ 

I p = G (V A − VB ) = G  B − VB  = GVB 
− 1 = GVB 
 cos φ

 cos φ 
 cosφ 
 cosφ 

⇒ GVB = I p 
 1 − cos φ 
Using these relationships, the coefficients can now be solved in terms of φ and I p :
For n = 0
I ds 0
1
1
θ 
I ds  dθ =
π
ω 
θ 
I ds   dθ
ω 
1 φ
G φ
= ∫ G (VA cos θ − VB )dθ = ∫ VA cos θ − VB dθ
=
π∫
π
=
=
π
0
G
π
1
π
φ
∫
0
π
0
0
[V A sin θ − VBθ ]φ0 = G [V A sin φ − VBφ ]
π
GVA sin φ −
1
π
GVBφ
 cos φ  
1  Ip

sin φ − I p 
φ 
π  1 − cos φ
 1 − cos φ  
Ip
1
(sin φ − φ cos φ )
=
π 1 − cos φ
I p sin φ − φ cos φ
=
π
1 − cos φ
=
For n = 1
I ds1
2
π
π
0
2
θ 
I ds   cos θdθ =
π
ω 
θ 
I ds   cos θdθ
0
0
ω 
2 φ
2G φ
2
= ∫ G (V A cos θ − VB ) cos θdθ =
∫ V A cos θ − VB cosθdθ
=
π∫
Using trig identity cos2 θ =
φ
∫
π
1 + cos 2θ
gives
2
0
457
I ds1
2G
 1 + cos 2θ 

 − VB cos θdθ
2
π


2G φ V A V A
=
+
cos 2θ − VB cos θdθ
2
π ∫0 2
=
φ
∫V
0
A
φ
2G VA
V sin 2θ

=
− VB sin θ 
θ+ A

2
2
π 2
0
V sin 2φ
2G VA

− VB sin φ 
φ+ A

2
2
π 2

2 GV A
2 GVA sin 2φ 2
=
φ+
− GVB sin φ
π 2
π 2
π
2
=
Using trig identity sin 2φ = 2 cos φ sin φ gives
I ds1
=
Ip
Ip
1
2  cos φ 
φ
+
2 cos φ sin φ − I p 
 sin φ
π 1 − cos φ 2π 1 − cos φ
π  1 − cos φ 
1
(φ + cos φ sin φ − 2 cos φ sin φ )
π 1 − cos φ
Ip
1
=
(φ − cos φ sin φ )
π 1 − cos φ
I φ − cos φ sin φ
= p
π
1 − cos φ
Ip
=
For n ≥ 2
I dsn
=
=
=
=
2
π∫
π
0
2
φ
π∫
0
2
θ 
I ds   cos(nθ )dθ
ω 
θ 
I ds   cos(nθ )dθ
ω 
φ
G (V
π∫
0
2G
π
φ
∫V
0
A
A
cosθ − VB ) cos(nθ )dθ
cos(nθ ) cosθ − VB cos(nθ )dθ
Using the following trig identity
cos u cos v
=
1
[cos(u − v) + cos(u + v)]
2
458
1
[cos(nθ − θ ) + cos(nθ + θ )]
2
1
= [cos(θ (n − 1) ) + cos(θ (n + 1) )]
2
cos(nθ ) cosθ =
gives the following I dsn
2G
VA
[cos(θ (n − 1)) + cos(θ (n + 1))] − VB cos(nθ )dθ
2
π
2G φ V A
V
=
cos(θ (n − 1)) + A cos(θ (n + 1)) − VB cos(nθ )dθ
∫
0
2
2
π
=
I dsn
φ
∫
0
φ
2G VA sin (θ (n − 1) ) V A sin (θ (n + 1) )
sin( nθ ) 
=
+
− VB

2
n −1
n +1
n  0
π 2
Applying the following trig identities
sin( u ± v )
= sin u cos v ± cos u sin v
sin (θ (n ± 1))
= sin (nθ ± θ ) = sin( nθ ) cosθ ± cos(nθ ) sin θ
gives
φ
I dsn
2G V A  sin( nθ ) cos θ − cos( nθ ) sin θ sin( nθ ) cos θ + cos( nθ ) sin θ 
sin( nθ ) 
=
+

 − VB

π 2 
n −1
n +1
n  0

Since every term has a sin() operation, the 0 limit of integration can be dropped
I dsn
=
2G V A  sin(nφ ) cos φ − cos( nφ ) sin φ sin(nφ ) cos φ + cos( nφ ) sin φ 
sin(nφ ) 
+

 − VB
π  2 
n 
n −1
n +1

=
2 1
sin(nφ ) 
 sin(nφ ) cos φ − cos( nφ ) sin φ sin(nφ ) cos φ + cos( nφ ) sin φ 
GV A 
+
 − GVB

π 2
n −1
n +1
n 


=
=
2 1

Ip
 cos φ  sin(nφ ) 
 sin(nφ ) cos φ − cos( nφ ) sin φ sin(nφ ) cos φ + cos( nφ ) sin φ 

+

 − Ip

n −1
n +1

 1 − cos φ  n 
π  2 1 − cos φ 
2  I p  sin(nφ ) cos φ − cos( nφ ) sin φ sin(nφ ) cos φ + cos( nφ ) sin φ cos φ sin(nφ ) 

+
−


π 1 − cos φ 
2(n − 1)
2(n + 1)
n

Let X = sin(nφ ) cos φ and Y = cos(nφ ) sin φ
459
I dsn
1  X −Y X +Y  X 
+

−
π 1 − cosφ  2  n − 1
n + 1  n 
2 I p  1 ( n + 1)( X − Y ) + ( n − 1)( X + Y ) X 
=
− 
π 1 − cosφ  2
n
( n − 1)(n + 1)
2 I p  1 nX + X − nY − Y + nX − X + nY − Y X 
=
− 
π 1 − cosφ  2
n
n2 −1
2 I p  1 2nX − 2Y X 
=
− 
π 1 − cosφ  2 n 2 − 1
n
=
2
Ip
2
Ip
 nX − Y X 
−
π 1 − cosφ  n 2 − 1 n 
2 I p  n( nX − Y ) − ( n 2 − 1) X 
=

π 1 − cosφ 
n( n 2 − 1)

=
 n 2 X − nY − n 2 X + X 

π 1 − cosφ 
n( n 2 − 1)

2 I p  X − nY 
=
π 1 − cosφ  n(n 2 − 1) 
=
2
Ip
Substituting X and Y expansions back into equation
I dsn
=
2
 cos φ sin( nφ ) − n sin φ cos(nφ ) 

n(n 2 − 1)
π 1 − cos φ 

I dsn
=
2 I p cos φ sin( nφ ) − n sin φ cos(nφ )
π
n(n 2 − 1)(1 − cos φ )
Ip
Fourier coefficients single-sided clipped-waveform
I dsn
 I p sin φ − φ cos φ

1 − cos φ
π
 I p φ − cos φ sin φ
=
1 − cos φ
π
 2 I p cos φ sin( nφ ) − n sin φ cos(nφ )

 π
n(n 2 − 1)(1 − cos φ )
n=0
n =1
n≥2
460
B.3. Summary of Fourier Coefficients for All Operating Modes
V p clipped
I dsn
 I p1 sin φ1 − φ1 cos φ1

1 − cos φ1
π
 I φ − cos φ1 sin φ1
=  p1 1
1 − cos φ1
π
 2 I p1 cos φ1 sin( nφ1 ) − n sin φ1 cos(nφ1 )
 π
n(n 2 − 1)(1 − cos φ1 )

n=0
n =1
n≥2
V f clipped
I dsn

I p 2  sin φ2 − (φ2 − π ) cos φ2 


 I DSS −
1
−
cos
π
φ
2



 I 
 p 2 (φ2 − π ) − cos φ2 sin φ2 


= −
1 − cos φ2

 π 
 2 I cos φ sin( nφ ) − n sin φ cos(nφ )
2
2
2
2
− p 2
2
n(n − 1)(1 − cos φ2 )
 π
n=0
n =1
n≥2
Vk clipped
I dsn

I p 2,eff  sin φ 2,eff − (φ 2,eff − π ) cos φ 2,eff 


 I DSS ,eff −

1 − cos φ 2,eff
π 


 I


 p 2,eff  (φ2,eff − π ) − cos φ 2,eff sin φ 2,eff 
= −

1 − cos φ 2,eff
π 


 2I
cos φ2,eff sin( nφ2,eff ) − n sin φ 2,eff cos(nφ2,eff )
− p 2,eff
π
n(n 2 − 1)(1 − cos φ2,eff )

n=0
n =1
n≥2
VBV clipped
I dsn

I p1,eff sin φ1,eff − φ1,eff cos φ1,eff
I 0 +
1 − cos φ1,eff
π

 I p1,eff φ1,eff − cos φ1,eff sin φ1,eff
=
1 − cos φ1,eff
 π
 2 I p1,eff cos φ1,eff sin( nφ1,eff ) − n sin φ1,eff cos(nφ1,eff )

n(n 2 − 1)(1 − cos φ1,eff )
 π
n=0
n =1
n≥2
461
V p / V f clipped
 I DSS sin φ1 − φ1 cos φ1 − sin φ 2 + φ 2 cos φ2

cos φ 2 − cos φ1
 π
 I φ − cos φ1 sin φ1 − φ2 + cos φ 2 sin φ2
=  DSS 1
cos φ 2 − cos φ1
 π
 2 I DSS cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ 2 sin nφ 2 + n sin φ2 cos nφ 2

n(n 2 − 1)(cos φ2 − cos φ1 )
 π
I dsn
n=0
n =1
n≥2
Vk / V p clipped
 I DSS ,eff sin φ1 − φ1 cos φ1 − sin φ 2,eff + φ2,eff cos φ 2,eff

cos φ 2,eff − cos φ1
 π
 I DSS ,eff φ1 − cos φ1 sin φ1 − φ2,eff + cos φ 2,eff sin φ 2,eff
=
cos φ 2,eff − cos φ1
 π
 2 I DSS ,eff cos φ1 sin nφ1 − n sin φ1 cos nφ1 − cos φ 2,eff sin nφ 2,eff + n sin φ 2, eff cos nφ 2, eff

n( n 2 − 1)(cos φ 2,eff − cos φ1 )
 π
I dsn
n=0
n =1
n≥2
VBV / V f clipped

I DSS − I 0 sin φ1,eff − φ1,eff cos φ1,eff − sin φ 2 + φ 2 cos φ 2
I 0 +
π
cos φ 2 − cos φ1,eff

 I DSS − I 0 φ1,eff − cos φ1,eff sin φ1,eff − φ 2 + cos φ 2 sin φ 2
=
cos φ 2 − cos φ1,eff
 π
 2( I DSS − I 0) cos φ1,eff sin nφ1,eff − n sin φ1,eff cos nφ1,eff − cos φ 2 sin nφ 2 + n sin φ 2 cos nφ 2

π
n(n 2 − 1)(cos φ 2 − cos φ1,eff )

I dsn
n=0
n =1
n≥2
Vk / VBV clipped
I dsn

I DSS ,eff − I 0 sin φ1, eff − φ1, eff cos φ1,eff − sin φ 2,eff + φ 2,eff cos φ 2, eff
I 0 +
π
cos φ 2,eff − cos φ1,eff

 I DSS ,eff − I 0 φ1, eff − cos φ1, eff sin φ1,eff − φ 2, eff + cos φ 2, eff sin φ 2, eff
=
π
cos φ 2,eff − cos φ1,eff

 2( I DSS ,eff − I 0 ) cos φ1, eff sin nφ1, eff − n sin φ1, eff cos nφ1,eff − cos φ 2, eff sin nφ 2,eff + n sin φ 2,eff cos nφ 2,eff

π
n( n 2 − 1)(cos φ 2,eff − cos φ1,eff )

Linear
I dsn
− GVB

=  GV A
 0

n=0
n =1
n≥2
n=0
n =1
n≥2
462
Complete Pinchoff
I dsn = 0,
n≥0
Complete Forward Conduction
n=0
n ≥1
I
I dsn =  DSS
 0
Complete Knee
I
I dsn =  DSS ,eff
 0
n=0
n ≥1
Complete Breakdown
I
I dsn =  0
0
n=0
n ≥1
463
APPENDIX C. TEST AND MEASUREMENT
C.1. Test Board and Fixture for Device Characterization
Measurements of the packaged Cree, Inc. CRF24010 10W SiC MESFET and
CGH40010F 10W GaN HEMT devices are performed in a 50 ohm test fixture with the
transistor mounted on an aluminum plate fastened to a fan-cooled heat sink for heat
dissipation under high power drive as shown in Fig. C-1. The substrate for all circuits
produced here is Rogers RT/duroid 5880 20mil microwave laminate.
Fig. C-1
Test fixture (a) top (b) angle (c) side (d) bottom.
464
C.2. IV Characterization
Static IV
Cree
An early version of the static IV test setup is shown in Fig. C-2.
Fig. C-2
Static IV test setup.
Pulsed Gate IV
The pulsed gate IV setup used in this work is shown in the schematic of Fig. C-3 and
photo of Fig. C-4.
465
Fan Supply
VFAN
Test Fixture with
PIV Board
5
µ
F
SMA to
BNC
Z0=50Ω
39
Ω
Cree
Pulse
Generator
5
0
Ω
B
N
C
Z0=50Ω
S
M
A
Drain Supply
SMA to
BNC
1Ω
+
S
M
A
200uF
10uF
BNC
VGS
VDS
VDD
Digital Oscilloscope
GPIB Controller
running Agilent
VEE Pro
Trigger
Pulsed IV Measurement Setup
Fig. C-3
PGIV test setup.
Fig. C-4
PGIV test setup photo 2009 (a) Full view and (b) Zoomed view of test
fixture (gate voltage optional and not probed here).
-
466
C.3. Small-Signal Characterization
S-parameters setup
The S-parameters test setup is illustrated in Fig. C-5. Either the HP 8510B or Agilent
8364B PNA are used. For the S-parameter measurements, a combination external bias
T’s and internal (network analyzer built-in) attenutators are used. External bias T’s are
used because the internal bias T’s cannot handle the current and voltage requirements of
these high power devices.
8510 Network Analyzer
Port 1
Port 2
Drain
Supply
Gate
Supply
Ammeter
Test Fixture with
S-Parameter
Board
DC
R
F
Bias
Tee
R
F
D
C
VGS
Z0=50Ω
VFAN
Fig. C-5
S-parameters test setup.
DC
VDS
Z0=50Ω
R
F
D
C
Bias
Tee
R
F
467
Network Analyzer Calibration using Through-Reflect-Line calibration kit
According to [142], making measurements in a non-coaxial environment using a
coaxial calibration can result in undesired reflections at the junction between mediums.
The solid-state devices under test are designed to be employed under a microstrip
transmission line system. Therefore, the physical discontinuity between the coaxial test
cables to microstrip test fixture degrades the effectiveness of a standard 3.5mm coaxial
calibration on the packaged device.
To improve the quality of the S-parameter measurements, a microstrip-based ThruReflect-Line (TRL) calibration kit is developed. The design of the TRL cal kit follows
the procedure specified in [142] for the applied substrate medium and test fixture
dimensions.
The text fixture of fixed length requires three standards THRU, LINE and OPEN. In
the example TRL cal kit described next, the maximum frequency is 4.5GHz. However,
the frequency range can be extended through the use of addition LINE standards.
THRU
Non-zero THRU based on fixture dimensions
1.
Find physical length of the fixture
A drawing of the test fixture is shown in Fig. C-6. Using a caliper, we measure the
length of the fixture
L fixture = 7.940cm
468
Lxtr
L4
L5
Lfixture
Fig. C-6
2.
Test fixture dimensions.
Solve physical length of input and output TL lengths, L4 and L5
Since we know that Lxtr = 0.42cm [78][79], we can solve for L4 and L5 given that they
are equal.
L4 = L5 =
L fixture − Lxtr
2
=
7.940cm − 0.42cm
= 3.76cm
2
Then the physical length of THRU is LTHRU = 2( L4 ) = 7.52cm .
A drawing of the thru microstrip board is shown in Fig. C-7.
469
L4
L5
LTHRU
Fig. C-7
3.
Microstrip TRL THRU standard.
Convert this into electrical length using Agilent ADS LineCalc
Although it is not specified in [142], we believe that this electrical length is independent
of ε eff .
l 4 (deg) = 122.805o
⇒ l 4 (cm)
122.805o
⋅ λo (assume l 4 is independent of ε eff )
360 o
 c 
= 0.341125 ⋅  
 fo 
=
= 0.341125 ⋅ (14.9895cm )
= 5.11329cm
4.
Set offset delay
Offset delay should be 0ps so that the 8510 does not consider the length of THRU in the
measurement. This is because we are using a non-zero length THRU. In the case of a
zero length THRU, we need to incorporate the above calculation.
470
LINE
LINE is based on the frequency range that this cal kit will cover. The LINE length will
be an extension of the THRU length as shown in Fig. C-8.
LLINE
LTHRU/2
Fig. C-8
1.
LTHRU/2
Microstrip TRL LINE standard.
Compute the electrical length of LINE based on the frequency range and equation
(1) from [142].
First, let f1 (GHz ) =0.1 and f 2 (GHz ) =4.5. Then
l LINE (cm)
=
15
f1 (GHz ) + f 2 (GHz )
15
0.1 + 4.5
= 3.2608695(cm)
=
2.
Convert l LINE (cm) into electrical length in degrees l LINE (deg)
l LINE (deg)
=
l LINE (cm)
3.2608695cm
⋅ 360 deg =
λo (cm)
14.9895cm
= 78.3157 o
471
3.
Solve for physical length of LLINE using LineCalc with Z o =50 ohms
LLINE = 2.39785cm
4.
Compute offset delay of LINE
offset delay =
l LINE (cm)
3.26cm
=
= 108.74278 ps
cm
10 cm
c( )
2.9979 × 10
s
s
Enter this value for the cal kit standards
OPEN
The OPEN standard is composed of two lines, one at each port and a gap separating them
in the middle as shown in Fig. C-9. Both lines are length LTHRU/2 that is open on the
other end. The gap spacing used is equal to LLINE. Basically, the board is the same as the
LINE board but with a gap in the middle instead of a line.
LLINE
LTHRU/2
Fig. C-9
Microstrip TRL OPEN standard.
LTHRU / 2 = 3.76cm and LLINE = 2.39785cm
LTHRU/2
472
Modifying the Cal Kit
The resulting cal kit standards to be programmed into the 8510 network analyzer are
shown in Table C-1 and the Standard Class Assignments are shown in Table C-2.
Table C-1
Standard
No.
Type
14
15
Cal Kit Standards for TRL calibration
C0
C1
C2
C3
L0
L1
L2
L3
fixed
or
sliding
Terminal
impedance
offset
min
max
Coax
or
wave
guide
50
0.1
4.5
C
Line
1
50
0.1
4.5
C
Line
2
50
0.1
4.5
delay
ps
Zo
Ω
Delay
0
Delay
108.74
freq (GHz)
Loss
GΩ/s
Stnd
label
16
17
18
Open
Table C-2
Standard Class
Assignments
0
0
0
0
Standard Class Assignments for TRL calibration
A
B
C
D
E
F
G
open
Standard Class Label
TRL Thru
14
Thru
TRL Reflect
18
Open
TRL Line
15
Line
Fabrication
The standards were fabricated on microstrip board with parameters described in Table
C-3.
The microstrip standards were fabricated sequentially to minimize processing
variations and then cut precisely to preserve the line lengths.
473
Table C-3
Microwave substrate parameters used in this work
Parameter
Symbol
Value
Relative permittivity
Er
2.17
Relative permeability
Mur
1.0
Dielectric thickness
H
20.0 mil
Conductor thickness
T
1.0 mil
Conductivity
Cond
5.96e7
Loss tangent
TanD
0.0006
Back analysis
The fabricated S-parameter test board #2 (Fig. C-10) was fabricated slightly longer
than the length of the fixture plate. Therefore, washers are used between the microstrip to
SMA connector and the fixture plate as described in Fig. C-10.
Fig. C-10
S-parameter fixture plate.
Now, the actual length of the fabricated line is measured to back-calculate the offset
delay and f2(GHz).
1.
First, measure the actual LLINE by measuring the physical length of the
transmission lines on the LINE and THRU boards and subtracting the lengths.
Measurements were performed using a Mitutoyo digital caliper.
lengthLINE ( physical ) = 10.014cm
lengthTHRU ( physical ) = 7.580cm
474
LLINE ( physical )
= lengthLINE − lengthTHRU
= 10.014cm − 7.580cm = 2.434cm
2.
Convert LLINE ( physical ) into electrical length in degrees using LineCalc
l LINE (deg) = 79.4964 o
3.
Recompute the electrical length in cm
l LINE (cm) =
4.
Keeping f1(GHz) the same as previous, recomputed f2(GHz)
f 2 (GHz ) =
5.
l LINE (deg)
79.4964 o
⋅ λo (cm) =
⋅14.9895cm = 3.31cm
360 deg
360 o
15
15
− f1 (GHz ) =
− 0.1(GHz ) = 4.431679(GHz )
l LINE (cm)
3.31cm
Finally, recompute the offset delay using the new l LINE (cm)
offset delay =
6.
l LINE (cm)
3.31(cm)
=
= 110.4106 ps
cm
10 cm
c( )
2.9979 × 10 ( )
s
s
Update the calibration kit parameters with the new calculations (Table C-4)
Table C-4
Final TRL calibration parameters
Parameter
Value
2.434
LLINE (cm)
l LINE (deg)
79.4964
l LINE (cm)
offset delay ( ps )
f 2 (GHz )
3.31
110.4106
4.431679
475
C.4. Large-Signal High-Power Harmonic Measurement System
This is a description of a fully automated, high power single- and two-tone active
device/circuit 50 ohm measurement setup. The setup measures high power transistor
input reflected and output power for the fundamental and higher-order harmonics, DC
voltages and currents over various sweep parameter ranges including: DC gate bias, DC
drain bias, RF incident power and frequency. It can also measure static IV characteristics
under 50 ohm RF terminations. The device under test (DUT) can be any FET or HEMT
transistor with or without matching networks.
Numerous versions of the high-power harmonic measurement system have been
employed over the course of this work. These versions follow the same principles as the
final version, but may consist of different power driving components. The final version
is described next.
The measurement setup has the following features:
1. Computer controlled via GPIB to a Windows PC using Agilent VEE Pro. With
the exception of the driving TWTA, all the instruments and settings are controlled
and accessible through the automated program.
2. Remote control and data access from any location (such as home) using Windows
Remote Desktop Connection. This is especially advantageous for time
consuming runs.
3. Harmonic power data and DC data is automatically stored in Excel
4. Configurable gate (-10V to +10V) and drain (0V to 60V) supplies
5. Incident power generation up to 10W RF with excellent harmonic suppression
6. Input port reflected power measurement up to a user-defined number of
harmonics
7. Output port power measurement up to a user-defined number of harmonics
8. DC gate voltage measurement (for feedback into VEE Pro and to monitor DC
gate voltage shifts)
9. DC drain voltage measurement (for feedback into VEE Pro)
10. DC drain current measurement
476
50
ohm
Single-tone test setup
Fig. C-11
Single-tone high power harmonic test setup.
A schematic and photograph of the single-tone measurement setup is shown in Fig.
C-11 and Fig. C-12, respectively. The signal flow is described next. The HP 83752B
generator provides the single tone signal which is amplified by the Hughes 8020H
TWTA. The output of the TWTA containing high-power fundamental and harmonics is
passed through the Innowave isolator 0960-638-1 and the higher order harmonics are
filtered by the HP8431A BPF. These higher-order harmonics reflected by the BPF are
absorbed by the preceding isolator to prevent damage to the TWTA output.
The
distortion-free fundamental then passes through the Innowave 1041 isolator through a
477
high directivity coupler, then through Aeroflex bias T No. 1 and drives the gate of the
input port of the DUT.
Fig. C-12
Photo of single-tone high power harmonic test setup.
This power wave incident on the DUT is Pavs. Mismatches at the DUT input will
cause significant power reflection resulting in a wave traveling away from the DUT input
(Prefl). Also, due to nonlinearities at the device input, this Prefl will have measurable
higher-order harmonic content.
The reflected Prefl passes back through the high-
directivity coupler and is absorbed by the Innowave 1041 isolator. The coupler samples
Prefl which is measured by Spectrum Analyzer 1 for a user-defined number of harmonics
(PSAin). The DUT also amplifies the incoming signal to produce an output power wave
(Pout), which also consists of higher order harmonics. The high power Pout energy
passes through Aeroflex bias T No. 2, is attenuated through the PE7018-20 20dB pad and
478
measured using Spectrum Analyzer 2 over a user-defined number of harmonics
(PSAout). The values of Prefl and Pout can be computed using PSAin, PSAout, Grefl
and Gout at the harmonic frequencies of interest.
The DC gate bias is provided by the function generator (HP 3314A) configured to
output only DC values. The function generator has a 50 ohm DC gate resistance which
allows for DC gate bias shifts under large RF drive. One of the Tek DM5120 voltmeters
measures the actual DC gate voltage and keeps track of these shifts under different
incident RF power levels. The DC drain bias is provided by the HP6034A system power
supply. This supply can provide up to 60V, or 10A (up to 200W) of DC power and is
connected to the DUT through the Agilent 334411A ammeter and fed through Aeroflex
Bias T No. 2. The Agilent 334411A measures the DC drain current and another Tek
DM5120 measures the actual DC drain voltage.
Two-tone test setup
An alternate configuration of this setup for high power two-tone intermodulation
measurement has also been designed. For the two-tone configuration, the connection
point A labeled at the input of the 20dB pad in Fig. C-11 is disconnected and replaced
with the source generation setup in shown Fig. C-13. Isolators are used to prevent
damage to the output ports of the synthesizers.
intermodulation products can be measured automatically.
A user-defined number of
479
Fig. C-13
Two-tone source generation.
Calibration
Calibration is performed manually, with specific configurations to measure the
attenuation of the reflected signal path (Grefl) and the attenuation of the output signal
path (Gout). An additional calibration step using a THRU in place of the DUT is
performed to measure Pavs. The configuration shown in Fig. C-11 is set up for S-band
inputs but can be modified for different bands.
480
APPENDIX D. ADS SCHEMATICS OF MODELS
All computer simulations of the device models and circuits are performed in the
Agilent Advanced Design System (ADS) software package.
Partial screen model
schematics for the SiC MESFET and GaN HEMT are shown in Fig. D-1 and Fig. D-2,
respectively.
C
Cpf
C=Cpf
L
Lg
L=Lg
R=
Port
P1
Num=1
R
Rg
R=Rg
R
Rgd
R=Rgd
C
Cds
C=Cds
L
Ld
L=Ld
R=
R
Rd
R=Rd
Port
P2
Num=2
model_thermal
X12
C
Cpg
C=Cpx
v gs_int_p
C
Cpd
C=Cpx
v ds _int_p
vgs _int_n
R
Rgs
R=Rgs
TdeltaK_Ipk
Vds mp
Vds mn
TdeltaK_P1
TdeltaK_P3
model_thermal
X8
model_thermal
X5
TdeltaK_P4
model_thermal
X9
Pdiss
R
R11
R=1
model_thermal
X6
SDD14P
SDD4P1
I[1,0]=Igs
I[14,0]=alphaB*alphaR*(Vds m-Vds m_avg)
I[1,1]=Qgs
C[1]=
I[2,0]=Ids
Cport[1]=
I[3,0]=Igd
Vds m_av g
I[3,1]=Qgd
Vgs _offset
I[4,0]=Pdiss *Rth*K_Ipk
I[5,0]=1 pA
I[6,0]=1 pA
I[7,0]=Pdiss *Rth*K_P1
model_thermal
I[8,0]=Pdiss *Rth*K_P3
X7
I[9,0]=Pdiss *Rth*K_P4
I[10,0]=alphaB1*Vds m_av g+alphaB0
model_thermal
I[11,0]=Pdis s x
X11
R
I[12,0]=1fA
R10
I[13,0]=Vdsi
R=1
vds _int_n
Va r
Eq n
VAR
Port_Voltage_Definitions
Vgs i=_v1
Vds i=_v2
Vgdi=_v3
KTdelta_Ipk =_v4
Vgs m=_v 5
Vds m=_v 6
KTdelta_P1=_v 7
KTdelta_P3=_v 8
KTdelta_P4=_v 9
alphaB=-_v 10
Pdis s =-_v 11
KTdelta_Cgd0=_v 12
Vds m_av g=-_v13
Vgs _offs et=-_v 14
R
Rs
R=Rs
L
Ls
L=Ls
R=
Port
P3
Num=3
Fig. D-1
SiC MESFET ADS schematic.
481
C
Cpf
R
C=Cpf
R12
R=100 k Ohm
L
Lg
L=Lg
R=
Port
P1
Num=1
R
Rg
R=Rg
R
Rgd
R=Rgd
C
Cds
C=Cds p
R
Rg1
R=1e6 Ohm
L
Ld
L=Ld
R=
R
R
Rd
Rg4
R=Rd
R=1e6 Ohm
Port
P2
Num=2
model_thermal_3_unnorm
X12
R
Rg2
R=1e6 Ohm
C
Cpg
C=Cpx
v gs _int_p
C
Cpd
C=Cpx
v ds _int_p
v gs _int_n
R
Rgs
R=Rgs
TdeltaK_Ipk
TdeltaK_P1
TdeltaK_P2
TdeltaK_P3
alphaA
model_thermal_3_unnorm
X19
Vgs i_av g
alphaB
TdeltaK_M
Vds i_av g
model_thermal_3_unnorm
X20
MIpk
model_thermal_3_unnorm
X8
Vgsoffs et
model_averager model_av erager
R
X9
X10
R11
R=1
SDD14P
SDD4P1
I[1,0]=Igs
I[1,1]=Qgs
I[2,0]=Ids
I[2,1]=Qds
I[3,0]=Igd
I[3,1]=Qgd
I[4,0]=Pdis s *Rth*K_Ipk
I[5,0]=Pdis s *Rth*K_P1
I[6,0]=Pdis s *Rth*K_P2
I[7,0]=Pdis s *Rth*K_P3
I[8,0]=Pdis s *Rth*K_M
I[9,0]=alphaA_eq
I[10,0]=Vgs i
I[11,0]=alphaB_eq
I[12,0]=Vds i
I[13,0]=Vgs _offs et_eq
I[14,0]=M_Ipk
C[1]=
Cport[1]=
R
R10
R=1
model_thermal_3_unnorm
X5
model_averager
model_av erager
X21
X6
v ds _int_n
Va r
Eq n
VAR
Port_Voltage_Definitions
Vgs i=_v 1
Vds i=_v 2
Vgdi=_v 3
KTdelta_Ipk =_v 4
KTdelta_P1=_v 5
KTdelta_P2=_v 6
KTdelta_P3=_v 7
KTdelta_M=_v 8
alphaA=-_v 9
Vgs i_av g=-_v 10
alphaB=-_v 11
Vds i_av g=-_v 12
Vgs offs et=-_v 13
MIpk =-_v14
R
Rs
R=Rs
L
Ls
L=Ls
R=
Port
P3
Num=3
Fig. D-2
GaN HEMT ADS schematic.
R
Rg3
R=1e6 Ohm
482
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