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High speed, high power gallium indium phosphide/gallium arsenide HBTs and their application to microwave monolithic integrated circuits (MMICs)

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HIGH SPE E D , HIGH POWER G a ln P /G a A s HBTS
AND THEIR APPLICATION TO MICROWAVE
MONOLITHIC INTEGRATED CIRCUITS (MMICS)
*>y
Jae-YVoo P a rk
A dissertation subm itted in partial fulfillment
o f the requirements for the degree o f
D octor o f Philosophy
(Electrical Engineering)
in The University o f M ichigan
2000
Doctoral Com m ittee:
Professor Dimitris Pavlidis, C hair
Professor Pal lab Bhattacharya
Research Scientist Jack East
Professor Joanna M irecki-M illunchick
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UMI N um ber 9963865
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UMI Microform9963865
Copyright 2000 by Bell & Howell Information and Learning Company.
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^
Jae-W oo Park
All Rights Reserved
© ___________________ 2000
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To my lovely family,
M ee-W ha, Jeong-H eum and Se-H eum
ii
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ACKLOWLEDGMENTS
I wish to thank my supervisor, Professor D. Pavlidis, for his guidance, encouragem ent
and introducing a wonderful w orld o f the microwave solid-state engineering throughout
this study. I also w ould like to thank the m embers o f my Ph. D dissertation com m ittee for
reviewing this manuscript. I w ould to like to express my thanks to Dr. Jean-Charles Garcia
and Dr. Jean-Luc Guyaux from Thom son-C SF and Dr. K arim S. Boutros from H ughes
Spectrolab for providing high-quality epitaxial layers for this work. Especially, I would
like to thank m y research partners, Dr. S. M ohamm adi, Dr. P. M arsh, Dr. J. O. Plouchart
for their useful discussions and com m ents. I personally thank to Prof. E. Leith for his
encouragem ent, kindness while I studied the course works in the University o f M ichigan. I
would also like to express my thanks to H yungsoo Kim, Jae-Youn K im and Hee-Seok Lee
w ho through a conscientious effort at w ord-processing skill, proof-reading.
The support provided by Thom son-C SF (Contract No. 94 6 M 917) and M U RI (Con­
tract No. D A A H 04-96-1-0001) during the course o f my research is highly appreciated.
Finally, I w ould like to thank m y wife, M ee-W ha Park and my tw o lovely and healthy
sons, Jam es (Jeong-Heum), Steve (Se-H eum ) for their endless support and encourage­
ment. W ithout my w ife’s deep understanding and support, this thesis w ould not have com ­
pleted.
I will not forget the beautiful m illions o f stars o f the evening sky in A nn A rbor when­
ever I com e back m y hom e from the school.
Finished ju st one day before 2000
ill
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TABLE OF CONTENTS
D E D IC A T IO N .........................................................................................................................
ii
A C K O W L E D G E M E N T .........................................................................................................
iii
L IS T O F F I G U R E S .............................................................................................................
vii
L IS T O F T A B L E S ...............................................................................................................
xvi
CH APTER
I. IN T R O D U C T IO N .............................................................................................
1.1
1.2
1.3
1.4
B rief O verview o f H B T s ...................................................................
Basic O peration o f H B T s ...................................................................
W hy G alnP/G aA s HBTs over AlG aA s/GaA s H B T s ...................
O bjective and Scope o f This T h e s is .................................................
II. G a ln P /G a A s H B T AND M M IC F A B R IC A T IO N T E C H N O L O G Y
2.1 O ptim ization o f ohmic contacts for base and
em itter contact la y e r s ........................................................................
2.2 O ptim ization o f passive com ponent technology for I C s
2.3 Selective W et Etching Technology for G alnP/G aA s HBTs . . .
2.4 Self-A ligned G alnP/G aA s HBT and M M IC Process Technology
2.5 L aterally Etched Undercut vs. Conventional T e c h n o lo g y
2.5.1 M aterial growth and Device stru ctu re.................................
2.5.2 B rief LEU Technology and D evice P erfo rm an ce
2.6 S u m m a ry ...............................................................................................
III. F U N D A M E N T A L A N A LY SIS O F G a ln P /G a A s H B T S ...................
3.1
3.2
3.3
3.4
1
1
3
6
9
13
14
18
20
23
28
32
33
39
40
A brupt Junction vs. G raded J u n c tio n ..............................................
D C C urrent Gain (P) and cutoff Frequency ( f f ) ............................
Im pact o f E m itter Size on M icrow ave Perform ance.....................
D iscussion and Conclusions on Basic HBT T re n d s .....................
40
46
51
58
TV. D E S IG N A N D A N A LY SIS O F H IG H S P E E D G a ln P /G a A s H B T S
60
4.1 T unneling Em itter Design o f G alnP/G aA s H B T s .....................
4.1.1 Introduction.................................................................................
4.1.2 M otivation...................................................................................
60
60
61
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4.1.3 D esign Considerations o f Tunneling Em itter
G alnP/G aA s H B T s ...................................................................
4.1.4 L ayer Structure and D evice F abrication..............................
4 .1.5 DC and M icrow ave P erfo rm an ce..........................................
4.1.6 Sm all Signal Param eter Extraction o f
the Tunneling Em itter H B T s .................................................
4.2 Com posite Em itter D esign o f G alnP/G aA s H B T s .......................
4.2.1 Introduction and Basic operation C onsideration
4.2.2 M onte Carlo study o f the com posite em itter design
4.2.3 Layer Structure and D evice F abrication..............................
4.2.4 DC and M icrow ave P erfo rm an ce..........................................
4.2.5 D evice Analysis and D iscussion............................................
4.3 Im proved High Speed o f G alnP/G aA s D H B T s ............................
4.3.1 Introduction.................................................................................
4.3.2 Layer Structure and D evice Analysis ................................
4.3.3 R esults and D iscu ssio n s..........................................................
4.4 Sum m ary ...............................................................................................
63
6 6
6 8
72
77
77
79
84
8 6
90
96
96
98
102
108
V. IM P A C T O F N i/G e/A u/T i/A u AND T i/P t/A u C O L L E C T O R M E T A L
O N G a ln P /G a A s H B T C H A R A C T E R IS T IC S .......................................
1
10
5.1 Introduction............................................................................................
5.2 D evice Processing and C h aracteristics............................................
5.3 M odel for the C ollector-Em itter Offset Voltage (Voffset)
5.4. DC C haracteristics............................................................................
5.5 RF Characteristics ...............................................................................
5.6 Pow er C haracteristics..........................................................................
5.7 S u m m ary .................................................................................................
110
Ill
113
114
118
121
123
V I. P A S S IV A T IO N AND R E L IA B IL IT Y ISSU ES O F
G a ln P /G a A s H B T S ........................................................................................
124
6.1
6.2
6.3
6.4
Passivation o f G alnP/G aA s H B T s............................................
124
Characterization o f Passivation layer in G alnP/G aA s HBTs . .
126
Reliability Issues o f H B T s..........................................................
132
Reliability T est o f G alnP/G aA s H B T s ...................................
133
6.4.1 Reliability Tests o f U npassivated G alnP/G aA s HBTs . .
133
6.4.2 Reliability Tests o f Passivated G alnP/G aA s H B T ..........
134
6.4.3 Evaluation o f M ean-Tim e-To-Failure (M TTF) for
the Passivated G alnP/G aA s H B T .................................
137
6.5 Sum m ary and D iscussion on Reliability o f G alnP H B T s
141
V II. B R O A D B A N D A N D H IG H G A IN T R A N S IM P E D A N C E
A M P L IF IE R S .................................................................................................
7.1 In tro d u ctio n ..................................................................................
7.2. B rief M M IC T echnology..........................................................
7.3 B roadband Transim pedance A m plifier 1
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143
143
145
- C om m on-E m itter (CE) and C ascode S tag e .................................
7.3.1 Design and Experim ental Results o f the Transim pedance
A m p lifiers....................................................................................
7.3.2 Large Signal Perform ance and Analysis o f the
T ransim pedance A m p lifie rs...................................................
7.4 Broadband T ransim pedance A m plifier 2
-D istributed A m plifiers......................................................................
7.4.1 D esign Consideration o f the G alnP/G aA s D istributed
A m p lifiers....................................................................................
7.4.2 Experim ental R esults o f D istributed A m plifier................
7.5 High-Gain T ransim pedance A m plifier
- M ulti-Feedback D e sig n ...................................................................
7.5.1 Design Consideration o f the High-gain Transim pedance
A m p lifie r....................................................................................
7.5.2 Experim ental R esults o f the Multi Feedback
T ransim pedance A m p lifier.....................................................
7.6 S u m m a ry ...............................................................................................
171
176
V III. A N A L Y SIS A N D C H A R A C T E R IZ A T IO N O F
H IG H P O W E R G a ln P /G a A s H B T S ......................................................
179
8.1 Introduction.............................................................................................
8.2 Pow er M easurem ents using O n-W afer Load-Pull System . . . .
8.3 High Pow er D ensity o f Self-aligned G alnP/G aA s HBTs .........
8.3.1 m otivation .................................................................................
8.3.2 L ayer Structure and D evice P e rfo rm a n c e ..........................
8.3.3 DC and RF c h a ra c te ristic s .....................................................
8.3.4 H BT Large-Signal M odeling and A n a ly s is .......................
8.3.5 H BT Pow er M easurem ents and Analysis ..........................
8.4 S u m m ary..................................................................................................
179
181
183
183
185
187
187
194
199
IX. C O N C L U S IO N S A N D F U T U R E W O R K ...............................................
201
9.1 C onclusions ...........................................................................................
9.2 Future W o r k ...........................................................................................
201
205
A P P E N D IX ..............................................................................................................................
B IB L IO G R A P H Y ..................................................................................................................
210
212
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146
147
152
158
161
166
170
171
LIST OF FIGURES
Figure
1.1.
1.2.
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
The energy band diagram o f an n-p-n heterojunction bipolar transistor
(H BT) with a w ide bandgap em itter, (a) at equilibrium state, AEV blocks
minority carrier diffusion from the base to the emitter, (b) under bias,
DEC helps to inject hot electrons for thermionic em ission
transport..................................................................................................................
4
State-of-the-art o f high frequency performance (fT, fmax) for G alnP /
G aA s HBT discrete devices..............................................................................
9
The etched G aA s base surface m orphology by H C1: H 2 O (1:1) (a) and
pure HC1 (b). The surface m orphology (a) is not uniform and has no
form ation o f undercutting to obtain self-aligned profile............................
2 0
Etch profiles at different crystalline directions. Shapes produced using
N H 4 O H : H 2 O 2 : H 2 O for G aA s and pure HC1 for G alnP em itters on
(100) oriented G aA s substrate..........................................................................
21
SEM photograph o f a 2 x 30 p m 2 fabricated HBT and photograph o f
typical M M IC fabricated using self-aligned HBT technology, resistor
(N i/Cr) and capacitor (AI2 O 3 ) deposition......................................................
28
A cross sectional view o f the em itter and adjacent self-aligned base
contacts. The separation (0.1 ~ 0.2 pm ) between em itter m esa an d base
m etal was achieved by optim ization o f the etching procedure used for
the em itter orientation so that fingers are aligned along [011] direction.
29
T he schem atic device layout and the associated cross section o f typical
H BT device w ithout (a) an d with LEU technique and RC netw ork for
th e base-col lector ju n ctio n ................................................................................
30
Cross section SEM pictures o f the self-aligned G alnP/G aA s H B T
w ithout (a) and w ith (b) L E U technology......................................................
34
D C characteristics o f the self-aligned G alnP/G aA s H BT w ithout(a) and
vii
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w ith(b) LEU technology. N o im pact o f LEU technology as observed on
DC characteristics................................................................................................
35
M icrowave perform ance o f 2 x 30pm 2 single em itter HBT w ithout and
with LEU technology at VCE=2.5V, Ic =20mA. fT o f 5 1 , 58GHz and
fmax o f 8 0 , 100GHz were m easured for w ithout and with LEU
technology respectively......................................................................................
36
Energy band diagram for (a) an abrupt G alnP/G aA s heterojunction and
(b) a graded G alnP/G aA s heterojunction [25]..............................................
40
Forward-biased I-V characteristics from the ideal. There are three
regions: low current space charge recom bination region, medium
current region, high level injection regions...................................................
42
M easured G um m el plot (a) and DC current gain (b) for an abrupt E-B
G alnP/G aA s HBT. The device size is 50 x 50 p m 2 ....................................
44
M easured G um m el plot (a) and DC current gain (b) for a graded E-B
G alnP/G aA s H BT.The device size is 50 x 50 p m 2 .....................................
46
Comm on em itter current gain vs. frequency for high and low DC gain
H B Ts.......................................................................................................................
48
The measured cutoff frequencies for he G alnP/G aA s HBTs with low
and high D C current gains.................................................................................
49
3.7.
A sim plified transistor structure o f a stripe geom etry H B T.......................
51
3.8.
The measured cutoff frequencies ( f j) and m axim um frequencies of
oscillation (fmax) for various em itter geometries. 5 x 10 (a), 5 x 20 (b),
5 x 30 p m 2 (c) single em itter finger G alnP/G aA s H B Ts...........................
54
T he m easured cu to ff frequencies (fT) and m axim um frequencies of
oscillation (fmax) for various em itter geom etries. 2 x 20 (a), 2 x 30 p n r
(b) single em itter finger G alnP/G aA s H B Ts................................................
55
2.8.
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.9.
4.1.
Sim ulated energy-band diagram s for G alnP/G aA s tunneling em itter H BT s. 63
4.2.
Simulated electric field for G alnP/G aA s tunneling em itter H BTs
4.3.
I-V (a) and gumm el (b) characteristics o f the G alnP/G aA s tunneling
and conventional em itter H B Ts.......................................................................
4.4.
High frequency perform ance o f 2 x 30 p m 2 single em itter HBT at Iq=
22 mA, VCE= 2.5 V. (a) Tunneling em itter design H BT at VCE= 2.5V,
viii
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64
6 8
[<2 = 2 0 mA, (b) C onventional em itter design HBT at VCE= 2.5 V, Ic =
18 m A .....................................................................................................................
70
Bias dependence o f fT and fmax for 2x30pm 2 G alnP/G aA s HBTs. (a)
Tunneling em itter design H B T (b) Conventional em itter design HBT.
72
the relation betw een C BE and RBE on V BE for the tunneling and the
conventional em itter G alnP/G aA s HBTs.......................................................
74
the relation between C BE and R BE on Ic for the tunneling and the
conventional em itter G alnP/G aA s H BTs.......................................................
75
Energy band diagram s o f G alnP/G aA s conventional (a) and com posite
em itter design HBTs (b )....................................................................................
80
Com parison o f electric field (a) and electron density profiles (b) for
G alnP conventional and A lG aA s-G alnP com posite em itter design
H BTs.......................................................................................................................
81
Com parison o f electron velocity profiles for G alnP conventional and
AlGaAs G alnP em itter design HBTs in the com posite em itter region. .
82
Bias dependence o f free electron carrier density for the com posite (a)
and the conventional em itter design HBTs...................................................
84
SEM picture o f the fabricated 2 x 30pm 2 single em itter G alnP/G aA s
H BT........................................................................................................................
8 6
DC characteristics o f com posite em itter (a) and conventional em itter (b)
design H B Ts.........................................................................................................
87
M easured and sim ulated m icrowave performance o f com posite em itter
(a) and conventional em itter (b) design HBTs...........................................
8 8
Bias dependence o f m icrow ave performance o f com posite em itter (a)
and conventional em itter (b) design HBTs....................................................
90
Com parison o f delay tim e o f com posite em itter and conventional
em itter design H B Ts...........................................................................................
92
4.17.
Com parison o f C BE and fT characteristics with collector current
93
4.18.
CBE and R BE dependence on Ic for the com posite and the conventional
em itter G alnP/G aA s H BTs ............................................................................
94
Energy-band diagram s fo r D HBTs with G alnP (a) and G aA s (b) spacers.
99
4.5.
4.6.
4.7.
4.8.
4.9.
4.10.
4 .1 1 .
4.12.
4.13.
4.14.
4.15.
4.16.
4.19.
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4.20.
4.21.
The sim ulated DC gain with various spacers; no spacer, G aA s and
G alnP spacers......................................................................................................
Etching Profile o f G alnP/G aA s D HBTs along [0 1 1] and [010] directions. 102
4.22. I-V characteristics o f the G alnP/G aA s D H B T with doped G alnP spacers.
4.23. High frequency perform ance o f 5 x 4 0 p m 2 single em itter G alnP/G aA s
D H B T sa tV CE= 4 V , Ic = 51.5 m A .................................................................
4.24.
100
103
104
Bias dependence o f fT and fmax as a function o f collector current for the
G alnP/G aA s DHBT with doped G alnP spacer.............................................
104
I-V characteristics o f 2 x 30pm 2 self-aligned G alnP/G aA s HBTs with
Ni/Ge/Au/Ti/Au (H BT A) and T i/Pt/A u (H B T B)......................................
Ill
5.2.
The m odified Ebers-M oll diagram with the collector metal barrier. . . .
113
5.3.
E-B (a) and B-C (b) diode characteristics for different collector metals.
115
5.4.
Energy-band diagram for n-G aAs subcollector(n=5xl018cm -3) and
m etal(Ti)................................................................................................................
116
M icrow ave perform ance o f G alnP/G aA s HBTs with different collector
metals (VCE = 3.5V, I B = 120mA, Ic= 19.5mA for H BT A, VCE = 3.5 V,
IB = 120mA, Ic = 14.1mA for H BT B )...........................................................
118
Pin-Pout o f G alnP/G aA s HBTs w ith different collector metals. The
devices were biased for Class B (VCE=7V , VBE=0.77V ) operation at
8GHz.................................................................................................................
121
SEM pictures for the cross section o f passivated G alnP/G aA s HBTs
with PECVD S i0 2 ................................................................................................
126
Com parison of I c ^ C E characteristics and HBTs Gummel plots before
andafter passivation for 2 x 10 p m 2 single em itter......................................
127
T he schem atic diagram o f the four m ajor base currents in HBTs. After
HBTs passivated w ith PEC V D S i0 2, the increase o f the base current
results from mainly additional base surface recom bination through
interface between em itter periphery and S i0 2 passivation film
128
T he surface recom bination current as function o f the collector current
density before and after passivation. T he surface recom bination current
was slightly increased after passivation with PECV D S i0 2 .....................
129
5.1.
5.5.
5.6.
6
6
.1.
. 2.
6.3.
6.4.
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6.5.
6
M icrow ave perform ance o f the 2 x 10 p m 2 em itter H BT before and after
passivation with PECVD Si 0 2 - The m icrowave perform ance is almost
the same before and after passivation except in the low frequency region
(around 1GHz) which is dictated prim arily by DC gain characteristics.
..................................................................................................................................
130
Reliability tests o f unpassivated 2 x 30 p m 2 G alnP/G aA s HBTs. Its
current gain tested at 25 kA /cm 2 w as m onitored over 9 days and was
found to decrease by not m ore than 10%. Its gain tested at 40 kA /cm decreased after this initial period by 21% within 7 days...........................
133
Reliability tests for passivated 2 finger 5 x 10 p m 2 em itter HBTs
operated a current density o f 40 kA /cm 2. The passivated HBTs show
only 2% degradation o f D C current gain over a total period o f 30.5 days
despite the fact that they are subjected to such high current density. . .
135
Gummel plot (a) and current gain versus collector current (b) for the
passivated G alnP/G aA s HBTs before and after the reliability stress test.
..................................................................................................................................
136
The extracted thermal resistance (R th) using the calibrated temperature
as function o f DC dissipated pow er for 2 x 30 pm 2 G alnP/G aA s HBTs.
The calculated Rth is 1430 K/W which is close to reported values for
this type o f technology [82]..............................................................................
139
.10. A rrhenius plot o f M TTF for devices subjected to various am bient
temperature. Bias stresses are VCE = 3.0 V, Jc= 33.3 kA /cm - for this
w ork (2 x 30 p m 2 single em itter G alnP/G aA s HBTs), VCE = 2.5 V, Jc =
60 kA /cm 2 for Fujitsu and A lG aA s/GaA s H BTs (2 x 10 p m 2 single
em itter geom etry)................................................................................................
140
.6 .
6.7.
6
.8 .
6.9.
6
7.1.
7.2.
7.3.
7.4.
Schem atic o f the G alnP/G aA s H BT transim pedance am plifiers; (a):
Design A (com m on-em itter based), (b): Design B (Cascode based). . .
148
Photograph o f the fabricated transim pedance am plifiers; (a): Design A
(com m on-em itter based), (b): D esign B (Cascode based)......................
149
Transm ission coefficient S21 and transim pedance gain of the com monem itter transim pedance am plifier [design A] (a) and the Cascode
transim pedance am plifier [design B] (b) m easured by on-w afer probing.
..................................................................................................................................
150
M easured Pout-Pin characteristics o f design A [comm on-emitter] (a)
and design B [Cascode] (b) transim pedance am plifiers. The com monem itter based transim pedance am plifier shows a more pronounced gain
com pression especially at low er frequencies. The C ascode based
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7.5.
7.6.
transim pedance circuit, however, shows very small gain com pression at
high input power. This is mainly due to the fact that self-biasing effects
resulting from the presence o f large signal input conditions are reduced
in this design........................................................................................................
152
The circuit schematics o f the C ascode transim pedance am plifier (design
B) using the HBT T-equivalent circuit, (b) DC com ponent o f the output
voltage is plotted vs. the am plitude o f the sinusoidal input voltage. . . .
154
Sim ulated fundamental and higher harm onic com ponents of output
pow er as function o f input pow er for design A (com m on-em itter based)
and design B (Cascode based) at 5 G H z fundamental frequency. The
output pow er lost in harmonics is much higher in the case o f design A
at pow er levels beyond -12 dBm where the device behaves in strongly
non-linear fashion................................................................................................
157
7.7.
T he current state-of the art for the gain-bandwidth performance of the
distributed amplifiers with G aA s and InP based HBTs. Gain-bandwidth
product o f 118 G Hz by U o f M ichigan is am ong the highest value
reported for the distributed am plifiers with G aA s and InP based HBTs.
................................................................................................................................................ 158
7.8.
Circuit schematic o f the 3-stage distributed am plifier fabricated with
G alnP/ G aA s HBTs using com m on-collector stage followed by Cascode
active cell..............................................................................................................
161
Photograph o f the 3-stage distributed am plifier fabricated with self­
aligned G alnP/G aA s HBTs. The chip size is 1200 x 1125 pm 2
164
7.9.
7.10. Sim ulated and measured S-Param eters o f the 3-stage distributed
amplifier. A S21 gain o f 12.7 dB over a bandwidth o f 27.5 GHz was
measured. This corresponds to a 118 G H z G ain-Bandwidth product,
which is am ong the highest reported values for H BT-based distributed
am plifiers..............................................................................................................
164
7.11. M easured S-Parameters o f the 3-stage distributed am plifier at low
frequency region (50 M Hz ~ 3 GHz). The gain flatness extends to low
frequency region..................................................................................................
167
7.12. M easured output eye-diagram o f the 3-stage distributed am plifier at 10
G b/sec 22 1 - 1 NRZ PRBS........................................................................... 167
7.13. B it-error rate o f the 3-stage distributed am plifier as function o f average
incident pow er measured at 10 G b/sec N RZ PRBS. The 27- l word
length showed a sensitivity o f -33 dBm at 10-9 bit-error-rate while the
2 15-1 word length had a low er sensitivity o f -25 dB m ...............................
xii
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168
7.14.
Schem atic o f the multi-feedback transim pedance am plifier fabricated
with G alnP/G aA s HBTs. Novel circuit approach allow s very good
stability(due to T5, T 6 com bination) as well as high gain and
bandw idth(T 1, T3, T 6 gain stages, T2, T4 feedback stages)....................
171
Photograph o f the fabricated m ulti-feedback transim pedance amplifier.
T he chip size is 1125 x 800 p m 2 ......................................................................
171
M easured S-Param eters o f the m ulti-feedback transim pedance
am plifier. S21 o f 18.8 dB with a 13.5 GHz bandwidth was measured.
T he gain-bandwidth product o f the am plifier calculated to be 118 G Hz
and is the highest reported figure for G alnP/G aA s HBT technology. . .
173
Effective transim pedance gain (52 dB£2 over a bandwidth o f 13.5 GHz)
o f the m ulti-feedback am plifier calculated from small-signal Sparam eter m easurem ent.....................................................................................
173
M easured eye-diagram o f the m ulti-feedback transim pedance am plifier
at 10 G b/sec 2 1 5 - 1 NRZ PR B S......................................................................
174
B it-error-rate o f the m ulti-feedback am plifier as a function o f average
incident pow er m easured at 10 G b/sec NRZ PRBS. The 27- l w ord
length showed a sensitivity o f -19 dBm at 10-7 bit-error rate while the
2 15-1 w ord length had a lower sensitivity o f -11 dB m ...............................
174
A utom ated on-w afer Load-Pull system setup for power m easurem ent of
H B T s......................................................................................................................
181
The current-state-of-art of pow er density and pow er-added-efficiency
(PAE) for G alnP/G aA s HBTs at X band measurement. The pow er
density by U o f Michigan show s the highest value am ong the published
values o f pow er density for G alnP/G aA s H B Ts..........................................
183
8.3.
SEM photograph o f 10 finger 2 x 20 p m 2 G alnP/G aA s H B T.................
187
8.4.
C om m on-em itter I-V characteristics o f 10 finger 2 x 20 p m 2 G alnP/
G aA s H B T.............................................................................................................
187
7.15.
7.16.
7.17.
7.18.
7.19.
8
.1.
8.2.
8.5.
8
.6 .
Sim plified analytical large signal H B T equivalent circuit m odel
T he sim ulated output pow er and associated gain perform ance as
functions o f device resistances and capacitances (RE, Rc , Cgc> C BE)
under class B operation (VBE = 0.74 V, VCE = 10 V) using the analytical
m odel and LIBRA large-signal H B T m odel.................................................
8.7. M easured and sim ulated pow er perform ance o f 1 finger 2 x 30 pm " G alnP/
xiii
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188
190
G aA s HBTs at VCE=10V, V BE=0.74V and X -band...................................
192
Dynamic load pull sim ulation from the m easured and extracted 1 finger
2 x 30 pm 2 G alnP/G aA s HBTs large signal param eters...........................
193
M easured C W output pow er and PAE as a function o f input pow er for
10 finger 2 x 20 p m 2 G alnP/G aA s H BTs at 8 G Hz. The measurements
were perform ed under different collector bias conditions (VCE= 8 ,10V ).
.................................................................................................................................
194
M easured CW output pow er and PAE as a function o f input pow er for 1
finger 2 x 30 p m 2 G alnP/G aA s HBTs at X-band. The measurements
were perform ed under different collector bias conditions (VCE= 8 , 10,
12V) with a constant V B E (0.74V ).................................................................
195
The measured Pout, Power G ain and current gain as function o f Pin for
10 finger 2 x 20 p m 2 G alnP/G aA s HBTs on HBT1 and HBT2 layer
structures...............................................................................................................
197
9.1.
Schematic cross section o f the collector-up H B T .......................................
205
9.2.
The etching profile of the G alnP/G aA s collector-up H B T.......................
206
8.8.
8.9.
8 . 10.
8 . 11 .
xiv
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LIST OF TABLES
Table
1.1.
Typical material properties for G alnP/G aA s and A lG aA s/GaA s
herterojunction system s......................................................................................
7
Ohmic contact study o f different metallization for p+ G aA s base layer.
Pt/Ti/Pt/Au was found to perform best due to low potential barrier
height metal to p-type sem iconductors...........................................................
15
Ohmic contact study for p+ GaAs base layer. A fter 410°C, 40sec RTA
treatm ent, the base contact resistance is degraded......................................
16
Ohmic study o f different metallization for n+ G aA s Layer. In/Ni/Au
gives the low est contact resistance but the surface m orphology this
metallization is not good and obviously not as reliable as a non-diffusing
metallization such as Ti/Pt/A u..........................................................................
17
Capacitor study for M M IC lumped elem ent. T hinner evaporated
dielectric material has m ore possibility o f pin-holes so that results in the
short-circuit with bottom metal plate. Thus A I 2 O 3 (3800A) was chosen
in this w ork............................................................................................................
18
Etching rate, undercut rate and selectivity for G aA s and G alnP em itter
fingers oriented along [O il] direction.............................................................
22
2.6.
The brief process em ployed for G alnP/G aA s H BT fabrication [ 2 2 ] ....
27
2.7.
The layer structure for the fabricated G alnP/G aA s H BTs. This H BT
structure was optim ized for high frequency perform ance.........................
32
2.1.
2.2.
2.3.
2.4.
2.5.
2.8.
Small Signal HBT Equivalent Circuit Param eters w ithout and with LEU
Technology. The H BT small-signal equivalent circuit param eters were
directly extracted from m easured S-param eter data using an in-house
analytical extraction technique. C g c ° f LE U technology is reduced by
xv
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3.1.
4 .1 .
4.2.
4.3.
4.4.
21.8% and leads to 25% im provem ent o f f , ^ .............................................
37
The relation between em itter geom etry and m easured microwave
performance with DC measurem ent data.......................................................
53
Comparison o f DC gain between G alnP tunneling em itter design and the
conventional HBTs..............................................................................................
69
Equivalent circuit param eters for 2x30 p m 2 single em itter HBT
between Tunneling em itter and Conventional design H BTs....................
73
Layer structure o f G alnP/G aA s DHBTs with 100A highly doped G alnP
spacer layer...........................................................................................................
97
Equivalent circuit param eters for 5x40pm 2 single em itter G alnP/GaAs
D HBTs with 100A highly doped G alnP spacer layer and SHBTs of
sim ilar design. Both devices were biased for best fT, fmax performance.
106
5.1.
8
.1.
8.2.
9.1.
Equivalent circuit param eters for 2x30 p m 2 single em itter HBT between
H BT A with Ni/Ge/Au/Ti/Au and HBT B with Ti/Pt/Au
collector m etal......................................................................................................
119
Layer structure o f G alnP/G aA s HBTs with different pow er
perform ance..........................................................................................................
184
Extracted large-signal param eters for tw o different H BTs with lOfinger
2 x20pm 2 as shown in Table 8.3.....................................................................
198
The layer structure o f ultra-high speed G alnP/G aA s H B Ts.......................
207
xvi
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CHAPTER I
INTRODUCTION
1.1 Brief Overview of HBTs
The first concept o f Heterojunction Bipolar Transistors (H B Ts) dates back to 1951
when the bipolar transistor was invented by W illiam Schockley [1]. This concept was fur­
ther developed by H. K roem er who introduced first HBTs with a w ide bandgap em itter in
1957 [2]. The realization o f the first H BT was not possible until 1970’s because the m ate­
rial growth and fabrication technology were immature. HBTs are currently key devices for
high speed and high pow er applications. Following the advancem ent in material growth
techniques such m olecular beam epitaxy (M BE) [3] and M etal-O rganic Chemical Vapor
Epitaxy (M O CV D ) [4], the atom ic level growth o f A lG aA s/G aA s heterostructures was
dem onstrated. H B T technology has then quickly evolved and led in ultra high speed per­
form ance w ith f r o f 250 G H z [5] and extrem ely high pow er density o f 5.4 W /m m [6 ]. The
lattice m atched A lG aA s/G aA s and InA lA s/InG aA s/InP have been the most com m on
material system s for H B T applications for wireless and optical com m unication system s.
Recently, G alnP/G aA s H B Ts have becom e the focus o f intense activity as alternatives to
A lG aA s/G aA s H BTs due to their attractive features (see C hapter 1.3 for further details)
1
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2
[7]. Thus, m -V HBTs have been dem onstrated to be superior to Si B ipolar Junction Tran­
sistors (BJTs) for high speed and high pow er applications. T he prim ary advantages o f n iV H BTs over Si bipolar transistors are sum m arized as following [8 ]: (1) T he possibility o f
bandgap engineering allows unique structures such as w ide bandgap em itter (SHBT),
w ide bandgap collector (D H B T) and graded base HBTs. (2) Due to the wide bandgap
em itter, H BTs allow a much higher base doping concentration (up to ~10 2 0 cm"3) and
result in im proved m axim um oscillation frequency, f ^ . (3) High em itter efficiency can
be achieved since m inority carriers flowing from the base to em itter are blocked by the
higher barrier o f the valence band discontinuity (AEV). (4) The features o f high electron
m obility (GaAs: 8500 cm 2 /V.s, InP : 4600 cm 2 /V.s vs. Si: 1500 cm 2 /V.s at 300 K), and
velocity overshoot result in reduced total transit time ( tt ). (5) Much higher Early voltage
is possible due to high base doping. (6 ) The availability o f sem i-insulating substrate can
decrease the substrate-related parasitic capacitance and allows convenient integration of
the devices. (7) The availability o f selective etchants allows to reach the device layers with
precise control.
From the mid 1980’s, high electron mobility transistors (HEM Ts) are one o f leading
devices for microwave applications because o f their high speed, high frequency and supe­
rior low noise perform ance. C urrent wireless and optical com munication system s require
better pow er handling capability and higher breakdown voltages. These requirem ents can
be best satisfied by em ploying HBTs rather than M ESFETs and HEM Ts. The H BTs offer
a num ber o f attractive features over M ESFETs and H EM Ts as following: (1) Com pared
w ith M ESFETs, the vertical epitaxial structure allows the critical dim ensions to be defined
w ith great precision by m odem grow th techniques. (2) T he key distances that govern elec­
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3
tron transit time are determ ined by epitaxial growth, and not by lithography allowing
therefore good high frequency perform ance with m odest processing requirem ents. (3)
Breakdow n voltage and tum -on voltage are also dependent on epitaxial technology and
can therefore be well controlled. (4) T he devices are well shielded from traps in the bulk
and surface regions, and present therefore low 1/f noise. (5) T he entire em itter area con­
ducts current, leading to high current handling capability and high transconductance.
C ircuit applications o f HBTs are essentially the sam e as those o f Si bipolar transistors,
the m ajor difference being the higher frequency operation o f the former. M icrowave appli­
cations o f HBTs include high efficiency and high linearity m icrowave and millimeterwave pow er amplifiers, oscillators and mixers. Digital applications o f H B Ts include com ­
ponents for high speed switching w ith low phase noise such as phase-locked loops and
direct digital frequency synthesizers. In addition, HBTs are being exploited for high per­
form ance analog circuits such as operational amplifiers.
1.2 Basic Operation of HBTs
T he energy band diagram o f an n-p-n heterojunction bipolar transistor (HBT) with a
wide bandgap em itter is shown in Fig. 1.1. HBTs resem ble a conventional bipolar transis­
tors m ade out o f homojunction em itter and base layers. However, they present a few
im portant differences such as highly doped base region that leads to im proved high fre­
quency perform ance and large AEV w hich leads to reduction o f the base current (Igp) from
base to em itter region. The overall current gain O bjt ) >s therefore im proved as follows;
$hbt
-
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( 1. 1)
4
Em itter
Base
Collector
AE
Ev
Em itter
Base
Collector
(b)
Fig. 1.1: T he energy b and diagram o f an n-p-n heterojunction bipolar transistor (HBT)
w ith a w ide bandgap emitter, (a) at equilibrium state, AEV blocks minority
carrier diffusion from the base to the emitter, (b) under bias, AEc helps to
inject hot electrons for therm ionic em ission transport.
Each term inal current can be decom posed to the following current com ponents:
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5
Em itter c u rre n t: l E - /„ + l B p + I B, SCr
( 1.2)
Base c u rre n t: l B = I BtP + I Bt bulk + I B>scr
(1.3)
C ollector c u rre n t: l c = l E - I B = I n - 1 B, bulk
(1.4)
where /„ is the electron injection current, l B p is the hole injection current, I Bj,u ik
*s the
recom bination current in the base region, and I B scr is the space-charge recom bination cur­
rent in the base-em itter junction. Two im portant performance param eters in H BT design
are the D C current gain (0), and em itter-base doping concentration ratio given by [8 ];
[c
_
~
h , bulk
__
max
(1.5)
i V r Vmd
max
^ -^ ex p (A E
B
PE
/kT)
( 1.6)
8
where N p / P b is the em itter-base doping concentration ratio, A E g is the energy gap dif­
ference between the em itter and base layers, v nB/ v PE is the ratio o f electron to hole veloci­
ties. 0max is the m axim um DC current gain value given by the ratio o f the injected electron
and hole currents I ^ I B>P in the absence o f recom bination currents and allows the em itterbase doping ratio to be «
1. A highly doped p+ base can therefore be realized enhancing
the m axim um oscillation frequency (frnax)- H om ojunction bipolar transistors are lim ited in
both speed and linearity due to the relatively low base doping. Finally, attention should be
paid in controlling the surface recom bination current by appropriate material choice and
processing since this param eter is a m ajor lim iting factor that reduces the D C current gain
O ).
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6
1.3 Why GalnP/GaAs HBTs over AlGaAs/GaAs HBTs
G alnP/G aA s heterojunction bipolar transistor (H BT) technology has evolved con­
siderably since the 1980’s [9] and com bines several attractive advantages over traditional
A lG aA s/G aA s H BTs such as high speed, high reliability (long life), and high pow er per­
form ance [10]. Table 1.1 shows typical material properties for G alnP/G aA s and AlG aA s/
G aA s heterojunction system s. The first advantage offered by G alnP/G aA s devices is
related to their em itter (E)-base (B) heterojunction which has a large valence band offset
(AEy = 0 .2 4 -0 .4 eV ) and small conduction band offset (AEC = 0.0 3 -0 .1 2 eV). This pro­
vides the possibility o f better injection efficiency com pared w ith AlGaAs/GaAs HBTs
w here AEy = 0.13 eV, AEC= 0.25 eV. A large AEy value can efficiently suppress the hole
injection to the em itter in npn HBTs and the energy band lineup in this type o f heterojunc­
tion im proves em itter injection efficiency. Reports on the AEC, AEy band offsets present
values that vary from 0.03eV to 0.19eV for AEC and 0.21 to 0.4 for AEy [11]. T he material
exists in ordered and disordered form depending on the growth tem perature and technique.
T he ordered structure is found to have a band gap energy E g - 1.85 eV and is referred to as
“abnorm al” indicating an ordered distribution state in the G a and In sublattice arrange­
m ent. T he random distribution o f Ga and In sublattice is referred to as “normal” and the
corresponding bandgap (Eg) and equal to 1.9 eV. The band gap energy (Eg) for GaxIn i.xP
grow n by M OVPE has been found to depend on the growth conditions, such as growth
tem perature and V /m ratio [12], even under fixed alloy com position (x=0.5). Reduction o f
the conduction band discontinuity (AEC) by the presence o f an InG aAsP layer between
G alnP and G aA s w as also reported [13] and led to 0.01V o f tum -on voltage which is
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7
sm aller than for conventional G alnP/G aA s HBTs. These considerations suggest that band
discontinuities and thus device perform ance can be strongly influenced by growth condi­
tions. The second advantage o f G alnP/G aA s over A lG aA s/GaA s H B Ts is the extremely
high etching selectivity between G alnP and GaA s, w hich enhances the process yield.
M oreover, AlGaAs is easily oxidized when exposed to air because o f the acute reactivity
o f aluminum . This im pacts the device lifetim e (reliability) and is a prim ary cause o f noise.
M ean tim e to failure (M TTF) values for these devices are in the range o f 104 hours. In
contrast, G alnP does not suffer from oxygen related im purities which are easily incorpo­
rated during the epitaxy o f AlG aA s. As a result, G alnP H BTs have achieved a M TTF val­
ues o f 106 hours at Tj = 200 °C which is adequate for the 25-year lifetime requirem ent o f
practical system s [84]. A nother advantage o f G alnP/G aA s over A lG aA s/G aA s HBTs is
related to material growth. Carbon has been used for p-type dopant in both GaAs and
A lG aA s. In case of G alnP/G aA s H BTs, a very sharp p-n junction is form ed between the
G alnP and GaAs interface since the carbon dopant has an am photeric behavior in G alnP/
GaA s. As a result, diffusion o f carbon from the base to the em itter results in n-type G alnP
and the em itter-base junction presents always sharp interface characteristics. The break-
p-n
heterojunction
£g
AEg
AEc
AEV
X
Structure
types
A lgjG ag^A s
0.38
0.25
0.13
3.71
4.07
A x<A Eg
GaAs
1.80
1.42
GaO.51In0.49P
GaAs
1.92
1.42
0.50
0 .1 2
0.38
3.95
4.07
A x<A Eg
Table 1.1: Typical material properties for G alnP/G aA s an d A lG aA s/G aA s herteroj unc­
tion systems.
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dow n voltage o f G ain ? devices is another im portant issue in term s o f pow er application.
N TT reported a high value (9.4V) o f breakdow n voltage in G alnP/G aA s FETs w hile main­
taining excellent high frequency perform ance by using a double-layered gate consisting o f
W SiN with different nitrogen contents, and by designing the device with variable epitaxial
layer thickness and im plantation dose [14]. B ulk G alnP is reported to have a breakdown
voltage o f >25V which is higher than 10V expected for GaAs. One can therefore consider
its use in the collector o f HBTs in order to obtain im proved pow er perform ance. The
resulting device is in this case a D ouble Heterojunction Bipolar Transistor(D H BT). A
spacer can be used between base and collector to reduce the conduction band spike and
enhance the DC and RF perform ance. This decreases the offset voltage (Voffset) by reduc­
ing the spike existing at the collector interface in the D HBT [12]. D espite the above dis­
cussed advantages, G alnP/G aA s H B Ts have still not been developed to the same degree as
A lG aA s/G aA s devices. In this w ork, high speed G alnP/G aA s HBTs (f-p= over 50GHz,
fmax= over 100GHz) com parable to conventional AlGaAs/GaAs H BTs are dem onstrated
and various layer designs such as tunneling em itter and electron launcher are studied. Fig.
1.2 shows state-of-the-art o f high frequency perform ance for G alnP/G aA s H BT discrete
devices reported in the literature. A m ong the G alnP/G aA s HBTs in Fig 1.2, fT o f 58GHz
and fmax o f 100 GHz using the tunneling em itter design (Sec. 4.1), fT o f 62G H z and f n ^
o f 75 G H z using the com posite em itter design (Sec. 4.2) and f j o f 28G H z and
o f 63
G H z using the D ouble HBTs were dem onstrated in the work presented in this thesis. The
U niversity o f M ichigan. The reliability characteristics o f these devices w ere also investi­
gated. B roadband transim pedance am plifier circuits (BW = over 17GHz) using various
circuit configurations such as C-E, Cascode, distributed, high gain m ulti feedback stages
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
9
250
NEC, 1995 (AlGaAs/GaAs)
+
200
Tl, 1997
a
❖
Hitachi, 1998
£ .5 0
o
• U of M, 1998 + y | m|n0|s 1 9 9 5
U of M, 1997 *
mino..,
Ti, 1993 ♦
• U of M, 1997
J*
X Columbia U, 1996
U of M, 1999 DHBTs
1 100
i<—■
50
U of M, 1 9 9 4 s
0
0
20
40
60
80
100
120
140
fT [GHz]
Fig. 1.2: State-of-the-art o f high frequency perform ance (fT, fmax) for G alnP/G aA s HBT
discrete devices.
were also designed, fabricated and successfully analyzed for near-future optical telecom ­
munication systems. Finally, the pow er perform ance o f G alnP/G aA s H BTs was also
investigated and the im pact o f collector metals, ballast em itter resistor and collector thick­
ness on the pow er characteristics are reported.
1.4 O bjectives and Scope of This Thesis
This thesis addresses the im provem ent o f high speed and high pow er perform ance o f
self-aligned G alnP/G aA s H eterojunction B ipolar Transistors (H BTs) by m eans o f various
layer designs such as tunneling em itter and electron launcher designs. T he G alnP/G aA s
HBTs presented in this w ork were grown by C hem ical Beam Epitaxy (CB E) at Thom sonCSF and M etal Organic C hem ical Vapor D eposition (M OCV D ) at H ughes Spectrolab
(Sec. 4.3). T he realization o f broadband, high-bit-rate transim pedance am plifiers using
optim ized devices for near future optical telecom m unication system s is also addressed.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
10
Chapter II presents the technology developed for the self-aligned G alnP/G aA s HBTs
and M M ICs. This w ork concentrates on the optim ization o f ohm ic contact and passive ele­
ments necessary for the fabrication o f H BTs and circuits with good electrical characteris­
tics. Various metals for n and p type layers were com pared and optim ized in term s o f
annealing tem perature and time. In the case o f capacitors, three kinds o f dielectric m ateri­
als, namely, AI2 O 3 , SiO, and SiC> 2 were electrically characterized. An effort was also
made to improve the adhesion between the metal and the deposited dielectric films. A sim ­
ple w et etching technology was em ployed to obtain lateral etching undercut (LEU) and
improve the electrical performance.
C hapter III presents the analysis and characteristics o f the fabricated G alnP/G aA s
HBTs and com pares various designs such as abrupt vs. graded em itter-base junction. The
DC current gain (fS) vs. cutoff frequency and the im pact o f em itter size on microwave per­
formance are also reported. The results obtained perm it to evaluate the device properties in
order to determ ine optim um device configuration for high speed and high pow er applica­
tions.
Chapter IV focuses on the theoretical study o f device properties using M onte C arlo
simulation, and reports the fabrication and analysis o f various H B T designs such as a com ­
posite emitter, tunneling em itter, and im proved high speed D HBTs using doped G alnP
spacer. Since the perform ance o f the circuits is influenced by device perform ance, various
H BT designs were considered, fabricated, and characterized.
In chapter V, the collector-em itter offset voltage o f G alnP/G aA s HBTs is investigated
using N i/G e/Au and Ti/Pt/A u collector contact metals. The w ay that the offset voltage is
influenced by the choice o f different collector metals in case o f HBTs w ith low-doped sub­
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11
collector designs ( 2 -
6
x 10 1 8 c m '3) is reported. Experim ental and theoretical investiga­
tions are conducted for this purpose and the Voffset dependence on collector metal barrier
is described. The offset voltage for H B Ts with Ti/Pt/Au collector m etal is shifted by
0.26V com pared to N i/G e/A u due to the 0.26eV barrier existing between the n-GaAs sub­
collector and the Ti/Pt/A u contact metal. O ther param eters affected by the collector con­
tact barrier and im pacting transistor perform ance include DC gain, microwave and pow er
performance.
Chapter VI presents passivation studies and reliability tests of G aln P HBTs. Once
devices are fabricated, a passivation process is required to prevent degradation o f the
device. DC and RF perform ance before and after passivation are then com pared to evalu­
ate the im pact o f passivation.
In chapter VII, various m onolithic transim pedance amplifiers are reported. Their
design, fabrication, and testing is discussed. These circuits show a transim pedance gain of
up to 47dB£i with bandw idth o f over 25 G H z and operation rate o f lOGb/sec. The large
signal characteristics o f tw o transim pedance am plifier designs (C-E vs. Cascode) with
sim ilar gain is also investigated and show that the cascode approach is m uch less sensitive
to input pow er level.
Chapter V m addresses the pow er characterization o f H BTs. A nalysis and character­
ization o f high pow er G alnP/G aA s H B Ts are described for single-finger (2 x 30 p m 2) and
multifinger em itter (10 finger 2 x 20 pm 2) devices. A simplified analytical large-signal
H B T model is introduced to predict the first order o f the pow er perform ance trends. A
m axim um pow er o f 1.08 W (5.4 W /m ra) using 10 finger 2 x 20 pm 2 G alnP/G aA s H BTs is
reported underclass B operation (VCE=10 V).
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12
Finally, Chapter IX provides the conclusions o f this work and presents suggestions
fo r future study in this area.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER II
G a ln P /G a A s HBT AND MMIC FABRICATION
TECHNOLOGY
This chapter describes the developm ent o f the self-aligned G alnP/G aA s H BT and
M M IC fabrication technology for high speed and high pow er applications. The fabrication
technology was based on all w et based chem ical etching technology which is sim pler and
m ore reliable than dry etching technology. The purpose o f this w et based chem ical etching
fabrication technology is to (1) reduce the total process tim e, (2) reduce layer dam age, (3)
enhance device yield and (4) dem onstrate possibility o f a simple technology in m anufac­
turing microwave and com m unication products. T he M M IC and self-aligned process tech­
niques are basically identical except for the additional fabrication steps o f resistor and
capacitor. This chapter begins with optim ization o f ohm ic contacts fo r base layer and pas­
sive lum ped elem ents for M M IC fabrication and then describes the key features o f each
process step. Finally a m ore advanced technology, called Laterally Etched U ndercut
(LEU ) technology using w et base etching is illustrated which reduces the total base-collector capacitance (C BC) and im proves the m axim um oscillation frequency ( f , ^ ) .
13
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14
2.1 Optim ization o f ohm ic con tacts for base and em itter
contact layers
The fabrication o f high speed heterojunction bipolar transistors (HBTs) requires a
heavily doped p-type base layer. M axim um oscillation frequency ( f , ^ ) is an im portant
figure o f merit for high frequency transistors and can be expressed using a sim ple form ula
as following;
(2. 1)
max
where f j is the current gain cutoff frequency, C BC is the base-collector capacitance and
R b is the total base resistance.
The total base resistance consists o f three com ponents as follows;
R B = r i + r a c c + r bc
(2 .2)
where q is the intrinsic base resistance in the active region, racc is the series access
com ponent o f the base resistance, and r ^ is the base ohm ic metal contact resistance, q is
bias dependent and decreases as the collector current increases. O n the other hand, racc and
r^c are bias independent an d controlled by base doping concentration and optim ization of
base metal deposition respectively. The use o f carbon as an acceptor dopant in the base
layer o f H BTs is o f interest due to the possibility o f incorporating high dopant levels (>
10 i 9 cm '3) with low diffusion coefficient
( - 6
x 10' 1 5 cm 2/sec at 900°C) [15] o f carbon as
com pared to the m ore com m only used B e dopant w hich has a diffusion coefficient o f
lx lO 'I 2 cm 2/s at 900°C; characterization o f diffusion coefficients at this high tem perature
was necessary in order to evaluate diffusion effects taking place upon layer annealing. At
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15
the growth and processing tem perature that are norm ally much lower than 900°C, it is
therefore expected that the diffusion coefficient will be much lower. The Pt/Ti/Pt/Au metal
system is one o f candidates for good ohm ic contacts o f base layer in HBTs. The key fea­
tures o f this metal system are (1) the diffusion front o f Pt after annealing is flat com pared
to that o f gold based metals such as A uZn/A u which m ay present alloy spikes. T hese may
reach the collector layer, thereby increasing the leakage current between base and collec­
tor, (2) extremely low contact resistivity to p+ G aA s is obtained by this metal system due
to the low potential barrier height o f m etal to p-type sem iconductors and (3) P t form s a
very stable intermetalic com pound with G aA s [16]. In this work, Three metal system s (Pt/
Ti/Pt/A u, Ti/Pt/Au, Pd/Zn/Pd/A u) are com pared to find an optim um base ohmic contact
m etal system in HBTs. T hese metal system s have been deposited by e-beam and have
been individually optim ized and suggested good base ohmic contact characteristics as
reported earlier [17], [18], [19] where the role o f Ti/Pt in Pt/Ti/Pt/Au and Pt in Ti/Pt/A u is
to block the diffusion o f A u into the base layer and Zn in Pd/Zn/Pd/Au m ainly leads in
higher p doping concentration in the p-base layer after diffusion into the base. H owever no
system atic com parison o f their characteristics was presented. In order to evaluate a suit­
able metallization schem e for base layer in G alnP/G aA s HBTs, three types o f base m etal­
lizations (Pt/Ti/Pt/Au (50/150/150/1500 A), Ti/Pt/A u (150/150/1500 A), Pd/Zn/Pd/A u
(250/100/250/1500 A)) w ere com pared before and after rapid therm al annealing (RTA) at
375°C, for lOsec. T he use o f RTA allow ed reduction o f the contact resistance value ( r ^ )
for the as deposited case w ithout risk o f spike form ation and thus danger o f short circuit­
ing from base to collector. T he results o f base ohmic contact resistance for the three m etal­
lizations are shown in Table 2.1. All tests resulted in sim ilar values o f base layer sheet
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16
Doping
p+ base: 5 x 1019cm"J 1000 A GaAs
Metal
system(A)
Pt/Ti/Pt/Au
(50/150/150/1500)
TVPVAu
(150/150/1500)
Pd/Zn/Pd/Au
(250/100/250/1500)
Resistance
Rc
(O)
Rs
(Q/sq.)
Rsc
(Q-cm2)
Rc
(Q)
Rs
(Q/sq.)
R sc
(Q-cm2)
Rc
(Q)
Rs
(Q/sq.)
Rsc
(Q-cm2)
Before Anneal
2.74
128
637x10*
6
433
1303
163x10*
<
3.04
130
7.98x10*
6
RTA 375'C.
lOsec
2.42
130.7
5x10**
2.8
131
6.47x10*
0
2.66
1314
6.05x10*
6
Work ftinction
of tbc metal
P t: 5.65eV
T I: 4 J3eV
P d : 5.12eV
Table 2.1: Ohmic contact study o f different metallization for p+ G aA s base layer. Pt/Ti/
Pt/Au was found to perform best due to low potential barrier height metal to
p-type sem iconductors.
resistance since the sam e p+ GaAs base layer was used for com parison. Although the Ti/
Pt/Au metallization schem e has traditionally been recognized as being very suitable for
base ohm ic contacts, Pt/Ti/Pt/Au w as found to perform best. This is likely to be related to
its higher work function (<!>M=5.65eV for Pt vs. 5.12eV for Pd and 4.33eV for Ti). This
allows m ore efficient hole transport over the m etal-sem iconductor interface and results in
im proved ohm ic contact quality. A slight contact resistance im provem ent was also
observed by rapid therm al annealing (RTA). This latter step w as also found im portant for
stabilizing the contact properties and achieving uniform and reproducible contact quality
over the wafer. Follow ing base ohm ic contact m etal optim ization, various tem perature and
annealing tim e experim ents w ere perform ed to further optim ize the base contact.
The results are shown in Table 2.2. A nnealing at low tem perature (385°C, 20sec)
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17
Doping
p+base: 4.2 x 10l9cm'3
600 A GaAs
Metal system(A)
Pt/Ti/Pt/Au
(50/150/150/1000)
Resistance
Rc
<Q)
(Q/sq.)
Before Anneal
1.75
529.2
385*C, 20sec
1.22
534
410*C, 40sec
2.03
537
Rs
Table 2.2: O hm ic contact study fo r p+ G aA s base layer. A fter 410°C, 40sec RTA treat­
ment, the base contact resistance is degraded.
offers base contact resistance im provem ent. O n the other hand, the base contact resistance
w as degraded after relatively high tem perature annealing (410°C, 40sec). The resulting
contact resistance was in this case sim ilar to the one obtained by as deposited Ti/Pt/Au.
A sim ilar study was carried out for the optim ization o f n+ G aA s em itter and collec­
to r contact. A high value o f contact resistance for the em itter and collector layer results in
a low D C current gain, high knee voltage, m ediocre microwave and pow er performance.
In these experim ents, n+ G aA s w ith a doping o f 10 1 9 cm ‘ 3 was used in order to evaluate
the properties o f three different m etallization schem es. T he n+ G aA s layers were grown by
C B E on SI G aA s substrates. T able 2.3 show s results obtained from TLM studies using
these contact metallizations. Ti/Pt/A u was chosen for this em itter ohm ic contact study.
O ther m etal schem es such as Pt/Ti/Pt/A u and In/N i/A u [20] w ere also com pared for inves­
tigating the low est value o f em itter ohm ic contact.
A s this study suggests In/N i/A u (250/500/2500 A ) gives the low est contact resis-
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18
Doping
n+ layer : 1 x lO ^cm 3 2000A
Ti/Pt/Au
(150/150/2500)
Metal systan(A)
Resistance
Pt/Ti/Pt/Au
(50/150/150/2500)
In/Ni/Au
(250/500/2500)
Rc
Rs
Rsc
Rsc
Rsc
(Q-cm2)
(Q/sq.)
(Q-cm2)
Rc
(Q)
Rs
(Q/sq.)
Rc
(Q)
Rs
(Q)
(Q/sq.)
(Q-cm2)
Before Anneal
7.23
31.05
1-89X10-*
16
28
lo jx itr4
12.1
28
5.89x10"*
RTA 375'C,
lOsec
6.76
31.2
1.65x10-*
8.86
30
2.94x10'*
4.84
31.4
8.4xl0*5
Table 2.3: O hm ic study o f different m etallization fo r n+ G aA s Layer. In/N i/A u gives the
low est contact resistance but the surface morphology of this m etallization is
not good and possibly not as reliable as a non-diffusing m etallization such as
Ti/Pt/A u.
tance. However, since the surface m orphology o f this metallization as tested by optical
inspection is not good and possibly not very reliable, Ti/Pt/Au was selected as the m ost
suitable ohmic contact approach in this technology. Ti/Pt/Au m anifested very good m or­
phology after therm al annealing treatment. M oreover, the ohmic contact resistance value
for Ti/Pt/Au is com parable to that o f In/N i/A u m etallization.
2.2 O ptim ization o f passive com ponent technology for ICs
M icrowave M onolithic Integrated C ircuits (M M IC s) and O pto-electronic Integrated
C ircuits (O EIC ) require reliable passive lum ped elem ents such as resistors and capacitors.
A study o f such com ponents was perform ed to determ ine the m ost suitable approach for
G alnP/G aA s ICs. F or resistors, a thin N i/C r film w as selected. T he thickness o f th e film
was adjusted to 700 A w hich corresponds to
2 0
Q /sq sheet resistance. The breakdow n
voltage o f th e resistor w as m ore than 20 V and the m axim um current it could handle
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19
exceeded 100 mA w hich is the current lim itation o f H P4145; this corresponds to a current
density o f at least 1 .4 x l0 5 kA /cm 2. M onolithic capacitors consist o f a dielectric m aterial
sandw iched between tw o m etal layers (M IM capacitor). The choice o f dielectric m aterial
is very im portant in determ ining the quality factor (Q factor) o f the capacitor w hich is
related to losses in resonant circuit. In this study, several dielectric m aterials i.e. A12 0 3,
SiO , S i0 2 were com pared as shown in Table 2.4. T he dielectric materials were deposited
using an e-beam evaporator. The adhesion between metal (especially Au) and dielectric
m aterial was im proved by adding a Ti (500 A) layer prior to dielectric deposition. T he
capacitor breakdown voltage for all o f these dielectric thin films was measured to be above
30V. All dielectric m aterials presented here are appropriate for capacitor fabrication. H ow ­
ever, thinner evaporated dielectric materials are m ore likely to present pin-holes for the
fabrication o f M M IC com ponents. Thus A 12 0
3
(3800A) was chosen in this work for the
fabrication o f M M IC com ponents.
Dielectric materials (Measured thick.)
AI20,(3800A )
SiO (2650 A)
SH>2 (800 A)
Theoretical dielectric constant
9
6
4
Ifcrget capacitance value (pF)
0.15
0.32
0.6
0.15
032
0.6
0.15
032
0.6
Measured capacitance value (pF)
0.15
0.29
0.54
0.12
0.26
0.47
039
0.83
1.51
Resistance (k£2)
11
4.96
2.65
18.8
8.43
3.6
34.1
183
10
Q factor at 1MHz
96
125
no
71
74
91
11.7
104
103
Calculated dielectric constant
8.9
5.56
536
Table 2.4: C apacitor study fo r M M IC lum ped elem ents. T hinner evaporated dielectric
material presents m ore pin-holes and can lead in short-circuited com ponents.
A12 0 3 (3800A ) appears to be a better choice.
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20
2 .3 Selective Wet Etching Technology for GalnP/GaAs
HBTs
Selective wet etching technology o f sem iconductors is an im portant step in the fabrica­
tion o f H BTs for high speed and high pow er applications. Excellent etching selectivity
between the G alnP em itter and G aA s base is needed due to the very small base thickness
(300 ~ 600 A) o f HBTs. Furtherm ore the successful realization o f self-aligned profiles
between em itter and base requires appropriate w afer orientation. T here are several candi­
dates o f G aA s and G alnP etchants such as citric acid/H 2 <I> 2 solution, N H 4 O H : H 2 0 2 : H20
solution for G aA s and pure HC1, H C 1 : H 3 PO 4 and H C 1 : H N O 3 for GalnP. In general, the
etchant for GaAs contains one com ponent that acts as the oxidizer (ex. H 2 0 2) and another
com ponent which is a dissolving agent (ex. NH 4 OH, citric acid) [21]. In this work,
NH 4 OH : H 2 0 2 : H20 solution for G aA s and pure HC1 for G alnP w ere chosen and investi­
gated for selectivity and etching profile.
The etching rate o f N H 4 O H : H 2 0 2 : H 20 (10 : 4 : 500) for G aA s is 33 A/sec and pre­
cisely reproducible from run to run. HC1 based solutions fo r the G alnP em itter offered also
the possibility o f undercut as necessary for self-alignm ent w hile perm itting good surface
morphology after etching. G aln P is less susceptable to oxidation than AlGaAs and appears
to contain few er deep level centers. It can be selectively w et etched in HCl-based solu­
tions. Fig. 2.1 shows the etched G aA s base surface m orphology by HC1 : H20 (1:1) (a)
and pure HC1 (b). As can be seen, the morphology o f surfaces treated by the H C 1 : H20
( 1 : 1 ) solution is not uniform and has no formation o f undercutting leading therefore in dif­
ficulty to obtain a self-aligned profile. D ue to anisotropy o f the etchant (NH 4 OH : H 2 0 2 :
H 2 0), the etched profile o f the em itter is obviously different in [011] and [01-1] directions;
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21
(a)
(b)
Fig. 2.1:
T h e etched G aA s base surface m orphology by H C 1 : H 20 (1:1) (a) and pure
HC1 (b). T he surface m orphology (a) is not uniform and has no form ation o f
undercutting to obtain self-aligned profile.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
E m itte r
Fig. 2.2: Etch profiles at different crystalline directions. Shapes produced using NH4OH
: H 2 O 2 : H 2 O for G aA s and pure HC1 for G alnP em itters on (100) oriented
G aA s substrate.
anisotropic properties arise due to the bonding energy difference along the different crys­
tal direction. Fig. 2.2 shows the etched em itter profiles treated by NH 4 O H : H 2 0 2 : H20
and HC1 solution at different crystal directions. Self-aligned HBTs can be achieved using
the [O il] direction etched profile. H igh selectivity values o f 1350 and infinity were
obtained for G aA s over G alnP and G alnP over G aA s respectively as extracted by 9 sam­
ples tested fo r that purpose at room tem perature. B ecause o f high degree o f selectivity, the
etch rate o f G aln P by an HC1 solution does not need to be carefully calibrated. The separa­
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23
tion o f the em itter m esa from th e base metal edge as controlled by pure HC1 is on the other
hand m ore im portant to obtain an appropriates self-aligned shape. Laterally etch rates o f
2 0 0
A/sec and 80 A /sec were achieved for 300 A and
2 0 0 0
A thick G alnP respectively
using pure HC1. Table 2.5 shows the summary o f etching rate, selectivity and undercut
separation to obtain self-aligned shape along [O il] direction o f GaAs and G alnP em itter
fingers.
2 .4 Self-Aligned GalnP/GaAs HBT and MMIC Process Tech­
nology
T he general process o f self-aligned H BTs is identical with the M M IC process
except for the resistor and capacitor levels. The self-aligned technology em ployed for
G alnP/G aA s H BTs uses the sam e basic surface preparation and etching procedures as the
conventional process that was em ployed for rapid evaluation o f H BT materials. Special
M aterial
Etchant
Etching
rate
GaA s em itter
NH 4 O H : H 2 0 2 : H20
33 A/sec
G alnP 300 A em itter
pure HC1
2 0 0
G aA s/G alnP
N H 4 O H : H 2 0 2 : H20
M odest
G alnP/G aA s
pure HC1
High
A/sec
U ndercut rate/
Selectivity
2 0 0
A/sec
Table 2.5: E tching rate, undercut rate and selectivity for G aA s and G alnP em itter fin­
gers.
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24
attention was placed on optim izing the em itter etch profile for good self-aligned base char­
acteristics. Additional levels o f processing were also necessary to allow trench isolation
for reduced parasitics and interconnection o f the H B T term inals [22]. This fabrication
technique uses a w et etching technique for all levels which is advantageous over tech­
niques such as Reactive Ion Etching (RIE) from the point o f view o f sm aller induced dam ­
age o r unintentional polym er formation. The resistor and capacitor deposition em ployed
for M M IC was optim ized as described in the previous section. The self-aligned technology applied to the G alnP/G aA s H BTs and M MIC technology can be summarized as fol­
lows.
P rep o sitio n (lift-off process): The first step in the self-aligned process consists o f
depositing alignm ent marks and device indicators using the Preposition mask level. Ti/Au
is deposited for this purpose after etching o f the InG aAs and G aA s em itter cap by 1500 A.
E m itte r c o n ta c t (lift-off process): T he em itter metal is in this step deposited on top of
the InGaAs o r G aA s cap layer. The nominal size o f the em itters covers a wide range o f
values but the work reported here focused on particular geom etries nam ely 2 x 30 pm 2, 2
x 10 p m 2, 5 x 10 p m 2, 5 x 30 p m 2. Follow ing em itter metallization, the em itter cap and
em itter layers are etched down to the base. Etching takes place in a w ay that an undercut is
form ed in the G alnP layers under the m etallization. P rior to etching o f the em itter layer,
the etching profile o f the em itter is confirm ed using test wafers analyzed by SEM. This
perm its precise control o f the separation distance between the em itter edge and the base
metal.
Base and Base trench contact (lift-off process): Pt/Ti/Pt/A u was used as base metal.
A thin base metallization is used to avoid short-circuiting the base-em itter terminals. T he
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25
thickness o f Au in the above base m etal system w as therefore varied from
1 0 0 0
~ 1500 A
depending on H BT design. To alleviate the high contact resistance resulting from the thin
base metal, a thick m etallization o f Ti/Pt/A u is subsequently deposited. This trench metal
overlays the top o f the thin base m etallization and extends to a larger pad on which the air­
bridge is deposited.
B ase R em oval a n d C o lle c to r R ealiza tio n (non lift-off process for base removal and
lift-off process for collector): Photoresist is used in this step to mask the em itter-base
region and w et etching is em ployed to rem ove the exposed base and collector regions. Fol­
low ing this step, the collector m etal (Ti/Pt/A u o r Ni/Ge/Au/Ti/Au) is deposited by e-beam
evaporation. The HBT D C characteristics can at this stage be m onitored and a go/no-go
decision is made.
M esa-Iso latio n (non lift-off process): W et etching is used fo r mesa- isolation. Test
patterns o f narrow dim ensions (1.0, 1.5, 2.0 pm ) helped in this case to evaluate the lateral
undercut evidenced by metal lift off. T he evaluation o f good m esa isolation can be tested
to confirm the insulator characteristics by tw o-point probe DC test after m esa-isolation
etch.
R e sisto r a n d C a p a c ito r (lift-off process): N i/C r is deposited on the sem i-insulating
G aA s substrate by e-beam evaporation. T he AI2 O 3 dielectric material for capacitor is
deposited on a bottom m etal plate m ade with collector metal. M IM capacitors are made
using interconnect metal for th e top capacitor plate. Before depositing the capacitor
dielectric, Ti is deposited to obtain good adhesion between the bottom metal and the
capacitor film.
In te rc o n n e c t, P illa r a n d A irb rid g e (lift-off process): Following device isolation for
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26
the H B T device process or resistor and capacitor deposition for M M IC process, a thick
interconnect m etal (Ti/Al/Ti/Au) is deposited using the interconnect mask. Finally, pillars
and airbridges were m ade by thick metal depostion (Ti/Al/Ti/Au).
T h e specific process em ployed for G alnP/G aA s H B T fabrication is briefly tabulated in
Table 2.6 together with the key features o f self-aligned technology for the base removal
and collector realization. Process sequence for the fabrication o f an air-bridge using evap­
oration technique can be found in the Appendix.
Fig. 2.3 shows (a) an SEM photograph o f a 2 x 30 p m 2 fabricated H BT before pillar
and airbridge realization and (b) a photograph o f typical M M IC fabricated with self­
aligned H B T technology, resistor (N i/Cr) and capacitor (AI 2 O 3 ) deposition. A cross sec­
tional view o f the em itter and adjacent self-aligned base contacts is shown in Fig 2.4. O ne
observes an inw ard slope of
- 2 0
w hich allows
0 .1
-
0 .2
p m separation between the em itter
finger and base m etal edge. This separation was achieved by optim ization o f the etching
procedure used for the em itter finger orientation along (0
1 1
) direction.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
27
Step
1
,#
2, # *
3, 9 +
5,9 +
6,9 +
Tide
D escription
Preposition
Etch InGaAs o r GaAs
em itter cap. Deposit
alignm ent marks and
device indicators using
Ti/Au.
Em itter
M etal and
Etching
D eposit em itter m etal, Ti/
Pt/A u o r Ni/Ge/Au for
em itter cap.
Etch em itter cap and em it­
ter to expose the base layer
using appropriate etchant
A for G aA s and B for
GalnP.
Base Metal
D evice profile
Emitter Metal
/
GalnP Emitter
D eposit base metal, Pt/Ti/
Pt/Au.
B ase Trench
M etal
D eposit base trench metal,
Ti/Pt/A u.
B ase
Removal
Etch away G aA s base and
extrinsic collector layer
using etchant A.
C ollector
M etal
D eposit collector metal
using Ti/Pt/Au o rN i/G e/
Au.
7,9 +
M esa Isola­
tion
Etch collector and subcol­
lector layer up to semiinsulating G aA s substrate.
E tch undercut o f em itter
and base trench bridges
using appropriate etchants.
8, ★
R esistor
D eposit resistor film using
Ni/Cr.
Baae metal
B a se Trench and Pad
Collector Metal
Emitter Metal
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
28
9 ,★
C apacitor
D eposit dielectric capacitor
using A12 0 3 o r SiO.
10,
Intercon­
nection
Metal
D eposit interconnect metal
using Ti/Al/Ti/Au.
11,
Pillars
R ealize Pillar evaporation
technique. D eposit Ti for
Pillar metal.
12, # ★
Airbridge
Etch Ti with Pillar pat­
terned. D eposit airbridge
metal using Ti/Al/Ti/Au.
Airbridge Metal
olleefo
Mesa Isolation
W here • : HBT process, ★: M M IC process, Etchant A: NH4O H : H 2 0
Etchant B: pure HC1.
2
: H20 ,
Table 2.6: T he brief process em ployed for G alnP/G aA s H BT fabrication [22].
2.5 Laterally Etched Undercut vs. Conventional Technol­
ogy
The base-collector capacitance (CBC) together with the base resistance (R B) are
the m ost im portant param eters fo r increasing the m axim um oscillation frequency (fmax);
Eq. (2.1) shows the way these tw o param eters determ ine f , ^ . The high frequency device
perform ance is usually determ ined by optim ization o f layer design, the fabrication process
and device layout. There are several ways to reduce CBC, such as the use o f thick collec­
tors w hich, however, causes an increase o f collector transit time. Ion im plantation under
the base m etal can also be em ployed but results in high cost and loss o f crytallinity (base,
collector). The Laterally E tched U ndercut (LEU ) technique under the base metal is a good
alternative over the previous techniques to reduce C BC. The LEU technique can be
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
29
Interconnect
}
/ s'
Collector
Emitter
Base
(a)
RcMslni
(b)
Fig. 2.3: SEM photograph o f a 2 x 30 p m 2 fabricated H B T and photograph o f typical
M M IC fabricated using self-aligned H B T technology, resistor (Ni/Cr) and
capacitor (AI 2 O 3 ) deposition.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
30
Fig 2.4: A cross sectional view o f the em itter and adjacent self-aligned base contacts.
The separation (0.1 ~ 0.2 pm ) between em itter m esa and base metal was
achieved by optim ization o f the etching procedure used for the em itter orien­
tation so that fingers are aligned along [O il] direction.
em ployed to decrease the base-collector capacitance (CBC) w hile the base resistance does
not suffer with this technique. The base-collector capacitance (CBC) consists o f the fol­
lowing components:
C BC =
C j + C acc + ^ b c t + C b ce
( 2 -3 )
w here Q is the intrinsic collector capacitance, C acc is the spacer region capacitance
betw een em itter and base edge,
contact transfer length and
is the base contact capacitance corresponding to the
is the extrinsic base contact capacitance beyond the trans­
fer length. The fringing capacitance around the collector m esa is too small and negligible
to affect the total base-collector capacitance (CBc). Fig. 2.5 shows the schem atic device
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31
E m itter finger
B ase C ontact region
Transfer length
B ase Extrinsic region
Conventional
a
Intrinsic region, Spacer regioij Contact region Extrinsic region
C ’#
F ig 2.3: T he schem atic device layout and the associated cross section o f typical H B T
device w ithout (a) and with L E U technique and RC netw ork for the base-col
lector junction.
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32
layout and the associated cross section o f a typical H B T device w ithout (a) and with (b)
LE U technique. The R C netw ork for the base-collector junction is also shown. Cacc is con­
trolled by the undercut distance and corresponds to only small portion o f the total capaci­
tance CBC. Cfce consists a considerable portion o f the C BC and can be reduced using the
LEU technique leading to im proved m axim um oscillation frequency (fma*).
This LEU technique benefited from the presence o f a thin G alnP etching stop layer
( 1 0 0
A) between the collector and subcollector layers. T he extrem ely high etching selec­
tivity between G aA s and G alnP perm itted to m aintain the subcollector structure and the
resulting overetching o f the G aA s collector material reduced the extrinsic base contact
capacitance (C ^g). A com parison between LEU and no LE U (conventional) technique is
presented in Sec. 2.5.2 together w ith a discussion on the im provem ent o f microwave per­
form ance obtained by L E U [23].
2.5.1 Material growth and Device structure
The H BT layers w ere grown by C B E with non-toxic precursors and proved to be o f
high quality as dem onstrated by m aterial and device characteristics [24]. G roup III atom s
w ere provided by TEG a and TM In. Precracked tertiarybuthylarsine and phosphine (TBA,
TBP) and uncracked trisdim ethylam inoarsine (tD M A A s) were em ployed as G roup V
sources, ty p ic a l H B T structures used in this w ork consist o f a 300 A InG aAs em itter con­
tact doped n+
(1
x
1 0 19
c m '3),
1 1 0 0
A GaAs em itter cap doped n+
(1
x
1 0 19
cm '3),
2 0 0 0
A
GaA s em itter doped n (2 x 10 1 7 c m '3), 300 A G alnP em itter doped n (4.5 x 10 1 7 c m '3),
600 A G aA s base doped p + (4 x
1 0 19
cm '3), and 7000 A G aA s collector n- (1.5 x
3).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1 0 16
cm '
33
A thin 100 A G alnP etching stop layer is inserted between G aA s collector and subcol­
lector layer (n+
1
x
1 0 19
c m '3) to reduce base collector capacitance (C g c) by using the
Laterally Etching U ndercut (LEU) technology discussed in next Sec. 2.5.2. Table 2.7
shows the details o f a typical layer structure used for fabrication o f G alnP/G aA s HBTs.
2.5.2 LEU Technology and Device Performance
Self-aligned G alnP/G aA s single HBTs were fabricated using sim ple all wet based
chem ical etching which m inim ized layer dam age and device degradation. Ti/Pt/Au non­
alloyed m etal w as deposited to em itter and collector layers w hile Pt/Ti/Pt/A u was used as
the base metal. Laterally Etched undercut (LEU) was developed and applied between the
G a ln P T b n n elin g
E m itte r S tru c tu re
Thickness
(A)
Doping
C ontact Metal
(cm '3)
InG aAs Em itter contact n+
300
l.OxlO 1 9
InG aAs grad. 0 -> 0.5 n+
250
l.OxlO 1 9
GaAs Em itter contact n+
1 1 0 0
GaAs Em itter
2 0 0 0
n
l.OxlO 1 9
2
.0 x l 0
17
G a ^ tln ^ c P E m itte r n
300
4 .5 x l0 1 7
G aA s B ase
p+
600
4 .0 x l0 1 9
G aA s C ollector
n-
7000
1 .5 x l0 1 6
Gao.5 Ino.5 P etch stop
GaAs subcollector
n+
n+
1 0 0
7000
Ti/Pt/A u
Pt/Ti/Pt/A u
l.OxlO 1 9
l.O xlO 1 9
Ti/Pt/A u
Table 2.7: The layer structure for the fabricated G alnP/G aA s HBTs. T his H B T structure
was optim ized for high frequency performance.
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34
base and collector region to reduce base-collector capacitance (CBC) w hile avoiding base
resistance degradation. The key features o f the fabrication used in this w ork are a 0.5pm
base undercut to guarantee a reduced base resistance and thus an im proved maximum
oscillation frequency (fmax) and laterally etched undercut between base and collector to
decrease the base-collector capacitance (CBC) and thus an im proved fmax- Although part
o f the base layer under the base m etal was etched away, the base contact resistance did not
suffer since it is dependent on the ohm ic contact transfer length nam ely the distance
required for current to flow into o r o u t o f the ohm ic contact for a given base thickness and
doping density. The transfer length for the contact characterized here w as less than 1pm
and current conduction took consequently place close to em itter m esa and very far from
the undercut region. LEU technology is lim ited by possible m isalignm ent o f the base level
with respect to the emitter.
Fig. 2.6 shows the SEM cross section o f the fabricated H B T w ithout (a) and with (b)
LEU technology. Typical DC characteristics o f 2 x 30 p m 2 single em itter H B T device for
both H BTs (a), (b) include DC gain o f 38, base ideality factor o f 1.32 and collector ideal­
ity factor o f 1.12 and a collector-em itter breakdow n voltage o f ~ 20 V. O verall the LEU
technology does not affect the DC characteristics as shown in Fig. 2.7.
2 x 30 pm 2 single em itter H BTs w ere m easured using a netw ork analyzer from 0.5 to
25.5 GHz. A reduction o f CBc from 46.7fF to 36.5fF (Table 2.8) by lateral etching o f
about 6000 A leads to higher m axim um oscillation frequency w hich leads in its tum to
10% gain im provem ent at 10GHz as shown in Fig. 2.8. C om pared to the m ost com m only
used approach for m inim izing CBc w hich is based on ion-im plantation through the active
base layer, the L E U process analyzed here offers sim plicity and a very effective way o f
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35
W it h o u t LEU
lle c to i
O iilliK Idyci
{ 1U U A )
(a)
With LEU
E m itter m etal
B a s e metal
Uolleutoi
LEU
(b)
Fig. 2.6: Cross section S E M pictures o f the self-aligned G alnP/G aA s H B T w ithout (a)
and w ith (b) LEU technology.
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36
W ithout LEU technology
0.03
0.025
0.02
3*
“ 0.015
_o
0.01
0.005
0
•0.005
0
0
3
1
1.5
2
2
3
3
3
3
4
vCe IV]
(a)
With LEU technology
0.03
0.025
0.02
0.015
0.01
0.005
•0.005
13
23
(b)
Fig. 2.7:
D C characteristics o f the self-aligned G alnP/G aA s H B T w ithout(a) and
w ith(b) L E U technology. No im pact o f L E U technology as observed on D C
characteristics.
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37
reducing C BC. The key in this technology step is the incorporation o f a thin ( l x l 0 1 9 cm ' 3
doped) G alnP layer between the n + and n ' G aA s collector w hich provides selectivity in
etching and determines the etching profile below the base. T he resulting profile w as found
to m anifest stability upon all rem aining processing steps and device testing. 2x30pm 2 sin­
gle em itter HBTs fabricated using LE U technology dem onstrated an fT o f 58GHz and f , ^
o f 100GHz at Ic =20mA, VCE= 2 .5V. This corresponds to an fT increase o f 11% and f , ^
increase o f 25% as a result o f using LE U technology (see in Fig. 2.8). The microwave per­
form ance o f the investigated G alnP/G aA s HBTs shows only slight change w ith bias and
permits therefore robust circuit design. Table 2.8 shows the extracted H B T small-signal
equivalent circuit param eters with and w ithout LEU technology
with LEU
without LEU
:-6dB/Oct
<0 15
H
2
T
Frequency[GHz]
100
Fig. 2.8: M icrowave perform ance o f 2 x 30pm 2 single em itter H BT w ithout and with
LE U technology at V CE=2.5V, Ic =20m A. fT o f 51, 58GHz and fma, o f 80,
100GHz were m easured for w ithout and w ith L E U technology respectively.
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38
Cbx
r£i
IF
S22p—
o n M -w /_ L y v 5 fe
*bx
ri
-w W
^bc
^be^
= t= c,pi
J k
' &
C o lle c t o r
" ” ^ ”be
777 T
W
4
J Emitter
Without LEU
With LEU
R g (Q)
4.4
4.5
R c (Q )
14
17
R e (G )
3.5
3.5
Td (psec)
2 .8 6
2.54
C b c (® )
46.7
36.5
AC b c (fF)
2 1
G&j>
0.99
0.99
fT/ftnav (GHZ)
51/80
58/100
V c e /I c
2.5V/20m A
2.5V/21m A
.8 %
Im p ro v ed
Table 2.8: Sm all Signal H B T Equivalent C ircuit Param eters w ithout and with LEU
Technology. The H B T sm all-signal equivalent circuit param eters were
directly extracted from m easured S-param eterdata using an in-house analyti­
cal extraction technique. C bc ° f LEU technology is reduced by 21.8% and
leads to 25% im provem ent o f fp^*.
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39
2.6 Summary
The developm ent o f the self-aligned G alnP/G aA s H BT and M M IC fabrication tech­
nology for high speed and high pow er applications was described in detail. The fabrication
technology was based on all w et based chem ical etching technology which is sim pler and
m ore reliable than dry etching technology. O hm ic contacts for base and em itter were first
optim ized. N i/Cr for resistor and AI2 O 3 for capacitor w ere chosen following an optim iza­
tion undertaken for passive lum ped elem ents o f M M ICs. The adhesion between metal, in
particularly Au and dielectric material was im proved by adding a Ti (500 A) layer prior to
dielectric deposition. NH4OH : H 2 0
2
: H 20 solution for G aA s and pure HC1 for G alnP
w ere chosen and investigated in term o f selectivity and etching profile geom etry they offer.
The etching rate o f NH 4 O H : H 2 0
2
: H20 (10 : 4 : 500) for G aA s is 33 A/sec and was
found to be very reproducible from run to run. Laterally etched rates o f
A /sec w ere achieved for 300 A and
2 0 0 0
2 0 0
A/sec and 80
A thick G alnP respectively using pure H C 1 .
L aterally Etched U ndercut (LEU ) technology using wet base etching was shown to
reduce the total base-collector capacitance (C qq ). H B T s fabricated with LEU technology
dem onstrated an fT o f 58GHz and f , ^ o f 100GHz at Ic =20m A, Vc e =2 .5V. This corre­
sponds to an fT increase o f 11% and f , ^ increase o f 25% as a result o f using LEU tech­
nology.
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CHAPTER III
FUNDAMENTAL ANALYSIS OF
G a ln P /G a A s HBTS
This chapter details the analysis and characteristics of the fabricated G alnP/G aA s
HBTs and com pares various designs such as abrupt vs. graded em itter-base junction. The
relation between DC current gain (P) and cutoff frequency and the impact o f em itter size
on microwave perform ance are also described. The results obtained perm it to evaluate the
device properties in order to determ ine an optim um device configuration for high speed
and high pow er applications.
3.1 Abrupt Junction vs. Graded Junction
Two types o f heterojunction structures can be generally distinguished. Fig 3.1 (a)
shows the band diagram with an abrupt em itter-base junction in which the In m ole fraction
changes abruptly from the G aln P em itter to the GaAs base while Fig. 3.1 (b) shows the
graded heterojunction in w hich the change in In mole fraction occurs gradually over a dis­
tance from
2 0 0
A to 600 A. In this section, the difference in DC characteristics between an
abrupt and a graded heterojunction is illustrated. The HBTs exam ined here are 50 x 50
p m 2 large size devices where the base current due to surface recom bination (lB,SUrf) *s ne§_
40
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
41
nF
Ev
n- G alnP
p - GaAs
(a)
•
#■
EF
Ev
p - GaAs
n- G alnP
(b)
Fig. 3.1: Energy band diagram for (a) an abrupt G alnP/G aA s heterojunction and (b) a
graded G alnP/G aA s heterojunction [25].
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42
ligible com pared to the base currents due to bulk recom bination (Is.buik) an£* space charge
recombination (IB scr). This is due to the fact that IBiSurf *s proportional to the em itter
perim eter o f the em itter area and P/A is very small for such devices; P/A = 0.08 for 50 x
50 p m “ vs. 1.07 for 2 x 30 p m . Thus tw o most im portant base current com ponents in
large HBT devices are IB scrand IBjbuik- Further details on the im pact o f the surface recom­
bination current (lBiSurf) on base current are provided in C hapter IV which addresses the
tunneling em itter designs.
The base current can be expressed by Eq. (3.1) [26] where the ideality factor, n is
determined by whether space charge recom bination (IB>SCr) or bulk recombination (IB,buik)
is dominant;
/fi°exp( ^ )
(3.1)
where I B 0 is the reverse saturation base current. The base current with space charge
recombination (/flJcr) is known to vary with e x p ( V BE/ 2 k T ) w hile the base current with
bulk recombination (I b MuiO var>es with e x p ( V BE/ k T ) . Fig. 3.2 shows I-V characteristics of
the em itter-base junction and illustrates the different m ajor recom bination components.
T he HBTs with an abrupt or graded junction exam ined in this section have the same em it­
ter design except for the em itter doping concentration which was 4.5 x 10 1 7 cm " 3 for
abrupt junction versus 3 x 10 1 7 cm " 3 for the graded designs. The base doping concentra­
tion for both HBTs was 4 x 10 1 9 c m '3. In the case o f collector current (Ic ), the collector
currents for an abrupt and a graded junction HBTs have same slope a n d e a n be expressed
by:
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43
l c = / r o e x p ^ ~ f o r abrupt and graded H BTs
(3.2)
w here Ic q is the reverse saturation collector current. Thus, the collector currents faboth
abrupt and graded junctions follow the ideal, n = l slope. The ideality factor o f the cdkctor
current depends on the ratio o f the em itter doping concentration over the base dopiqjconcentration and is given by [6 8 ];
Ea/A/j
tlc =
where £*/,
1
+* =
1
+
e PN a
<3-3>
Ep are the dielectric constants (F/m) for n and p type layers and N d,N a ae the
em itter and base doping levels (cm '3), respectively. Thus the ric value is usually veryclose
to
1
since the em itter doping level is usually a few orders o f m agnitude less than thebase
2kT : High level injection
kT
2 k T : Space charge
recom bination region
Fig. 3.2: Forw ard-biased I-V characteristics from the ideal. There are three regions: low
current space charge recom bination region, medium current region, high level
injection regions.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
44
doping level.
Fig. 3.3 (a) shows the collector current (Ic ) o f an abrupt E-B junction HBT as a func­
tion o f VBE with an ideality factor O le) o f 1.03, w hile the base current ideality factor ( t|B)
is 1.41. An ideality factor between 1 and 2 indicates that the base currents are com posed o f
both the bulk recombination ( I b m h c k T ) and the space charge recombination current
{I b .scp 2 k T ) . Fig. 3.3(b) illustrates the DC current gain as a function o f the collector cur­
rent. As observed in this figure, the DC current gain increase slowly as the collector cur­
rent increases and nearly saturates at high collector current region. This behavior indicates
that both space charge recom bination and bulk recom bination co-exist in the low collector
current region whereas bulk recom bination dom inates at high collector current levels.
Com pared to abrupt E-B junction G alnP/G aA s H BTs, graded E-B junction G alnP/G aA s
HBTs have more significant /g Jcr rather than I b ,bulk since m ore space charge recom bina­
tion events take place at the depleted region including the additional graded em itter region.
The higher IB scr o f the graded E-B junction H BTs suggests that the depleted thickness
(xdn) in the graded em itter side is w ider than in abrupt E-B junction HBTs. This is simply
possible due to the slight difference in dielectric constants (er = 13.2 for GaAs, 11.35 for
G alnP) and can be given by;
X
-
f
2 e "EP N
X V bi
I 5 ..
i « N D( e p N D * e t IVA ) J
e ne p
t pN D + z „ N A
1' '
where En, ep are the dielectric constants for em itter and base layers and Vbi is the built-in
voltage. If one assumes that the graded em itter layer is nearly pure GaAs (er = 13.2), one
finds from Eq. (3.4) that the depleted thickness for the graded E-B junction HBTs is w ider
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45
le-OI
le-02
le-03
Ie-04
<
—
JU
le-05
"co
a le-0 6
le-07
le-08
le-09
lc-10
0.6
0.8
1.4
1.2
1.6
1.8
V BE- v c e M
(a)
lo o t
10
c
'3
°
1
0.1
•
■
•
0.01 1 - - ■ - - - — - le-05
le-04
-
le-03
. . .
le-02
0.1
IC [A]
(b)
Fig. 3.3: M easured Gum m el plot (a) and DC current gain (b) for an abrupt E-B G alnP/
G aA s HBT. The device size is 50 x 50 |xm2.
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46
than for the abrupt E-B junction HBTs. The estim ated increase o f the depleted thickness is
about
1 2
%.
Fig. 3.4 (a) is the measured Gum m el plot o f the graded E-B junction HBT. It shows the
collector current (Ic ) dependence on V BE for a graded E-B junction HBT and corresponds
to an ideality factor (rjc ) o f 1.06. The base current ideality factor (r|B)o f the same device
is 2.0. This suggests that the space charge recom bination current (2kT)
dominates
throughout the entire current range. Fig. 3.4 (b) show the measured DC current ( P ) as a
function o f collector current (Ic). P increases slowly as collector current increases and
never saturates to a constant value, which is a typical phenom ena in the graded E-B ju n c ­
tion HBTs. Thus, one can estimate the presence o f an abrupt or graded junction in HBTs
from the Gummel plot and DC current gain shapes.
3.2 DC Current Gain
(P)
and cutoff Frequency (fT)
In Si bipolar transistors, the cutoff frequency (fT = a>i-/27t) is typically defined as;
(oT =
r
P
„ , = „
^(C.+C„)
c„ + c„
for Si BJTs
(3.5)
where P is the DC current gain, rn is the base-em itter resistance, C^ is the base-em itter
capacitance (= C BE), C^ is the base-collector capacitance (= C BC) and gm is the transcon­
ductance. Thus, one needs high values o f P to im prove the cutoff frequency o f Si bipolar
transistors. However, this is not the case for im proving the fT o f HBTs. From Eq. (3.5), the
fx o f the Si bipolar can be mainly represented by the em itter transit time ( l / r E = Eq. (3.5))
since t e o f the Si bipolar dominates and corresponds alm ost to the total transit time ( t e c =
l/o>p = l/27tfT). In other words, t e »
( t b + t c + Rc C^). Moreover, the values o f C^, C n
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47
le-OI
le-02
lc-03
le-04
lc-05
t le-06
le-07
Tic = 1.06
le-08
lc-09
lc-10
0.6
0.7
0.8
I.I
0.9
1.2
1.3
1.4
1.5
1.6
V BE- V CE [V ]
(a)
100— .
10
— _
•
e
'3
O
I .
0.1
•
o.oi L .
—4 . .
le-08
lc-07
.
................................. ...................................
le-06
le-05
le-04
le-03
le-02
0.1
Ic [A]
(b)
Fig. 3.4: M easured Gummel plot (a) and D C current gain (b) for a graded E-B G alnP/
G aA s HBT.The device size is 50 x 50 |xm2.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
48
for Si BJT are around 20 times higher than for HBTs. D ue to these limitations o f Si BJTs,
the fT perform ance o f the device is lower i.e 18GHz [44]. The high D C current gain (3) of
high speed BJTs are often very high (3=1600 in [44]) to ensure good microwave perfor­
mance.
In HBTs, unlike Si bipolar transistors, the dom inant transit times are the base and col­
lector transit tim es ( t B, xc ). Therefore Eq. (3.5) should be modified to include the t b ,
xc
as following;
o)y = I”—
+ C g ^ ) + Tg +
+ C B^->(/?^ + /?^-.)l
for HBTs
(3.6)
where gm is the transconductance which is related to the base-em itter resistance, C BE is
the base-em itter capacitance, C BC is the base-collector capacitance, xB is the base transit
time, Xc is the collector transit time, RE is the em itter resistance and Rc is the collector
resistance. Thus, the cutoff frequency (fT = a>p/27i) o f H BTs is not significantly improved
by the DC current gain (3) but depends more on other param eters such as base and collec­
tor transit time.
Fig. 3.5 shows the common em itter current gain as a function o f frequency for HBTs
with high and low DC gain together with such characteristics for BJTs. The cutoff fre­
quency ( f j) is independent o f the DC current gain for H B Ts while fT depends on the DC
current gain for Si BJTs.
The m easured cutoff frequencies ( f j) for G alnP/G aA s HBTs with low and high DC
current gains are shown in Fig. 3.6. The tw o devices tested here were chosen from the
sam e w afer an d had therefore identical layer structures. The measured DC current gain
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
49
w as 70 for 5 x 30 p m 2 devices and 35 for 2 x 30 ^ m 2 devices. A maximum fT o f 50 G H z
was m easured at VCE = 2.5 V, Jc = 29.6 kA /cm 2 for 5 x 30 p m 2 devices and VCE = 2.5 V,
Jc = 26 kA/cm 2 for 2 x 30 p m 2 devices. From Fig. 3.6, the current gain, |H 2 i I of the 5 x 30
p m 2 devices is much higher than that of 2 x 30 p m 2 devices in the low frequency region
but alm ost the same at high frequency region. This results in obtaining the same cutoff fre­
quency from both HBTs.
The current gain values, |H 2 i| at i GHz are 32 dB for the 5 x 30 p m 2 devices and 28
dB for the 2 x 30 pm~ devices respectively. These values are consistent with an estimation
based on 20 log P where the respective P is 70 and 35 at very low frequency corresponding
to 37 dB for the 5 x 30 p m 2 devices and 31 dB for the 2 x 30 pm 2 devices. Thus, the cur-
High DC gain HBT (a)
2C*log P
-20 dB/decade
'tligli D C gain B.
Low DC gafn BJT
to [Hz|
^°3dB (a)
^ 3 d B (b)
Freq. [Hz]
Fig. 3.5: Comm on em itter current gain vs. frequency for high and low DC gain HBTs
and BJTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
50
rent gain in the low frequency region is significantly affected by the DC gain.
In the high frequency region, the current gain, IH2 1 I is m ore affected by other param e­
ters such as base and collector transit tim es ( t b , t c ) . The base transit time ( t b ) is defined
as following;
In =
B
WB
(3.7)
2D n
'
where W B is the thickness o f the base layer and Dn is the electron diffusion constant in the
base region. xB varies with the square o f the base thickness and can be reduced by decreas­
ing the base thickness. However, decreasing the base thickness will increase the base resis­
tance (Rb ) which decreases the maximum frequency of oscillation (fmax). Thus, there is a
35
32 dB
30
25
28 dB
03
*
2
a
5 x 30 p m single em itter
G alnP/G aA s HBT
20
*5
O
c 15
g
Low DC gain : 35
2 x 30 p m ” single em itter
G alnP/G aA s HBT
u 10
5
0
1
10
100
Freq. [GHz]
Fig. 3.6: The m easured cutoff frequencies for he G alnP/G aA s HBTs with low and high
D C current gains.
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51
trade-off between the base transit time and the base resistance.
The current gain is also affected by the collector transit time (tc ) which is given by;
where W ^,. is the width o f the space charge region in the collector. The collector transit
tim e can be reduced by decreasing the collector thickness. However, this m ethod also
brings an unintentional side effect, nam ely an increased RC charging time for the collector
region. Thus, there is also a trade-off between the collector transit time and the RC collec­
tor charging time. The RC collector charging time can be reduced without sacrificing
tc
by m eans o f ion implantation or Lateral Etched U ndercut (LEU) technology.
In summary, the cutoff frequency (f-p) for HBTs is independent o f the DC current gain
(3) due to the fact that other param eters in HBTs such as base and collector transit time are
more pronounced. High speed performance (fT=83GHz, fmax=197GHz) o f HBTs was for
exam ple dem onstrated in this work using a graded InG aA s base layer to reduce the base
transit time [37].
3.3 Impact of Emitter Size on Microwave Performance
Choosing an optimum em itter size for H B T devices is crucial for high speed applica­
tions. Fig. 3.7 shows a simplified HBT structure o f stripe geometry. The impact o f em itter
width (W E) and length (LE) on H BT microwave performance, i.e. fT and fmax was investi­
gated. The devices selected for this purpose w ere HBTs with 2 x 20, 2 x 3 0 ,5 x 2 0 ,5 x 30
p m 2 em itter stripes. The total transit time ( t Ec ) from em itter to collector can be found
from the equation for cutoff frequency given by Eq. (3.6):
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52
E m itter
m e ta l/
B ase
m etal
BC
C o llecto r
m etal z '
'EB
w,
S EB
S EB
Fig. 3.7: A sim plified transistor structure o f a stripe geom etry HBT.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
53
1
tec =
kT
2 n f T ~ ^ 7 ^ ^ f i£ + ^ s c ) + Ts + Tr + <'B c (^ E + ^ c )
k T ( esW e L e
= ^
r °
^
es( W e
_ *7Y ^
+ 2 S eb + 2 W b ) L e^
+
t /s t^ E +
\
d
Tc
r
+
P^E +
D BC
, £ ,(^ £ + 2 5 ^ +
-^ (5 7 /
(3.9)
°
(3
P^C
I0>
'i
/
v ^ E
2
c
^
T C
J+Ts+^ +x
(31,)
where W E, W B and Wc are the em itter, base and collector widths, LE = LB = L c, are the
emitter, base and collector lengths, C BE is the base-em itter capacitance, CBC is the basecollector capacitance,
tb
is the base transit time (=Eq. (3.7)),
tc
is the collector transit
time given by Eq. (3.8), RE and Rc are the em itter and collector contact resistances, DEB
and Db c are the base-em itter and base-collector depletion thicknesses, e s is the dielectric
constant, p is the resistivity, dE and d^ are the em itter and collector contact lengths. SEB
and Sc s are the em itter-base and collector-subcollector access distances and Wc is the
effective collector width related to the transfer length.
The dependence o f m easured microwave perform ance on em itter geom etry for about
the sam e collector current density is sum m arized in Table 3.1 together with the corre­
sponding DC bias conditions. Fig. 3.8 and 3.9 present the frequency dependent gain char­
acteristics o f the G alnP/G aA s HBTs used for extraction o f these data. T he measured
devices in Fig. 3.8 (HBTs w ith same (5pm ) em itter width) and Fig. 3.9 (HBTs with same
( 2 pm ) em itter width) have the sam e layer structure and were selected from the same
wafer. T heir highest cutoff frequency and the associated m axim um frequency o f oscilla-
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54
tion was obtained at a VCE bias o f 2.5V.
The results o f Table 3.1 show that the cut-off frequency (fT) is independent on the
em itter width (W E) and length (LE), and equals about 50 GHz independent o f device
geometry. These trends can be explained by considering Eq. (3.10) which shows that as
W E increases from 2 to 5 pm , Ic increases but Jc remains alm ost constant (30 kA/cm2).
De e also rem ains constant resulting in a constant value in the first term ( t e ) o f Eq. (3.11);
d bc
is kept constant when W E changes since the maximum f j and fmax perform ance
shown in Table 3.1 and Figs. 3.8-3.9 were obtained at a bias which corresponds to condi­
tions before Kirk effect takes place. t e and x q are not affected by WE and depends only on
the base, collector thickness and diffusion coefficient which remain constant since the
same layer design is em ployed for com parison. The 4th term o f Eq. (3.9) is also not
Em itter
geom etry
C ollector
current
Collector
current
density (JE)
DC
current
gain (p)
V CE
10
69
2.5
17.2
34
50/60
5x20
72
2.5
30.3
30
50/62
5x30
74
2.5
44.5
30
50/62
x
2 0
27
2.5
1 2 .2
30.5
50/80
2x30
31
2.5
15.5
31
52/80
[pm 2]
5x
2
[V]
(Ic )
[mA]
^T^max
[GHz]
[kA/cm2]
Table. 3.1: T he relation between em itter geom etry and measured microwave perfor­
m ance with D C m easurem ent data.
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55
35
30
5 x 1 0 n m 2 single em itter
25
20
15
(a)
H21
10
5
max
0
100
35
30
5 x 20 ^irn2 single em itter
25
20
(b)
15
10
5
T
0
'max
100
35
30
5 x 30 ^ m - single em itter
25
20
15
(c)
H21
10
5
0
max
100
Fig. 3.8: The m easured cutoff frequencies (fT) and maximum frequencies o f oscillation
(fmax) for various em itter geom etries. 5 x 10 (a), 5 x 20 (b), 5 x 30 |am 2 (c)
single em itter finger G alnP/G aA s HBTs.
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56
35
3 Q
2
x 2 0 |im 2 single em itter
25
20
15
\u
H2I
N
10
'
5
s
\
f j \ ^ \ max
0
'
* Too
(a)
2 x 30 nm single emitter
100
(b)
Fig. 3.9: The m easured cutoff frequencies (fx ) and maximum frequencies o f oscillation
(fmax) f° r various em itter geometries. 2 x 20 (a), 2 x 30 (im 2 (b) single em itter
finger G alnP/G aA s HBTs.
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57
affected by W E since the RE and CBC variations are cancelled out as W E changes. M ore­
over, this term is usually the sm allest one representing less than
1 0
% o f the total transit
tim e [27]. Based on the above one sees that according to Eq. (3.11), the cutoff fre­
q u e n c y ^ ) is expected to be independent on W E. L E also does not affect the cutoff fre­
quency according to Eqs. (3.11) -(3.12). This is due to the fact that the increase o f C BE and
C BC is canceled out by the corresponding increase o f Ic while the increase o f C BE is can­
celed out by the decrease o f RE + Rc as L E varies.
The maximum frequency o f oscillation (fmax) is obviously affected by the em itter
width (W E) as shown by the following equation.
/
=
lm ‘x
/ / t .=
4 R„C bc
/________________
Al R Bz , ( W E + 2 S EB + 2 W B ) L E
/ td bc
/
Z tD bcW b
^
13)
p d BEs ( W E + 2 S EB + 2 W B )
P
VW B L
_
(3 12)
es(
W e + 2 S eb + 2 W b )L e
ej
where RB is the base resistance, W B is the effective base width related with transfer
length and dB is the base contact length. The fmax-W E dependence can be understood by
the corresponding trends which show that as CBC decreases due to W E decrease fmax
increases. The contribution o f LE is canceled out in the fmax expression and therefore fmax
is independent on LE. The results o f Table 3.1 support these observations.
3.4 Discussion and Conclusions on Basic HBT Trends
This chapter focused on the analysis o f G alnP/G aA s HBTs in term s o f abrupt vs.
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58
graded em itter-base junction design, dependence o f DC current gain on cutoff frequency
and im pact o f em itter size on microwave performance.
The presence o f abrupt o r graded E-B junctions can be evaluated by the ideality factor
o f the base current equation (Eq. (3.1)). A brupt junctions are dom inated by bulk recom bi­
nation (Iu.buik) w hich depends on kT, w hile graded junctions are dom inated by space
charge recombination (IB scr) which depends on 2kT. M easured Gummel plots show
=
1.41 and rig = 2.0 for abrupt and graded E-B junction HBTs respectively. T he ?iB value o f
1.41 indicates that the base currents includes both a bulk recom bination current (lB,buih
k T ) and a space charge recom bination current ( IB scr 2 k T ) com ponent while an r |B value o f
2 .0
suggests that only the space charge recom bination current U b .scp 2 k T ) is present in
graded junction HBTs. C om pared to abrupt E-B junction G alnP/G aA s HBTs, graded E-B
junction devices have larger values o f / S 5cr rather than I b ,bulk com ponents since space
charge recombination is m ore serious in the depleted region and the graded em itter region
o f these devices.
The cutoff frequency (f-p) is independent o f the DC current gain in HBTs w hile fp
depends on the D C current gain for Si BJTs. The m easured cutoff frequencies (fp) of
G alnP/G aA s H BTs with low and high DC current gains were com pared and DC current
gain values o f 70 were found for 5 x 30 p m 2 devices and 35 for 2 x30 p m 2 devices. A
maxim um fp o f 50 G H z w as m easured at VCE = 2.5 V, J^= 29.6 kA/cm 2 for 5 x 30 p m 2
devices and VCE = 2.5 V, Jc = 26 kA /cm 2 fo r 2 x 30 p m 2 devices. The current gain, |H 2 i| o f
the 5 x 30 pm 2 devices is much higher than for 2 x 30 p m 2 devices at low frequency but
alm ost the same at high frequency resulting in the same cutoff frequency. Thus, the DC
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59
current gain affects only the current gain at low frequencies while at high frequencies the
current gain, JH2 j| is affected by param eters such as base and collector transit tim es (xB,
Tc)The effect o f em itter width (W E) and length (LE), 2 x 20, 2 x 30, 5 x 20, 5 x 30 p m 2
em itter stripes on the microwave perform ance, fp and fmax was investigated. As W E
increases from 2 to 5 pm , Jc rem ains alm ost the sam e (30 kA/cm2) and D EB decreases
resulting in a constant value o f xE; D BC is constant since m axim um fp and fmax perfor­
mance is measured before presence o f the Kirk effect. I<^ increases and D EB decreases as
W E increases resulting in the sam e xE for different em itter geom etries. xB and xc are not
affected by W E but depend on the base and collector thickness and diffusion coefficient
which are associated with layer design. The impact o f RE and C Bc com ponents is can­
celed out and rem ains constant as W E increases. Moreover, their effect on xEC is very
small and represents less than 10% o f the total transit time. Overall, the theoretically esti­
m ated t e c value suggests that the cutoff frequency is independent on WE and LE.On the
other hand, the m axim um frequency o f oscillation (fmax) is affected by the em itter width
(W E) since CBC is decreased as W E decreases leading to high fmax. However, fmax does
not depend on LE.
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CHAPTER IV
DESIGN AND ANALYSIS OF
HIGH SPEED G a ln P /G a A s HBTS
4.1 Tunneling Emitter Design of GalnP/GaAs HBTs
4.1.1 Introduction
G alnP/G aA s heterojunction bipolar transistors (H BT) have evolved considerably since
their first dem onstration in M BE and M O CV D technology [9], [93]. Several attractive
advantages distinguish this technology over traditional AlGaAs/GaAs H BTs in terms of
high speed, high reliability (long life), and high pow er perform ance [10], [96], [92], [95].
Recently, high speed ICs for 10~40 G bit/sec. optical com m unication system s using
A lG aA s/GaA s, InP/G aA s as well as G alnP/G aA s H BTs have been dem onstrated [28],
[84]. The high speed perform ance o f such ICs is determ ined by circuit properties but
device speed perform ance also plays a determ ining role. A ttem pts to im prove device per­
form ance include reduction o f the total transit time(Tgc) using different layer designs.
Reduction o f base transit tim e (xB) can for instance be achieved using a graded InGaAs
base [37], w hile the collector charging tim e (Rc C g c) can be decreased using Lateral
Etched U ndercut (LEU ) technology [23]. T h e collector transit tim e can also b e reduced
60
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61
using for exam ple, a p+ subcollector followed by n-collector [29]. The em itter-collector
tim e constant (xEC) contains transit tim e and RC tim e constant term s and can be estim ated
analytically using the follow ing expression.
XE C ~ 2 n f ' t ~ J ^ C B E + C B C ^ + XB + XC + C B C ^ R E + R C ^
where fT is the current gain cutoff frequency o f the device, gm is the transconductance
which is related to the base-em itter resistance (RBE), C BE is the base-em itter capacitance,
C BC is the base-collector capacitance, tb is the base transit tim e, t c is the collector transit
tim e, RE is the em itter resistance and Rc is the collector resistance. Since usually the baseem itter capacitance (C BE) is m uch larger than the base-collector capacitance (C BC), the
first term o f Eq. (4.1) is sim plified to RBEC BE. A trade-off exists in the determ ination of
R b e , C be for high speed perform ance since RBE is decreased as the collector current (Ic )
increases while at sam e tim e C BE is increased. This trade-off im poses a difficulty in reduc­
ing the em itter transit tim e (% ) and thus enhancing the device operation capability. This
section describes the use o f tunneling em itter designs using a thin G alnP layer in order to
achieve best trade-off in the choice o f these param eters and lead to an overall reduction o f
the em itter transit tim e.
4.1.2 Motivation
T he key feature o f th e tunneling em itter design described in this work is the possibility
o f large transconductance (gm) im provem ent through tunneling o f electrons for the sam e
incremental change o f VBE. T his is at sam e time accom panied by a small degradation o f
the base-em itter capacitance (CBE) leading therefore to on overall reduction o f the em itter
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62
transit tim e com pared to conventional designs. T he H B T design calls therefore for satis­
faction o f the following relation.
g
I
s m\
.
Ifnnnf/
-
-
/
= ____ !___ > » |
d V n r* C 9tunnel
BE
/?_ _
.
n BE, tunnel
ftt
.
tconventtonai
_
d
i
= ______ !_____ ( 4 . 2 )
/IV ^ _ Cy conventional
BE
/?_ _
#
BE. conventional
As shown in Sec. 4.1.3 (see derivation o f Eq. (4.4)), this is indeed the case for proper
tunneling em itter designs. Tunneling barriers have been used in a variety o f applications
such as m etal-insulator-sem iconductor silicon solar cells [30] and also in A lGaAs-GaAs
H BTs with a thin 200 A A IGaAs tunneling em itter to improve th e em itter injection effi­
ciency [31]. The tunneling barrier acts as a “ mass filter” and should provide a much higher
ratio o f tunneling probability, a higher em itter injection efficiency, and sm aller series resis­
tance (high transconductance) com pared to conventional designs leading therefore to
im proved microwave perform ance.
The structure investigated in this w ork has a thin tunneling barrier sandwiched
between the n-type em itter and p-type base o f an otherw ise homo-junction bipolar transis­
to r design. The enhancem ent o f em itter injection efficiency is achieved by taking advan­
tage o f the very large difference in the tunneling probability Te an d 7), for electrons (e ’s)
and holes (h ’s) in the barrier layer respectively. Te can be evaluated from the following
expression which gives the probability for elastic tunneling in a triangular barrier under
the W KB approxim ation (W entzel-K ram ers-Brillouin m ethod) [32]:
T e * exp
' 4 7 2 m * (A £
c ) 3 /2
(4.3)
3h q F
w here, r e=tunneling probability, m *=electron effective mass, AE C= E C discontinuity,
F =electric field; approxim ate values fo r Te are derived in Sec. 4.1.3.
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63
A large difference in the tunneling probability for e ’s and h ’s leads the enhancem ent
o f em itter injection efficiency and thus transconductance w hile avoiding degradation o f
the base-em itter capacitance. This results in higher D C current gain, reduced em itter time
constant (Te c ) and thus im proved cutoff frequency o f the device.
4.1.3 Design Considerations o f Tunneling Emitter GalnP/GaAs HBTs
The band diagram s and corresponding electric field o f G alnP/G aA s tunneling
em itter HBTs were sim ulated for different barrier thicknesses (100, 300, 2000 A). The
sim ulated HBTs had an 3000 A thick G aA s em itter, and a G aA s base and collector with
600 A and 7000 A thickness, respectively. The tunneling barrier
( 1 0 0
A and 300 A) was
found to act as an effective “ mass filter” and provided a much higher ratio o f electron to
hole tunneling probability ( Te) than in case o f thick conventional em itter barrier HBTs
A). Fig. 4.1 shows the sim ulated energy band diagram and layer structure for
(2 0 0 0
G alnP/G aA s tunneling em itter H B Ts w ith G alnP barrier thicknesses o f
2 0 0 0
A. In case o f the 300 A and
2 0 0 0
1 0 0
A, 300 A and
A G alnP em itter design HBTs, the corresponding
device structures were grown and fabricated and the device characteristics are described in
next section. Sim ulated electric fields for different barrier thickness are shown in Fig. 4.2.
M axim um electric fields (F) presented in the devices had values o f 55kV /cm and 28kV/cm
fo r
1 0 0
A and 300 A,
2 0 0 0
A G alnP em itters respectively. T he depletion extends in both
the n-G aA s em itter (2 x 10 1 7 cm ‘3 )/n-G aInP em itter (4.5 x 10 1 7 cm*3) region and n-G alnP
emitter (4.5x 1017cm'3)/p-GaAs base (4x 1019cm‘3). The presence of 100A thin barriers
leads in much higher values of maximum electric field that in case of thicker barrier. The
corresponding depletion thickness extends on both sides of the barrier and equals 385A. In
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64
GalnP Emitter
2000AGalnP Emitter HBT
300AGalnP Emitter HBT
100AGalnP Emitter HBT
0.5
-0.5
.GalnP 300A Emil ter
G alnP 2000A Emi ter
e -2.5
G alnP 100A Emil
-3.5
-4.5
0.2
0.4
0.6
0.8
1.4
Distance [pm]
TUnneling
Thickness Type
(A)
GaAs emitter
G alnP emitter
GaAs base
3000
100,
300,
2000
600
GaAs collector 7000
Doping
(cm'3)
n-
2 xlO17
n-
4.5 xlO17
P+
4 xlO19
n-
1.5 xlO16
Fig. 4.1: Sim ulated energy-band diagram s for G alnP/G aA s tunneling em itter HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
65
b
M
120
g1
80
*
60
•a
!3 40
100A GalnP Emitter HBT
,30? r
GalnP 2000A
1 jjs r
w 20
•c
h
S 0
5 -20
1
L .A
GalnP 300.-Y
-40
-60
0.2
c
p•GaAs
100
^
I
b
2000AGalnP Emitter HBT
300AGalnP Emitter HBT
rc
v ;
\ ,
v'
G alnP lOOA
0.25
03
0 35
04
045
03
0 35
0.6
Distance [pm]
Fig. 4.2: Sim ulated electric field for G alnP/G aA s tunneling em itter HBTs.
case o f 2000A thick G alnP em itter design one observes only partial depletion o f the em it­
ter and form ation o f tw o distinct depletion regions, one close to the base-side and the other
close to the n-G aA s em itter side o f the G alnP layer. Since the non depleted G alnP is rela­
tively thick (~15(X)A), no tunneling transport can take place between these tw o distinctly
separated depletion regions.
T he electron tunneling probabilities were calculated for G alnP
1 0 0
A and 300 A
thick G alnP barriers using Eq. (4.3) and the corresponding values w ere found to be
Te=Q. 72 and 0.52, respectively. The total transport rate (Re) can be evaluated as the sum o f
the tunneling probability (Te) and the probability o f transport by therm ionic em ission for
electrons as follows;
R e= Te + (1 - Te)e x p (-A E c /k T ) = 0. 76 f o r 1 0 0 A
R e= 0 .5 8 f o r 3 0 0 A G a ln P e m itte r la y e r
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66
w here A E C is the conduction band discontinuity.
T he collector current density in the presence o f transport through the E-B junction by
tunneling and therm ionic em ission can be expressed using the Ebers-M oll equation as fol­
lows;
Jc = Js l T e +
( 1
- T e) ^ { - t > E c / k B T ) ) [ * M q V BE/ n k B T) - 1]
(4.4)
w here J s is the saturation current density and n is the ideality factor. Eq. (4.4) shows
that at given b ase-em itter (V BE) bias, the collector current density is increased in the pres­
ence o f tunneling com pared w ith operation based solely an conventional, thermionic em is­
sion transport. An estim ate o f the current increase is m ade in the following section. To
obtain full benefit o f the tunneling em itter technology, one needs to com bine the resulting
enhanced current and transconductance capability o f this design together with a small
base-em itter capacitance (CBE). Im proved speed perform ance can in this way be achieved
provided the collector current increase is not accom panied by significant base-em itter
capacitance increase. The variation of C BE w ith current was analyzed experimentally for
the conventional and tunneling em itter designs and the results are presented in section
4.1.6.
4.1.4 Layer Structure and Device Fabrication
T he H B T layers were grow n by reduced-toxicity precursors and proved to be o f high
quality as dem onstrated by m aterial and device characteristics reported previously by the
authors for conventional designs [24]. G roup in atom s w ere provided by TEG a and TM In.
Precracked tertiarybuthylarsine and phosphine (TBA, TB P) and uncracked trisdimethylam inoarsine (tDM AAs) were em ployed as G roup V sources. The em ployed growth
approach resulted in very high level o f reproducibility o f growth param eters and low
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
67
defect density o f 10 def/cm 2. T he tunneling em itter H BT structures studied here is shown
in Fig. 4.1. A thin
1 0 0
A (n+
1
x 10 1 9 cm"3) G alnP etch stop layer w as inserted between
the G aA s collector and subcollector layers. This allow ed reduction o f the base collector
capacitance (CBC) by using the Laterally Etching U ndercut (LEU ) technology discussed
below. To better evaluate the advantages o f the tunneling em itter design and validate the
proposed approach, an abrupt junction G alnP/G aA s conventional H B T was also grown
and fabricated for com parison. T he em itter o f the conventional H B T consisted o f a 2000 A
thick G aA s layer doped n (4.5 x 10 1 7 cm"3), and had identical base and collector layer
designs as the tunneling em itter H B T (see Fig. 4.1).
Self-aligned G alnP/G aA s single H B Ts were fabricated using sim ple all w et based
chem ical etching which m inim ized layer dam age and device degradation. Ti/Pt/Au non­
alloyed m etal was deposited to em itter and collector layers w hile Pt/Ti/Pt/A u was used as
the base metal. A partially Laterally E tched U ndercut (LEU ) technique was em ployed to
decrease the base-collector capacitance (CBc ) while ensuring that the base resistance was
not increased. This LE U process benefited from the presence o f a 100 A thin G alnP etch
stop layer between the collector and subcollector layers. By overetching the GaAs collec­
tor below the base region it w as possible to reduce CBC. T he extrem ely high etching selec­
tivity between G aA s and G alnP perm itted protection o f the subcollector region while
etching the base and collector regions laterally under the base metal. T he G alnP etching
stop layer was rem oved next w ith pure HC1 and Ti/Pt/Au, collector m etal was deposited
after suitable patterning. H B T D C characterization confirm ed at this stage that devices
were operational. T he cross-sectional SEM picture o f a self-aligned H B T is shown in Fig.
2.6 (b). T he base undercut in the em ployed L E U schem e resulted in m axim um base under­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
68
cut o f 0 .5 p m and avoided consequently the increase o f base resistance. This w as possible
due to the fact that the rem aining base layer w idth (~ 1.5pm) exceeded the transfer length
o f the base contact (~ 0.4pm ) and current conduction could therefore take place close to
em itter mesa. Enhancem ent of the m axim um oscillation frequency (fmm) was therefore
possible by com bining the fixed base resistance characteristics with a reduced base-collec­
tor capacitance (C BC).
4.1.5 DC and Microwave Performance
The DC and microwave properties o f the H BTs were obtained by characterizing 2 x
30 p m 2 single em itter finger H BTs in com m on-em itter configuration. O ther em itter geom ­
etries w ere also measured. The I-V and Gum m el characteristics o f the tunneling em itter
HBT are shown in Fig. 4.3. The D C current gain was approxim ately 38 fo r the tunneling
em itter design and 28 for the conventional design. The breakdown voltage (VCEO) was
more than 20V for both designs. T he base ideality factors o f 1.32, 1.56 and the collector
ideality factors o f 1.12,1.27 are obtained for the tunneling and conventional em itter HBTs
respectively.
T he D C current gain was investigated as a function o f device geom etry and the results
are shown in Table 4.1 for the tunneling and conventional em itter HBTs. O verall, the DC
current gain o f tunneling em itter H B T s is higher than for the conventional em itter H BTs.
As the P/A (Perim eter/Area) ratio decreases, the D C gain o f the devices increases due to
the reduced im pact o f surface recom bination effects. M oreover, the D C current gain is
shown to decrease w ith device periphery fo r designs with the sam e area (A =30pm 2) due to
large surface recom bination through th e long periphery.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
69
8
7
—Tunneling Em itter H BT
6
wo»>wowow»mww»
5
Conventional Em itter HBT
4
CJ
/ 4-—
MMNMMMMMM
3
2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
v CE [V]
(a)
le-01
le-02
Tunneling Em itter HBT
le-03
le-04
£» le-05
le-06
Conventional Em itter HBT
le-07
le-08
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VfiE >V c e [V]
(b)
Fig. 4 . 3 : 1-V (a) and gum m el (b) characteristics o f the G alnP/G aA s tunneling and con­
ventional em itter HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
70
Assum ing no surface recom bination, one can estim ate using Eq. (4.4) that the collector
current at VBE=1.5V should be im proved by 210% for the 300A G alnP tunneling em itter
H BT com pared with the conventional em itter HBT. The experimentally observed
im provem ent o f collector current is in fact 180% as seen from the results o f Table 4.1.
The microwave properties o f the HBTs were also investigated using an HP8510B net­
work analyzer from 0.5 to 25.5GH z. The current gain (|H 2 i|2) and M ason’s unilateral
pow er gain (U) versus frequency characteristics were extracted from measured S param e­
ters and are presented in Fig. 4.4 for the case o f best perform ance. Fig. 4.4 (a) shows that
the tunneling em itter device presents a cutoff frequency (fT) o f 58GHz and a M ason’s uni­
lateral pow er gain, m axim um oscillation frequency (fmax) ° f 100GHz at VCE=2.5V, Ic=20
mA. On the other hand, the conventional em itter design H BT shows that a cutoff fre­
quency (f-p) o f 44G H z and a M ason’s unilateral pow er gain, maximum oscillation fre-
Device scale (pm2)
single emitter
DC gain of
Tunneling
Emitter HBT
DC gain of
Conventional
Emitter HBT
P/A ratio
Area (pm2)
2x10
36
30
1.2
20
3x5
38
32
1.07
15
5x10
70
43
0.6
50
5x30
76
45
0.47
150
3x10
54
35
0.87
30
2x15
39
34
1-13
30
1.5x20
32
28
1.43
30
Table 4.1: Com parison o f DC gain between G alnP tunneling em itter design and the con­
ventional HBTs.
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71
2.20
tAAX
100
Frequency[GH z]
(a)
- 6dB/Oct
Frequency[GHz]
(b)
Fig. 4.4: High frequency perform ance o f 2 x 30 ^ m 2 single em itter HBT at Ic = 22 mA,
VCE= 2.5 V. (a) Tunneling em itter design H B T at VCE= 2 5 V’ Ic = 20 m A , (b)
Conventional em itter design H B T at VCE= 2.5 V, Ic = 18 mA.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
72
quency (fmax) ° f 67G H z at VCE= 2.5 V, Ic = 18 mA as shown in Fig. 4.4(b). This
corresponds to an fT increase o f 32% and f , ^ increase o f 49% as a result o f using a tun­
neling em itter design. T he bias dependence o f fT and f ^
is shown in Fig. 4.5. The m axi­
m um fx and fmax reach 4 5 ,7 0 G H z for the conventional em itter H BT and 5 8 ,1 0 0 G H z for
the tunneling em itter HBT. The overall, fx and f , ^ variation o f both designs with bias
w ere found to be very small as shown by the results o f Fig. 4.5. This is due to the absence
o f K irk effect in the range o f Ic bias used for the study ; Ic currents sm aller than 30m A are
necessary for operation o f these H BTs w ith reduced pow er dissipation. This feature is o f
interest for circuit designs and results in circuit perform ance im m une to voltage and cur­
rent variations. The enhanced fx characteristics at high collector current are mainly attrib­
uted to the reduction o f the em itter transit time. fmax o f the tunneling em itter H BT presents
a larger degree o f im provement due to th e additional im pact o f slightly higher base doping
in this design which leads to base resistance reduction.
4 .1.6 Small Signal Parameter Extraction of the Tunneling Emitter
HBTs
The im provem ent o f the em itter transit tim e for the tunneling em itter H B T design
w ere analyzed using sm all-signal equivalent circuit param eters for the HBTs obtained by
equivalent circuit param eter fitting to m easured S-param eters. Table 4.2 shows the small
signal equivalent circuit param eters o f the tunneling em itter and conventional design
H B Ts. T he param eters w ere extracted at the sam e VBE bias o f 1.48V (the closest m ea­
sured VBE value for the conventional design is 1.46V) so that an evaluation o f g m - l / R BE
im provem ent (105% ) through tunneling can be made. T he equivalent circuit param eters of
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
73
no
max
100
Vos (V)
3-5 X-—X---X X
3.0 A — A - A — A
2J
----X
x—
10
12
14
16
18
Ic [mA]
20
22
24
(a)
no
too
Vce(V)
3.5 X—X X X
max
10
12
14
16
18
Ic [mA]
— f
h
20
22
24
(b)
Fig. 4.5: B ias dependence o f fx and
fo r 2x30pm 2 G alnP/G aA s HBTs. (a) Tunneling
em itter design HBT (b) Conventional em itter design HBT.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
74
CBC
rB+*c
t EC
Rb
r be
Rc
*E
Cbe
VBE
fT^Max
Vce^C
Tunneling
37
2.0
2.6
5.4
134
2.7
033
214
1.48
58/100
2.5/20
Conventional
40
2.8
4.1
9.2
2.78
8.2
0.52
134
1.46
39/60
23/12
Conventional
40
2.0
33
8
1.93
7.9
0.51
224
1.55
44/67
2.5/18
Sample
Where R = £1, C = fF, t = psec, fi = DC current gain, ti/rMn = GHz, Ib = nA, Ic = mA, VCE=V
Table 4.2: Equivalent circuit param eters for 2x30pm 2 single em itter H BT between Tun­
neling em itter and Conventional design HBTs.
the conventional H BT w ith best perform ance presented in Fig. 4.4 (b) (V be = 1-55V) are
also given for com parison. The analytical extraction technique reported earlier [105],
[126] was used for the extraction. As expected, the base-em itter resistance (R b e ) >s found
to be sm aller for the tunneling em itter design due to the additional transport m echanism by
tunneling through the thin G alnP em itter barrier. This causes higher em itter injection effi­
ciency and leads to the observed higher DC current gain com pared with the conventional
thick em itter H B T design. RBe changed from 1.93Q to 1.3512 corresponding to a 30%
reduction and 43% im provem ent o f gm. This resulted in a change o f em itter transit tim e
(Te = R be ( c b e + C b c )) front 0.51psec to 0.33psec corresponding to 35% im provement.
Fig. 4.6 shows the C Be and R b e dependence on base-em itter voltage (VBe ) at
V ce= 2.5 V for the tunneling and the conventional em itter G alnP/G aA s HBTs. A s can be
seen, the
r be
values for the tunneling em itter H BT are sm aller com pared w ith those o f
conventional H B Ts w hile the C Be values for the tunneling em itter H BT are higher.
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75
<
S
£
Ic (Collector current
10
300
250
BE
g200
8
I
150
m
S ,o°
2 06
BE
50
« Conventional Emitter
■
0
1.44
1.46
1.48
1.5
1.52
•
■ 'Hinnding Emitter
1.54
1.56
1.58
1.6
VBe M
Fig. 4.6: the relation between C BE and R BE on V BE for the tunneling and the conven­
tional em itter G alnP /G aA s HBTs.
A lthough the C BE o f the tunneling em itter H B T also increases w ith VBE, the RBE decrease
in this design plays a predom inant role, leading therefore to an overall reduction o f the
em itter tim e constant ( t e ). A t VBE= 1.49V, for instance, the RBE for tunneling em itter
design is im proved by 108% (from 2.4 to 1.15&2) while C BE for tunneling em itter design is
increased by 54% (from 162 to 250 fF). T h e extracted em itter transit tim e ( t E = R BE(CBE
+ C Bc ) corresponding to the results o f Fig. 4.6 is m aintained 0.33 psec for the tunneling
em itter design and 0.51 psec for the conventional em itter design H BT over the entire range
o f investigated base-em itter voltage (V BE); the CBC value used fo r
te
estim ation was at
this bias 40fF. T he tunneling results therefore in RBE and an overall reduction o f the em it-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
76
3
300
Conventional Emitter
• Turmdinj Emitter
2.5
250
m
Se ’
S
gl.5
TeS
100 «
8m
S
'
0.5
0
12
14
16
18
20
22
24
Collector current [Icl
Fig. 4.7: the relation between C BE and RBE on Ic for the tunneling and the conventional
em itter G alnP/G aA s HBTs.
ter transit time. Moreover, the increased C BE values at high V BE bias are com pensated by
the R b e reduction leading therefore to
t e
values which are bias independent.
Fig. 4.7 illustrates the CBE and transconductance (gm) dependence on collector current
(Ic) at V c e =2.5 V for the tunneling and the conventional em itter G alnP/G aA s HBTs. The
extracted collector ideality factor from Fig. 4.7 using gm (= qlc/nkT , w here n is the ideal­
ity factor) is 1.09, 1.29 for the tunneling em itter and conventional H B Ts respectively.
T hese values are very close to the m easured collector ideality factor from the Gum m el plot
o f Fig. 4.3 (b). As can be seen, the C BE for the tunneling em itter H B T is low er than for the
conventional design at sam e collector current since lower base-em itter voltage is needed
for the tunneling em itter H B T to achieve the sam e am ount o f collector current. This leads
in sm aller CBE for the tunneling em itter design H BTs at sam e collector current. The
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
77
obtained results agree with the perform ance expected based on Eq. (4.3), (4.4) and dis­
cussed in Sec. 4.1.3.
4.2 Composite Em itter Design of GalnP/GaAs HBTs
4.2.1 Introduction and Basic operation Consideration
For long-haul optical com m unication system s, ultra-broadband, high bit rate front-end
transim pedance amplifiers are needed. 40G b/sec-class ICs using A lG aA s H BTs have
already been dem onstrated [33], [34]. G alnP/G aA s Heterojunction B ipolar Transistors
(HBTs) grown by M OCVD have been first dem onstrated by the authors [93] and this tech­
nology is currently accepted as a superb alternative to A lG aA s/G aA s H B Ts due to the
absence o f Al, the excellent etching selectivity and better reliability characteristics [35],
[84]. M onolithic broadband G alnP/G aA s H BT transim pedance am plifiers having a band­
width (BW ) o f 19 G Hz have been dem onstrated by the authors and their large signal, as
well as, a high gain perform ance have been reported [95], [104]]. Excellent microwave
perform ance o f f p s 140 G H z and fmax= 230 GHz has been achieved using G alnP/G aA s
H BTs [28], and Chem ical Beam Epitaxy (CBE) using TB A /TB P precursors has been
reported for growth o f G alnP/G aA s devices [24]. H igh speed m icrowave perform ance o f
G alnP/G aA s H B Ts can be achieved using various designs such as tunneling em itter [36],
strained InG aA s base [37], and collector undercut [38]. A com m on lim itation in high
speed perform ance o f H BTs has been their relatively large base-em itter capacitance (CBE)
which results from lim ited m obile carrier transport and thus charge accum ulation in the
em itter region [39]. The use o f lightly doped em itter w ith 5-doping w as reported to reduce
CBE at low current density [40] but this does not resolve the problem at high current den­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
78
sity w here C BE is considerably increased. As expected, a trade-off exists in the relation
between R BE and C BE for high speed perform ance since R BE is decreased as the collector
current (Ic) increases while at sam e tim e C BE is increased. This trade-off im poses a diffi­
culty in reducing the em itter transit tim e (Tg) and thus enhancing the device microwave
perform ance. T he em itter transit tim e o f an H B T can be estim ated analytically using the
following expression.
kT
%E ~ ^
x
kT (
'e
CB E + CB C ) -£ 7 7
“
b e
+ Ci
(4.5)
BC.
where xE is the em itter transit tim e o f the device, kT/qJc is the transconductance, CBE is
the base-em itter capacitance, C Bc is the base-collector capacitance, Qe is the electron
charge in the em itter region. Since usually the base-em itter capacitance (CBE) is much
larger than the base-collector capacitance (C BC), the first term o f Eq. (4.S) is sim plified to
r
BEc BE- M obile carrier transport takes place in conventional em itter HBT designs by dif­
fusion and results in charge accumulation in the em itter and thus increased C BE. In this
work, a com posite A lG aA s/G alnP em itter design was em ployed to reduce the im pact o f
this effect follow ing the approach originally reported by [41]. W hile the im proved H BT
perform ance presented in [41] was only show n theoretically, first experim ental results on
H B Ts designed w ith this approach were dem onstrated by the authors [126] and further
theoretical and experim ental validation o f this concept is described in this work.
In the design presented here, a com positionally graded AlGaAs layer form s an electron
launcher at the interface w ith the G alnP layer, which injects the electrons at a high kinetic
energy tow ards the rem aining part o f the em itter. It leads to lower free carrier concentra-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
79
tion (Qe) and sm aller C BE com pared to a conventional em itter design approach, even
under high current operation conditions. The low free carrier concentration in the em itter
is achieved w ithout any transconductance degradation, due to the high electron velocity in
th e electron launcher region. As a result, an overall perform ance im provem ent com pared
to conventional em itter design is achieved. This w ork provides an analysis o f the em itter
and total delay tim es in H BTs and dem onstrates the advantages o f using electron launcher
region in the em itter for reduction o f these delay times. Theoretical and experim ental veri­
fications o f the im proved delay tim es are shown using M onte Carlo simulation and
through device characterization and small-signal modeling. Furtherm ore, it is shown that
the reported com posite em itter H B T design using the A lG aA s/G alnP approach achieves
reduced C BE and im proved high frequency performance over a broad collector current
range.
4.2.2 Monte Carlo study of the composite em itter design
G raded A lG aA s-G alnP com posite em itter design H B Ts w ere studied using M onte
C arlo simulations. A s discussed earlier, the graded AlGaAs layer introduced in the com ­
posite em itter design is im portant fo r reducing the em itter charging tim e ( te ). This layer
form s an electron launcher at the interface with the G alnP layer as shown in Fig. 4.8 (a).
T h e launcher injects electrons into the G alnP region with elevated kinetic energy. This
ensures high-energy electron transport through the G alnP em itter and results in overshoot
velocity before carriers start being injected into the base, leading to a low er free carrier
concentration in the em itter and thus low er te . The role o f G aln P em itter layer in the com ­
posite em itter structure is to block the holes from back-injecting into the em itter and sepa­
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
80
rate the launcher from the base, giving a reduced em itter-base capacitance (CBE). Fig. 4.8
shows the energy-band diagram s and layer structure o f G alnP/G aA s com posite (a) and
conventional (b) em itter design H BTs studied in this work. In case o f the G alnP/G aA s
conventional em itter design HBT, a 800A thick G alnP em itter layer is added to allow
com parison with A lG aA s-G alnP com posite em itter design H B Ts o f sam e overall em itter
thickness. Since the energy separation between the T band and L band in G alnP is small
(A EpL=0153eV), the A1 com position (x) at the A lG aA s-G alnP interface m ust be chosen
properly to avoid intervalley scattering.
In this study, an A1 com position (x) o f 0.22 w as chosen to prevent the intervalley scat­
tering. This com position yields an electron launcher with a height o f 0.125eV. Fig. 4.9
shows the electric field (a) and electron density (b) versus distance profiles for G alnP/
G aA s conventional and A lG aA s-G alnP com posite em itter design HBTs. Compositionally
graded AlGaAs em itter H BTs have m uch stronger electric fields present in the emitter. A
m axim um value o f 40kV /cm is for exam ple observed within the A lG aA s region o f the
com posite design while no electric field is present in the em itter o f the conventional
design. The corresponding electron density is therefore dram atically decreased due to the
presence o f a drift velocity com ponent in this region o f the emitter. O n the other hand,
G alnP conventional em itter H BTs do not have a built-in electric field w ithin the em itter
region and the electron density in this case is increased due to slow transport o f carriers
and thus carrier accum ulation. T he enhancem ent o f the drift velocity using the com posi­
tionally graded A lG aA s design can be better understood from the results o f Fig. 4.10. This
figure focuses on the velocity characteristics responsible for th e im proved frequency char-
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
81
graded AlGaAs n-GalnP
>A
y^p-GaAs
n-GaAs C
n-GaAs
0.2
0.4
0.6
0.8
1.2
D ista n ce [pm]
(a)
n-GalnP
p-GaAs
n-GaAs C
0.5
0.4
0.6
0.8
1.2
D ista n ce [pm]
(b)
Fig. 4.8: Energy band diagram s o f G alnP/G aA s conventional (a) and com posite em itter
design H BTs (b).
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82
aic .> i|
n .in P | Comptxilc emitter
GalnPE | Comrcnlioaalemitter
120
„ 100
Emitter
Collector
g
^ 80
A 60
■8
3 40
to
"
i
Vce=3V
Vbe=1.43V
Gafn^
20
Conventional Emittei
o
-20
"**8.25
0.3
GalnP-AlGaAs
Composite Emitter
0.35
0.4
0.45
0.5
Distance [pm]
0.55
(a)
AIGaAij GalnP | Compoaile cmillcr
GalnP E
ConraitkHial emitter
Emitter
Collector
VCE=3V
Vbe=1.43*
G alnP
Cbnventidnal Emitter
^GalnP-AlGaAs
Composite Emitter
0.35
0.4
0.45
Distance [pm]
0.5
0.55
(b)
Fig. 4.9: Com parison o f electric field (a) and electron density profiles (b) for G alnP con­
ventional and A lG aA s-G alnP com posite em itter design H BTs
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
83
AIGaAfl GalnP
l
1
u
'o
Compodtc design
CowtnUonal design
0.8
VCE=3V
Vbe=I.43V
0.6
AlGaAs-GalnP
Composite Emitter
*
1
J
0.4
e
GalnP
Conventional E n i t t i
s 0.2
«»
Si
u
0.25
0.3
0.35
0.4
0.45
0.5
0.55
Distance [pm]
Fig. 4.10: Com parison o f electron velocity profiles for G alnP conventional and A lG aA s
G alnP em itter design HBTs in the com posite em itter region.
acteristics described in the work. In case o f the com posite em itter design, the electron
velocity is high due to the drift velocity com ponent in the special em itter region. O n the
contrary, the electron velocity o f the conventional em itter design is slow er than for the
com posite em itter design since diffusion carrier transport is dom inant in the em itter region
which consists only o f GalnP. O ne sees from these sim ulations that C BE for the com posite
em itter design H B T is expected to be sm aller than for the conventional em itter H BT due to
the stronger electric field in the com posite em itter region. This leads to reduced te (AQg/
AJC) w hich is an im portant param eter in determ ining the cu to ff frequency fj-=l/TEC w here
te c
is s iven by;
t £C = T£+ tb + tc + C bc J?c
(4.6)
and t e can be evaluated from xE ~ ^ Q ^ ^ J c - C b ERbe- An estim ate o f t e for the tw o
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84
designs using M onte Carlo sim ulation (from Fig. 4.9(b) and Fig. 4.11) showed values o f
0.13ps and 0.57ps for the com posite and conventional design respectively proving the
superiority o f the former.
The theoretically expected carrier density values for designs em ploying the sam e con­
cept can be found in Fig. 4.11. The thickness and doping concentration (800A vs. 2000A
and 5 x l0 1 6 vs. 3 x l0 1 7 cm ’ 3 for com posite and conventional em itters respectively) o f the
em itter layer em ployed in this sim ulation are correspond to those o f the fabricated HBTs.
As shown in the inset o f Fig. 4.11 (a), the increase in the free electron concentration (AQ e)
at the base-em itter junction o f the com posite em itter design due to VBE increase is small,
w hereas the AQ e increase in the conventional design (see the inset o f Fig. 4.11 (b)) is sig­
nificant. The difference in the AQ e values is again due to the presence o f a stronger electric
field and thus higher electron velocity in the vicinity o f the base-em itter junction o f the
com posite em itter design com pared to the conventional design.
4.2.3 Layer Structure and Device Fabrication
T he G alnP/G aA s H B T layers w ere grown by CB E using reduced toxicity precursors
such as TBA, TBP. The details o f th e growth technique and material characteristics were
described by the authors [24], [23]. T he com posite em itter H BT design consists o f a com positionally graded 5 x l0 1 7 cm ’3, 380A thick AlGaAs (A1 :
0
->
0
.2 2 ) layer follow ed by
undoped 100A thick G alnP w hich serves in reducing the spike created in the conduction
band o f the A lG aA s-G alnP heterointerface. A 400A thick n ( 5 x l0 1 6 cm*3) G alnP em itter
layer is used below the undoped G alnP and a 500 A G aA s base doped p +
( 6
x 101 9 c m '3),
and a 7000 A GaAs collector n- (1.5 x 10l 6 c m '3). To better evaluate the advantages o f the
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85
GaAs E
S
u
90
e*■<
0.8
u 0.6
fi
.2 0.4
fca
W 0.2
0.2
0.25
0.3
0.35
0.4
0.45
Distance [pm]
0.5
0.55
0.6
GalnP Emitter
■
S
u
00
•©
1.2
1 p* ••
rrssl
I
441017
\
)4l0'7
1
2.io'7
|
mo17
00
o
VB E = * « jU ^
046
*s
|
VBEal.6V
044
GalnP E
0.6
0.3
032
034
I
'
0.5
0.55
!
u
41
u 0.4
es
U
0.2
0.2
0.25
0.3
0.35
0.4
0.45
Distance [pm]
0.6
(b)
Fig. 4.11: B ias dependence o f free electron carrier density for the com posite (a) and the
conventional (b) em itter design HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
86
com posite em itter design and validate the proposed approach, an abrupt junction G alnP/
G aA s conventional H BT was also fabricated for com parison. T he em itter design o f the
conventional H B T consists, starting from the em itter cap, o f an n+ ( l x l 0 1 9 cm*3) GalnP,
700A thick layer followed by 2000A thick G aln P emitter doped n (3 x 1017cm*3), a 600 A
G aA s base doped p + ( 4 x
1 0 19
cm*3), and a 7000 A G aA s collector n- (1.5 x 10I6 c m '3).
The em itter doping and thickness (3 x 10 1 7 cm*3, 2000A ) o f the conventional H BT were
optim ized for sufficient DC gain and high frequency perform ance. A com m on design fea­
ture o f the tw o H B T structures is a G alnP etch stop layer between the GaAs collector and
subcollector. This can be used to form a laterally etched undercut and leads to reduction of
the C BC capacitance and thus cutoff frequency as well as m axim um oscillation frequency
enhancem ent [23]. Self-aligned H BTs w ith single 2 x 3 0pm 2 em itter fingers were fabri­
cated on the above layers and a photograph o f a device before airbridge metal realization
is shown in Fig. 4.12. The key process features are as follows; Ti/Pt/A u non-alloyed em it­
ter and collector ohmic contacts; Pt/Ti/Pt/A u non-alloyed base contacts, G aln P em itter
etch by HCI and pillar/airbridge fabrication using Ti/A l/Ti/A u. G aA s collector undercut as
necessary for reducing C BC was achieved by a w et etching solution consisting o f NH4OH
: H 2 O 2 : H 2 0 . A cross-sectional view o f a com pleted H B T with laterally etched undercut
can be found in a previous report by the authors [23].
4.2.4 DC and Microwave Performance
The D C characteristics o f 2 x 30 pm 2 single em itter finger H BTs with the com posite
and conventional em itter designs were m easured using an H P4145B sem iconductor
param eter analyzer. Fig. 4.13 shows the I-V characteristics o f the fabricated 2 x 30 p m 2
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87
C ollector
^
E m itter
^
B ase
Fig. 4.12: SEM picture o f the fabricated 2 x 30pm 2 single em itter G alnP/G aA s HBT.
single em itter finger G alnP/G aA s HBTs for the com posite and conventional em itter
devices. A DC gain o f 30 and 28, base ideality factors o f 1.74, 1.82 and collector ideality
factors o f 1.15,1.18 and a collector-em itter breakdown voltage o f above 17 V are obtained
for the com posite em itter and conventional em itter device respectively.
The microwave properties o f H BTs were m easured in com m on-em itter configuration
using on w afer tests and an HP8510B network analyzer. The current and pow er gain ver­
sus frequency characteristics o f the com posite em itter H B T are shown in Fig. 4.14. The
current gain cutoff frequency (fT) extrapolated from the m easured |H 2 i| using a
-6
dB/Oct.
slope rule w as 62 G H z for the com posite em itter design HBT, and 45 G H z for conven­
tional em itter design HBT. T he m axim um oscillation frequency ( f , ^ ) from M ason’s uni­
lateral gain (U) was 72 G H z at VCE= 2-0 V, Ic =18 mA for the com posite em itter design
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88
6
5
4
0
0
0.5
1.5
2
2.5
3
3.5
4
VCe M
(a)
0
0.5
1
1.5
2
2.5
3
3.5
4
v Ce M
(b)
Fig. 4.13: DC characteristics o f com posite em itter (a) and conventional em itter (b)
design HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
89
35
30
25
20
6
■fiST
d B /O ct
15
10
100
Frequency[GHz]
S 20
6
d B /O ct
max
> Simulated
-
Measured
Frequency[GHz]
100
(b)
Fig. 4.14: M easured and sim ulated microwave perform ance o f com posite em itter (a) and
conventional em itter (b) design HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
90
and 55 G H z at
2.0 V, Ic = 18 m A for the conventional em itter design. C om parison o f
the m icrow ave perform ance o f the com posite em itter and the conventional em itter design
shows that the fT o f the com posite em itter design is by 38% higher. fT and f , ^ were also
evaluated from the sm all-signal H B T equivalent circuit param eters and the results are also
shown in Fig. 4.14. The fT, f , ^ values found using this approach were 63G H z and
120GHz for the com posite em itter design and 45 and 60G H z for the conventional em itter
design respectively. Although the fmax o f the com posite H BT obtained from this technique
is higher than the one obtained by extrapolation (120G Hz vs. 72G Hz), the overall trends
are the sam e and dem onstrate the superiority o f com posite em itter HBTs.
Fig. 4.15 shows bias dependence o f fT and f ^ ^ as a function o f collector current for the
two design H BTs. In case o f the com posite em itter design, the peak fT and fmax are 63
GHz at V c e = 2 V, Ic = 21.5 m A and 84 G H z at VCE= 3 V, Ic = 20 m A respectively. The
enhanced fT characteristics at high collector current region obtained for com posite em itter
HBT (Fig. 4.15 (a)) are due to its overall sm aller C BE value. The higher fT o f the com pos­
ite em itter HBTs at low Ic appears to be related to their sm aller CBE which results from
the low er em itter doping concentration in the com posite em itter H B T (n = 5 x l0 1 6 vs.
n = 3 x l0 17). It will be analyzed and discussed in m ore details in the next section.
4.2.5 Device Analysis and Discussion
The H B T sm all-signal equivalent circuit param eters w ere directly extracted from m ea­
sured S param eter data using an in-house analytical extraction technique based on a tech­
nique that was previously reported [105]. T he total delay tim e (xEC) an d forw ard transit
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91
100
VCE(V)
to X
X
X
X
is
■—■—•
■
2 .0 ■
»—■» <----»
max
S'
60
40
10
12
14
16
18
20
22
24
Ic [mA]
(a )
100
3. 0 A
,
2.5 ■ —
▲— A
■
2.0
▲
X
max
x10
12
14
16
18
20
22
24
Ic [mA]
(b)
Fig. 4.15: B ias dependence o f microwave perform ance o f com posite em itter (a) and con­
ventional em itter (b) design H BTs
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92
tim e (t f = x B + t c ) w ere calculated analytically from the im pedance block elem ents o f the
H BT equivalent circuit. The relations below summarize the approach used [39], [105]:
[ Z 1 2 “ Z2 1 ]
XE C ~ XE + XB + XC + X C = a n g [ z ~ 2 - Z 2 l ]
1
R e[aZ ffC ]
XF = XB + X< r
where
xe
(4 7 )
~ R B E ^ C B E * C B c }'
1
x c
(4.8)
~ c b c ^r e + r c ^
and Zy is an im pedance m atrix, Z BC is the im pedance value o f C Bc , a is the base trans­
port factor and Tp is the forw ard transit time.
The calculated
t e c ,t f
as function o f frequency from the extracted small signal param e­
ters are shown in Fig. 4.16. In case o f the com posite em itter design, a t e c of 2.33 psec, a
tf
o f 1.8 psec were achieved w hich leads to an em itter delay tim e ( t e = xEC - Tp - x’c ) of
only 0.22 psec; x’c = C b c (Re + Rc ) was in this case 0.31 psec. On the other hand, the
total delay tim e (xEC) o f the conventional em itter design was 3 psec w hile its forward tran­
sit time (Tp) was 1.8 psec. T he resulting em itter delay tim e (xE) for the conventional em it­
ter design w as consequently 0.62 psec. These results indicate that the em itter delay tim e o f
the com posite em itter design leads to enhancem ent o f cutoff frequency which in the case
o f the tested devices is o f the order o f 13%. The C BE and fp dependence on
m anifests
distinct features for com posite and conventional em itter designs as shown in Fig. 4.17 for
a 2x30|iim2 single em itter device. In particular, the CBE o f com posite em itter H BTs is sig­
nificantly low er than that o f conventional em itter designs and presents a w eak J c depen-
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93
5
CE=
4
.1 mA
sM 3
Q.
¥
I 2
0
5
10
15
20
25
30
Frequency[GHz]
(a)
5
single emitter
1 8 .3 m A
4
V
0
5
10
IS
20
25
30
Frequency[GHz]
(b)
Fig. 4.16: Comparison o f delay tim e o f com posite em itter and conventional em itter
design HBTs.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
94
70
350
*
300
200
150
IdllaaO
250
100
5
10
15
20
25
lc [mA]
(a)
350
300
200
F 30
150
100
5
10
15
20
25
lc [mA]
(b)
Fig. 4.17: C om parison o f CBE and fT characteristics with collector current.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
[dl]aaO
250
95
14
350
•*-------- « Composite Emitter
12
300
• --------■ Conventional Emitter
10
250
cF
200 8
I s
1
150 g
6
$
4
100
BE
2
0
5
15
10
20
25
Collector current [Ic]
Fig. 4.18: C BE and R BE dependence on Ic for the com posite and the conventional em itter
G alnP/G aA s HBTs.
dence. This feature is representative o f the com posite em itter design and as expected from
theory leads to enhanced fT perform ance.
Fig. 4.18 illustrates that the CBE and R BE on collector current (Ic) at VCE=2 .0 V for the
com posite and the conventional em itter G alnP/G aA s HBTs. As expected, C BE for the
com posite em itter H B T is reduced by 55 ~ 77% com pared with the conventional em itter
H BT since the electron carrier density is dram atically decreased due to the high drift
velocity in this region o f the emitter. O n the other hand, R BE is a function o f collector cur­
rent (Ic) and has sim ilar values for both designs over the entire range o f investigated col­
lector currents.
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96
4.3 Improved High Speed o f GalnP/GaAs DHBTs
4.3.1 Introduction
D ouble H eterojunction B ipolar Transistors (D HBTs) em ploy w ide-bandgap sem icon­
ductor materials for the em itter and collector and present ideally sym m etrical operation
which leads to circuit flexibility. B ecause o f their unique structure, D H B Ts have several
advantages over conventional designs. A key advantage o f D HBTs is their high pow er
potential [42] which is due to the use o f a wide bandgap material for collector and thus
possibility of sustaining higher electric fields (Ebr=650kV /cm for G alnP vs. Ebr=400kV /
cm for GaAs for a value o f ionization coefficient equal to 104 cm _1). This leads to high
operation voltage BV C E 0 values typically o f ~ 25V for GaAs DHBT vs. 17V for GaAs
SHBT. T he sym m etrical structure between em itter-base and base-collector also leads in a
very small offset voltage (V0 ffset) (0.03V ) which makes them useful for m odem wireless
com m unication system s with low voltage supply and high PAE.
In addition to reduced V o f ^ values, DHBTs are also better suited for integrated circuit
applications than single heterojunctions. They present suppression o f hole injection from
base into collector in digital sw itching transistors under conditions o f saturation and em it­
ter/collector interchangeability [43].
G alnP/G aA s H B T s have a sm aller conduction-band and larger valence-band disconti­
nuity
(AEc=0.03~0.12eV,
AEv =0.24~0.4eV )
com paring
to
A lG aA s/G aA s
H BTs
(AEc=0.25eV, AEv =0.13eV ). This leads in im proved electrical perform ance fo r SHBTs
but also DHBTs. T h e sm all conduction-band discontinuity (spike) at the heterointerface o f
base-collector region can, however, disturb the electron transport and result in low current
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97
gain. In addition, the effective collector charging time can be increased due to captured
electrons at this spike and the high frequency perform ance can consequently be degraded.
M any attem pts have been m ade to reduce this unintentional conduction-band discontinuity
at the heterointerface [45], [46], [47], [48], [52], [6 8 ], These include doped GaAs, graded
G axIni_xP and G aA s/G alnP com posite spacers. Am ong them , G aA s spacer designs were
explored from the point o f view o f both DC and high frequency characteristics [47], [48],
[52], w hile graded G axIni_xP spacer H BTs were simply suggested as a possible design
alternative [6 8 ]. M oreover, in case o f constant com position G aA s/G alnP com posite spacer
designs only D C characteristics were reported [47]. This section describes a com plete
study o f the design, process and D C, as well as high frequency experimental characteris­
tics o f a new design alternative em ploying doped G alnP spacer. The investigated design
allow s reduction of the discontinuity at the base-collector interface and led in excellent
high frequency perform ance and breakdown voltage for these DHBTs for the first time.
The doped G alnP spacer leads to a significant spike reduction and improves consider­
ably the electron transport from the base to collector. A lthough this approach presents
advantages in terms o f transport properties, it requires very precise doping control from
the low doped collector region (~1.5 x 1016) to the doped G alnP spacer (1.5 x 1018).
M oreover, excessive values o f spacer doping m ay cause Zener breakdown in the base-col­
lector junction. The advantage gained in term s o f speed appears, however, to be m ost
im portant com pared w ith the com prom ise m ade in term s o f other features.
W hile G alnP collectors offer im proved breakdown properties, they also limit the high
frequency perform ance o f D H B Ts due to the low saturation velocity (4 .4 -8 .0 x l0 6 cm /s)
in G alnP vs. GaAs (8 .0 ~ 1 0 .0 x l0 6 cm /s) [49], [50]. This effect can, however, to som e
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98
Thickness
Doping
GalnAs emitter cap
300
5 x l0 18
GalnAs grad 0 -> 0.5
250
5 x l0 18
GaAs emitter contact
1000
5 x l0 18
GaAs emitter
2000
3 xl017
GalnP emitter
300
4.5x10*7
GaAs Base
600
4.0xl019
GalnP
100
I.5xl018
GalnP collector
5000
3x1016
GaAs subcollector
7000
SxIO18
Table 4.3: L ayer structure o f G alnP/G aA s D H B T s with 100A highly doped G alnP spacer
layer.
extent be com pensated by em ploying an advanced collector undercut technology as
described in this section in order to reduce the base-collector capacitance (C bc )-
4.3.2 Layer Structure and Device Analysis
Table. 4.3 shows a cross section o f the G alnP/G aA s D H B Ts studied in this work. A
100A thick doped G alnP spacer (1.5 x 10 1 8 cm*3) w as em ployed between the G aA s base
and G aln P collector. A 300A G aln P tunneling em itter layer was used to improve the DC
current gain, as already described by others and the authors [31], [51]. The collector dop­
ing w as 3 x lO 1 6 cm*3.
The energy-band diagram s, D C characteristics and m icrowave perform ance of the
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99
D H B Ts described in this w ork were evaluated using the TM A -M ED IC I simulator. A com ­
parison w as also perform ed with respect to the G aA s spacer approach which is another
possibility for designing DHBTs. The tw o designs were identical except for the spacer.
Fig. 4.19 shows the energy-band diagram s o f the D HBTs. A 100A G alnP spacer (DHBT
A ) and 50A G aA s (1.5 x 10 1 6 cm ‘3) spacer (D H B T B) were em ployed in the simulations;
the G aA s spacer design resem bled th e one reported by J.-I. S ong e t a l [52]. A significantly
large spike is present between the base and collector for D H B T B w hile this spike is con­
siderably reduced using a doped G aln P spacer for D H B T A. Sim ulated characteristics
show no difference D C and microwave perform ance between 50A and 100A G alnP spacer
designs. Thus, best perform ance can be obtained w ithout unnecessarily going to smaller
thickness as in case o f G aA s spacer designs [52].
Fig. 4.20 shows the sim ulated DC gain for various spacer designs as a function of V BE
voltage. In case w here no spacer is used, the D C gain is less than one due to the presence
o f a large conduction band discontinuity at the B-C junction. M oreover, the DC gain o f the
100A doped (1.5 x 10 1 8 cm ‘3) G alnP spacer D H B T is much larger than that o f the 50A
G aA s (1.5 x 10 1 6 cm*3) spacer design. As shown by the corresponding conduction band
diagram for each design, this is due to the enhanced reduction o f the conduction band dis­
continuity (A Ec) at the B-C junction in case o f doped G alnP spacer D H BTs. This suggests
the interest in a design o f this type w hich is the subject o f the w ork described in this sec­
tion. T h e experim ental results presented for these devices address their DC but also their
high frequency characteristics and extend previous studies w hich w ere lim ited in num eri­
cal m odeling and D C characteristics o f G aA s [46], [53], [55] and com posite G aA s/G alnP
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100
6.0
VBE>1.4V,Veea2.8V
4.0
0.0
-
2.0
QaAa E
QalnP E
0.2
QalnPC
0.4
0.6
0.8
D istan ce [pm]
6.0
Vbe=1.4V, Vce- 2 8 V
4.0
5 2.0
*
0.0
-
2.0
inPE
QalnP C
-4.0
0.2
0.4
0.6
0.8
D istan ce [pm]
Fig. 4.19: Energy-band diagram s for D H B Ts with G alnP (a) and GaAs (b) spacers.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
101
GalnP spacer
_____ a —
CO.
GaAs spacer
No spacer (Abrupt Junction)
Fig. 4.20: The sim ulated DC gain with various spacers; no spacer, G aA s and G alnP
spacers.
[47], [55] spacers. As m entioned earlier, microwave characteristics o f D HBTs were exten­
sively investigated for G aA s spacer design but not for other spacer approaches. A sim ula­
tion o f their high frequency characteristics showed that their current gain cutoff frequency
(f-p) and m axim um oscillation frequency (fmax) are 17 G H z and 45 G H z respectively
(DHBT B). The corresponding values for fT and f ^ ^ o f doped G alnP spacer designs
(DHBT A) were 30 G H z and 80 GHz. Thus, the design investigated in this work presents
interest both from the point o f view o f superior DC but also high frequency performance.
D H B Ts with a doped G alnP spacer were also studied experimentally. Layers for these
devices w ere grown by M etaloiganic Chem ical Vapor Deposition (M OCVD). Self-aligned
G alnP/G aA s D H B Ts w ere fabricated using simple all w et based chem ical etching which
minimizes layer dam age and device degradation. Ti/Pt/Au non-alloyed m etal was depos­
ited to the em itter layer w hile Pt/Ti/Pt/A u was used as the base metal. A partial collector
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102
undercut technique was em ployed to decrease the base-collector capacitance (CBC) while
ensuring that the base resistance was not increased. The technique benefited from the pres­
ence o f a G aA s subcollector etch stop layer below the G alnP collector. By overetching the
G alnP collector below the base region it w as possible to reduce C B£. The extremely high
etching selectivity between G aln P and G aA s, perm itted lateral etching o f the G alnP col­
lector and spacer under the base m etal w ithout attacking the G aA s subcollector. Etching of
the G alnP collector and spacer w as lim ited to the “extrinsic” base-collector region and
w as possible using pure HC1. N i/G e/Au/Ti/Au metal was em ployed for collector contact
following patterning.
Unlike the collector etching profile o f G alnP/G aA s SH B Ts [23], collector etching in
the [010] direction o f D HBT is m uch faster than in the [010] direction. As can be seen
from Fig. 4.21 (a), the collector undercut technique can not be used in DHBTs when the
em itter fingers are aligned in the [011] direction. By designing the em itter fingers in the
[010] direction it is possible to achieve com plete undercut o f the D H B T collector (Fig.
4.21 (b)) and obtain reduced C g c values.
4.3.3 Results and Discussions
T he D C and microwave properties o f the D HBTs were obtained by characterizing 5 x
40 p m 2 single em itter finger devices in com m on-em itter configuration. The I-V character­
istics o f the D H B T are shown in Fig. 4.22. T he offset voltage (Voffset) was 0.03V due to
the sym m etric heterostructure design o f the em itter-base and base-collector junction.
R eported Voffset values for D H B Ts exceed the value obtained in this work; Voffset = 0.3 V
for 50A G aA s (3 x 1016cm'3) spacer [52], 0.18 for 100A G aA s (1 x 1018cm*3) [42], 0.3V
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
103
Fig. 4.21: Etching Profile o f G alnP/G aA s D H B T s along [O il] and [010] directions.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
104
25
S ta rt: 0 mA
20 S to p : 1.8 mA
S te p : 0.2 mA
15
5
0
0
1
2
3
5
4
Vc e M
Fig. 4 .2 2 :1-V characteristics o f the G alnP/G aA s D H B T with doped G alnP spacers.
for no spacer [53]. A D C current gain o f 12, base ideality factor o f 1.30 and collector ide­
ality factor o f 1.04 were obtained. The breakdow n voltage (BVCE0) exceeded 26V which
is higher than the previous results (B VCEO=22V for [52]).
The microwave properties o f the D H B Ts were m easured in com m on-em itter configura­
tion using on w afer tests and an H P8510B netw ork analyzer from 0.5 to 25.5GHz. The
current gain (|H 2 i |2) and M ason’s unilateral pow er gain (U) versus frequency characteris­
tics w ere extracted from m easured S param eters as shown in Fig. 4.23. The current gain
cutoff frequency (fT) extrapolated from the m easured |H 2 i| using a
-6
dB/O ct. slope rule
was 28 GHz. The value corresponding to f , ^ from M ason’s unilateral gain was 63 G H z at
VCE= 4.0 V, Ic = 51.5 mA. The collector current bias dependence o f fT and f , ^ is shown
in Fig. 4.24. M axim um f j and f , ^ reach state o f the art values o f 33 G H z and 63 G H z
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105
'5 10
(63 GHz)
(28 GHz)
fT
max
100
Freq. [GHz]
Fig. 4.23: High frequency perform ance o f 5 x 40
DHBTs at VCE= 4 V, Ic = 51.5 mA.
70
60
p m 2 single em itter G alnP/G aA s
SV: X X X X
4V: ■— ■— ■—■
3V : A
a
a
▲
max
20
10
30
35
40
45
50
55
60
Ic [mA]
Fig. 4.24: B ias dependence o f fp and fmat as a function o f collector current for the
G alnP/G aA s D H B T w ith doped G alnP spacer.
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106
respectively. Previous reports presented fmax values o f 75G H z at Jc = 150kA/cm2,
VCe = 2V for DHBTs with G aA s spacer but substantial lowering to f , ^ o f 45G H z was
seen w hen the devices were biased at equivalent low Jc values (25.8kA /cm 2) used in this
work [52]. Moreover, the fT and f ^
characteristics o f the D H B Ts reported here were
fairly constant over the entire range o f investigated collector current. This is a useful prop­
erty for circuit designs where small sensitivity to applied voltage and current is sought.
The use o f a highly doped spacer prevents the early presence o f base push-out and leads to
fp, f max values that can be m aintained constant over a broader frequency range [54]. The
high f j values obtained for the D H B T are mainly attributed to the reduction o f conduction-band discontinuity using a highly doped G alnP spacer and the associated improved
carrier transport at the heterointerface. M oreover, the improved fmax o f this device benefits
not only from the enhanced fp but also from the collector undercut technique which leads
to reduction o f the base-collector capacitance (Cgc)SHBTs with an identical tunneling em itter design and G aA s rather than G alnP collec­
tor were also fabricated and com pared to the DHBTs o f this work. T he collector thickness
and doping were 7000A and 1.5 x 10 1 6 cm ' 3 respectively fo r the SH B Ts, w hile the corre­
sponding values o f the D H BTs were 5000A and 3 x l 0 1 6 cm *3 (see Table 4.3). The SHBTs
showed Voffsct o f 0.1 V, D C current gain o f 42 and BV C
E 0
o f 22V. T heir m axim um fp, f , ^
values w ere 3 7 ,63GHz respectively under VCE=3V, Ic =51.3m A . This bias corresponds to
the sam e collector current condition as the one used for obtaining the best D H B T fT, fma,
values. As expected, SH B Ts have a higher gain than DHBTs due to th e absence o f con­
duction band spike at the base-collector region. Their breakdown is also lower than for
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107
1f 5 X 4 0
C bc
Re
Rb
Rc
r be
r bc
aT
tf
VCE
•c
Il^max
DHBT
63
2.9
4.3
2
0.5
8K
0.92
5.5
4
51.5
28/63
SHBT
69
4
4.7
5
0.54
20K
0.98
4.0
3
51.3
37/63
Table 4.4: Equivalent circuit param eters for 5x40pm 2 single em itter G alnP/G aA s
DHBTs with 100A highly doped G alnP spacer layer and SHBTs o f sim ilar
design. Both devices w ere biased for best fT, f , ^ performance.
DHBTs due to the use o f GaAs rather than G alnP collector; the larger collector thickness
o f SHBTs (7000A vs. 5000A for G alnP collector) enhances the breakdown voltage char­
acteristics o f the SHBTs. The offset voltage o f the SHBTs is as expected larger due to the
asym m etric nature o f the E-B/B-C heterointerfaces.
The microwave perform ance o f the D H B T was analyzed by extracting sm all-signal
equivalent circuit param eters were used for this purpose as obtained from m easured Sparam eters. Table 4.4 shows such param eters for the devices whose microwave character­
istics w ere presented in Fig. 4.23. It also includes the param eter values o f the SH B T used
for com parison. An analytical extraction technique was em ployed for param eters extrac­
tion to m aintain their physical significance [105], [126]. As expected, the base transport
factor ( a ) is found to be fairly large in SH B Ts (0.98 vs. 0.92 for DHBTs) due to its small
conduction-band discontinuity in the base-collector region. This causes higher DC current
gain, as w ell as reduced effective collector charging tim e and leads to im proved fT values
(37 G H z vs. 28G Hz for DHBTs). T he
o f SH B Ts and DHBTs was found to be same.
This is due to the slightly higher RB and C Bc values o f SHBTs, which dim inishes their
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108
advantage in term s o f fT. The results dem onstrate that by em ploying a suitable spacer
design with doped G alnP and by applying the collector undercut technique, both fT and
fmax values o f D H B Ts can be reasonably high.
4 .4 Summary
In this chapter, High speed perform ance o f G alnP/G aA s HBTs was dem onstrated
using various layer designs. First, high speed G alnP/G aA s H B Ts with reduced em itter
transit tim e are designed, fabricated and successfully characterized by means o f a tunnel­
ing em itter design where a thin wide bandgap (300A G alnP) em itter layer is employed.
The tunneling em itter device presents a cutoff frequency (fT) o f 58GHz and a maximum
oscillation frequency (fmax) o f 100GHz at VCE=2.5V, Ic= 20 mA. The enhanced fT charac­
teristics at high collector current are mainly attributed to the reduction o f the em itter tran­
sit time. An em itter transit tim e reduction by 35% (from 0.51 to 0.33 psec) was found by
using tunneling rather than conventional H B T designs. Tunneling through a thin wide
band-gap em itter layer im proves the transconductance (gm) w hile avoiding considerable
base-em itter capacitance (CBE) degradation. The RBE fo r tunneling em itter design is
improved by 108% (from 2.4 to 1.15£2) w hile C BE for tunneling em itter design is
increased by 54% (from 162 to 250 fF) at VBE=1.49V. A t given collector current C BE for
the tunneling em itter H B T is low er than for conventional designs since a lower VBE is
required in the former.
Secondly, self-aligned com posite em itter A lG aA s-G alnP/G aA s H B Ts were also
designed, fabricated and analyzed. The com posite em itter design H BTs show ed superior
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109
characteristics in term s o f reduced em itter-base capacitance (CBE) and enhanced fT perfor­
mance. These results agree with sim ulated characteristics obtained by M onte Carlo.
Experim ental studies showed that fT im proved from 44 G H z to 62 G Hz by using o f the
com posite em itter design. Also, C BE o f the com posite em itter design HBT w as found to be
at least 3 tim es lower than that o f the conventional em itter design H BT under high Ic (Jc)
bias operation conditions.
Finally, High speed G alnP/G aA s D ouble H BTs w ere designed, fabricated and success­
fully m easured using doped G alnP spacers between the G aA s base and the G alnP collec­
tor to reduce the conduction band discontinuity. U nlike G alnP/G aA s single H BTs, it is
found that the collector o f DHBTs can be etched much faster along the [010] rather than
[O il] direction. The DC and microwave properties were obtained by characterizing 5 x 40
pm single em itter finger devices in com m on-em itter configuration and the corresponding
breakdown voltage (VCEO) was found to exceed 26V. The current gain cutoff frequency
(fp) was 28 G H z and the associated maximum oscillation frequency (fmax) was 63 GHz.
The good D C current gain and fp characteristics obtained for the D H B T are m ainly attrib­
uted to the reduction o f the conduction-band discontinuity using the doped G alnP spacer
layer w hich results in im proved carrier transport at the heterointerface. M oreover, the
im proved f ^ benefits not only from the high fT values but also from the reduction o f the
base-collector capacitance (CBC) through lateral etching undercut.
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CHAPTER V
IMPACT OF N i/G e /A u /T i/A u AND
T i / P t / A u COLLECTOR METAL ON
G a ln P /G a A s HBT CHARACTERISTICS
5.1 Introduction
G alnP/G aA s H B Ts are considered a good alternative to A lG aA s/G aA s H BTs due to
their large etching selectivity between the G alnP em itter and GaAs base which facilitates
m anufacturing and alum inum -free design which can be beneficial for im proved reliability
operation. The advantages o f G alnP/G aA s over A lG aA s/G aA s-based H B T technology are
supported by various reports on discrete device performance [56], [93], [94], but also on
integrated circuits such as high-gain (18.8dB , 52dBQ), broad-bandw idth (19GHz) tran­
sim pedance amplifiers [95], [127]. The presence o f collector-em itter offset voltage (Voff_
set) im pacts the H BT characteristics [57] and is o f prim e im portance, in m odem wireless
applications w here low voltage supply and high power-added-efficiency are key require­
ments. A possible way to reduce Voffset is by m aking use o f double H B T (DHBT) design
[58], [59]. The collector and em itter contact metals are also affecting the offset voltage. In
case o f em itter contacts, the use o f highly doped n+InG aA s allows significant reduction in
110
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Ill
em itter access resistance. T his approach cannot, however, be im plem ented for reducing
the collector resistance (R ^) due to lattice m ism atch between InG aAs and GaAs. Alloyed
AuGeNi is usually em ployed as collector metal in G aA s-based devices. However, nonal­
loyed contacts such as Ti/Pt/Au provide m ore reproducible and uniform characteristics
[60]. Ti/Pt/A u can present good ohm ic characteristics when used as subcollector contact
provided that it is deposited on highly doped n-G aAs. This approach allows ohmic behav­
ior by tunneling despite the fact that the metal w ork function o f Ti is much higher than that
o f n-GaAs.
This chapter describes th e way that the offset voltage is influenced by the choice o f dif­
ferent collector metals in case o f H BTs with low -doped subcollector designs (2~
6
x
10 1 8 c m '3). Experim ental and theoretical investigations are conducted for this purpose and
the V0 ffset dependence on collector metal barrier is discussed.
5.2 Device Processing and C haracteristics
The G alnP/G aA s H BT wafers were grown by reduced-toxicity chem ical-beam epitaxy
(CBE). Ti/Pt/A u metal was first deposited on the InG aA s em itter cap which was doped at
lx lO l 9 c m
3
and the em itter layer w as subsequently etched to allow self-aligned base con­
tact form ation. NH 4O H and HCl-based solutions w ere used for etching o f the GaAs and
G alnP em itter layer respectively. Pt/Ti/Pt/Au was used for the base as this perm itted m ini­
m um base contact resistance. A laterally E tched U ndercut (LEU ) process w as developed
and applied at the base and collector region to reduce base-collector capacitance (C bc)
w hile avoiding base resistance degradation [23]. C ollector contacts using different metals
w ere Anally deposited. The w afers w ere diced into tw o pieces and tw o different metals,
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112
nam ely Ni/G e/Au/Ti/Au (250/320/650/500/3000A ) (HBT A) and Ti/Pt/A u (500/500/
4000A ) (HBT B) were deposited on the collector. Typical I-V characteristics for the two
types o f devices are shown in Fig. 5.1. The collector-em itter offset voltage was found to be
shifted by -0 .2 6 V for H B T B w ith Ti/Pt/A u collector metal ( ^ ^ = 0 . 5 IV ) com pared to
H BT A with N i/G e/A u/Ti/A u (Voffset=0.25V). T he D C gain (£=140) for HBT B is also
low er than for HBT A (£=180). To analyze these phenom ena, the sub-collector doping
concentration was extracted using T L M patterns and the E-B and B-C junction diode char­
acteristics were evaluated for the different metal schemes. Com parisons o f the Voffset val­
ues as obtained directly from I-V characteristics were then perform ed to investigate the
im pact o f metallization choice due to differences in E-B and B-C junctions.
0.03
TA
0.025 - H B T -B
0.02
<
Base current
S ta r t: 0 p A
S to p : 140 pA
S te p : 20 p A
0.015
0.01
o.oos
0
0.5
1
1.5
2
2.5
3
3.5
4
VceM
Fig. 5.1: I-V characteristics o f 2 x 30pm 2 self-aligned G alnP/G aA s HBTs w ith N i/G e/A u/
Ti/A u (HBT A ) and Ti/Pt/A u (HBT B).
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113
5.3 Model for th e Collector-Em itter O ffset Voltage (Voftet)
The collector-em itter offset voltage is defined as the difference between the turn-on
voltage o f the em itter-base (E-B ) and the base-collector (B-C) junctions.
V0 ffset= ^ B E ' ^BC at Ic = OmA
(5.1)
The collector current (Ic) is expressed using the Ebers-M oll equation as follows;
l c — a F A g J Ese x p [ q { V BE — I ER E — I BR B) / k BT ] - A CJ c s & x p [ q { V B C - 1 CR C — I BR B) / k BT ]
(5.2)
w here R E, R E, R q are em itter, base and collector series resistances, J ES, J c s are em itter and
collector saturation current densities, I B, I E are the base and em itter currents, A E, A c are
em itter and collector areas and a F is the forw ard current transfer factor.
^offsetcan
obtained by setting Ic = OmA, [57], [59] in Eq. (5.2) and solving for Voffset
as defined by Eq. (5.1). T his leads to the following expression;
( J cs
,
Vo ffs ',,c . - « e ' B + V
1"
(5.3)
{,a F J E S j
For the case where an additional barrier o f q<J>B=q(<t>s~X) (w here
m etal-sem iconduc-
to r barrier height, <j>s is m etal w ork function and % is electron affinity) exists between the
n-G aA s collector and the collector m etal, the m odified Ebers-M oll model is provided in
Fig. 5.2 and the corresponding collector current equation is given by;
Ic = a f AEJESe\p[q(VBE- I ERE - I BRB) / k BT]
~[ACJ C S t x p [ q { V BC - 1CR C - 1 BR B) / k B T] + AgJ C S e x p l q $ B/ k g T]]
w here V
bc-
(5.4)
^ b c * § B and J ’c s *s the collector saturation current density in case o f therm i-
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114
l cse x p (q $ tfk BT)
B
l F ~ AEJ ES exp^ VB E ~IERE ~ , BRB^/ k BT ^
l R = ACJ
B C ~1CRC ~ 1BRB^/ k BT ^
Fig. 5.2: The modified Ebers-M oll diagram with the collector metal barrier.
onic em ission at the collector m etal barrier. This modified equation for the offset voltage
can be found as Ic=Oi
kBT ' ^ c |
V offset, ce = $B + r e ! B + - ^_ ,n
1A e )
jkF_ ( j cs
*
(5.5)
" I «F JESJ
T he above equation will be used as basis o f the analysis perform ed in the next section in
order to understand the im pact o f m etal type on H B T perform ance.
5.4. DC C haracteristics
Four point probe m easurem ents w ere perform ed on T L M patterns deposited on the var­
ious H B T layers (E, B and C ) to allow m etal/sem iconductor contact evaluation. In case o f
Ti/Pt/A u m etals, it was not possible to extract the contact resistance due to the Schottky
nature o f the contact. In case o f N i/G e/A u/Ti/A u m etal, the m etal-sem iconductor charac­
teristics w ere ohmic and the evaluated contact param eters were Rc =3.2& (contact resis-
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115
tance), R s =37.5£2/sq. (layer sheet resistance) and 1^=6.38^101 (transfer length). The
extracted subcollector doping concentration from TLM measurements w as 5 x l0 1 8 cm '3.
Fig 5.3 shows the E-B and B-C junction diode characteristics. In case o f the E-B junc­
tion (Fig. 5.3a), the tum -on voltages are identical (V BE=1.25V ) since the sam e em itter and
base m etals are used and only the collector m etallization is different. T h e B -C junction
diode characteristics (Fig. 5.3b) m anifest, however, a tum -on voltage (VBC) for HBT B
(1.75V ) which is b y 0.75V larger than for H B T A (1.0V). According to the theoretically
predicted collector-em itter offset voltage (Voffset) o f Eq. (5.1), VBE (1.25V )-V b c ( 1 . 0 V) is
expected to be 0.25V for H BT A which agrees with the offset voltage predicted from the IV characteristics o f Fig. 5.1 (see discussion in Sec. 5.3).
Fig. 5.4 shows the m etai-sem iconductor band diagram which can be used to analyze the
Voffset characteristics for H B T B. Here a Schottky barrier is form ed betw een n-GaAs
(qX=4.07eV) and metal (Ti, q<|>s=4.33eV ) and a collector contact barrier height
(cl<l>B=<l(<l>S- X)) *s established w hich equals 0.26eV. If the n-GaAs subcollector is heavily
doped, the barrier does not behave as Schottky but presents ohmic characteristics due to
tunneling effects. However, the extracted subcollector doping concentration (5 x 10 1 8 cm '
3) is not sufficiently high to allow ohm ic contact operation as also evidenced by the small
tunneling probability o f less than
1 0
% estim ated from the following equation [61].
T ( q ) * e x p ( - ^ / S qq )
(5.6)
w here £ ,
(5.7)
and es is the sem iconductor perm ittivity (13.1), m* is effective mass o f G aA s (0.067),
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116
0.02
0.018
0.016
HBT B
H BT A
0.014
0 .0 1 2
1(A)
0 .0 1
0.008
0.006
0.004
0.002
•5
-4
•3
-2
2
0
3
V (V )
(a)
0.02
0.018
0.016
0.014
HBT A
0.012
0.01
H BT B
1(A ) 0.008
0.006
0.004
0.002
-6
-4
-2
0
2
4
6
V (V )
(b)
Fig. 5.3: E-B (a) an d B -C (b) diode characteristics for different collector metals.
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117
Ti
GaAs subcollector
qX=4.07eV
Ec Ef
. . .
q$s=4.33eV
/
r
Eftn
q0B=q(0s-X))=O-26*V
E*—
/
ioo A
Fig. 5.4: Energy-band diagram fo r n-G aA s subco llecto r(n = 5 x l0 1 8 c m '3) and metal(Ti).
is donor im purity density (5 x 10 1 8 cm ‘3) and (fe is Schottky barrier height on n-type sem i­
conductor (0.26 eV).
To achieve the same potential energy in the E-B and B -C junctions o f the investigated
G alnP/G aA s H BTs, the tum -on voltage (V Bc ) should be 1.25V so that it equals V BE.
T hus, an additional +0.25V bias is needed at the collector side to obtain a total VBC value
o f 1.25V for H B T A (N i/G e/A u/Ti/A u collector metal). In case o f H BT B (Ti/Pt/Au col­
lector m etal), one needs to consider the additional Schottky barrier (qi|>B=0.26V) in con­
junction with the corresponding tum -on voltage, VBc = l .0V. The com bination o f
VBC=1.0V and contact barrier(<|>B) o f 0.26V results in an effective V BC value (V ’BC) value
o f 0.74V. A t least +0.5 IV need consequently to be applied under such circum stances to
the collector in order to obtain a net V BC value o f 1.25V w hich equals the base-em itter
tum -on voltage. T he obtained results are consequently consistent w ith the value o f 0.51V
m easured for Voffset o f H B T B.
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118
In summary, for a Schottky contact between n-G aA s and Ti m etal (H B T B), the offset
voltage is given by;
V o ffs e t
= VBtf 1.25V n-GaInP/p-GaAs)-VBCf].OV for p-GaAs/n-GaAs -0.26 Vfor Schottky barrier) = 0.51V
By em ploying suitable values for the param eters o f Eq. (5.5) ( 6 B= 0.26V , REIB=0.5mV,
the third term o f Eq. (5.5) = 0.1V, the forth term o f Eq. (5.5) = 0.15V ), Voffset for H BT B
was estim ated to be 0.51V which agrees with the value obtained from V0 ffset=VBE - V ’Bc.
The potential barrier formed between the n-GaAs collector and the collector metal results
in current blocking which im pacts the total collector current (Ic ). Thus, a modified total
collector current equation in presence o f a potential barrier as shown in Eq. (5.4) needs to
be considered. Consideration o f Fig. 5.2 showed that the barrier height (<|>B) affects the
H B T saturation current Is which in turn affects the (Xplp current source ( a FIs = apA EJES)
and as a result the total collector current (Ic) can be reduced for increased
0
B values.
A ccording to large signal model extraction using H SPICE, the extracted Is is 6.26 xlO ' 2 3
and 4.76 xlO ' 2 3 for H BT A and H B T B respectively. The calculated total collector current
(at Vb e =1.4V, Vc e =2.5V ) for H B T B using Eq. (5.4) is therefore found to be by 5mA
low er than H B T A which agrees w ith the m easured total collector current for H BT B.
5.5 RF Characteristics
T he microwave properties o f both H B Ts types w ere m easured in com m on-em itter con­
figuration using on w afer tests and an HP8510B netw ork analyzer. The pow er and current
gain versus frequency characteristics o f the H B Ts w ith different collector metals are
shown in Fig. 5.5. A com parison o f microwave perform ance at sam e VCE(3.5V) and
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119
HBT A
-V -
100
10
Freq [GHz]
(a)
35
HBT B
30
25
ca
2
20
e
*3 15
O
10
u
6 3 B /O c f
-H 2 1
v
-N r
5
s \
\
0
10
Freq [GHz]
\
*nux
100
(b)
Fig. 5.5: M icrow ave perform ance o f G alnP/G aA s H B Ts with different collector metals
(VCE = 3.5V, IB = 120pA, Ic = 19.5mA for H B T A, VCE = 3.5V, IB = 120pA,
Ic = 14.1mA fo r HBT B).
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120
Iq(120^A ) bias should ideally result in sim ilar perform ance for H BT A and B if the same
collector metal is em ployed. T he fT and fmax values extracted from Fig. 5.5 em ploy there­
fore the sam e bias conditions (VCE, IB) so that the im pact o f collector metal can be inves­
tigated. The current gain cutoff frequency (fT) extrapolated from the m easured |H 2 i| using
the -6 dB/Oct. slope rule w as 47G H z for H B T A with Ni/Ge/Au/Ti/Au collector m etal, and
42G H z for H BT B with Ti/Pt/A u collector metal. The maximum oscillation frequency
(fmax) from M ason’s unilateral gain (U ) w as 65G H z for the H BT A and 52G Hz for HBT B
respectively. This corresponds to an fT increase o f 1 % and fmax increase o f 25% as a result
o f using N i/G e/A u/Ti/A u collector metal.
High-frequency sm all-signal equivalent circuit param eters o f the G alnP/G aA s H BTs
w ith different collector metals were extracted in an attem pt to provide physical insight to
the device by analyzing the obtained param eters [105]. As expected the collector contact
resistance (Rc) for H B T A is much lower than for H BT B as shown in Table 5.1. This
Sample
Rb
Rbe
Rc
Re
CBe
CBC
“T
P
HBT A with
Ni/Ge/Au/Ti/Au
7-37
1-33
12.6
433
530
32
0.99
162
47/65
120
3.5/19.5
HBT B with
Ti/Pt/Au
84
1.86
274
433
380
34
0.99
116
42/52
120
3.5/14.1
Vce/Ic
W here R (W), C (IF), fp Cm,, (GHz), I (mA)
Fable 5.1: Equivalent circuit param eters for 2 x 30pm 2 single em itter H BT betw een H BT
A with N i/G e/A u/Ti/A u and H B T B with Ti/Pt/Au collector metal.
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121
reflects the fact that the contact resistance is reduced when em ploying Ni/Ge/Au/Ti/Au.
T he intrinsic and access collector resistances im pact significantly the total resistance due
to the low subcollector doping o f 5 x 10 1 8 cm ' 3 in both devices but the im pact o f contact
resistance can still be seen in the m easured total collector resistance values. Study o f the
sm all-signal equivalent circuit param eters, showed that the base-em itter resistance (RBB)
is reduced but the base-em itter capacitance (CBE) o f H B T A is increased due to the collec­
to r current (Ic) increase. As a result, the em itter transit time (Te = R BE x C BE) o f H BT A
has the sam e value as for H B T B and the fT values do not differ significantly. Since the
collector current o f H BT A is higher than for HBT B, the base resistance (RB) o f H BT A is
reduced leading to im proved the m axim um oscillation frequency (fmax= 54GHz) charac­
terization. In summary, H B T B with Schottky barrier in the collector produces higher Rc
and low er I c due to current blocking in the Schottky barrier. Thus R B which is the func­
tion o f I c is increased and the m axim um oscillation frequency (f-p) is reduced.
5.6 Power C haracteristics
T he influence o f different collector m etals on the pow er characteristics was also studied.
Fig. 5.6 shows the m easured large signal output pow er (Pout) and pow er-added efficiency(PAE) as a function o f the R F input pow er for 1 finger 2x 3 0 ^m 2 devices. All H BTs
w ere characterized under optim um bias, source and load im pedance conditions for m axi­
m um output pow er under large signal operation at
8
GHz. The devices were biased for
C lass B (VCh=7V, V b e =0.77V ) operation.
T he input pow er was sw ept up to the 3dB gain com pression point w hile m aintaining
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122
100
£l2
H BT A
HBT B
4
5
6
7
8
9
10
12
Pin [dBm]
Fig. 5.6: Pjn-Pout o f G alnP/G aA s H BTs w ith different collector metals. The devices were
biased for Class B (V CE=7V, VBE=0.77V ) operation at 8 GHz.
constant VCE and V BE bias. T he output pow er (Pout), pow er gain (G) and the collector cur­
rent o f the H B T were recorded and the pow er-added efficiency (PAE) was evaluated. The
HBT A with Ni/Ge/Au/Ti/Au collector metal produces higher output pow er as well as
PAE com pared to HBT B with Ti/Pt/A u collector metal. The m axim um output pow er was
18.4 dB m and 17.5dBm for H B T A and H B T B respectively while the corresponding peak
PAE was 63.1% and 51.2%. This indicates that the larger pow er dissipation through the
large RE(Ti/Pt/Au collector contact) o f H B T B affects its m axim um output pow er perfor­
mance. In particular, H B T A w ith N i/G e/A u/Ti/A u m etal has low er knee voltage (V k)
which leads in increased output pow er as a result o f the im posed limits in Vk at Icmax and
Vnux at Ic =0 and higher D C gain com pared to H B T B. T hus the small contact resistance
o f the H B T A with N i/G e/Au/Ti/Au collector m etal leads to im proved pow er perform ance
due to the resulting low er knee voltage and higher D C gain.
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123
5.7 Summary
The im portance o f the collector metal choice in HBT DC, RF, pow er perform ance is
described. T he presence o f unintentional collector contact barrier leads to a change in the
Ebers-M oll model predicted characteristics and affects the collector offset voltage due to
the presence o f a barrier height (q<J>B=0.26V fo r Ti/Pt/Au). As a result, the total collector
current is reduced leading to sm aller D C gain (AP=46) for HBTs with Ti/Pt/Au collector
m etal. The R F and pow er perform ance o f H B Ts with Ti/Pt/A u is influenced by the pres­
ence o f the large R c resulting from the presence o f the collector contact barrier. The m ax­
im um output pow er for H BTs with N i/G e/A u/Ti/A u metal is 18.4 dBm w hile the peak
PAE is 63.1% . This corresponds to im proved pow er characteristics com pared with HBTs
that present a Schottky barrier at the collector contact.
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CHAPTER VI
PASSIVATION AND RELIABILITY ISSU ES
O F G a ln P /G a A s HBTS
6.1 Passivation o f GalnP/GaAs HBTs
An im portant step in the HBT process is the passivation o f the device. A good pas­
sivation layer plays a role o f preventing degradation o f the device and reducing the density
o f surface states and results in low surface leakage current. This leads to long-lifetim e
device characteristics as necessary in practical applications.
N ative oxide grown on Si, silicon dioxide (SiC^), is an excellent passivation layer,
as well as a perfect insulator in Si based sem iconductors. However, passivation o f com ­
pound sem iconductors is difficult because it involves treatm ent o f a sem iconductor surface
w hich in case o f III-V com pounds is know n to suffer from increased surface states and
Ferm i level pinning.
M any attem pts for deposition o f native S i0 2 and SiO oxide layer on G aA s and other
HI-V com pound sem iconductors have been m ade but the results obtained w ere not satis­
factory. For instance, in the case o f G aA s, since the native oxide on G aA s consists o f a
m ixture o f unstable, non-uniform elem ents such as G a 2 0 3, As 2 0 5, GaO etc., this layer can
not be reliable for insulation o r passivation purposes [62]. Thus, a good “extrinsic” passi124
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125
vation layer on G aA s and related com pound sem iconductors is required for long-lifetime
devices as necessary for w ireless and optical com m unication systems. There are many
types o f passivation m aterials such as S i0 2, SiO, Si 3 N4, SiN x, and Polyim ide that can be
used and the choice am ong them is not straight forw ard [63]. Various deposition tech­
niques, i.e. PEC V D , e-beam evaporation, spin coating are available for depositing the pas­
sivating layers. As to date, no universal passivation technique is available. In practice, the
type o f passivation material does not play an im portant role an the process technique in
obtaining good passivation properties [64].
A nother attem pt for the passivation o f H BTs consists o f em ploying an em itter ledge
in the access region betw een the base contact and the em itter mesa. The depleted G alnP
em itter ledge technique has proven to passivate the free G aA s surface recom bination
effectively in the access base area o f the H B Ts and led to increase o f the current gain [65],
[6 6 ], [67]. The G alnP em itter ledge is form ed after etching the em itter layer on the pat­
terned base region for base m etal deposition. T he passivation ledge thickness is required to
be thin enough so that it is fully depleted by a com bination o f the free-surface Fermi level
pinning above and the base-em itter junction below, otherw ise, a considerable leakage cur­
rent flows through it. If the em itter m esa o f the H B T is fully surrounded by the base con­
tact, the base surface recom bination current m ay be assum ed to be constant along the
em itter periphery. T he dependence o f current gain on P/A ratio can then be evaluated as
follows;
i. = _L +
P
P,
1™lL
Jc *
(6 1)
^
w here P and f t are the m easured and the ideal current gain w ithout any surface recom bina­
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126
tion current, respectively. P and A are the em itter periphery and area, Jsurf is the surface
recom bination current p e r centim eter and Jc is the collector current density. This ledge
technology, however, requires som ew hat large access base area and is not consequently
suitable for self-aligned technology. Furtherm ore, the em itter thickness is lim ited in case
o f depleted ledge technology since it is difficult for a thick em itter to be fully depleted.
Moreover, etching o f the em itter ledge is not easily achieved in a reliable and uniform way
im posing additional difficulty in the im plem entation o f this technology.
In this section, passivation o f H BT w as attem pted by SiC> 2 (4500 A) thin film depo­
sition at 300 °C by m eans o f Plasm a Enhanced Chem ical Vapor D eposition (PECVD).
G alnP/G aA s H BTs before and after passivation were investigated and com pared in term s
o f DC and microwave perform ance.
6.2 Characterization of Passivation layer used for
GalnP/GaAs HBTs
PECVD S i0 2 w as deposited after H B T fabrication including airbridges was com ­
pleted. Fig. 6.1 shows the cross sectional SEM view o f passivated G alnP/G aA s HBT.
Since PECV D passivation w as carried out in the last step o f the H BT process, it was nec­
essary to investigate w hether the em itter-base side wall and the access base layer are fully
covered by S i0 2. As shown in these figures, the access base surface layer where the m ajor
surface recom bination current flows is successfully covered by the S i0 2 passivation layer;
the devices com pared w ere 2 x 10 p m 2 single em itter and 2 finger 5x10pm 2 em itter HBTs.
A com parison o f Ic -V c e characteristics an d G um m el plots before and after passivation for
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127
Substrate
Fig. 6.1: S E M pictures for the cross section o f passivated G alnP/G aA s HBTs with
PEC V D S i0 2.
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128
Before Passivation
After-Passivation
■StarHBrGStop IB: 250 pA
.Step: 50
1.5
2
2.5
v CE[V]
le-01
Before Passivation
A fter Passivation
le-02
le-03
le-04
** le-05
le-06
le-07
0.4
0.6
0.8
1
v
Fig.
6
1.2
1.4
1.6
1.8
Be . v c e [V]
. 2: C om parison o f Ic-V CE characteristics and H B Ts G um m el plots before and
after passivation for 2 x
1 0
pm 2 single emitter.
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129
2 x 1 0 n m 2 single em itter is shown in Fig. 6.2.
A fter passivation, th e DC gain is decreased slightly but no obvious change in Gum m el
plots was observed. T he base current was found to increase slightly after passivation. To
explain the observed trends, one needs to consider the base current com ponents which
include: ( 1 ) the space-charge recom bination current (I b ,sct) *n
( 2 ) the bulk recom bination current ( I B ,buik)
base-em itter junction,
the base region, (3) the current (IB,p) arising
from holes being back injected across the forw ard biased base-em itter junction from the
base into the em itter, (4) the surface recom bination current (lB,Surf)at the exposed em itter
periphery and extrinsic base region [6 8 ], [69]. A schem atic diagram depicting these four
m ajor base currents in HBTs is shown in Fig. 6.3. The surface recombination current Jsurf
can be evaluated as a function o f the collector current density by evaluating the H BT cur­
rent gain before and after passivation. Use o f Eq. (6.1) allows then evaluation o f JSUIf
PECV D S i0 2 Passivation
Em itter
%,bulk
IB.surf
Fig. 6.3: T he schem atic diagram o f the four m ajor base currents in HBTs. A fter H BTs
passivated w ith PEC V D S i0 2, the increase o f the base current results from
m ainly additional base surface recom bination through interface between
em itter periphery and S i0 2 passivation film.
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130
le-02
2
x
1 0
p m 2 em itter
lc-03
2f 5 x 10 pm
x—x—x
] Alter Passivation
] Before Passivation
le-04
10
100
1000
10000
Jc [A/cm2]
Fig. 6.4: T he surface recom bination current as function o f the collector current density
before and after passivation. The surface recom bination current was slightly
increased after passivation with PECV D S i0 2.
before and after passivation. 0; o f Eq. (6.1) before and after passiavtion was extracted to
be identical (0j=6OOO). This is plotted in Fig. 6.4 for tw o different types o f geometry.
The surface recom bination current after passivation with PECVD S i0 2 was slightly
increased for both 2 xlO p m 2 em itter and 2 finger 5 x 10 pm 2 em itter HBTs. M oreover, the
surface recom bination current for 2 x 10 p m 2 em itter H B T is higher than that o f 2 finger S
xlO p m 2 em itter devices since the form er has a larger P/A (Perim eter/A rea) ratio; P/A was
12000 cm ' 1 for 2 xlO p m 2 em itter H B T and 6000 cm '
1
for 2 finger 5 xlO p m 2 em itter
devices. This is consistent w ith the expectation o f higher surface recom bination current
through a larger em itter m esa periphery. T he increase o f the base current after passivation
is m ainly due to additional base surface recom bination at the em itter m esa periphery inter­
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131
face with the S i0 2 passivation film. Surface states in the passivated surface provide addi­
tional generation-recom bination centers and lead in form ation o f an electron accumulation
layer, which acts as a surface leakage path. Sim ilar surface recom bination trends were
reported by other using various dielectric films [70].
Fig. 6.5 illustrates a com parison o f microwave perform ance before and after passi­
vation for a 2 xlO p m 2 em itter HBT. The microwave perform ance is alm ost the same
before and after passivation except in the low frequency region (around 1GHz) which is
dictated prim arily by DC gain characteristics. O ne concludes that the PECV D S i0 2 passi­
vation layer tested in this w ork does not affect the microwave perform ance and can be a
potential candidate for HBTs w ith good reliability characteristics. The reliability charac-
35
2 x 1 d p i n2 sin gle emitter
j
i 1 ! ifl
i
i
1 1I i
| ;
Before Pi iss(vation j
25
i
1f
i :
ii
i
! 1 ; -i
i
1
, j
i; !i : . ■r
ii
I
a 20
!
I ' i i :1
1
1
■ i 1 ,:
1 15
r ri
O
J
H2i
1/Oct. 1i i’ 11
|
10
1
j
1
' I !
After Pass ivatic n l
j
;
|
j
i
i
1
I .
5
I
|
5
1
:
i
i
f
■!
11
i
K*MAX :
0
10
F req u en cy [GHz]
I
:
t
y
o -----
r-----
30
Fig. 6.5: M icrowave perform ance o f the 2 xlO p m 2 em itter H B T before and after passi­
vation with PECV D S i0 2. T he microwave perform ance is alm ost the same
before and after passivation except in the low frequency region (around
1GHz) which is dictated prim arily by D C gain characteristics.
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132
teristics o f these passivated devices were evaluated and are discussed in the next section.
6.3 R eliability Issues of HBTs
Reliability tests determ ine the expected life-tim e o f devices. The reliability o f het­
erojunction devices has been extensively studied but there are still significant on going
efforts for determ ining the lifetim e and explaining the observed properties through an
appropriate model.
A prim ary reliability issue o f H BTs is the base dopants stability, particularly Be and
C. The m ost serious concern in using Be is the diffusion o f doping im purities from the
base into the em itter layer during transistor operation. Experim ental data on the activation
energy concerning the current peak degradation o f tunnel diodes [71] and numerical inves­
tigations concerning D H BT degradation [72] suggest a recom bination-enhanced diffusion
o f the B e sublattice. Therefore an attractive alternative for HBTs with very high base
dopant concentration is carbon (C) due to its very low diffusion coefficient. This is a con­
sequence o f the fact that C occupies the As rather than the Ga sublattice [73]. In spite o f its
low diffusivity, the C atom s suffer from a stability problem due to inclination to the forma­
tion o f C -H com plexes [74] in presence o f hydrogen contamination. SIM S analysis dem ­
onstrated that hydrogen is incorporated during M O CV D growth and also that it can be
absorbed during plasm a deposition o f SiN x or introduced by H+ im plant isolation [75].
The effect o f carbon passivation by H atom s leads to a tim e-dependent current gain, a
behavior which negatively affects the device reliability. T he observed decrease o f the cur­
rent gain w as attributed to the debonding o f H from the C acceptors, probably enhanced by
m inority carrier injection [76]. This m echanism should give rise to an increase o f the
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133
effective base doping [77].
D uring current stress tests o f C-doped HBTs an initial current gain increase has also
been observed. This behavior has been explained by the reduction o f recom bination cen­
ters involving hydrogen atom s [78] and it seems to affect also the low frequency noise
spectra o f the HBTs [79].
A nother issue regarding H BT reliability is the ohm ic contact reliability. The resis­
tance o f ohm ic contacts was found to increase with tim e during HBT operation. AuGe/Ni/
Ti/A u alloyed contacts to n-type G aAs, degrade under therm al stress. G a and As interdif­
fusion is believed to be responsible for this degradation [80]. Systems using refractory
m aterials w ere also investigated for p-type contacts such as Pt/Ti/Pt/Au. N ot only does this
contact provide low resistivity, but it is also reliable under thermal stress [81], [82]. In the
next section, the reliability characteristics o f the fabricated passivated and unpassivated
G alnP/G aA s H B T devices is reported under various bias conditions.
6.4 R eliability T ests o f GalnP/GaAs HBTs
A program w hich controls the base current (IB) to maintain constant collector cur­
rent density (Jc ) was developed using Lab View control software. The collector current
density (Jc ) values selected for the tests were 25 and 40 kA/cm2. A bias tee w as connected
at the collector and em itter term inals to suppress device oscillation. I-V characteristics
were m easured and com pared before and after reliability tests. Passivated devices were
prepared with PEC V D S i0 2 (toX= 4500 A ) as m entioned in the previous section.
6.4.1 Reliability Tests of Unpassivated GalnP/GaAs HBTs
The reliability o f unpassivated 2 x 30 |xm 2 single em itter devices with fT = 58 GHz,
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134
fmax = 1 0 0 G H z w as investigated an d tests w ere perform ed as a function o f current density.
The device shown in Fig.
6 .6
(a) w as tested at 25 kA/cm2. Its current gain was m onitored
over 9 days and was found to decrease by not m ore than 10%. As the current density
increases, the HBT is subjected to m ore stress and is therefore expected to degrade m ore
rapidly. This is shown in Fig.
6 .6
(b) which corresponds to 4 0 kA /cm 2 bias stress o f
another device o f com parable microwave performance. The tests were perform ed in this
case over a period o f 7 days. D uring the first 2 days, the device was found to rem ain stable,
Its gain decreased after this initial period by 21% within 7 days. Possible reason for the
observed DC gain degradation are surface reaction with O 2 am bient through exposed sur­
face o f the device in high collector current conditions and degradation in E-B heterojunc­
tion interface quality. C onsidering the fact that stress at 25 kA /cm 2 is generally acceptable
for testing HBT reliability, one concludes that these unpassivated devices show m odest
degradation.
6.4.2 Reliability Tests of Passivated GalnP/GaAs HBT
Passivated 2 finger 5 x 10 nm 2 em itter G alnP HBTs with a 4500 A S i0 2 layer w ere
also subjected to reliability tests. A PECV D deposited S i0 2 layer was used for passiva­
tion. These tests led to very encouraging results, as discussed next.
Fig. 6.7 shows such reliability tests for passivated 2 finger 5 x 10 p m 2 em itter H BTs
operated at a current density (Jc) o f 4 0 kA /cm 2. T he results show that over a total period
o f 30.5 days, passivated H B Ts show only 2% degradation o f D C current gain despite the
fact that they are subjected to the high current density o f 40 kA/cm 2 used for these tests.
Passivated HBTs show a m uch m ore stable perform ance than unpassivated ones. Shown in
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135
50
2 x 3 0 pm single emitter
45
40
35
02.
c 30
3
“ 25
g
Jc = 25 kA/cm2
t 20
Ic = 15 mA
U 15
V ce = 3V
10
5
9 days
0
0
1x10s 2x10s 3 x l0 5 4 x l0 5 5x10s 6x10s 7x10s 8x10s [sec]
Time[sec]
(a)
50
2 x 3 0 \xm single emitter ■
45
40
35
CO.
c 30
C3
“ 25
c
Jc = 40 kA/cm2
1 20
Ic = 24 mA
U 15
Vce = 3V
10
7 days.
5
0
0
1x10s
2x10s
3x10s
4x10s
Time[sec]
5x10s
6x10 [sec]
(b)
Fig. 6 .6 : Reliability tests o f unpassivated 2 x 30 p m 2 G alnP/G aA s HBTs. Its current gain
tested a t 25 kA /cm 2 w as m onitored over 9 days and was found to decrease by
not m ore than 10%. Its gain tested a t 4 0 kA /cm 2 decreased after this initial
period by 21% w ithin 7 days.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
136
60
50
G
E
L40
s
Jc = 40 kA/cm2
I
c 30
Ic = 40 mA
K
u
VCE= 3 V
3 20
2 f i n g e r 5 x 1 0 \u n 2 e m i t t e r
10
30days
0
0 .5 x l0 6
l xl O 6
1.5xl0 6
2x10s
2 .5 x l0 6
3x
T im e [sec]
Fig. 6.7: Reliability tests for passivated 2 finger 5 x 10 p m 2 em itter H B Ts operated a cur­
rent density o f 40 kA /cm 2. The passivated HBTs show only 2 % degradation
o f DC current gain over a total period o f 30.5 days despite the fact that they
are subjected to such high current density.
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137
Fig.
6
.8 (a) is the G um m el plot o f the passivated G alnP/G aA s HBTs before and after the
reliability stress test. The results show that the current gain at m edium to high collector
current is not very much affected by the stress. In the low collector current region (Ic < 10'
6
A), however, the base ideality factor (rig) is increased from 1.31 to 1.44. This indicates
that th e space-charge recom bination current (lQtScr) is increased and then activation of
recom bination centers in the base-em itter junction takes place during the long reliability
stress test.
Fig.
6
.8 (b) illustrates the m easured current gain as a function o f the collector current.
As can be seen, the current gain is more degraded in the low current region indicating a
larger value o f recom bination current and thus increased base current as described in the
previous section. T he observed change is, however, m odest and overall one can say that
the presence o f additional space-charge recom bination current (lB,scr) results in only small
degradation o f device performance.
6.4.3 Evaluation of Mean-Time-To-Failure (MTTF) for the Passivated
GalnP/GaAs HBTs
The M ean-Time-To-Failure (M TTF) o f a device can be extracted under various ju n c­
tion tem peratures and is expressed by the A rrhenius equation:
M T T F = K e x p fE J k T )
(6.2)
where K is a constant, E a is the activation energy o f the degradation m echanism (eV),
k is Boltzm an constant (k = 8.617 x 10's eV /K ) and T is absolute tem perature in Kelvin.
The activation energy (Ea) can be derived using Eq. (6.2) as applied to tw o reliability
experim ents at a junction tem perature T j and T 2 with corresponding M T lF j and M TTF 2
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138
le-1
le - 2
le-3
le-4
le-5
le - 6
After Test ^
le-7
(30.5 days)
le - 8
rib = 1 4 4
Before Test
nb = i-3i
le-9
le - 1 0
0.4
1.2
1.4
1.6
1.8
V BE [V]
(a)
100
Before Test
go.
After Test
(30.5 days)
le-4
le-3
le - 2
le - 1
Collector Current [A]
(b)
Fig. 6 .8 : Gum m el plot (a) and current gain versus collector current (b) for the passivated
G alnP/G aA s H B Ts before and after the reliability stress test.
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139
values. T he junction tem perature and the thermal resistance o f the device are also calcu­
lated when perform ing these studies.
The junction tem perature o f th e device can be expressed as follows,
= Tambient + ^
where AT = Pdiss x Rth, Pdiss is the dissipated pow er and
(6.3)
is the therm al resistance of the
device. T he calculation o f the therm al resistance (Ry,) can be achieved by perform ing the
following test and analysis [83]: (1) the base-em itter voltage (V BE) is m easured at differ­
ent substrate tem peratures (T) and collector current levels; (2) the relation between VBE
and the dissipated pow er (Pdjss) is determ ined by measurem ent o f V BE at a constant col­
lector current level and substrate tem perature at various V CE! (3) by com bining the two
plots of V BE vs. Pdiss and V BE vs. Temp, a plot o f the calibrated tem perature (T) vs. the
dissipated pow er (Pdiss) can be draw n and R^, can be extracted from this com bined plot as
shown in Fig. 6.9. The m easured devices were in this case 2 x 30 p m 2 single em itter
G alnP/G aA s H B T passivated w ith PEC V D S i0 2 as discussed in the previous section. The
therm al resistance o f the device can be extracted from the slope o f Fig. 6.9 and was found
to be 1430 K/W. This value is close to the reported thermal resistance values o f 1550 K/W
by TEKTRONIX and 1413 K /W by T he University o f M ichigan, [83].
High tem perature life tim e tests allowed M TTF evaluation. Fig. 6.10 shows the
dependence o f the M ean-Tim e-To-Failure (M TTF) to the junction tem perature (Tp. The
failure criterion used in this work w as a
2 0
% current gain reduction from the initial current
gain value before stress application. Each o f the three data points in this figure corre­
sponds to different am bient tem perature and represents the M T T F o f the device which was
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140
400
380
360
340
I 320
£
300
R,h = 1430 K/W
280
2 x 30 p m 2 G alnP/G aA s H B T
260
60
80
100
120
140
D C pow er (mW )
Fig. 6.9: The extracted therm al resistance (R ^ ) using the calibrated tem perature as
function o f DC dissipated pow er for 2 x 30 p m 2 G alnP/G aA s HBTs.
The calculated
is 1430 K /W which is close to reported values for
this type o f technology [83].
a 2 x 30 p m 2 single em itter G alnP/G aA s H B Ts subjected to VCE = 3.0V, Jc = 33.3 kA /cm 2
bias stress. The estim ated M T T F was 2 x 107 hr at Tj = 125 °C w ith an activation energy
(Ea) o f 1.37 eV. This com pares w ell w ith reported activation energy values for G alnP/
G aA s H B Ts which are found to be in the range o f 0.7 to 2.0 eV [84], [85]: the M TFF ver­
sus tem perature dependence o f HBT, reported by other groups is also show n in this figure.
T he activation energy is known to vary depending on the bias stress condition, layer struc­
ture and base refractory metal [85]. T he results o f passivated G alnP/G aA s H B Ts tested in
this w ork suggest satisfactory perform ance and possibility o f application o f the developed
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141
Junction Tem perature [°C]
125 °C
le+12
60 °C
le+10
hm
* le+06
CS)
s
S
le+04
❖
<►: This work
■ ■ ■ : Fujitsu GalnP/GaAs HBT
+—+- + : AIGaAs/GaAs HBT (Fujitsu)
le+02
1.6
l.S
2
2.2
2.4
2.6
2.8
3
1000/T [1/K]
Fig. 6.10: A rrhenius plot o f M T T F for devices subjected to various am bient tem pera­
tures. Bias stresses are VCE = 3.0 V, Jc = 33.3 kA /cm 2 for this w ork (2 x 30
p m 2 single em itter G alnP/G aA s HBTs), VCE = 2.5 V, Jc = 60 kA/cm 2 for
Fujitsu and AIGaAs/GaAs H BTs (2 x 10 p m 2 single em itter geometry).
technology in applications such as wireless and optical com m unication systems.
6.5 Summary and D iscussion on R eliability o f GalnP HBTs
This chapter described the passivation and reliability characteristics o f G alnP/G aA s
HBTs. Passivation o f com pound sem iconductors is difficult because it involves treatm ent
o f a sem iconductor surface which in case o f m -V com pounds is known to suffer from
increased surface states and Fermi level pinning.
In this w ork, G alnP/G aA s HBTs before and after passivation were investigated and
com pared in term s o f D C and microwave perform ance. Passivated H BT devices were
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142
obtained by Si0
2
(4500 A) thin film deposition at 300 °C using PECVD. The surface
recom bination current after passivation with PEC V D S i0 2 was slightly increased for both
2 xlO pm 2 em itter and 2 finger 5 x 10 pm 2 em itter HBTs. The increase o f the base current
observed after H B T passivation results from additional base surface recom bination at the
em itter m esa periphery. T he microwave perform ance is alm ost the sam e before and after
passivation except in the low frequency region (around 1GHz) which is dictated prim arily
by DC gain characteristics. T he reliability characteristics o f passivated and unpassivated
G alnP/G aA s HBT devices were also investigated to evaluate the device life-time. The reli­
ability o f unpassivated 2 x 30 p m 2 single em itter devices was investigated, at a collector
current density (Jc) of 25 kA/cm2. T he current gain was m onitored over 9 days and was
found to decrease by not m ore than 10%. Reliability tests were also carried out 2 finger 5
x 10 p m 2 em itter G alnP H BTs with a 4500 A PECV D S i0 2 passivation layer. T he stress
test was perform ed for 30.5 days and the H B T continued to operate with only 2% o f cur­
rent gain degradation despite the rather high current density (40 kA /cm 2) used for these
tests. Gum m el plots o f the passivated G alnP/G aA s HBTs before and after stress test show
that the current gain at m edium to high collector current is not much affected by the stress
but the base ideality factor (q B) is increased from 1.31 to 1.44 in the low collector current
region (Ic < 10' 6 A ). This suggests that the space-charge recom bination current (lB,scr) ' s
increased due to the activation o f recom bination centers in the base-em itter junction.
T he dependence o f the M ean-Tim e-To-Failure (M TTF) on the junction tem perature
(Tj) was also investigated and the estim ated M TTF in this w ork was 2 x 107 hr at Tj = 125
°C with an activation energy (Ea) o f 1.37 eV.
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CHAPTER VII
BROADBAND AND HIGH GAIN
TRANSIMPEDANCE A M PLIFIERS
7.1 Introduction
H igh speed and high capacity transm ission system s are necessary for next genera­
tion optical com m unications. Integrated photoreceivers com prising both photodetector
and pream plifier stages are now advancing into the m ultigigabit per second regime, with
the em phasis ranging from com pletely m onolithic [87] to flip-chip m ounted [8 8 ] detector
structures. Avalanche photodiode detectors (A PD s), PIN and m etal-sem iconductor-m etal
(M SM ) photodiodes are among the m ost com m only used photodetectors for this applica­
tions. Considerations made in the developm ent o f such system s include process yield
which is related to cost reduction, perform ance stability and device life time under actual
circum stances.
R ecently em erging lightwave com m unications technologies are about to bring 10 G b/
sec system s into com m ercial use [8 8 ]. T here is an urgent need to provide 20 Gb/sec and 40
G b/sec front-end pream plifiers in order to develop the next generation o f cost effective
w avelength division m ultim ixing (W D M ) and tim e division w avelength m ultim ixing
(TD M ) optical fiber networks [89], H igh speed electronic circuit technology is the key to
143
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144
TD M system s for 4 0 G b/sec data rates and W D M system s which use 4 0 G b/sec data rates
per channel.
The transim pedance negative feedback pream plifier has becom e established as a
m ethod to obtain high bandw idths w ithout sacrificing optoelectronic gain o r receiver sen­
sitivity. In the past few years, p-i-n diodes have been m onolithically integrated with tran­
sim pedance am plifiers em ploying H B Ts [90]. T he higher transconductance o f bipolar
transistors as com pared to field-effect transistors (FETs) [91] at the sam e quiescent operat­
ing current results in bipolar amplifiers with sm aller pow er dissipation.
Pream plifier converts current data signals from a photodetector into voltage data
signals and am plifiers in an photoreceiver. A bandw idth o f m ore than 28 G H z (70% o f the
bit rate) is necessary to achieve 40 Gb/sec. The relation between the bandw idth o f the
pream plifier and the device param eters o f the im plem ented transistor w as described by the
authors [92]. The bandw idth mainly depends on the base resistance and base transit time,
and reductions in the base resistance and the base transit tim e are indispensable for more
broadband pream plifiers. However, there is a trade-off between the base resistance and
base transit time. A IGaA s/G aA s H B T pream plifiers based on advanced p + regrow n extrin­
sic technology have dem onstrated excellent perform ance (34.6G H z) with a transim ped­
ance gain o f 41.6dB£2 [92]. G alnP/G aA s H eterojunction B ipolar Transistors (H BTs),
however, are well know n alternatives over AIGaA s/G aA s H BTs due to their attractive fea­
tures such as excellent etching selectivity w hich contributes to process yield, device reli­
ability [84] and im proved carrier injection efficiency [93], [94] due to their large valence
band discontinuity. C om pared w ith the conventional A IGaAs/GaAs H B Ts, their G alnP/
G aA s H BTs guarantees a mean tim e to failure (M TTF) o f 106 hours (at Tj = 200 °C)
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145
which is satisfied for 25 y ear lifetim e requirem ent o f an practical system [84]. G alnP/
G aA s HBT m onolithic transim pedance amplifiers can be used for short distance com m u­
nication (0 . 8 p m ) such as board-to-board o r chip-to-chip data links but also as an alterna­
tive solution to InP-based technology for long distance com m unication (1.3~1.5|xm) by
m eans o f flip chip hybrid m ounted InP photodiodes.
This chapter describes th e design, fabrication and high frequency characteristics o f
transim pedance am plifier O EIC s using the G alnP/G aA s HBT approach.
7.2. Brief MMIC Technology
The M M IC technology im plem ented with self-aligned G alnP/G aA s H B Ts was
described in details in C hapter II. This section illustrates the sum m ary o f the M M IC tech­
nology to fabricate various transim pedance amplifiers on one chip. First, The G alnP/G aA s
H BTs em ployed in this w ork w ere fabricated on layers which were grown by a specially
developed hydride and hydrogen-free Chem ical Beam Epitaxy (CBE) process w hich guar­
anteed a very high degree o f reproducibility o f growth param eters with small defect con­
tent and high output capability. Self-aligned G alnP/G aA s single H BTs were fabricated on
these layers using sim ple all w et chem ical etching w hich m inim ized layer dam age and
device degradation. Ti/Pt/Au non-alloyed metal was deposited to em itter and collector lay­
ers while Pt/Ti/Pt/Au was used as the base metal. Laterally E tched undercut (LEU ) was
developed and applied betw een the base and collector region to reduce base-collector
capacitance (C g c) w hile avoiding base resistance degradation. Fabricated devices w ere
m easured using a netw ork analyzer from 0.5 to 25.5 GHz. A 2 x 30pm 2 single em itter
H B T has been em ployed in the O EIC designs. This H B T showed a cut-off frequency (fT)
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i
146
o f 60G H z and m axim um oscillation frequency ( f , ^ ) o f 100GHz based on current gain
and unilateral gain m easurem ents up to 25.5GH z and under VCE=3V, I^ ^ O m A bias. The
microwave perform ance o f the investigated G alnP/G aA s HBTs shows only slight change
with bias and permits therefore robust circuit design. A fter mesa-isolation which is the
step for etching away all conductive layer (subcollector) and results in semi-insulating
substrate, A N i-Cr (700 A) was deposited on the sem i-insulating substrate and followed by
a A12 0
3
dielectric m aterial deposition by e-beam evaporation on collector metal plate to
achieve a M IM m onolithic capacitors. As described in Chapter n, a thin Ti (500 A) was
deposited before the dielectric material deposition to im prove the adhesion between the
collector metal plate and the deposited dielectric film. A fter the pillar and airbridge real­
ization by evaporation techniques (See Appendix A), the M M IC im plem ented with
G alnP/G aA s HBTs was passivated with PECV D S i0 2 (4500 A) which was characterized
by long reliability tests and satisfied for requirem ent o f long lifetime devices. To open the
microwave and DC probe contacts, the passivated film on the M M IC was selectively
etched away using interconnect m ask and BH F etchant.
7.3 Broadband Transimpedance Amplifier 1
- Common-Emitter (CE) and Cascode Stage
As described in the previous section, high bit rate perform ance in the
com m unication systems is dependent on the bandw idth o f the preamplifier. For instance,
A bandw idth o f more than 28 G H z (70% o f the bit rate) is necessary to achieve 40 Gb/sec
perform ance. There are many kinds o f circuit schem atic configurations to design a certain
perform ance. Reduction o f the m iller capacitance in the circuit configuration is a main
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147
key to design a broadband circuit performance. A first report on a broadband
transim pedance am plifier w hich exceeds 19 GHz was recently presented and com pared
between com m on-em itter and C ascode stage by the authors [95]. Both small and large
signal characteristics o f the transim pedance am plifiers are reported. The large-signal
characteristics o f these am plifiers becom e an im portant issue w hen the front-end pre­
am plifier receives large pow er signals from a photodiode as often occurs in optical
receiver systems [96].
Finally, It shows that large-signal characteristics can affect its speed and output
signal waveform and consequently the bit-error-rate perform ance o f the transimpedance
am plifier.
7.3.1 Design and Experimental Results o f the Transimpedance
Amplifiers
The circuit design w as based on DC and high frequency characteristics o f discrete
H BTs (2 x30 pm 2 single em itter H BTs in this work). Sm all-signal equivalent circuit
param eters were directly extracted from measured S-param eters using an in-house analyt­
ical extraction technique. A m odel w as then developed by com bining the DC model with
high frequency data. The circuit w as sim ulated using LIB R A -H P program. Self-heating
effect in LIBRA is incorporated to account for the negative slope observed in Ic -V Ce char­
acteristics o f the H BT at higher H B T dissipated power. Resistors are also fabricated using
N i-C r alloy to give a sheet resistance o f 20£2/sq. and m odeled separately to account for
their parasitics for a m ore accurate m odeling o f the circuit. By com parison to other tran­
sim pedance am plifier designs the approach adopted in this paper offers:
(1)
A very simple and robust design which is fairly insensitive to the device perfor­
mance variation.
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148
(2)
T he predicted perform ance is rath er independent o f the choice o f the bias and
therefore a better high-frequency perform ance versus pow er consum ption trade-off can be
achieved.
Fig. 7.1(a) shows the schem atic o f the com m on-em itter based transim pedance am pli­
fier (design A ) em ployed in this work. T he input signal current (Ijn) is am plified by the
com m on-em itter stage o f transistor T t and resistor R t . The feedback netw ork which con­
sists o f resistors R 2 and R 3 stabilizes the transim pedance gain. Transistor T 2 serves as a
buffer to isolate the feedback netw ork from the gain stage. T 3 and R 4 behave as another
buffer to isolate the feedback netw ork and output. Fig. 7.1(b) shows the schem atic o f the
C ascode based transim pedance am plifier (design B) which was also explored and fabri­
cated in the sam e lot. The schem atic is identical to that o f the sim ple transim pedance
am plifier o f Fig. 7.1(a). except that in this case, a C ascode stage is used as the gain stage.
As shown in the following, the C ascode design not only im proves the bandw idth, but also
contributes to better large signal perform ance.
Fig. 7.2 shows a photograph o f the fabricated transim pedance circuits (com m onem itter (a) and Cascode (b) design). C oplanar waveguide transm ission lines were
em ployed to connect the am plifier to SO £2 term inations. The chip size for these circuits
was 1125 x 800 p m 2.
Fig. 7.3(a) shows the m easured transm ission coefficient (S 2 j) and transim pedance
gain o f the com m on-em itter based transim pedance am plifier o f the circuit o f Fig. 7.1(a)
m easured w ith H P 8722D network analyzer. A S 2 1 gain o f 17 dB w ith a bandw idth o f
10GHz has been m easured using an on-w afer probe m easurem ent technique.
Fig. 7.3(b) show s S2i and transim pedance gain o f the C ascode transim pedance am pli-
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149
too
In p u t ©■
Output
(a)
Voo
Input
o>
Output
(b)
Fig. 7.1: Schem atic o f the G alnP/G aA s H B T transim pedance amplifiers; (a): D esign A
(com m on-em itter based), (b): D esign B (C ascode based).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
150
\ i
T I
In
\ .:
\
\ .
\
\ (
K '
k i
'
Oui
(a)
(b)
Fig. 7.2: Photograph o f the fabricated transim pedance am plifiers; (a): D esign A (com ­
m on-em itter based), (b): D esign B (Cascode based).
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151
60
50
£9 40
£
tran! imped ancc Gain
30
Gain
10
0
Frequency [GHz]
(a)
60
50
Bias A
Bias B
l ’” '
1
^
■
a 40 ________ Transimpedance Gain;
10 B tas-B
0
Frequency [GHz]
(b)
Fig. 7.3: Transm ission coefficient S21 and transim pedance gain o f the com m on-em itter
transim pedance am plifier [design A] (a) and the Cascode transim pedance
am plifier [design B] (b) m easured by on-w afer probing.
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152
fier o f the circuit o f Fig. 7.1(b). A sim ilar S2i gain o f 17 dB w ith a bandw idth o f 15GHz
has been achieved for bias condition A (Vc ^ =5V). The transim pedance gain was
47dB£2 and 50dB£2 for design A and design B respectively. By increasing the collector
voltage o f the C ascode stage (Bias condition B), th e bandw idth could be increased to
19GHz w hile the associated S 2 1 and transim pedance gain w ere 12dB and 47dBQ, respec­
tively.
7.3.2 Large Signal Performance and Analysis of the Transimpedance
Amplifiers
T he large signal perform ance o f the two transim pedance designs was evaluated
using an H P 8722D network analyzer and the output pow er was m onitored with a power
m eter for higher accuracy.
Figs. 7.4(a) and 7.4(b) show the m easured
P o u t- P jn
characteristics for different fre­
quencies for the com m on-em itter based (design A) and Cascode based (design B) transim­
pedance am plifiers respectively. T he chips com pared showed sim ilar gain-frequency
characteristics under sm all-signal conditions. The com m on-em itter based transim pedance
am plifier show s a m ore pronounced gain com pression especially at low er frequencies. The
Cascode based transim pedance circuit, however, shows very sm all gain com pression at
high input power. This is mainly due to the fact that self-biasing effects resulting from the
presence o f large signal input conditions are reduced in this design.
A com parison between the collector currents o f transistor T 3 (output stage) o f these
two designs revealed that in the case o f design A, the collector current increases from the
nom inal value o f 18 m A to 48 m A as the input pow er increases from 15 dB m to -3 dBm.
The C ascode design however shows a negligible current increase. O verall, the Cascode
design appears to be less sensitive to increased input pow er levels. This feature, in addition
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153
a.
0-10
-15
-20
12
-15
-10
Input Power [dBm]
(a)
f(G H z)
3-10
-15
-20
-15
-10
Input Power [dBm]
(b)
Fig. 7.4: M easured Pout-Pin characteristics o f design A [com m on-em itter] (a) and design
B [Cascode] (b) transim pedance am plifiers. T he com m on-em itter based tran­
sim pedance am plifier shows a m ore pronounced gain com pression especially
at low er frequencies. T he Cascode based transim pedance circuit, however,
shows very sm all gain com pression at high input power. This is mainly due to
the fact that self-biasing effects resulting from the presence o f large signal
input conditions are reduced in this design.
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154
to a higher bandw idth, m ake the C ascode design a better choice for optoelectronic applica­
tions. Frequency dependence tests o f the large-signal gain proved again the superiority o f
the C ascode design in term s o f im m unity to increased input pow er level conditions.
O ne might consider the self-biasing effect analysis for both topology
transimpedance amplifiers. T o show the effect o f input signal on DC biasing o f
am plifiers, a com parison o f transim pedance am plifier characteristics based on analytical
expressions and a sim ple T-equivalent circuit for HBTs w as performed. This analysis was
done at small frequencies (D C to 1 G H z) for which the junction reactances are negligible
so that an estim ate o f circuit perform ance can be made on a DC basis without significant
impact from reactive elem ents. Fig. 7.5(a) shows the circuit schematics o f the Cascode
transim pedance am plifier (design B) using the HBT T-equivalent circuit. The em itter
current of the input transistor (T t) can be written as following;
I Fl = 70ex p
V rf
+
V in
——
V in
= / FIGe x p ~
(7.1)
w h e r e I F 1 is th e e m i t t e r c u r r e n t o f T j , If 1 q is th e q u ie s c e n t c o m p o n e n t o f th e e m itte r
c u r r e n t, IQ is th e e m itte r - b a s e d a r k c u r r e n t, a is th e HBT e m itte r in je c tio n e f f ic ie n c y , VBE
is th e q u ie s c e n t c o m p o n e n t o f th e b a s e - e m itte r v o lta g e , V jn is a s in u s o id a l in p u t v o lta g e
a n d VT is th e th e r m a l v o lta g e .
For the purpose o f the analysis, it is assum ed that all H BTs in the circuit have the
same current gain since they are all operating around th e same bias condition. O ne can
find the quiescent current com ponent I f 1 q and the output voltage V0ut fo r this circuit as
(7.2)
/
F1Q
(1 -
ol) R
2 + a 2 K 1 / F 1 Ge x p (V /n/ y 7.)
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155
*cc
B»
ai
Input,
(a)
C-E b a se d (D esign A)
>
u
00
C3
O
>
C a sc o d e b a se d (D esign B)
U
Q
3
a.
3
o
Input Sinusoidal Signal A m plitude [mV]
(b)
Fig. 7.5: The circuit schematics o f the Cascode transim pedance am plifier (design B)
using the H BT T-equivalent circuit, (b) D C com ponent o f the output voltage
is plotted vs. the am plitude o f th e sinusoidal input voltage.
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156
Therefore the D C com ponent o f the output voltage can be approxim ated by the
average o f m inim um and m axim um voltage o f the output signal with 90° and 270° phase
shift, respectively with respect to the input.
V ou, ,C a ,c ,4 ' = V c c - ^ V BEj>n - a \ l n Q e ^ { . V in/ V T )
(7.3)
By em ploying the sam e approach, one can also establish a DC large-signal model for
the com m on-em itter transim pedance am plifier (design A). The output voltage, in this
case, is given by the following equation.
(1 —0t)/?2
V oui,CE
=
(
V C C ~ 2 V BE ,on)( {
+ a /? ( e x p ( V ^ / V r )
( ? '4 )
B ased on the previously described theory, one can estim ate the change of the
output voltage DC com ponent as the input voltage swing increases for the two different
designs. Such a com parison is shown in Fig. 7.5(b) where the DC com ponent o f the
output voltage is plotted vs. the am plitude o f the sinusoidal input voltage. Design A
w hich is based on the com m on em itter approach shows a larger variation o f the DC bias
for the output stage transistor T 3 due to self-biasing. Self-biasing occurs when the non­
linear operation o f the transistor generates by rectification an additional D C com ponent
which effectively changes the operating bias o f the transistor. T ransistor H BT T 2 o f the
previous stage o f design A also shows significant self-biasing w hile transistor H BT T 2 o f
design B is not subjected to significant self-biasing.
T o explain the difference in the output voltage D C com ponent, one should notice
that the tw o am plifiers com pared in this study were designed to provide sim ilar gain. In
com m on-em itter design (design A), H B T T 1 has a large voltage gain and therefore a large
effective M iller capacitance is in parallel to resistor R t . In order to keep the gain high, the
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157
value o f R] m ust be higher than that o f design B (Cascode configuration) in which the
M iller effect is minimal ( R ^ O O Q in design A vs. R t=75 Q in design B). Since optimal
bias needs to be em ployed for large bandw idth o f operation, the bias voltage o f the circuit
(Vc c ) has to increase to provide the sam e current in resistor R t (Vc c =12 V in design A
vs- Vc c =5 V in design B to provide 20 m A current in R ^ . The optim um collector-em itter
voltage for the HBTs em ployed in th e circuits is 3 Volts and transistor T* o f design A is
biased at 3 V olts while its m axim um collector voltage can reach 12 Volts. On the other
hand, the m inim um attainable collector voltage o f this transistor, neglecting the offset
voltage, is close to 0 Volt. Therefore at high input pow er, transistor T i operates between
0 to 12 V resulting in a shift o f collector voltage DC com ponent to about
6
Volts. Design
B, how ever, shows a sm aller shift in D C com ponents in presence o f high input pow er due
to sm aller Vc c , and thus the self-biasing is not pronounced in this design; under high
pow er input signal conditions, the C ascode design corresponds to signal swings between
0 and 5 Volts. Self-biasing effects can deteriorate the gain o f the am plifier by driving the
H BT out o f its optim um bias setting.
A s expected, the higher harm onic com ponents o f the output pow er o f the am plifier
o f designs A and B increase as the input incident pow er increases.
Fig. 7.6 shows these features by assum ing that the fundam ental frequency for
am plification is 5 G H z and exam ining m ultiples o f this frequency. O ne sees that the
output pow er lost in harm onics is m uch higher in the case o f design A at pow er levels
beyond -12 dB m where the device behaves in strongly non-linear fashion.
A s a result, the gain degradation w ith input pow er level is expected to be sm aller in
design B.
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158
Design B (5 GHz)
Design A (5 GHz)
iign A (10 GHz
Design B (10 GHz)
Design A (20 GHz
Q*
Design B (20,1
•20
Input Pow er [dBm]
Fig. 7.6: Sim ulated fundam ental and higher harm onic com ponents o f output pow er as
function o f input power for design A (com m on-em itter based) and design B
(C ascode based) at 5 G H z fundamental frequency. The output pow er lost in
harm onics is much higher in the case o f design A at pow er levels beyond -12
dB m w here the device behaves in strongly non-linear fashion.
7 .4 Broadband Transimpedance Amplifier 2
- Distributed Am plifiers
D istributed am plifiers are also good candidates to satisfy the requirem ent o f near
future high-bit-rate optical com m unication system s (> 40 G b/sec) due to a num ber o f
advantages ov er conventional transim pedance am plifiers. F or instance, the D A has a
good input, output im pedance m atching, much m ore broad flat gain and reduces the noise
contribution into artificial transm ission line [97], [98]. Recently, H B T D A s have been
im proved rapidly due to his own advantages such as low noise and higher input sensitive
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
159
20
(Gain-Bandwidth Product'.GHz)
■ TRW, ‘94, InP/InGaAs (84 GHz)
15
* U of M, ‘98, GalnP/GaAs (118 GHz)
x TRW, *91, AIGaAs/GaAs (71 GHz)
TRW, ‘96, InAlAs/InGaAs (59 GHz)
♦
5
+
TRW, ‘96, AIGaAs/GaAs (33 GHz)
A
TRW, ‘97, InAlAs/InGaAs (82 GHz)
0
0
10
20
30
40
50
60
Bandw idth [GHz]
Fig. 7.7: The current state-of the art for the gain-bandwidth perform ance o f the distrib­
uted amplifiers with G aA s and InP based HBTs. G ain-bandw idth product o f
118 G H z by U o f M ichigan is am ong the highest value reported for the dis­
tributed amplifiers with G aA s and InP based HBTs.
rather than FETs DAs [99]. Furtherm ore, many researchers have developed the HBT D A
based on G aA s and InP to obtain m ore broad band and high flat gain using attenuation
com pensation techniques [ 1 0 0 ] and input active load for im provem ent o f gain at low
frequency region [ 1 0 1 ].
Fig. 7.7 shows the current state-of the art for the gain-bandwidth perform ance o f the
distributed am plifiers with GaAs and InP based H BTs. The relation between gain and
bandwidth is a trade-off and can be controlled by the circuit configuration in term s o f
certain purposes in the com m unication system s. O ne figure o f merit, gain-bandw idth
product o f 118 GHz by U o f M ichigan is am ong the highest value reported for the
distributed am plifiers w ith G aA s and InP based H B Ts as shown in Fig. 7.7.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
160
U nlike the m onolithic photoreceivers fabricated with InP based H BTs for long
w avelength (-1 .3 pm ), em ploym ent o f G aAs-based technology allow s realization o f
integrated optical receivers for short wavelength (-0 .8 pm ) com m unication. This
technology can also be used in conjunction with InG aAs diodes in hybrid form for long
wavelength system s. M oreover, the absence o f integration capability with 1.55 pm
photodiodes can be com pensated by the significant progress m ade recently in flip-chip
m ounting technology [102]. An additional advantage o f hybrid approach is the possibility
o f the selection o f optim um PIN photodiode characteristics so that small input pow er
levels and good overall quantum efficiency can be achieved. First results on the use o f
G alnP/G aA s H BT technology [103] for the realization o f transim pedance [95] and
distributed [104] am plifiers were recently presented by the authors. In this section, a
m ethodology to design broad band and high-gain H BT distributed am plifiers is described
and its validity through experim ental results are also dem onstrated. G alnP/G aA s HBT
technology offers several advantages over A IGaAs/GaAs such as high injection
efficiency and very good etching selectivity between G alnP and GaAs. M oreover, the
reduced toxicity TB A , T B P precursors em ployed in this w ork proved to result in
excellent discrete device and 1C chip perform ance as previously reported by the authors
[95], [103]. T he design o f distributed am plifiers with different active cells and various
num ber o f stages is presented in the following Section 7.4.1. T h eir perform ance is also
com pared on the basis o f high-gain (>12 dB) and high-bandw idth (25 G H z) requirement.
Based on the results, a 3-stage large bandw idth 50 M H z-27.5 G H z distributed am plifier
with a S21 gain o f 12.7 dB was fabricated. Characterization details are described in
Section 7.4.2. The fabricated circuit has a com m on-collector C ascode active cell designed
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
161
using attenuation com pensation technique [100]. Although, the design does not em ploy
an active load at the input an d output transm ission lines [98], [101], its low-frequency
perform ance proved to extend to 50 M H z since no capacitor is used for matching the
input and output.
7.4.1 Design Consideration of the GalnP/GaAs Distributed Amplifiers
The distributed am plifier circuit design was based on same techniques as the
conventional circuit design described in section 7.3.1. O n-w afer probe m easurem ent o f
discrete 2 x 30 p m 2 H BTs was used to model the device inside the H P-EESO F LIBRA
environm ent. Physical sm all-signal equivalent param eters were extracted from cold and
hot S-param eter measurements [105]. The developed small signal model was used to
design distributed am plifiers with different active cell designs and various num ber of
stages.
D istributed am plifiers using traditional approaches such as com m on-em itter and
Cascode active cells were exam ined first. These designs were found to provide limited
values o f gain due to the relatively high access resistance o f the HBT base and collector
term inals.
A m axim um gain S2i o f 10 dB with input and output m atched condition w as achieved
with a 3-stage Cascode-based distributed amplifier. Increasing the num ber o f stages only
increased the gain o f the am plifiers at low frequencies. The high losses introduced by the
H B T input and output series resistances resulted in an overall gain reduction at high
frequency (> 20 GHz) as the num ber o f stages exceeded four. Thus, such designs are not
suitable for broadband high-gain distributed am plifiers and alternative design approaches
are addressed in this section.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
162
Input
Ve
Ve
Ve
Tb
T5
R2
Vcc
Ro
Rs
Output
Fig. 7.8: C ircuit schematic o f the 3-stage distributed am plifier fabricated with G alnP/
G aA s H BTs using com m on-collector stage followed by Cascode active cell.
T he alternative design approach explained in this work is based on the attenuation
com pensation technique [100], nam ely a com m on collector stage follow ed by a Cascode
transistor pair. Fig. 7.8 shows a 3-stage distributed am plifier based on the "commoncollector C ascode" active cell approach. This schem e provided high gain and high
bandwidth as described later. No active load was em ployed at the input and output
transm ission lines as reported by the authors [98], [101]. The com m on-collector stage
(T i, T 4 o r T 7 in Fig. 7.8) provides at the base and thus input C PW line a transform ation
o f the capacitive loads C BE seen at the em itter o f H B T T 1? T4, T 7 into a negative
resistance fo r the frequencies o f interest. The effective negative resistance, com pensates
the losses due to the loading effect o f the C PW line and the other transistors. Resistors
R j, R 2 and R 3 serve as biasing resistors. O ur simulation show ed that the required gain
and bandw idth specifications o f S 2 1 > 12 dB , BW > 23 GHz can be achieved using three
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163
stages o f am plification o f this design scheme.
Circuit analysis w as perform ed to understand the m echanism s responsible for the
features observed in the 3-stage distributed am plifier as shown in Fig. 7.8. The input
im pedance o f the transistors o f other distributed cells (T 4 in 2nd stage and T 7 in 3rd
stage) dom inates the losses seen at the input C PW transm ission line. The circuit permits
com pensation o f this loss by m eans o f a negative resistance induced at the base terminal
o f transistor T j. T ransistor T j, being a com m on-collector stage, transform s the capacitive
load provided by transistor T 2 into a negative resistance, which cancels out the losses
seen at the input CPW line. Com pensation o f losses present in the circuit allows one to
obtain higher gain (>12 dB) which cannot be realized using traditional distributed
am plifiers em ploying com m on-em itter o r Cascode cells. A distributed am plifier with a
Cascode active cell could only provide a gain S2i o f 10 dB over a bandwidth o f 25 G H z
w hile com m on-em itter based designs were lim ited in gain as well as bandwidth (S2i <
8
dB, BW < 20G Hz). The stability o f operation is assured by carefully selecting the length
o f transm ission lines such that the overall stability factor K is always greater than one.
The physical m echanism s responsible for this is the transform ation o f negative resistance
through the C PW lines and cancellation o f the losses induced by other distributed cells,
leading to an overall stable operation.
The gain stage consists o f the T 2 -T 3 C ascode pair. The use o f C ascode rather than
com m on-em itter gain stage allow s a higher bandw idth for each individual stage due to
suppressed m iller capacitance effect in the C ascode p air as analyzed in the previous
section. A s a result, a sm aller num ber o f stages is required to produce the sam e overall
bandwidth. A nother advantage o f the C ascode configuration is the reduced output
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
164
transm ission line losses due to the higher output im pedance o f com m on-base stage [106].
75 S i CPW lines were used to achieve the required phase delay am ong the active cells
and to achieve the necessary inter-stage matching. U se o f 75 S I rather than 50 £2
im pedances allow ed design o f the am plifier with shorter CPW transm ission lines, thus
reducing the overall size o f the circuit. A irbridge interconnects reduced line m oding to
ensure pure CPW mode operation.
An analysis o f the distributed am plifiers show ed that the design requirem ent of
minim um gain o f 12 dB over a bandw idth o f DC-27 could be satisfied with three stages
o f distributed am plification. The sim ulated and experim ental S-parameters o f the 3-stage
distributed am plifier is shown in Fig. 7.10. The use o f a 2- rather than 3-stage distributed
am plifier schemes provides sm aller gain (10 dB ) over a narrow er bandwidth o f 25 GHz.
A larger num ber of stages (> 4) tends to increase the gain only at low er frequencies. For
instance, four stages o f distributed am plification provide a gain o f 15 dB up to 15 GHz,
while for frequencies between 15 to 27 G H z the gain is not affected by the additional
stage and remained at about 12 dB. Therefore, the 3-stage distributed am plifier design
was considered an optim um choice and was chosen for implem entation. All H BTs were
biased at or close to their optim um bias point (V c e = 3 V, Ic = 13 - 22 mA). A typical
bias condition for the circuit w as Vb=2.9 V, Vc=4.5 V and Vcc =9 V and the DC pow er
consum ption was 650 mW.
The input and output lines w ere m atched to Rout,b = 2 5 S i and RoUt,c= ?5
£2
resistors,
respectively. This choice o f resistors allow ed flat gain characteristics to extend to very
low frequencies as w ell as suppressed noise com ponents stem ming from the resistors due
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Fig. 7.9: Photograph o f the 3-stage distributed am plifier fabricated with self-aligned
G alnP/G aA s HBTs. T he chip size is 1200 x 1125 Jim 2.
S21 (Sim .) !
Sim.)
(Sim.)
10
1
30
Frequency [GHz]
Fig. 7.10: Sim ulated and m easured S-Param eters o f the 3-stage distributed amplifier. A
S2i gain o f 12.7 dB over a bandw idth o f 27.5 G H z was measured. This corre­
sponds to a 118 G H z G ain-Bandw idth product, which is am ong the highest
reported values for H BT-based distributed amplifiers.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
166
to their sm all values. The reasonably low values o f these resistors d id n ot significantly
im pact the pow er consum ption o f the circuit; base and collector biases were provided
through these resistors. Resistors R lt R 2 and R 3 w ere used to bias the C ascode cells. Bias
tuning o f independent stages was possible through the term inals denoted by Vc.
Previous dem onstrations o f H B T distributed am plifiers em ployed capacitors at the
input and output transm ission lines to provide the required m atching and flat gain
conditions. T he use o f small value resistors enabled circuit design w ithout any capacitor
at the input o r output transm ission lines. Capacitors were only used for high-frequency
grounding purposes at the base o f com m on-base transistors T3, T 6 and T 9 in Fig. 7.8.
Since no capacitors in the signal path were em ployed in the design, an im proved lowfrequency perform ance o f the am plifier with a flat gain dow n to a low frequency o f at
least SO M H z was achieved.
The distributed am plifier o f Fig. 7.8 was fabricated using the G alnP/G aA s HBT
technology described in C hapter n. Fig. 7.9 shows a photom icrograph o f the fabricated
distributed am plifier in G alnP/G aA s H B T technology. The chip size w as 1200 x 1125
2
|xm .
7.4.2 Experimental Results of Distributed Amplifier
O n-w afer testing was used for circuit characterization. T he S-param eters o f the
distributed am plifier were m easured from 50 M H z to 40 GHz using an H P8722D
netw ork analyzer. Fig. 7.10 shows the sim ulated and m easured S-param eters o f the
am plifier m easured at Vb = 2.9 V, V c = 4.5 V and Vcc = 9 V. A S 2 1 gain o f 12.7 dB over
a bandw idth o f 27.5 G H z was achieved. This corresponds to a 118 G H z G ain-Bandw idth
(G P) product, w hich is am ong the highest reported values fo r H B T-based distributed
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
167
am plifiers i.e., 107 G H z o f G P for an InP based H B T distributed am plifier [107] and 71
G H z o f G P for A IGaAs/GaAs HBT distributed am plifier [108]. A m plifier isolation (S 1 2 )
ranged from -SO to -12 dB in the operation bandw idth w hile input and output m atching
(Si 1 , S 2 2 ) ranged from -13 to -3 dB.
D istributed am plifier designs benefit from the presence o f an active load at the input
and output transm ission lines to extend the bandw idth to low frequencies [98], [101] and
im prove noise perform ance [99]. The am plifier reported here does not use such active
loads, but dem onstrates operation capability at low frequency.
This is due to the fact that the attenuation com pensation schem e em ployed in these
am plifiers allow s one to use low term ination resistor values Routb and RoUt,c w hile
achieving high gain by means o f the negative resistance provided by the com m oncollector transistors. The noise perform ance o f the am plifier also benefits from the use o f
low input and output m atching resistors. Fig. 7.11 shows details o f the transm ission
coefficients (S 2 1 . S n and S2 2 ) o f the am plifier m easured in the 50 M H z to 3 G H z range.
As can be seen from the figure, the gain does not change significantly at low frequencies.
Capacitive loading at the input and output transm ission lines proved to deteriorate the
low -frequency perform ance o f the am plifier and w as thus avoided.
Eye-diagram tests w ere perform ed for the am plifier at 10 G b/sec w ith a 2 15-1 N RZ
pseudo-random bit sequence (PRBS) using an A nritsu M P1701B pattern generator and a
sam pling oscilloscope. Fig. 7.12 shows the m easured results indicating very open eye
characteristics w ith no signal skew ing and very sm all inter-sym bol interference (ISI) and
no jitter. R educed signal skew ing and ISI in the eye-diagram are attributed to the circuit
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
168
-10
-15
-20
-25
0.05
Frequency [GHz]
Fig. 7.11: M easured S-Param eters o f the 3-stage distributed am plifier at low frequency
region (50 M H z ~ 3 G Hz). T he gain flatness extends to low frequency region.
Time (n sec)
Fig. 7.12: M easured output eye-diagram o f the 3-stage distributed am plifier at 10 Gb/sec
2 2 1 - 1 N R Z PRBS.
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169
high bandwidth o f operation. It is expected that this circuit perform s well up to 40 Gb/sec
bit rates.
The electrical sensitivity o f the am plifier w as m easured using an Anritsu M P1702A
bit-error rate detector. Fig. 7.13 show s the bit-error-rate (BER) m easured at 10 Gb/s NRZ
pseudo-random bit sequence with tw o different w ord lengths.
The 27- l w ord length show ed a sensitivity o f -33 dBm at 10' 9 bit-error-rate w hile the
2 15-1 word length had a low er sensitivity o f -25 dBm . The sensitivity o f the distributed
am plifier reported in this work is am ong the highest reported figures [109]. The high
sensitivity o f the am plifier is usually attributed to the high-bandwidth o f operation and
10Gbtt/s
3
a
OS 1*>07
la-11
•34
-32 -30 -21 -21 -2« •22
A verage Incident P ow er (dBm)
Fig. 7.13: B it-en o r rate o f the 3-stage distributed am plifier as function o f average inci­
dent pow er m easured at 10 G b/sec N R Z PRBS. The 27- l w ord length showed
a sensitivity o f -33 dB m a t 10" 9 bit-error-rate w hile the 2 15-1 w ord length had
a low er sensitivity o f -25 dBm .
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
170
low noise perform ance for the am plifier which, results in very small inter-symbol
interference (ISI) and therefore provides a higher noise m argin [104].
7.5 High-Gain Transimpedance Amplifier
- Multi-Feedback Design
H igh-speed optical com m unication receivers often use a high-gain transimpedance
pre-am plifier in conjunction w ith a photodiode to transform the optical signal into
electrical signal. These transim pedance am plifiers are utilized w ith various technologies
such as hybrid and m onolithic H EM T and H BT based integrated circuits. Very high
bandw idths
have been
reported for receivers fabricated by
various technology
approaches. 23-G H z m onolithic InP/InG aA s HBT transim pedance am plifier [110] and 20
G b/s operation speed with a sensitivity o f -17.6 dBm at a bit erro r rate of 10‘ 9 InP OEIC
[111] have been achieved. A bandwidth o f 18.5 G H z has been dem onstrated for a
m onolithic InA lA s/InG aA s H EM T photoreceiver [112] w hile AlG aA s/InGaA s pre­
am plifiers show ed 4 0 G b/sec transm ission capability with a bandw idth o f 34.6 GHz and a
transim pedance gain o f 41.6 d B Q [113]. The use o f InP based technology offers the
advantage o f integration possibility with PIN photodiodes and thus operation at 1.55 pm
wavelength.
Em ploym ent o f G aA s based technology allows realization o f integrated optical
receivers for short w avelength (~0.8 pm ) com m unication. It can also be used in
conjunction with InG aA s PIN photodiodes in hybrid form for long wavelength systems.
G aA s technology offers the advantages o f high throughput, high yield and process
m aturity over its InP based counterpart. M oreover, the lack o f integration capability with
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171
l.SS p m photodiodes can be com pensated by the significant progress made recently in
flip-chip m ounting technology [114]. An additional advantage o f this approach is the
possibility o f selecting optim um PIN photodiode characteristics so that small input pow er
levels and good overall quantum efficiency can be achieved.
In this section, a high-gain transim pedance am plifier with a transim pedance gain o f
52 dB Q and a bandw idth o f 13.5 G H z is presented. G alnP/G aA s H B T technology has
been em ployed for am plifier realization since it offers several advantages over AlG aA s/
G aA s as described in the previous section.
7.5.1 Design Consideration of the High-gain Transimpedance Ampli­
fier
O n-w afer probe m easurem ent o f discrete 2 x 30 p m 2 em itter finger H BTs was used to
model the devices in H P-EESO F LIBRA environm ent. A physical small signal model
was extracted from sam e techniques as described in the previous section.
T he developed small signal m odels w as used to design the transim pedance am plifier.
The design em ployed tw o cascaded com m on-em itter stages (transistors T t and T 3 ) with
dual-feedback netw ork (Rn ,
and R ^ ) for im proved bandwidth and gain stability
[115], [116] (see Fig. 7.14).
A com m on-base output stage (transistor T$) w as used for im proved output matching
to 50 £2. T he design w as optim ized for high-gain yet large-bandwidth operation. Fig. 7.15
show s a photograph o f fabricated transim pedance am plifier in G alnP/G aA s HBT
technology. T he chip size is 1125 x 800 p m 2.
7.5.2 Experimental Results of the Multi Feedback Transimpedance
Amplifier
O n-w afer sm all-signal S-param eter m easurem ents were perform ed to assess the
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172
Vcc
R4
R7
Output
R2
VC
Input
Re
Vb
R3
Rt2
Rt3
Rfl
Fig. 7.14: Schem atic o f the m ulti-feedback transim pedance amplifier fabricated with
G alnP/G aA s HBTs. Novel circuit approach allows very good stability(due to
T 5, T 6 com bination) as w ell as high gain and bandw idth(Ti, T 3, T 6 gain
stages, T2, T 4 feedback stages).
c m
>
\ h
\ c»
\ it
c m
>
\ ic
\b
c m
)
M I M i a|i.ic ilcn
N i-( '[■ r o d n r
X
14
I (>
I>
"
I
( )ll(
.2
Fig. 7.15: Photograph o f the fabricated m ulti-feedback transim pedance amplifier. T he
chip size is 1125 x 800 p m 2.
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173
am plifier perform ance. A forw ard transm ission gain (S 2 i) o f L8 . 8 dB w ith a 13.3 G H z
bandw idth was m easured. Input and output reflection coefficients w ere better than
-8
dB
o v er the bandwidth o f operation (see Fig. 7.16).
The gain-bandwidth product o f the am plifier calculated to be 118 GHz and is the
highest reported figure for G alnP/G aA s H BT technology. M oreover, the effective
transim pedance gain w as calculated from measured sm all-signal S-parameters and
show ed a flat gain o f 52 dB£2 over a bandw idth o f 13.5 G H z (see Fig. 7.17).
Eye-diagram tests w ere perform ed for the am plifier at 10 Gb/s with a 2 15-1 NRZ
pseudo-random bit sequence (PR BS) using an Anritsu M P1701B pattern generator and a
Tektronix 11801B sam pling oscilloscope. Fig. 7.18 shows the m easured results indicating
very open eye characteristics, thus, proper operation o f the am plifier at 10 Gb/sec input
data. The electrical sensitivity o f the am plifier w as m easured using an Anritsu M P1702A
bit-error rate detector.
Fig. 7.19 shows the bit-error-rate m easured at 10 G b/s N R Z pseudo-random bit
sequence with different w ord lengths. T he 27- l word length show ed a sensitivity o f -19
dBm at 1 0 '' bit-error rate w hile the 2 15-1 w ord length had a low er sensitivity o f -11 dBm.
By w ay o f com parison, InP-based H B T photoreceivers show ed a sensitivity o f -20 dBm
for data rates o f 10 G b/s at a bit-error rate o f 10' 9 [111].
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174
•10
-15
•20
1
Frequency [GHz]
10
Fig. 7.16: M easured S-Param eters o f the m ulti-feedback transim pedance amplifier. S 2 1
o f 18.8 dB with a 13.5 GHz bandw idth was measured. The gain-bandwidth
product o f the am plifier calculated to be 118 G H z and is the highest reported
figure for G alnP/G aA s H B T technology.
50
40
j
TGain=52dB£2— r
| BW=13.5GHz j
30
20
10
0
Frequency [GHz]
Fig. 7.17: Effective transim pedance gain (52 dB£2 over a bandw idth o f 13.5 GHz) o f the
m ulti-feedback am plifier calculated from sm all-signal S-param eter m easure­
ment.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
175
0.8
0.6
>
0.4
00
« 0.2
0
0.2
•#
0.4
••
0.6
0
SO
100
ISO
200
2S0
300
3S0
400
4S0
500
Tim e [nsec]
Fig. 7.18: M easured eye-diagram o f the m ulti-feedback transim pedance am plifier at 10
G b/sec 2 1 5 - 1 N R Z PRBS.
10 Gbit/s
OS to *
•II
-II
-14
-12
A verage Incident Pow er [dBm]
Fig. 7.19: Bit-error-rate o f the m ulti-feedback am plifier as a function o f average incident
pow er m easured at 10 G b/sec N R Z PRBS. T he 27- l w ord length show ed a
sensitivity o f -19 dB m at 10 ' 7 bit-error rate w hile the 2 15-1 w ord length had a
low er sensitivity o f -11 dBm.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
176
7.6 Summary
In this chapter, The design, fabrication and high frequency characteristics o f transimpedance am plifiers im plem ented with the G alnP/G aA s H B T approach w ere described
using various circuit schem es such as com m on-em itter, Cascode, distributed, high gain
m ulti-feedback designs. T he transim pedance negative feedback pream plifier has become
established as a m ethod to obtain high bandw idths w ithout sacrificing optoelectronic gain
o r receiver sensitivity. A bandw idth o f m ore than 28 G H z (70% o f the bit rate) is necessary
to achieve 40 G b/sec for next generation optical com m unication systems.
G alnP/G aA s HBT m onolithic transim pedance am plifiers can be used for short dis­
tance com m unication ( 0 . 8 pm ) such as board-to-board o r chip-to-chip data links but also as
an alternative solution to InP-based technology for long distance com m unication
(1 .3 - 1.5pm) by m eans o f flip chip hybrid m ounted InP photodiodes. A G alnP/G aA s HBT
broadband transim pedance am plifier w hich exceeds 19 G H z was presented using Cascode
design and com pared betw een com m on-em itter and C ascode stage. The large-signal char­
acteristics o f these am plifiers becom e an im portant issue when the front-end pre-am plifier
receives large pow er signals from a photodiode as often occurs in optical receiver systems.
The com m on-em itter based transim pedance am plifier shows a m ore pronounced gain
com pression especially at low er frequencies. The C ascode based transim pedance circuit,
however, shows very sm all gain com pression at high input power. This is m ainly due to
the fact that self-biasing effects resulting from the presence o f large signal input condi­
tions are reduced in this design.
D istributed am plifiers are also good candidates to satisfy the requirem ent o f highbit-rate optical com m unication system s (> 40 G b/sec) due to a num ber o f advantages over
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177
conventional transim pedance am plifiers. H B T DAs have been im proved rapidly due to his
ow n advantages such as low noise and higher input sensitive rather than FETs DAs.
A 3-stage large bandw idth 50 M Hz-27.5 G H z distributed am plifier with a S21 gain
o f 12.7 dB was fabricated using G alnP/G aA s H BT approach. A distributed am plifier with
a Cascode active cell could only provide a gain S 2 1 o f 10 dB over a bandwidth o f 25 G H z
w hile com m on-em itter based designs w ere lim ited in gain as well as bandwidth (S 2j
<
8
dB, BW < 20GHz). The use o f Cascode rather than com m on-em itter gain stage allow s a
higher bandwidth for each individual stage due to suppressed miller capacitance effect in
the Cascode pair.
The bit-error-rate (BER) m easured at 10 G b/s N RZ pseudo-random bit sequence
with tw o different w ord lengths. T he 27- l w ord length showed a sensitivity o f -33 dB m at
10‘ 9 bit-error-rate w hile the 2 15-1 w ord length had a low er sensitivity of -25 dBm . T he
sensitivity o f the distributed am plifier reported in this w ork is among the highest reported
figures.
High-speed optical com m unication receivers often use a high-gain transim pedance
pre-am plifier in conjunction with a photodiode to transform the optical signal into electri­
cal signal. These transim pedance am plifiers are utilized with various technologies such as
hybrid and monolithic HEM T an d H BT based integrated circuits. A high-gain transim ped­
ance am plifier with a transim pedance gain o f 52 d B Q and a bandwidth o f 13.5 GHz is p re­
sented. M ain idea o f this transim pedance design for im proving the gain is that the design
em ployed tw o cascaded com m on-em itter stages w ith dual-feedback netw ork for im proved
bandw idth and gain stability. A forw ard transm ission gain (S 2 i) o f 18.8 dB with a 13.5
G H z bandwidth was m easured. Input and output reflection coefficients w ere better than
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-8
178
dB over the bandwidth o f operation. The gain-bandwidth product o f the am plifier calcu­
lated to be 118 G H z and is the highest reported figure for G alnP/G aA s H BT technology.
M oreover, the effective transim pedance gain was calculated from m easured small-signal
S-param eters and show ed a flat gain o f 52 dB Q over a bandw idth o f 13.5 GHz.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
CHAPTER VIII
ANALYSIS AND CHARACTERIZATION OF
HIGH POW ER G a ln P /G a A s HBTS
8.1 Introduction
Pow er amplifiers (PAs) w ith low cost and high power-added efficiency are needed
for current mobile com m unication system s. HBTs are the m ost suitable devices for such
applications due to their high gain at low bias voltage as com pared to the silicon bipolar
transistor or the silicon M O SFET and its operation with no negative voltage supply as
com pared to the G aA s M ESFET. H BTs also offer several advantages over other solid-state
devices in terms o f pow er density (W /m m , m W /pm 2), operating voltage, linearity and col­
lector efficiency. H BTs have dem onstrated strong potential for high-power, high-efficiency
microwave solid-state am plifier applications [118], [119], [122], [123]. The pow er perfor­
m ance o f H BTs is lim ited by therm al rather than electrical constraints. Thus, careful ther­
mal design to control the m axim um junction tem perature is a key to realize the full
microwave potential o f GaAs H BTs.
HBTs for pow er applications have several advantages over M ESFET and H EM T and
can be sum m arized as follows: [1 17]-[120]. (1) H igh pow er density operation originating
179
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180
from higher current handling capability. This provides much sm aller device size with high
input im pedance and higher output pow er com pared to M ESFET amplifiers. HBT input
and output im pedances have sm aller reactive com ponent than F E T counterparts at the
sam e frequency and pow er levels. T his makes it easier to m atch im pedance over a larger
bandw idth and greater im pedance ratios. The output m atching netw ork becom es sim pler
due to the higher output im pedance. (2) High pulse-up capability. 3-4 dB higher output
pow er than C W m ode for short (few ps) pulses. (3) Well controlled breakdown voltage
with collector epitaxial design (thickness and doping). Unlike M ESFETs and HEM Ts, the
breakdow n voltage is independent o f input voltage and is insensitive to device processing
steps. (4) T he transconductance increases with collector current and is typically much
higher than a M ESFET at com parable bias. (5) High efficiency Class B and C operation
w ithout sacrificing output pow er perform ance and needing reduced pow er supply voltage
[121] -[124]. (6 ) Extrem ely low leakage current requiring no extra DC switch (unlike
M ESFET) to turn o ff the pow er supply in standby mode. T hese features o f the HBTs
together with the greater com pactness achieved due to higher pow er density, and all-opti­
cal lithography processing allow s the fabrication o f the predictable and reproducible
devices for the pow er applications.
Among H BTs, there has been a considerable interest in G alnP/G aA s HBTs as active
devices in low -phase noise oscillator and pow er amplifiers. Since G alnP/G aA s H BTs can
be fabricated w ith highly selective etchants, im proved yields and hom ogeneities are
expected in com parison to A lG aA s/G aA s HBTs. In contrast to the G alnP/G aA s material
system , a delicate base etch m onitoring is required in the A lG aA s/G aA s material system.
E xcellent DC and R F results have been dem onstrated for G alnP/G aA s HBTs. Recently,
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181
G ood pow er perform ance o f 2 W (4.0 W /m m ) w as dem onstrated at X-band using 2 x 500
p m 2 G alnP/G aA s HBTs grown by M OCV D [124]. G alnP/G aA s HBTs were also studied
for L-band pow er amplifier applications and dem onstrated 2.7 W (2.1 W /m m ) under class
AB operation using 64 finger 2 x 20 p m 2 H B Ts at a collector bias (VCE) o f 3.5V [125],
The reduced toxicity growth approach used for the developm ent o f power HBTs described
in this w ork offers a good alternative to the traditionally used M OCV D approach. G alnP/
G aA s H BTs grown by C B E using reduced toxicity precursors such as TBA , T B P have
dem onstrated excellent high speed/frequency perform ance as discussed in various reports
on discrete devices as well as transim pedance amplifiers [95], [126], [127].
In this chapter, power analysis and characterization o f single-finger (2 x 30 pm 2)
and m ultifinger em itter (10 finger 2 x 20 p m 2) G alnP/G aA s H BTs grown by C B E technol­
ogy are described. Devices were investigated at
was varied between
8
8
G H z and the collector voltage (VCE)
, 10 and 12 V to perm it class B operations. A maximum pow er of
1.08 W (5.4 W /m m ) using 10 finger 2 x 20 p m 2 G alnP/G aA s H B Ts is reported under class
B operation (VCE=10 V).
8.2 Power Measurements using On-Wafer Load-Pull System
O n-w afer pow er m easurem ents for H B Ts w ere perform ed using a load-pull system
with electrom echanical tuners by FO C U S MICROWAVES. The m easurem ents w ere per­
form ed at
8
GHz (X-band) w ith com puter-controlled FO C U S tuners and CA SCA D E sta­
tion to allow on-w afer characterization. Fig. 8.1 shows the setup for pow er measurement
o f G alnP/G aA s HBTs. The input and output tuners are connected to the base and collector
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182
Power Meter
A
I
B»
Bias Supply
Input
Timer
IEEE 488 Bus
Output
Timer
Timer Control Bus
Computer
Fig. 8.1: A utom ated on-w afer Load-Pull system setup for pow er m easurem ent o f HBTs.
term inals o f the HBT, respectively. The bias tees provided the biasing voltage o f the base
and collector term inals. The input RF signal was m onitored using a -20dB coupler while
the H B T output pow er was fed into the load tuner w hich was connected through a bias tee
to a pow er meter. The source pow er was controlled by com puter to allow fo r variable HBT
input powers. A critical limitation o f the load-pull m easurem ent system is the maxim um
reflection coefficient (|F|) which is determ ined after calibration. D ue to various losses in
the test setup such as adapter between the tuner and device ports and limitation o f the tun­
ers, the m axim um |r | at the device levels was lim ited to 0.8. The entire system is fully
com puter controlled for m easurem ent autom ation and accuracy. A fter system calibration,
the system program can effectively control the device bias conditions, input power, source
im pedance, load im pedance and autom atic load-pull contour m easurem ent. T his program
can also m easure the device average current, output pow er (Pout) and pow er gain (G). The
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183
power-added-efficiency (PAE) is calculated using the measured pow er gain (G) character­
istics and by taking into account the power dissipated in the collector, as well as, base ter­
minals. CW pow er characteristics were m easured under constant
v c e » V BE
bias at 8 G H z
for both the single finger 2 x 30 pm 2 and 10 finger 2 x 20 p m 2 HBTs.
8.3 High Power Density of Self-aligned GalnP/GaAs HBTs
8.3.1 motivation
G alnP/G aA s heterojunction bipolar transistor (H BT) technology offers several attrac­
tive features over traditional A lG aA s/GaA s HBTs in terms o f manufacturing, high speed,
high reliability[93], [35], [23], [84], [129].
The pow er characteristics o f G alnP/G aA s HBTs also appear to be promising. G ood
power perform ance o f 2 W (4.0 W /mm) was dem onstrated at X-band using 2 x 500 p m 2
G alnP/G aA s H BTs grown by M O CV D [124]. G alnP/G aA s H BTs were also studied for Lband pow er am plifier applications and dem onstrated 2.7 W (2.1 W /mm) under class AB
operation using 64 finger 2 x 20 pm 2 H BTs at a collector bias (VCE) of 3.5V [125]. The
reduced toxicity growth approach used for the developm ent o f pow er HBTs described in
this w ork offers a good alternative to the traditionally used M OCV D approach. G alnP/
GaAs H B Ts grow n by Chem ical Beam Epitaxy (CBE) using reduced toxicity precursors
such as TBA, TB P have dem onstrated excellent high speed/frequency perform ance as dis­
cussed in various reports on discrete devices and transim pedance amplifiers [126], [95],
[127].
Fig. 8.2 shows the current-state-of-art o f pow er density and power-added-efficiency
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
184
O
7
'E
A U o f M (1999)
»
6
E
i
x U o f M (1999)
, 5
>>
■ T I (1994)
•s
e *
❖ Bell Lab. (1993)
3
u
£
o 2
0- *
1
I
D aim ler-B enz (1995) +
0
20
30
40
50
60
70
80
PAE [%]
Fig. 8.2: The current-state-of-art o f pow er density and power-added-efficiency (PAE) for
G alnP/G aA s H BTs at X band m easurem ent. The pow er density by U o f M ich­
igan shows the highest value am ong the published values o f power density for
G alnP/G aA s HBTs.
(PAE) for G alnP/G aA s H B Ts at X band measurement. The pow er density by The Univer­
sity o f M ichigan shows the highest value am ong the published values o f pow er density for
G alnP/G aA s HBTs.
In this study, the large-signal characteristics and the im pact o f different large signal
param eters on the pow er perform ance o f the HBTs are analyzed using a sim plified analyt­
ical H BT model in order to obtain a better understanding o f the physical trends governing
the H B T pow er characteristics. T he results obtained were com pared with those found
from a G um m el-Poon large-signal m odel developed at the U niversity o f M ichigan [131].
High pow er and high pow er density experim ental characteristics are reported for single­
finger (2 x 30 pm 2) and m ultifinger em itter(10f-2 x 20 p m 2) G alnP/G aA s HBTs grown by
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185
HBT 1
HBT 2
Thickness
Doping
GalnAs emitter cap
300
lxlO19
GalnAs grad 0 -> 0.5
250
lxlO19
GaAs emitter contact
2000
lxlO19
AlxGa,.xAs
(x:0->0.22)
380
5xl018
GalnP emitter
100
GalnP emitter
Thickness
Doping
GaAs emitter contact
1500
lxlO19
undoped
GalnP emitter
700
lxlO19
400
5xl016
GalnP emitter
1500
3xl017
GaAs Base
500
6xl019
GaAs Base
600
5 xl019
GaAs collector
7000
1.5x1016
GaAs collector
7000
1.5xl016
GaAs subcollector
700
lxlO19
GaAs subcollector
700
lxlO19
GalnP etching stop
100
lxlO19
GalnP etching stop
100
lxlO19
GaAs subcollector
7000
lxlO19
GaAs subcollector
7000
lxlO19
Table 8.1: Layer structure o f G alnP/G aA s H B Ts with different pow er perform ance.
CBE. The devices were investigated at
8
G H z and the collector voltage (VCE) was varied
betw een 8 ,1 0 and 12 V to perm it class B operation. A maxim um pow er o f 1.08 W (5.4 W /
m m ) using 10 finger 2 x 20 p m 2 G alnP/G aA s H B Ts is reported under class B operation
(VCE=10 V).
8.3.2 Layer Structure and Device Performance
T he G alnP/G aA s layers w ere grow n by C B E using reduced toxicity precursors (TBA,
TBP). Two different H BT layer designs w ere investigated, as shown in Table 8.1. T he first
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186
layer design called H B T 1 consists o f a com positionally graded 5 x 10l 7 cm*3, 380
A lG aA s (Al: 0 -> 0.22) layer followed by undoped 100
A
A thick
thick G alnP which serves in
reducing the spike created in the conduction band o f the A lG aA s-G alnP heterointerface
and enhance the device speed by reducing C BE as described in earlier reports [126], [41].
A 5
x
10 1 6 cm*3, 400
A
thick G alnP em itter layer w as used between the undoped G alnP
and the p-doped (4 x 1019 cm*3) GaAs base. The collector consists o f a 7000A (1.5 x 1016
cm '3) G aA s layer followed by a 700A (1 x 1019 c m '3) G aA s subcollector. This layer was
em ployed to obtain the high power perform ance described in this section.
The other H B T layer structure, referred to as H BT2 has identical sub-collector and col­
lector design. It w as used to for com parison with the first layer and provided the m eans of
determ ining the factors leading to the good perform ance. The base layer o f HBT2 has
slightly different design than HBT1 with a 600A thick base doped at 5 x 1019 cm*3. The
em itter layer design o f H BT2 consists o f 1500A, 3 x 1017 cm *3 G alnP em itter followed by
700A, 1 x 101 9 cm *3 G alnP em itter contact and 1500A, 1 x 1019 cm *3 G aA s em itter con­
tact. N o InG aA s contact layer was used for em itter therefore it is expected that the em itter
parasitic access resistance o f HBT2 is higher than that o f HBT1.
A key feature o f collector design in both H B T structures is the G aln P etch stop layer
introduced betw een the GaAs collector and subcollector. This w as used to form a laterally
etched undercut profile and led to reduction o f the CBc capacitance and thus im proved fre­
quency perform ance [23]. Self-aligned H B Ts w ere fabricated using sim ple all w et based
chem ical etching w hich m inim ized layer dam age and device degradation. The 10 finger 2
x 20 p m 2 devices reported here consist o f a 5 x 2 array o f 2 x 20 p m 2 em itter fingers. An
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187
SEM photograph o f the fabricated 10 finger G alnP/G aA s HBTs is shown in Fig. 8.3.
8.3.3 DC and RF Characteristics
Typical D C and R F characteristics o f 1 finger 2 x 30 p m 2 HBTs using C B E growth and
reduced toxicity precursors were reported previously by the authors [126]. Fig. 8.4 shows
the com m on-em itter I-V characteristics o f a 10 finger 2 x 20 p m 2 G alnP/G aA s H BT fabri­
cated using HBT1 layer. A D C gain o f S3, base ideality factor o f 1.55 an d collector ideal­
ity factor o f 1.10 and a collector-em itter breakdown voltage exceeding 17V w ere obtained.
The offset voltage (V 0 ffset) was about 0.3 V for all HBTs independent o f their geometry.
The small signal high frequency characteristics o f 10 finger 2 x 20 p m 2 G alnP/G aA s
HBTs were m easured using on w afer tests and an HP8510B netw ork analyzer. T he current
gain cutoff frequency (fT) extrapolated from the m easured IH2 1 I and the m axim um oscilla­
tion frequency (fmax) evaluated from the M axim um available gain (MAG) were 44 G Hz at
VCe = 3 V, Ic = 84.6 m A for HBT1 layer design. fT and f , ^ for the 10 finger 2 x 20 p m 2
H BT fabricated using HBT2 layer w ere 32 and 43 GHz, respectively. The small signal
gain o f the devices (M AG) was found to be at
8
G Hz in the range o f 14 dB to 17 dB for
HBT1 layer and between 10 dB to 12 dB for HBT2 layer depending on Ic and V CE bias.
8.3.4 HBT Large-Signal Modeling and Analysis
The im pact o f the large-signal param eters on the pow er perform ance was studied using
a simplified analytical large signal H B T equivalent circuit model shown in Fig. 8.5. The
simplification o f the large signal H B T equivalent circuit model results in solutions th at are
not very accurate, but allow a first order prediction o f the pow er perform ance trends as a
function o f device physical param eters. M oreover, the use o f the analytical model perm its
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188
Fig. 8.3: SEM photograph o f 10 finger 2 x 20 p m 2 G alnP/G aA s HBT.
20
Base current
Start: OpA
16 ' Stop: 350p/
14 . Step : 50pA ,
18
12
10
6
4
2
0
-2
0
0.5
1
1.5
2
2.5
3
3.5
4
v CErvi
Fig. 8.4: Com m on-em itter I-V characteristics o f 10 finger 2 x 20 p m 2 G alnP/G aA s HBT.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
189
CC
Collector
Base
I VOUT
so a
BE
Emitter
Fig. 8.5: Simplified analytical large signal H BT equivalent circuit model.
fast convergence and short com putation time. T he analytical model w as em ployed by
assum ing single frequency (fundam ental com ponent o f 8 GHz) excitation. Comparison of
the results obtained w ith this model with those simulated using H P-EESOF/LIBRA
showed good agreem ent w ith pow er levels within 1 dB when the loss o f the pow er in har­
m onics is considered. T he m odel consists o f a source with pow er Psource and correspond­
ing voltage V s, source (Zs ) and load (Z^) im pedances representing the input and output
tuners, base
(RB)>em itter (Re) and collector (R^) resistances, and base-em itter (CBE) and
base-collector (CBC) capacitance. F o r simplicity, C BC and CBE were assum ed to be con­
stant in the analytical model.
U sing sim ple node and m esh analysis, the following seven equations can be extracted to
analyze the estim ated pow er perform ance.
vcc + vo u t
=
" 5 0 /c
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(8 .1 )
190
VCC + v O U T ~ v 2 =
(8 -2 )
*CZ L
v 2 ~ v l = ( ,C “ a , )^BC
V 1
(8.3)
= ( Z£ - , )Z g £ +
(8.4)
v5 = JB(5 0 + Z 5 + /eB) + v,
(8.5)
*C + *B = *£
( 8 .6 )
* = i isoC* P ( ( v \ - i R E ) / k T )
(8-7>
where Vc c applied collector voltage, a is the base transport factor, v o u t *s output voltage
and i is the diode current through the base-em itter junction.
values o f
c BC
Z BC
and Z BE are im pedance
and C B£ at 8 GHz. Solution o f the above system o f nonlinear equations was
possible by an iterative approach using MATLAB. T he solution w as considered to con­
verge w hen the error was sm aller than
Fig.
8
1 0
'4.
.6 (a) shows the calculated output pow er as a function o f resistance and capaci­
tance values under two different input pow er excitation condition using the analytical
model. T he sim ulated values are w ithin ± ld B m from the values predicted by LIBRA and
the observed trends are similar. At high input pow er levels, the im pact o f the em itter and
collector resistances (RE, R ^) is m ore pronounced due to the m ore pronounced effect o f
the knee voltage ( V ^ ^ ) on the signal swings. Sim ilar trends are observed fo r R^.
In general, the m axim um output pow er can be expressed as follows;
n
_ ^max ( B V c e o ~ V knee)
g
r out, max ~
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
,Q
191
27
26
Re ( Anal:
LIBRA:
Rc ( Anal:
LIBRA:
25
I 24
r
S
22
21
20
10
15
R e >r c 1 ^ ]
25
20
(a)
25
24
CBC
23
C BE
'BE
ftf 20
BC
Analytical model
19
Plas 20 dBm
Pin =10 dBm
18
17
0
20
40
60
80
100
120
140
160
Capacitance [fF]
(b)
Fig.
8
.6 : T he sim ulated output pow er and associated gain perform ance as functions o f
device resistances and capacitances (RE, R c, C Bc , C BE) under class B opera­
tion (V BE = 0.74 V ,V CE = 10 V ) using the analytical m odel and LIB RA largesignal H B T model.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
192
w here 1 , ^ is the m axim um collector current, BV CEO is the break down voltage and
is the knee voltage o f the HBTs. As expected, the knee voltage ( V ^ ^ ) in the I-V charac­
teristics is increased at high RE and
values. This leads to limited output voltage in
H BTs with high V ^ g and results in degradation o f the output power as estim ated from
Eq. ( 8 .8 ) and sim ulated by the results o f Fig. 8 .6 . It should also be noted that at given bias,
the degradation becom es m ore im portant at high Pjn values where the signal waveforms
approach the knee voltage region o f the I-V characteristics.
The im pact o f base-collector capacitance (CBc ) on the output power shows a m ore pro­
nounced effect than RE, Rc under small input pow er level conditions as shown in Fig.
8
.6 (b). Both C BC and C BE present m inim um influence on the output pow er characteristics
at large input pow er levels (P in=20dBm ). However, at sm aller input pow er levels
(Pjn=10dBm), C BC influences severely the output pow er characteristics leading to a reduc­
tion o f Pout at large C BC values. The larger im pact o f C Bc under small-signal conditions is
due to the influence it has on the transistor gain. Since the output pow er is strongly influ­
enced by transistor gain under sm all-signal excitation, while it is set by DC bias param e­
ters such as B V ECO, Vjyjgg under large signal conditions, it is reasonable to find a larger
im pact o f C Bc under the form er excitation. T he im pact o f R B on the pow er perform ance
w as found to resem ble th at o f C BC.
Fig. 8.7 shows the m easured and sim ulated characteristics Pout vs. Pin and G vs. Pjn o f
the 1 finger 2 x 30 Jim 2 fabricated device (H BT1) under 10V o f
bias. A discussion on
the pow er perform ance dem onstrated by this device together which dependence on VCE
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
193
ST 60
a tV CE=10V,VBE=0.74V
Simulated
Measured
lfinger 2 x 30pm
E
3 io
6
8
10
12
14
16
18
20
Pin [dBm]
Fig. 8.7: M easured and sim ulated pow er perform ance o f 1 finger 2 x 30 n m 2 G alnP/G aA s
H BTs at VCE=10V, VBE=0.74V and X-band.
bias is presented in Sec. 8.3.5. The results dem onstrate good agreem ent between theory
and experim ent and proved confidence in em ploying the model described in this section
for studying the im pact that individual device param eters have on the power characteris­
tics.
The dynam ic load lines w ere also sim ulated using the com plete H BT large-signal model
in LIBRA . This perm itted evaluation o f output voltage and current handling under various
Pin signal conditions. Fig.
8 .8
shows the dynam ic load sim ulation for the m easured 1 fin­
ger 2 x 30 iu n 2 G alnP/G aA s HBTs. T he m axim um collector current and voltage in this
device reach 170 mA and 22 V for Pin = 18dBm under optim um source and load im ped­
ance m atching conditions; T he high V CE voltage sw ing o f 22V arises mainly from the
reactive com ponent o f the input and output tuner im pedance. T he calculated m axim um
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
194
200
lB Start : 0 mA
S t o p : 0.3 6 mA
S t e p : 0 .0 3 mA
'in = 18 dBm
:2dBm
'T 100
Pin = 6 dBm
10
15
v CEm
Fig.
8
.8 : Dynamic load pull sim ulation from the m easured and extracted 1 finger 2 x 30
pm G alnP/G aA s H BTs large signal param eters.
output power
( P ou t, ma x )
fr° m this figure is in good agreem ent with the measured output
pow er (see Fig. 8.10) for the sam e bias condition.
8.3.5 HBT Power Measurements and Analysis
O n-w afer pow er m easurem ents w ere perform ed for H B Ts o f different geom etries using
a load-pull system with FO C U S electrom echanical tuners. The input R F signal was moni­
tored using a -20dB coupler and the output pow er from the H BTs w as fed into the load
tuner which w as connected through a bias tee to a pow er meter. T he power-added-effi­
ciency (PAE) w as calculated using m easured pow er gain (G ) characteristics and by taking
into account the pow er dissipated in the collector, as well as, base term inals. CW pow er
characteristics were m easured under constant V BE bias at
8
G H z for both the single finger
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195
2 x 30 p m 2 and 10 finger 2 x 20 p m 2 H BTs.
Fig. 8.9 shows the m easured output pow er (Pout) and power-added-efficiency (PAE)
characteristics as a function o f the R F input pow er (Pin) for the 10 finger 2 x 20 pm 2
device fabricated on HBT1 layer. The m easurem ents were perform ed at collector bias
(V ce) o f
8
and 10 V and VBE o f 0.74 V. T h e initial DC collector current was 0 m A before
any input pow er was applied and the collector current was found to increase in the pres­
ence o f increased levels o f im pact pow er excitation. T he average collector current was
found to vary from 131 m A at P in = 16 dB m to 193 mA at Pin = 23.4 dB m at VCE = 10 V
suggesting class B operation. U nder these conditions, the 10 finger 2 x 20 p m 2 device
delivered 1.08 W (30.33 dBm ) o f m axim um output pow er corresponding to a pow er den­
sity o f 5.4 W /mm. To our knowledge, this result is the highest value o f pow er density ever
■
•
■ ■ 10V
— 8 V
out
£ 29
5 28
PA E
16
18
20
22
24
P to [dB m ]
F ig. 8.9: M easured CW output pow er and PAE as a function o f input pow er for 10 finger
2 x 20 pm 2 G alnP/G aA s H B Ts a t 8 GHz. T h e m easurem ents w ere perform ed
under different collector bias conditions (VCE= 8 ,1 0 V ).
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196
28
PAE
26
f=
24
fifi
8
GHz
f—
22
S
«« 20
_a
o
18
g
S'
out
16
■
14
8
10V
V
-
16
14
12
10
8
Pin
20
18
20
[dBm]
Fig. 8.10: M easured CW output pow er and PAE as a function o f input pow er for 1 finger
2 x 30 u rn 2 G alnP/G aA s H BTs at X-band. The m easurem ents w ere perform ed
under different collector bias conditions (VCE= 8 , 10, 12V) with a constant
V BE (0.74V).
reported for G alnP/G aA s H BTs at X-band.
The pow er-added-efficiency (PAE) was m axim um (49% ) at an output pow er o f 0.65 W
(3.3 W /m m ) and a VCE bias o f
8
V, while it had a value o f 44% under m axim um output
pow er conditions o f 1.08W (5.4 W /m m ) at V CE= 10 V. T he corresponding linear gain o f
the devices w as 9.4 dB and 6.9 dB at
8
V and 10 V respectively. The associated pow er
gain (G) varied from 11.3 to 5.9 dB for VCE=
8
dBm and from 11 to 6.9 dB for VCE= 10 V at
V at
8
8
G H z as Pin varied from 15.8 to 23.2
G H z as Pj„ varied from 16 to 23.4 dBm
respectively.
Fig. 8.10 illustrates the m easured output pow er and PAE as a function o f P|„ and bias
voltage VCE for a 1 finger 2 x 30 p m 2 device using HBT1 layer at 8 G H z. T he V CE bias
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197
was selected to be
8
, 10, 12
V and D C collector current (Ic) was set to 0 m A to perm it
class B operation; a constant base-em itter voltage (V BE) o f 0.74 V was used for these
tests. The average collector current was found to vary from 16mA at P in = 8.9dBm to
28m A at Pin =18.8dBm a t
ulations o f Fig.
8 .8
Vrf?=10V- This corresponds according to the dynam ic load sim ­
to m axim um current and voltage swings o f 170mA and 22V respec­
tively. The highest PAE achieved was 53.6% with a corresponding output pow er (Pout) o f
21.3 dB m (135 mW ) at V CE =
8
V. A m axim um Pout o f 23.2 dBm (209 mW ) with PAE o f
47.2% was obtained at VCE = 12 V. The m easured perform ance corresponds to the highest
output pow er reported for single finger 2 x 30 p m 2 G alnP/G aA s HBTs. The results indi­
cate that the highest PAE is obtained at 8 V while the largest Pout is found at a higher col­
lector bias (VCE), condition o f 12 V.
As m entioned earlier, the sm all-signal gain (M AG) o f HBT1 is higher than that of
HBT2 by an average value o f 4 dB under sim ilar bias conditions. This difference in M AG
is also reflected under large-signal conditions as discussed next. Fig. 8.11 shows the pow er
perform ance for lOf 2 x20pm 2 H BTs fabricated on HBT1 and H BT2 layers under identi­
cal bias conditions in class B operation (VCE=8V, v BE=o .74V). The optim um source and
load tuner settings for these devices w ere sim ilar and equal to Z s= 8 + jl2 Q , ZE=21+j25Q
for HBT1 and Z s=8+jl5£2, ZL=16+j38£2 for HBT2. A s can be seen from the figure, the
output pow er and gain o f the device fabricated using the HBT1 layer are about 3 dB higher
than those o f the device fabricated on H BT2 design. The high-frequency current gain
(H 2 1 ) o f these tw o devices is show n in the inset o f Fig. 8.11 and indicates that the devices
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198
out
- HBT 1
■ HBT 2
Power Gain
VCe =8V, Vbe=0.74V at f=8GHz
16
18
20
lOf 2 x20(im
22
24
Pln [dBm]
Fig. 8.11: The m easured Pout, Pow er G ain and current gain as function o f P in for 10 fin­
ger 2 x 20 fim 2 G alnP/G aA s HBTs on HBT1 and H BT2 layer structures.
have sim ilar current gain characteristics as the input power (Pjn) is varied.
This suggests that the difference in the pow er performance o f the tw o H BTs is related to
the elements, determ ining their sm all-signal pow er gain (M AG) and not their large-signal
current gain (H 2 i). F urther analysis o f these H BTs revealed that their em itter access resis­
tance (Re) and knee voltage ( V ^ g ) are the prim e factors contributing to the difference in
their pow er perform ance. W hile HBT1 had a sm all em itter access resistance (R e =1-2£2)
and knee voltage ('Vkriee= l V), the corresponding values for H BT2 w ere Re=6.5£2 and
Vknee= l -4V. M oreover, since the knee voltage is m ainly affected by RE+ R o it appears that
R E is the m ain contributor to the difference in pow er characteristics o f these tw o HBTs.
T he key large-signal param eters o f HBT1 and H BT2 shown in Table 8.2 confirm these
observations.
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199
HBT 1
HBT 2
Param eter
Value
Value
Re ( « )
1 .2
6.5
R b (&)
2
1 .8
R c (Q )
2.5
2.7
DC gain,max
55
50
C JC (pF)
0.3
0.3
C JE (pF)
0.42
0.44
Vknee (V ) a*
1 .0
1.4
(Jc =3.13K /cm 2)
Table 8.2: Extracted large-signal param eters for tw o different HBTs with lOfinger
2 x20pm 2 as shown in Table 8.3.
The sim ulated and m easured pow er perform ance o f the 1 finger 2 x 30 n m 2 G alnP/
G aA s H B T using HBT1 layer w ere presented in Fig. 8.7. As in case o f the multi-finger
H BT design, the pow er perform ance o f this device is largely influence by its em itter
access resistance value which in this case equals 5Q. O verall, the obtained results and
analysis o f power characteristics show state o f the art pow er perform ance from the
reported G alnP/G aA s HBTs.
8.4 Summary
This chapter focused on pow er perform ance and analysis o f self-aligned G alnP/G aA s
H BTs. Large-signal analysis and high pow er characterization o f G alnP/G aA s H eterojunc­
tion B ipolar Transistors (HBTs) grown by Chem ical B eam Epitaxy (CBE) are dem on­
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200
strated at X -band. The im pact o f different large signal param eters on the power
perform ance o f HBTs has been analyzed using th e large signal H BT model based on
H PEESO F-LIB R A and simplified analytical H B T model calculated by MATLAB. From
the analysis, the output pow er is lim ited by Cbc* R b at l°w input pow er and RE and Rc at
high input power. Based on the accurate large signal HBT m odeling, the on-w afer power
m easurem ents o f G alnP/G aA s H BTs were perform ed at 8 GHz. A m axim um output pow er
o f 1.08 W (5.4 W /m m ) with PAE o f 44% w as obtained for 10 finger 2 x 20 |tm 2 at
VCE=10 V under class B operation, w hile m axim um Pout was 23.2 dB m (209 mW ) with
PAE o f 47.2% at VCE=12 V and class B operation for 1 finger 2 x 30 |im 2 HBTs. To our
know ledge, the pow er density for
1 0
finger
2
x
2 0
nm 2 and output pow er for
1
finger
2
x
30 |im 2 H BTs corresponds to the best perform ance reported for discrete G alnP/G aA s
H BTs at X -band.
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CHAPTER IX
CONCLUSIONS AND FUTURE WORK
9.1 Conclusions
The w ork in this thesis has been aim ed to im provement of high speed and high
pow er perform ance for self-aligned G alnP/G aA s HBTs and development o f broad band
transim pedance amplifiers for near future high bit-rate (up to 40 Gb/s) com m unication
system s. First, the fabrication technology based on all wet based chemical etching tech­
nology which is simpler and m ore reliable than dry etching technology was developed.
T his w ork begins with optim ization o f ohm ic contact for base and em itter cap layer. N i/Cr
for resistor and AI2 O 3 for M IM (M etal-Insulator-M etal) capacitor were chosen and opti­
m ized for passive lum ped elem ents o f M M IC fabrication. The adhesion between metal
(especially Au) and dielectric m aterial w as im proved by adding a Ti (500 A) layer prior to
dielectric deposition. NH 4 O H: H 2 0 2: H 20 solution for G aA s and pure HC1 for G alnP w ere
chosen and investigated for selectivity and etching profile. A m ore advanced technology,
called Laterally Etched Undercut (LEU ) technology using w et base etching technique is
illustrated to reduce the total base-collector capacitance (CBC). LEU technology dem on­
strated an fT o f 58G Hz and f , ^ o f 100GHz at Ic=20m A , VCE= 2 .5V. This corresponds to
201
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202
an fx increase o f 11% and
increase o f 25% as a result o f using LE U technology.
A fter the process optim ization for the H BTs and M M ICs, a basic analysis o f G alnP/
GaA s H B T properties, such as abrupt vs. graded em itter-base junction, DC current gain
vs. cutoff frequency, and im pact o f em itter size on microwave perform ance, was carried
out.
U sing the optim ized H B T process technology and ohm ic contact, high speed G alnP/
G aA s HBTs w ith reduced em itter transit tim e w ere designed, fabricated and successfully
characterized. A tunneling em itter design using a thin wide bandgap (300A G alnP) em itter
layer w as used am ong other design to satisfy these requirem ents. The enhanced fx charac­
teristics at high collector current o f this device are mainly attributed to the reduction o f the
em itter transit tim e. An em itter transit tim e reduction by 35% (from 0.51 to 0.33 psec) was
found by using tunneling rather than conventional H BT designs. Tunneling through a thin
w ide band-gap em itter layer im proves the transconductance (gm) while avoiding consider­
able base-em itter capacitance ( C ^ ) degradation. The RBE for tunneling em itter design is
im proved by 108% (from 2.4 to 1.5S2) w hile C BE for tunneling em itter design is increased
by 54% (from 162 to 250 fF) at VBE= 1.49 V.
A nother high speed perform ance design, using self-aligned com posite em itter
A lG aA s-G alnP/G aA s also proved to perform well. HBTs using this design were fabri­
cated and successfully analyzed. The H B Ts showed reduced em itter-base capacitance
(CBE) and en hanced fT perform ance. T hese results agree w ith the sim ulated characteristics
w here fp w as m easured to be im proved from 44 G H z to 62 GHz by using o f the com posite
em itter design. A lso, C BE o f the com posite em itter design H B T is at least 3 tim es lower
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203
than that o f th e conventional em itter design H B T under high Ic (Jc ) bias operation condi­
tions.
In addition, H igh speed G alnP/G aA s D ouble HBTs were designed, fabricated and suc­
cessfully m easured using doped G alnP spacers between the G aA s base and the G alnP col­
lector to reduce the conduction band discontinuity. Unlike G alnP/G aA s single H BTs, it is
found that the collector o f D H B Ts can be etched m uch faster along the [010] rather than
[011] direction. T he DC and microwave properties w ere obtained by characterizing 5 x 40
pm single em itter finger devices in com m on-em itter configuration and the corresponding
breakdown voltage (VCEO) w as found to exceed 26V. The current gain cutoff frequency
(fx) was 28 G H z and the associated m axim um oscillation frequency (fmax) was 63 GHz.
The im proved D C current gain and fT characteristics obtained for the D H BT are mainly
attributed to the reduction o f the conduction-band discontinuity using a highly doped
G alnP spacer layer w hich results in im proved carrier transport at the heterointerface.
Moreover, the im proved fmax benefits not only from the high fT values but also from the
reduction o f th e base-collector capacitance (C BC) through lateral etching undercut.
The im portance o f the collector metal choice in H BT D C , RF, pow er perform ance was
described. The presence o f unintentional collector contact barrier leads to a change in the
Ebers-M oll m odel and affects the collector offset voltage due to the barrier height
(q<(>g=0.26V fo r Tl/Pt/A u). T he total collector current is reduced by the collector contact
barrier and leads to a reduced D C gain (A{3=46) for HBTs w ith Ti/Pt/A u collector metal.
The RF an d pow er perform ance o f the H B T w ith Ti/Pt/A u is influenced by the presence of
a large R c as a result o f the collector contact barrier. The m axim um output pow er for
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204
H BTs with Ni/Ge/Au m etal is 18.4 dB m w hile the peak PAE is 63.1%.
A fter optimization o f various H B T designs, the passivation and reliability characteris­
tics o f G alnP/G aA s H B Ts were studied. In this work, G alnP/G aA s H BTs before and after
passivation were investigated and com pared in term s o f D C and microwave perform ance.
Passivated HBT devices were obtained by SiC> 2 (4500 A ) thin film deposition at 300 °C by
m eans o f PECVD system. T he selected devices were 2 x 10 pm 2 single em itter and 2 fin­
ger 5 x 10 p m 2 em itter HBTs. The microwave perform ance is almost the sam e before and
after passivation except in the low frequency region (around 1GHz) which is dictated pri­
marily by DC gain characteristics.
The reliability characteristics o f the fabricated passivated and unpassivated G alnP/
GaA s H BT devices have been also investigated and are reported under various bias condi­
tions to evaluate the device life-tim e. Reliability tests w ere carried out for the passivated 2
finger 5 x 10 pm 2 em itter G alnP H BTs with a 4500 A PEC V D Si0
2
layer. The stress test
was continued for 30.5 days and the H B T continued to operate with only 2% o f current
gain degradation despite the rather high current density (40 kA/cm2) used for these tests.
The design, fabrication and high frequency characteristics o f transim pedance amplifi­
ers im plem ented with the optim ized G alnP/G aA s H BT approach are described using vari­
ous circuit schemes such as com m on-em itter, Cascode, distributed, and high gain m ulti­
feedback designs. A G alnP/G aA s H B T broadband transim pedance am plifier which
exceeds 19 GHz is presented using C ascode design and com pared between com m on-em it­
ter and Cascode stage.
Finally, large-signal analysis and high pow er characterization o f G alnP/G aA s H BTs
were carried out at X -band. T he im pact o f different large signal param eters on the pow er
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205
perform ance o f H B Ts has been analyzed using a large signal H BT model. From the analy­
sis, the output pow er is found to be lim ited by C qq, R b at low input pow er and RE and
at high input pow er level excitation. O n-w afer power m easurem ents o f G alnP/G aA s HBTs
were perform ed at 8 GHz. A m axim um output pow er o f 1.08 W (5.4 W /m m ) with PAE of
44% was achieved w ith 10 finger 2 x 20 p m 2 HBTs at V C E = 10 V under class B operation.
Power m easurem ents are presented for single em itter finger 2 x 30 p m 2 devices at various
collector biases (VCE= 8 ,1 0 ,1 2 V). A maximum Pout o f 23.2 dBm (209 mW ) with PAE o f
47.2% w as obtained at VCE= 12 V under class B operation.
9.2 Future Work
Collector-up HBTs and ultra-high speed design H B Ts (>fr= 100G H z) with thin base
and collector layers are good candidates for im proving high frequency performance.
In case o f collector-up HBTs, the order o f the collector-up layer design is reversed
with respect to the em itter-up layer. The collector is topm ost and the em itter is in the bot­
tom as shown in Fig. 9.1. O ne o f the m ost im portant param eters to effect the high fre­
quency H B T perform ance is the base-collector capacitance (CBC). In general, the collector
area is m uch larger than the em itter area for the em itter-up H BTs (for instance, for a 2 x30
pm 2 single em itter finger with both sides at
least
6
2
pm base w idth, the collector area can be at
x 30pm 2), and the lateral etching undercut technology discussed in C hapter II per­
mits reduction o f the extrinsic base-collector capacitance under the base metal. However,
C Ec can also be m inim ized using a collector-up design as shown in Fig. 9.1. A t least a 3
tim es low er CBc value can be achieved in such a collector-up H B T com pared w ith an
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206
Collector metal
B
II lllllllllllllllll D
C
U -------- L
Base metal
1
J
Emitter metal
Fig. 9.1: Schem atic cross section o f the collector-up HBT.
em itter-up, no L E U technology approach. The resulting C BC reduction leads to increased
fmax according to the expression fmax=(fT/8 7 tRBC BC) 1/2- In addition, the reduction o f C BC
can enhance the switching speed o f digital circuits [132], [133].
A lthough several papers have been presented on the fabrication and perform ance of
collector-up H BTs [134], [135], good perform ance has not yet been dem onstrated experi­
mentally. T he m ost im portant process step for the fabrication o f the collector-up H BTs is
the form ation o f a barrier at the extrinsic em itter-base region to suppress the excess base
current th at can be injected from the em itter contact layer into this region. Several
attem pts w ere m ade to suppress electron injection to the extrinsic base such as highly
resistive A lG aA s barrier o r 0 + im plantation between the extrinsic base and the em itter
contact layer [136]. LEU (lateral etching undercut) allows to remove the extrinsic em itter
under the base m etal as discussed in C hapter n. Work on the study o f the etching profile of
the em itter region fo r collector-up H BTs showed that the profile is identical to that of
D HBTs since the m aterial under consideration is in both cases GalnP. A s described in
C hapter IV, etching in the [010] direction o f the G alnP em itter layer is much faster than in
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207
C o llector m etal
1
Em itter
m etal
"
Base metal
/
- r
v
<
Lateral E tc h in y U n d e rc u t
Fig. 9.2: The etching profile o f the G alnP/G aA s collector-up HBT.
the [O il] direction (See Fig. 4.21). As a result, a suitable em itter undercut can not be
obtained along the [O il] direction for G alnP/G aA s DHBTs. Fig. 9.2. shows the etching
profile o f a collector-up H B T along the [010] direction. As can be seen, the bottom em itter
layer is etched laterally. Full undercut rem oving all extrinsic em itter layer was in this case
not possible due to the m ask m isalignm ent. D espite extensive lateral undercut etching for
the extrinsic em itter region, the DC current gain o f the devices was found to rem ain less
than 1. O ne possible reason for this is that excessive surface recom bination current flows
through the large exposed base region under the base, as com pared to the small exposed
base region o f the em itter-up HBTs. U se o f a G alnP thin ledge layer com bined with
another G aA s thin layer next to the base m ay effectively suppress the surface recom bina­
tion current. This modified collector structure m ight im prove the DC current gain and lead
to im proved high frequency perform ance.
U ltra-high speed G alnP/G aA s H BTs with thin base and collector layers are attractive
for high frequency and low pow er applications [29], [56]. The basic idea for ultra-high
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208
Thickness
Type
Doping
GalnAs emitter cap
300
n+
1.3xl019
GalnAs grad 0 -> 0.5
250
n+
1.3xl019
GaAs emitter contact
1000
n+
1.3xl019
GaAs emitter
1000
n-
5xl018
GalnP emitter
1000
n-
2xl018
GaAs Base
300
P+
l.OxlO20
GaAs collector
2000
n-
1.5xl016
GaAs subcollector
700
n+
1.3xl019
GalnP etch stop
100
n+
1.3xl019
GaAs subcollector
7000
n+
1.3xl019
Table 9.1: The layer structure o f ultra-high speed G alnP/G aA s HBTs.
speed HBTs is to reduce the base ( tg ) and collector transit times (Tc), so that im proved
frequency perform ance can be obtained through increase o f fT and consequently f , ^ .
Table 9.1 shows a possible layer structure for ultra-high speed H B T performance utilizing
thin base and collector layers. The base thickness was reduced here by 50% (from 600A to
300A) and 71% for the collector thickness (from 7000A to 2000A ) com pared to conven­
tional HBT designs. O ne side effect o f this design is expected to be a large increase in C g c
due to the small collector thickness (2000A). To com pensate for this side effect, the LE U
technique can be em ployed to reduce the C gc . The reduced base thickness (from 600A to
300A ) can be com pensated by a highly doped base layer (from 4 x
1 0 19
to
1
xlO 2 0 c m '3).
The sim ulated f j and fmaT for this design are 105GHz and 230GHz. First attem pts to study
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209
experim entally this design resulted in f-p and
values o f 50G Hz and 50G Hz respec­
tively which are much sm aller than expected. Moreover, the turn-on voltage (V BE) for
transistor activation was higher than the typical value obtained for conventional H BT
designs (1.65V vs. 1.45). This results from a relatively high em itter doping which was
originally intended enhance the D C current gain (P). The high tum -on voltage leads in its
tum to additional resistance through the base-em itter loop and resulted in degraded high
speed performance. O ne solution to improve the high speed perform ance was mentioned
consists of using a highly doped wide-band gap emitter layer (500A, 5 x 1018 cm'3)
towards the emitter cap side and half lightly doped wide-band gap emitter layer (500A, 3 x
10 1 7 c m '3) toward the base side [137]. It is expected that the tum -on voltage o f such
designes is low due to the lightly doped em itter and the em itter resistance (RE) can be
deceased due to the use o f a highly doped em itter layer. By applying this em itter design to
the above discussed structure, it is believed tha the high speed perform ance o f the G alnP/
GaAs HBTs with thin base and collector layer may be improved.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
APPENDIX
210
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211
Process Sequence for the fabrication of an air-bridge
using Evaporation Technique
PR
Ti (500A)
(2)
PR with overhang
(3)
PR
Etching Ti w ith BHF.
(4)
PR
Evaporation Ti/AiyTi/Au
for an air-bridge
1
(5)
(6)
L ift-off using Acetone.
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
BIBLIOGRAPHY
212
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213
[1]
W. Schokley, U .S . P a te n t. 2 5 6 9 ,3 4 7 ,1 9 5 1 .
[2]
H. Kroemer, ‘T h eo ry o f a W ide-Gap Em itter for Transitors” , P ro c . I .R .E , vol. 45,
pp. 1535-1537,1957.
[3]
A. Y. C o, J. R. Arthur, “M olecular beam epitaxy” , P r o g . S o lid - S ta te C h e m ., vol.
10, Pt. 3, pp. 157-191,1975.
[4]
R. D. D upuis, L. A. Moudy, P. D. D apkus, ’’Preparation and properties o f G aj.
xA lxA s-G aA s heterojunction grown by m etal-organic chem ical vapor deposition”
G a lliu m - A r s e n id e a n d R e la te d C o m p o u n d s , 1st. P h y s . C o n f. S e n . vol. 45, pp. 1-9,
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