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Analog circuits for auditory sound source localization using current mode techniques

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B O STO N UNIV ERSITY
C O LLEG E OF ENGINEERING
D issertation
ANALOG CIRCUITS FOR AUDITORY SOUND SOURCE LOCALIZATION
USING CURRENT MODE TECHNIQUES
by
CHRISTIAN KARL
B.E., U niversity o f A pplied Science, Regensburg, 1998
M .S., B oston University, 2005
Subm itted in partial fulfillm ent o f the
requirem ents for the degree o f
D octor o f Philosophy
2006
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UMI Number: 3214952
Copyright 2006 by
Karl, Christian
All rights reserved.
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©
Copyright by
CH RISTIAN KARL
2006
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Approved by
First Reader
Allyn E. Hubbard, Ph.D.
Professor o f Electrical and Computer Engineering
Second Reader
Mark Horenstein, Ph.D.
Associate Dean o f Graduate Studies and Research
Professor o f Electrical and Computer Engineering
Third Reader
Ronald Knepper, Ph.D.
Professor o f Electrical and Computer Engineering
Fourth Reader
Selim Unlu, Ph.D.
Professor o f Electrical and Computer Engineering
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This dissertation is dedicated to
B arry Thom as Ballard
B.T.B.
1 9 6 0 -2 0 0 4
A celebration o f life
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Acknowledgements
I w ant to express m y gratitude to Professor A llyn E. H ubbard for being m y advisor. In
1997 Professor H ubbard invited me to w ork w ith him in the V LSI Lab. These ten months
in 1997/98 set the direction for my future professional and academ ically life. In the year
2000, Professor H ubbard gave me again the opportunity to w ork w ith him on a challeng­
ing project. I gladly accepted. In these years, Professor H ubbard and his wife M ary H ub­
bard always w elcom ed me w arm ly at their house and over the years, I could see how
their children grew up, graduated from high school and also becam e students at Boston
U niversity. The years w orking with Professor H ubbard w ere very inspiring and support­
ing. Professor H ubbard enabled opportunities that I never could have dreamt o f and I
consider m yself very lucky to know him. Professor H ubbard and I w alked a very long
w ay together and I am looking forw ard to our w ork together in the future.
I sincerely thank Professor K nepper, Professor H orenstein and Professor Unlu for having
served on my dissertation committee. I am grateful for their patience, understanding and
trust. In my last year at BU, I got the opportunity to w ork for Intel. W ithout their faith in
m e, I w ouldn’t be were I am now.
This research and dissertation could not have been possible w ithout the collaboration,
encouragem ent, and aid o f my colleagues. I w ant to thank D uk Joong Kim for his loyalty
over the years. Besides ju st being colleagues, w e are close friends w ho lived and worked
v
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together over the years. I w ant to thank Dr. Zibing Yang for his generous help and advice
on m y research as w ell being a good friend who has enabled great opportunities in my
professional life. I also w ant to thank Dr. Todd H inck for his support over the years that
actually started in 1 9 9 7 .1 want to thank Dr. Socrates D eligeorges for his support over the
years since some things I indirectly asked him to do w ere and are beyond m any things
other people w ouldn’t have done. I am thankful for that. I w ant to thank also Aleks Zosuls for his support throughout the years. He enabled things w hen hope was lost. A nd he
still does. I w ant to thank H ow ard E. Cohen for his patient support over the years. Mr.
Cohen has the ability to organize things that actually seem not to be possible to acquire
and hence was a great support for m y research.
I also w ant to thank some people from the Boston U niversity EC E staff. H em ayat Nabiel,
w ho alw ays fixed m e up when som ething w ent wrong. M r. N abiel becam e also a very
good friend - at B U and the time outside BU. Our discussions about us and the rest o f the
w orld kept my senses on the ground. I w ant to thank Carly M archioni for her support and
positive spirit - and I am surprised that she never got m ad at m e ... I w ould have. I also
w ant to thank A aron Caine who patiently was listening to our research needs and greatly
supported us with his talent and expertise.
I w ant to say thank you to my colleagues at Intel Corporation. Larry Tate gave me an op­
portunity that I truly cherish and he gave me the level o f freedom I needed to finish this
research and dissertation. I also w ant to thank M atthew B ecker for his clear lead that
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helped to com bine professional w ork w ith my research at Boston University. His inspir­
ing leadership certainly helped to keep the discipline to finish this dissertation. I also
w ant to thank Frank Schw ertlein from Infineon Technologies. M r. Schwertlein was m y
first m entor regarding analog circuit design and w e m anaged to stay in touch for all these
years.
I w ant to thank also the founders o f BioM im etic Systems. From a crazy idea, all people
joined into this adventure and BioM im etic Systems m ight be able create the dawn o f a
new technology. I w ant to thank Dr. H ubbard for his support over the years and actually
his w illingness to engage into som ething that m any people w ould not have bothered with.
I w ant to thank Dr. D eligeorges for his leadership as a president. I w ant to thank Dr.
M ountain for sharing his know ledge and his flexibility towards this project. I w ant to
thank Aleks Zosuls for his positive attitude and com m on sense that can sometimes easily
be lost. I w ant to thank Tyler Gore for his loyalty, trust and vision into this project. I w ant
to thank Dr. Yang for his support when BM S was bom and I w ant to thank Dave A nder­
son for his discipline to w ork on the project when other people are already asleep.
Time outside school was very precious but I was blessed with tm e friends that kept up
with me all these years. I w ant to say thank you to D uk Joong Kim w ho could endure m y
attitudes with such patience. For years, we w orked and lived together. Starting from
breakfast to late night drinks. I w ant to thank H em ayat N abiel for being an inspiring
friend and tm e gentlem an w ho has an open mind and opinion and w ho helped me to think
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som etim es outside the engineering. I w ant to thank Kostya Aizkov for the talks through­
out the nights and his w ide views on the w orld and being a friend who does not ask why
and accept things how they are. I w ant to thank Tyler Gore for his uncom prom ised loy­
alty and friendship. Even now separated for thousands o f m iles, it’s ju st like in the old
days. I also w ant to thank Zibing Y ang for all his support and advice. A nd very often I
think how Zibing w ould do it. Since we are w orking together, I guess I ju st w ill ask. I
also w ant to thank V anessa K och for her support in my after hours at work. B eing “m y
bartender” and friend, she helped me to rearrange my mind so I could find some sleep at
night. I hope you w ill take a chance on life. I also w ant to thank Tim Ziou for his friend­
ship and inspiring conversations. A nd believe m e - I am interested. I know som etim es I
do n ’t make it easy for you.
I w ant to say very special thanks to m y friends that stayed w ith me over all these years. I
am separated from them for over six years. Once a year we have the chance to m eet again
in person and I feel honored to have such true friends that don’t ask who or w hat you are.
You are a part o f them and they never let you down. True friendship is one o f the hardest
things to find. I w ant to say thank you to M artin Reidl, my friend, my brother for the last
27 years. We are bonded together. I w ant to thank m y friend M artin Dietl w hose positive
way o f thinking alw ays kept me inspired - this includes life as it is but also the m usic and
the arts. When times are hard it is good to know that there is someone who will never let
you down. I w ant to say thank you to Dr. M arkus Pindl for his friendship that started
when we first m et at the university in 1993. Since then we always engaged in scientific
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projects and long night talks. I also w ant to thank you Dr. Juergen Kempf, an inspiring
professor at m y form er university that show ed me that engineering is a very interdiscipli­
nary field and how to m ake the connection betw een the dots. O ver the years we becam e
friends and he show ed m e that it is w orth to go the extra mile. I w ant to say thank you to
Dr. Francesco D ePellegrini for his friendship throughout the years. H e showed me how to
add some jo y to live w hen engineering gets pretty busy. I also w ant to thank Joseph
Pfitzer for his loyalty over the years. O ur conversations keep me inspired and gave me
the hope that there is alw ays a second chance. I also w ant to thank D aniel Plappert for
keeping in touch w ith m e over the years and w ho kept m y old professional live up-to-date.
I hope I don’t disappoint you in m y new ventures planned!
I want to say thank you to m y fiancee M arianne N ourzad. I know that the life with me is
sometimes difficult and I get sometimes too engaged into things that are at the end not
from im portance. H er loving support and h er understanding have helped me to finish this
dissertation. M arianne showed me that there is a w ay to m anage w ork and private life.
There were tim es I m ight have lost the ability to laugh but she always proved me that
there are m ore than one w ay you could look at things. This helped m e in my private life
as well in my professional career.
I want to say thank you to my family. I know that it was hard for my mum, Lydia Karl, to
let me go. She knew that when we said good-bye, w e w o n ’t see each other for a long time
and the time w e will be able to share w ill be always quick and short. A s tim e is m oving
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on, I w hish there w ill be a chance to be closer and see each other m ore often since I fear
that there w ill be the time I will regret that w e did not spend m ore tim e together. I also
w ant to thank m y father, Siegfried Karl, for his support in m y career. H e gave me always
the freedom I needed: As a teenager, a student, an engineer or as a researcher. His pa­
tience and advice m ade me to the m an I am today. I also w ant to thank m y sister Elisa­
beth K noellinger w ho showed me that even w hen life puts all the hardship on one person,
there is always a room to laugh and happiness can be found everywhere. I also w ant to
say thank you to m y brother in law, Andreas K noellinger, who has been a strong support
in the fam ily and I d o n ’t know w ere w e w ould be today if he w ouldn’t be there.
Time m oved quickly. And I learned that life at its best can turn quickly. A ugust 9th be­
came a date I have to rem em ber throughout m y life. In 2003, a friend o f mine, Josef
W inkelm ayer, got killed in an instance by a drunk driver. H e left us his w ork and inspira­
tion. A year later, the same day, A ugust 9th, a very close friend o f mine died. As my
other close friend, he opened my eyes, and p u t light on things - politics, social science,
research, you nam e it. He made me grow as a person since he w as inspiring but above all
honest and hearty. And I have to admit that there is seldom a day I don’t think o f him.
M ost o f the time I rem em ber his laughter that could put sunshine on pretty much every
bad day in my life. Barry Ballard and I w ere quiet different and in the sam e way very
sim ilar and som etim es I referred to him as a Steppenwolf. V ery often we w alked through
the dark nights talking about us and the rest o f the world. Since he is gone, I avoid these
streets since som etim es even a Steppenw olf needs a companion.
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A n a l o g C ir c u it s f o r A u d it o r y S o u n d S o u r c e L o c a l iz a t io n
u s in g
C u r r e n t M o d e T e c h n iq u e s
(O rder No.
)
CHRISTIAN KARL
Boston U niversity, College o f Engineering, 2006
M ajor Professor: A llyn E. Hubbard, Professor o f Electrical and C om puter Engineering
Abstract
This dissertation focuses on the analog V LSI im plem entation o f auditory nerve models
using current m ode circuit design techniques. The target application o f these chips is
sound source localization, a task difficult to accom plish using standard digital signaling
processing methods, especially in a reverberant environm ent. The m odels and the result­
ing circuitry have not been previously used com m ercially. In general, the usage o f such
m odels requires a dramatic rethinking o f how to process sound signals. The approach it­
self is called “biom im etic” ; that is to say, m im icking nature’s biological systems, in this
case the m am m alian auditory system. The usage o f a biom im etic schem e for sound proc-
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essing is new and little or no circuitry has been developed to date to support such proc­
essing. This dissertation shows how appropriate circuits can be built, highlighting the im ­
portance o f accuracy using analog VLSI.
A 64 analog channel system design com posed o f 512 very low frequency current m ode
integrators and 128 current m ode m ultipliers is presented. The design is constrained by
the available pow er budget and layout area. U nder these constraints a system is presented
that is suitable for sound source localization with sensor spacing o f eight inches and
above. The m ain building blocks o f a current m ode auditory channel have been designed,
fabricated and tested. The m easured results from the test chips agree w ith the theoretical
predictions as w ell as w ith the results from circuit and M onte Carlo simulations. The dis­
sertation highlights the im portance o f m atching constraints in current m ode circuitry
w hen designing m assively-parallel, non-linear structures. U sing M onte Carlo methods as
w ell as a D esign O f Experim ent (DOE) approach, an analysis has been done, which re­
veals how to lim it m ism atch-induced tim ing jitter. The non-linear circuit behavior was
characterized and methods have been elaborated, w hich w ill theoretically produce near
100% design yield under reasonable process com er limitations.
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TABLE OF CONTENTS
1
INTRODUCTION................................................................................................. 1
1.1
Background / M otivation..............................................................................................................................1
1.2
Auditory Physiological Background..........................................................................................................6
1.2.1
Physiology....................................................................................................................................................6
1.2.2
Peripheral Auditory Nerve M odel......................................................................................................... 10
1.3
G oals................................................................................................................................................................. 17
1.4
Overview o f the D issertation..................................................................................................................... 19
1.5
Summary o f Contributions........................................................................................................................ 21
1.6
References for Chapter 1............................................................................................................................22
2
SOUND SOURCE LOCALIZATION............................................................... 25
2.1
Introduction....................................................................................................................................................25
2.1.1
Plane R eceiver............................................................................................................................................ 26
2.1.2
3D Sound Localization............................................................................................................................. 28
2.2
Defining n o ise................................................................................................................................................ 31
2.3
Atmospheric Im pacts.................................................................................................................................. 32
2.4
Available Approaches and their D raw backs........................................................................................36
2.4.1
Sound Source Localization using D S P .................................................................................................. 37
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2.5
Auditory Localization and Interaural Tim e D e la y .............................................................................39
2.5.1
Time-Frequency Signal Processing........................................................................................................40
2.5.2
Sensor Setup................................................................................................................................................41
2.5.3
Temporal Behavior o f the Auditory M odel.......................................................................................... 43
2.6
Auditory Sound Source Direction Finding Prototype.........................................................................48
2.6.1
Vehicle tracking using a one cubic inch Sensor...................................................................................49
2.6.2
Gunshot Detection using Auditory M odels...........................................................................................52
2.7
Data processing extension - correlated vector feedback.................................................................... 59
2.8
Summary.......................................................................................................................................................... 60
2.9
References........................................................................................................................................................60
3
CURRENT MODE CIRCUITS..........................................................................63
3.1
Technology Choice: W hy Current M ode?............................................................................................. 63
3.1.1
Single-ended versus differential im plem entations...............................................................................66
3.1.2
Current M ode T echnology.......................................................................................................................68
3.2
Basic Element - Current M irror.............................................................................................................. 70
3.3
Enhanced E lem ents.......................................................................................................................................77
3.3.1
Differential Current to Voltage converter with low harmonic distortion........................................ 78
3.3.2
Fully Balanced Current M irror................................................................................................................ 81
3.3.3
R ectifiers......................................................................................................................................................83
3.3.4
Continuous Time F ilters........................................................................................................................... 89
3.3.5
M ultipliers................................................................................................................................................. 103
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3.4
Sum m ary.......................................................................................................................................................114
3.5
References:................................................................................................................................................... 115
4
MISMATCH BEHAVIOR OF CURRENT MODE CIRCUITS....................... 118
4.1
Introduction - Design Goal, Design Constraints...............................................................................118
4.2
Causes o f M ism atch.................................................................................................................................. 120
4.3
M ism atch......................................................................................................................................................122
4.3.1
Defining M atching C onstraints............................................................................................................. 122
4.3.2
Parameter C o rrelation.............................................................................................................................129
4.3.3
Correlation coefficient.............................................................................................................................131
4.4
M onte Carlo Analysis of C ircu its..........................................................................................................132
4.4.1
Current Mode Low-Pass Filter C h ip .................................................................................................... 133
4.4.2
Fully Balanced Current M irror.............................................................................................................. 136
4.4.3
Current Mode M ultiplier........................................................................................................................ 140
4.5
Layout Considerations
4.6
References for Chapter 5 ..........................................................................................................................153
5
................................................................................................................... 147
AUDITORY NERVE CHIP............................................................................... 156
5.1
Introduction..................................................................................................................................................156
5.2
Design Goal and M etric............................................................................................................................ 159
5.3
AN Building Blocks....................................................................................................................................161
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5.3.1
R ectifier.....................................................................................................................................................164
5.3.2
Envelop D etector.....................................................................................................................................168
5.3.3
Dual A G C ................................................................................................................................................. 173
5.3.4
Spiking N e u ro n ....................................................................................................................................... 185
5.3.5
Further Spike Processing....................................................................................................................... 198
5.4
AN System Param eters.............................................................................................................................200
5.4.1
5.5
Statistical Variations within the Auditory Nerve C hannel..............................................................200
System A sp ects............................................................................................................................................206
5.5.1
Bias distribution......................................................................................................................................206
5.5.2
Pow er B udget.......................................................................................................................................... 211
5.5.3
DC Offset C orrection.............................................................................................................................213
5.6
Design o f Experiment (D O E )..................................................................................................................213
5.7
Sum m ary.......................................................................................................................................................219
5.8
References for Chapter 6..........................................................................................................................221
6
CONCLUSION................................................................................................ 222
6.1
Feasibility......................................................................................................................................................222
6.2
Perform ance................................................................................................................................................ 223
6.3
Yield, area and cost factor........................................................................................................................225
6.4
System Rem arks..........................................................................................................................................227
6.5
Future W ork.................................................................................................................................
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229
APPENDIX A
OVERVIEW CHIP SUBMISSION..............................................230
APPENDIX B
CIRCUIT SYMBOL REFERENCE............................................232
APPENDIX C
ASYNCHRONOUS BUS CONTROLLER................................233
C .l
R eferences.................................................................................................................................................... 237
APPENDIX D
VOLTAGE MODE DUAL A G C .................................................238
APPENDIX E
CIRCUIT ANALYSIS.................................................................. 241
E .l
Distortion A nalysis.....................................................................................................................................241
E.2
Distortion Analysis o f the Pseudo Differential I2V Converter...................................................... 243
E.3
Transfer Function Current M ode Low Pass F ilter.......................................................................... 247
E.4
Transfer Function of the Fully Differential Current Mode Integrator...................................... 249
E.5
M ismatch Analysis Fully Balanced Current M irror........................................................................254
E.6
R eferences.................................................................................................................................................... 260
BIBLIOGRAPHY.................................................................................................... 261
V IT A .........................................................................................................................274
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LIST OF TABLES
Table 2-1: Number of microphones versus available edges.............................................................. 42
Table 2-2: Gunshot data results processed through prototype...........................................................59
Table 4-1: THD for different chips.................................................................................................... 135
Table 4-2: CMRR for different designs............................................................................................. 138
Table 4-3: THD for the submitted chip..............................................................................................146
Table 5-1: Symbol mapping table.......................................................................................................162
Table 5-2: Spike jitter from Monte Carlo run versus different input amplitudes...........................195
Table 5-3: Monte Carlo results of an excited channel, input amplitude luA .................................201
Table 5-4: DC Monte Carlo results comparing excited/resting channel........................................ 202
Table 5-5: Power budget for single three population auditory nerve implementation..................212
Table 5-6: DOE variables....................................................................................................................215
Table 5-7: Summary of fit...................................................................................................................217
Table 6-1: Chip area calculation........................................................................................................ 226
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LIST OF FIGURES
Figure 1-1: Cross-section of the cochlea [4]......................................................................................... 7
Figure 1-2: Details o f the IHC and OHC [5]......................................................................................... 9
Figure 1-3: Overview of processing stages of the auditory nerve model..........................................12
Figure 1-4: IHC membrane voltage versus displacement...................................................................14
Figure 1-5: Single section o f the dual AGC.........................................................................................15
Figure 1-6: Onset and steady state response o f the auditory nerve....................................................16
Figure 2-1: Time delay of arrival......................................................................................................... 27
Figure 2-2: Tetrahedral arrangement of sensors.................................................................................29
Figure 2-3: Distance-frequency relation of atmospheric absorption.................................................34
Figure 2-4: Simulation o f atmospheric absorption............................................................................ 35
Figure 2-5: Magnitude and phase response of an asymmetrical bandpass filter front end............. 45
Figure 2-6: Maximum phase delays under different matching conditions of passive components.
........................................................................................................................................................ 46
Figure 2-7: Area photo AGP.....................................
49
Figure 2-8: Ground-truth referred error for all vehicle classes.......................................................... 50
Figure 2-9: Error referred to ground truth data for a M548, 200 seconds........................................ 51
Figure 2-10: Characteristics of a gunshot............................................................................................ 53
Figure 2-11: Picture o f a 7.62mm NATO bullet in supersonicflight [17].........................................54
Figure 2-12: Summed auditory output response to a gunshot................................
55
Figure 2-13: Output response o f the auditory model to a gunshot.................................................... 57
Figure 2-14: Test setup ARL data set...................................................................................................58
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Figure 3-1: Simple current mirror........................................................................................................ 71
Figure 3-2: SNR for a single-ended current mirror under power supply ripple...............................74
Figure 3-3: Schematic current-to-voltage conversion concept.......................................................... 78
Figure 3-4: Schematic of the fully balanced current mirror...............................................................81
Figure 3-5: Precision half-wave rectifier.............................................................................................84
Figure 3-6: Pseudo-differential half-wave rectifier............................................................................ 87
Figure 3-7: Pseudo-differential full-wave rectifier............................................................................. 88
Figure 3-8: OTA with level shifter.......................................................................................................89
Figure 3-9: Chip layout for the current mode low-pass filter............................................................ 91
Figure 3-10: Current mode low-pass filter.......................................................................................... 93
Figure 3-11: Small-signal model of the single-ended current mode low-pass filter........................94
Figure 3-12: Transfer curve of the single-ended current mode low-pass filter................................95
Figure 3-13: Schematic o f the continuous current mode time integrator......................................... 96
Figure 3-14: Integrator frequency response in comparison with an ideal integrator....................... 98
Figure 3-15: Integrator frequency response versus frequency for different vref.............................99
Figure 3-16: Measured gain transfer curve........................................................................................101
Figure 3-17: Measurement of the cut-off frequency versus vref.................................................... 102
Figure 3-18: Measurement o f the cut-off frequency versus vgm.....................................................102
Figure 3-19: Output signal at cut-off frequency of 1Hz................................................................... 103
Figure 3-20: Layout of the fully differential current mode multiplier............................................ 105
Figure 3-21: Squaring Circuit by Liu et al......................................................................................... 107
Figure 3-22: Current mode multiplier [18]........................................................................................ 108
Figure 3-23: New fully differential current mode multiplier........................................................... I l l
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Figure 3-24: Transient test data - Amplitude modulation................................................................ 113
Figure 3-25: XY Graph - Four quadrant operation..........................................................................114
Figure 4-1: Pelgrom's model for standard deviation (left) and variance (right).............................124
Figure 4-2: Simple Current M irror.................................................................................................... 126
Figure 4-3: Pelgrom vs. Edge Roughness for W=L device sizes.................................................... 128
Figure 4-4: Correlation of parameters................................................................................................ 130
Figure 4-5: THD full chip under process and mismatch deviation................................................. 134
Figure 4-6: CMRR under mismatch variation...................................................................................138
Figure 4-7: Measured CMRR..............................................................................................................139
Figure 4-8: Spectrum of the current mode multiplier....................................................................... 141
Figure 4-9: Distribution HD2 for -1%< Ai.g <+1%........................................................................... 143
Figure 4-10: THD under process variation, cc = 75%......................................................................144
Figure 4-11: THD under mismatch variation with cc=95%.............................................................145
Figure 4-12: Monte Carlo run for submitted chip............................................................................. 145
Figure 4-13: Full differential current mode multiplier (with VI converter)................................... 148
Figure 4-14: Full differential current mode low-pass filter..............................................................149
Figure 4-15: Common centroid device placement............................................................................ 151
Figure 4-16: Common centroid placement with M=8...................................................................... 152
Figure 4-17: Inter-digitated device arrangement............................................................................... 152
Figure 5-1: 20x20 mm2 reticle of submitted design.......................................................................... 157
Figure 5-2: Auditory nerve system outline........................................................................................ 163
Figure 5-3: Input waveform into the auditory nerve channel..........................................................165
Figure 5-4: Transient response of the half-wave rectifier................................................................ 166
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Figure 5-5: Monte Carlo channel simulation at the rectification stage, output current mismatch.
...................................................................................................................................................... 167
Figure 5-6: Monte Carlo Channel simulation at the rectification stage, DC mismatch.................168
Figure 5-7: Symbolic representation o f the envelope detector........................................................ 169
Figure 5-8: Transient response of the envelop detector................................................................... 170
Figure 5-9: Monte Carlo channel simulation at envelope detector with output current mismatch.
...................................................................................................................................................... 171
Figure 5-10: Monte Carlo channel simulation at the envelope detector with DC mismatch
172
Figure 5-11: Monte Carlo channel simulation at envelope detector with common mode mismatch.
...................................................................................................................................................... 173
Figure 5-12: System outline of the dual AGC.............................
174
Figure 5-13: AGC loop simplified for analysis.................................................................................175
Figure 5-14: Transient simulation results for equation 5-2 solved for |sin|.................................... 176
Figure 5-15: Transient simulation of the dual AGC......................................................................... 178
Figure 5-16: Monte Carlo channel simulation at dual AGC, with output current mismatch
179
Figure 5-17: Monte Carlo channel simulation at dual AGC, DC mismatch...................................180
Figure 5-18: Monte Carlo channel simulation at dual AGC, common mode mismatch............... 181
Figure 5-19: Transient response with Monte Carlo variations at the dualAGC output................. 182
Figure 5-20: Detail gain variation.......................................................................................................183
Figure 5-21: Monte Carlo channel simulation at the input of the spiking neuron with DC
mismatch...................................................................................................................................... 184
Figure 5-22: State diagram of the SRMO spike generation..............................................................186
Figure 5-23: SN system diagram.........................................................................................................186
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Figure 5-24: Current comparator........................................................................................................ 187
Figure 5-25: Spike generation.............................................................................................................189
Figure 5-26: Refractory signal generator........................................................................................... 190
Figure 5-27: Transient response o f the refractory pulse generator..................................................191
Figure 5-28: Transient response o f the high-pass filtered current pulse.........................................192
Figure 5-29: RSG transient response..................................................................................................193
Figure 5-30: Monte Carlo channel simulation at spike output: Spike jitter....................................194
Figure 5-31: Transient response with Monte Carlo variations at the spiking neuron input.......... 195
Figure 5-32: Cross channel spike jitter vs cc..................................................................................... 197
Figure 5-33: Transient response: Primary and secondary spike generation................................... 198
Figure 5-34: System map to acquired Monte Carlo results..............................................................200
Figure 5-35: Spike thresholds............................................................................................................. 204
Figure 5-36: Refractory timeout thresholds UTH.............................................................................205
Figure 5-37: gmcurrent source............................................................................................................ 207
Figure 5-38: Measured bias distribution across 64 channels of an earlier design......................... 208
Figure 5-39: Bias distribution............................................................................................................. 209
Figure 5-40: Current Bank..................................................................................................................210
Figure 5-41: DC offset injection points with variable mapping...................................................... 214
Figure 5-42: JMP predicted plot......................................................................................................... 216
Figure 5-43: Spike jitter residual........................................................................................................ 217
Figure 5-44: JMP prediction profiler..................................................................................................218
Figure C -l: Arbiter circuit.................................................................................................................. 234
Figure C-2: Steering circuit................................................................................................................ 235
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Figure C-3: Handshake protocol..........................................................................................
237
Figure D -l: Transient Response to a sin-input wave form..............................................................239
Figure D-2: Tuning Curve of the voltage mode dual AGC.............................................................240
Figure E -l: Small signal model CMI................................................................................................ 249
Figure E-2: Fully balanced current mirror........................................................................................254
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LIST OF ABBREVIATIONS
Abbreviation
Explanation
ABC
A synchronous bus controller
ACK
A cknow ledge
ADF
A coustic direction finding
AER
A ddress event representation
AGC
A utom atic gain control
ANB
A uditory nerve board
ANC
A uditory nerve chip
APG
A berdeen proving ground
ARL
A rm y research labs
BJT
B ipolar junction transistor
BM
B asilar m em brane
CAD
C om puter aided design
CC
C urrent conveyer
cc
correlation coefficient
CM
C urrent mode
CMA
C urrent m ode adder
CMI
C urrent m ode integrator
CMM
C urrent m ode m ultiplier
CMOS
C om plem entary m etal-oxide sem iconductor
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CM RR
Comm on m ode rejection ratio
CPG
C urrent pulse generator
CS
Chip select
CTC
C urrent threshold crosser
DAGC
D ual AGC
DCM M
D ifferential current m ode m ultiplier
DIFFM ULT
D ifferential m ultiplier
DOE
D esign o f experim ent
DSP
D igital signal processing
EC
Electronic cochlea
ECANC
Electronic cochlea and auditory nerve chip
FBCM
Fully balanced current m irror
FPGA
Field program m able gate array
FW R
Full w ave rectifier
GPS
G lobal positioning system
HD
H arm onic distortion
HEM M T
H eavy expanded m obility tactical truck
HM M W V
H igh m obility m ultipurpose w heeled vehicle
HPF
H igh pass filter
HRTF
H ead related transfer function
HWR
H alf w ave rectifier
IC
Integrated circuit
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IHC
Inner hair cell
ILD
Interaural level difference
ITD
Interaural time difference
LPF
Low pass filter
LTH
Low er threshold
MC
M onte Carlo
M OS
M etal-oxide sem iconductor
oc
Organ o f Corti
OHC
O uter hair cell
ON
On-set response
OTA
Operational transconductance am plifier
PCB
Printed circuit board
PSRR
Pow er supply ripple rejection
REFRA
Refractory
REQ
Request
RMS
Root-M ean-Square
RSG
Refractory signal generator
RSM
Response surface m ethod
SN
Spiking neuron
SNR
Signal to noise ratio
SPKJIT
Spike jitter
SPL
Sound pressure level
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SRMO
Spice representation m odel 0
STS
Steady state response
TD O A
Time delay o f arrival
THD
Total harm onic distortion
U TH
U pper threshold
V2I
Voltage to current
V LSI
V ery large scale integration
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1 Introduction
This dissertation focuses on the analog V LSI (Very Large Scale Integration) im plem enta­
tion o f auditory models using current m ode techniques suitable for sound source localiza­
tion. The goal is to show a successful path to im plem ent such structures in respect to
m anufacturability. The auditory m odel is a parallel system o f non-linear functions that is
im plem ented in analog circuitry. The m ain challenge is to find an im plem entation that
can accom m odate m ism atch and process deviations under given design constraints such
as chip area and power. A chip history to this goal is provided in A ppendix A.
1.1 Background / Motivation
Biologically-inspired data processing has been studied for years. In general, the com puta­
tion o f these non-linear system s or biom im etic systems is quite dem anding. W ith the
com m on availability o f VLSI technology, these data processing schem es are realized u s­
ing dedicated hardware in order to achieve real-tim e solutions. Sensor designs inspired by
the hum an eye [1] or ear [2] can be found in selected publications. A lso, neural netw ork
researchers have focused on VLSI im plem entations and their feasibility [3].
Currently, none o f these technologies are available in industrial or m ilitary markets as
applications. Sensor data processing is still dom inated by com m on D SP im plem entations
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w ith w ell-established signaling processing schemes. R egarding acoustic sound source
localization, standard DSP im plem entations have up until now failed to realize a robust
sound source locator. Sound source localization is a very basic, hum an experience and in
general, the task o f acoustic sound source localization does not sound very challenging.
Indeed, it is actually not very hard to realize acoustic sound source localization if one
tries to come up w ith a solution that attempts to locate a specific signal in a fixed envi­
ronm ent. In a real w orld application, however, neither the sound source nor the environ­
m ent is fixed; thus, m ost o f to d ay ’s approaches fail. I f the reader takes a minute and tries
to think about available sound source localization solutions, he w ill soon realize that there
are not m any for this seem ingly easy task. They ju st do not exist for com mon use. Right
now there is only an unsatisfying niche m arket for acoustic sound source localization.
A large segment o f signal processing will always benefit from D SP solutions. Biom im etic signal processing uses the natural w orld as a tem plate for new ways o f solving sig­
nal processing tasks. The m otivation o f doing so exists in the nature o f the signals to be
analyzed or interpreted. As an extreme counter example, w ireless com m unication has b e­
com e a com modity in contem porary society, and digital signal processing allows the re ­
generation o f bits at very low signal-to-noise ratios (SNR). O ne reason w hy this technol­
ogy works extrem ely w ell is the fact that the source o f the inform ation has a know n state
due to selected frequency bands and signal coding. C om paring this extreme exam ple w ith
acoustic sound source localization, the signal to be located has to be isolated from any
other sound source in the low bandw idth spectra. The sound source to be located can in-
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terfere w ith other sound objects and the frequency content changes dram atically w ith any
change in environm ental conditions or the location o f the sound source itself (e.g., in­
creasing and decreasing distance or m odified sound path because o f obstacles). So the
question is, how w ell can standard signal processing solutions do w hen the signal can be
pretty much anything at all?
In dialogues with other researchers, m ost people showed little interest in sound source
localization due to th eir daily experience, suggesting it m ust be a rather easy task. Look­
ing at the problem in a first-order approxim ation, it states itself quite simply: There is a
sound that is received w ith some delay at two separated receivers. One is m easuring the
phase difference betw een the tim e o f arrival and the direction o f the sound can be deter­
mined. There is nothing w rong w ith this explanation. But the question that really m atters
is: W hat are w e listening to?
The answ er to that is in our case vehicles and im pulse sound sources, like gunshots. This
defines a limited class o f signals to be interpreted and distinguished. One has to isolate
these signals out o f any other sound sources in the environm ent, e.g., wind, rain, crickets
(they can set a quite high environm ental noise floor) or anything in an urban environm ent
that contributes the background rum ble o f a city noise floor. These other signal sources
are like the signal to be detected; that is, they share same frequency bands and can be also
coherent since they can have a distinct origin or sound. Hence, treating these “other” sig­
nals from the perspective that they are ju st noise w ould lead in the w rong direction. Be-
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sides these background signal sources, one has also to distinguish between the signal and
the reflection o f the signal, w hich can look the sam e in an urban environment.
Besides other signal sources and reverberation, the incoming signal to be detected is
shaped and reshaped on its w ay to the receiver. Some atm ospheric assumptions can be
m ade that w ill im pact the frequency content o f the signal, but in general, sound source
localization is a blind source problem : One w ill never know w hat to expect. The m uzzle
blast o f a gunshot traveling over 200 m eters w ill be shaped by buildings and any object
w ithin its path. A n acoustic frequency range o f 10 H z to 10 kH z has a corresponding
w ave length o f 33 meters to 33 mm. This w avelength range is within natural and m anm ade object dim ensions and w ill im pact the signal when passing by or through. H igh fre­
quencies have to “bend around” objects, w hereas low frequencies will ju st continue trav­
eling. This leads to additional frequency dispersion in the signal.
M entioning some o f the aspects which w ill im pact an acoustic signal, one m ight now
m ore appreciate w hat the hum an ear and brain is able do. H earing is our daily experience
and one o f our first prim ordial senses that connects us to the outer w orld while still in a
fetus state: First there was hearing; then there w as the sense o f seeing. Throughout nature,
mam m als show the same im plem entation o f hearing: The cochlea will always m ake its
turns and we have com e a long way throughout evolution to act and react to environ­
mental sounds w ith all their im pact on social behavior. Hearing enabled us to form
sounds that are m ore than ju st noises. H earing allowed us to put meaning on sound se-
4
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quences— words— and to connect these abstract sounds to a symbolic space in our brain,
enabling us to re-interpret them w ith higher order functions between other abstracts in
our sym bolic space, our way o f thinking.
Focusing again on the engineering aspect, the question arises, w hat has to be done to use
this exam ple from nature to suggest a processing scheme? Decades o f research in the
field o f hearing has led to many theories about how sound is perceived and processed. In
general, com paring m odels based on these theories to regular signal processing methods
show a m uch more com plex effort in com putation due to the non-linearity o f the models.
The signal processing happens in a continuous transient space, rather than in a timefrequency domain. The transient and non-linear nature o f the m odels does not allow the
use o f efficient com putational m ethods, available in the DSP community. As an example,
the m odel used in this study does not allow the fram ing o f data. One operator cannot be
used over a range o f input data points, and the data has to be com puted on the basis o f
sample-by-sample operation, inevitably slow ing dow n any digital signal processor.
There are ways around it. Our first choice o f im plem enting these auditory m odels using
VLSI w as an analog approach, due to expertise in the field o f analog signal processing.
This m ethod and especially the use o f current m ode signal processing with auditory m od­
els will be highlighted throughout this study. This approach showed that the im plem enta­
tion o f such models for signal processing is quite challenging.
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Throughout this study o f the processing scheme, it becam e clear that a real-tim e digital
version for sensor applications m ight be feasible. The im plem entation, however, needs a
new w ay o f defining architecture to com prehend the transient driven nature o f the models.
N ew generations o f field program m able gate arrays (FPGA) m ight have the ability to
custom ize the architecture to fit the com putational requirement. Custom ASIC design can
open the door to offer an IP block to the digital com m unity that allows hearing and sound
source localization for any given application.
1.2 Auditory Physiological Background
This chapter provides a b rief overview o f the physiological background that inspired the
overall signal processing schem e used in this study. Two aspects are m ainly highlighted:
1) the anatom y o f the ear and 2) how it translates into a behavioral model.
1.2.1
Physiology
Sound processing begins in the outer and m iddle ear, w here the resonant properties o f the
outer ear and ear canal gently shape the spectrum o f the sound signal. A prim ary function
o f the m iddle ear is the im pedance m atching betw een the air and the liquid-filled inner
ear. This is achieved through the large area o f the eardrum to the relatively small area o f
the oval window, which is driven by the O ssicular chain using law o f the lever. The oval
w indow borders the Scala vestibule, w hich connects at the upper part o f the cochlea
(Helicotrema) to the Scala tym pani. Figure 1-1 shows the cross-section o f the cochlea.
6
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Tectorial
membrane
Reissner's
m embrane
Stria
vascularis
Scala
vestibuli
Spiral
limbus
Scala
media
S p ir a l
Organ
• of
Corti
***£
o a}*
ganglion
•
'
Spiral
ligament
Scala
tympani
Bony
spiral
lamina
Basilar
membrane
Figure 1-1: Cross-section o f the cochlea [4].
The Scala media is located in betw een and is separated from the Scala tympani through
the Basilar M embrane (BM ), w hich separates the cochlea lengthw ise. The width o f the
BM increases starting at the oval w indow and tow ards the H elicotrem a. A t the same time,
the stiffness decreases. I f a sound w ave is present at the oval w indow , a pressure differ­
ence longitudinal to the BM betw een the Scala vestibule and Scala tym pani occurs. The
BM deflects and a traveling wave begins to m ove along. O ver the length o f the BM , the
velocity o f propagation decreases exponentially w ith distance. H igh frequencies deflect
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the m em brane close at the oval window, whereas low frequencies deflect the m em brane
at its end. Hence the tim e-dom ain inform ation is encoded into spatially encoded inform a­
tion by spreading out the signals in space according their frequency.
The inner hair cells (IHC) and outer hair cells (OHC) are located in the Organ o f Corti
(OC), and perform as m echanical-electrical transducers. Stereocilia are arranged on the
top o f these hair cells. The ends o f the Stereocilia are em bedded into the gelatine-like tec­
torial m em brane w hich converts the up and down m ovem ent o f the BM into a transverse
m ovem ent o f the Stereocilia. D epending on the lateral deflection o f the Stereocilia, the
hair cells discharge. A fferent nerve fibers start from the IH C and transm it via the auditory
pathw ay inform ation tow ards the brain stem. Hence, they perform as sensors. The OHCs
have the ability to contract and help to am plify acoustically in the mid and high fre­
quency ranges. H ence, an active feedback for sensitivity and frequency selectivity for the
BM is achieved. R egarding the OHC, the active am plifying elem ent theory is still dis­
cussed and is part o f on-going research. Figure 1-2 shows the arrangem ent o f the IHC and
OHC.
8
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Figure 1-2: Details of the IHC and OHC [5].
Spiral-ganglion synapses connect to each IH C and produce fixed-width, fixed-height
pulses in response to the IHC electrical activity and then transm it the spike-encoded in­
formation via axons to the brain stem. These nerve fibers are called auditory nerves and
all auditory relevant inform ation has to be transm itted via these nerve fibers. The trans­
duction o f the hair cells only transm its half-w ave rectified auditory electrical inform ation
towards the auditory nerve, since the stereocilia only depolarize after deflection in a cer­
tain direction. Transm itter depletion also limits the IHC to follow signals over 1 kHz. The
maxim um rate o f an auditory nerve fiber is around 1000 spikes per second, w hich corre­
sponds to an approxim ate refractory time o f 1 ms. The spikes o f the auditory nerve have
the property to phase-lock to an input w aveform . With increasing stimulus, the m ean
spike rate goes up and phase-locking im proves. For input stimulus with frequencies
higher than 1 kH z, the m axim um spike rate o f the neurons cannot code the input w ave-
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form in every phase. In statistically frequent intervals, periods are skipped. A nother typi­
cal property is the adaptation or com pression m echanism o f the auditory nerve. D uring
input changes, a high discharge rate o f the neurons can be seen (on-set response), w hich
after a certain am ount o f time goes to a low er level o f spike activity.
1.2.2 Peripheral Auditory Nerve Model
The scope o f this study is the im plem entation o f the peripheral auditory nerve m odel [6],
including the inner hair cell and auditory model.
Before any signal is further processed by the auditory nerve, the input signal is processed
by the Cochlea mechanics. The cochlear behavior and its model im plem entations are not
discussed in this study. Nevertheless, they should be addressed w hen it comes to the
overall system perform ance, since the cochlea represents the input into the peripheral
auditory nerve model.
Interestingly, in 1863, H elm holtz [7] described the Cochlea as being formed o f basic
elements, each one resonating at a different frequency. In the late 1930s, Bekesy intro­
duced the traveling w ave theory [8] for w hich he was rew arded with a N oble prize in
1961. In short, a traveling wave w ithin the cochlear can be described as the B M dis­
placement as a function o f frequency. The m ovem ent o f the BM begins at the base (stiff)
and propagates towards the apex (flexible). Frequencies can be m apped by location into
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the BM . The base responds to higher frequencies, whereas the apex reacts on low fre­
quency signals. H ence, cochlear m echanics can be understood as mechanical filterbank,
w here the frequency corresponds to a certain location w ithin the BM (frequency map).
The properties o f the cochlea can be explained b y resonance and the traveling wave.
The outer hair cell (OHC) is held responsible for the excellent properties o f sensitivity
and tuning o f the cochlea. The physical m odel o f dam ped resonance based upon OHC
properties seems to model the active m echanism o f the cochlear in an excellent way.
The O rgan o f Corti (OC) [9] can be described as the neuro-sensory elem ent o f the coch­
lea. The OC is seated on the BM and is com posed o f sensory cells such as IH C, OHC and
nerve fibers reaching or leaving the OC. The im plem entation in electrical circuits o f IHC
and nerve fibers is the main part o f this prospective proposal. The OHC are omitted, since
an active feedback mechanism w ould have to be im plem ented. The tectorial m em brane is
bending the OHC stereocilias and leads to K + ion entry into OHC, w hich then leads to its
de-polarization, resulting in the contraction o f the OHC and hence the acceleration o f the
tectorial membrane. The tectorial m em brane bends the IHC stereocilia. The bending re­
sults in the depolarization o f the IHC and triggers the synaptically connected afferent
nerve fibers connected to the IHC.
Physiological m easured data [10], [11], [12], [13] lead to different models describing the
mechanics in the auditory periphery, such as the M eddis model, Carney model and the
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dual A G C m odel [14], [15], [16], A ll m odels follow a similar structure consisting o f three
sections: 1) cochlear m echanics, 2) inner hair cell and 3) inner hair cell to auditory nerve
synaptic transm ission. As previously m entioned, the cochlear m echanics are not within
the scope o f this work.
The choice o f im plem entation for this w ork was the dual automatic gain control (AGC)
m odel [16]. The reasoning behind this choice w as the good m atch to the biological m eas­
ured data, sim pler feedback loops and because the designated task is believed to be the
best choice regarding the transient dynam ic response.
Figure 1-3 gives a symbolic overview o f the different processing stages for the used audi­
tory nerve model. The different processing states are shown from left to right: Input
w aveform , rectification and envelope (m odeling the inner hair cell response), automatic
gain control and spike encoding (m odeling auditory nerve).
Figure 1-3: Overview of processing stages o f the auditory nerve model.
In order to provide an overview, the raw signal processing scheme o f the auditory nerve
model is described. A more detailed description can be found in the later context. The
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m odel used suggests that the IH C can be approxim ated by a stage o f half-w ave rectifica­
tion to address the polarization effect in the Stereocilias and a 2nd order low-pass filter to
approxim ate the transm itter depletion.
R egarding amplitude, the inner hair cell m em brane voltage can be expressed by equation
1-1, using a sum o f two tw o-state Boltzm ann functions [17]
Mv
1 + e x p [- (x - x0) / SxQ]
l + e x p [ - ( x - x ,) / 5 x 1]
^
^
w hich has a very good m atch w ith the biological data, w here IH C mv is the inner hair cell
m em brane voltage, A o ,A j are m odel constants and xo, x j as w ell as S
, S
are express­
ing the transducer displacem ent constants. Figure 1-4 show s the m em brane voltage for
IHC displacem ent o f +/- lOOnm.
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IH C M o d el
0005 '0
-10<b-9
-50
z-9
50E-9
-4E-3-J............
100 E-9
—
Displacement [m]
Figure 1-4: IHC membrane voltage versus displacement.
The m em brane voltage corresponds to the calcium activation w ithin the cell. These
m echanism s are replaced by a sim ple rectification stage to sim plify the overall model.
Concerning the dynam ic response o f the IHC, as a consecutive stage to the half-w ave rec­
tification stage, a low -pass filter centered around a cut-off frequency o f fipf=l kH z models
the transm itter depletion w ithin the IHC for frequencies above fiPf. This cut-off frequency
varies from species to species. In general, the low-pass filtering after rectification causes
the model to lim it its ability to phase lock for frequencies above fipf.
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A nalyzing the m odel at this point leaves a lot o f questions marks. A n input signal is first
bandpass filtered and com pressed through the cochlear mechanics, half-w ave rectified
and then low -pass filtered. Some questions m ight arise; for example, how are higher fre­
quencies perceived? Frequency selectivity is achieved via the location o f the hair cells
along the Cochlea. For frequencies greater than 1 kHz, for example, the signal is ex­
pressed m ore via its energy rather than through its transient behavior.
The low-pass filter form s in conjunction w ith the half-w ave rectifier an envelope detector
for higher frequencies. The envelope detector can be also seen as a form o f RM S or en­
ergy detector. The use o f this analogy brings us to the dual AGC im plem entation that
models the transient behavior o f the auditory nerve. Figure 1-5 shows the basic topology
o f a single elem ent o f the dual AGC. The topology is sim ilar to a standard AGC, except
that it is m issing an RM S detector in the feedback loop and the feedback energy is actu­
ally subtracted rather than added. K1 is constant, w hich m ainly influences the signal am ­
plitude, and too is the loop that filters unity gain frequency response.
X(t)
z(t>
K1
Figure 1-5: Single section of the dual AGC.
15
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In general, this leads to a kind o f differentiator response w ith integrated com pression and
enhances tem poral features. Subsequent signals are suppressed / compressed. The per­
form ance o f this topology is expressed with tw o param eters: onset response (ON) and
steady state response (STS). Figure 1-6 com pares the onset and steady state response o f
the m odel w ith experim ental data acquired by W esterman.
On-Set and Steady-State response
Dual AGC vs Westerman
On-Set Response Dual AGC
On-Set Response Westerman
aT>
3
ft.
3
o
Steady State Response Westerman
-10
Steady State Response Dual AGC
Input [dB]
Figure 1-6: Onset and steady state response of the auditory nerve.
The model agrees w ith W esterm an’s data. O ut o f this graph, the features o f the dual A GC
mechanism can be discussed. The m ain features are the non-linear com pression o f the
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input w aveform by maintaining input dynam ics o f the signal. Steady state signals corre­
spond to signals with frequencies close to DC or to harmonic input w aveform s with t->oo.
The input am plitude is dram atically com pressed down. U nder this com pression, transient
features can be still preserved. A ny change from the steady state translates into a b rief
onset response, which is also com pressed com pared to the input w aveform . In general,
onset and steady state response are preserving transient features that enhance phase accu­
racy [6].
The output o f the dual AGC model does not generate individual spikes but a waveform
w hich represents the instantaneous firing rate o f the nerve in response to the input stim u­
lus. In order to phase encode the output o f the AGC in the circuit im plem entation, a
threshold-crossing spiking neuron w ith absolute refractory time and dynam ic threshold is
used, sim ilar to the SRMO model [18]. The com pression o f the dual A GC relaxes the dy­
nam ic range for the spiking neuron, w hich now has to cover only 25 dB over the 60dB
input range.
1.3 Goals
The goal o f this study is to present an im plem entation o f the current m ode system, w hich
is suitable for sound source localization using auditory models. Suitable is a generic term
and needs a definition. Spike jitter is used as a m etric to evaluate the system perform ance.
17
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Spike jitte r is the ability o f the system to generate a spike event w ithin a certain time
fram e w ithin the limits o f the process com ers and under the presence o f mismatch.
From a system perspective, the im plem entation o f such a V LSI signal processing scheme
is a m assively parallel and the analog design m ust be robust enough to accom m odate all
process com ers to achieve a theoretical design yield near 100% w ithin the process toler­
ance window. Also, the spike generation betw een channels has to stay w ithin a certain
lim it to assure m eaningful correlated output data for sound source localization. Besides
process variation, the design freedom is lim ited by design constraints such as auditory
channels per chip and pow er consum ption. The anticipated goal is 64 auditory nerve
channels per chip with a pow er consum ption «
1W.
H ence, the goal o f this study is to produce an analog V LSI system im plem entation that
m ight find its w ay towards a practical realization, w hich can then be produced in mass.
This processing aspect exists currently only for m inor concerns w ith digital im plem enta­
tion, but it is o f high im portance w hen it com es to analog im plem entation or, in the spe­
cific case o f this implem entation, a w ide array o f analog cells w hich are exposed to all
com ers o f process and m ism atch variation. The target is to m ake the design robust
against these process technology im pacts and to stay w ithin a certain area, pow er and
tim ing window.
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1.4 Overview of the Dissertation
C hapter 2 provides an overview o f the challenges that com es along w ith auditory sound
source localization. Basic m ethods o f acquiring the phase inform ation out o f a signal are
provided and atm ospheric im pacts are briefly discussed. In addition, m easured field data
is provided that is based on auditory sound source localization. These data sets are based
on a PCB board im plem entation o f the overall scheme that translates down into one sim i­
lar to VLSI. The acquired field data gives an outlook o f the overall perform ance capabili­
ties o f auditory sound source localization. The auditory processing scheme is verbally
described throughout the data sets.
C hapter 3 provides an introduction into current m ode signal processing. Basic examples
are provided and evolve rapidly to higher order processing blocks. The main processing
blocks discussed are a fully differential current m ode m ultiplier and an ultra-low fre­
quency current m ode integrator. These are two key com ponents to realize an auditory
model. These circuits are discussed with respect to their circuit perform ance. Some tran­
sient chip data is provided. Also, a novel fully balanced current m ode mirror is intro­
duced. This building block is an im portant com ponent interfacing different current m ode
signaling blocks by providing a high com mon mode rejection ration and high dynamic
19
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range. A dditionally, partly based on the current m ode integrator, a novel current-tovoltage converter is introduced.
Chapter 4 introduces the m ethodology and assumption used to design the system blocks
that are robust against m ism atch variations. The problem o f m ism atch and especially its
im pact on current m ode circuit perform ance is discussed. Circuits introduced in Chapter
3 are theoretically analyzed w ith respect to their robustness to mismatch. Submitted de­
signs are then com pared against theoretical data, sim ulation data and m easured data. The
m ethodology and assum ptions used in Chapter 4 agrees w ith m easured chip data and is
hence valid to design further system blocks.
Chapter 5 picks up the design m ethodology suggested by C hapter 4 and a full current
m ode auditory nerve channel m odel is designed and built. A dditional circuit blocks are
introduced, such as a half- and full-wave rectifier, current com parator and a refractory
signal generator. These building blocks are m erged together to form an auditory nerve
channel. System sim ulation provides transient response data as w ell as M onte Carlo re­
sults. The M onte Carlo results drive the system prediction and expected perform ance data
under the given design. A dditionally some system im plem entation issues such as pow er
consumption, bias distribution and current DC shifts inside the system are discussed.
Chapter 6 concludes the feasibility o f realizing a m assively parallel analog current m ode
system using auditory m odels for sound source localization.
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1.5 Summary of Contributions
This study provides som e contributions that are novel to the analog VLSI community:
•
A com pact pseudo-differential current-to-voltage converter suitable for sm all cur­
rent signals.
•
A n im proved fully differential current m irror w ith high dynam ic range and good
com m on m ode rejection.
•
A n im proved folly differential current m ode m ultiplier
•
A n im proved current m ode integrator suitable for low current signal processing
and ultra low frequency operation.
•
A current m ode spiking neuron based on the SRMO model.
•
First study discussing a m assive parallel auditory nerve current mode signal proc­
essing schem e suitable for sound source localization.
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1.6 References for Chapter 1
[1]
R. Carm ona-Galan, F. Jim enez-G arrido, C. M. Dominguez-M ata, R. Dom inguezCastro, S. E. M eana, I. Petras, and A. Rodriguez-Vazquez, "Second-order neural
core for bioinspired focal-plane dynam ic im age processing in CM OS," IE E E
Transactions on Circuits a n d System s I: Regular Papers [see also Circuits a n d
System s I: IE E E Transactions on F undam ental Theory and Applications], vol. 51,
pp. 913-925, 2004.
[2]
R. Sarpeshkar, C. Salthouse, J. Sit, M. W. Baker, S. M. Zhak, T. K.-T. Lu, L.
Turicchia, and S. Balster, "An ultra-low -pow er program m able analog bionic ear
processor," IE E E Transactions on biom edical engineering, vol. 52, pp. 711 - 727,
2005.
[3]
J. Liu, M. A. Brooke, and K. H irotsu, "A CM OS feedforward neural-netw ork chip
with on-chip parallel learning for oscillation cancellation," IE E E Transactions on
N eural N etworks, vol. 13, pp. 1178-1186, 2002.
[4]
W. Bloom and D. W. Fawcett, A Textbook o f H istology., 12th ed: A H odder A r­
nold Publication, 1997.
[5]
P. Dallos, A. N. Popper, and R. R. Fay, The Cochlea., 1st ed. New York: Springer
Verlag, 1996.
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[6]
S. Deligeorges, T. Gore, A. E. H ubbard, C. Karl, D. C. M ountain, and A. Zosuls,
"Biomimetic Acoustic D etection and Localization System." USA, 2005 (patent
pending).
[7]
H. Helm holtz, D ie Lehre von der Tonem pfindungen als physiologische Grundlage
f u r die Theorie der M usik, ls te d . B runsw ick, Germany: V iew eg-V erlag, 1863.
[8]
G. von Bekesy, Experim ents in hearing. N ew York, USA: M cG raw Hill, 1960.
[9]
A. Corti, "Recherches sur l'organe de Corti de l'ouie des m am m iferes," Zeitschrift
f u r wisschenschaftliche Zoologie, vol. 3, pp. 1-106, 1851.
[10]
L. A. W esterm an and R. L. Smith, "R apid and short-term adaptation in auditory
nerve responses," H earing Research, vol. 15, pp. 249-260, 1984.
[11]
L. A. W esterm an, "Adaptation and Recovery o f A uditory N erve Responses," in
N euroscience (unpublished doctoral dissertation). Syracuse: Syracuse University,
1985, pp. 187.
[12]
L. A. W esterm an and R. L. Smith, "R apid adaptation depends on the characteris­
tic frequency o f auditory nerve fibers.," H earing Research, vol. 17, pp. 197-8,
1985.
[13]
L. A. W esterman and R. L. Smith, "Conservation o f adapting com ponents in auditory-nerve responses.," Journal o f the Acoustical Society o f Am erica, vol. 81, pp.
680-91, 1987.
[14]
R. M eddis, "Simulation o f m echanical to neural transduction in the auditory re­
ceptor.," Journal o f the A coustical Society o f Am erica, vol. 79, pp. 702-11, 1986.
23
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[15]
L. H. Cam ey, "A model for the responses o f low -frequency auditory-nerve fibers
in cat.," Journal o f the Acoustical Society o f Am erica, vol. 93, pp. 401-17, 1993.
[16]
G. S. D eligeorges, "A m odel for tem poral processing in the auditory system," in
B iom edical Engineering (unpublished m aster thesis). Boston: Boston University,
1997, pp. 85.
[17]
G. S. Deligeorges and D. C. M ountain, "A M odel for periodicity coding in the
auditory system.," in C om putational N euroscience: Trends in Research, B. J.M.,
Ed. N ew York: Plenum, 1997, pp. 609-16.
[18]
W. G erstner and M. K. Kistler, Spiking N euron M odels, 1st ed. Cambridge, UK:
Cam bridge U niversity Press, 2002.
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2 Sound Source Localization
The accuracy o f sound source localization is an im portant factor in applications such as
teleconferencing, voice control systems, and robot navigation using sonar or battlefield
surveillance. Several groups have installed free field m icrophone rigs on m obile robots to
endow them w ith localizing capability [1], [2]. Some recent systems have im plem ented
gunshot detectors [3], [4], [5],
2.1 Introduction
Sound source localization is the ability to determine the location o f a sound source in
space. The source orientation is determ ined by its azim uth and/or elevation angle relative
to a predeterm ined origin. I f the angle o f a source is know n w ith respect to at least tw o
different points in space, it is possible to derive the direction o f the sound source.
O ne hundred years ago, Lord Rayleigh developed the so called D uplex Theory, in w hich
he described the Interaural Tim e D ifference (ITD) and Interaural Level D ifference (ILD )
as the prim ary cues for azimuth determ ination o f a hum an listener. ITD strongly depends
on the geom etric relation betw een the sensors, whereas ILD depends on the geom etry o f
the object between the sensors. ILD is highly frequency dependent.
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2.1.1 Plane Receiver
The Tim e-D elay-O f-A rrival (TD O A) is a com mon method to solve for a sound source
direction. In its essence, the time difference At between two signals is m easured and by
know ing the m axim al tim e difference betw een left and right receiver (e.g., m icrophone).
The angle o f arrival can be expressed by equation 2-1:
(2- 1)
max
w here tmax is the tim e difference betw een the left and right receivers. tmax can be calcu­
lated using the speed o f sound c (equation 2-2):
Ax,receiver
t,max
(2-2)
C
The previous equations can becom e very com plex if an interfering object is placed b e­
tween the two receivers, as indicated in Figure 2-1. A plane sound w ave arrives at the
sphere at an angle o f 0. O nce perceived at one ear, the sound needs to travel additional
2-n-r-d/360° + rsin (d ) before it reaches the other ear, w here r is the radius o f the sphere.
The additional term 2-n-rd/360° added to the pure geom etric relation expresses the dif­
fraction o f the sound w ave around the spherical obstacle, or in other words, the additional
way the waveform has to travel “around” the sphere.
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Sound Source
rsin (0 )
r (0)
rsin (0 )
Figure 2-1: Time delay o f arrival
Hence, this is the com ponent that resolves the pure geom etric relation to a m ore som e­
what accurate m odel for sound waves, w hich in general is referred to as head related
transfer function or H RTF. These transfer functions are com plex and norm ally deter­
mined through experim ents. A ssum ing a pure spherical shape o f a head and only a tw o
dimensional sensor configuration, the ITD can be approxim ated as (equation 2-3)
ITD = —•(© + sin ©), - 90° < 0 < +90°
c
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(2-3)
w here c represents the speed o f sound. Exam ining equation 2-3 the ITD is zero if the
sound w ave arrives at an angle 9=0 and reaches its m axim um (equation 2-4)
™ max= - * + l
c v2
j
(2-4)
at 6 = 90. ITD max is around 800ps for a hum an head.
W hen localizing a targeted source, in m ost cases it is crucial to determ ine w hether the
signals received by the sensors have been generated by the source in question or not. E n­
vironm ental noise, reverberation, sound shaping through nearby objects (e.g., the sensor
itself) and H RTF make sound source localization a challenge.
2.1.2 3D Sound Localization
Out-of-plane sensor configuration allows the calculation or bearing and elevation. M athe­
matically, the problem can be described as following: The exam ple is based on a tetrahe­
dron-shaped sensor, shown in Figure 2-2. The tim e o f arrival is determ ined at each m i­
crophone. As sim ple as this sounds, this is the m ain challenge in sound source localiza­
tion, since this process indicates that the sam e signal w as detected at each m icrophone.
The time o f arrival can then be transform ed into a six-dim ensional vector dt. dt represents
28
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delta tim e betw een the time o f arrival at each sensor divided by the speed o f sound. The
task is to find a vector that maps the acquired distance vector dt to the tetrahedron dis­
tance m atrix A o f the tetrahedron.
B,
Figure 2-2: Tetrahedral arrangement of sensors
In general, this can be expressed as (equation 2-5):
A = P -d t
(2-5)
where A is tetrahedrons distance matrix, dt the acquired distance vector, and P the result­
ing position vector (normal vector). Expanding equation 2-5 results in (equation 2-6):
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Solving equation 2-6 by right hand side division gives the norm al vector o f the incoming
sound source (equation 2-7):
P - A \d t
(2-7)
P is the normal vector to the sound source. A n arctan-transform ation betw een the three
com ponents o f the vector delivers the relative sound source angle. This simple math ap­
proach is only valid, however, for free-spaced sensor configurations. Systems such as [3],
[4], [5] or [6] are using this sensor configuration and sim ilar m athem atical routines. As
indicated in Chapter 3.1.1, the solution becom es more com plex once an object is placed
betw een the sensors and a more refined m odel expressed as a H RTF is needed to solve
the localization problem.
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2.2 Defining noise
In the case o f electrical circuits, noise can be nam ed easily since it is related to its m ate­
rial: W hite noise is due to the random m otion o f the electrons in the conductor; flicker
noise is traced back for integrated circuits to surface states o f the processed sem iconduc­
tor surface. Both o f these noise sources are uncorrelated and hence w ill define from an
electrical standpoint w hat the dynam ic range will be and w hat signal range can be proc­
essed.
H aving a look into the incom ing audio data, the definition o f noise can be expressed as
everything that is not the signal to be detected. Using a m ultiple m icrophone setup, the
only uncorrelated noise source is the m icrophone itself, w hich is again electrical in its
nature. All other signals converted into an electrical signal are correlated, w hich is, o f
course, the essence, using a m ultiple sensor setup, but this m akes interpretation o f the
signal m uch harder.
The signal to be detected has to be separated by other correlated sound sources such as
running w ater from a nearby river, w hich would be close to a correlated w hite noise
source, any m an-m ade sound sources such as engine noise, and o f course, hum an speech.
Further examples are w ind that can seem highly correlated at the sensor, raindrops if they
hit the sensor w ithin a certain time frame or crickets that can generate in masses a quite
high environm ental noise floor.
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2.3 Atmospheric Impacts
One focus o f the sound source localizations scheme is the localization and detection o f a
gunshot, especially the m uzzle blast. Since the opening o f the gun barrel is much sm aller
than the w avelength o f the m uzzle blast, a gun can be regarded as a point sound source.
The initial blast contains a w ide spectrum o f frequency content. The fundam ental har­
m onic o f the gun blast o f a rifle is in a frequency range o f 200 - 400 Hz, w hich relates to
the length o f the gun barrel. The barrel is filled with highly pressurized gas and is re­
leased after the bullet opens up the barrel. The positive pressurized gas results in a sharp
onset in the nearby atm osphere and spreads out in a radial pattern. The harm onics o f the
initial blast a w ideband w ith additional sound shaping by explosive residue.
As this pressure w ave travels through air, high frequency inform ation is m ore and m ore
filtered out due to the absorption o f air. Equations 2-8 describe the atm ospheric absorp­
tion process in air [7], w here a is the absorption coefficient, f is the frequency, T is the
temperature in K elvin w ith To as reference temperature, h is the hum idity in %, Fr o is the
oxygen relaxation frequency and Fr>N is the Nitrogen relaxation frequency Figure 2-3
shows the absorption in air for frequencies versus distance.
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/
a -
1/2
869- / 2 1 .8 4 - 1 0 11 -
- 5 /2
+ 'L
-2239.1 I T
12.75 -10 3 -
V
e
\
-3 3 5 2 I T
,
+106.8 10 3
K,o + f 2/ F r,N
K o+flF r*.
y
F 0 = 24 + 4.04-104 h- °-02 + h.
r’°
0.391 + /?
f
rji
T
\
- \n
v -T'o
(
U n ^ T '
9 + 280 ■h-e'
^
J
J
Tn = 2 9 3 .1 5 °/:
(2-8)
Besides this classical absorption model o f air, in addition, w eather conditions, ground
interaction, atm ospheric turbulence, vegetation, obstructions and barriers influence tre­
mendously the reshaping o f the traveling sound w ave and m ake it hard to draw any as­
sumptions about the incom ing signal. This m akes acoustic sound source localization to a
blind source a problem . Besides the signal that should be detected and localized, other
sound sources overlap w ith the incom ing signal. These “other” sound sources are in this
respect noise sources w ith variable amounts o f coherence. In a conducted field test,
crickets added a significant am bient noise level. Also, m an-m ade sound sources such as
engine noise w ill contribute to the overall noise floor w ith respect to gunshot detection.
The scenario is o f course inverse if the application is m eant to be for vehicle tracking.
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Atmospheric Absorption: Distance-Frequency, T=300k, humidity = 70%
D istance [m]
Frequency [Hz]
Figure 2-3: Distance-frequency relation o f atmospheric absorption.
For frequencies above 1 kHz, the absorption increases rapidly over distance. A tm ospheric
absorption is an im portant im pact for gunshot localization tasks. The bottom graph o f
Figure 2-4 shows the waveform o f a received gunshot. The upper graph represents the
same signal received 20m further aw ay from the current position o f the receiver. The
relative hum idity is set to 70%.
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Atmospheric Absorption Only: Hypersonic and Gunshot 20m from Receiver
■o 0.5
-0.5
0.05
0.1
0.15
0.2
0.25
0.3
Time [s]
Atmospheric Absorption Only: Hypersonic and Gunshot at Receiver
0.5
-0.5
0.05
0.1
0.15
0.2
0.25
0.3
Time [s]
Figure 2-4: Simulation o f atmospheric absorption
Figure 2-4 visualizes the significance o f atm ospheric absorption to a gunshot signature.
The hypersonic portion o f the signal (first w ave front) decays rapidly w ithin the 20 m eter
range. This behavior could be observed in local perform ed field tests. The m uzzle blast is
only limited and im pacted by the atm ospheric absorption model.
Due to this strong relation to atm ospheric absorption, hypersonic inform ation is only de­
tected in the current system im plem entation, but not further processed to this point. BBNs
gunshot detector system [5] is using hypersonic inform ation to perform localization tasks.
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D oing so puts a natural limit on the sensor perform ance. The bullet has to travel close by
in order to be detected. Also, m ultiple stable m easurem ents have to be performed, in or­
der to determ ine the bullet path and trace back the shooter position. A sensor network
w ould give a better perform ance regarding the determ ination o f the bullet path, but this
again puts constraints on the reliability o f such a system. The suggested prototype is us­
ing only the m uzzle blast to detect the origin o f the shooter. H ypersonic inform ation is
treated as an added bonus.
2.4 Available Approaches and their Drawbacks
A lthough an extensive am ount o f research has been dedicated to this field over the last
decades, no com m on application or standard has been established yet. M any approaches
use cross-correlation to detect the phase difference betw een tw o signals, w hile other ap­
proaches enhance the data using additional algorithm s such as noise cancellation or bio­
logical m otivated approaches [4]. N ext, the existing approaches and their limitations will
be discussed briefly. To conclude, an innovative system w ith enhanced perform ance will
be presented.
M ost existing systems use large baselines (up to hundreds o f m eters o f microphone sepa­
ration) to resolve the task via traditional triangulation. For exam ple, the system Shot
Spotter [3] consists o f an array o f sensors w here the obtained data is then enhanced via
netw ork data fusion.
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It is obvious that sm aller baselines are much more desirable, since they open the possibil­
ity o f m ore flexible and integrated solutions. But as the baseline decreases, the task b e­
comes m ore and m ore challenging, since the phase differences to be resolved will only be
in the order o f few m icroseconds. To date, such systems are not very com m on and lim ­
ited by the available angular resolution and robustness (e.g., B oom erang by BBN [5]).
2.4.1 Sound Source Localization using DSP
M ost o f the available systems use digital signal processing (DSP) im plem entations. Fo­
cusing ju st on the estim ation o f the TD O A value, DSP techniques include cross correla­
tion, generalized cross correlation and cross-power spectrum phase methods. In general,
each frequency band has the same im portance in the cross correlation. Hence, depending
on the sound source, only a finite w indow region o f the spectrum w ill contribute useful
inform ation to the sound source location. Exceptions are w ide-band signals such as any
im pulsive source (e.g., ham m er blow , shot, clapping, etc) [8]. These wide-band signals
are naturally short transients and introduce another lim itation o f DSP: sampling fre­
quency. M any DSP tasks are perform ed utilizing the frequency dom ain and hence avoid­
ing the time domain w hich is com putationally intensive if non-linearity is introduced (e.g.,
automatic gain control AGC). Cross-correlation itself can be deployed on tim e-based sig­
nals but is com putationally very intensive and delivers depending on signal-to-noise ratio
and the coherence o f other noise sources limited perform ance.
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The following exam ple shows the com putational effort estim ating TD O A using cross
correlation technique. N samples (e.g., using a sliding w indow w ith 50% overlap) ac­
quired from two m icrophones w ith distance d are com puted w ith a simple cross correla­
tion to express the coherence m easure (equation 2-9)
n=0
w here xi[n] is the signal from receiver i and x is the correlation lag in sample points. The
cross correlation is reaching its m axim um at the offset o f both signals. The com plexity o f
this operation is O (n ). In order to reduce the com plexity to 0 ( n ,log2(n)), an approxim a­
tion can be derived in the frequency domain by com puting the inverse FFT o f the cross­
spectrum. To put the com plexity estimate into real num bers, follow ing exam ple is as­
sumed: The sam pling frequency is 44.1 kH z and the baseline betw een the two receivers is
0.254 meters. The speed o f sound is assumed to be 330 m/s. H ence, the m axim um time
difference betw een the two receivers is roughly tmax=770 us resulting at the correspond­
ing sampling frequency to 34 samples acquired. A ssum ing 0(n'log2(n)), 62 m ultiplica­
tion within tmax have to be perform ed. One floating point m ultiplication can take 40 clock
cycles to be executed. Taking all these num bers into account, a m ultiplier w ould have to
run at 3.2 MHz to perform this specific cross-correlation in real-tim e neglecting any other
execution overhead.
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This approach has a lim itation on the statistical properties o f the sound source. Even
though several techniques such as spectral w eighting functions and w hitened cross­
correlation can be used to optimize the com putation [9], the am ount o f algebraic opera­
tions needed lim its this concept. A biologically m otivated approach offers different im ­
plem entations to solve sound source localization.
2.5 Auditory Localization and Interaural Time Delay
Even though biologically m otivated auditory m odels should be the key to solve this prob­
lem, the use o f auditory m odels for signal processing or in this case for sound source lo­
calization is hard to find. There are only a few groups that take the biom im etic inspired
route to resolve this task: The V LSI Research Lab at Boston U niversity in collaboration
with the Hearing R esearch Center at Boston U niversity [10], Signal Systems Corporation
in conjunction w ith John Hopkins University [11] and Safety Dynam ics in collaboration
with the U niversity o f Southern California [4],
Cross correlation techniques are standard processing schem es and it is hard to find appli­
cations without it. B ut by using auditory models, one has to overcom e the fact, that solid
cross-correlation is replaced by neural spike encoding m arking tim e-based events w ith a
single spike. Before the spike-data-encoding, a non-linear pre-processing schem e is im ­
plemented as it w as introduced in Chapter 2: A band-pass limited signal is first rectified
39
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and low-pass filtered at around 1 kHz. Even higher frequency channels will be filtered at
1 kHz, delivering only the envelope to the subsequent stages. This filtered output is then
processed by the so called dual AGC m odel, w hich in its topology is very close to a real
AGC. In its dynam ics, it responds to changed input am plitudes w ith subsequent com pres­
sion o f periodic tones.
O ur approach presented here is based on a biom im etic solution utilizing biological m od­
els to enhance temporal features and to spike-encode the phase differences. Due to the
am ount o f algebraic com putation needed that by far exceeds a cross-correlation method,
the difficulty to realize a real-tim e processing scheme in the digital domain has led us to
choose an analog VLSI im plem entation. This obvious trade-off is rew arded by an excel­
lent system perform ance regarding accuracy and robustness. The biom im etic approach is
also universal regarding the sound source to be detected and hence makes it a potential
candidate to set a standard for sound source localization. Chapter 2.6 provides some pre­
liminary results achieved w ith a proto-type version realizing auditory models in analog
circuitry. By using this approach, w e are able to achieve good results using very small
baselines (dow n to one inch m icrophone separation).
2.5.1 Time-Frequency Signal Processing
A udio signal processing is using the tim e-frequency domain to perform any desired sig­
nal transform ation or filtering. Signal processing schemes trying do interpret the audio
40
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inform ation such as speech recognition or direction finding use generally the m ethod o f
m apping the audio data into both tim e and frequency. The m ost com monly used tech­
nique is the Fourier transformation, w hich divides the frequency space into finite slices
and its resolution is only limited by the sam pling rate. This space can be segm ented by
using different m aps such as a Fourier or D irac map. The Fourier map uses a w ider sam­
ple base to represent the frequency inform ation. In this way, this map delivers very good
frequency inform ation. The Dirac m ap on the other hand only uses a very small sample
base and has a lim ited capability to represent frequency inform ation but com pared to the
Fourier map, it has a better a time resolution [12]. The w avelet transform ation combines
both maps.
2.5.2 Sensor Setup
The overall signal processing can be divided into four main blocks: front end filter, audi­
tory signal processing, spike encoding for pitch and bearing, and detection. T he front end
filter plus the auditory processing schem e precondition the input signal in such a way,
that the phase inform ation is conditioned for signal encoding. The spike encoding can be
described as a threshold crosser w ith adaptive threshold. Om itting the adaptive threshold
for a moment, a signal out o f the auditory processing path is time stam ped at a certain
threshold. The occurrence o f two spikes o f the same frequency band but different channel
(e.g., microphone one and m icrophone three in a 3 kH z frequency band) but w ithin a cer­
tain time interval marks a bearing event.
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The input into the system is an audio signal from in space separated sensors. Sensors in
our case refer to a com m on m icrophone. A m inim um o f tw o sensors is needed to do
sound source localization. For other applications such as m achine monitoring, a mono
system can be sufficient. The num ber o f m icrophones adds to the com plexity o f the sys­
tem. In the case o f the biom im etic front-end, w hich is com posed o f a filter and auditory
signal conditioning, this portion scales linear w ith the num ber o f m icrophones added. The
bearing unit scales with the num ber o f edges betw een the m icrophones. The num ber o f
theoretical bearing pairs available is N /2*(N -1). For a tetrahedral configuration with N=4,
a num ber o f six edges is available to determ ine the location. The num ber o f edges deter­
m ines certain system capabilities. Table 2-1 provides an overview.
Number microphones
Available edges
Capability
Limitation
2
1
Bearing
Front-back ambiguity
3
3
Bearing
4
6
Bearing / Elevation
5
10
Bearing / Elevation
6
15
Bearing / Elevation
Table 2-1: Number o f microphones versus available edges.
For the case o f using two m icrophones, the problem o f front-back am biguity arises. The
system can not distinguish, if the signal came from the back or from the front since only
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the tim e o f arrival o f one single pair is available and hence tw o solutions exist. In the case
o f a hum an listener, these am biguities are norm ally not observed. This can be explained
by tw o m echanism s that are norm ally not used in artificial sound source localization sys­
tem s: interaural Level D ifferences or ILD and the shape o f the pinna, w hich provides di­
rectionality. R egarding ILD, the hum an head is an obstacle is the signal path and due to
head shadowing, level differences in the sound energy can be observed. This effect can
be observed in the daily life. I f one is not certain o f the direction o f the sound, the head is
m oved towards a norm al position regarding the potential source o f the sound. In this way,
the head is aligned in such a w ay, that ITD and ILD are at its m axim um .
T he num bers o f edges determ ine also the redundancy capability o f such a system. A four
m icrophone system can determ ine bearing and evaluation. I f one sensor is faulty, the sys­
tem still has the ability to perform by reporting only bearing inform ation.
2.5.3 Temporal Behavior of the Auditory Model
The signal processing scheme o f the auditory nerve model is from a first order perspec­
tive not very intuitive. As a w orst case example, a 10 kH z input w aveform is first recti­
fied, than 1 kH z low -pass filtered before it is sent into a structure that is sim ilar to an
AGC. The resulting output w aveform is then time tagged w ith a spike function that is de­
pendent on previous events. In standard signal processing schem es, one would acquire
the signal, filter it (such as active noise control), try to enhance it further and analyze the
43
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signal using cross-correlation methods. The second approach sounds less exotic and more
likely to achieve useable results and people, not fam iliar w ith auditory models, w ould
rather choose the standard approach then a stranger biom im etic approach. A nd there is
much truth behind this. Just using the overall m odel w ithout understanding its dynamics
will lead to a rather po o r perform ing system. Biom im etic processing has to be understood
in order to be useful. The following sections will describe in a verbal m anner the dynam ­
ics o f the biom im etic signal processing.
2.5.3.1 Filterbank Front End: Asymmetric versus symmetric.
The shape o f the front end filter bank has certainly im pact on the overall signal process­
ing scheme. The filter front end is not part o f the overall system im plantation in this study,
but since it is im portant to the overall behavior, it is here shortly discussed.
A symmetric band pass filter with Qs adjusted for optimal band overlap m ight be the first
choice realizing this front end. These filters w ere tested, and good results could be
achieved. A less straight forward choice is an asym m etric filter bank or in a m ore bio­
logical senses a cochlear like behavior. The cochlear is a highly non-linear, asym m etric
filterbank with dynam ic compression. The interested reader can find more detailed in­
formation under [13]. Figure 2-5 shows asym m etrical front-end filter m agnitude and
phase responses o f different center frequencies.
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Magnitude Response of Asymetrical / Cochlear Like Filterbank
Frequency [Hz]
P hase R esponse o f A sym etrical / C ochlear Like F ilterbank
300
250 —
50
10
10
10
Frequency [Hz]
Figure 2-5: M agnitude and phase response o f an asymmetrical bandpass filter front end.
The asym m etry has the follow ing im pact to the system: The frequency inform ation is dif­
ferently weighted. The higher frequency end is abruptly cutoff, w hereas low er frequency
information is passed through more and adds to the overall DC value in the D ual A GC
stages, allowing sharper onset responses to small changes. N evertheless, the m ain signal
is centered around the center frequency o f the filter.
The filterbank is the very first stage in this non-linear processing scheme. A ny error m ade
at the very front will be inherited through the system. D ue to the nonlinear behavior o f
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the system , calibration schemes cannot be utilized. This fact is pointed out since for ana­
log front end filters, phase m atching is a key issue. In one o f the prototypes, an analog
front-end based on discreet RC com ponents w as designed. Figure 2-6 displays the m atch­
ing criteria o f such an analog front-end for filter frequencies from 100 Hz to 10 kHz.
A sym etrical Band Pass F ilter D elay u nd er D ifferent M atchin g C onditions
R=l%, 0 2 %
R =0.1% , C =0.2%
R =0.01% , 0 0 . 0 2 %
10
3 io
10
F ilterb an k Nr.
Figure 2-6: Maximum phase delays under different matching conditions of passive components.
In the case o f a discrete version, m atching in the order o f lOOppm has to be achieved in
order to resolve m icrosecond resolution. The task becomes m ore challenging, w hen ap­
proaching lower frequencies. A n analog integrated version o f such a filter configuration
would have extremely high m atching constraints in order to preserve the relative phase
inform ation across channels.
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2.5.3.2 Auditory Nerve: Frequencies above 1 kHz:
The rectifier in conjunction w ith the 1 kH z low-pass filter can be regarded in its function­
ality as a RM S detector for frequencies above 1 kHz. The resulting output curve consists
o f a DC value with attenuated am plitude inform ation riding on the dc value. This signal
goes into the dual AGC structure, w hich w ill com press the DC value to a certain level,
but accentuates any transient changes. Pure harm onics w ill be also com pressed. This in­
form ation goes into the spiking neurons. For harm onic inform ation, the spiking neuron
does, due its frequency limitation, not any phase locking. For any harm onics, depending
on the frequency content o f the input w aveform , a random num ber o f cycles w ill be
skipped. Nevertheless, the channels above 1 kH z are not useless. First, any change in am­
plitude (e.g., short transient, any other onset in the time domain) w ill be accentuated by
the dual AGC and hence overrepresented to the spiking neuron, w hich is syncing up on
this event and correctly time stam ps the event. Pure harm onics w ill be perfectly com ­
pressed by the dual AGC structure. N evertheless, pure tones are hard to find in realistic
environm ental conditions.
2.5.3.3 Auditory Nerve: Frequencies below 1 kHz.
For frequencies below the cut-off frequency o f the 1 kH z low-pass filter, only the rectifi­
cation process and dual AGC stage are im portant. The dual AGC w ill create a sharp on-
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set response for the first couple o f periods o f low frequency signals due to the rectifica­
tion process. Since the dual A GC has a very low frequency feedback system , the overall
R M S dc value is achieved in the dual AGC stage. The dual A G C at this point begins to
suppress the harm onic nature o f the incom ing signal. A fter a couple o f periodic cycles,
the onset response o f the incom ing signal w ill be suppressed to a value close to the steady
state response. The dual A GC feeds into the spiking neurons. Since the spike rate is faster
than the maxim um input frequency, spikes w ill lock into the input w aveform and code
each phase change. Since the dual AGC reacts w ith an on-set response to the rectified
input waveform, good spike synchronization to the input data can be achieved.
2.6 Auditory Sound Source Direction Finding Prototype
A prototype for the auditory processing w as built as a group effort in the VLSI Neural
Systems lab at Boston U niversity, based on printed circuit boards (PCB). Based on this
system, a more advanced version w as designed incorporating features beyond this thesis.
Interested readers are referred to [14]. In general, the individual functions were im ple­
m ented using discrete elements such as resistors and capacitors and discrete active ele­
m ents such as Opamps, m ultipliers, diodes and transistors [15], [10]. The bearing infor­
m ation is extracted using a X ILIN X FPGA chip [16]. The overall system in size is ap­
proxim ately 12”x7”x6” and supports two m icrophone inputs.
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2.6.1 Vehicle tracking using a one cubic inch Sensor
The system was used for a field test at the U.S. A rm y Installation Aberdeen Proving
G round (APG). The front end was a one cubic inch sensor w ith standard hearing aid m i­
crophones built in. The task o f this field test was to track different vehicle classes around
a 700m long and 100m w ide oval track (Figure 2-7).
Figure 2-7: Area photo AGP
Four vehicle classes w ere tested. The examples consisted o f a M 60 tank, a M 548 trans­
porter, a M983 Heavy Expanded M obility Tactical Truck (H EM M T) and a M 998 HighM obility M ultipurpose W heeled V ehicle (HMM W V). The M 60 and M548 are tracked
vehicles. The sensor setup followed all vehicle classes w ith a real-tim e update interval o f
10 Hz. Figure 2-8 shows the error in degrees o f the tracking result versus ground-truth
global positioning system (GPS) data for all vehicle classes.
In general, the tracking
stayed within a +/-5 degree error window.
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Error Sensor-GPS vs. TRACKED Distance ALL Vehicles
10H
0
100
200
300
400
'
500
600
distance [m]
Figure 2-8: Ground-truth referred error for all vehicle classes.
Exam ining Figure 2-8, the error at close range shows a lot o f deviation. This can be ex­
plained as follows. F or sound source localization, a point source is norm ally assumed. A n
M548 within 25 m o f sensor range does not satisfy this assum ption and squeaking, track
noise and engine noise are summing up, introducing an a larger variation o f the error.
Gradient flow techniques can be used to im prove sensor perform ance in close range, e.g.,
tagging a tracked object w ith a velocity vector w hich has to stay in physical boundaries.
At long range, the tracking o f the M548 and M 60 was fairly good. Since the input signal
o f the one inch sensor is w eak at these distances, other objects such as airplanes som e­
times got the attention o f the detection algorithm .
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Figure 2-9 shows the error histogram o f the M 548 only, representing a 200-second re­
cording interval at a 10 H z update interval o f the M 548 around the 700m oval track. A p­
proxim ately two sigm a stayed w ithin the +/-5 degree error window.
Error Sensor-GPS M548 200 seconds
-6
-4
-2
0
2
4
6
error [degree]
Figure 2-9: Error referred to ground truth data for a M 548,200 seconds.
Overall, the tracking perform ance o f the one inch sensor was very good and proved the
excellence o f auditory m odels for sound source localization. The used im plem entation at
that time was in a very early prototype stage. R efined versions showed im proved per­
formance. Besides the accuracy, the field test show ed that the encoding scheme p roved to
be very robust.
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2.6.2
Gunshot Detection using Auditory Models
A t the A PG test site, gunshots and artillery fire could also be detected with the sensor
configuration that was used. This is rem arkable, since the system w as designed to track
continuous signals. Gun shots and artillery are short transients. Follow up research w ith
the A rm y Research Labs (ARL) intensified this research direction.
2.6.2.1 Characteristics of a Gunshot
Figure 2-10 shows a typical w aveform o f a gunshot. The first sharp transient at 50ms is
the hypersonic shock wave from the bullet, follow ed by in am plitude a smaller and fast
decaying w ave front betw een 75 and 100ms. This secondary wave is the result o f ground
reflections along the bullet path from the hypersonic shock wave. A round 150ms, the
m uzzle blast o f the gun arrives at the sensor.
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Typical Signature o f a Gunshot
Hypersonic shock wave
0.4
M uzzle B last
u - 0 .2
- 0.6
G round reverberation due to
- 0 .8
the hvnersnnie shock w a v e
0.05
0.2
0.25
0.3
Figure 2-10: Characteristics of a gunshot.
H ypersonic shock waves result because the fired projectile travels faster than sound. D e­
pending on the caliber, bullets travel around 2.5 the speed o f sound. Figure 2-11 shows a
shadowgraph o f a hypersonic bullet during flight. The shock w ave is leaving the projec­
tile at a characteristic angle. This angle is m ainly a function o f the bullet speed (M ach
angle) and tip angle o f the bullet itself. By know ing the bullet flight path, and the distance
to the shooter, the mach angle can be used to narrow down different types o f calibers.
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'7.(>2ntlllNATO H l l.1 l : 1 fu K l'P E K S O M C 11.1<;II I
[7S0ni/s - 2559Cs]
Figure 2-11: Picture o f a 7.62mm NATO bullet in supersonic flight [17].
2.6.2.2 Auditory Model Representation of a Gunshot
Figure 2-12 combines the acoustic transient o f a gunshot and the sum m ed output o f the
auditory signal processing scheme before the spike encoding. The summed output is
com posed o f 16 channels connected to the same receiver and gives a visual representa­
tion o f the energy coding w ithin the system.
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Sound Input / Summed Auditory Output
Sum m ed auditory ouput
<
0 .4
Z
0.2
Sound Signal
- 0.2
0.1
0.2
0.3
0.4
0.5
0.6
0.7
time [s]
Figure 2-12: Summed auditory output response to a gunshot.
The first sharp transient o f the sound source is a hypersonic shock wave. The input w ave­
form is norm alized. To put the reader back to scale, the hypersonic shock wave in this
picture is approxim ately 150 dBSPL followed by a m uch sm aller transient, the muzzle
blast, w ith an am plitude o f around 120 dBSPL. This extrem e exam ple gives a good in­
sight about the adaptive nature o f the auditory signal processing scheme. The summed
auditory output takes little dynam ic range due to the non-linear signal processing and
com pressing techniques. M ost im portant, the transient features are preserved and actually
tem porally enhanced across channels. A nother im portant feature that can be seen from
this figure is that energy is stored w ithin the system. B y only adjusting to transient
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changes, an internal DC level is formed. All tem poral enhancements start at this DC level
and hence an auto-adjustm ent to environm ental noise floors is achieved.
Figure 2-13 shows the auditory output before the spike encoding for individual channels
represented as center frequency. The figure corresponds to the data displayed in Figure
2-12 but instead show s the summation— all 16 frequency channels are shown. The hyper­
sonic shock w ave is encoded throughout the 16 channels, whereas the m uzzle blast only
occupies certain frequency regions. This frequency behavior is later exploited in order to
identify the signal type. It should be noted that the spiking neurons w ill additionally sort
out inform ation w ith respect to phase information.
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Auditory Output Response to a Gunshot
C e n te r F re q u e n cy [Hz]
Figure 2-13: Output response of the auditory model to a gunshot.
2 .6.23
Experimental Results
Instead o f using a one inch sensor, the A rm y Research Lab (ARL) provided a data set
from a H M M W V -based m icrophone setup w ith a sensor spacing o f six feet. Figure 2-14
shows the urban test setup w ith m ultiple buildings along the bullet path. This setup re­
sulted in very coherent reflections o f the m uzzle blast and hypersonic shock w ave from
the walls o f buildings as well from H M M W V itself, where the receiver m icrophones
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w ere m ounted. The test data set w as 161 shots, fired from different positions, including
shots out a window.
ARL Set2
Distance Shooter-HMMWV:48.3 m
_ Gnd Truth Angle to Shooter:6.23 deg
Map: One Tick 1 0 m _______________
Back Line
BldgD
FLT
Front Line
Bank
Bldg
# POSS
V POS3
BldgF
POS2
* POS1
Bldg K
Figure 2-14: Test setup ARL data set.
Table 2-2 gives an overview over the test results processed through the first generation o f
the auditory sound source detector based on the data set provided by ARL. The set was
161 shots strong and was com posed o f m ultiple sets reflecting different shooter locations,
for example, a shooter laying on the ground or shooting out o f a w indow from an ele­
vated floor. Out o f 161 shots, 28 shots w ere m issed or miss-classified. The average m ean
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error to the ground truth data was 1.0°. The m aximum error w as 9.5°. The repeatability o f
the m easurem ent result expressed as the standard deviation a w as 1 . 1 °.
Set N um ber
2 -8
A verage M ean Error
M axim um Error
Standard D eviation
M issed
9.5°
1.09°
28/161
. °
1 0
Table 2-2: Gunshot data results processed through prototype.
The overall sensor perform ance w as good. A dditional local field tests were performed
and im provem ents to the prototype setup w ere made. The accuracy o f the system in the
2m spacing configuration could be im proved to o<0.5° for the m uzzle blast and o<2.0°
for hypersonic shock w aves (which includes the inaccuracy o f the shooter targeting a pre­
defined target and hence defining a bullet path). The detection rate w as higher than 90%
in a highly reverberant environm ent. A prototype w as delivered in M arch 2003 to ARL.
O ngoing funding opened the opportunity to adopt the system to a helm et-based system
(2004, eight inch sensor separation) and to a m obile robot platform (2005, eight inch sen­
sor separation, iRobot Packbot system).
2.7 Data processing extension - correlated vector feedback.
This biomimetic signal processing schem e can be further enhanced. For vehicle tracking,
correlated output from the bearing m odule can be used to adjust gain settings in the chan-
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nel in the front end. In this w ay, the signal-to-noise ratio is enhanced according to its cor­
relation to signal input pairs. This scheme can be enhanced by using a classifying func­
tion to provide further feedback into the front end. This classifier w ould m ask out events
and keep track o f selected events.
2.8
Summary
This chapter provided an overview on different aspects o f sound source localization.
Som e basic schem es regarding sound perception using m ultiple sensors w ere provided.
A dditionally, atm ospheric aspects were discussed in conjunction w ith gunshot detections.
A dditionally, field data from a prelim inary auditory nerve sensor prototype was presented.
2.9 References
[1]
J. Huang, "A m odel-based sound localization system and its application to robot
navigation," Robotics a n d autonomous system s, vol. 27, pp. 199-209, 1999.
[2]
J. W eng and K. Y. G uentchev, "Threedim ensional sound localization from a
compact non-coplanar array o f m icrophones using tree-based learning," A cousti­
cal Society Am erica Journal, vol. 110, pp. 310-323, 2001.
[3]
ShotSpotter, "w w w .shotspotter.com ."
[4]
T. Berger and U. o. S. California, "w w w .safetvdvnam ics.net/products.htm ."
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[5]
B BN -Technologies, "w ww .bbn.com /boom erang/index.htm l."
[6 ]
M etravib, "gunshot-detection.01db-m etravib.com /."
[7]
A N SI, "A m erican N ational Standard M ethod for the Calculation o f the A bsorp­
tion o f Sound by the Atmosphere," Am erican N ational Standards o f the A cousti­
cal Society o f Am erica, vol. S I, pp. 35, 1995.
[8 ]
P. Pertila, T. Pirinen, A. Visa, and T. K orhonen, "Com parison o f three post­
processing m ethods for acoustic localization," P roceedings o f SPIE, vol. 5090, pp.
9-17, 2003.
[9]
J.-M . Valin, F. M ichaud, D. Letoum eau, and J. Rouat, "Robust sound source lo­
calization using a m icrophone array on a m obile robot," Proceedings IE E E /R SJ
International Conference on Intelligent Robots a n d System s, pp. 1228-1233, 2003.
[10]
C. Karl, H. I. Cohen, G. S. Deligeorges, T. Gore, D. C. M ountain, M. N ourzad, Z.
Y ang, A. Zosuls, and A. E. Hubbard, "Real-tim e A uditory Signal Processing for
Sound Localization in B attlefield Acoustics," presented at Proceedings o f the
Eighth International Conference on Cognitive and N eural Systems, Boston, M A,
2004.
[11]
P. Julian, A. G. Andreou, L. Riddle, S. Sham m a, D. H. Goldberg, and G. Cauwenberghs, "A com parative study o f sound localization algorithm s for energy
aware sensor netw ork nodes," IEEE Transactions on Circuits a n d System s I:
R egular Papers [see also IE E E Transactions on Circuits a n d Systems I: F unda­
m ental Theory a n d Applications], vol. 51, pp. 640-648, 2004.
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[12]
N. H ess-N ielsen and M. V. W ickerhauser, "W avelets and tim e-frequency analy­
sis," Proceedings o f the IEEE, vol. 84, pp. 523-540, 1996.
[13]
Z. Y ang, "Low -frequency analog integrated circuit design using current-m ode
techniques," in Electrical Engineering (unpublished doctoral dissertation). B os­
ton: B oston University, 2004, pp. 235.
[14]
S. D eligeorges, T. Gore, A. E. H ubbard, C. Karl, D. C. M ountain, and A. Zosuls,
"Biom im etic A coustic Detection and Localization System." USA, 2005 (patent
pending).
[15]
C. Karl, Z. Y ang, G. S. Deligeorges, D. C. M ountain, H. I. Cohen, A. Zosuls, and
A. E. Hubbard, "A Current-M ode, M ixed Signal VLSI Auditory N erve Chip,"
presented at Proceedings o f the Seventh International Conference on Cognitive
and N eural Systems, Boston, M A, 2003.
[16]
T. Gore, J. Boura, A. Cherry, H. I. Cohen, G. S. Deligeorges, C. Karl, D. C.
M ountain, A. Terrinoni, A. Zosuls, and A. E. Hubbard, "A Pitch and Bearing
A uditory Feature Extractor Im plem ented in an FPGA," presented at Proceedings
o f the Seventh International Conference on Cognitive and N eural Systems, B os­
ton, M A, 2003.
[17]
R. Nennstiel, "Picture o f a 7.62m m N A TO bullet in supersonic flight.." W ies­
baden, Germany: B undeskrim inalam t (BK A) W iesbaden(Federal B ureau o f In­
vestigation).
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3 Current Mode Circuits
C hapter 1 and 2 provided some insight into the topic o f auditory sound source localiza­
tion. The current existing system suitable for m obile-based system such as helmetm ounted sensors and robot-m ounted systems, the overall costs are still quite high. In or­
der to realize a small com pact and universal system setup, an integrated realization o f the
processing scheme is highly desirable. C hapters 3 to 5 will focus on the V LSI im plem en­
tation o f the outlined processing scheme.
3.1 Technology Choice: Why Current Mode?
Current mode technology allows the im plem entation o f certain signal processing stages
in a very elegant and simple fashion. A good exam ple is the current m irror that allows
addition and subtraction, as w ell as the G ilbert cell [1], which im plem ents m ultiplication.
A nother advantage is the adjustm ent o f dynam ic range by varying the bias current ac­
cordingly. In the case o f a low im pedance im plem entation, a high dynam ic range can be
achieved without increasing the pow er supply voltage. Current mode techniques are also
well known in the RF com m unity and are w ell established in low voltage differential sig­
naling com m unication channels.
Throughout this study, the choice o f im plem entation is continuous tim e current m ode cir­
cuitry. As this project was developing, the current mode im plem entation had the best
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likelihood o f success over other im plem entations. Subthreshold voltage m ode circuits are
very tem pting because o f the low pow er consum ption [2], Chips subm itted by the VLSI
Lab at B oston University that are using subthreshold circuits always had a very delicate
setup and were sensitive to all kinds o f induced stress factors, e.g., pressure on the pack­
age or an extremely high sensitivity to tem perature. As an exam ple, the center frequency
o f a 64-channel passive cochlea chip could be shifted by ju st by pressing the package
harder into the socket.
Switched capacitor applications have great advantages w hen it com es to DC offset cor­
rection and hence has the capability to be designed with small device sizes. This technol­
ogy was not utilized, since the sam pling criterion for im plem enting the auditory nerve
m odel was quite high because time differences o f lu s had to be resolved. Also, an onchip anti-aliasing operation w ould have to be perform ed in order to feed back into the
spiking neuron circuitry. In general, the sw itched capacitor approach had too m any uncer­
tainties to plan the project ahead. In general, a switched capacitor im plem entation m ight
prove to also be a good technology choice, but only a detailed study can deliver the an­
swer to this subject.
Another technology choice w ould be continuous tim e voltage m ode circuits. For the low
cut-off frequencies needed, different im plem entations other than subthreshold w ould
have to be utilized. Also, precision m ultiplication in voltage m ode circuits can be very
pow er and area intensive. In order to keep the differential offset o f the input stage low,
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larger aspect ratios o f the differential pairs or high bias currents for the input branch have
to be u sed to assure low DC offset, that w ould otherwise becom e a part o f the signal and
hence w ould be factored in.
The last technology choice is a pure digital version o f the auditory nerve processing
scheme. In general, this w ould be the best solution regarding reliability. A t the time o f
w riting this thesis, a digital version o f the auditory nerve m odel is on its way. In order to
resolve the phase differences in this transient driven processing scheme, standard archi­
tectures cannot be applied and a custom digital auditory core has to be developed in order
to provide real-tim e processing capabilities.
N evertheless, current m ode is as tricky as any other im plem entation. One can list all the
pros b u t there will be always a lot o f pitfalls that accompany the developm ent o f current
m ode systems. In general, a learning curve w as passed until all aspects o f current mode
processing in conjunction w ith a system im plem entation w as understood. In general, the
research was conducted under quite high expectations and alw ays in a timely manner.
Hence, leaps were m ade instead o f sm all steps. In general, it is not a good idea to do so
when a project reaches a certain com plexity, as in our case w ith approxim ately
analog transistors for signal processing on a single die.
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1 0 0 ,0 0 0
3.1.1 Single-ended versus differential implementations
In the voltage mode dom ain, single-ended im plem entations are very common. A good
exam ple is an operational am plifier w hich naturally features a differential input stage plus
a single-ended output stage. A voltage follower is im plem ented by connecting the output
to the negative input. This scheme can be considered to be single-ended.
In the current mode dom ain, single-ended solutions can be found throughout the literature.
A current m irror could be com pared to a voltage follow er in that respect, that a current in
produces a current out. H ence, a current m irror could be considered as a current follower.
U sing this blunt com parison, one m ajor difference becom es clear. In current m ode do­
main, there is only lim ited gain available and the real estate effort regarding area and
pow er is tremendous, since every current gain step im plem ents itself in a parallel con­
nected current mirror branch. Hence, active feedback as in the voltage follower is not
available.
U tilizing no active feedback has several im plications on the circuit behavior. The m ost
severe one is that the output o f the current m irror is “blind” to its source, or in other
words, no restoring force through feedback is available. This leads to following prob-
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lems: offset, and gain error due to mismatch, such as im pedance or device size differ­
ences.
For the proposed w ork, a full differential im plem entation o f the auditory nerve model is
used. A n im portant advantage o f differential signaling is the higher im m unity to com mon
m ode noise sources such as supply voltage and digital lines along analog differential lines.
O ther advantages are increased dynamic range due to 6 dB increase o f peak-to-peak signal
leveling and the reduction o f 2 nd order harmonics.
A nother m otivation to im plem ent the system as fully differential is that the signal is cen­
tered around a com m on m ode bias rather than referred to a fixed reference point, as it is
in the case for single-ended systems. In the presence o f m ism atch (see Chapter 5), every
change on the signal will be absolute. A normal effect o f m ism atch is the introduction o f
D C components. Since m ism atch is a random event, a prediction on the signal state can­
not be made. Since the auditory processing has stages o f m ultiplication and thresholding,
a single-ended im plem entation can be a bad choice. D ifferential signaling gives the pos­
sibility to control the differential signal branches in a correlated fashion and hence in­
crease the im m unity to mism atch effects.
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3.1.2 Current Mode Technology
In 1968, the current conveyer (CCI) was introduced by Smith and Sedra as the first build­
ing block for current m ode processing [3]. Enhanced versions o f the current conveyer
w ere introduced later [4], V oltage mode circuits becam e dom inant w ith the general intro­
duction o f integrated operational am plifiers during the same time frame that the current
conveyer w as reported. The concept o f operational am plifiers had been know n since
Frederic W illiam s introduced the concept in the early 1940s and old concepts could be
easily applied to the new integrated device. The current mode approach throughout the
years did not develop at the same pace as voltage m ode approach.
In current m ode circuitry, the signal is represented in the current domain, w hereas in
voltage mode, the voltage swing is the signal. W ith em erging low voltage designs, volt­
age m ode circuits are naturally limited in dynam ic range. Since in current mode, the sig­
nal swings around its D C current bias, the reduction o f the pow er supply voltage has, to a
first order, no im pact on the dynamic range as long the circuit consists o f low -im pedance
nodes, resulting in only sm all voltage swings.
Nevertheless, both im plem entations still follow fundam ental circuit behavior: A current
swing always generates a voltage swing, and vice versa. W hen designing current m ode
circuits, the designer still has to take care o f the voltage states inside the circuit. O n the
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other hand, the designer o f voltage m ode circuits has to consider the current bias condi­
tions in the voltage signal driven circuit.
Current m ode circuits in general have advantages in signal processing, since fundam ental
operations like addition, subtraction or m ultiplication (remember: m ultiplication in a G il­
bert-cell is a current m ode operation) can be im plem ented easily, resulting in a less com ­
plex circuit realization than that achieved using voltage mode circuits. C urrent m ode cir­
cuits also becam e the focus in research for high-frequency applications [4].
In the case o f auditory signal processing, the choice for current mode cam e naturally,
since m ost operations are best perform ed in the current domain. A good exam ple is the
very front end, w here a rectification stage has to be implemented. In the discrete opera­
tional am plifier (O pam p) world, one w ould choose a standard diode-O pam p configura­
tion to im plem ent this task. Im plem enting this function in standard CM OS technology
requires a not-so-com m only available N PN option, plus area-consum ing operational am ­
plifiers. A m ore elegant and popular w ay is to use a voltage-to-current converter (e.g.,
transconductance am plifier OTA) and perform this task essentially over a diode con­
nected MOS transistor.
A nother good exam ple driving the decision tow ards current m ode circuits are m ultipliers.
Voltage-mode m ultipliers generally consum e a lot o f pow er in order to increase dynam ic
range. To im plem ent a decent linear CM OS m ultiplier, a large portion o f the chip area
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has to be invested to m aintain a linear transfer function. A nother challenge in designing
voltage m ode m ultipliers is DC offset at the inputs. C urrent m ode CM OS multipliers
based on square law overcom e m any o f these problem s in a very elegant w ay by using
currents that are applied at low im pedance nodes and hence result in low voltage swing
w ithin the circuit. They offer very high dynam ic range at very little pow er consumption.
3.2 Basic Element - Current Mirror
Current m irrors are the m ost com m only used building blocks in analog circuit design. A
diode-connected transistor produces a corresponding gate-source voltage to an applied
current into this structure. Transistors w ith the same device dim ensions connected to this
potential to their gate will replicate the current set by the diode-connected circuit. For low
frequencies, the gate current is negligible and m any transistors can be connected to the
diode-connected transistor for m ultiple copies o f the applied current.
For analog signal processing, the question arises concerning how accurately a current is
copied. For the following analysis, m ism atch aspects are generally omitted. The im pact
o f m ism atch will be broadly discussed in Chapter 5. The focus here is the theoretical
lim itation o f the current m irror circuit under circuit conditions. In order to start the dis­
cussion on current mode signal processing, this simple building block is analyzed in dif­
ferent configurations and aspects.
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The current m irror operates on the principal that if the gate-source voltage V
o f two
M OS transistors are equal, both branch currents should be equal. Figure 3-1 shows the
im plem entation o f the simplest form o f a current mirror. Since this is the very first sche­
m atic drawn, a symbol reference for circuit schematics can be found in Appendix B,
w hich is valid for all circuits show n in this study. V
is set by the current flowing
through the diode-connected transistor, representing the voltage that produces the set
am ount o f current. Any other transistor connected to this potential will produce the same
am ount o f current when operated under the same bias conditions.
Figure 3-1: Simple current mirror.
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M l is in saturation,3 since V.a s \ = F„,
. For V.a s 2 > F„
- V,m 2 ’ M2 is also in saturation. In this
S s1
Ssl
case, the transfer function can be expressed as (equation 3-1):
\2
h u , _ K 2 W2 -L x
K x L 2 -Wx
v
F
- F
th\ y
l + A-V,ds-y
l + A - V ds,
(3-1)
W here for each o f the transistors Mi and M 2 , the param eters are defined as followed:
•
C urrent gains: K x and K 2
•
Physical gate dim ensions: Wx, W2 (w idths) and L x, L 2 (lengths)
•
Gate-source potentials: Vgs>, VgSi
•
Threshold levels: Vllh, Vl/h
•
D rain-source potentials: F^ , VdSi
•
The channel length m odulation param eter expressing the finite output im pedance
o f the transistors, Lam bda: h
Equation 3-1 shows three m echanism s that influences the copying accuracy o f this sim ple
current mode structure:
•
Differences in source-drain voltage
•
D ifferences in physical dim ensions
•
D ifferences in threshold levels
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A problem that can be dealt from the circuit side is that o f channel length m odulation
originating from different source-drain voltages on each side o f the branch o f the current
m irror. A ssum ing identical devices, equation 3-1 reduces to (equation 3-2)
out
(3-2)
VdSt is fixed due to the diode connection o f M l and only depends on the change o f input
am plitude o f I in. The drain voltage o f M2 is basically undefined and strongly depends on
the circuitry this node is connected to. D ifferentiating equation 3-2 yields (equation 3-3)
out
_
(3-3)
in
For X «
1, the equation 3-3 simplifies to a linear relationship. The nature o f changes can
be constant, such as source loading o f another block connected to the current m irror out­
put, but changes e.g., in the pow er supply will also introduce changes to the output cur­
rent. Changes such as pow er supply noise will directly im pact the dynam ic range o f a
simple current m ode structure.
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Current m ode signal processing needs a pre-set bias current to convey the current signal
through the current m irror branches. A good ratio betw een bias current and signal current
is
1 :1 0
for single-ended current m ode structures in order to preserve dynam ic range by
limiting signal distortions (M odulation Index 0.1). Figure 3-2 illustrates the SNR for a
simple current m irror biased at lOuA w ith a lu A maxim um signal current. These bias and
signal settings are som ew hat typical, since it is a tradeoff betw een electrical noise floor,
pow er consum ption and dynamic range. The pow er supply was set to 3.3V.
SNR [dB] due to power supply ripple @ Signal = 1uA / IBias = 10uA
100
m
60
■a
“
50
«
40
0 .0%
1 .0 %
2 .0 %
3.0%
4.0%
5.0%
P o w e r S u p p ly N o ise I R ipple [%]
Figure 3-2: SNR for a single-ended current mirror under power supply ripple.
Referring to Figure 3-2, for a voltage pow er supply ripple o f 1% (corresponding to
33mV) the SNR decreased rapidly to 49dB. In order to achieve a higher im m unity due to
74
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pow er supply variations, fully differential circuit im plem entations have to be chosen. The
pow er supply ripple becom es a com m on m ode artifact.
The finite output im pedance o f a sim ple current m irror has another im pact on the dy­
nam ic range on this structure. Rew riting equation 3-2 as a function o f the voltage differ­
ence betw een the drain-source potentials and neglecting quadratic X term s yields equation
3-4:
=
l + A -fo ,
(3-4)
in
For AVds = 0 , then I in = - I out. In order to analyze the im pact o f any m ism atches to the
harmonic behavior o f the CM structure, the transfer function is first rew ritten in terms o f
input and output loading. D ifferences in
are the cause o f any current m ism atch in a
current m irror and cause a DC offset. In order to control this variable, one m ust achieve
equal loading conditions in order to m aintain sim ilar voltage values. VdSj and VdSi can be
expressed as (equation 3-5):
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V ,.
= V ,. +
•
\
°s,mM\
LR;
y
(3-5)
V
= V
+ I ■
v d s2
r ds T 1 in
V
J
°A/ 2
U sing a small signal approach, w e can rew rite I out as (equation 3-6)
^ out
l + A-7.,
Rl
“
•7,
I* .
(3-6)
'Jj
Very often, current m ode structures are cascaded, connecting the high impedance output
o f a current mirror to the low im pedance input o f another current m irror (diode connected
with identical W/L). For this scenario, RL «
g 0u2 and R irt»
g m^ and we can write
(equation 3-7)
4, =-(i+* 4 ■
■
)■/,.=-4 -4 •*•a*
loading
(3-7)
Exam ining equation 3-7, the im pedance m ism atch yields a 2nd order harmonic distortion
in the output signal. The 2nd order harm onic distortion can be expressed (equation 3-8)
therefore as
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(3-8)
From equation 3-8, we can derive that HD2 is zero w hen the loading is identical. This is
true as long as both MOS transistors M l and M 2 o f Figure 3-1 are biased and operated in
the saturation region, which is always true for M l.
This small signal analysis m ethod is in general only valid around the operating point.
This m ethod becom es very valid for current m ode circuits w ith low im pedance nodes. In
regular operation, the signal current only causes small voltage swings and is keeping the
circuit in the small signal domain. D ue to the sim plicity o f small signal parameters, this
m ethod will be used throughout for further circuit analysis. A s a guideline, a value o f
about 5% o f gm variation o f a transistor is used to define a small signal region.
3.3 Enhanced Elements
This section provides a general overview o f current m ode building blocks. M ost o f these
building blocks are used w ithin the current m ode auditory nerve channel. The perform ­
ance o f these circuits is highlighted in this section as well in Chapter 4, where impacts o f
m ism atch on m ost o f these circuits are analyzed. H igher order functional blocks based on
these elements are introduced in Chapter 5 and again observed under mismatch condi­
tions.
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3.3.1 Differential Current to Voltage converter with low harmonic distortion
In current mode processing, a current to voltage conversion m ight become necessary. A
good exam ple is off-chip com patibility with other chip sets w here a voltage signal rather
than a current representation is needed. Figure 3-3 shows a new pseudo differential cur­
rent to voltage converter. A similar topology w ill be further discussed in Chapter 3.3.4
and in Chapter 5.
p
F igu re 3-3: Schem atic cu rren t-to-voltage con version concept.
M l and M2 are operated in the triode region. A sm all signal analysis for the circuit in
Figure 3-3 leads for the voltage output votil
(equation 3-9):
(3-9)
v.out,
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M l and M 2 act in this arrangem ent (biased in triode region) as voltage controlled resis­
tors. The OTA in the feedback loop clamps the drain voltage o f M l and M2 to the refer­
ence voltage and hence is dynam ically adjusting the transconductance o f M l and M 2 to
changing input currents. A s easy this topology is, no sim ilar structure could be found in
literature discussing it as a potential current to voltage converter. A reason for that m ight
be that the circuit operated in a single-ended version has an extreme
2
nd order harm onic
distortion. Large signal analysis o f the single-ended structure (using a level one transistor
m odel (Shichm an and H odges [5])) and neglecting the channel length m odulation pa­
ram eter due to the input voltage clamping o f the circuit reveals (equation 3-10)
HD2 =
(l + 2-gm IT
--------------------------------------------
i
4v
+ 2 . SmO
* TA • A
/ +
g TA v
+ £ ^2 - * I . ( I SmO
W here I B is the bias current o f the structure, ij
reference voltage applied to the OTA, g m
(3 -io )
+ v>f) | )
is the signal input current, Vref is the
is the transconductance o f the OTA, Vt is the
threshold voltage and n ■Cox and W /L are transistor param eters respectively.
The second harm onic distortion is linearly dependent on the input voltage. U nder typical
circuit conditions, the total harm onic distortion (THD) is approxim ately 4% for input cur-
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rents one tenth o f the bias current. The THD for a single-ended version is too large to be
a useful current to voltage converter. D eploying this circuit in a differential fashion, the
second order harm onic is suppressed. The third harmonic can be sim ply expressed as
(equation 3-11))
(3-11)
U nder the same bias conditions as described for H D 2, the THD is only 0.04% . The circuit
has a THD o f 1% at 50% o f the bias current. These numbers w ere also confirm ed w ith
circuit sim ulations. A detailed derivation o f equations 3-10 and 3-11 can be found in A p­
pendix E .l and E.2.
Overall, the topology shown in Figure 3-3 m ight be a useful circuit to the current m ode
community. Since the circuit operation is conducted in the triode region and large aspect
rations o f W /L are needed, the circuit usage is m ainly limited to applications targeting the
audio frequency range. A dditionally, since the 2nd harmonic for the single-ended case is
fairly large, this pseudo-differential circuit topology is sensitive regarding m ism atch. A
continuous tim e filter introduced in C hapter 3.3.4 using a sim ilar topology as the currentto-voltage converter im plem ents a crossed-over signal path to achieve fully differential
performance.
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3.3.2 Fully Balanced Current Mirror
In short a very useful elem ent is introduced: The fully balanced current m irror (FBCM )
allows differential current mode operation with good common m ode rejection ratio.
O riginating from the current conveyer II [6 ] and following a design idea from [7], the
FBCM can be realized and it is shown in Figure 3-4.
•+
Io
„•+
in
in
F igu re 3-4: S chem atic o f th e fully balanced current m irror.
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R eferring to [7], the change is m inim al but effective. In the original circuit im plem enta­
tion, the source o f Mi and M 4 are biased with current sources m atching the bias current o f
I B. These current sources w ere rem oved and the differential signal path was closed by
replacing these current sources w ith current m irrors follow ing the signal current w ithin
the branches o f M 2 and M 3. B esides reducing the biasing circuit com plexity, the CM RR
is enhanced since the voltage sw ing at the sources o f Mi and M 4 is accordingly reduced.
The m ost common use for this elem ent is to enhance the C M R R w ithin an analog system
and to be an im pedance bridge betw een different system building blocks. Examining
Figure 3-4, the topology is fairly simple. In general, the sizing o f this circuit is quite
straight forward as it can be seen as a true current m irror that does not need special bias
conditions. As an example, for the later use o f this element, I B w as typically set to lOuA
using a simple current m irror structure. D epending on technology and bias conditions,
this elem ent is also suitable for high frequency operations.
In general, this elem ent has a very high CM R R and is through its topology a good candi­
date to be robust against m ism atch and process variations. This behavior originates par­
tially through the use o f the enhanced W ilson current mirror, w hich is through its sym m e­
try a good choice for counterbalancing m ism atch. The differential output current is given
by (equation 3-12). A detailed derivation o f equations 3-12 can be found in Appendix E.5.
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'out.
j
^ ((«,,
hn „)
(3-12)
From equation 3-12 follows, that the differential gain Adiff = 2 . Since the common mode
gain A cm depends on the m atching behavior o f this topology, the analysis is continued in
C hapter 4.4.2 discussing the im pact o f mism atch. M easured chip data is also provided.
3.3.3 Rectifiers
Full and half-w ave rectifiers are very im portant building blocks for analog signal process­
ing. The m ost com m on application for a full-wave rectifier is the usage in automatic gain
control loops, RM S detectors and peak detectors. In conjunction w ith high perform ance
Opamps and diodes, very precise rectifiers can be realized.
There are m any solutions for rectification in analog signal processing. One very popular
voltage m ode im plem entation is to use Opamps in conjunction w ith diodes. Since this
im plem entation is realizing voltage rectification, it is not a suitable building block for the
overall current mode processing scheme. Theoretical, this rectifier topology could be im ­
plem ented before the voltage to current conversion. B ut this im plem entation needs a
good Opamp with m oderate slew rate and low input voltage offset that manifests itself in
large devices and hence is not acceptable regarding layout area.
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Several [ 8 ], [9] ,[10], [11], [12], [13], [14], [15]
current m ode im plem entations have
been proposed. [14] and [15] are discussed in m ore detail. The im plem entation o f [14] is
show n in Figure 3-5 showing only the half-w ave rectification portion.
- M
|
M
Figure 3-5: Precision half-wave rectifier.
[14] is using a m odified W idlar current m irror as an analog switch in a positive feedback
configuration (Figure 3-5). Ib is a small bias current in the nA range in order to pre-bias
M4. I B sets the lowest rectification current as w ell as the tim e constant o f this circuit.
W hen I in is sinking current into M i, the current set w ith I B can flow through M 2 and
hence is limiting the current flow through M 3 . W hen l in is sourcing current out o f this
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circuit, M 2 is sw itched o ff and I B is charging up the gate o f M 4 allowing current flow
through M3 . This im plem entation is very good w ith respect to accuracy and speed. N ev­
ertheless, this im plem entation is not suitable for this current m ode processing schem e in
this study. Except [15], all current m ode rectification schemes operate in non-currentbiased environm ent w hich makes it difficult to interface these circuits w ith other biased
current m ode blocks on chip. The input im pedance for [14] is rem arkably low. Though,
to send the current signal from one building block to this rectification block, certain crite­
ria have to be met. First o f all, the input node should be a high im pedance node, w hich is
generally the case for current m ode output nodes.
A popular current m ode building block is the current conveyor. Like this building block,
m ost current m ode circuits operate in a biased environm ent. The signal is sitting on top o f
a dc bias current in order to set DC operating points norm ally in the saturation region o f
the transistor. The problem w hich one has to face using this circuit [14] is that the struc­
ture is unbiased. Interfacing such circuits result in DC offsets and distortion. The D C off­
sets overlay w ith the signal and no rectification is achieved. The output o f the rectifier
w ould be a signal again riding on a DC signal o f unknow n state. M athem atically, one
might consider subtracting the DC current bias out. B ut such an operation w ould force
one o f the transistors o f the active biased circuit into a different m ode o f operation w hich
would introduce DC offsets and distortion.
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In general, the problem breaks dow n to if there is no current, the source drain voltage o f a
transistor is zero (neglecting any storage effects) or in a general scheme, zero current cor­
responds to absolute 0 volts. B ipolar biased circuits have advantages rectifying currents,
since the devices are biased betw een negative voltage and positive voltage and allowing
OV to be a voltage state w ith leaving all other devices still in their operating region. In
general, bipolar pow er supply schemes should be avoided when possible since it put con­
straints on the infrastructure around this circuit block. U nipolar pow er supply schemes
are preferred.
[15] is addressing the bias point issues since the target here is an overall system design
and stages have to be interconnected. A sim ilar structure using a fixed bias class AB cur­
rent conveyer w as subm itted on the first A N B chips in 2003. In [15], rectification is again
realized as a m odification to a class AB current conveyer but w ith a sm art design choice
to control the AB current conveyer w ith an active feedback circuitry. T he rectification
has to be aligned w ith an OTA that controls the dead band zone o f this structure. For
voltages below the dead band threshold, no current is rectified. The proposed im plem en­
tation achieves a very good alignm ent o f the dead band voltage w ith acceptable draw ­
backs regarding therm al noise issues. D ue to the input stage, this circuit has lim ited
bandwidth. Since the application is targeting an audio frequency range, this draw back
does not affect the system proposed in this thesis.
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The design idea o f [15] was used for the auditory nerve scheme since experience existed
w ith a sim ilar design. Figure 3-6 show s a pseudo-differential im plem entation o f a half­
w ave current m ode rectifier and Figure 3-7 shows the corresponding full w ave rectifica­
tion
•+
Figure 3-6: Pseudo-differential half-wave rectifier.
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• +
in
•+
Figure 3-7: Pseudo-differential full-wave rectifier.
Inspecting the structure in Figure 3-6 and Figure 3-7 shows im m ediately a positive feed­
back loop between the left and right hand side o f the circuit. As long the current gain is
sm aller than one, both configurations are stable. This positive feedback configuration as­
sures correlation between the uncorrelated processing branches. In these pseudodifferential configurations, the rectified portion o f a differential signal is processed b e­
tw een an nmos branch as well as a pm os branch. Since there is little correlation between
these branches under process conditions, the cross coupled configuration evens out the
differences in-between.
88
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A n O TA w ith a level shifter is used according to [15] in order to reduce the dead zone
betw een the input switches o f the nm os and pmos. The realization o f this circuit is shown
in Figure 3-8.
OUt2
Figure 3-8: O T A with level shifter.
The transient rectification behavior under m ism atch conditions is provided in Chapter
5.3.1.
3.3.4 Continuous Time Filters
In order to realize the auditory model in analog current m ode circuits, 1st order low -pass
filters with very low cut-off frequencies are needed. The range o f cut-off frequencies
span from 10 Hz to 1 kHz. Chip area is always a lim iting factor. In the overall chip archi-
89
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tecture, up to 64 channels have to be im plem ented. Each channel is com posed o f six first
order integrators. H ence, a 64-channel version w ould have 384 integrators on chip. The
am ount o f low-pass filters puts a constraint on the available capacitance per integrator. In
general, a lOpF w orked out to be a good com prom ise betw een chip area and circuit per­
form ance. Figure 3-9 shows the chip layout o f the subm itted chip realizing current m ode
low -pass filters. LPF1 and LPF2 are two concatenated 1st order low pass filter resulting in
a 2nd order low pass filter response. These structures w ill be discussed in this section. V2I
is a highly linear voltage to current converter. FBCM1 is a fully balanced current m irror
w ith a clam ped voltage input circuit for com m on m ode suppression; FBCM 2 is a basic
fully balanced current m irror as described in Chapter 3.3.2. BIAS is the centralized bias
circuitry for the full chip design. The 2nd order low pass filter is replicated on the other
h a lf o f the chip.
90
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Mirrored design
LPF1
FBCM1
BIAS
FBCM2
V2I
LPF1
Figure 3-9: Chip layout for the current mode low-pass filter.
The chip contains four first order low -pass filters. A dditionally, there are a voltage-tocurrent converter plus fully balanced current m irrors for input and output to the low-pass
filter where integrated. The overall chip size is 4.8 m m 2. A single 1st order low-pass filter
takes about 0.37 m m 2 chip area in a 1.50um technology.
3.3.4.1 Analysis of the Topology
The low pass filter concept goes back to [16]. B ased on the architecture o f this design,
general im provem ents to the filter structure w ere conducted. The design goal was to im­
prove tuning range, dynamic range and pow er consumption. From an operating stand­
point, the biggest difference between the two filters is the m ode o f operation. The original
91
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design operated the active devices for the filter operation in saturation, w hereas this de­
sign operates purely in the triode region. This mode o f operation allow s using the internal
reference voltage Vref as a tuning param eter for the cut-off frequency by controlling the
transconductance o f the active devices. In the original design, the cut-off frequency is
controlled by Vgm o f the internal transconductance o f the operational transconductance
am plifier (OTA). The second tuning param eter Vref allows in com bination w ith V
a
filter operation dow n to 1 Hz. H ence, a tuning range o f 1 H z to 1 kH z can be achieved,
which is w ithin the requirem ents o f the auditory nerve models.
In general, the filter can be operated in a 1.5um technology down to 3.3 V. For pow er, the
original filter used bias currents around lOOuA. The filter was im proved for low er pow er
consumption. The filter can be biased using a typical bias current o f 5uA w ith an antici­
pated signal current o f m axim um luA . Typically, a bias current is lOuA is used to allow
some perform ance overhead. U nder the lOuA bias condition, the filter always has a total
harmonic distortion «
1% for full input bias swing. The input stage allow s a 1Vpp opera­
tion and is com patible w ith standard sound card output voltage standards.
In short, the overall filter operation is briefly introduced. A detailed description o f the
overall concept can be found in [17]. Figure 3-10 shows h alf o f the differential integrator.
This structure is sim ilar to current m ode gm-C filters, w here the OTA in Figure 3-10 is
replaced with a diode connection to M l and the unity gain frequency is hence
92
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o)U = g^ mmM \ 1Cin-,,
w here n
i
1
is the transconductance o f transistor M l and C-,
is the ca*n i
pacitance connected to the gate o f M l. B y replacing this diode connection w ith an OTA,
the unity gain frequency becom es a function o f the gm o f the O TA and is hence tunable.
I.
3
Figure 3-10: Current mode low-pass filter.
The schematic in Figure 3-10 is by itself a current m ode low -pass filter. Figure 3-11
shows the small signal m odel o f this building block. The small signal model also includes
the gate-drain capacitance explicitly, since Cgd^ set a zero and hence can determ ine the
dynamic range o f the integrator.
93
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c
c
S d M \
I
,
lh
v„
v,_
£
M\
vS
£
v
^ >mOTA m
W <X>
T
SdM2
T
VO
M
f
S'
c i-
tT
c s»
V
T
ISdS;
I
Figure 3-11: Small-signal model o f the single-ended current mode low-pass filter.
Equation 3-13 shows the small signal transfer function o f the basic building block, w here
C,„,
= C lnt
-, + CSSM\ + Cgs U2 + Cg a.U \ + C S a.M 2 is the total capacitance
connected to node vS„ . A
lot
r
detailed derivation o f equations 3-13 can be found in A ppendix E.3.
-1
*(o=-
(3-13)
’ S ds,.
1+ s
1 + 5-
gm ■gn
c.
gn XOTA J
The transfer function has a pole at o \ = g m gm0TA anc| a zero at
gds,,
_
Depending
c.
on the mode o f operation, coi is in the 1 kH z to 10 kH z range, w hereas co0 is far below 1
94
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kHz. N evertheless, the zero limits the overall frequency response o f this low-pass filter.
Figure 3-12 shows this frequency behavior.
Frequency Response CM LPF vs. vref—O.6.. 1.5, gmota=10nA/V
s•o
s
(*
O
F req u e n cy [Hz]
Figure 3-12: Transfer curve o f the single-ended current mode low-pass filter.
The good news is, when deploying the building block from Figure 3-10 into a differential
current mode integrator scheme, the zeros cancel out, allow ing a dynamic range not
bounded to any zeros. Figure 3-13 show the full topology [17].
95
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K
+
i,i n
9K
hin
Figure 3-13: Schematic o f the continuous current mode time integrator.
A detailed analysis o f the small signal model o f the full differential current m ode integra­
tor (see Appendix E.4) o f Figure 3-13 reveals follow ing transfer function (equation 3-14
and 3-15)
1
+^co,
*(,)=■
1
coo V
+^CO,
w here
96
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(3-14)
§ m
§ m nTA
C0Q= --------- 1------- —---- r
2 -S ds\ 2 -cgd+cin«)
§ m
& mnT,
cox = --------------------—---------
3 -cgd-gm+ cint-g ds
^
_________________________
( C^
(2
+ C i n . ) - ( 3 - C^
Cgd~^~C in t )
Sm
& m OTA_________________________
+ C i n t ) - ^ + 2 - C^ - ( 2 - V
+ C int)‘^m
(3-15)
Cint is again the total node capacitance attached to the integration node. g m is the trans­
conductance o f transistors M l to M 6 and assum ed to be equal. g ds is output conductance
o f transistors M l to M 6 and also assum ed to be equal, g
is the transconductance o f
the OTA.
coo is the unity gain frequency o f the integrator portion. g>i and CO2 are small non-ideal as­
pects o f this current m ode integrator, coj and o>2 are forming a pole and a zero are very
close to each other. H ence, they nearly com pensate each other. Figure 3-14 visualizes this
behavior in com parison with an ideal integrator where a small shift in the frequency re­
sponse is visible. Figure 3-15 shows the frequency response for different frequency
sweeps.
97
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Differential Current Mode Integrator real/ideal vref=lV, gmota=10nA/V
as
■o
s
-20
-40
-60
Frequency [Hz]
Figure 3-14: Integrator frequency response in comparison with an ideal integrator.
CO) and CO2 exist because o f the gate-drain capacitance. Setting cgd in equation 3-15 to
zero, the transfer function in 3-14 reduces to an ideal behavior (see A ppendix E.4).
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Differential Current Mode Integrator vref=0.6..1,5V, gmota=10nA/V
40
*D
e
CS
O
-20
-40
-60
Frequency [Hz]
Figure 3-15: Integrator frequency response versus frequency for different vref.
As a final remark, this version o f a continuous low -pass operated in the triode region fil­
ter also features the ability o f an inherited current-to-voltage conversion. As described in
Chapter 3.3.1, the single-ended signal cannot be used due to the strong second order har­
monic. D eploying the topology in a differential m anner allows a current-to-voltage con­
version with low harm onic distortion (equation 3-11). A dditionally, the operation in the
triode region, obtained by clam ping the source-drain voltage to a set voltage also im ­
proves greatly the tem perature stability o f the filter. Assum ing that the bias currents are
temperature com pensated, the transconductance o f the input stage is fixed. A ny change in
99
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tem perature w ill only result in a shift o f the gate voltage, w hich does not impact the filter
operation.
3.3.4.2 Chip Data
T he following section provides some perform ance data from the subm itted chips. A m ore
in-depth data discussion is provided in C hapter 5 w here the chip results are analyzed w ith
respect to mism atch conditions.
Figure 3-16 show the gain transfer curve for all 2nd order low -pass filters from a set o f
five chips. The test setup w as com posed o f a voltage differential input and an external
current-to-voltage converter, using O pam p circuitry. The current output is backcalculated know ing the resistive values chosen for the current-to-voltage converter. Due
to the m easurem ent setup and the general high electrom agnetic noise floor in the lab, in­
p ut amplitudes below lm V deliver m arginal results. Though, the gain-transfer curve
highlights the anticipated dynam ic range o f 60dB. In general, the filter topology is not
lim ited towards an upper bound. H igher bias currents can open up the dynamic range.
100
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Gain Transfer Curve @ f < fc
100E-6
1E-3
10E-3
100E-3
1E+0
lUC-O
1E-6
<
3
O
100E-9
is
c
o
10E-9
1E-9
mnF-19
Differential Vin [V]
|
Figure 3-16: M easured gain transfer curve.
Figure 3-17 shows the cut-off frequency vs. v ref. Sw eeping v ref, a bandw idth range from
approxim ately 160 Hz to 1100 Hz can be obtained. Figure 3-18 shows the cut-off fre­
quency versus vgm o f the OTA? w here v gm is the bias voltage that controls the transcon­
ductance o f the OTA. The bandwidth can be adjusted from 80 H z to 1100 Hz.
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Cut-Off Frequency vs vref, vgm=3.9V
1200
£
1000
>>
£
a>
3
O’
<D
U.
O
3
O
800
600
400
■
200
0.6
0.7
0.9
0.8
1.1
1.0
vref [V]
Figure 3-17: M easurement o f the cut-off frequency versus vref.
Cut-Off Frequency vs vgm, vref=1V
1200
£
1000
800
600
L i-
400
200
3.80
3.85
3.90
3.95
4.00
4.05
4.10
vgm [V]
Figure 3-18: M easurement o f the cut-off frequency versus vgm.
102
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A djusting v ref =0.6V and v gm=4.22V (extrem e limit) and hence com bining both control
voltages, a 3dB point at 1 H z can be reached. Figure 3-19 shows the transient o f the filter
at this particular frequency.
Low Pass Filter Operation -3db @ 1Hz
vref=0.6V, vgm=4.22V
150E-3
100E-3
50E-3
JS 000E+0
-50E-3
-100E-3
-150E-3
0
1
3
2
4
5
Time [s]
Figure 3-19: Output signal at cut-off frequency o f 1Hz.
3.3.5 Multipliers
Analog m ultipliers are important elem ents for analog signal processing systems. M ulti­
pliers find usage in linear am plitude m odulators, AGC am plifiers, variable quadrature
oscillators and variable gain amplifiers. The squaring feature o f a m ultiplier gives also
access to frequency doubling and full wave rectification. In general, m ultipliers are typi-
103
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cally better described as current m ode rather than voltage mode. In voltage m ode circuits,
a voltage is converter to a current. Biased in saturation, the current is proportional to the
square law. Squaring techniques allow the manipulation o f the input signals in such a
w ay that a m ultiplication results in the current domain. The signal is converted back to a
voltage signal. In current mode m ultipliers, the signal processing path stays in the current
domain. The input signal is current, the m anipulation is perform ed in the current domain,
and the output is again a current. W hat m ost M OS m ultipliers have in com m on is that
they exploit the square law dependency o f the drain current on the gate voltage. The only
exceptions are circuits using the translinear principle [4]. Here transistors biased in sub­
threshold achieve an exponential dependence and this is o f course true for the original
im plem entation, using BJTs. The translinear principle is based on the linear dependence
o f the transconductance to the collector current. The translinear m ultiplier is also know n
as log-antilog m ultiplier.
3.3.5.1
Current Mode Multiplier Design
A b rief introduction o f a full differential current mode m ultiplier is provided. A m ore indepth discussion o f this topology under m ism atch conditions is provided in Chapter 5.
Based on this design, a test chip was subm itted. Figure 3-20 shows a top-level layout pic­
ture o f the subm itted chip w ith two fully differential current m ode m ultipliers. V 2I is a
highly linear voltage to current converter. FBCM is a fully balanced current m irror, de-
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scribed in Chapter 3.3.2. FBCM x4 is the same structure as the FB C M but w ith four dif­
ferential output pairs feeding into the m ultiplier core (M ULT). SUB is a current mode
subtracting circuit. The m ultiplier core only takes approxim ately 1.5% o f the chip area.
M ost o f the chip area goes to voltage to current converters, differential current multipliers
for input pair generation and differential current output drivers.
FBCMx4
FBCM
FBCMx4
MULT
Mirrored d esig n
Figure 3-20: Layout o f the fully differential current m ode multiplier.
The full differential current m ode m ultiplier (DCM M ) is based on [18], which is a single­
ended im plem entation. The proposed m ultiplier uses the squaring technique introduced
by [19]. By rearranging the input pairs into the squaring circuitry, a full differential op­
eration with true differential output is achieved. Again, for testing a highly linear V2I
converter was put on chip. The different input pairs are generated using the FBCM ele-
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m ent introduced in C hapter 3.3.2. The output o f the m ultiplier is again buffered w ith a
FBCM element. The overall perform ance o f the m ultiplier is very good. Excluding inter­
face elem ents towards the squarer core, the overall current consum ption is nine times the
bias current.
A s an exam ple, a reasonable bias current is lOuA, although can be lower. A t this bias
level, a m axim um differential input current o f 20uA can be processed without exceeding
a THD o f 1%. A t noise levels far below 200pA/VHz (long channel nm os device), this cir­
cuit has an outstanding perform ance overhead. N evertheless, the dynam ic range w ill be
lim ited by circuit mism atch effects. The large dynamic range w ill assure at least a 60dB
dynam ic range operation under the w orst case production environm ent without any tun­
ing.
The fully differential current m ode m ultiplier is an enhanced version o f [18], [19]. The
full differential im plem entation assures com patibility w ith other differential circuits and
is the main contribution. The backbone o f this current m ode processing scheme is the
current mode squaring circuit, proposed by Liu et al [19].
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i
O
F
-
H
h
i
n
Figure 3-21: Squaring Circuit by Liu et al.
A nalyzing the circuit perform ance, the output current through the squaring branch can be
expressed by equation 3-16
I
Ibias ^
—
(3-16)
1 6 m- I bias
W here m is a scaling factor betw een the bias generator w ith bias current I blas and the
squaring circuitry. I,„ is the total current into the squaring node. The bias current allows
the scaling o f the output current. B ased on this squaring technique, [ 18] proposed a cur­
rent m ode m ultiplier based on [19], Figure 3-22 shows the topology o f the current m ode
multiplier.
107
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Current Mode Subtractor
m:
X
/y
Figure 3-22: Current mode m ultiplier [18].
A nalyzing the circuit behavior, the output current can be expressed by equation 3-17:
m I -I..
(3-17)
As in the squaring circuit, m can be used to scale the output current. In general, this cur­
rent m ode m ultiplier was the role m odel used to construct a fully differential im plem enta­
tion. In order to achieve a differential current m ode scheme, the input pairs have to be
arranged around the square law in such a w ay that differential m ultiplication is achieved.
In order to achieve full differential m ultiplication, the m ultiplier core needs eight current
108
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input pairs, form ed out o f the two differential current mode input pairs. Equations 3-18
show the needed configuration and refers back to the basic equation o f the current m ode
squarer [equation 3-16], ix and ix is the differential input pair o f one node o f the m ulti­
plier. iy and iy is the other m ultiplier input pair respectively, m is the scaling factor o f
the bias branch and hws is the bias current.
i
K
16
1
m -h ia s
l c„
m -h ia s
[m ' i k
1
m 'h ia s
im ' ( k + 0 - 4 -7* . ) 2
16
m -h ia s
16
- f j - 4 ' 7* - ) 1
M 'h ia s
1
+ iy , ) ~ A ' I b,a s}
dn
16
16
1 im i \
im \ k
16
1
i (™4 - O -4-7^ ) 2
+ 0 - 4-7**,)2
k
m 'h ia s
16
m -h ia s
1
(m i k - i y ) - * ' 1* . }
16
m ' h ia s
(3-18)
Equation 3-19 shows the required addition and subtraction o f the squared currents from
equation 3-18 in order to achieve differential m ultiplication.
(L ,,,
-
L,„
) = t/,„ +
)-
(h„ + \
J+
+k h (k
+
k
)
109
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(3 - 19 >
Equations 3-18 and equation 3-19 result in equation 3-20, expressing a full differential
im plem entation w ith differential output current. The differential output current is a very
im portant feature o f this implem entation. This differential output assures very good com­
patibility w ith other differential circuit blocks without the need o f a single-ended to dif­
ferential conversion.
(3-20)
^ bias
As in [18], the squaring operation, the input transistors have to be kept in the saturation
region. The saturation condition is defined by Vgs > Vt and Vds > Vgs - Vt . It can be shown
that the input range for the m ultiplier is (equation 3-21):
(3-21)
Figure 3-23 shows the differential im plem entation o f a current m ode m ultiplier based on
current mode square law using pm os devices:
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/
L
+ / y„
+ /..
L
+ /..
OW
?p
C urrent-M ode Subtractor
outn
Figure 3-23: New fully differential current mode multiplier.
The eight input pair generation w as realized using a FBCM elem ent from Chapter 3.3.2.
The differential output branch w as replicated four times for each input node o f the m ulti­
plier. D epending on the input pair “polarity,” the outputs o f the FBCM s were directly
connected together and fed into the current m ode m ultiplier. The output o f the current
m ode m ultiplier was again buffered w ith an FBCM element.
Ill
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3.3.5.2 Chip Results / Transient Response
The fully differential current m ode design was subm itted and fabricated. The test chip
w as com posed o f a highly linear V 2I converter, tw o 4x FBCM elements for the input pair
generation, the differential current m ode m ultiplier cell and a FBCM element for output
current buffering. The test chip w orked very well and m atched all design bias conditions.
Figure 3-24 shows the transient behavior o f the current m ode m ultiplier test chip as an
am plitude m odulator at m axim um input levels. A 100 H z input waveform is m odulated
w ith a 1 kH z carrier frequency. For easier visualization, the w aveform s are shifted and
hence, only relative am plitude is im portant. Also, the output current was externally con­
verter to a voltage via an O pam p-based current to voltage converter.
112
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Transient Response: Amplitude Modulation DiffMult
------------X*Y
—
10E+0
2 .0E -3
4 .0 E -3
6 .0 E -3
8 .0 E -3
X
10.0E -3
Time [s]
Figure 3-24: Transient test data - Amplitude modulation.
Figure 3-25 shows the four quadrant m ultiplication o f the m ultiplier versus the maxim um
targeted input voltage range o f lVdifr- In this input range, the m ultiplier showed very
good linear behavior w ith a m axim um error o f 0.07%. The transconductance o f the V2I
converter was set to 5uA/V.
113
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C hip Data: Four Q uadrant Multiplication Differential Multiplier
— 5E-&
------------ ------------ ------------ —-5E-6-J------------------------------------- ------------1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
VINX [V]
Figure 3-25: XY Graph - Four quadrant operation.
The perform ance o f the current m ultiplier m atched the expectation o f the design. Further
test data can be found in Chapter 4.4.3 where the im pact o f m ism atch on the design is
highlighted.
3.4 Summary
This chapter provided some insight to current m ode signal processing. The m ost im por­
tant building blocks for auditory signal processing w ere introduced, nam ely a first/second
order low-pass filter and a multiplier. Both topologies w here submitted and chip per­
formance was briefly presented. The differential m ultiplier is a novel design based on
previous w ork by [18] and [19]. Also, a novel fully balanced current m irror was intro-
114
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duced. A dditionally, a linear pseudo differential current-to-voltage converter for audio
frequency range w as introduced.
3.5
References:
[1]
B. G ilbert, "A precise four-quadrant m ultiplier w ith subnanosecond response,"
IE E E Jo u rn a l o f Solid-State Circuits, vol. 3, pp. 365 - 373, 1968.
[2]
R. Sarpeshkar, C. Salthouse, J. Sit, M. W. Baker, S. M. Zhak, T. K.-T. Lu, L.
Turicchia, and S. Balster, "An ultra-low -pow er program m able analog bionic ear
processor," IE E E Transactions on biom edical engineering, vol. 52, pp. 711 - 727,
2005.
[3]
K. Sm ith and A. Sedra, "The current-conveyor - a new circuit building block,"
IE E E Proceedings, vol. 56, pp. 1368 - 1369, 1968.
[4]
C. Toum azou, F. J. Lidgey, and D. G. e. Haigh, Analogue IC design: the current
mode approach. London: Peter Peregrinus Ltd, 1990.
[5]
H. Shichm an and D. A. Hodges, "M odeling and sim ulation o f insulated gate field
effect transistor switching circuits," IE E E Journal o f Solid-State Circuits, vol. SC3, pp. 2 8 0 - 2 8 9 , 1990.
[6 ]
A. Sedra and K. Smith, "A second-generation current conveyer and its applica­
tions," IE E E Transactions on circuit theory, vol. CT-17, pp. 132 - 134, 1970.
115
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[7]
R. H. Zele, D. J. Allstot, and T. S. Fiez, "Fully balanced CM OS current-m ode cir­
cuits," IE E E Journal o f Solid-State Circuits, vol. 28, pp. 569 - 575, 1993.
[8 ]
C. Toum azou and F. J. Lidgey, "W ide-band precision rectification," IEEE P ro­
ceedings G, vol. 134, pp. 7 - 15, 1987.
[9]
F. J. Lidgey, K. Hayathleh, and C. Toum azou, "New current m ode precision recti­
fiers," IE E E International sym posium on circuits a n d system s, pp. 1322 - 1325,
1993.
[10]
C. Toum azou, F. J. Lidgey, and S. Chattong, "High frequency current conveyor
precision full-wave rectifier," Electronics Letters, vol. 30, pp. 745 - 746, 1994.
[11]
K. H ayathleh, S. Porta, and F. J. Lidgey, "Tem perature independent current con­
veyor precision rectifier," E lectronics Letters, vol. 30, pp. 2091 - 2093, 1994.
[12]
S. I. Liu and C. C. Chang, "Current-m ode full-wave rectifier and vector sum m a­
tion circuit," Electronics Letters, vol. 36, pp. 1599 - 1600, 2000.
[13]
Z. W ang, "Novel pseudo R M S current converter for sinusoidal signals using a
CM OS precision current rectifier," IE E E Transactions on instrum entation and
m easurement, vol. 39, pp. 670 - 671, 1990.
[14]
S. K hucharoensin and V. K asem suw an, "High perform ance CM OS current-m ode
precision full-wave rectifier (PFW R)," Proceedings o f the 2003 International
Sym posium on Circuits and Systems, 2003. ISC A S '03., vol. 1, pp. 1-41 - 1-44 v o l.l,
2003.
116
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[15]
S. M. Zhak, M. W. B aker, and R. Sarpeshkar, "A low-power wide dynamic rannge envelope detector," IE E E Journal o f Solid-State Circuits, vol. 38, pp. 1750 1753, 2003.
[16]
Z. Yang, T. Hinck, H. I. Cohen, and A. E. Hubbard, "Current-m ode integrator for
voltage-controllable low frequency continuous-tim e filters," Electronics Letters,
vol. 39, pp. 883 - 884, 2003.
[17]
Z. Yang, "Low -frequency analog integrated circuit design using current-m ode
techniques," in E lectrical E ngineering (unpublished doctoral dissertation). B os­
ton: Boston University, 2004, pp. 235.
[18]
K. Tanno, O. Ishizuka, and Z. Tang, "Four-quadrant CM OS current-m ode m ulti­
plier independent o f device param eters," IE E E Transactions on Circuits a n d Sys­
tems II: Analog a n d D igital Signal Processing [see also IE E E Transactions on
Circuits and System s II: Express B riefs], vol. 47, pp. 473 - 477, 2000.
[19]
B.-D. Liu, C.-Y. H uang, and H .-Y . W u, "M odular current-m ode defuzzification
circuit for fuzzy logic controllers," Electronics Letters, vol. 30, pp. 1287 - 1288,
1994.
117
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4 Mismatch Behavior of Current Mode Circuits
M ism atch is the process that causes tim e-independent random variations in physical
quantities o f identically designed devices [1]. On the other hand, m atching is the statisti­
cal study o f the differences betw een identically designed com ponents placed at a small
distance in an identical environm ent and used w ith the same bias conditions. M ism atch in
this study is o f key im portance. The auditory m odel consists o f a m assively parallel archi­
tecture (parallel channels). In the case o f sound source localization, signals betw een chan­
nels are compared. A ny deviation betw een channels has im pact on the accuracy o f the
system. Because o f the parallel nature o f the system, external tuning means global tuning
o f the system. The ability to tune individual circuits is lost. Therefore, the system has to
rely on quality com ponents, w hich do not need individual tuning and stay w ithin a nar­
row tolerance w indow across the channels in order to assure system performance.
4.1 Introduction - Design Goal, Design Constraints
The overall goal o f this study is to construct an auditory nerve chip suitable for sound
source localization. This analog schem e is like any analog circuitry, sensitive to m is­
match. In order to cope w ith m ism atch in signal processing current mode circuitry, high
bias currents or large device sizes have to be chosen.
118
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In order to im plem ent an auditory nerve chip, following top level design constraints have
to be met:
-
64 channels (16x4) w ith three spike populations on a single die
Pow er < 1W
These top-level constraints m ight not look challenging. I f w e revisit the auditory nerve
channel outline again, it will becom e clear that these design constraints are not easy to
meet. One auditory nerve consists o f eight integrators. W ith 64 channels, there w ill be a
total o f 512 integrators on chip. The tuning range o f these integrators is from 4 H z to 1
kHz. Tw o o f these integrators operate below 100 Hz. N o external capacitors can be used.
Also, 128 analog m ultipliers have to be fit on the sam e die. Regarding power, assum ing a
conservative pow er supply scheme o f 5V, the current consum ption per channel has to be
sm aller than 3.1mA. The limited pow er budget suggests that the bias current w ithin the
circuitry has to be constrained, w hich has im plications fo r the useable signal swing.
In any case, in order to develop a system that can com prise 64 auditory nerve channels on
one chip, one has to find a com prom ise betw een device area and bias currents. The
choice o f area and pow er is in the first case less driven by perform ance than by the m is­
match within such a m assive parallel analog circuitry. M ism atch is introducing different
kinds o f effects into analog circuitry. D epending on the circuit topology, mism atch has
impact on common m ode rejection, total harm onic distortion and DC offsets.
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DC offsets are o f special concern and are discussed in detail in Chapter 6 . The two analog
m ultipliers in each channel will am plify any DC offset induced by m ism atch behavior. A
general m ethod to rem ove DC offsets would be, e.g., high pass filters. Since the auditory
nerve has to cope w ith acoustic frequencies below 100 Hz, the im plem entation on the
chip w ould, again, not be trivial due to the area constraint. Even if it were possible to fit
these filters on the chip, it w ould m in the overall signal processing scheme. DC states
w ithin the auditory nerve are crucial signal inform ation that allow s the processing scheme
to adapt to environm ental changes. Hence, DC offset cancellation is not a possibility for
this processing scheme.
The following sections will provide an overview on the cause and im pact o f m ism atch on
current m ode circuits. Chapter 4 m ainly discusses m ism atch on a circuit block level.
Chapter 5 extends these observations on a system level.
4.2 Causes of Mismatch
M ism atch originates out o f the statistical nature o f each processing step used in IC fabri­
cation and varies according to process param eters such as doping concentration and car­
rier mobility, and also dimensional param eters such as oxide thickness and oxide gate
length and width. Those param eter fluctuations have direct im pact on device param eters
such as threshold voltage and current gain.
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M ism atch affects all com ponents on integrated circuits, such as resistors, capacitors, bi­
polar and M OS transistors. In the case o f m atching transistors, relative mism atch betw een
the com ponents is m ainly o f interest, w hereas in the case o f resistors and capacitors, the
absolute m ism atch is very often a key issue. Exam ples for absolute m atching w ould be
resistors for bias generation or capacitor value for filtering applications.
M ism atch betw een “identical elem ents” can be divided into tw o categories: stochastic
and system atic effects. Stochastic effects originate from the IC processing steps used,
such as roughness in polysilicon (e.g., gate electrode or resistor), random interface
charges (im purities or crystal defects) or uneven doping concentrations. These stochastic
effects are dom inating at small distances betw een the devices. Systematic effects can
originate from m ore global induced effects like m echanical stress (passivation, bonding,
and packaging) or tem perature gradients across the chip (e.g., due to pow er stage on chip).
O ther system atic effects can originate m ore on the device level, such as orientation be­
tw een devices or parasitic components such as line resistance or parasitic capacitors.
System atic effects can be mainly identified as DC offsets effects and can be often (if
identified) corrected by design changes. Stochastic effects represent the “quality” o f the
fabrication itself. Process parameters underlie a very strong process control (that brought
the IC fabrication to the level it is today). N evertheless, they have to follow physical
principles. The process w indow chosen for each param eter will vary w ithin its boundaries
121
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independently and can be seen as the “true” m ism atch o f IC fabrication. The IC fabrica­
tion equipm ent that is used will also introduce gradients across the w afer and can be a
source o f m ism atch, w hich can be im portant for large devices or large distances.
4.3
Mismatch
This section provides a b rief overview o f the m ism atch assum ptions m ade w hich are used
throughout this study. Also, some basic definitions regarding correlation are provided.
4.3.1 Defining Matching Constraints
In the m id 80, the concern o f m ismatch im pacting the circuit perform ance arose [2], [3].
M. Pelgrom et al. [1] introduced the idea o f interpreting the sm all random mism atch
variation as a source o f spatial frequencies and introduced a tw o-dim ensional “param eter
noise function” . This function is determ ined by statistical processes w ithin the fabrication
process and a geom etry dependent m ism atch transfer function, w hich is given by the lay­
out topology o f the devices [6 ], M. Pelgrom et al. stated a first order linear relationship
betw een m ism atch and device distance (equation 4-1).
^
&
= J L + s 2p - D 2
W- L
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(4-1)
The param eter Ap in equation 4-1 is a first order area-m ismatch param eter, expressing the
distribution o f local variations or in a spectral sense, the level o f w hite noise. Sp is a first
order distance-m ism atch param eter, expressing the distribution w idening w ith increasing
distance between the devices due to param eter gradients across the wafer. W and L are the
length o f the device, respectively. D is the distance betw een the m atched devices. A m ore
detailed insight into the im pact o f Sp can be found in [4]. A dditionally, [5] provides some
insight to bias current distributions across a die. Interestingly, periodic patterns can be
observed that likely have their origin in the m achining tools used in the fabrication.
In Figure 4-1, Pelgrom ’s equation is visualized for variation in threshold w ith A vln~25
mV*um, S'vrAuV/um and a fairly large transistor size o f W =L=30um . The local area vari­
ance in the right-hand side o f Figure 4-1 can be seen as a constant line as it is independ­
ent from distance, w hereas the distance variation follows a quadratic behavior. W ith in­
creasing distance, the variation w ith distance becom es dominant. The left side o f Figure
4-1 expresses the standard deviation o f param eter Vt„.
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Pelgrom: a
Pelgrom : V ariance V
(Vto)
W=30um L-30um
2.5
W=30umL=30um
o
8c:
0.5
40
60
20
100
100
Distance [um]
Figure 4-1: Pelgrom 's model for standard deviation (left) and variance (right).
M ore detailed modeling techniques for m ism atch are reported in [ 6 ], allow ing continuous
m ism atch modeling by introducing a spectral model. A dvanced simulation engines for
predicting mism atch can be found under [7]. M easurem ents in this paper also indicated
that Pelgrom ’s linear approach betw een m ism atch and device distance is only acceptable
for very short distances. A dditionally, Pelgrom ’s area based approach depends strongly
on the device shape or aspect ratio [ 8 ].
The M onte Carlo sim ulation setup using Cadence was set up to use the simplified ap­
proach using Pelgrom ’s linear approach. In order to run M onte Carlo simulations, the
correlation coefficient betw een devices has to be found. The correlation coefficient re­
flects the physical m atching betw een devices and is hence strongly dependent on layout.
For this study, the follow ing design assum ptions are made: The design is observed sepa-
124
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rating m atching and process deviations. The reasoning for this choice is that A vt has a
value in the order lOmV/um. U sing large transistors, Vt is likely to change w ithin the
process tolerance and expresses hence to some extent device distance effects o f process
param eters. In the case o f the m atching correlation factor, a higher value is chosen to ex­
press the physical m atching between devices utilizing layout techniques.
In order to narrow dow n the correlation factor for the device matching, [9] w as used. This
particular paper is quite fascinating since it reflects the causes o f mism atch on the physi­
cal level, or in other w ords the edge roughness o f the polysilicon gate. Pelgrom ’s ap­
proach reflects the m ism atch o f e.g. Vt as an average function o f device size. Following
Pelgrom ’s approach, for submicron transistors, the m atching should therefore be ex­
trem ely good, since the physical separation betw een the devices is quite small. N everthe­
less, m ism atch becom es m ore and m ore o f im portance in subm icron devices and begins
to im pact timing assum ptions. For analog design, m ism atch is always important. As de­
scribed in [9], the polysilicon edge roughness dom inates the m atching o f the devices. In
[10], this observation is additionally confirmed. In this paper, A vt and Ap (current gain) are
compared over process generations (2.5um to 0.18um). W ith shrinking device sizes, A vt is
decreasing accordingly but Ap stays nearly constant and again points out that from device
generation to device generation the w idth/length variation did not improve. R eferring to
[9], the SL is in the order o f 15nm. The designs in this study are using gate lengths and
widths o f 30um. C om paring this num ber to the <5L=15nm, this effect seems to be o f little
importance to the design.
125
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In current m ode circuits, the signal is current or, from another perspective, it is varying
the fixed bias that is m irrored into the next branch. U sing [9] w ith the proposed data, a
30x30um current m irror configuration as shown in Figure 4-2, biased w ith lOuA, w ould
cause a 3 a bias variation o f 3.4nA. This num ber seem s still to have little importance.
Since the bias current is conveyed m odulating the bias current, this bias variation has im­
pact on the signal current.
h
Figure 4-2: Simple Current Mirror
M ost o f the current m ode circuits shown in this study are biased w ith lOuA, targeting a
signal range from 0 to 2.5uA or more. The 3.4nA m ism atch due ju st to the polysilicon
roughness could limit the dynamic range to values < 60dB and does not include any ef­
fects originating out o f the device size itself, such as threshold voltage variation. This
126
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statem ent is only true for circuits w here the DC inform ation is part o f the signal. M is­
m atch expresses itself in a DC shift o f the signal. The current m ode auditory nerve proc­
essing schem e is sensitive to DC shifts, since the processing schem e is using the DC in­
form ation to adopt itself the environm ental settings. The auditory nerve also consists o f
tw o current m ode multipliers. A ny DC shift w ill be m ultiplied by these elements. In
m any applications, these kinds o f DC offsets w ould not have any im pact on the circuit
perform ance (e.g., bias current o f a voltage m ode differential pair). B ut again, one has to
distinguish w hat kind o f system is being designed. In current m ode signal processing cir­
cuitry, these kinds o f effects will im pact the overall system perform ance. The problem
gets m ore severe w hen a m assive parallel system has to be designed in w hich no offset
tuning is available. To w in the race against m atching constraints in signal processing cur­
rent m ode technology, there are only two cures: higher bias currents and signal swings or
larger device sizes.
The question rem ains— w hat correlation coefficient (cc) should be chosen to express the
m atching o f physical devices? Figure 4-3 shows a M onte Carlo run (Pelgrom ) for the cir­
cuit displayed in Figure 4-2. A dditionally, the data for poly roughness from [9] is shown.
The vertical axis is the three sigma deviation o f the bias current, set to lOuA. The hori­
zontal axis expresses the transistor sizes w here the transistor length equals the transistor
w idth for each data point.
127
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Pelgrom vs Poly Roughness, cc=0.97, Simple Current Mirror, Bias=10uA
180E-9
160E-9
140E-9
o
120E-9
E
10
100E-9
n
80E-9
■C
13
E
O)
(75
to
\\
\\
\\
\\
---------------
60E-9
40E-9
Poly Roughness
— • Monte Carlo (Pelgrom)
\
\
\
^
20E-9
000E+0
000E+0
_
-
----------5E-6
10E-6
15E-6
20E-6
25E-6
30E-6
Length=Width [m]
Figure 4-3: Pelgrom vs. Edge Roughness for W=L device sizes
A ssum ing that for small devices the po ly roughness dominates the m ism atch behaviour o f
a transistor rather than the threshold variation, cc can be adjusted in such a w ay that for a
small device size, the three sigma deviation from the M onte Carlo sim ulation m atches the
three sigma estimate via the poly roughness. For this particular case, a cc=0.97 is m atch­
ing the M onte Carlo simulation for a device o f 2x2um. For a larger device size as shown
in Figure 4-3, the threshold variation quickly dom inates the m ism atch behaviour. N ever­
theless, the edge roughness w ould still contribute approxim ately 1/3 o f the overall bias
current variation for a device size o f 30x30um.
128
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This m ethod o f finding a correlation coefficient is m ore a guideline since it assumes that
the data found in [9] is true for a w ide variety o f process generations above 250nm nodes.
The data provided in [10] is strengthening this assum ption and is also supported by [11].
F or all M onte Carlo sim ulations in this study, a low er correlation coefficient cc o f 0.95
w as used for all m ism atch sim ulations. In Chapter 4.4 M onte Carlo sim ulation data using
a cc=0.95 is com pared w ith test chip data. The results m atch up for a limited num ber o f
chips (2x5 chips). Thus, w ith the used layout style, the correlation coefficient seems to
m eet reality and is therefore used throughout this study.
4.3.2 Parameter Correlation
In general, physical fabrication process variations are not directly m odeled in M onte
Carlo simulations, since these param eters are hard to acquire. In order to extract m is­
m atch and process variations, non-physical param eters are evaluated, w hich are easier to
measure. Figure 4-4 [6 ] gives an overview o f physical param eters w ith their im pact on
non-physical param eters used in M OS device modeling. A n overview betw een the corre­
lation o f BSIM spice model param eters can be found in [12],
129
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n
H
U
U
S
CL
E
o
m
u
at
TJ
o
' ok
E
TO
Non-Physical
Physical
Figure 4-4: Correlation o f parameters.
M onte Carlo sim ulations have the tendency to be very pessim istic. In order to perform
realistic simulations, the problem for current m ode circuits should be split into two inde­
pendent simulations: process variation and m ism atch variation. Threshold variation has
less im pact on a current m ode circuit than the physical geom etry of, for example, a cur­
rent mirror. Using this exam ple, a variation in w idth has a dram atic im pact on copied cur­
rent, whereas the deviation o f the threshold does affect the circuitry less. An easy expla­
nation for this phenom enon is that the threshold voltage variation for a particular device
is dependent on inverse area (equation 4-1), whereas the variation in width directly im ­
pacts the current ratio. This difference m ight be obvious, but the designer o f current m ode
circuits must be aw are o f this fact in order to m ake M onte Carlo simulations useful for
predicting circuit behavior.
130
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In analog circuit design, matching is the key to a successful design. The matching b e­
tw een tw o devices under the influence o f the standard deviation is expressed using a cor­
relation coefficient, cc (equation 4-2):
^
= ^ toto/ - V l - c c
Equation 4-2 [13] show s the dependencies betw een the param eters, w here
deviation spread and
a COrr
(4-2)
o t0tai
is the full
the resulting spread under correlated conditions. A cc=0.75 ex­
presses that the deviation between two m atched devices is h a lf the total spread o f this pa­
ram eter during overall processing. For the proposed work, a cc=0.75 is chosen for proc­
ess variations and a cc= 0.95 between m atched transistors. In depth correlation methods
can be found in [13].
4.3.3 Correlation coefficient
Statistically, the correlation coefficient cc m easures the strength and the direction o f a
linear relationship betw een two variables. The value o f cc is such that - 1 < cc < 1 where
a positive correlation indicates that both variables change into the same direction,
whereas a negative cc indicates that the change in one variable drives the other variable
into a negative direction. Equation 4-3 expresses the correlation coefficient function:
131
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(4-3)
HZ*2)-(X4 ■MZSHZy)2
W here x and y are functions with n num ber o f samples. A correlation greater than 0.75 is
generally described as strong, whereas a correlation less than 0.5 is generally described as
weak. T he squared correlation describes the proportion o f variance (fluctuation) betw een
the tw o variables. The value o f cc2 is such that 0 < cc < 1. cc2 expresses how w ell the
regression line represents the data. For exam ple, i f cc = 0.866, cc 2 = 0.75. H ence, 75% o f
the total variation in one o f the variables can be explained by the linear relationship be­
tw een the variables. The rem aining 25% percent o f variation rem ains unexplained [14],
4.4 Monte Carlo Analysis of Circuits
This section discusses perform ance issues o f circuits introduced in Chapter 4 under m is­
m atch conditions. Furtherm ore, the sim ulated and analytical derived behaviors o f the dif­
ferent circuits are cross-checked against subm itted design and a trusted design guideline
is established. The circuits analyzed are the current m ode low-pass filter (LPF), the fully
balanced current m irror (FBCM ) and the fully differential m ultiplier (DIFFM ULT),
w hich are the m ain building blocks o f a current m ode auditory nerve.
The param eters o f interest are common m ode rejection ratio (CM RR) and total harm onic
distortion (THD). Both param eters are good indicators o f the presence o f mism atch. The
132
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C M R R o f an ideal differential circuit w ould be theoretically infinite. In general, differen­
tial circuits have lim ited CM RR due to circuit limits such as finite gain. The presence o f
m ism atch puts additional constraints on the circuit behavior and can be the dom inating
factor, determ ining the CMRR. TH D gives insight into any non-linear behavior o f cir­
cuits. Ideally, differential circuits w ould not have even order harm onic distortions, allow ­
ing an extended dynam ic range. U nder m ism atch, even order harm onics are generated
and can becom e dominant. Taylor series expansion gives in this w ay insight into the non­
linear dynam ics o f the analyzed circuits.
The core circuitry o f the submitted designs is surrounded by additional circuit elements
such as on the chip V 2I converter and FBCM elements for buffering purposes. Thus, the
overall m ism atch behavior is a function o f all system elements.
The general m ethod o f analysis is M onte Carlo simulations. The circuits are also ana­
lyzed using analytical methods around sm all-signal parameters. A dditionally, both M onte
Carlo sim ulations and analytical results are com pared with chip test data.
4.4.1 Current Mode Low-Pass Filter Chip
The current m ode low-pass filter chip was com posed o f highly linear V2I converters fol­
low ed by an FBCM element interfacing the current mode low -pass filter. The output o f
the current m ode low-pass filter was again buffered by an FBCM element.
133
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Figure 4-5 shows the M onte Carlo sim ulation result for the w hole chip. The input was
1Vdiff w ith typical bias currents set to lOuA. The cut-off frequency w as set to »
1 kHz.
THD Mismatch Variation cc =95%
THD Process Variation cc=75%
300
0.2
0 .4
THD Pi]
Figure 4-5: THD full chip under process and mismatch deviation.
The process variation shows a uniform distribution. The origins o f this are the V2I con­
verters. The carrier m obility variation is the limiting factor here. The non-G aussian dis­
tribution originates from the carrier m obility deviation, w hich is uniform ly m odeled in
the M onte Carlo sim ulation setup and is an indication for a process control parameter.
The m ism atch variation follow s a G aussian distribution with a standard deviation o f
0.047%. In both cases, the circuit does not exceed a THD>1% u nder m axim um input
conditions.
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The subm itted chip w as tested under the same bias conditions as the M onte Carlo sim ula­
tion. T able 4-1 gives an overview o f the THD o f each chip and channel. Each chip had
tw o 2 nd order low-pass channels.
Chip.Channel
1.1
1.2
2.1
2.2
3.1
3.2
4.1
4.2
5.1
5.2
THD [%]
0.1 6 6
0 .1 6 3
0 .1 6 9
0 .1 6 6
0.167
0.169
0.1 6 9
0.174
0.171
0 .1 6 7
Table 4-1: THD for different chips from the same fabrication run.
Com paring Table 4-1 w ith the data o f Figure 4-5 shows that the data is w ithin the pre­
dicted range. Com paring the m easured THD w ith the sim ulated THD under process
variation suggests that the process w indow was at a near extrem e. W ith a single chip
subm ission, one should be careful o f m aking such a statement. Since the results in C hap­
ter 5.5.4 are on target and validate the design assumptions, it is believed that this run was
m ade at a process w indow extrem e. The standard deviation o f the THD under m ism atch
o f Figure 4-5 is 0.047% , w hereas the standard deviation o f the m easured THD in Table
4-1 0.003% and hence nearly an order o f m agnitude better than predicted. In general, one
w ould doubt the design assum ptions, but again, in Chapter 5.5.4, the results line up very
exactly. The standard deviation o f the THD is an indicator o f the m ism atch behavior.
Since the overall THD was at the low er end, the 2nd order harm onics which w ould indi­
cate the impact o f m ism atch cannot contribute.
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4.4.2 Fully Balanced Current Mirror
The fully balanced current m irror topology was introduced in C hapter 3.3.2. In order to
m odel the mism atch behavior o f the FBCM with respect to the CM RR, a variation o f the
transconductance o f the transistors is considered. In general, all transistors are operated in
saturation. Hence, gm can be expressed as (equation 4-4):
(4-4)
The com m on mode rejection o f both subm itted designs is dom inated by the FBCM ele­
ment. In general, the m ultiplier core and current m ode integrator do not have a very good
CM RR, and therefore have to rely on interface elem ents such as the FBCM elem ent to
introduce com mon m ode rejection ability. Due to this fact, the core stages were protected
from the input and output side w ith FBC M elements.
Threshold variations due to process variations are not considered, since they have little
impact on A cm. In order to model the variation o f g m, w idth changes, AW, and length
changes, AL, are considered. In M onte Carlo, A W and AL are absolute variations and sub­
je ct to process control. The norm alized g m deviation clgm can be expressed as (equation 4-
5)
136
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, w here A W» 0.4um and AL&0. lu m for a typical 0.8um process. Since the circuit is highly
sym m etric, com m on m ode gains occur through m ism atch o f one h alf side o f the differen­
tial structure. A very pessim istic expression for the com m on m ode gain is (equation 4-6).
A detailed derivation o f equations 3-13 can be found in A ppendix E.5.
t’ + ^ m
a x )2
(1 +
J-
l1+^mj (1+^
Sm
max
(4-6)
The subm itted circuit was sized with 30x30 um 2 transistors. Assum ing a correlation coefficient o f cc=0.95, the com m on mode rejection ratio CM RR=36dB. As awful as this
value sounds, it basically expresses the C M R R for tw o independent h alf circuits that are
mism atched in tw o extreme regions. Figure 4-6 show s the C M R R o f the FBCM element.
U nder the sim ulated conditions, the worst case C M R R is >50 dB and its mean value is
6 6
dB. This value has to be im proved in the future. A ctive m ethods such as com m on­
m ode feedback can be applied to increase C M R R as discussed in [15].
137
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CMRR under Mismatch Variation cc =95%
4 0 0r
CMRR [cIB]
Figure 4-6: CM RR under mismatch variation.
The subm itted designs incorporated the FBCM elem ents w ithin the system. The pre­
sented data for C M R R expresses the overall C M R R o f the chip. Since the FBCM elem ent
has the highest CM RR, acquired CM RR data can be traced back to this element. Table
4-2 show s the CM RR for the low -pass filter and current m ultiplier chip submission.
Figure 4-7 displays the numbers from Table 4-2.
Chip.C hannel
1.1
1.2
2.1
2.2
3.1
3.2 4.1
4.2
5.1
5.2
C M R R LPF [dB]
62
63
56
59
62
61
60
64
60
63
C M R R M U LT [dB]
58
61
63
59
56
62
57
64
70
68
Table 4-2: CM RR for submitted designs.
138
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Measured CMRR FBCM from MULT/LPF
6
50
55
60
65
70
75
CMRR [dB]
Figure 4-7: M easured CMRR.
Com paring Figure 4-6 w ith Figure 4-7 show s a good agreem ent betw een the simulation
and the actual m easurem ent o f the fabricated designs. The data betw een the independent
chip subm issions agree w ith each other. B oth submissions have the sam e FBCM element
in com m on and hence point additionally to this element, determ ining the overall CMRR.
The CM RR is a good indicator for the m ism atch behavior for this particular element.
Hence, the m atching correlation coefficient o f 95% is a good choice to m odel the im pact
o f m ism atch variation.
139
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4.4.3 Current Mode Multiplier
In C hapter 3.3.5, the differential current mode m ultiplier was introduced and transient
test data was presented. This section highlights the m ultiplier perform ance w ith respect to
expected m atching behavior. Figure 4-8 shows the spectrum o f the current multiplier,
w here one input was set to 2VPP @ DC and the other input was driven by a 100 Hz sine
w ave w ith an am plitude o f 2VPP. The bias currents were set to lOuA. U nder these operat­
ing conditions, the m ultiplier exceeds 60dB o f dynamic range w ith a T H D « 1 % . W ith
further increase o f the input voltage, the
2
nd harm onic distortion is gaining dominance
due to m ism atch in the fabricated circuitry.
The spectrum contains also some harm onics at vary low frequencies (23H z fundamental,
harm onics up to the 5th order harm onic at 138Hz can be observed). These harm onic con­
tributions are from the test setup or equipm ent used to test the chip - the exact origin o f
these low frequencies causing this effect is unknown.
140
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Spectrum VX 1Vpp @ 100Hz
1
10
100
- 1 0 --------
1000
2
10000
HD (a> 200Hz
-2 0 -------^
- 3 0 ----------
m
-4 0 --------
05
- 5 0 ---------60
«
3 H D (a), 300Hz
-70 -80 - - 9 0 -S
-
100- -
Frequency [Hz]
Figure 4-8: Spectrum o f the current mode multiplier.
The system outline o f the current m ode auditory nerve chip is full differential, and hence
a full differential m ultiplier is needed in order to avoid differential-to-single-ended con­
versions, and vice versa. The single-ended-to-differential conversion is also a potential
source o f com mon-mode artifacts.
As discussed in Chapter 3.3.5, the m ultiplier needs eight w ell-m atched input pair currents.
If the input pair currents are m ism atched, a 2nd order harm onic distortion will appear at
the output o f the multiplier. In general, the input offset current can be m odeled as an o ff­
set to these input pairs (equation 4-7)
141
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4, =4,-(i+a,)
w here
(4-7)
is the m ean value for input current pairs. A t is the m ism atch percentage for a
corresponding input pair. Using this approach, it can be shown that the w orst-case second
order harm onic distortion H D 2 can be expressed as (equation 4-8)
(l
V + A2m ax /) I y diff ~
w here I
and /
max' / yvdidr
(4-8>
are the ideal differential input currents that are forming the eight
m atched input pairs into the multiplier. Amax is the m axim um offset percentage. For the
m axim um allowed input current (equation 4-9)
the worst-case is a second order harm onic distortion /fZ)2 max*AmaX. Hence, w ith Amax= l% ,
a second order HD 2 w ith 1% can be expected. Since equation 4-8 indicates a linear rela­
tionship between Amax and HDjnax, one m ight conclude that the H D 2 has a linear distribu­
tion. Figure 4-9 shows the result for a linear param eter sweep over A) to Agvia the origi-
142
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nal function. The distribution has a m ean value o f 0.23% . The HD 2 depends on the over­
all distribution o f its input offsets.
Distribution HD2 4Q uad Mult @ DC offset 1 %
2500----------------- .-----------------,----------------- 1----------------- ,-----------------
THD[%]
Figure 4-9: Distribution HD2 for -1% < A2_g <+1%.
M onte Carlo sim ulations on the submitted circuits w ere also performed. The M onte Carlo
simulations for any param eter to be analyzed are perform ed in two steps: Process varia­
tion and m ism atch variation. The correlation coefficient factor cc expresses how the dis­
tribution o f the overall process variation affects the m atched transistors. A cc=0.75 indi­
cates that the distribution for any M onte Carlo param eter is h alf the overall process varia­
tion o f this param eter. On the other side, the physical m atching corresponds to the fabri­
cation accuracy o f poly-silicon gate, w hich includes also the im pact o f additional proc­
essing steps such as deposition or etching. Figure 4-10 shows the total harm onic distor­
tion (THD) o f the circuit under process variations and a cc=0.75.
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THD Process Variation cc =75%
300
p
25
0.3
1---------- 1-----------■
-----------1-----------1---------- 1----------
0.35
0.4
0.45
0.5
0.55
0.
THD [%)
Figure 4-10: THD under process variation, cc = 75%.
C urrent m ode circuits are sensitive to geom etrical mism atch. A correlation coefficient
cc=0.75 as used in the process deviation sim ulation does not make m uch sense for the
m ism atch analysis. A s previously m entioned, a cc=0.75 equals h a lf the total standard de­
viation. A t geom etry level, this correlation factor w ould basically make m atching o f de­
vices nearly obsolete. In general, correlation coefficients for geom etry are m uch higher.
In some special applications, a m atching coefficient over cc=0.99 is realized, w hich is
narrow er than ten times the standard deviation distribution. For the developm ent o f the
new circuits, a cc=0.95 or approxim ately 4.5 tim es narrow er than the standard deviation
distribution for w idth and length was chosen (see also C hapter 4.3.1). Figure 4-11 shows
the sim ulation result under these conditions. T he bias for the m ultiplier w as set to h ias=10uA and the maxim um input signal /,„ w as 20uA (see equation 3-21).
144
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THD Mismatch Variation cc =95%
0 .5 2 4
.1
0 526
0.528
0 .53
0 .5 3 2
0
THD
Figure 4-11: THD under mismatch variation with cc=95% .
Figure 4-12 shows the M onte Carlo sim ulation w ith respect to harm onic distortion for the
foil subm itted chip including V2I converters, FBCM elements and m ultiplier core. The
core o f the m ultiplier is biased at 5uA, reflecting the input range set for the V2I converter.
The m axim um voltage swing is 2Y PP.
THD Process Variation cc= 75%
0.4
0.6
THD Mismatch Variation cc =95%
0 .8
03
THD [%)
0.3 1
0.3 2
THD [%)
Figure 4-12: M onte Carlo run for submitted chip.
145
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As in C hapter 4.4.1, the process variation shows a uniform distribution and originates
from the V2I converter. The carrier m obility variation is the lim iting factor. The m is­
m atch variation follows a G aussian distribution with a standard distribution o f 0.052%. In
both cases, the circuit does not exceed a TH D >1% under m axim um input conditions.
The subm itted chip was tested u nder the same bias conditions as the M onte Carlo sim ula­
tion. Tw o fully differential current m ode multipliers were integrated on a single chip and
are indicated in Table 4-3 as channels.
Chip.Channel
1.1
1.2
2.1
2.2
3.1
3.2
4.1
4.2
5.1
5.2
T H D [% ]
0.415
0.476
0.290
0.397
0.303
0.448
0.479
0.398
0.404
0.373
Table 4-3: THD for the fabricated chip.
Comparing the THD o f Table 4-3 w ith the THD under process variation o f Figure 4-12
shows that the run stays w ithin the predicted limit and is close to a nom inal value. The
standard deviation o f the TH D under m ism atch conditions in Figure 4-12 is 0.052%,
whereas the m easured standard deviation suggests a 0.063% m atching variation, w hich is
a good match w ith the sim ulation results.
146
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4.5
L ayout C onsiderations
The layout sizing was driven by the available pow er budget. A s previously mentioned,
there are only two w ays to cope w ith mism atch in a current m ode signal processing
scheme: higher bias currents or larger device sizes. The design goal was a 64-channel
chip with a pow er consum ption < 1W. The overall bias current can be calculated to be in
the range o f lOuA. H ence, the signal swing will be lim ited to e.g., 2.5uA. Since the signal
current has to be kept small, the device sizes have to be increased. In general, a die can
have up to 360 m m o f active chip area (including pad frame), which is the area con­
straint for the overall system. A n initial estimate o f the total num ber o f transistors was
made. The area lim itation suggested that an nm os current m irror could use up to
30x30um. The chip subm issions introduced in Chapter 4.4 are using these device dim en­
sions.
Figure 4-13 shows the layout o f the full differential current m ode m ultiplier (cell size
1550pm x 750pm). The design consists o f V2I converter, fully balanced current mirrors,
the m ultiplying core, a current subtracting circuit and a current output stage. The two dif­
ferential inputs have their ow n pathway. Hence, some portions o f Figure 4-13 seem to be
horizontally mirrored. M irroring is norm ally a bad layout practice. But since only local
m atched groups are necessary, this is not necessarily true for this design. Com m on cen­
troid structures were used to enhance the matching betw een the devices. For larger cur­
rent mirror arrays, an interleaved layout style was used. All groups used dumm y devices.
147
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In general, it is not so easy to lay out w ith large devices. A large device can be broken
into sm aller devices, but very often the level o f interconnection required to enhance
m atching w ould sacrifice a trem endous am ount o f the layout area. M ore area means m ore
threshold variation betw een the devices. Thus, a good balance betw een layout style and
interconnect effort has to be found.
V2I
FBCMx4
,
V2I
TTTfi
•
MULT
7771
FBCMx4
SUB
FBCM
Figure 4-13: Full differential current mode m ultiplier (with VI converter).
Figure 4-14 shows the m ain block o f a 1st order current m ode low-pass filter (cell size
800pm x 370pm). A gain, the large device sizes are obvious. The large and long transis-
148
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tors in the bottom o f the figure (A) are the nm os integration transistors. The long channel
assures the operation in the triode region. A bove from this structure, a com m on centroid
pm os current m irror (B) sets the bias current for (A). On the left side o f this figure, a
chess-board like configuration indicates the capacitor (C) for the integration node. This
2x1 OpF capacitor is an interleaved capacitor structure using unitized poly capacitors for
the differential signaling path. The design is quite com pact and interleaved w ith dummy
structures all around the effective capacitor. The m otivation behind this is to assure a
good roll-off behavior in the pass-band region. P oor m atching o f the capacitor would
cause DC shifts in the pass-band. Structure (D) is the differential OTA, w ith a com mon
centroid differential input pair (E).
»4f j f f l
it
■
F igure 4-14: Full d ifferen tial cu rren t m ode low -pass filter.
149
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A good reference for layout is [16]. In analog design, the type o f circuitry drives the lay­
out style. In this low frequency signal processing application, the transistor placing dom i­
nates the layout and signal routing is secondary. In high speed designs, m atching m ight
be sacrificed in order to achieve shorter nets to im prove parasitic loading on critical nets.
In analog layouts, there is no unified answ er to the perfect layout, since the problem sets
are close tied to the design. A general truth exists, though: Symmetry w ill generally en­
hance the circuit perform ance [17].
C om m on centroid is an accepted m ethod o f device m atching and is m ainly used for dif­
ferential circuits especially for differential input pairs. The devices are placed in an iden­
tical m anner around a common center point. Larger devices can be split into sm aller de­
vices and arranged in this fashion. In general, structures w ith a com m on centroid struc­
ture take more effort to plan and layout. For m atched devices, the current should flow
into the same direction. A mirrored design is likely to have different electrical character­
istics and should be avoided. Figure 4-15 show s a simple but typical device placem ent for
a com m on centroid structure with all drains o f the devices e.g. oriented to the left. This
pattern can be used for example in a differential input pair (device A and B) where these
large devices are each split into M sm aller structures w ith uniform dim ensions. W here the
factor M m ultiplied with the size o f one o f the sm aller devices equals the size o f the lar­
ger one. For instance a 20um wide by lu m long transistor w ill be split into M = 8 sm aller
transistors each sized 2.5um wide by lu m long.
150
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F igure 4-15: C om m on centroid device placem ent.
In general, this com m on centroid structure w ould be surrounded b y dum m y devices and a
guard to assure that all devices “see” the same local environm ent. M ore com plex struc­
tures need a m ore careful strategy. In general, common centroid w orks w ell for two de­
vices w ith an even order. Figure 4-16 shows a m ore com plex arrangem ent for a factor
M = 8 (split o f the differential input pair into eight smaller devices). The choice for the
factor M should be 2, 4, 8 , 16, 24, 32, ... to achieve best symmetry.
151
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A
B
A
B
B
A
B
A
A
B
A
B
B
A
B
A
F igu re 4-16: C om m on centroid placem ent w ith M =8.
Circuits with more than tw o devices to be matched, inter-digitating m ight be the m ore
practical solution. A good exam ple for this is e.g. a current m irror w ith the diode con­
nected input and tw o current output branches. Figure 4-17 provides an ideal example.
The diode connected transistor is indicated as A (with an M =3) and two current output
branches (B and C w ith an M =2). D indicates a dumm y device.
D C A B A C A B D
F igu re 4-17: Inter-digitated device arrangem ent.
The diode connected transistor is evenly distributed over distance “providing” devices to
the left and to the right bias voltage that reflect local process condition. Hence, distribut­
ing A over space helps to average out any special gradients such as variation in threshold,
stress conditions as w ell tem perature gradients.
152
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4.6 References for Chapter 5
[1]
M. Pelgrom , A. D uinm ajer, and A. W elbers, "M atching properties o f M OS tran­
sistors," IE E E Jo u rn a l o f solid-state circuits, vol. 24, pp. 1433-1439, 1989.
[2]
J.-B. Shyu, G. C. Tem es, and F. K rum m enacher, "Random error effects in
m atched M OS capacitors and current sources," IE E E Journal o f solid-state cir­
cuits, vol. S C -19, pp. 948 - 955, 1984.
[3]
K. R. Lakshm ikum ar, R. A. Hadaway, and M. A. Copeland, "Characterisation and
m odeling o f m ism atch in M OS transistors for precision analog design," IE E E
Journal o f Solid-State Circuits, vol. 21, pp. 1057-1066, 1986.
[4]
U. Schaper, C. G. Linnenbank, and R. Thew es, "Precise characterization o f long­
distance m ism atch o f CM OS devices," IE E E Transactions on sem iconductor
m anufacturing, vol. 14, pp. 311 - 317, 2001.
[5]
A. G. A ndreou, K. A. Boahen, P. O. Pouliquen, A. Pavasovic, R. E. Jenkins, and
K. Strohbehn, "Current-m ode subthreshold M OS circuits for analog VLSI neural
systems," IE E E Transactions on neural networks, vol. 2, pp. 205 - 213, 1991.
[6 ]
U. Gruenebaum , J. Oehm, and K. Schumacher, "M ism atch modeling and sim ula­
tion - a com prehensive approach," K luw er A cadem ic Publishers, A nalog inte­
grated circuits a n d signal processing, vol. 29, pp. 165 - 171, 2001.
153
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[7]
G. B iagetti, S. O rcioni, C. Turchetti, P. Crippa, and M. Alessandrini, "SiSM A-a
tool for efficient analysis o f analog CM OS integrated circuits affected by device
m ism atch," IE E E Transactions on C om puter-Aided D esign o f Integrated Circuits
a n d System s, vol. 23, pp. 192-207, 2004.
[8 ]
S. J. Lovett, R. Clancy, M. W elten, A. M athew son, and B. M ason, "Characteriz­
ing the m ism atch o f submircon MOS transistors," Proceedings o f the 1996 IE E E
international conference on m icroelectronic test structures, vol. 9, pp. 39 - 42,
1996.
[9]
R. D iffenza, P. Llinares, S. Taupin, R. Palla, C. G amier, and G. Ghibaudo, "Com ­
parison betw een m atching param eters and fluctuations at the w afer level," pre­
sented at Proceedings o f the IEEE 2002: International conference on m icroelec­
tronic test structures (ICM TS 2002), N ew York, N ew York, 2002.
[10]
P. R. K inget, "Device m ism atch and tradeoffs in the design o f analog circuits,"
IEEE Journal o f Solid-State Circuits, vol. 40, pp. 1212-1224, 2005.
[11]
P. G. D rennan and C. C. M cA ndrew, "U nderstanding M OSFET m ism atch for
analog design," IE E E Journal o f solid-state circuits, vol. 38, pp. 450 - 456, 2003.
[12]
C. M ichael and M. Ismail, "Statistical m odeling o f device mismatch for analog
MOS integrated circuits," IE E E Journal o f solid-state circuits, vol. 27, pp. 154 166, 1992.
[13]
M. Conti, P. Crippa, S. Orcioni, and C. Turchetti, "Layout-based statistcal m odel­
ing for the prediction o f the m atching properties o f MOS transistors," IE E E
154
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Transactions on circuits and system s - I: Fundam ental theory a n d applications,
vol. 49, pp. 680 - 685, 2002.
[14]
R. J. Rumm el, A pplied fa c to r analysis. Evanston: N orthw estern U niversity Press,
1970.
[15]
K. Koli and K. A. I. Halonen, "C M RR enhancem ent techniques for current-m ode
instrum entation amplifiers," IE E E Transactions on Circuits and Systems I: Fun­
dam ental Theory a n d Applications [see also IE E E Transactions on Circuits and
System s I: Regular Papers], vol. 47, pp. 622 - 632, 2000.
[16]
A. Hastings, The art o f analog layout, 2nd ed: Prentice Hall, 2005.
[17]
J. Bastos, M. Steyaert, B. G raindourze, and W. Sansen, "Matching o f M OS tran­
sistors w ith different layout styles," P roceedings o f the 1996 IE E E international
conference on m icroelectronic test structures, vol. 9, pp. 1 7 - 18, 1996.
155
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5 Auditory Nerve Chip
In this chapter, individual building blocks for the current m ode auditory nerve chip are
introduced and discussed w ith respect to their transient behavior and the perform ance un­
der m ism atch constraints. In general it should be noted that this chapter relies only on
sim ulation. M ethods and observations from Chapter 3 and 4 are used and fused together
in this chapter. The dom inating building blocks are the differential current m ode m ulti­
plier, as well the current m ode integrator. These two designs w ere fabricated and tested
and so strengthen the overall system perform ance prediction.
5.1 Introduction
The detailed analysis o f the current m ode auditory nerve chip in this study was strongly
m otivated by an overall failing system perform ance o f previously subm itted chips. Hence,
as an introduction, here is a small history o f previous subm itted runs. Figure 5-1 shows a
reticle w ith six different current m ode designs. The low er left com er o f Figure 5-1 shows
a current m ode auditory nerve chip (C). The design to the low er right shows a current
m ode auditory nerve chip (D) with a traveling w ave cochlea filter bank [1], [2] as its in­
put. Overall, six different designs w ere put on the reticle, w hich at the end consisted o f
tw o versions o f the ANC (B,C), one version o f an electronic cochlea (A), a m erged ver­
sion o f EC and ANC on a single die (ECA N C, D), a low pow er version o f ECA N C (with
156
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external w atchdog control, E) and a test chip. All chips were designed using current mode
circuitry (F).
e
m mm
F igu re 5-1: 20x 2 0 m m 2 reticle o f subm itted d esign .
This w as the second try to realize an integrated version o f the auditory nerve model. R e­
garding the ANC portion o f this subm ission, the input to the A N C w as changed to be sin­
gle-ended to save pins. Also, revisions were m ade to the rectifier and 2nd order LPF. The
single stage AGC was changed to be a dual AGC. Instead o f using a current-to-ffequency
157
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converter, a spiking neuron w ith three populations was im plem ented. The asynchronous
interface was revised and im plem ented to be delay-insensitive.
The overall system perform ance could not be determined. The biggest problem was oscil­
lating spiking neurons. O nce triggered, a chain reaction triggered all other neurons and
this behavior cannot be stopped until the system is reset. A nother problem was the devia­
tion o f set values across the channels. For the input interfaces, a lOOnA current w ould set
the transconductance o f the V 2I converters. M easuring the bias values for each channel,
the bias current distribution deviates around 30%. This value could only be m easured at
the input stage, but the internal bias distribution should follow a sim ilar distribution.
A t this point it becam e clear that the bias distribution has to be addressed differently in
parallel current m ode structures by using individual current lines, rather than a global
voltage line, to set the bias current locally. If the bias settings betw een stages are off, a
DC shift for a single-ended im plem entation will occur. The sim ilar effect will occur
w ithin one processing stage under process and mism atch variations, since current m irrors
as main processing elem ents are sensitive to the device m atching. The elements in the
ANC were all m atched, b u t later M onte Carlo simulations showed that there is still a very
big need for im provem ent. A t the start o f the chip design, the CAD environm ent w as not
ready to accom m odate M onte Carlo simulations. Since the architecture is parallel, indi­
vidual tuning o f elem ents w as not possible. The whole processing scheme had to rely on
elements staying w ithin a specified tolerance window w ithout any external tuning.
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The test points m easured along the main processing core showed poor circuit perform ­
ance. The m easured DC voltage values at certain test points corresponded w ith the sim u­
lation results, but the input voltage swing for the V2I converter needed to exceed the lin­
ear range to get a response from the circuit. In m ost stages, the current signal ju st seem ed
to drift away. W e saw a sim ilar problem in the electronic cochlea chip. A fter three stages,
the response o f the circuit w as gone. In the current domain, a DC voltage does not neces­
sarily give an indication o f w hat w ent wrong. The current signal level inside the channel
is from InA to lu A (and above). M ost o f the internal nodes are low im pedance resulting
in a small voltage swing.
The results o f these subm issions w ere quite disillusioning. But the lesson was learned
w hen addressing such a m assive parallel analog structure: A different design m ethodol­
ogy has to be used. This m ethodology was introduced in Chapter 5 for basic building
blocks and is extended to a system level in this chapter.
5.2 Design Goal and Metric
The following sections show the M onte Carlo sim ulation results o f the individual current
mode building blocks o f the auditory nerve channel. The M onte Carlo analysis is based
on the conclusions m ade in Chapter 4. The sim ulation results focus on the DC offset o f
the individual stages as well for the whole auditory channel. The DC offset dom inates the
159
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overall system perform ance since the signaling path includes two analog multipliers. A ny
DC offset becom es a part o f the signal and is subject to get am plified according to the
signal processing schem e and is equivalent to an overall gain variation in the channel.
This gain variation has im pact on the spike encoding. D ifferent slew rates will trigger the
spike generator earlier or later and hence is introducing a spike tim ing jitter. This spike
timing jitte r is a metric to evaluate the perform ance o f the system. The focus o f this dis­
sertation is to present an analog current m ode auditory nerve chip that is suitable for
sound source localization using the tim e-delay-of-arrival m ethod (TDOA, C hapter 2).
The distance betw een e.g. tw o receivers (m icrophones) sets the m axim um time w indow
to determine the arriving angle o f the sound source. Spike jitter is the m easurem ent inac­
curacy o f the system. For a system w ith an eight-inch sensor spacing, a spike jitte r o f
lOOus w ould limit this system to an angle accuracy o f +/- 15 degrees. H ence, the system
performance evaluation is based on spike tim ing jitter.
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5.3 AN Building Blocks
In this chapter, a detailed overview o f the circuit im plem entation o f the auditory nerve
based on [3] will be provided. Basic stages like the current m ode integrator and multiplier
w ere already discussed in Chapter 4 and Chapter 5 and highlighted w ith respect to circuit
perform ance and mism atch. The overall auditory nerve circuit com plexity is around 1000
analog-operated transistors. In order to provide good system overview, the overall im ­
plem entation is highlighted by a sym bolic representation. A m ap to the symbols can be
found in Table 5-1.
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Current M ode M ultiplier (CM M )
0
Fully Balanced Current M irror (FBCM )
C urrent M ode Integrator (CM I)
B
B
©
Full W ave R ectifier (FW R)
H alf-w ave rectifier (HW R)
C urrent M ode A dder (CM A)
^ fl=
Spiking N euron (SN)
JL
C urrent Pulse G enerator (CPG)
Current Threshold Crosser (CTC)
R efractory Signal G enerator (RSG)
T able 5-1: Sym bol m app ing table.
162
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Table 5-1 contains more symbols than initially displayed in Figure 5-2. This table will be
a reference throughout this chapter for highlighting system aspects. Figure 5-2 shows the
overall circuit topology in a symbolic representation. To m aintain simplicity, the system
is displayed in a single-ended fashion, but shall represent a full differential im plem enta­
tion. A lso, feedback paths for the current m ode integrator (CM I) to form a low-pass filter
w ere om itted.
LPF
L LPF
F igu re 5-2: A ud itory nerve system outline.
A rough system outline based on biological models was provided in Chapter 1. Figure
5-2 shows now a more detailed representation that also points out some system aspects. A
current is first half-wave rectified (HW R). Rectification is perform ed in a non-biased en­
vironm ent. Flence, input and output im pedances can change rapidly. In order to protect
the low-pass filter (LPF) from any com m on m ode signals and also to m atch input im ped­
ances, a fully balanced current m irror (FBCM ) is inserted betw een the rectifier and low-
163
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pass filter. Two consecutive LPFs form a 2nd order response. This stage connects to the
dual autom atic gain control stage (DAGC), com posed o f two current mode m ultipliers
(CM M ), tw o current m ode adders (CM A) and three LPFs. The DAGC is the core elem ent
o f the auditory nerve processing scheme. The output o f this stage is again buffered w ith a
FBCM before the signal goes into a full w ave rectifier (FW R). This output connects to
the spiking neuron (SN) module. The SN circuitry is a sub-m odule w ith too m uch com ­
plexity to be shown in this system level and is thus displayed separately.
Figure 5-2 also highlights im portant system param eters that control the overall system
response. Om itting for now the param eters for the SN, the m ain channel is tuned w ith
five tim e constants for the filters, respectively tlp f, t i , t 2 and X3 , and tw o gain constants,
nam ely K1 and K2. These constants are all set in the current dom ain and control the dy­
nam ic response o f the auditory nerve.
5.3.1
Rectifier
The rectifier is in its functionality the simplest elem ent in the auditory nerve scheme.
Nevertheless, this building block can generate certain lim itations if certain design con­
straints such as accuracy, speed and limited chip area have to be met. The circuit im ple­
m entation o f a pseudo differential half-w ave rectification stage was discussed in C hapter
3.3.3.
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Figure 5-3 shows the input pattern into the channel. In consecutive sections, transient
graphs will relate to this input pattern: a 100 H z sine w ave w ith a 2.5 kHz am plitude
m odulation. The am plitude o f the input w ave form is lu A peak to peak. A ll transient
graphs represent differential output waveforms.
Channel Simulation: Input Transient Response
Time [s]
F igure 5-3: In p u t w aveform into the auditory nerve channel
Figure 5-4 shows the transient response to the input w aveform o f Figure 5-3. The rectifi­
cation process rem oves the bottom h a lf o f the input waveform.
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x106
Channel Simulation: Rectifier Transient Response
T im e [s]
F igu re 5-4: T ran sien t resp onse o f th e h alf-w ave rectifier.
In order to provide a statistical insight into the behavior o f the half-w ave rectifier, a
M onte Carlo sim ulation o f the w hole system w as performed. D espite the transient figure
in Figure 5-3, the input w aveform for the M onte Carlo run was a differential current pulse
with 2uA peak-to-peak. This choice was m otivated to reduce sim ulation time but also to
determine the gain variation o f the dual A GC stage with respect to its onset response.
Figure 5-5 shows the current output peak-to-peak o f the subm itted run. The correlation
between m atched transistors was 95% and included m ism atch as well as process devia­
tion.
166
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Monte Carlo Channel Simulation: Rectifier Output Current
1.
2.02
2.03
2.04
2.05
2.06
Ill
2.07
DifTerentml O u tp u t [A]
2 .0 #
2.09
2.1
x 10
F igure 5-5: M on te C arlo channel sim ulation at th e rectification stage, ou tp ut current m ism atch.
The input am plitude into the channel w as 2uA peak-to-peak. The m ean value o f the out­
put response under mism atch and process variation is 2.05uA w ith a standard deviation o f
12nA. Hence, under a three sigma assum ption, the am plitude can vary from 2.014uA to
2.086uA, w hich corresponds to an am plitude variation o f +/- 1.8% to the given output
waveform.
Figure 5-6 displays the distribution o f the DC com ponent o f the input signal. The DC off­
set com ponent is from special interest, since due to the m ultiplication stages, the DC off­
set will show up as a gain change at the dual A GC output.
167
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Monte Carlo Channel Simulation: Rectifier DC
<1.5
DC1A1
1
x 10
Figure 5-6: M onte Carlo Channel simulation at the rectification stage, DC mismatch.
For Figure 5-6, the m ean value for the DC offset is -300pA w ith a standard deviation o f
6
nA. W ith a three sigma assumption, the DC offset can vary in the range o f -18nA to
+18nA.
5.3.2 Envelop Detector
The envelope detector is com posed o f a second order low -pass filter. The topology was
introduced in Chapter 3.3.4 and discussed in C hapter 4.4.1 w ith respect to mism atch
variation. Figure 5-7 shows the symbolic representation.
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^ LPF
L
^ LPF
I ,out
in re c
Figure 5-7: Symbolic representation of the envelope detector.
The low -pass filter or in general, the current m ode integrator, is a recurring circuit
throughout the system. Figure 5-8 shows the transient response o f the envelope detector
after the rectification process. A n envelope is built up around the 2.5 kH z amplitude
m odulation (see Figure 5-3). The cut-off frequency t Lpf o f the envelope detector was set
to 1 kH z according to the auditory model.
169
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X
Channel Simulation: Envelope Transient Response
10'
1.4
1.2
s
©
0.6
0.4
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Tim e [s]
Figure 5-8: Transient response o f the enveiop detector.
Figure 5-9 shows the differential peak-to-peak output under a process and m ism atch
variation for a 2uA peak-to-peak current input pulse. The correlation betw een m atched
devices was 95%.
170
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Monte Carlo Channel Simulation: Envelope Output Current
30:
Differential O utp u t [A J
Figure 5-9: Monte Carlo channel simulation at envelope detector with output current mismatch.
The m ean o f the am plitude is 2.94uA with a standard deviation o f 16nA. Since this is a
channel simulation, this distribution also contains the m ism atch o f the previous rectifica­
tion stage. U nder a three sigma assum ption and given input w aveform , the am plitude can
change from 2.89uA to 2.99uA w hich corresponds to +/- 1.6% in gain.
Figure 5-10 shows the distribution o f the DC offset o f the output signal. The m ean value
o f the DC offset is 2nA w ith a standard deviation o f 16nA. Hence, the DC point can vary
in the range o f -48nA to 48nA, assum ing a three sigma distribution. The DC offset will
go into the dual A G C stage and hence into a m ultiplication stage. This DC offset will
contribute significantly to the gain variation. A n offset com pensation such as a high-pass
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filter is not possible, since the DC inform ation is a crucial portion o f the overall signal
processing.
Monte Carlo Channel Simulation: Envelope DC
DC |AJ
Figure 5-10: M onte Carlo channel simulation at the envelope detector with DC mismatch.
Figure 5-11 show s the com m on mode m ism atch at the output o f the envelope detector.
The standard deviation o f the com m on m ode is only 4nA but with a com m on m ode m ean
value o f 1.1 lu A . This 1.1 lu A comes m ainly from the input, w hich is connected to a
FBCM element. Im pedance m ism atch shifts the DC value to luA . Since the CM I has
very low com m on m ode rejection, the com m on m ode offset m akes it through the CMI.
This fact also m otivated the chip subm ission o f this configuration, discussed in Chapter 4,
where the CM Is w ere buffered with an FBC M at the input and output.
172
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t(>
Monte Carlo Channel Simulation: Envelope Common Mode
14
12
t.i
1.105
1.11
C o m m o n M o d e [A]
LI.
1.125
-6
X 10'
Figure 5-11: M onte Carlo channel simulation at envelope detector with common mode mismatch.
Since the interface block into the dual AGC is a full-differential m ultiplier w ith an FBCM
elem ent w ith high CM RR at its input, the com m on m ode signal is rejected.
5.3.3 Dual AGC
The dual AGC is the most com plex circuit elem ent in the auditory nerve scheme. The
dual A G C is com posed o f two main com ponents: current m ode integrator and multiplier.
These circuits w ere introduced in C hapter 4 and 5 and discussed regarding performance
and their behavior under mismatch conditions. A s previously m entioned, the overall audi­
tory nerve circuit im plem entation is fully differential. Figure 5-12 shows the system out­
line o f the dual AGC.
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out
/ in
env
K1
K2
Figure 5-12: System outline o f the dual AGC.
The transfer function o f the dual AGC is highly non-linear and hence an equation based
approach to the system behavior is has limited utility. O nly a very limited insight pro­
vides the approach, suggested in Figure 5-13. N evertheless it can help to get an equation
based insight into the dynam ics o f dual AGC. In contrast to the im plem entation in Figure
5-12, the low-pass filter in the feedback loop is replaced w ith an integrator. This is true in
“regular” A GC loops, w hen the RC tim e constant is m uch larger than the closed-loop
time response [4], In our case, the A GC has a com pressing function: The initial transient
input w aveform is first am plified and then regulated back after the tim e response o f the
low-pass filter. Hence, we look into a tim e-response m uch sm aller than the closed loop­
time response and hence define the region w here the assum ption o f using an integrator
174
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rather than a low pass filter is true. This m ust be taken into account w hen plotting the de­
rived function (see also Figure 5-14).
X (t)
z (t)
K1
Figure 5-13: AGC loop simplified for analysis.
U sing the m ethod o f replacing the low-pass filter with an integrator, following differen­
tial equation 5-1 can be derived:
dt
z (0 + z U ) - x ( t ) - K 1 - x ( t ) = °
The O D E is separable resulting in (equation 5-2):
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(5-1)
r
jx(u)du
^x(t)-eQ
dt
(5-2)
1
| x( u)du
e°
This equation does not yield any steady state response. Solving equation 5-2 for an abso­
lute sin-function yields the following plot (Figure 5-14):
Transient Simulation - Auditory AGC Approximation
.2
1
0.8
- - 'Input
0.6
AGC1
0.4
0.2
0
0
1
2
3
4
6
5
7
8
9
10
Time [s]
Figure 5-14: Transient simulation results for equation 5-2 solved for |sin|.
Figure 5-14 shows at very low frequencies behavior sim ilar to an A GC im plem entation.
As previously stated, the time scale is determ ined by the assum ption made that the low
pass filter in the A GC loop can be replaced with an integrator. Certain characteristics are
176
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m issing using this approach: Steady-state response and com pression over time. Hence,
equation 5-2 only provides some insight into the dynamic response o f a single stage audi­
tory AGC. In general, the onset behavior o f the AGC is dependent on the interaction o f
exponential functions. First, the initial response to an input waveform results in high gain.
O ver time, the gain is low ered and is m oving towards zero. This on-set behavior can be
observed with the full m odel/circuit im plantation that is using a low-pass filter rather than
an integrator in the feedback loop. Hence, the m athem atical approach can help to under­
stand some o f the system dynam ics originating out o f the dual AGC.
Back to circuitry, Figure 5-15 shows the transient sim ulation results based on the input
received from the envelope detector o f the previous section. A fter 50ms, the periodic in­
put signal is com pressed down. A close inspection o f the w aveform shows also the non­
linear treatment o f the input slope. The rising edges o f the w aveform are sharper than the
falling edges. This is an im portant behavior that translates into the spike encoding.
177
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Channel Simulation: Dual AGC
1.2
X
10
0.6
0.4
0.2
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Time [s]
Figure 5-15: Transient simulation o f the dual AGC.
Figure 5-16 shows the M onte Carlo result o f the channel simulation at the output o f the
dual AGC. A gain, the input into the system was a lu A differential current pulse in order
to provide m eaningful data. The output o f the dual AGC represents the overall channel
deviation with respect to gain and DC offsets from previous stages. The m ean value o f
the dual AGC onset response is 2.69uA with a large standard deviation o f 345nA at the
given input amplitude. The distribution in Figure 5-16 is not sym m etric and has a tail to-
178
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w ards higher output amplitudes. Using a three sigma assumption, the output amplitude
can change from 1.65uA to 3.7uA, w hich corresponds to ±39% am plitude variation.
Monte Carlo Channel Simulation: Dual AGC Output Current
I .
Differential O u tp u t [A]
4
x 10
•6
Figure 5-16: M onte Carlo channel simulation at dual AGC, with output current mismatch.
Figure 5-17 shows the DC mism atch at the output o f the dual A GC stage. The m ean
value is around 3nA with a standard deviation o f 35nA, w hich puts the DC offset into a
range o f +/- lOOnA.
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Monte Carlo Channel Simulation: Dual AGC DC
DC [A]
* to'7
Figure 5-17: M onte Carlo channel simulation at dual AGC, DC mismatch.
Figure 5-18 shows the com mon m ode at the output o f the dual AGC. The m ean value
In A w ith a standard deviation o f only 3nA.
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Monte Carlo Channel Simulation: Dual AGC Common Mode
-
8
..III
-
6
-
4
2
0
2
Common M ode [A]
4
6
8
x 10
Figure 5-18: M onte Carlo channel simulation at dual AGC, common mode mismatch.
Figure 5-19 depicts this am plitude variation o f ±39% for the input w aveform used in the
M onte Carlo Run (differential current pulse 2uA peak-to-peak). H ere a very im portant
feature o f the dual AGC becom es clear: The onset is alw ays sharp and is less prone to
overall gain variations (due to the DC com ponents added by the m ism atch behavior o f the
different circuit blocks resulting in the ±39% am plitude variation). This behavior w ill be
reflected in the spike encoding. The M onte Carlo sim ulation o f the spike generator will
highlight the system im pact o f this gain change variation. As a note, the current glitches
around 2.7ms and 4.5ms correspond to the generated spikes. This charge injection effect
was addressed in the spike generator. The spike generator was built in such a way, that
positive feedback is provided, once a spike is generated. This adds im m unity and stable
181
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spike generation to any noise in the system. A dditionally, this graph highlights one major
m otivation o f using a full w ave rectifier at the output o f the dual A G C stage: There is lit­
tle current below zero and therefore, the signal riding on a DC offset is still put into the
spiking neuron.
Hk
0
0
1
3
2
4
5
Time [ms]
Figure 5-19: Transient response with M onte Carlo variations at the dual AGC output.
The output am plitude variation in Figure 5-19 is shown in more detail in Figure 5-20.
182
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h om in a l Am plitude
Figure 5-20: Detail gain variation.
Figure 5-21 displays the DC offset treatm ent o f the input signal as a histogram. D ue to
the full-wave rectification process, the distribution is no longer Gaussian. The distribu­
tion spans roughly -lO nA up to lOOnA.
183
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Monte Carlo Channel Simulation: Spiking Neuron DC
-I
I I
tt
III u
J
1
DC (A]
5
■■
6
; ■.
7
tt
x 10"*
Figure 5-21: M onte Carlo channel simulation at the input o f the spiking neuron with DC mismatch.
The output o f the dual A GC represents the end o f the analog channel and the analog sig­
nal processing and enters a m ixed-signal domain. A fter the dual AGC, the signal is spike
encoded. Throughout the M onte Carlo runs, the channel never failed w ith respect to over­
large DC shifts or gain errors. Hence, the sizing o f the topology is in the right range.
H igher precision can be achieved by using m ore layout area, but that would limit the total
num ber o f channels to be im plem ented on a single die. It is also im portant to note that the
gain changes at the end o f the channel reflect the changes across channels. For an audi­
tory channel used for sound source localization, the channels w ould be grouped accord­
ing to the num ber o f input m icrophones and hence enhance the correlation w ithin the sig­
naling group.
184
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5.3.4 Spiking Neuron
A spiking neuron is in general a state m achine that encodes input amplitudes using a dy­
nam ic threshold m echanism . The choice o f spiking neuron w as the so-called SRMO [5]
m odel, that had for the auditory signal processing schem e for sound source localization
the best perform ance outlook. In general, there are a lot o f different im plem entations
available for spiking neurons. M any o f these im plem entations are quite small and low in
pow er consum ption [6 ]. In general, these im plem entations are hard to control w ith re­
spect to their system param eters. It seems that the overall b elief is that a spiking neuron
does not need to be accurate. Looking back to the nature m odel, this b elief is very true.
B ut nature has one m ore param eter that is not com m only available in VLSI: m assive par­
allelism. This parallelism leads to spike synchronization and at the end to our am azing
ability to localize sounds. Since chip area is limited, the lack o f spiking neurons has to be
counterbalanced w ith accuracy. Hence, the SRMO im plem entation was the choice. The
V LSI im plem entation o f the SRMO has three independent param eters:
w here
Il t h
is the low er threshold,
o f the refractory generator.
I lth
Iu t h
is the upper threshold and
Trefra
Ilth, Iuth
is the com parison current for the input signal. O nce an
control the tem poral spike behavior. A fter a spike is generated,
against the fixed
is low er than
Ir e f r a ,
Ir e f r a ,
Trefra,
is the time constant
input signal goes over this threshold, a spike is generated. The com bination o f
Trefra
and
which is bounded to
Trcfra
Iu t h
Iu th
and
is com pared
in its exponential decay. As long
Iu t h
no further spike can be produced and m arks the absolute refractory
timeout. The spike generation process is illustrated in the state diagram o f Figure 5-22.
185
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Irefra< Iuth
R EFR A
iR E F R A ^IU T H
'U T H
Vspk=1
Vspk=0
Vspk=0
R E F R A " '' UTH
R E F R A ^ IU T H
refra
'uth
Figure 5-22: State diagram o f the SRMO spike generation.
The occurring spike w idth is in the order o f m icroseconds. A fter the spike occurs,
Irefra
is adjusted accordingly and forces the spike to go low again. The system im plem entation
o f the SRMO m odel in current m ode is outlined in Figure 5-23.
I
Figure 5-23: SN system diagram.
186
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The spiking neuron consists o f tw o m ain m odules: a current m ode threshold crosser
(CTC) and a refractory signal generator (RSG). The CTC compares the incom ing signal
from the DAGC to a preset reference level, w hich is in continuous operation dynam ically
adjusted by the RSG. The RSG can be seen as a function generator, providing an expo­
nential threshold decay curve after a spike w as generated by the CTC. The im plem enta­
tion o f the CTC for the spike generation is show n in Figure 5-24.
out
DAGC
REFRA
Q
'" O
Figure 5-24: Current comparator.
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The current com parator is a level-sensing circuit w ith high gain feedback via the output
inverter configuration. The input into this topology is a resistive divider form ed by an
nm os/pm os pair. The DC value o f this configuration in conjunction w ith the inverter
feedback is close to VDD/2. As long the sum o f
Ilth
and
Ir e fr a
is larger than
Id a g c ,
the
output V0ut stays close to VDD. In order to sharpen the output o f this circuit, an addi­
tional inverter can be used. This configuration is due to its active feedback topology very
robust against m ism atch variation. O nce the threshold is crossed, the high gain feedback
assures a sharp rising edge at the output. The time jitter o f the generated spike is « l u s .
Figure 5-23 displays the param eters that determ ine the system behavior:
Iurn
and
Ilth
the preset threshold currents, w hich are partially controlling the spike generation.
(lower threshold) is com pared against the input signal
the dynam ically adjusted current out o f the RSG.
Idag c,
Iu t h
are
Ilth
om itting the dependency o f
is an upper threshold. Once the
signal o f the RSG is above this level, the system goes into a refractory tim eout phase.
Iu t h
is thus controlling the tem poral behavior o f the SN in conjunction with Trefra. 'trefra is
setting the time constant for the dynam ic threshold decay. Figure 5-25 shows a zoom ed
version o f the spike generation process. The spike width is in the range o f <10us. The
positive slew rate o f the spike is around 5V/us and is determined by the positive feedback
o f the CTC after a threshold is crossed.
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Channel Simulation: Spike
6.7us
Slew rate ~ 5V/us
a :
Q
.
50
>
6.54
6.55
6.56
6.57
6.58
6.59
Time [s]
6.6
x 10
-3
Figure 5-25: Spike generation.
The CTC behavior is straightforward. Once a current crosses a certain threshold in the
CTC, a spike is generated. R egarding the RSG, the system is again displayed as a further
sub-module to highlight the system behavior, shown in Figure 5-26.
189
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TFF
sp k
^refra
Figure 5-26: Refractory signal generator.
Spikes generated by the CTC are first frequency divided by an ordinary T-flip-flop (TFF).
Positive slopes o f V spk set the output high or low. This is necessary to drive a current
pulse generator (CPG) on only positive edges o f incom ing spikes. The CPG is hence
sw itched on or off. Figure 5-27 gives an overview o f the current pulse generation. The
w aveform corresponds to the output after the TFF. Each edge m arks an occurring spike.
190
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Channel Simulation: Refra Pulse Generation Transient Response
-6
LO
2.5 -
0.5-
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.0?
o.i
Time [s]
Figure 5-27: Transient response o f the refractory pulse generator.
Before the current pulse goes into the input o f the CM I, it is, as in the m ain channel, buff­
ered by a FBCM element. The output o f the CPG is actually inserted at two points around
the CM I (Figure 5-26), input and output, hence form ing a high-pass filter response with a
tim e constant o f xrefra. Figure 5-28 shows the high-pass filtered current pulse.
191
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Channel Simulation: Bidirectonal Refra Transient Response
x 10
<
3
Oi
i—
0.01
0.02
0.03
1.04
0.05
0.06
0.07
0.08
0.09
0.1
Time [s]
Figure 5-28: Transient response o f the high-pass filtered current pulse.
The sharp edges o f the current pulse are differentiated and provide the signal shape
needed for the SN. Since a differentiated response is positive or negative depending on
the slope o f the incom ing signal, a FW R is inserted. A gain, because o f the im pedance
switching, a FBC M is inserted between the CM I and FWR. The output o f the RSG feeds
back to the CTC to dynam ically adjust the thresholds. Figure 5-29 shows the output sig­
nal from the RSG system block with two threshold adjustm ents triggered by two spikes.
The signal Iout o f this block feeds back continuously into the CTC elem ent and adjusts the
threshold dynam ically as a function o f the spike generation process.
192
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Channel Simulation: Refra Transient Response
3.5
x 10
3
2.5
2
3
O
1.5
1
0.5
0,
0
0.01
0.03
0.02
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Time [s]
Figure 5-29: RSG transient response.
The CTC elem ent is robust against m ism atch variations. The spike jitter is m ainly de­
pendent on the variations o f its input signals, nam ely
Idagc
and
I r efr a - I refra
has large
signal responses and the sharp rise tim es lim it the im pact o f m ism atch on the spike jitter.
From previous sections,
Idagc
has an am plitude variation o f ±39% (referred to the nom i­
nal value). The output o f the dual AGC w ill determ ine the spike jitter.
193
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Figure 5-30 is very likely the m ost im portant figure in this study. It puts numbers on the
spike jitte r over the process and m ism atch variation across the auditory nerve channel to
the spike encoding. The dual A G C produced output current changes o f ±39% (referring
to the nominal output current). F or a lu A differential input current pulse into the channel
(the rectifier is the first stage), the spike jitter across random channels is 4us (one sigma).
30-
25-
20
Monte Carlo Channel Simulation: Spike Jitter
.................
-
T im e (sj
x
10'5
Figure 5-30: M onte Carlo channel simulation at spike output: Spike jitter.
A o=4us is quite a good result. Figure 5-31 w as previously shown. The current jitte r at
2.7ms and 4.5ms indicates the spike generation process. A careful look on the slope re­
veals that the spike jitte r w ill be a function o f input am plitude and threshold level.
194
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3
<
2
1
0
Time [ms]
Figure 5-31: Transient response with Monte Carlo variations at the spiking neuron input.
In fact, lowering the differential input am plitude into the channel from lu A dow n to
125nA (-18dB) and keeping the threshold level
Ilth
fixed, the spike jitter goes up to 54us.
Table 5-2 provides an overview over input am plitude and spike jitter.
Input A m plitude
125nA
250nA
Standard D eviation Spike Jitter
54ps
11
pis
500nA
6
ps
lOOOnA
4ps
Table 5-2: Spike jitter from Monte Carlo run versus different input amplitudes.
195
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54us spike jitter instantly raises the question i f the suggested system outline will produce
successful spike generation suitable for sound source localization. The answer to that can
be ‘y e s’ or ‘n o ’ and goes back to layout and system outline. The results displayed show
the spike behavior o f random channels, indicating that the devices and system blocks are
m atched w ithin the channel but do not correlate at all from channel to channel. In order to
perform spike generation that is highly correlated across channels, the channel circuitry
o f the sam e frequency band but from different sensors have to be grouped, w hich w ill
m ake the overall layout challenging. N evertheless, this is a necessary step to assure a cor­
relation w ithin channel pairs for a two m icrophone application or a quad channel group­
ing for a four m icrophone application. D oing so w ill introduce a correlation betw een the
spike generation o f m atched channels o f 90% and higher. U sing a correlation betw een
m atched groups w ithin a channel o f 90% , the spike groups will co-vary resulting in a
spike jitter w ithin the group o f 16us for input am plitudes o f 125nA. Figure 5-32 shows
the cross channel spike jitte r as a function o f channel correlation.
196
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Spike Jitter 125n A current pulse vs cc
60E-6
50E-6
40E-6
30E-6
o.
20E-6
10E-6
OOOE+O
0.0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Correlation Coefficient cc
Figure 5-32: Cross channel spike jitter vs cc.
Figure 5-33 highlights another interesting effect. The first spike generation is m ainly de­
term ined by the onset signal from the dual A G C, whereas the secondary spike generation
is m ainly driven by the amplitude change o f the dual AGC. This behavior is o f less con­
cern, since spike generation and its synchronization m ainly come from onset responses o f
the dual AGC.
197
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>
4*4
Oh
C/3 7
2
>
1
0
0
1
2
3
Time
4
[m
5
s]
Figure 5-33: Transient response: Primary and secondary spike generation.
5.3.5 Further Spike Processing
A single spike marks a time point. For sound source localization, at least another spike
event is needed to determine the azim uth o f an incoming sound source. Since spiking en­
coding is at this point purely kept in the analog domain, the value has to be captured to an
absolute tim e base. This point is the transition from the analog w orld into the digital
world. To determ ine bearing, the digital circuitry would have to perform follow ing task:
Once a spike on one channel is received, a digital counter is started. I f a spike on the
other channel is received before the counter times out, a bearing event is detected and
198
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quantized. The time base for this counter determines the resolution o f the system and is
also dependent on the m icrophone spacing o f the system. In general, our system im ple­
m entations used a lu s tim ing resolution for best accuracy for sensor spacing betw een one
to ten inches.
There are two methods for how the spike inform ation can be processed: Im plem enting a
pitch-bearing m odule on chip or transm itting the spike inform ation to another chip. The
second m ethod is used in the existing PCB implementation, w here the spike inform ation
is read into a FPGA perform ing the pitch and bearing encoding. F or an on-chip solution,
an asynchronous approach is a good choice since the overall spike data rate is quiet low
and m ost o f the time, the pitch-bearing m odule is idle. Only w hen spikes are occurring, a
clock w ith a know n time base (e.g. lOus) has to be switched through in order to drive the
encoding in the pitch-bearing m odule.
Further spike data processing is beyond the scope o f this study. In general, the spike
events are translated into bearing events. These events are grouped and a spike detection
m odule puts the first layer o f decoding on the spike information. The spike space is then
further processed w ith a classification program, in order to distinguish different sound
sources. Further inform ation on this topic can be found [3],
199
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5.4 AN System Parameters
5.4.1 Statistical Variations within the Auditory Nerve Channel
This section mainly sum m aries the statistical findings with respect to gain, DC and com ­
m on mode variations. Figure 5-34 outlines the auditory nerve channel. The arrows indi­
cate probing points. These probing points are summarized in Table 5-3.
Envelope
Taul
AGC1
AGC2
AGC3
SN
Tau3
Figure 5-34: System map to acquired Monte Carlo results.
Table 5-3 describes the variation w ithin a channel for a current pulse o f luA . In general,
the common m ode is very w ell behaved throughout the system. The DC offset is the
weak point in the system. B y observing this table, one can note that the DC offset is re-
200
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duced by a factor o f tw o at the output o f the dual AGC. The reason for that is the low er
K2 system param eter, w hich is scaling dow n the output am plitude and hence decreasing
the DC offset. The SN *) entry indicates a non-G aussian distribution.
Peak-to-Peak [A]
Mean
Stdev
CM [A]
DC [A]
Stdev
Mean
Stdev
n
-48n
4n
n
16n
l.llu
4n
3n
Mean
Rectifier
2.05u
1
Envelope
2.94u
15n
AGC1
4.28u
145n
3n
41n
-96n
Taul
1.31u
29n
13n
60n
1 0 2
AGC2
5.96u
207n
4n
60n
1.18u
4n
AGC3
2.69u
360n
3n
35n
In
3n
Tau3
143n
13n
-2 n
54n
1.16u
4n
SN *)
2.74u
343n
14n
15n
-2 n
In
REFRA
3.05u
n
13n
7n
-3 Op
In
2 0
-300p
2
6
.
u
8
2
n
n
Table 5-3: M onte Carlo results of an excited channel, input amplitude luA .
In order to provide a reference, Table 5-4 com pares the DC offset o f an excited channel
(lu A current pulse) with a resting channel (no current goes into the system).
201
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DC [A],
DC [A],
for Ij„=luA
for Iin=0uA
Mean
Rectifier
Envelope
-300p
Stdev
Mean
n
-300p
6
Stdev
6
n
n
16n
2
n
16n
AGC1
3n
41n
4n
41n
Taul
13n
60n
13n
60n
AGC2
4n
60n
4n
60n
AGC3
3n
35n
3n
35n
Tau3
-2 n
54n
-2 n
54n
SN *)
14n
15n
31n
2 2
2
n
Table 5-4: DC M onte Carlo results comparing excited/resting channel.
The DC points o f the excited and resting channel agree extrem ely well. The DC state at
the SN system block m arks a potential low er bound for the lowest spike generation popu­
lation. Putting a spike threshold below lOOnA w ill trigger a channel correlated spike
event. These spike events are over time random due to tim ing inaccuracies (Figure 5-33).
The further the spike threshold is lowered, the m ore spike events are produced. Since the
DC offset value is static and not correlated to the input, there is potential for com pensa-
202
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tion schemes, e.g., applying static DC current sinks and sources to accom m odate the DC
offsets.
Figure 5-35 shows a three population threshold encoding scheme. The dashed horizontal
lines m ark the three threshold levels, whereas the solid horizontal line m arks the expected
m axim um DC level o f the system due to m ism atch. The choice o f threshold levels is not
random . The OdB point o f the system is chosen to be lOnA input level. This zero DC
point refers to a point where onset-response and steady-state response begin to differ sig­
nificantly. Population threshold level 1 is set about 25% betw een the OdB point and the
upper level o f the steady state response. Population threshold level 2 is set about 10%
above the steady state response whereas population threshold level 3 is set at approxi­
m ately 65% o f the saturated onset response. These threshold settings assure a m eaningful
encoding o f the dynam ic range o f the spiking neurons. Population 1 will fire at certain
input levels or, in the case o f a DC shift, it will fire uncorrelated once in a while. Popula­
tion
2
w ill only fire if there was onset response and will not fire on steady state response.
Population 3 responds to highly energetic events.
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Onset Response Dual AGC - Threshold Encoding
P o p u la tio n 3 T hreshold
<
U
0
<
75
s
Q
a
■e
s
...
P o p u la tio n 2 T h resh o ld
1
3
DC
... !
P o p u la tio n 1
10
-7
to-0
Input A m plitude [A]
Figure 5-35: Spike thresholds.
A DC offset higher than population 1 does not necessarily m ake this population useless.
A more or less random spike is generated. D epending how the spike rate is set, a spike
event can occur every 10ms or slower. A signal event producing an onset response in the
dual A GC w ill create a spike in population 1 by crossing its threshold. H ence, spike syn­
chronization based on an event is still possible.
Figure 5-36 shows a tuning graph for
Iuth,
which sets the absolute refractory timeout.
Depending on the desired spike rate behavior,
Iuth
has to be set accordingly. For a time
204
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constant o f 2.5ms, every 10ms another spike event is produced, assum ing an ILth o f OnA
and no D C offset.
_x 10' Refractory Timeout Thresholds UTH for different Spike Rates
1.5
UTH4=1.35uA
UTH3=1.22uA
TAU4=10.0ms
a.
0.5
TAU2=2.5ms
TAU1=1.0ms
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
0.01
Tim e [s]
Refractory Timeout =1.0ms
Figure 5-36: Refractory timeout thresholds UTH.
The m axim um spike rate is fixed to 1 kH z due to the refractory tim e-out setting. In gen­
eral, Iu th can be easily determined, using equation 5 -3
REF R A '
I u th
I m a x
' exP
TAU ,
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(5 -3 )
W here
Im a x
is an arbitrary current, REFR A is the tim eout setting and TAU is the decay
coefficient setting the overall spike behavior.
Im a x
should be set high in order to avoid
m ism atch im pacts and in order to achieve fast slew rates.
5.5
System Aspects
In this section, a b rief overview o f system aspects is provided. We consider bias distribu­
tion, pow er budget and DC com pensation schemes.
5.5.1 Bias distribution
A nother lesson was learned from a fabricated 64-channel auditory nerve design. The bias
distribution was im plem ented w ith gm-current sources (Figure 5-37). One reference volt­
age Vg w as used for the w hole chip to set the gm o f the bias current sources producing
reference/bias currents I R , . I R , ...
206
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V
.
s,
• • •
|<-»
S m @ X2
S m @ X1
S m @X 3
Distance x
Figure 5-37: gm current source.
The pmos devices in Figure 5-37 are distributed across the chip and hence not matched.
Sharing the same bias voltage Vg will result in very different reference currents. Figure
5-38 shows the m easurem ent across all 64 channels o f the fabricated chip.
207
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V2I Bias Distribution Across Channels
120E-9
115E-9
110E-9
~
105E-9
£
£
O
100E-9
£
95E-9
c
5
90E-9
85E-9
80E-9
1 4
7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Channel
Figure 5-38: M easured bias distribution across 64 channels of an earlier design.
For this particular m easurem ent o f one chip, the bias changed w ithin a w indow o f 30nA.
The targeted m ean value w as lOOnA. H ence, the bias deviated +/- 15% for this particular
chip. In any case, gm-current sources are in general a bad design choice to im plem ent cur­
rent m ode systems. A fully differential design can buffer these deviations, but absolute
reference circuits such as the spiking neuron cannot tolerate such current variations.
In order to im plem ent a successful current m ode auditory nerve chip, attention has to be
paid to the bias distribution. Figure 5-39 illustrates a bias distribution scheme. The cur­
rent settings are provided externally into a m aster current bank. F or the current m ode
auditory nerve chip, a minimum o f 15 bias settings is needed. These 15 current bias set-
208
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tings have to be distributed across all channels (N num ber o f channels) and each current
bias line has to be routed individually. A ssum ing a system w ith N =64 channels, the m as­
ter current bank w ould have to distributed 12x64=768 bias lines to the local bias distrib­
uting blocks (Biasi ... BiasN in Figure 5-39). In order to reduce the num ber o f bias lines,
the local bias distribution blocks can provide the bias current for m ultiple blocks, e.g. for
channels that form a bearing pair or bearing quads. A ssum ing that four channels are
grouped, the total num ber o f bias lines w ould be 192. This bias distributing scheme is
quite expensive but necessary to assure system perform ance. Since only DC inform ation
is distributed, the wire routing is quite flexible but a voltage drop along the bias lines has
to be taken into account.
BiasN
Current M ode A N Channel N
•
•
•
Bias3
Bias2
Bias,
y~ BiasN
•
•
•
yyy-
•
•
•
Current M ode A N Channel 3
Bias3
Current Mode AN Channel 2
Bias2
Current M ode A N Channel 1
f"
¥■
Bias,
8 -N / '
' 7>N
Master Current Bank
f
,
External Setting or DAC
Figure 5-39: Bias distribution.
209
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Figure 5-40 shows a typical topology for a current bank. I B is a current bias setting
w hich is externally provided or set internally w ith a digital-to-analog converter (DAC).
This current is then replicated b y a pm os current mirror (M 0 to M n). The m atched bias
currents 7^ to 7^ are then routed to the local bias distribution blocks. Figure 5-40 has to
be replicated for each current bias setting.
M,
Figure 5-40: Current Bank
In order to assure precision, the input bias current I B should be large and then scaled
down by the current m irror Mo to M N- In order to scale the bias current down, M 0 has to
210
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
be a factor o f N larger than the M i to M n - In general, this current bank is fairly large in
area and threshold variations across the devices will accum ulate w ith distance. In order to
im prove m atching betw een the devices, the multiple transistors o f Mo w ould be evenly
distributed am ong the rest o f the current m irror transistors M] to M n (interdigitate) and
hence average out any threshold variations or other gradients.
5.5.2 Power Budget
So far many circuits and sub-m odules w ere discussed. Pow er consum ption to this point
was not so m uch o f a concern. In order to realize a m assively parallel system in reality,
the pow er budget m ust be m anageable.
Table 5-5 breaks dow n the system outline o f Figure 5-2 into the individual blocks w ith its
corresponding current consumption. The current consum ption calculation is based on a
three population spike encoding model.
211
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Current
DC Current
Building Block
Occurrence
Consumption
Consumption
HWR
< lu A
1
< lu
FWR
< lu A
1
< lu
CMI
90uA
5
45 OuA
FBCM
70uA
1
70uA
MULT
400uA
2
800uA
CTC
30uA
3
90uA
RSG
240uA
3
720uA
Total Current Consumption
2130uA
Table 5-5: Power budget for single three population auditory nerve implementation.
A full auditory nerve channel w ith three populations consum es around 2.1mA, using a
typical bias current o f lOuA per building block. A n anticipated 64-channel configuration
w ould thus consume 136mA. W ith a pow er supply o f 5V, this adds up to 700m W atts o f
pow er dissipation. In general, the pow er supply can be considerably lowered. Any block
mentioned in this study can operate at 3.3V using a 1.5um technology. M igrating into
processes with lower thresholds can low er the pow er supply schem e significantly.
212
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5.5.3 DC Offset Correction
As discussed in previous sections, the DC offset w ithin the system is driving the spike
jitter. Table 5-4 showed that the DC offset is not correlated to an excited channel. A po­
tential DC offset correction m odule could be im plem ented like this: A low precision (e.g.
5bit) D AC im plem enting current sources and sinks can be used to correct the DC offset
in the last stage o f the dual AGC (m ost sensitive to DC offset). The CTC (current thresh­
old com parator) can be used to m easure the success o f the DC offset correction. W ith no
input applied to the channel, the output o f the dual A GC is com pared against a OuA
threshold set in the CTC. As long the output o f the CTC does not change its direction, the
bits in the DAC are swept through. O nce a transition is detected, an optimal offset DC
correction setting is found and the value is stored in a local register.
5.6 Design of Experiment (DOE)
The non-linear system behavior m akes it difficult to predict how certain m ism atch p a­
rameters will im pact the spike perform ance. In order to investigate the DC offset problem ,
a VerilogA model was developed that im plem ents an ideal version o f the auditory nerve
model. Between system building blocks, a DC offset was inserted to model the non-ideal
DC behavior. Figure 5-41 shows the D C-O ffset injection points.
213
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LPF
DAGC1
DAGC2 DAGC3
REC
TAU1
TAU3
Figure 5-41: DC offset injection points with variable mapping.
A total o f seven variables have to be sw ept across the individual DC three sigma ranges.
In order to perform an effect screening, a statistical m ethod called “D esign o f Experi­
m ent” (DOE) was used [7], This m ethod is non-exhaustive and allows w ith the statistical
analysis software package JM P to screen the individual im pact o f variables.
V ia M onte Carlo runs on the actual circuit schem atics, the three sigma points o f the DC
offset were determined. The input pulse into the system was lu A differential. All other
system param eters are set accordingly to the sim ulation setup in Chapter 5.3. Only the
threshold current for the CTC was doubled in order to im prove the spike jitte r screening
that is mainly a function o f the am plitude variation o f the dual A GC output (Section
214
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5.3.4). Table 5-6 provides an overview o f the variable set used for the DOE. The minnom -m ax boundaries are set w ithin a three sigma limit.
Variable
3(3Min
Nom
3dMax
[nA]
[nA]
[nA]
Variable Description
Name
REC
R ectifier output DC offset
-18
0
18
LPF
Envelope detector DC offset
-26
0
26
-32
0
32
-26
0
26
-26
0
26
-26
0
26
-32
0
32
O utput DC offset current mode m ul­
DAGC1
tiplier o f the first dual A GC stage
1st order low-pass filter DC output
TAU1
offset in first dual A GC loop
1
st order interm ediate low-pass filter
DAGC2
betw een the two A GC stages
1st order low-pass filter DC output
TAU3
offset in second dual A G C loop
O utput DC offset current m ode m ul­
DAGC3
tiplier o f the first dual A GC stage
Table 5-6: DOE variables.
A D OE with 256 runs was designed using a response surface m ethod (RSM). The RSM
analysis allows finding a second order prediction to the desired output response by using
215
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
a 2nd order factorial effect screening process across the variable space. The RSM m odel­
ing is m ost advantageous w hen local m inim a or m axim a have to be predicted.
The D O E runs provide absolute spike times. Post processing converts these absolute
spike tim es to spike jitter, w hich is the difference betw een current spike-tim e o f a single
run m inus the average spike-tim e o f the overall DOE run. The experim ent setup plus the
spike jitte r is re-im ported into JM P for statistical analysis.
Figure 5-42 shows the curve fitting or correlation betw een actual runs versus predicted
runs. Since the variable space is only seven variables, the R 2 is nearly one and thus we
can be confident that JM P will provide a good prediction o f the system behavior im ­
pacted by DC offsets.
10 -
0-
'5
o.
- 10-
-15
-15
-10
Spike Jitter [us] Predicted PO.OOOO RSq=1.00 RMSE=0.1236
F igure 5-42: JM P predicted plot.
216
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Figure 5-43 displays the residual o f predicted versus actual run. The residual is «
and random ly distributed (no clustering). Table 5-7 sum m arizes the m odel fitting.
R asid u al by P re d ic te d Plot
0.3-
'55 0.2
0.1
•*
■
. M
■0 . 1 -
Q.
CO -0.2
-15
-10
Spike Jitter [us] Predicted
Figure 5-43: Spike jitter residual.
| Summary of Fit
R-square is the portion of variation attributed to the model, between 0 anr
1. Root Mean Squared Error "RMSE" estim ates the standard deviation of
residual.
RSquare
0.999691
RSquare Adj
0.999642
Root Mean Square Error
0.123614
Mean of R esponse
0.004297
Observations (or Sum W gts)
256
Table 5-7: Summary o f fit.
217
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Figure 5-44 shows the prediction profiler o f JMP. W ith this tool, the interaction o f swept
variables to the spike jitte r (SPKJIT) can be screened. The vertical axis is the spike jitter
in microseconds. The horizontal axis lists the individual variables w ith their sweep range
(three sigma) in nanoam ps.
P re d ic tio n P rofiler
T he c h a n g e in predicted r e s p o n s e a s y o u v a ry o n e f a c to r a t a tim e, holding
the oth er f a c to rs at their cu rre n t v a lu e s . Click in th e g raph to c h a n g e th e
current v a lu e s of th e fa c to rs .
12.7027 ‘ -
t12.61061
± 0.0921
-13.3 *
co
-18
26
REC
LPF
cCMo
co
-32
26
DAGC1
TAU1
CM
-26
DAGC2
CO
CM
26
TAU3
co
CM
-32
DAGC3
Figure 5-44: JM P prediction profiler.
The prediction profiler gives insight into the non-linear system behavior across the vari­
able space. The slope o f the individual variables is an indicator how im portant this vari­
able is to have an im pact on the spike jitter output (horizontal axis). V ery interestingly,
only the last stage o f the dual A GC actually drives the spike jitter. TAU3 is the D C offset
o f the low-pass filter in the feedback o f loop o f the last dual AGC stage, and D A G C 3 is
the DC offset o f the current m ode multiplier.
This is a very im portant insight into the system behavior, since the result o f this analysis
suggests that DC offset correction w ith the proposed system outline is actually only nec-
218
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essary at the end o f the auditory nerve channel. This makes an overall system DC offset
correction schem e m uch m ore feasible, since the offset correction does not have to be
perform ed at each system block. The prediction profiler can be used to sim ulate this con­
dition by setting the DC offset at the output o f the dual A GC (DAGC3) to zero. The
overall spike jitter is reduced by a factor o f three to +/- 4us. This m ight open the w ay for
an integrated DC offset correction scheme using the current threshold com parator o f the
CTC as m easurem ent instrum ent for DC offsets, as it was described in C hapter 5.5.3.
5.7 Summary
This chapter provided a detailed insight o f the system design o f the current mode auditory
nerve chip. Basic building blocks and higher order building blocks such as the spiking
neurons w ere discussed. The m ost im portant result o f this chapter is the prediction o f the
spike jitter under m ism atch conditions. A M onte Carlo sim ulation on the current m ode
auditory nerve channel showed prom ising spike perform ance, but also show ed potential
limitations regarding spike jitter due to the large amplitude variation at the output o f the
dual AGC. A DOE was perform ed on an idealized VerilogA [8 ] m odel, investigating the
spike jitter perform ance due to DC offsets inside the system. Surprisingly, only the last
stage o f the auditory nerve channel is driving the spike jitter and hence a D C offset cor­
rection scheme can be easily im plem ented. In general, the DC offset is in w ithin accept­
able limits throughout the process and m ism atch comers.
219
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The overall design yield o f the parallel system can be essentially 100% regarding w ork­
ing channels. The application yield w ill be determ ined how the spike jitter is distributed
on a full system. W ith e.g. spike jitters up to 125us, such a chip could be used for a sen­
sor spacing o f six foot whereas a system w ith m axim um spike jitte r o f lOus can be used
for an application w ith eight inch sensor spacing.
220
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5.8
References for Chapter 6
[1]
A. H ubbard, "A traveling-w ave am plifier m odel o f the cochlea," Science, vol. 256,
pp.
[2]
6 8
- 7 1 , 1993.
Z. Yang, "Low-frequency analog integrated circuit design using current-mode
techniques," in Electrical E ngineering (unpublished doctoral dissertation). Bos­
ton: Boston University, 2004, pp. 235.
[3]
G. S. D eligeorges, "Auditory Biom im etics: A m odeling study o f temporal proc­
essing in the auditory system," in Biom edical E ngineering (unpublished doctoral
dissertation). Boston: Boston U niversity, 2004.
[4]
J. E. Ohlson, "Exact dynam ics o f automatic gain control," IE E E Transactions on
com m unications, pp. 72 - 74, 1974.
[5]
W . G erstner and M. K. Kistler, Spiking N euron M odels, 1st ed. Cambridge, UK:
Cam bridge University Press, 2002.
[6 ]
G. Indiveri, E. Chicca, and R. D ouglas, "A V LSI array o f low -pow er spiking neu­
rons and bistable synapses with spike-tim ing dependent plasticity," IEEE transac­
tions on neural networks, vol. 17, pp.
2 1 1
-
2 2 1
, 2006.
[7]
JM P, "w w w .im p.com ;’ 2006.
[8 ]
EDA, "Verilog-A language reference manual," O pen V erilog International, 1996.
221
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6 Conclusion
This study provided an overall insight on how to construct an analog auditory nerve chip
suitable for sound source localization. Chapter 1 provided a b rie f insight into the biologi­
cal background and C hapter 2 w orked out the challenges o f sound source localization in
general. C hapter 3 introduced current m ode technology and show ed some examples o f
basic current m ode processing blocks. Also, several novel circuits w ere introduced in this
chapter as w ell chip data o f subm itted designs was presented. C hapter 4 described the
challenges o f im plem enting a m assively parallel analog signal processing system. Some
basic exam ples w ere provided and main circuit blocks for the auditory nerve scheme
w ere discussed, regarding their robustness to mism atch. D esign assumptions w ere vali­
dated w ith test results o f subm itted designs. B ased on results from Chapter 4, the overall
current m ode auditory nerve circuit im plem entation was introduced in Chapter 5. The
overall auditory nerve perform ance was studied under m ism atch conditions, and per­
form ance m easures such as spike jitter were also studied to understand the im pact o f m is­
m atch.
6.1
Feasibility
The suggested current m ode im plem entation o f the current m ode auditory nerve chip is
quite feasible based on the sim ulation results o f Chapter 5. T he feasibility is based on
222
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achievable accuracy constrained by the num ber o f channels that can be im plem ented on a
single chip (area) and the available pow er budget o f less than one watt. The suggested
im plem entation according to the sizing o f the elements achieves a theoretical design yield
o f nearly 100%. This o f course does not include any yield im pacts due to m anufacturing
(e.g. defect density issues) or production yields. N eglecting any im pacts due to m anufac­
turing, the suggested analog system does not produce any un-useable channels under all
process and m ism atch variations.
6.2 Performance
The analysis o f the auditory nerve chip was focused on isolated auditory nerve channels.
For low input am plitudes (e.g., around lOOnA), the spike jitte r can reach significant lev­
els, limiting the m inimum sensor spacing or accuracy o f the system (Table 5-2). Channels
o f the same frequency band that are connected to e.g. four sensors have to be grouped in
the layout in order to m inim ize the spike jitter. This enhances the m atching w ithin this
group. As an exam ple, the input differential pair o f an OTA w ould have to be interdigitated for all four channels. H ence, the layout effort is quite significant, since this scheme
w ould have to be m aintained throughout the channel. By doing so, the matching betw een
the channels w ith the same frequency band (intra-channels) can be significantly boosted
and spike jitter can be reduced. Spike deviations betw een channels w ith different targeted
frequency bands are not o f concern.
223
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The dynam ic range o f the system is bounded by the bias current o f the current m ode
structures. Throughout this study, a bias current o f lOuA was used. Looking at isolated
blocks such as the CM I and DIFFM U LT and using a maxim um signal current o f lu A
keeps these blocks w ithin in a dynam ic range o f approxim ately 60dB w ith a THD «
1%.
This w ould indicate a m inim um processing current o f InA . The system can easily handle
input currents close to the bias current, e.g., a signal current o f 5uA causes an output cur­
rent w hich stays close to 1% THD (FBCM Element). The “output dynam ic range” is
coded by the spiking neurons covering a 25dB range (Figure 1-6), w hereas the input dy­
namic range can be 60dB.
Regarding pow er, Table 5-5 gives an overview o f the current consum ption o f a single
channel. All design assum ptions and sizing o f this w ork was based on lim ited chip area
and a pow er budget o f < 1W. U sing the num bers from Table 5-5, and one is assum ing a
system o f 64 channels pow ered by a single 5V supply, the pow er consum ption is 0.68W .
Again, this estim ate is rather pessim istic, since all circuitry can be operated at 3.3V and
low er depending on the choice o f technology. The only lim iting block w ith respect to the
voltage supply is the CM I. The integration node o f this block (gate voltage) has a high
impedance and results in a larger voltage swing. Appropriated scaling can adopt this
block to the pow er supply requirem ents. In general, the pow er supply can be quite low,
since common m ode artifacts originating e.g. out o f the pow er supply ripple is suppressed
by the full differential im plem entation.
224
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6.3 Yield, area and cost factor
The suggested im plem entation does not fail under process and m ism atch variations and
therefore a 100% design yield can be guaranteed. The design yield does not include any
process yields due to m anufacturing. R egarding quality, the design yield can be binned
into systems w ith low spike jitte r and systems with high spike jitter. D epending on the
anticipated application, the m axim um spike jitte r will set the m inim um sensor spacing
that can be used. In general, all chips should perform very w ell for a sensor spacing o f six
feet.
Table 6-1 gives an overview o f required chip area for a single auditory nerve w ith three
spike populations. The “Function” colum n specifies the realized function, w hereas the
“Sub-blocks” colum n lists the required blocks to realize this function. Sub-blocks such as
M U LT (differential m ultiplier) are self-contained blocks w hich include, e.g., FBCM ele­
ments. For the total area calculation, no layout overhead was taken into account, since the
specified area represents blocks that can be abutted together.
225
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Function
Sub-blocks
Total N um ber o f
A rea per Sub­
Total Area o f
Sub-blocks per
block [mm2]
Sub-blocks
Function
[mm2]
V2I
V2I
1
0.171
0.171
REC
REC
1
0.028
0.028
LPF
CMI
2
0.303
0.606
DAGC
M ULT
2
0.871
1.742
CMI
3
0.303
0.909
FBCM
6
0.119
0.714
CMI
3
0.303
0.909
FULLREC
4
0.047
0.187
SNTH
3
0.037
0 .1 1 2
SN3POP
Total A rea per A uditory N erve [mm2]
5.4
Table 6-1: Chip area calculation
The DAGC im plem entation takes approxim ately 49% o f the total chip area, whereas the
three population spike encoding takes 36% o f the chip area. In order to realize a 64channel system, a total area o f 344 m m 2 is needed. In general, this size o f a chip is lim­
ited by the reticle used to step die by die on the wafer. Techniques such as reticle stitch­
ing are available but are not necessary. In general, a single die can be 20 x 20 m m 2,
226
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w hich corresponds to 400 m m 2. Assum ing that the pad fram e w ould lim it the area for circuitry to 360 mm (19 x 19 m m ), enough chip area is left to realize off-chip routing and
bias distribution. Hence, w ith the proposed design, a 64-channel system is easily feasible.
In the follow ing calculation the m ask costs for fabrication are om itted. The numbers are
based on subm itted prototype runs. The cost for a 4-inch run that yields 140 designs over
ten w afers is approxim ately $20,000. H ence, the cost per design w ould be $142 per 64channel auditory nerve chip. These costs w ould be dram atically reduced under large scale
fabrication on eight inch lines. On an eight inch wafer,
6 8
designs can be fitted, yielding
680 designs over ten wafers. Assum ing that the higher cost prototype runs average out
the higher production costs o f an eight inch run, the costs p er system would go down to
$30. A ll calculations do not take fabrication yields into account.
6.4 System Remarks
The goal o f this study was to im plem ent a 64-channel auditory nerve chip. As previously
shown, this goal can be achieved. H aving the chance to realize the full system on the chip,
another strategy would be used. Rather than im plem enting a cochlear like chip and an
auditory nerve chip independently, a single integrated system com prising cochlear like
behavior and auditory nerve channels is suggested.
227
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The m otivation behind this suggestion is interconnectivity. Since both chip sets would
need 64 differential lines, a com pact system solution is hard to achieve, since the package
size has to be rather big. In general, it w ould be wise to realize a 32-channel system
(8
frequency bands w ith four channels grouped: 8x4 = 32 channels) w hich requires that all
processing be integrated. R egarding pinout and neglecting the pow er supply scheme,
each chip w ould need four analog inputs feeding into four integrated microphone pream ­
plifiers w hich then feed into the cochlear section o f the chip. The output w ould be a five
bit w ide A ER encoded digital interface (see also A ppendix C). U sing a four bit w ide se­
rial interface to set internal biases, the overall pinout w ith one pin for reset (but neglect­
ing pow er supply pins) would be only 14 and hence the package choice can be deter­
m ined by pow er consum ption rather than by pinout.
A s the analysis show ed in C hapter
6
, the spike jitter across channels under process and
m ism atch variation stays w ithin a well defined range and hence multiple chips can be
connected in parallel to cover an extended frequency range. Since the cochlear-like sec­
tion w ould be sm aller than the auditory nerve chip, an asynchronous state m achine realiz­
ing pitch and bearing could be also im plem ented on the chip and hence further decrease
system com plexity from a user perspective.
228
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6.5 Future Work
The outlined biom im etic signal processing scheme can be further extended. The current
im plem entation can be used as a signal pre-conditioner for spike encoding. The output o f
this processing scheme can be used to feed back into the input stage. This can open the
capability to a closed loop system w ith high frequency selectivity by locking into corre­
lated signal sources. D epending on the post processing scheme, frequency bands can be
assigned to certain bearing events and m ight open the w indow to acoustic m ulti-target
tracking. Since the biom im etic signal processing scheme is very prom ising, future w ork
will be invested to push this technology into the industry.
229
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Appendix A
1
Overview Chip Submission
N ame
R esult
Testchip
Chip worked. Test structures for biasing.
Experim ental test structures.
2
A synchronous Bus C ontrol­
Chip worked.
ler.
3
64 C hannel auditory nerve
Som e sections w orked but no spike output
chip V I
could be achieved. Com plexity -1 0 0 ,0 0 0
analog operated transistors plus -
2 0 ,0 0 0
digital operated transistors.
4
64 C hannel auditory nerve
Some sections worked. In general, portions
chip V 2 (shared reticle with
o f the chip could be biased to be opera­
test structures)
tional. Low dynam ic range. One big prob­
lem:
Spiking neurons w ere
oscillating.
Com plexity -1 0 0 ,0 0 0 analog operated tran­
sistors plus -
1 0 ,0 0 0
digital operated tran­
sistors.
230
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5
V oltage m ode Dual AGC
Chip worked. Voltage m ode im plem enta­
tion needed high bias conditions. O utput o f
the four dual AGC stages was not well
matched.
6
C urrent m ode full differen­
Chip worked.
tial low pass filter V I
7
C urrent m ode full differen­
Chip worked.
tial m ultiplier
8
C urrent m ode fully differen­
Chip worked. Im proved input stage over
tial low pass filter V2
version V I for im proved linearity o f the
V 2I converter.
231
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Appendix B
Circuit Symbol Reference
Description
Symbol
T
Pow er supply, e.g. V dd
G round, e.g. Gnd
-o -
Ideal voltage source
i
♦ 4>
Ideal current source
T ransconductance
♦
T
R esistor
Capacitor
PM OS, substrate connected to positive pow er supply
<
N M O S, substrate connected to ground
232
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Appendix C
Asynchronous Bus Controller
The asynchronous bus controller (A BC) was designed to provide scalability to the tar­
geted 64-channel versions o f the so-called auditory nerve chips (ANC). The scalability
aspect allows expanding the num ber o f channels and hence either the frequency range o f
the system or a sm aller bandw idth w indow per channel. The A N C has an asynchronous
digital interface based on the address event representation (A ER) [1] protocol. The chip
expands the address space by chip num ber and delivers the data w ith its origin e.g. ad­
dress to its destination. This chip design was m ainly to study feasibility and to outline the
architecture in order to provide system scalability. The system is based on an asynchro­
nous arbitration scheme. Figure C -l shows the arbiter cell [1]. This basic cell can be con­
catenated in a tree fashion to handle m ultiple requests. A n incom ing request (Ri, R 2 ) is
passed via an OR-gate into the next stage and form s hence a request (REQ). A flip-flop
(FF) is used as a decision element. D epending w hich signal cam e in first, the output o f
this flip flop will set the correct path in the steering circuit cell (SC).
233
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ACK
FF
SC
Figure C - l: Asynchronous arbiter.
The steering circuit cell is show n in Figure C-2. A returning acknow ledge signal (ACK)
(e.g. from another arbiter cell) w ill be routed to either A i or A 2 depending how the deci­
sion was evaluated in the flip flop. A returning Ai or A 2 (acknow ledge) signal is indicat­
ing that the request is granted.
234
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CK
Figure C-2: Steering circuit.
The A BC handles the incom ing asynchronous spike events. O n requests (REQ SP) from
the A NCs, the A BC is using an internal arbitration to decide w hich chip w ill be serviced
first. The w inner is selected by a chip select (CS) signal. W ith CS, the channel address
plus chip address is p u t on the bus and REQ is issued to the pitch-bearing receiving chip.
An acknowledge signal is sent back to all A N Cs connected to the ABC. Since CS is still
high, only the selected chip will be acknowledged. The REQ SP goes low, CS is released
and REQ goes down.
This chip was designed using an AM I 1.5um process. The chip was only tested using a
wire wrap setup, w hich did not allow proper termination. The tim ing behavior can be
235
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seen in Figure C-3. The tim ing cycle for a single request is around 350ns, w hich puts the
bus speed in this setup at around 3 MHz. This slow system speed is determ ined by the
slow rise and fall tim es due to the test setup. A PCB-based solution w ith proper term ina­
tion can enhance the service speed to approxim ately 10 M H z (simulation). The gate delay
o f the 1.5um process plus the 10 drivers determ ine this operation. A sm aller feature size
can boost the bus speed accordingly to higher speeds.
This chip was designed at a very early tim e o f the project. Later im plem entations m ade
this chip obsolete, since the pitch-bearing chip w as realized in an FPG A w here m ultiple
handshake interfaces can be easily im plem ented and the use o f tri-state buses is supported.
236
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Asynchronous Bus Handler: Handshake Protocol
6.0
5 .0 -----4.0
aO
>
n)
4^
REQ S P [V]
- - - REQ \V]
o
>
C S [V]
2.0
• —
N.
0.0
o
+
LLi
05
05
O)
05
LLI
UJ
LLJ
UJ
LLi
05
CO
LLI
LU
CO
Time [s]
Figure C-3: Handshake protocol.
C .l
References
[1] K. Boahen “Retinom orphic V ision System s II: Com m unication Channel D esign” ,
Proceedings o f the IEEE: International Sym posium for Circuits and Systems, volume
Supplement, Piscataway NJ, 1996. IEEE Circuits and Systems Society, IEEE Press.
237
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Appendix D
Voltage Mode Dual AGC
Besides the current m ode effort, a voltage m ode im plem entation o f the dual AGC was
designed and fabricated. Initially, this chip was designed to be used in the PCB version o f
the auditory nerve. Since the chips did not com e back from fabrication on time for being
used in an upcom ing fieldtest, the dual A G C was built up using off-the-shelf analog m ul­
tipliers.
O nly the chip data is shown. In general, the voltage m ode dual A G C chips w orked and
show ed proper transient responses. The design w as sensitive to mism atch. Identical de­
signs on the same chip (four dual A G C s) show ed different transient behavior and careful
tuning regarding the dual AGC system param eters (see Figure 5-12) w as necessary. Fig­
ure D -l shows the transient response o f the voltage m ode dual AGC.
238
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Voltage Mode Dual AGC Transient Response
Input [V]
'Output [V]
Time [s]
F igure D -l: T ransien t R esp onse to a sin -inp ut w a v e form .
Figure D-2 shows the on-set and steady state response o f the voltage m ode dual AGC.
From a perform ance standpoint, at around lOmV input voltage, the dual A GC begins to
kick in. The design begins to saturate for input voltage levels o f around IV.
239
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Onset/Steady State Response DualAGC
1.2
O n-set response
1.0
0.8
0.6
0.4
Steady state Response
0.2
0.0
1E-3
10E-3
100E-3
1E+0
Input Voltage [V]
F igu re D-2: T u n in g C urve o f the v o ltage m ode dual A G C .
240
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Appendix E
E .l
Circuit Analysis
Distortion Analysis
D istortion is an undesired effect that appears in analog circuits due to non-linear behavior
o f the devices and their lim ited dynam ic range. The V olterra series is the m ost popular
symbolic m ethod to analyze distortion. It com bines the theory o f convolution and Taylor
series expansion and expresses the non-linear behavior o f systems w ith memory. A de­
tailed description o f the analyses m ethod can be found in [1]. A n easier approxim ation
technique can be found in [2 ], w here the system is handled as a non-linear m em ory-less
system and hence is using on the Taylor expansion to gain insight into the non-linear be­
havior. The T aylor series representation is shown in equation E -l.
T(X) = a0 + a\ ■x + a2 ■x 2 + ct3 ■x:3 +...
(E -l)
Using this m ethod, tools such as M athem atic or M atlab can be used to replace the tedious
Taylor series expansion in an automated manner. Once an output transfer function is de­
rived, the input signal node can be replaced by a single tone input signal (equation E-2).
Hence, the system is “stim ulated” with a single tone.
241
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(E-2)
Inserting equation E -l into the output transfer function and using a Taylor series expan­
sion, the harm onic com ponents can be found (equation E-3). The “stim ulated” system
produces higher order harm onics that contribute to the overall total harm onic distortion
(THD) o f the output signal iout.
- ax( j ■co) ■itest ■exp( j ■co-t) +
a2(j ■co) ■itest2 ■exp { j ■2-a>-t)+
(E-3)
a3(j • of) ■itest 3 •exp(y •3 co ■t) +...
Hence, the harm onic distortions (HD 2 , H D 3 , ...) as well as the total harm onic distortion
(THD) can be expressed as (equation E-4):
HD2 =
nest
ax{j-a>)
HD3 =
( j • co)
— <-■itest1
ax(j-co)
THD = H D 2 + HD3 +...
242
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(E-4)
E.2
Distortion Analysis of the Pseudo Differential I2V Converter
The sm all signal transfer function o f the I2V converter o f Chapter 3.3.1 is the input cur­
rent divided by the gm o f the transistor the current is applied to, expressing the triode re­
gion behavior o f this circuit. H ence, the harm onic distortion o f this circuit w ould be zero.
N evertheless, sim ulating this circuit, the distortion profile is dom inated by a very strong
2nd order harmonic. H ence, the sm all signal assum ption does not hold as it was used in
other current m ode circuits w ith low im pedance nodes. The analysis o f this circuit has to
be perform ed in the large signal domain.
From Figure 3-3, only the h a lf circuit w ith transistor M2 is analyzed. Equation E-5 ex­
presses the gate voltage o f M2, g
is the transconductance o f the OTA, VDS
is the
source drain voltage o f transistor M 2 and Vref is the reference voltage.
M2 is operated in the triode region. The large signal behavior is form ulated in equation
E- 6 . Ib is the bias current, I sjg is the positive input signal, VOM is the output voltage
( VGS ). B is the transistor gain (B = p C ox'W /L).
243
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(E-6)
First, w e solve equation E - 6 for VDS . This yields (equation E-7):
vVDS
=-
-2-B-VOM+2-B-V,h+. 4 B . ( l B+Isigp) + (2.B.Vlh- 2 . B . V oulp)
(E-7)
2 B
W e substitute equation E-7 into equation E-5. The large signal expression for the gate
voltage o f M2 Vout is given by (equation E - 8 ).
-B ■gmOTA■(Ke/ + g">OTA■K<f ~ V,H) + ^ ■glT,
+ 2 ■gTH^ ■/* + I ^ + 2 ■gl»m •7,^ + B •(g W ■Kre/ + F,, )' j
(E -8 )
B(l + 2-gmra)
W e can find the second order harm onic distortion o f equation E - 8 by perform ing a Taylor
series expansion. This yields (equation E-9):
HD2 =
( l + 2 ■g m 0TA) ■I sjg________________
4 '[ h
+ 2 ■S m OTA
J B + B - { g m OTA ■K e f + V,k ^
(E . 9 )
)
The differential output is given by equation (E-10) and is com posed o f the difference o f
Voul and VBUt , w here Vout is the output voltage o f the other h a lf circuit.
244
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
J b ■gtn0TA ■
2 • gm0TA ■Is + Isjg + 2 • gm0TA ■I sig + B ■( gm0TA ■Vref + Vlh) j
+
Voutdiff
5 - ( l + 2 -gm 0TA)
■ jB
- g m OTA2
• ( 7S +
2
'g
m OTA ' h
-
I , ig
-
2
•g ™ O T A ’ h i s +
(E - 10)
B
'{ g
m OTA
' K ef
+ K l, f
)
B - ( \ + 2 -g m 0TA)
Perform ing a Taylor series expansion on equation E-10, yields equation E -l 1. Equation
E - l l is the third order H arm onic. The differential approach rem oves the 2nd order har­
monic.
HD3 = —
(l + 2 -g moTJ) 'Isis ___________
( E - ll )
8'( / « + 2 '^o,, ■JB+ B i g mm 'Kef+Kh) )
The circuit o f Figure 3-3 is a pseudo differential im plem entation. Hence, a fabricated cir­
cuit w ill yield 2nd order harm onics depending on the m atching o f the circuitry. The 2nd
order harmonics are very dominating. This topology is also used for the current mode in­
tegrator, which is a full differential im plem entation and is hence better suited to achieve
the current to voltage conversion.
245
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In order to com pare the im pact o f the 2nd and 3rd order harm onic distortion, HD2 and
HD3 are evaluated w ith typical circuit settings: g m
= 1OuA/V, Isi„=luA
,
"'O T A
®
B =5pA /V 2, Vref=l V,
I
b
= 1 0
u
A ,
V th = 0 .7 V .
The ratio betw een bias current
Ib
and signal current
I Si g
is 10:1. U nder these bias and sig­
nal settings, HD2 is in the order o f 20%. H ence, the single ended version is not suitable
for current to voltage conversion. U sing the pseudo differential scheme, HD3 reduces
dram atically to
0
.1 %
246
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
E.3
Transfer Function Current Mode Low Pass Filter
From the small signal m odel in Figure 3-11, following equation system can be derived
(equation E-12):
+c^,
' s + cS^
' s + c^
-s + c^ - s
+
c.m ■ s
^ mOTA ^SdMl
£ d s M1
0
o’ V
0 v,»
1
•
J o
.
0
h
0
(E-12)
Before deriving the transfer function H(s)= ioli. from equation E-12, follow ing sim plifi­
cations are m ade: g m^ = g muj = g m^ = g mand g dSM= g dSu= g ds. These sim plifications can
be made, since the current m ode structure is equally biased. This results in output resis­
tance and equal transconductance. U sing these sim plifications, H(S) can be derived (equa­
tion E-13) as:
-1
*«=■
1
C to t
+5■
Sm
(E-13)
S d S i,
c.
' Sn
1 + S ■§ n
g d MI
'O TA
/
247
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The transfer function has a pole at a>0 = - m- ——— and a zero at &>, = ^ m°TA . Depending
C to t
& dsm
C ' g d MX
on the m ode o f operation, coi is in the 1 kH z to 10 kHz range, w hereas coo is far below 1
kHz. N evertheless, the zero limits the overall frequency response o f this low -pass filter.
248
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
E.4
Transfer Function of the Fully Differential Current Mode Inte­
grator
Figure E -l shows the sm all signal m odel o f the full differential current m ode integrator.
SdS:
S ds,
Sds,
int
M2
g
& m M
4
vi
g5 mM6 v t
Sds,
int,
Figure E -l: Small signal model CMI.
249
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In order to derive the differential transfer function H(S) for the fully differential current
m irror, follow ing sim plifications/groupings are made: Cgd^ = Cgd^ =
C S ^ ,M 2 = C .
— Cg d ,\ i 6 = Cg dj„
C i n t,M = Cg s M \ + CS S M 3 + CS S M S + C-i n t , C- i n t n =
= Cgd ,
c
g s M2
+
c
S S MA
+
CgSui + Cint. Exam ining the small signal m odel for the output current io yields following
set o f equations (equation E - l4):
'3 •C^-5 + Cmt/5
0
0
C gd„
~ C gdp
'S+ Cint„ ~S
~ S
m0TA~
S d s M1
+
&mOTA
S
c gd„
0
S
’S
0
Sdsm
0
0
S m ui
Cgd p '
& d s M 1 + S d s Mi
0
o'
0
0
0
1
V
'o '
0
v*„
= \
V.
•
/„
\
0
Vv
A
_
(E -l 4)
Solving this equations result in a h a lf circuit analysis. In order to derive the full differen­
tial transfer function, the small signal m odel in Figure E -l is hence also examined for the
output current io (equation E - l 5).
0
0
3 ' C gdm •5 +
~ c gdp
C ,n .„
~ S m 0TA ~ ° g d „
& dsM 2 +
0
& m M6
s
S d sM 3
0
0
S m 0TA
S
C gdp
~ C gd„
^
0
& dsu 1 +
0
S d s M4
S
o'
0
0
0
1
V
V
'o '
0
gp
g„
v.
•
=
v.
'?
_
'0,
_
\
\
0
(E -l 5)
250
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In order to reduce the com plexity o f the equation system further, all cgd terms are com ­
bined since all transistors have identical dim ensions. A lso, all g ds and g m terms are com ­
bined. These simplifications can be m ade, since the current m ode structure is equally bi­
ased. This results in output resistance and equal transconductance. U sing these sim plifi­
+
0
cint-s
- CSJ'S
0
S r n OTA
sm
Sm
Sm
Sm
0
0
Cgd
‘S
~ Cg d - S
0
2-sdk
0
Sm
Cg d ' S
S m 0TA
2 -Sds
0
o'
0
0
0
'o'
0
•*tj *
~3-cgd-s
1
1
cations, equations E - l4 and E - l 5 can be rew ritten as (equation E - l 6 ):
v *.
•
=
\
0
A.
1
0
c i * - s
0
3 -
V
5 +
Sm
Sm
Sm
Sm
Sm
0
~ Cg * ' S
Ci n t ' 5
S m OTA
Cgd ' S
2 ~Sds
0
0
S m OTA
Cgd
‘S
~ C g J - S
0
2 'S d s
0
o'
0
0
0
1
'o'
•ts
~c g d - s +
____ I
1
(E -l 6 )
0
Vs„
•
=
\
K
\
J o „
_
0
(E -l 7)
Solving the equation system (equation E - l 6 and E - l 7) for H(S)= i0 Ui =i0 //' , the trans­
fer function for the h a lf circuits can be found as (equation E -l 8 ):
251
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
1+—
H (s)=
(E -l 8)
s
1+ CO.
coo, coi and
©2
C0-,
can be found as (equation E-19):
8 m
ox
=
S mnT.
--------------------------------------- —
2 - g d s - ( 2 - c g d + c m t)
cox
Sm
-
—
2 ’C gd
'
a>2 =
S mnTA
----------------
—
' Sm
C gd
<
-'int ’ S
+ Cint
ds
J'g m 'S /r,
(csd + c int) -( 3- cgd+ cmt) - gds+ 2 - c gd-( 2-c gd + cint)-g„
(E-19)
The transfer function for the full differential circuit is the same as equation E - l 8 , w ith a
co0
Sm 'S m
------~t~~— — -----r , which is the unity gain frequency o f the integrator. H i is a zero
^ • ( 2 ’c^ + c int)
w here as
©2
sets another pole in the transfer function. B y com paring ©0 , coi and ©2 , all
poles and zeros are very close to each. Setting cga to zero, ©o,©i and
©2
are reducing to
(equation E-20):
252
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Sm ' S n
6) 0 = S d s ’ C ir
S m * S i m OTA
cox =-
(E-20)
S d s ' C ir
co2 =
Sm
S mQ
S d s ' C in
Inserting
a » o ,c o i
and
©2
into the transfer function o f equation E -l 8 yields the ideal transfer
curve o f the current m ode integrator (equation E-21). The poles and zeros cancel each
other out.
* (,)= ■
s
253
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(E-21)
E.5
Mismatch Analysis Fully Balanced Current Mirror
Figure E-2 shows the schematic o f the fully balanced current m irror. For the mism atch
analysis, only the DC current gain is derived and only transconductance are considered.
Any bulk effects are neglected.
O
Figure E-2: Fully balanced current mirror.
254
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
The equation system for the DC operating point for the positive output current is as fol­
low ing (equation E-22):
0
0
0
0
0
0
0
0
0
0
0
0
VK
tin.
%
l 'np
0
0
0
0
0
0
0
0
0
1
v*.
0
V * ,0
0
Vx2
0
0
•
0
&mM
\2
0
0
0
0
0
0
10
0
0
0
0
V*3
0
0
0
0
0
0
0
0
v *4
0
0
0
0
z
0
6
%
l 0
+
z
0
0
J o u tp
_
(E-22)
The equation system for the DC operating point for the positive output current is as fol­
low ing (equation E-23):
0
0
0
0
0
0
0
o '
0
0
0
0
0
0
0
&mM
6
^™M\
0
0
s mu.
0
0
0
zbmM+ zOmM
9
0
0
0
0
Smu ,
0
0
0
&mM\a
0
0
0
0
0
0
&mM
9
3
&mM9
V-n„
%
1
0
0
•
*inp
v *.
0
v *7
0
VX3
0
0
0
0
0
0
V
0
0
0
0
Vx9
0
0
&mMU
0
2
0
(E-23)
255
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
Solving equation E-22 for iout yields (equation E-24):
SmMI3 SmM,
Sm,,,,
Si
'" m i
5
(E-24)
1out„
S r"n’MX
„,
Solving equation E-23 for /
°S i m M 11
yields (equation E-25):
S m M4 + S m M n
^% n
'
S m M6
om
J„
.
’
SmmI
(E-25)
in,
& mMl
C om bining equation E-24 and E-25 yields the differential output current io. , can be ex'dig
pressed as (equation E-26):
_
°utdiff
•
outn
_
•
out„
_
^ % n
&">mx + ^ "'m x x ’ S m u s ' .
_
_
_
inn
Smm
S m MU
Sm uu
Sm ui + Sm un
S m M6 _ .
_
S m MI2
ii
S m M1
(E-26)
A ssum ing that all gm’s o f equation E-26 are equal, the differential gain Adjff can be found
to be two (equation E-27).
A dif f
_
1QUIP
-
.
l outn _
0
.
L
l.mn - m
1„
-
256
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(E-27)
The com m on mode gain can be expressed as (equation E-28)
_ l°utp
^
lout„
SmMi+ Smuu &mM5
&mMU ' SmMi + &mM12 SmM6
cm
in
SmM| SmMn
m M\2
(E-28)
■s,
°
m M l
By using the assumptions, that all gm’s are identical, the com m on m ode is 0. In order to
derive the com mon m ode gain under m ism atch conditions, a transconductance offset
dgmcan be derived as (equation E-29)
4 m = * ^ = l1 + * r
m
gm
W
V
(E-29)
U sing (equation E-30)
(E-30)
Hence, all gm’s can be expressed as (equation E-31).
257
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
gn,m = g m i l ± dgm)
g mM2= g m- { l ± d g m)
g^
= g m' ( 1±£f e j
g mM4= g m{ l ± d g m)
gn,M5 = g mi l ± dgm)
gmM6 = g m\ x±dgm)
g mui = g m- { \ ± d g m)
g mm= g m- ( l ± d g m)
gmM9 = g mi l ± dgm)
g mmo = g m •( 1 ± dgm)
gmmx = g mi l ± dgm)
g mun = g m ■( 1 ■
± dgm)
g m m 3 = g m’( 1 ± dg m)
g„mt = g m •( 1 ± d gm)
3
(E-31)
Inserting equation E-31 into equation E-28 yields (equation E-32)
i.
out., -~'ou,„
_ (:i ± d gm) - ( \ ± d g m) + ( i ± d g m)• ( i ± d gm)
L,„
4 cm =
(i± * .).(i± * .)
(E32)
{ \ ± d g m) - ( \ ± d g m)
A w orst case A cm is expressed in equation E-33 by m axim izing all ratios and differences
o f equation E-32:
4
. - ^
lin
^
=£
(1
^ 4
~ d g m)
(l + dg m)
258
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
(E-33)
For a 0.8um process, the process com er A W =0.4pm and AL =0.1 pm. U sing equation xx,
a m axim um dg m o f 0.5% can be found. In order to express the m atching o f the devices, a
correlation coefficient o f 95% is used. The relative m axim um deviation betw een the tran­
sistors is hence dgm o f 0.11%. U sing this number, the com mon m ode gain A cm is 0.0177
or -36dB. This num ber is pretty high for a com mon m ode gain. E quation E-33 m akes the
assumptions, that the left hand side circuitry o f Figure E-2 is fully independent o f the
right hand side. The w orst case com m on m ode rejection ratio C M R R can be found as
(equation E-34):
CM RR =
A.ldiff
A.cm
2
(E-34)
{l +dgm)2 ( l - 4 g j 2
i} + dgmf
Hence, the w orst case CM R R for this circuit w ould be in the order o f 42 dB.
259
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
E.6
References
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VITA
Christian Karl
216 Saint Paul Street, Apt. 501
Brookline, M A 02446
PROFESSIONAL EXPERIENCE
Intel, Hudson, M A M CP, N ovem ber/2005 - Present
A nalog Circuit D esigner
o
Analog Circuit design for high speed probing solution,
o
Signal Integrity W ork on m id-bus for instrum ented and un-instrum ented
decks.
Infineon Technologies - Pow er Sem iconductors Division, M unich, Germany.
November/1998 —Septem ber/2000
Analog Circuit D esigner
274
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o
D esigned circuit for industrial and autom otive applications in the field o f
Low D rop O ut (LDO) linear V oltage Regulators (VR) (consists o f bandgap circuitry, pow er stage, differential am plifiers, watchdog, etc.).
o
Supervised layout processes.
o
Evaluated first samples, set up test engineering w ith test protocols, defined
and evaluated quality assurance and product monitoring,
o
Products developed (still m anufactured parts): TLE 4307 (Pow er Charge
Pum p and LDO VR), TLE 4299 (5V LD O VR, low quiescent current),
TLE 4264 (5V LDO VR), TLE 4266 (5V LD O V R w ith inhibit). Technol­
ogy used: D OPL32 (bipolar).
•
Intel, H udson, M A, Observability Port (Coupler), June/2005 - N ovem ber/2005
Student Internship: D esigned porting o f an analog high speed data read out system. Task
included verification o f individual cell blocks as w ell system simulations including m is­
m atch effects.
Siemens A G Sem iconductors - Regensburg, Germany.
Spring and Sum m er 1995, Spring 1997
275
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Responsibilities included program m ing and evaluating scanning electron m icroscopes in
line production, building up a network, statistic process control o f different processing
equipm ent used in the sem i-conductor industry and com puter-integrated manufacturing.
Colorado State U niversity - O ptoelectronics C om puting Systems, Fort Collins.
M arch/1996 - September/1996
Student Internship: Responsibilities included redesigning a sm art pixel for a holographic
database application using a GaAs process. The circuit was tested and characterized.
W ork also involved M ESFET modeling.
•
Siemens A G Semiconductors - Regensburg, Germany.
October/1994 - February/1995
Student Internship: Responsibilities included Repeatability and Reproducibility (R&R) o f
processing equipm ent in production and introducing the Ford R & R m ethod tow ards scan­
ning electron m icroscopes in line production.
276
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EDUCATION
Ph.D Program , Boston U niversity - College o f Engineering, B oston, MA:
Septem ber/2000 - Present. Planned graduation: Spring 2006.
o
M ajor: V LSI circuit design. C urrent GPA: 3.9 w ith full scholarship from
B oston University.
o
D esigned, simulated, laid out and tested 9 analog and m ixed signal fullcustom V LSI chips using CM OS and BiCM OS processes such as AM I ABN
and A M S BYR.
o
D esigned and im plem ented full differential current m ode elem ents that are ro ­
bust against process and m ism atch variations. Circuit elem ents such as voltage
to current, current to voltage, low -pass filters and m ultipliers suitable at very
low frequencies (<10 Hz) w ere designed,
o
D esigned and im plem ented an analog audio processing chip for sound source
localization consisting o f different filter functions, autom ated gain controls
and asynchronous interface,
o
Proficient in Cadence tools w ith m ore than
6
years’ experience. Installed and
m aintained Cadence for the V LSI research environm ent at B oston University,
o
Relevant coursew ork includes: V LSI system design, Sem iconductor devices,
D esign o f asynchronous circuits and systems, Sem iconductor fabrication
technologies, Interconnection networks, Com puter hardw are testing.
277
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D iplom ingenieur, U niversity o f A pplied Science - Regensburg.
M icrosystem s Technology, Regensburg, G erm any - October/1993 - July/1998
o
Thesis “D esign and A nalysis o f a M ixed Signal IC ,” at Boston University,
Boston, M A , 1998.
SKILLS
Cadence Tools, Saber, H-Spice, Spectre, Cougar, Lynx, Ocean, Oread, U nix, M atlab,
M aple, M athem atica (Analog Insydes), C++, Perl, Unix com m and scripts, V erilog HDL,
A nalog HDL, H ardware testing, SolidW orks
MAJOR AWARDS
2003: D ean’s A w ard o f College o f Engineering, Science and Technology
Day Poster Contest, Boston U niversity
2000-2005: Research A ssistantship, the VLSI Laboratory, B oston U niversity
1997: Stipend DAAD (G erm an A cadem ic Exchange Service), scientific exchange
program
278
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MISCELLANEOUS
Co-Founder o f Biom im etic Systems, w ww .biom im etic-system s.com
PUBLICATIONS
C. K arl, H. I. Cohen, G. S. D eligeorges, T. Gore, D. C. M ountain, M. Nourzad, Z. Yang,
A. Zosuls, and A. E. H ubbard, "R eal-tim e Auditory Signal Processing for Sound L ocal­
ization in Battlefield A coustics," presented at Proc. Seventh International Conference on
Cognitive and N eural Systems, Boston, M A, 2004.
C. Karl, Z. Yang, G. S. D eligeorges, D. C. M ountain, H. I. Cohen, A. Zosuls, and A. E.
Hubbard, "A Current-M ode, M ixed Signal VLSI A uditory N erve Chip," presented at
Proc. Seventh International C onference on Cognitive and N eural Systems, Boston, M A,
2003.
C. Karl and J. Kempf, "E ntw urf und Sim ulation von M ikrosystem en," in M eiLe - N eue
M edien in der Lehre., H. Kopp and M. W erner, Eds.: Luchterhand, 2001, pp. 265.
C. Karl and A. E. Hubbard, "A ddress-Event-Representation (AER) Protocol," presented
at Second International C onference on Cognitive and N eural Systems, Boston, M A, 1998.
279
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Z. Y ang, C. Karl, T. A. Hinck, H. I. Cohen, A. Zosuls, D. C. M ountain, and A. E. H ub­
bard, "A Current-M ode Electronic Cochlea Chip B ased on a Traveling-W ave A m plifier
M odel," presented at Proc. Seventh International Conference on Cognitive and N eural
Systems, Boston, M A, 2003.
T. Gore, J. Boura, A. Cherry, H. I. Cohen, G. S. D eligeorges, C. Karl, D. C. M ountain, A.
Terrinoni, A. Zosuls, and A. E. H ubbard, "A Pitch and B earing Auditory Feature Extrac­
tor Im plem ented in an FPGA ," presented at Proc. Seventh International Conference on
Cognitive and N eural Systems, Boston, M A, 2003.
PATENTS
G. S. Deligeorges, T. G ore, A. E. Hubbard, C. Karl, D. C. M ountain, and A. Zosuls,
"Biomimetic Acoustic D etection and Localization System." USA, 2004 (patent pending).
280
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