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JP2007181190

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This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
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DESCRIPTION JP2007181190
An object of the present invention is to provide a semiconductor device in which a small hollow
capacitor can be formed with a simple configuration. A hollow capacitor portion composed of a
pair of opposing electrodes 14 and 24 and a hollow portion 23 between the opposing electrodes
and semiconductor circuit portions 11a 11b 12 are formed on the same substrate 10 The hollow
portion 23 of the capacitor portion is surrounded by the insulating layers 16, 17 and 18, and the
insulating layers 17 and 18 have an introduction hole 22 connected to the hollow portion 23.
The surface of the insulating layer 17 covering the hollow portion 23 is planarized, and the thick
insulating layer 17 located on the side of the hollow portion 23 holds the thin insulating film 17
and the upper electrode 24 located above the hollow portion 23. doing. [Selected figure] Figure 1
Semiconductor device and method of manufacturing the same
[0001]
The present invention relates to a semiconductor device characterized in that a hollow capacitor
portion constituted by a hollow portion located between a semiconductor circuit portion, a pair
of counter electrodes and the counter electrodes is provided on the same substrate.
[0002]
Ultrasonic waves with a frequency of several tens of kHz to several tens of MHz can be detected
even if the object is transparent in the visible light range because the directivity is strong. It is
applied to a wide range of fields, taking advantage of the property of being less susceptible to
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1
For example, as ultrasonic sensors, distance measuring machines such as fish finders, diagnostic
devices capable of nondestructive inspection, flaw detection machines, etc. have been put to
practical use, and as ultrasonic wave based instruments, cleaning machines and welding
machines And the like have been put to practical use (see, for example, Non-Patent Document 1).
The ultrasonic sensor is generally divided into a transmitting unit that transmits an ultrasonic
wave and a receiving unit that receives the transmitted ultrasonic wave.
[0003]
However, since the receiving part of the conventional ultrasonic sensor usually uses a
piezoelectric ceramic vibrator, the cost of the apparatus becomes high, and there is a problem
that it can not be made very small. In addition, in order to improve detection sensitivity, the
substrate side of the vibrator has to be etched and thinned, which causes a problem that the
manufacturing process becomes complicated. Therefore, the use application was limited.
[0004]
FIG. 10 is a cross-sectional view showing the structure of a receiving unit of a conventional
ultrasonic sensor.
[0005]
Lead zirconate titanate (PZT), which is a ferroelectric ceramic material, is formed on the substrate
as a material of the piezoelectric ceramic vibrator 100.
Usually, in order to form PZT, it is necessary to sinter at a high temperature of 550 ° C. or
higher in an oxygen atmosphere, so that the material of the electrode 101 is to prevent the
formation of an insulator due to oxidation in the sinter process. And platinum group materials
such as platinum and iridium which are difficult to be finely processed and expensive. Also, in
order to ensure sensitivity, it is necessary to thinly etch the back surface of the substrate on
which the piezoelectric ceramic vibrator is formed to form the opening 102. For example, an 8inch Si wafer has a thickness of about 750 μm, The etching technique of about 1 to 2 μm,
which is usually performed in the process of forming a semiconductor device, can not be applied,
and a special process has to be used to form the opening 102.
04-05-2019
2
[0006]
On the other hand, Patent Documents 1 to 3 disclose ultrasonic sensors comprising a
semiconductor circuit portion and a hollow capacitor on a semiconductor substrate. Here, the
hollow portion provided between the pair of electrodes is formed by removing the sacrificial
layer by wet etching with hydrofluoric acid or the like. Tomikawa Yoshiro, "Ultrasonic Electronics
Vibration Theory-Fundamentals and Applications", Asakura Shoten, February 20, 1998 Patent
No. 2545713, Japanese Patent No. 2002-518913, Japanese Patent Laid-Open No. 2002-250665
[0007]
However, a liquid etchant such as hydrofluoric acid is introduced into the sacrificial layer when
forming a fine hollow portion having a width of several μm to several mm and a gap of several
hundred nm to several μm, which is necessary as an ultrasonic sensor It is very difficult. Further,
even if the liquid etchant can be introduced from the hollow portion, even if the liquid etchant
can be introduced, the surface tension of the liquid etchant causes the hollow portion to collapse.
[0008]
The present invention was made to solve the above problems, and its main object is to provide a
semiconductor device capable of forming a small-sized hollow capacitor with a simple
configuration.
[0009]
In order to achieve the above object, a semiconductor device according to the present invention
comprises a hollow capacitor portion constituted of a pair of opposing electrodes and a hollow
portion between the opposing electrodes, and the hollow portion of the hollow capacitor portion
is It is characterized in that it is wrapped in an insulating film.
[0010]
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With such a configuration, a compact hollow capacitor (ultrasonic sensor) can be easily realized
with a simple structure.
Further, the upper electrode of the hollow capacitor portion is vibrated by the incidence of the
ultrasonic wave, and thereby, the distance between the upper electrode and the lower electrode
changes, whereby the capacitance of the hollow capacitor portion changes.
The capacitance change of the hollow capacitor portion can be amplified and detected by a signal
processing circuit mounted on the semiconductor circuit portion to operate as an ultrasonic
sensor.
[0011]
In one preferred embodiment, the insulating film is a first insulating film covering a lower
electrode of the hollow capacitor portion, and a second insulating film covering a hollow portion
of the hollow capacitor portion formed on the first insulating film. It is comprised from the film |
membrane and the 3rd insulating film which covers the upper electrode of the hollow capacitor
part formed on the 2nd insulating film.
[0012]
With such a configuration, when the sacrificial layer provided in advance in the region where the
hollow portion is to be formed is etched away in order to form the hollow portion, the portion
other than the sacrificial layer such as the upper electrode and the lower electrode is etched. Can
be prevented.
[0013]
In one preferred embodiment, the semiconductor device further includes a first hole connected to
the hollow portion of the hollow capacitor portion, and the first hole penetrates the third
insulating film and the second insulating film.
Thereby, the etchant for forming the hollow portion can be easily introduced into the sacrificial
layer.
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[0014]
In one preferred embodiment, the semiconductor device further comprises a second hole
connected to the hollow portion of the hollow capacitor portion, wherein the second hole
penetrates at least the third insulating film and the upper electrode of the hollow capacitor
portion.
As a result, more etchant can be introduced into the sacrificial layer, and the hollow portion can
be easily formed.
[0015]
Here, the wall surface of the second hole is preferably covered with a protective film. Thus, when
the hollow portion is formed by etching away the sacrificial layer, it is possible to prevent the
upper electrode and the like from being etched.
[0016]
Further, it is preferable that the insulating film and the protective film be made of a silicon oxide
film, the upper electrode and the lower electrode of the hollow capacitor portion be made of
polycrystalline silicon, and the upper electrode be vertically sandwiched by a silicon nitride film.
Thereby, the ceiling portion of the hollow portion can be made to stand independently regardless
of the type and shape of the upper electrode.
[0017]
Furthermore, it is preferable that a charge retention layer is provided between the upper
electrode of the hollow capacitor portion and the hollow portion, and the charge retention layer
is surrounded by the insulating film. Thus, when ultrasonic waves are received, the voltage
change between the upper electrode and the lower electrode of the hollow capacitor can be
increased, and the reception sensitivity can be increased.
04-05-2019
5
[0018]
Another semiconductor device according to the present invention is a fixed electrode formed on
a substrate, a first insulating film formed on the substrate so as to cover the fixed electrode, and
a first insulating film. A hollow portion formed above the fixed electrode, a second insulating film
formed on the first insulating film so as to cover the hollow portion, and a second insulating film
on the second insulating film, And a movable electrode formed above the hollow portion, wherein
the fixed electrode, the hollow portion, and the movable electrode constitute a hollow capacitor,
and the second insulating film is characterized in that its surface is planarized. I assume.
[0019]
With such a configuration, the second insulating film and the movable electrode located above
the hollow portion can be held by the thick second insulating film located on the side of the
hollow portion. It is possible to prevent the second insulating film and the movable electrode
located above the hollow portion from bending and blocking the hollow portion.
[0020]
In a preferred embodiment, a third insulating film is further formed on the second insulating film
so as to cover the movable electrode.
[0021]
In a preferred embodiment, an introduction hole connected to the hollow portion is formed in the
second insulating film and the third insulating film.
[0022]
In a preferred embodiment, the hollow portion has a communication hole extending from the
periphery of the hollow portion to the second insulating film side, and the introduction hole is
connected to the communication hole.
With such a configuration, it is possible to increase the thickness of the thick second insulating
film located on the side of the hollow portion, thereby making the second insulating film and the
movable electrode located above the hollow portion stronger. Can be held in
[0023]
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It is preferable that the hollow portion has a rectangular shape, and the communication hole
extends from the periphery of the hollow portion in the shape of a cross to the second insulating
film side.
[0024]
The method of manufacturing a semiconductor device according to the present invention
comprises the steps of: forming a fixed electrode on a substrate; forming a first insulating film on
the substrate so as to cover the fixed electrode; and on the first insulating film. Forming a
sacrificial layer above the fixed electrode, forming a second insulating film on the first insulating
film so as to cover the sacrificial layer, and forming a surface of the second insulating film
Planarizing so that a second insulating film having a predetermined thickness remains on the
sacrificial layer; forming a movable electrode on the second insulating film above the sacrificial
layer; Forming a third insulating film on the second insulating film so as to cover the movable
electrode; and forming an introduction hole for reaching the sacrificial layer in the second
insulating film and the third insulating film And forming a hollow portion in the second
insulating film by etching away the sacrificial layer through the introduction hole, and fixing
Poles constitute a hollow capacitor hollow portion, and the movable electrode.
[0025]
In a preferred embodiment, the sacrificial layer has a portion extending from the periphery of the
sacrificial layer to the second insulating film side, and the introduction hole is connected to the
portion extending the sacrificial layer.
[0026]
According to the semiconductor device of the present invention, a small-sized hollow capacitor
(ultrasonic sensor) can be easily realized with a simple structure.
Further, according to the method of manufacturing a semiconductor device according to the
present invention, a hollow capacitor (ultrasonic sensor) having a hollow portion with a stable
shape can be manufactured by a simple manufacturing method.
[0027]
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Hereinafter, the best mode for carrying out the present invention will be described using the
drawings.
The embodiment described below is an example used to explain the configuration of the present
invention and the operation thereof in an easy-to-understand manner, and the present invention
is not limited to the following embodiments.
[0028]
First Embodiment A semiconductor device (ultrasonic sensor) according to a first embodiment
will be described with reference to FIGS. 1 to 5.
[0029]
[Configuration of Ultrasonic Sensor] FIG. 1A is a cross-sectional view schematically showing the
configuration of the ultrasonic sensor according to the present embodiment, and FIG. 1B is a
cross-sectional view of the ultrasonic sensor according to the present embodiment. It is the top
view which showed the hollow capacitor part.
Moreover, FIG. 5 is sectional drawing which showed the structure of the ultrasonic sensor which
concerns on the modification of this embodiment.
[0030]
As shown in FIG. 1A, the ultrasonic sensor according to this embodiment includes a hollow
capacitor portion in which an upper electrode (movable electrode) 24 and a lower electrode
(fixed electrode) 14 face each other, a field effect transistor element, etc. It has a configuration in
which a semiconductor circuit portion including an amplifier circuit, a noise removal circuit, an
output circuit and the like configured is integrated.
Although FIG. 1A shows one hollow capacitor portion and one transistor in one semiconductor
circuit portion, a plurality of such hollow capacitor portions may be arranged in an array.
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In this case, a selection transistor capable of selecting each hollow capacitor arbitrarily is
connected to the plurality of hollow capacitor portions.
Here, FIG. 1A is a cross-sectional view passing through the main part (A-A ′ line) of the hollow
capacitor portion illustrated in FIG. 1B.
[0031]
As shown in FIG. 1A, a source region 11a and a drain region 11b in which an n-type impurity is
diffused are formed on the surface of a p-type silicon substrate 10.
A device isolation region 13 of a thick oxide film is formed on both sides of the source region
11a and the drain region 11b, and a first interlayer insulating layer (first insulating film) 16 is
formed on the surface of the silicon substrate 10. A second interlayer insulating layer (second
insulating film) 17, a third interlayer insulating layer (third insulating film) 18, and a surface
protection film 26 are stacked. The surface of the second interlayer insulating layer 17 is
planarized so that the second interlayer insulating layer 17 a having a predetermined thickness
remains on the hollow portion 23. Here, the first interlayer insulating layer 16, the second
interlayer insulating layer 17, and the third interlayer insulating layer 18 are formed of a silicon
oxide film.
[0032]
The gate electrode 12 is formed between the source region 11 a and the drain region 11 b, and
the lower electrode 14 is formed on the element isolation region 13. Furthermore, an
introduction hole (first hole) 22 connected to the hollow portion 23 and the hollow portion 23
via the first interlayer insulating layer 16 is formed on the lower electrode 14.
[0033]
As shown in FIG. 1B, the hollow portion 23 has communication holes 23a extending horizontally
from the periphery of the hollow portion 23 to the second interlayer insulating layer 17 side, and
each introduction hole 22 is a communication hole 23a. Connected to the end of the For
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example, in the example shown in FIG. 1B, the hollow portion 23 has a rectangular shape, and
the communication holes 23a extend from the sides of the hollow portion 23 in a cross shape
toward the second interlayer insulating layer 17. The end of the upper electrode 24 is located
above the communication hole 23 a extending from each side of the hollow portion 23.
[0034]
With such a configuration, the second interlayer insulating layer 17 a located above the hollow
portion 23 and the upper electrode 24 can be held by the thick second interlayer insulating layer
17 b located laterally of the hollow portion 23. Thus, it is possible to prevent the second
interlayer insulating layer 17a and the upper electrode 24 located above the hollow portion 23
from being bent and blocking the hollow portion 23.
[0035]
By providing communication holes 23a extending from the sides of the hollow portion 23 in the
hollow portion 23, the second interlayer insulating layer 17b having a large film thickness is
formed at a portion located on the side of the communication holes 23a. A pillar supporting the
upper electrode 24 can be provided, whereby the second interlayer insulating layer 17 a located
above the hollow portion 23 and the upper electrode 24 can be more firmly held.
[0036]
Here, the area of the lower electrode 14 is larger than the upper electrode 24.
The hollow portion 23 is covered with a silicon oxide film.
Here, the hollow portion 23 has a height of approximately 300 nm to 1 μm and an area of
approximately 90 nm × 90 nm to 1000 μm × 1000 μm. Further, the opening area of the
surface portion of the introduction hole 22 is approximately long side 100 nm × short side 70
nm to long side 800 μm × short side 10 μm.
[0037]
An upper electrode film 24b is provided above and below the hollow portion 23 by the tension
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10
films 24a and 24c, and the upper electrode 24 is formed of the tension films 24a and 24c and
the upper electrode film 24b. Here, the tension films 24a and 24c are made of, for example, a
silicon nitride film, and the film thickness is thinner than the upper electrode film 24b and is
approximately 30 nm to 250 nm. The upper electrode film 24 b is made of, for example, a
polysilicon film, and the film thickness is approximately 200 nm to 450 nm. The area of the
upper electrode 24 is about 100 nm × 100 nm to about 1100 μm × 1100 μm, and the area of
the lower electrode 14 is about 110 nm × 110 nm to about 1200 μm × 1200 μm.
[0038]
Here, the hollow portion 23 is square and the introduction hole 22 is connected to the hollow
portion 23 in a cruciform manner, but the hollow portion 23 is circular or gear-shaped, and the
introduction hole 22 is any hollow portion 23 It may be connected with the point of
[0039]
Above the source region 11a, the drain region 11b and the gate electrode 12, a contact hole 19
in which a tungsten (W) or polysilicon film connected to the wiring 25 is embedded is formed.
Note that sidewalls 15 are formed on the side surfaces of the gate electrode 12 and the lower
electrode 14.
[0040]
The lower electrode 14 and the gate electrode 12 are preferably made of the same material and
have the same film thickness. As a result, the lower electrode 14 and the gate electrode 12 can
be simultaneously formed and processed simultaneously, and a semiconductor device with a
simpler structure and a smaller size can be realized. Here, the gate electrode 12 and the lower
electrode 14 are made of, for example, a polysilicon film, and the film thickness is about 200 nm
to about 450 nm.
[0041]
The lower electrode 14 is also provided with a contact hole 20 connected to the wiring 25 at a
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11
portion not covered with the hollow portion 23 at the upper side, for example, in which a
tungsten (W) or polysilicon film is embedded. The hole diameters of the contact holes 19 and 20
may be different.
[0042]
The upper electrode 24 is also provided with a contact hole 21 in which a tungsten (W) or
polysilicon film is embedded, for example, which is connected to the wiring 25 at a position
where the hollow portion 23 is not provided below. The hole diameter of the contact hole 21
may be different from the hole diameter of the contact holes 19 and 20. For example, the hole
diameter of the contact hole 19 is approximately 0.6 μm to 2.5 μm, the hole diameter of the
contact hole 20 is approximately 0.6 μm to 2.0 μm, and the hole diameter of the contact hole
21 is approximately 0. It is about 4 μm to 1.0 μm.
[0043]
Further, as shown in FIG. 5, another introduction hole 27 (second hole) may be formed through
the upper electrode 24 and reaching the hollow portion 23. In this case, it is necessary to provide
a wall surface protection film 28 having a thickness of about 50 nm to 150 nm, for example,
made of a silicon oxide film so that the introduction hole 27 penetrates the upper electrode 24 so
that the upper electrode 24 is not exposed. . Here, the hole diameter of the introduction hole 27
is approximately 1 μm to 10 μm, and the opening area of one introduction hole 27 is 1% or less
of the area of the upper electrode 24.
[0044]
Method of Manufacturing Ultrasonic Sensor Next, a method of manufacturing the ultrasonic
sensor according to the present embodiment will be described. 2 to 4 are cross-sectional views
showing the manufacturing process of the ultrasonic sensor according to the present
embodiment, and FIG. 4 (b) is a plan view showing the hollow capacitor portion in FIG. 2 (b).
[0045]
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12
First, as shown in FIG. 2A, the thick oxide film 13 is selectively formed on the surface of the ptype silicon substrate 10 as an element isolation. Subsequently, a gate insulating film and a
polysilicon film are deposited, and a lower electrode 14 is formed on the gate electrode 12 and
the thick oxide film 13 from the polysilicon film using lithography and dry etching.
[0046]
Subsequently, impurities are implanted into the surface of the p-type silicon substrate 10 using
the gate electrode 12 as a mask to form a source region 11 a and a drain region 11 b made of an
n-type impurity diffusion layer. Thereafter, sidewalls 15 are formed on the gate electrode 12 and
the lower electrode 14, and then the first p-type silicon substrate 10 is covered with the field
effect transistor element portion and the lower electrode 14 over the entire surface using the
CVD method. A silicon oxide film to be the interlayer insulating layer 16 and a polysilicon film to
be the sacrificial layer 29 are deposited. Note that in order to manufacture a finer transistor
element, a salicide may be formed on the transistor in the semiconductor circuit portion.
[0047]
Subsequently, as shown in FIG. 2B, the sacrificial layer 29 is processed into a predetermined
shape corresponding to the hollow portion 23 using the lithography method and the dry etching
method. For example, as shown in FIG. 4B, a pattern area such as a cruciform, square, circular, or
gear shape is formed from the polysilicon film. Next, a silicon oxide film to be the second
interlayer insulating layer 17 is formed on the surface of the first interlayer insulating layer 16
and the sacrificial layer 29 formed in the shape of the hollow portion 23 using the CVD method
using the CVD method. Deposit Subsequently, the surface of the deposited second interlayer
insulating layer 17 is planarized using an etch back or a chemical mechanical polishing (CMP)
method or the like. The deposited film thickness of the second interlayer insulating layer 17 is
set so that a predetermined thickness remains on the sacrificial layer 29 after planarization.
[0048]
Next, a silicon nitride film, a polysilicon film, and a silicon nitride film are sequentially deposited
using a CVD method, and an upper portion composed of a tension film 24a, an upper electrode
film 24b, and a tension film 24c using a lithography method and a dry etching method. An
electrode 24 is formed.
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[0049]
Subsequently, as shown in FIG. 2C, the third interlayer insulating layer 18 is deposited on the
upper electrode 24 and the second interlayer insulating layer 17 by the CVD method.
Subsequently, the upper surface of the third interlayer insulating layer 18 is planarized using
etch back or chemical mechanical polishing (CMP) method or the like, and then the contact
connected to the upper electrode film 24 b using the lithography method and the dry etching
method The holes 21 are formed.
[0050]
Further, contact holes 19 and 20 connected to the source region 11a, the drain region 11b, the
gate electrode 12, and the lower electrode 14 of the transistor are formed by using the
lithography method and the dry etching method. Thereafter, a conductive film made of a
tungsten or polysilicon film is deposited by the CVD method so as to fill the contact holes 19, 20,
21. Subsequently, etch back or chemical mechanical polishing is performed on the deposited
conductor film to remove the conductor film on the surface of the third interlayer insulating
layer 18, thereby forming a plurality of contact plugs.
[0051]
Next, as shown in FIG. 3A, for example, titanium, titanium nitride, aluminum, titanium nitride is
deposited by sputtering, and the wiring 25 is formed by lithography and dry etching. .
[0052]
Furthermore, after depositing a silicon nitride film by a CVD method, the silicon nitride film on
the upper surface of a pad (not shown) for electrical connection with an external device is
removed using a lithography method and a dry etching method, and a surface protective film
Form 26.
[0053]
Subsequently, as shown in FIG. 3B, the surface protection film 26, the third interlayer insulating
layer 18, and the second interlayer insulating layer 17 are penetrated by using the lithography
method and the dry etching method, and the shape of the hollow portion 23 is obtained. An
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introduction hole 22 connected to the sacrificial layer 29 formed in
[0054]
Thereafter, as shown in FIG. 4A, the polysilicon film of the sacrificial layer 29 is completely
removed using a gas material capable of etching the polysilicon film, for example, fluorine
trichloride, to form the hollow portion 23.
Here, xenon fluoride as a gas material may be used as an etchant for hollow etching.
Further, an etchant having a surface tension reduced by adding a surfactant such as ethanol to
fluoronitric acid of a liquid material may be used.
[0055]
Here, before hollow etching, the following steps may be added to form another introduction hole
27 and then hollow etching may be performed.
[0056]
As shown in FIG. 5, silicon oxide is formed through the upper electrode 24 to form an
introduction hole reaching the sacrificial layer 29 using a lithography method and a dry etching
method, and subsequently forming a wall surface protective film 28 on the entire surface by a
CVD method. Deposit the film.
Next, the introduction holes 27 are formed simultaneously with the formation of the introduction
holes 22 using the lithography method and the dry etching method.
At this time, the wall surface protective film 28 remains on the side surface of the introduction
hole 27. At this time, the silicon oxide film on the upper surface of a pad (not shown) for
electrical connection to an external device is also removed.
04-05-2019
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[0057]
When the upper electrode 24 is formed, an opening may be formed in the upper electrode 24.
Then, since the third interlayer insulating layer 18 is also embedded in this opening, the
introduction hole 27 can be formed at the same time as the formation of the introduction hole 22
without adding a process. .
[0058]
Superiority of Ultrasonic Sensor The ultrasonic sensor according to the present embodiment
having the above structure has the same structure as the semiconductor circuit portion, the pair
of opposite electrodes, and the hollow capacitor portion formed of the hollow portion between
the opposite electrodes. Being on the substrate, a simple structure and a compact ultrasonic
sensor can be realized.
[0059]
When ultrasonic waves are incident, the upper electrode of the hollow capacitor portion vibrates
to change the distance between the upper electrode and the lower electrode, thereby changing
the capacitance of the hollow capacitor.
The capacitance change of the hollow capacitor portion is amplified and detected by a signal
processing circuit mounted in the semiconductor circuit portion, and operates as an ultrasonic
sensor.
[0060]
In addition, by forming the introduction hole 22 connected to the sacrificial layer 29 of the
hollow capacitor portion, and further the introduction hole 27 connected to the sacrificial layer
29 through the upper electrode 24 of the hollow capacitor portion, an etchant during hollow
etching Can be introduced into the sacrificial layer 29 and the hollow portion 23 can be easily
formed.
[0061]
In addition, by covering the hollow portion 23 with a silicon oxide film, it is possible to prevent
the upper electrode 24 and the lower electrode 14 from being etched when the sacrificial layer
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29 is hollow-etched.
[0062]
In addition, the upper electrode 24 is structured such that the upper electrode film 24b is
sandwiched vertically in the substrate direction by the tensile films 24a and 24c which are high
in tensile stress and made of, for example, silicon nitride films, thereby obtaining the type and
shape of the upper electrode. The ceiling portion of the hollow portion can be formed
independently without regard to the above.
Furthermore, by not forming the contact hole 21 for the upper electrode 24 on the hollow
portion 23, the vibration of the upper electrode 24 can be facilitated to improve the sensitivity.
[0063]
Further, by making the size of the counter electrode of the hollow capacitor portion larger in the
lower electrode 14 than in the upper electrode 24, the contact hole 20 for connecting the lower
electrode 14 and the wiring 25 can be easily formed.
[0064]
Further, since the lower electrode 14 is made of the same material as the gate electrode 12 and
the film thickness is the same, the lower electrode 14 and the gate electrode 12 can be
simultaneously formed and processed at the same time. A compact semiconductor device with a
simple structure can be realized.
[0065]
In addition, by forming the lower electrode 14 on the thick oxide film 13, element separation can
be facilitated.
[0066]
Further, the diameters of the contact holes 19 to the semiconductor circuit portion, the contact
holes 20 to the lower electrode 14 of the hollow capacitor portion, and the contact holes 21 to
the upper electrode film 24 b of the hollow capacitor portion are different. By changing each of
them, it is possible to make the aspect ratio optimal for taking contacts.
04-05-2019
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[0067]
Second Embodiment A semiconductor device (ultrasonic sensor) according to a second
embodiment will be described with reference to FIGS.
[0068]
[Configuration of Ultrasonic Sensor] The configuration of the ultrasonic sensor will be described
using FIGS. 6 and 9.
FIG. 6 is a cross-sectional view showing the configuration of the ultrasonic sensor according to
the present embodiment, and FIG. 9 is a cross-sectional view showing the configuration of the
ultrasonic sensor according to a modification of the present embodiment.
[0069]
As shown in FIG. 6, in the ultrasonic sensor according to this embodiment, a semiconductor
circuit portion including a charge retention material in a hollow capacitor portion in which an
upper electrode and a lower electrode are opposed and further including a field effect transistor
element or the like. Make up an integrated structure.
Although FIG. 6 illustrates one hollow capacitor portion and one transistor in one semiconductor
circuit portion, a plurality of hollow capacitor portions are arranged in an array, and each of the
plurality of hollow capacitor portions is provided. A plurality of hollow capacitors may be
integrated by connecting a selection transistor so that a hollow capacitor can be arbitrarily
selected.
[0070]
As shown in FIG. 6, a source region 11 a and a drain region 11 b in which n-type impurities are
diffused are formed on the surface of a p-type silicon substrate 10.
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Then, element isolation regions 13 of a thick oxide film are formed on both sides of the source
region 11 a and the drain region 11 b, and a first interlayer insulating layer 31 and a second
interlayer insulating layer 32 are formed on the surface of the substrate 10. A third interlayer
insulating layer 33 and a surface protection film 26 are stacked.
Here, the first interlayer insulating layer 31, the second interlayer insulating layer 32, and the
third interlayer insulating layer 33 are formed of a silicon oxide film.
[0071]
The element isolation region 13 is formed between the semiconductor circuit portion and the
hollow capacitor portion, and on the silicon substrate 10 surrounded by the element isolation
region 13, a lower electrode sandwiched vertically by the tension films 14a and 14c. There is a
film 14b, and the lower electrode 14 is composed of the films 14a, 14b and 14c.
[0072]
Further, a through hole 34 is formed in the silicon substrate 10 under the lower electrode 14.
Then, an introduction hole 22 connected to the hollow portion 23 and the hollow portion 23 via
the first interlayer insulating layer 31 is formed.
Here, the introduction holes 22 are connected in a cruciform manner to each side of the
rectangular hollow portion 23.
Here, the tension films 14a and 14c are made of, for example, a silicon nitride film, and the film
thickness is thinner than the lower electrode film 14b and is approximately 30 nm to 250 nm.
The lower electrode film 14 b is made of, for example, a polysilicon film, and the film thickness is
approximately 200 nm to 450 nm. The area of the upper electrode 24 is about 100 nm × 100
nm to about 1100 μm × 1100 μm, and the area of the lower electrode 14 is about 110 nm ×
110 nm to about 1200 μm × 1200 μm. Further, the opening area of the semiconductor
element surface portion of the introduction hole 22 is approximately long side 100 nm × short
side 70 nm to long side 800 μm × short side 10 μm.
04-05-2019
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[0073]
Here, the area of the lower electrode 14 is larger than the upper electrode 24. The hollow
portion 23 is covered with a silicon oxide film. The charge retention material 35 is formed
between the hollow portion 23 and the upper electrode 24 and covered with the second
interlayer insulating layer 32 and the third interlayer insulating layer. Here, the hollow portion
has a height of approximately 300 nm to 1 μm, and an area of approximately 90 nm × 90 nm
to 1000 μm × 1000 μm.
[0074]
Here, the hollow portion 23 is square and the introduction hole 22 is connected to the hollow
portion 23 in a cruciform manner, but the hollow portion 23 is circular or gear-shaped, and the
introduction hole 22 is any hollow portion 23 It may be connected with the point of
[0075]
Above the source region 11a, the drain region 11b and the gate electrode 12, a contact hole 19
in which a tungsten (W) or polysilicon film connected to the wiring 25 is embedded is formed.
Note that sidewalls 15 are formed on the side surfaces of the gate electrode 12 and the lower
electrode 14.
[0076]
The lower electrode 14 and the gate electrode 12 are made of the same material and have
substantially the same film thickness, so that a semiconductor device with a simpler structure
and a smaller size can be realized. Here, the gate electrode 12 and the lower electrode film 14 b
are made of, for example, a polysilicon film, and the film thickness is about 200 nm to about 450
nm.
[0077]
04-05-2019
20
The lower electrode 14 is also provided with a contact hole 20 connected to the wiring 25 at a
portion not covered with the hollow portion 23 at the upper side, for example, in which a
tungsten (W) or polysilicon film is embedded. The hole diameters of the contact holes 19 and 20
may be different.
[0078]
Further, as shown in FIG. 9, another introduction hole 27 may be formed to penetrate the upper
electrode 24 and reach the hollow portion 23. In this case, it is necessary to provide a wall
surface protection film 28 having a thickness of about 50 nm to 150 nm, for example, made of a
silicon oxide film so that the introduction hole 27 penetrates the upper electrode 24 so that the
upper electrode 24 is not exposed. . Here, the hole diameter of the introduction hole 27 is
approximately 1 μm to 10 μm, and the opening area of one introduction hole 27 is 1% or less
of the area of the upper electrode 24.
[0079]
Method of Manufacturing Ultrasonic Sensor Next, a method of manufacturing the ultrasonic
sensor according to the present embodiment will be described. 7 to 8 are cross-sectional views
showing manufacturing processes of the ultrasonic sensor according to the present embodiment.
[0080]
First, as shown in FIG. 7A, the thick oxide film 13 is selectively formed on the surface of the ptype silicon substrate 10 as an element isolation. Subsequently, a gate insulating film and a
polysilicon film are deposited, and a gate electrode 12 is formed from the polysilicon film using a
lithography method and a dry etching method. Subsequently, impurities are implanted into the
surface of the p-type silicon substrate 10 using the gate electrode 12 as a mask to form a source
region 11 a and a drain region 11 b made of an n-type impurity diffusion layer.
[0081]
Subsequently, a silicon nitride film of the tension film 14a is deposited by the CVD method. Then,
04-05-2019
21
a polysilicon film is deposited, and a polysilicon film 14b of the lower electrode is formed using
lithography and dry etching. Subsequently, the silicon nitride film of the tension film 14c and the
silicon oxide film of the first interlayer insulating film 31 are deposited.
[0082]
Next, as shown in FIG. 7B, a polysilicon film to be a sacrificial layer 29 is deposited on the surface
of the first interlayer insulating layer 31 by the CVD method. Subsequently, the sacrificial layer
29 is processed into a predetermined shape corresponding to the hollow portion 23 using a
lithography method and a dry etching method. Here, as in the first embodiment, the polysilicon
film is processed into a pattern shape such as a cruciform. Next, the silicon oxide film of the
second interlayer insulating layer 32 is deposited using the CVD method on the surface of the
sacrificial layer 29 formed in the shape of the hollow portion 23 and the first interlayer
insulating layer 31 using the CVD method. . Subsequently, the upper surface of the deposited
second interlayer insulating layer 32 is planarized using an etch back or a chemical mechanical
polishing (CMP) method or the like. The thickness of the deposited second interlayer insulating
layer 32 is set so that a predetermined thickness remains on the sacrificial layer 29 after
planarization.
[0083]
Next, as shown in FIG. 8A, the charge retention material 35 is formed using a CVD method, a
lithography method and a dry etching method. For example, a Teflon (registered trademark) film
or the like is used as the charge retention material 35. Thereafter, a charge is charged to the
charge retention material 35 using corona discharge, and then the silicon oxide film of the third
interlayer insulating layer 33 is deposited to cover the charge retention material 35.
Subsequently, the upper surface of the third interlayer insulating layer 33 is planarized using an
etch back, a chemical mechanical polishing (CMP) method, or the like. The deposited film
thickness of the third interlayer insulating layer 33 is set so that a predetermined thickness
remains on the charge retention material 35 after planarization.
[0084]
Subsequently, contact holes 19 and 20 connected to the source region 11a, the drain region 11b,
the gate electrode 12, and the lower electrode film 14b of the transistor are formed by using the
04-05-2019
22
lithography method and the dry etching method. Thereafter, a conductive film made of a
tungsten or polysilicon film is deposited by the CVD method so as to fill the contact holes 19 and
20. Subsequently, etch back or chemical mechanical polishing is performed on the deposited
conductor film to remove the conductor film on the surface of the third interlayer insulating
layer 33, thereby forming a plurality of contact plugs.
[0085]
Subsequently, for example, titanium, titanium nitride, aluminum, and titanium nitride are
deposited by sputtering, for example, and the upper electrode 24 and the wiring 25 are formed
by lithography and dry etching.
[0086]
Furthermore, after depositing a silicon nitride film by a CVD method, the silicon nitride film on
the upper surface of a pad (not shown) for electrical connection with an external device is
removed using a lithography method and a dry etching method, and a surface protective film
Form 26.
[0087]
Next, as shown in FIG. 8B, the shape of the hollow portion 23 is penetrated through the surface
protection film 26, the third interlayer insulating layer 33, and the second interlayer insulating
layer 32 using lithography and dry etching. An introduction hole 22 connected to the sacrificial
layer 29 formed in
Subsequently, a resist film (not shown) having an opening below the lower electrode 14 is
formed on the back surface of the wafer by lithography, and the back surface other than the
opening is masked.
[0088]
Subsequently, the polysilicon film of the sacrificial layer 29 is completely removed using a gas
material as an etchant for hollow etching, such as fluorine trichloride or xenon fluoride, to form a
hollow portion 23.
04-05-2019
23
At this time, the silicon substrate 10 in the opening is simultaneously etched to form a through
hole 34 in the silicon substrate 10 below the lower electrode 14.
[0089]
Here, before hollow etching, the following steps may be added to form another introduction hole
27 and then hollow etching may be performed.
[0090]
As shown in FIG. 9, an introduction hole which penetrates the upper electrode 24 and the charge
retention material 35 and reaches the sacrificial layer 29 is formed using a lithography method
and a dry etching method, and then a wall protective film is formed on the entire surface by a
CVD method. A silicon oxide film to be 28 is deposited.
Next, when the introduction hole 27 is formed simultaneously with the introduction hole 22 in
the through hole by using the lithography method and the dry etching method, the wall surface
protective film 28 remains on the side surface of the introduction hole 27. At this time, the
silicon oxide film on the top surface of the pad (not shown) for electrical connection with the
external device is also removed.
[0091]
Superiority of Ultrasonic Sensor The ultrasonic sensor according to the present embodiment
having the above structure has the same structure as the semiconductor circuit portion, the pair
of opposite electrodes, and the hollow capacitor portion formed of the hollow portion between
the opposite electrodes. Being on a semiconductor substrate, a simple structure and a compact
ultrasonic sensor can be realized.
[0092]
When ultrasonic waves are incident, the upper electrode of the hollow capacitor portion vibrates
to change the distance between the upper electrode and the lower electrode, thereby changing
the capacitance of the hollow capacitor.
04-05-2019
24
The capacitance change of the hollow capacitor portion is amplified and detected by a signal
processing circuit mounted in the semiconductor circuit portion, and operates as an ultrasonic
sensor.
[0093]
Further, an introduction hole 22 connected to the sacrificial layer 29 of the hollow capacitor
portion is formed, and further, an introduction hole 27 connected to the sacrificial layer 29 is
formed through the upper electrode 24 and the charge retention material 35 of the hollow
capacitor portion. Thus, the etchant during hollow etching can be further introduced into the
sacrificial layer 29, and the hollow portion 23 can be easily formed.
[0094]
Further, by covering the hollow portion 23 and the charge retaining material 35 with a silicon
oxide film, it is possible to prevent the charge retaining material 35 and the lower electrode 14
from being etched when the sacrificial layer 29 is hollow-etched.
[0095]
Further, by providing the charge retaining material 35 surrounded by the insulating film between
the upper electrode 24 of the hollow capacitor portion and the hollow portion 23, the upper
electrode 24 and lower portion of the hollow capacitor due to the change of the interelectrode
distance at the time of ultrasonic reception. The voltage change between the electrodes 14 can
be increased, and the reception sensitivity can be increased.
Further, by forming the charge retaining material 35 between the hollow portion 23 and the
upper electrode 24, process damage to the charge retaining material 35 due to heat treatment
such as annealing at the time of forming an ultrasonic sensor element can be significantly
reduced. .
[0096]
Further, by disposing the charge retention material 35 between the opposing electrodes, the
charge supply circuit to the capacitor portion becomes unnecessary, the circuit area can be
reduced, and the size can be reduced.
04-05-2019
25
[0097]
In addition, since the silicon substrate 10 under the lower electrode 14 of the hollow capacitor
portion is opened by the through hole 34, ultrasonic waves can be received with high sensitivity.
[0098]
Although the present invention has been described above by the preferred embodiments, such
descriptions are not restrictive and, of course, various modifications are possible.
For example, in the present embodiment, an ultrasonic sensor has been described as an example
of a semiconductor device provided with a hollow capacitor, but the present invention can be
applied to other acoustic sensitive devices such as a condenser microphone, for example.
[0099]
As described above, the present invention is useful for an ultrasonic sensor or the like in which a
semiconductor circuit is integrated, is suitable for mounting not only on a single body but also in
various electronic devices, and has high industrial utility value.
[0100]
(A) is sectional drawing which showed the structure of the semiconductor device based on the
1st Embodiment of this invention, (b) is the top view.
(A)-(c) is process sectional drawing which showed the manufacturing method of the
semiconductor device concerning the 1st Embodiment of this invention.
(A)-(b) is process sectional drawing which showed the manufacturing method of the
semiconductor device concerning the 1st Embodiment of this invention.
(A) is process sectional drawing which showed the manufacturing method of the semiconductor
device which concerns on the 1st Embodiment of this invention, (b) is a top view which shows
04-05-2019
26
the hollow capacitor part in FIG.2 (b). FIG. 7 is a cross-sectional view showing a modified example
of the semiconductor device in the first embodiment. FIG. 6 is a cross-sectional view showing a
configuration of a semiconductor device according to a second embodiment of the present
invention. (A)-(b) is process sectional drawing which showed the manufacturing method of the
semiconductor device concerning the 2nd Embodiment of this invention. (A)-(b) is process
sectional drawing which showed the manufacturing method of the semiconductor device
concerning the 2nd Embodiment of this invention. It is sectional drawing which showed the
modification of the semiconductor device in the 2nd Embodiment of this invention. It is sectional
drawing which showed the structure of the conventional ultrasonic sensor.
Explanation of sign
[0101]
DESCRIPTION OF SYMBOLS 10 silicon substrate 11a source region 11b drain region 12 gate
electrode 13 thick oxide film (element isolation region) 14 lower electrode 14a, 14c tension film
14b polysilicon film 15 side wall 16, 31 first interlayer insulating layer 17, 17a, 17b , 32 second
interlayer insulating layer 18, 33 third interlayer insulating layer 19, 20, 21 contact hole 22, 27
introduction hole 23 hollow portion 23a communicating hole 24, 24b upper electrode 24a, 24c
tension film 25 wiring 26 surface protective film 28 Wall protective film 29 Sacrificial layer 34
Through hole 35 Charge retention material
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