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JP2008085246

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DESCRIPTION JP2008085246
A semiconductor device manufacturing yield is improved. A lower electrode M0E, insulating films
5 and 7, an upper electrode M1E, and insulating films 9 and 11 are formed on a semiconductor
substrate 1S in a sensor area SA1. A cavity VR1 is formed between the insulating films 5 and 7
above the lower electrode M0E, and a variable capacitance sensor is formed by the lower
electrode M0E, the insulating film 5, the cavity VR1, the insulating film 7 and the upper electrode
M1E. . The cavity VR1 is formed by etching the sacrificial pattern between the insulating films 5
and 7 through the holes 10 formed in the insulating films 7 and 9. Dummy lower electrodes M0E
and insulating films 5, 7, 9, 11 are also formed on the semiconductor substrate 1S in the TEG
regions TA1 other than the sensor region SA1, and the dummy between the insulating films 5
and 7 is formed on the lower electrode M0E. The conductive layer of the same layer as the upper
electrode M1E is not formed on the dummy cavity VR2. [Selected figure] Figure 17
Semiconductor device and method of manufacturing the same
[0001]
The present invention relates to a semiconductor device and a method of manufacturing the
same, and more particularly to an ultrasonic sensor manufactured by MEMS (Micro Electro
Mechanical System) technology and a technology effectively applied to the method of
manufacturing the same.
[0002]
Ultrasonic sensors have been put to practical use in various devices including, for example,
medical ultrasonic echo diagnostic devices and nondestructive inspection ultrasonic flaw
detection devices.
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[0003]
Until now, ultrasonic sensors mainly use the vibration of a piezoelectric body, but with the recent
advance of MEMS technology, development of a capacitance detection type ultrasonic sensor
using MEMS technology has been promoted.
[0004]
In this capacitance detection type ultrasonic sensor, a vibrator having a hollow portion between
electrodes facing each other is formed on a semiconductor substrate, and by applying a DC
voltage and an AC voltage to each electrode in a superimposed manner. The membrane vibrates
near the resonance frequency to generate an ultrasonic wave.
By applying this principle and devising the structure of the electrode, research and development
of a 1.5-dimensional array compatible with short-axis variable focus and a two-dimensional array
compatible with real-time 3D imaging have been conducted.
[0005]
The technology related to such an ultrasonic sensor is described, for example, in US Pat. No.
6,320,239 B1 (Patent Document 1), and a capacitive detection type ultrasonic transducer using a
silicon substrate as a lower electrode is disclosed. .
[0006]
There is also a capacitive detection type ultrasonic transducer of a structure formed on a
patterned lower electrode (see, for example, Patent Document 2 and Non-patent Document 1).
[0007]
Further, for example, US Pat. No. 6,571,445 B2 (Patent Document 3) and US Pat. No. 6,562,650
B2 (Patent Document 4) disclose an ultrasonic transducer of a capacitive detection type on the
upper layer of a signal processing circuit formed on a silicon substrate. A technique is disclosed
for forming
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U.S. Pat. No. 6,320,239 B1 U.S. Pat. No. 6,271,620 B1 U.S. Pat. No. 6,571,445 B2 U.S. Pat. ),
2003, p. 577-580
[0008]
According to the study of the inventor, the following was found.
[0009]
The ultrasonic sensor examined by the present inventor is a capacitive detection type ultrasonic
sensor using MEMS technology.
A plurality of ultrasonic sensor cells (oscillators) are densely arranged in a honeycomb shape on
the main surface of the semiconductor chip constituting the ultrasonic sensor.
[0010]
Each ultrasonic sensor cell has a capacitance detection type cell configuration including a lower
electrode formed on the main surface of the semiconductor chip and an upper electrode disposed
to face the lower electrode via a cavity. ing.
In the ultrasonic sensor having such a configuration, electrostatic force is exerted by applying a
direct current voltage and an alternating current voltage to the lower electrode and the upper
electrode in a superimposed manner, and the membrane located above the cavity vibrates around
the resonance frequency. , Can generate ultrasound.
[0011]
In such an ultrasonic sensor, a cavity can be formed by disposing a sacrificial layer between
insulating films and removing the sacrificial layer by etching through a hole formed in the
insulating film.
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At this time, it is important to prevent the etching residue of the sacrificial layer.
If the ultrasonic sensor is manufactured with the etching residue of the sacrificial layer, the
cavity is not formed into a predetermined shape, and the membrane located above the cavity can
not vibrate well. It will not be possible to fully exhibit the function as a sound wave sensor. For
this reason, the occurrence of the etching residue of the sacrificial layer reduces the
manufacturing yield of the ultrasonic sensor (semiconductor device). In addition, the occurrence
of the etching residue of the sacrificial layer degrades the performance of the ultrasonic sensor
(semiconductor device).
[0012]
However, when the sacrificial layer is etched away from the periphery of the sacrificial layer
while the upper electrode is disposed on the upper side of the sacrificial layer, the sacrificial
layer is gradually etched to form a cavity. It was found that the presence or absence of the
etching residue of the sacrificial layer can not be confirmed by an optical metallurgical
microscope etc.
[0013]
In order to avoid this, the method of forming the cavity before forming the upper electrode on
the top of the sacrificial layer was examined.
However, in order to form the upper electrode after the formation of the cavity, the hole for
forming the cavity needs to be closed in advance with an insulating film such as a silicon oxide
film. Since the insulating film is formed on the top of the cavity, the upper electrode is disposed
above the insulating film, and the distance between the upper electrode and the lower electrode
is increased by the thickness of the insulating film. It has been found that a new problem arises
that the transmission / reception sensitivity (performance) of the ultrasonic sensor
(semiconductor device) is lowered.
[0014]
An object of the present invention is to provide a technology capable of improving the
manufacturing yield of semiconductor devices.
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[0015]
Another object of the present invention is to provide a technology capable of improving the
performance of a semiconductor device.
[0016]
The above and other objects and novel features of the present invention will be apparent from
the description of the present specification and the accompanying drawings.
[0017]
The outline of typical ones of the inventions disclosed in the present application will be briefly
described as follows.
[0018]
The present invention is a semiconductor device having a sensor area in which a plurality of
sensor cells are formed on a main surface, and is formed on a semiconductor substrate, a first
insulating film formed on the semiconductor substrate, and the first insulating film. , A patterned
first conductor layer formed on the second insulating film, and a third insulating film formed on
the second insulating film to cover the first conductor layer And a fourth insulating film formed
on the third insulating film, and each of the plurality of sensor cells is formed between the first
insulating film and the second insulating film in the sensor region. And a first electrode formed of
the first conductor layer and formed on the top of the first cavity, and the second and third
insulating films have the second and third insulating films. A first opening is formed through the
third insulating film to reach the first cavity, the first opening being A second cavity formed
between the first insulating film and the second insulating film in a first region other than the
sensor region on the main surface of the semiconductor device; A second opening which
penetrates the second and third insulating films and reaches the second cavity in the second and
third insulating films, and the second opening is the second The first conductor layer is not
formed on the upper part of the second cavity portion which is closed by the fourth insulating
film and is the farthest from the second opening portion in the second cavity portion.
[0019]
Further, the present invention is a method of manufacturing a semiconductor device having a
sensor area in which a plurality of sensor cells are formed on the main surface, which comprises:
(a) forming a first insulating film on a semiconductor substrate; (1) forming a sacrificial pattern
for forming a cavity on the insulating film, (c) forming a second insulating film on the first
insulating film so as to cover the sacrificial pattern, (d) forming the second insulating film
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Forming a first conductor layer patterned on a film, (e) forming a third insulation film on the
second insulation film so as to cover the first conductor layer, (f) the second And forming an
opening in the third insulating film to expose a part of the sacrificial pattern, (g) selectively
etching the sacrificial pattern through the opening to form the first insulating film and the first
insulating film. Forming a cavity between the two insulating films, (h) g) after the step of forming
a fourth insulating film on the third insulating film so as to close the opening, each of the
plurality of sensor cells includes the hollow portion in the sensor region; And a first electrode
provided on an upper portion of the hollow portion, wherein the first sacrificial pattern of the
sacrificial pattern is formed on the sensor region in the step (b). Forming a second sacrificial
pattern in the first region other than the sensor region, and in the step (f), exposing a part of the
first sacrificial pattern to the second and third insulating films Forming a first opening and a
second opening that exposes a portion of the second sacrificial pattern; in the step (g), the first
and second sacrifices are formed through the first and second openings. The first region is
selectively etched after the pattern is selectively etched. It is to the observation of the etched
state of the second sacrificial pattern.
[0020]
The effects obtained by typical ones of the inventions disclosed in the present application will be
briefly described as follows.
[0021]
The manufacturing yield of the semiconductor device can be improved.
[0022]
In addition, the performance of the semiconductor device can be improved.
[0023]
Before describing the present invention in detail, the meanings of terms in the present
application will be described as follows.
[0024]
1.
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The semiconductor substrate refers to silicon other semiconductor single crystal substrates,
quartz substrates, sapphire substrates, glass substrates, other insulation, anti-insulation or
semiconductor substrates, etc. and composite substrates thereof used for manufacturing
semiconductor integrated circuits.
[0025]
In the following embodiments, when it is necessary for the sake of convenience, it will be
described by dividing into a plurality of sections or embodiments, but they are not unrelated to
each other unless specifically stated otherwise, one is the other And some or all of the variations,
details, and supplementary explanations.
Further, in the following embodiments, when referring to the number of elements (including the
number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited
to a specific number in principle. Except for the specific number, it is not limited to the specific
number, and may be more or less than the specific number.
Furthermore, in the following embodiments, the constituent elements (including element steps
and the like) are not necessarily essential unless explicitly stated or considered to be obviously
essential in principle. Needless to say.
Similarly, in the following embodiments, when referring to the shapes, positional relationships
and the like of components etc., the shapes thereof are substantially the same unless particularly
clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes
things that are similar or similar to etc.
The same applies to the above numerical values and ranges.
[0026]
Hereinafter, embodiments of the present invention will be described in detail based on the
drawings.
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In all the drawings for describing the embodiments, members having the same functions are
denoted by the same reference numerals, and the repetitive description thereof will be omitted.
Further, in the following embodiments, the description of the same or similar parts will not be
repeated in principle unless particularly required.
[0027]
In the drawings used in the embodiments, hatching may be omitted to make the drawing easy to
see even if it is a sectional view.
Further, even a plan view may be hatched to make it easy to see the drawing.
[0028]
First Embodiment A semiconductor device according to the present embodiment is an ultrasonic
wave transmission / reception sensor manufactured using, for example, a MEMS (Micro Electro
Mechanical System) technology.
[0029]
FIG. 1 is an overall plan view of a semiconductor chip 1 constituting the semiconductor device of
the present embodiment.
Although FIG. 1 is a plan view, the TEG area TA1 is hatched in order to make the drawing easy to
see.
[0030]
The semiconductor chip 1 has a first main surface (upper surface, front surface) and a second
main surface (lower surface, back surface) located opposite to each other along the thickness
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direction.
FIG. 1 shows a plan view (that is, a top view) of the first main surface side of the semiconductor
chip 1.
[0031]
As shown in FIG. 1, the planar shape of the semiconductor chip 1 is formed, for example, in a
rectangular shape.
The length of the semiconductor chip 1 in the longitudinal direction (second direction Y) is, for
example, about 4 cm, and the length of the semiconductor chip 1 in the short direction (first
direction X) is, for example, about 1 cm. However, the planar dimension of the semiconductor
chip 1 is not limited to this, and can be variously changed. For example, the length in the
longitudinal direction (second direction Y) is about 8 cm and the length in the short direction
(first direction X) There are various sensors, such as about 1.5 cm.
[0032]
A sensor area (sensor cell array, vibrator array) SA, a plurality of bonding pads (hereinafter
referred to as pads) BP1 and BP2, and a TEG area TA1 (first area) are arranged on the first main
surface of the semiconductor chip 1 It is done.
[0033]
In the sensor area SA, a plurality of lower electrode wirings M0, a plurality of upper electrode
wirings M1 orthogonal to the plurality of lower electrode wirings M0, and a plurality of vibrators
(corresponding to sensor cells and vibrators 20 described later) are arranged.
[0034]
The plurality of lower electrode wirings M0 are formed to extend along the longitudinal direction
(second direction Y) of the semiconductor chip 1, and for example, 16 in the short direction (first
direction X) of the semiconductor chip 1. Channels (hereinafter also referred to as ch) are
arranged side by side.
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[0035]
Lower electrode interconnections M0 are electrically connected to pads BP1, respectively.
A plurality of pads BP1 are provided along the short side of the semiconductor chip 1 so as to
correspond to the lower electrode wiring M0 in the vicinity of both ends of the sensor area SA in
the longitudinal direction (second direction Y) of the semiconductor chip 1 They are arranged
side by side.
[0036]
The plurality of upper electrode wires M1 are formed to extend along the short direction (first
direction X) of the semiconductor chip 1, respectively. For example, 192 ch in the longitudinal
direction (second direction Y) of the semiconductor chip 1 They are arranged side by side.
[0037]
The upper electrode wires M1 are electrically connected to the pads BP2, respectively.
A plurality of pads BP2 are provided along the long side of the semiconductor chip 1 so as to
correspond to the upper electrode wiring M1 in the vicinity of both ends of the semiconductor
chip 1 in the short direction (first direction X). They are arranged side by side.
[0038]
The vibrator (corresponding to the vibrator 20 described later) has, for example, an electrostatic
variable capacitance configuration, and is disposed at the intersection of the lower electrode
wiring M0 and the upper electrode wiring M1.
That is, a plurality of transducers (corresponding to the transducers 20 described later) are
regularly arranged in a matrix (matrix, array) form in the sensor area SA.
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In the sensor area SA, for example, 50 vibrators are arranged in parallel at the intersection of the
lower electrode wiring M0 and the upper electrode wiring M1.
[0039]
Therefore, the sensor area SA is a sensor area in which a plurality of sensor cells (corresponding
to the vibrator 20 described later) are formed, and the semiconductor chip 1 is a sensor in which
a plurality of sensor cells (corresponding to the vibrator 20 described later) are formed. This is a
semiconductor device having the area SA on the main surface (first main surface).
[0040]
The TEG area TA1 is provided on the first main surface of the semiconductor chip 1 outside the
sensor area SA (that is, an area other than the sensor area SA), for example, near the corner of
the first main surface of the semiconductor chip 1 It is arranged.
The planar dimension of the TEG region TA1 can be, for example, about 1 mm × 1 mm. The TEG
area TA1 is an area in which a TEG (Test Element Group) pattern for confirming a wafer process
is formed. In the present embodiment, in the TEG region TA1, a dummy vibrator (corresponding
to a dummy vibrator 20a described later) used to prevent an etching residue of the sacrificial
pattern 6 described later is formed.
[0041]
Next, FIGS. 2 and 3 are plan views (parts enlarged plan views) of main parts of the semiconductor
chip 1, and FIGS. 4 and 5 are cross-sectional views of main parts of the semiconductor chip 1.
FIGS. 2 and 4 show a plan view and a sectional view of an essential part of a main body area SA1
of the semiconductor chip 1 (an area obtained by combining the sensor area SA and the area
where the bonding pads BP1 and BP2 are formed). FIG. 5 shows a plan view and a cross-sectional
view of main parts of the TEG region TA1 of the semiconductor chip 1. 4 substantially
corresponds to the cross-sectional view taken along line X1-X1 of FIG. 2, and FIG. 5 substantially
corresponds to the cross-sectional view taken along line X2-X2 of FIG. FIG. 2 is a plan view in the
case where one vibrator is disposed at the intersection of the lower electrode wiring M0 and the
upper electrode wiring M1. For simplicity, in FIG. 2 (body region), the lower electrode wiring M0
is 2ch, the upper electrode wiring M1 is 3ch, and the vibrator 20 located at each intersection of
each lower electrode wiring M0 and each upper electrode wiring M1 is shown. A plan view of
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one case is shown. Further, FIG. 3 (TEG area TA1) shows one dummy vibrator 20a.
[0042]
A semiconductor substrate 1S constituting the semiconductor chip 1 is made of, for example,
silicon (Si) single crystal, and a first main surface (upper surface, surface) 1Sa and a second main
surface (lower surface) opposite to each other along the thickness direction , Back surface) 1Sb.
As shown in FIGS. 2 and 4, the plurality of vibrators 20 are disposed (formed) on the first main
surface 1Sa of the semiconductor substrate 1S via the insulating film 2 made of, for example,
silicon oxide (SiO.sub.2 etc.) ).
[0043]
As shown in FIG. 3, each of the plurality of transducers 20 is formed, for example, in a planar
hexagonal shape, and is arranged, for example, in a honeycomb shape. As a result, the plurality of
transducers 20 can be disposed at high density, and sensor performance can be improved.
[0044]
Each vibrator 20 has a lower electrode M0E, an upper electrode M1E provided to face the lower
electrode M0E, and a cavity (first cavity) VR1 interposed between these electrodes. There is.
[0045]
The lower electrode M0E is formed at a portion where the upper electrode wiring M1 overlaps in
plan view in the lower electrode wiring M0.
That is, lower electrode M0E of each vibrator 20 is formed by a part of lower electrode wire M0,
and a portion of lower electrode wire M0 overlapping in plan with upper electrode wire M1 (ie,
below upper electrode wire M1). The portion located on the lower electrode M0E is the lower
electrode M0E. The lower electrode M0E and the lower electrode wiring M0 are made of a
conductor layer (laminated film 3), and formed, for example, by sequentially laminating a
titanium nitride (TiN) film 3a, an aluminum (Al) film 3b and a titanium nitride film 3c from the
lower layer. It is done. A tungsten (W) film may be used instead of the titanium nitride film 3c.
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[0046]
From the viewpoint of reducing the step due to the thickness of lower electrode M0E and lower
electrode wiring M0, side walls (sidewall insulating film, insulating film, etc.) are formed on the
side surfaces of lower electrode M0E and lower electrode wiring M0. Sidewall spacer SW is
formed. The surfaces of lower electrode M0E, lower electrode interconnection M0, insulating film
2 and sidewall SW are covered with insulating film 5 made of, for example, silicon oxide or the
like.
[0047]
On the insulating film 5, an insulating film 7 made of, for example, a silicon oxide film is
deposited. The upper electrode M1E is provided on the insulating film 7 so as to face the lower
electrode M0E.
[0048]
The upper electrode M1E is formed in a portion where the lower electrode wiring M0 overlaps in
plan view in the upper electrode wiring M1. That is, the upper electrode M1E of each vibrator 20
is formed by a part of the upper electrode wiring M1, and a portion of the upper electrode wiring
M1 overlapping in plan with the lower electrode wiring M0 (ie, above the lower electrode wiring
M0 The upper electrode M1E is a portion located on the The planar shape of the upper electrode
M1E is formed in a substantially hexagonal shape, and the upper electrode wiring M1 is formed
in a pattern wider than the connecting portion M1C which extends in the first direction X and
connects the upper electrodes M1E. There is. As described above, the upper electrode wiring M1
includes the plurality of upper electrodes M1E and the connecting portion M1C that connects the
upper electrodes M1E adjacent in the first direction X.
[0049]
The upper electrode wiring M1 including the upper electrode M1E and the connection portion
M1C is made of a conductor layer (laminated film 8), and for example, a titanium nitride (TiN)
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film 8a, an aluminum (Al) film 8b and a titanium nitride (TiN) film 8c are lower layers It is formed
by laminating | stacking in order from. A tungsten film may be used instead of the titanium
nitride film 8c.
[0050]
The hollow portion VR1 is formed between the lower electrode M0E and the upper electrode
M1E (between the insulating film 5 and the insulating film 7). The planar shape of the hollow
portion VR1 is formed, for example, in a hexagonal shape.
[0051]
An insulating film 9 made of, for example, a silicon nitride (Si3N4 or the like) film is deposited on
the insulating film 7 so as to cover the upper electrode wiring M1 including the upper electrode
M1E and the coupling portion M1C. In the insulating films 7 and 9, in the vicinity of the
hexagonal portion of the hollow portion VR1, holes (openings, contact holes, through holes) 10
reaching the hollow portion VR1 are formed. The hole 10 is a hole (a hole for forming a cavity
VR1) for etching a sacrificial pattern (a sacrificial pattern 6 described later) between the
insulating films 5 and 7 through the hole 10 to form a cavity VR1 as described later. It is.
[0052]
An insulating film 11 made of, for example, a silicon nitride film is deposited on the insulating
film 9. A part of the insulating film 11 is in the hole 10, whereby the hole 10 is closed.
[0053]
In the insulating films 5, 7, 9 and 11, an opening 12 a reaching a part of the lower electrode
wiring M <b> 0 is formed. A part of the lower electrode wiring M0 exposed from the opening 12a
is the pad BP1. In the insulating films 9 and 11, an opening 12b reaching a part of the upper
electrode wiring M1 is formed. A part of the upper electrode wiring M1 exposed from the
opening 12b is the pad BP2.
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[0054]
On the insulating film 11, an insulating film (protective film) 13 made of, for example, a negative
photosensitive polyimide film is deposited.
[0055]
Openings 14 a and 14 b are formed in the insulating film 13.
Among these, the opening 14a is formed at a position and a planar size that planarly encloses the
opening 12a, and a part of the lower electrode wiring M0 exposed from the opening 14a is the
pad BP1. The opening 14b is formed to have a planar size and a position that includes the
opening 12b in a planar manner, and a part of the upper electrode wiring M1 exposed from the
opening 14b is the pad BP2. The pads BP1 and BP2 are terminals for input and output of the
semiconductor chip 1, and bonding wires and the like are electrically connected to the pads BP1
and BP2.
[0056]
The insulating film 13 has a function as a protective film for protecting the plurality of vibrators
20 on the first main surface of the semiconductor chip 1 in a dicing step or the like for cutting
the semiconductor chip 1 from the semiconductor wafer. If unnecessary, the formation of the
insulating film 13 can be omitted, and the insulating film 11 can be used as the uppermost layer
film (protective film).
[0057]
In the semiconductor chip 1, the vibrator 20 as described above is formed in the sensor area SA.
The semiconductor chip 1 of the present embodiment is further formed on the first main surface
1Sa of the semiconductor substrate 1S as shown in FIGS. 3 and 5 in the area other than the
sensor area SA (here, the TEG area TA1). A dummy vibrator 20 a is disposed (formed) via the
insulating film 2.
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[0058]
The dummy vibrator 20a has the same shape as the vibrator 20, and is formed in, for example, a
planar hexagonal shape. The dummy vibrator 20 a has a dummy lower electrode M 0 E 2 and a
dummy hollow portion (second hollow portion) VR 2 which are substantially similar to the lower
electrode M 0 E of the vibrator 20 and the hollow portion VR 1. There is no equivalent to the
upper electrode M1E.
[0059]
The dummy lower electrode M0E2 is formed by (the pattern of) the conductive layer in the same
layer as the lower electrode M0E (lower electrode wiring M0), and the dummy cavity VR2 is
formed by the cavity in the same layer as the cavity VR1. It is done. Therefore, as described
above, when lower electrode M0E and lower electrode wiring M0 are formed of a laminated film
in which titanium nitride (TiN) film 3a, aluminum (Al) film 3b and titanium nitride film 3c are
sequentially laminated from the lower layer, The dummy lower electrode M0E2 is also a
laminated film in which a titanium nitride (TiN) film 3a, an aluminum (Al) film 3b and a titanium
nitride film 3c are sequentially laminated from the lower layer. A tungsten (W) film may be used
instead of the titanium nitride film 3c.
[0060]
Similar to lower electrode M0E and lower electrode wiring M0, sidewall SW is formed on the side
surface of dummy lower electrode M0E2, and insulating film 5 is formed on the surface of
dummy lower electrode M0E2 and sidewall SW on the side surface. Covered by An insulating film
7 is deposited on the insulating film 5. Above the dummy lower electrode M0E2, a dummy cavity
VR2 having the same shape (same size) as the cavity VR1 is formed between the insulating film 5
and the insulating film 7. The hollow portion VR1 and the dummy hollow portion VR1 have
substantially the same planar shape. Therefore, the dummy hollow portion VR2 is also formed,
for example, in a hexagonal shape, similarly to the hollow portion VR1. The cavity VR1 of the
sensor area SA and the dummy cavity VR2 of the TEG area TA1 have substantially the same
thickness (dimension in the direction perpendicular to the first major surface 1Sa of the
semiconductor substrate 1S).
[0061]
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In the sensor area SA, the upper electrode M1E is provided on the insulating film 7 so as to face
the lower electrode M0E. However, in the TEG area TA1, the upper electrode is disposed above
the dummy lower electrode M0E2. There is no equivalent to M1E.
[0062]
The insulating film 9 is deposited on the insulating film 7, and holes (openings reach the dummy
cavity VR2 in the vicinity of the hexagonal portion of the dummy cavity VR2 in the insulation
films 7 and 9 of the TEG region TA1. , Contact holes, through holes) 10a are formed.
As described later, the hole 10a is a hole (dummy cavity VR2 for forming a dummy cavity VR2 by
etching a sacrificial pattern (sacrifice pattern 6a described later) between the insulating films 5
and 7 through the hole 10a. Hole for the The position (formation position) of the hole 10 with
respect to the cavity VR1 and the position (formation position) of the hole 10a with respect to
the dummy cavity VR2 are substantially the same.
[0063]
Also in the TEG region TA1, the insulating film 11 is deposited on the insulating film 9. A part of
the insulating film 11 intrudes into the hole 10a, whereby the hole 10a is closed. An insulating
film (protective film) 13 is deposited on the insulating film 11. As described above, if
unnecessary, the formation of the insulating film 13 can be omitted, and the insulating film 11
can be used as the uppermost layer film (protective film).
[0064]
As described above, the semiconductor chip (semiconductor device) 1 of the present embodiment
is a semiconductor device having the sensor area SA in which the plurality of sensor cells
(vibrator 20) are formed on the main surface, and the semiconductor substrate 1S and the
semiconductor substrate An insulating film 5 (first insulating film) formed on 1S, an insulating
film 7 (second insulating film) formed on the insulating film 5, and a patterned first formed on
the insulating film 7 Conductor layer (here, a laminated film 8 of titanium nitride film 8a,
aluminum film 8b and titanium nitride film 8c) and insulating film 9 (third insulating film)
formed on insulating film 7 so as to cover the first conductor layer And the insulating film 11
04-05-2019
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(fourth insulating film) formed on the insulating film 9. Each of the plurality of sensor cells
(vibrator 20) of the semiconductor chip 1 has a cavity VR1 (first cavity) formed between the
insulating film 5 and the insulating film 7 in the sensor area SA, and the first A conductor layer
(here, a laminated film 8 of a titanium nitride film 8a, an aluminum film 8b and a titanium nitride
film 8c), and an upper electrode M1E (first electrode) formed on the upper portion of the cavity
VR1. In the sensor area SA, a hole 10 (first opening) which penetrates the insulating films 7 and
9 and reaches the cavity VR1 is formed in the insulating films 7 and 9, and the hole 10 is closed
by the insulating film 11. It is done. Furthermore, the semiconductor chip 2 is a dummy formed
between the insulating film 5 and the insulating film 7 in the first region (here, TEG region TA1)
other than the sensor region SA in the main surface having the sensor region SA. A cavity VR2
(second cavity) is provided, and a hole 10a (second opening) is formed in the insulating films 7
and 9 to reach the dummy cavity VR2 through the insulating films 7 and 9. The holes 10 a are
closed by the insulating film 11. Then, the first conductor layer (here, the laminated film 8) is not
formed in the upper part of the dummy cavity VR2 farthest from the hole 10a, and in the present
embodiment, the dummy cavity is formed. The first conductor layer (here, the laminated film 8)
is not formed above the portion VR2 (however, in the second embodiment described later, the
first conductor layer (the laminated film 8 is formed above the dummy cavity VR2). ) Is formed).
[0065]
The semiconductor chip 1 further includes a patterned second conductor layer (here, a laminated
film 3 of the titanium nitride film 3a, the aluminum film 3b and the titanium nitride film 3c)
formed on the semiconductor substrate 1S, and insulating The film 5 is formed on the
semiconductor substrate 1S so as to cover the second conductor layer (here, the laminated film
3), and each of the plurality of sensor cells (vibrator 20) of the semiconductor chip 1 is in the
sensor area SA. A lower electrode M0E (second electrode) formed of the second conductor layer
(here, the laminated film 3) and formed below the cavity VR1 is further included. The second
conductor layer (here, the laminated film 3) is formed as a dummy lower electrode M0E2 below
the dummy cavity VR2. Each of a plurality of sensor cells (vibrator 20) of the semiconductor chip
2 has a lower electrode M0E (first electrode), an upper electrode M1E (second electrode), an
insulating film 5 between the lower electrode M0E and the upper electrode M1E, and a cavity
This is a variable capacitance sensor formed by the portion VR1 and the insulating film 7. On the
other hand, the dummy cavity VR2 is a cavity not used as a sensor, and the dummy lower
electrode M0E2 is a dummy lower electrode not used as a sensor.
[0066]
04-05-2019
18
In the ultrasonic transmission / reception sensor having such a configuration, electrostatic force
is exerted by superimposing DC and AC voltages on lower electrode wiring M0 (lower electrode
M0E) and upper electrode wiring M1 (upper electrode M1E), and each vibration A direction
(vertical direction in FIG. 3) in which the membrane (membrane located above the cavity VR1) of
the child 20 crosses the first main surface 1Sa of the semiconductor substrate 1S near the
resonance frequency by balance with the force of the spring of the membrane. ) To generate
several megahertz ultrasonic waves (ultrasonic pulse). In the case of reception, the pressure of
the ultrasonic wave reaching the membrane of each transducer 20 vibrates the membrane, and
the capacitance between the lower electrode M0E and the upper electrode M1E changes, thereby
detecting the ultrasonic wave. can do. That is, the displacement of the space between the lower
electrode M0E and the upper electrode M1E due to the reflected wave is detected as a change in
electrostatic capacitance (electrostatic capacitance of each vibrator 20).
[0067]
Next, a method of manufacturing the semiconductor device of the present embodiment will be
described with reference to FIGS. 6 to 17 are main-portion cross-sectional views of the
semiconductor device in the present embodiment during the manufacturing process thereof, and
show main-portion cross-sectional views of the main body area SA1 and the TEG area TA1. The
main body area SA1 shown in FIGS. 6 to 17 is an area corresponding to the left half of FIG. The
TEG area TA1 shown in FIGS. 6 to 17 is an area corresponding to FIG.
[0068]
In order to manufacture the semiconductor chip 1, first, as shown in FIG. 6, a semiconductor
substrate (in this stage, a semiconductor thin plate in a substantially circular shape called a
semiconductor wafer in this stage) 1S is prepared. The semiconductor substrate 1S is made of,
for example, silicon single crystal, and has a first main surface (upper surface, front surface) 1Sa
and a second main surface (lower surface, back surface) 1Sb located opposite to each other along
the thickness direction. .
[0069]
Next, over the entire surface of the first main surface 1Sa of the semiconductor substrate 1S, the
insulating film 2 made of, for example, a silicon oxide (SiO 2 or the like) film is formed
04-05-2019
19
(deposited). The film thickness of the insulating film 2 can be, for example, about 400 nm.
[0070]
Next, a titanium nitride (TiN) film 3a is formed on the insulating film 2, an aluminum (Al) film 3b
is formed on the titanium nitride film 3a, and a titanium nitride (TiN) film 3c is formed on the
aluminum film 3b. . Thereby, a laminated film (conductor layer, second conductor layer) 3 of the
titanium nitride film 3a, the aluminum film 3b and the titanium nitride film 3c is formed. The
aluminum film 3 b is made of a conductor film containing aluminum as a main component, such
as an aluminum single film or an aluminum alloy film. The titanium nitride film 3a, the aluminum
film 3b, and the titanium nitride film 3c constituting the laminated film 3 can be formed by using,
for example, a sputtering method. Further, since the aluminum film 3b is a main conductor film
of the lower electrode wiring M0, the film thickness of the aluminum film 3b is thicker than the
film thicknesses of the titanium nitride films 3a and 3c, for example, the film thickness of the
titanium nitride film 3a is 50 nm The thickness of the aluminum film 3b can be about 500 nm,
and the thickness of the titanium nitride film 3c can be about 50 nm.
[0071]
Alternatively, after a titanium (Ti) film is formed on the insulating film 2, the titanium nitride film
3a can be formed on the titanium film. Alternatively, after a titanium (Ti) film is formed on the
aluminum film 3b, the titanium nitride film 3c can be formed on the titanium film. Also, a
tungsten (W) film or the like can be used instead of the titanium nitride films 3a and 3c.
[0072]
Next, as shown in FIG. 7, the laminated film 3 is patterned (processed, selectively removed) using
a lithography method, a dry etching method, or the like. A lower electrode wiring M0 (lower
electrode M0E) and a dummy lower electrode M0E2 are formed by the laminated film (conductor
layer, second conductor layer) 3 patterned.
[0073]
04-05-2019
20
Thus, the lower electrode wiring M0 and the dummy lower electrode M0E2 are formed on (the
insulating film 2 of) the semiconductor substrate 1S. The lower electrode wiring M0 and the
dummy lower electrode M0E2 are formed on (the insulating film 2 on) the semiconductor
substrate 1S, and are formed of the conductor layer (the laminated film 3 here) of the same layer
patterned (patterned). Since lower electrode interconnection M0 and dummy lower electrode
M0E2 are formed of the laminated film of the patterned metal film (aluminum film 3b) and metal
nitride film (titanium nitride films 3a and 3c) as described above, It can be regarded.
[0074]
The lithography method (photolithography method) is a method of patterning a resist film into a
desired pattern (resist pattern) by a series of steps of application of a resist film (photoresist
film), exposure and development.
[0075]
Further, the lowermost titanium nitride film 3a of the laminated film 3 can function to improve
the adhesion (adhesiveness) between the insulating film 2 and the lower electrode wiring M0
(laminated film 3). .
The aluminum film 3b of the laminated film 3 is a main conductor film of the lower electrode
wiring M0, and the lower electrode wiring is formed by forming the aluminum film 3b with a
conductor film mainly composed of aluminum such as aluminum or aluminum alloy. It is possible
to reduce the resistance of M0. The titanium nitride film 3c of the uppermost layer of the
laminated film 3 can function as an antireflective film in the exposure step of the lithography
(photolithography) process at the time of patterning the laminated film 3. In addition, the
titanium nitride film 3c of the uppermost layer of the laminated film 3 can function to relieve the
unevenness on the upper surface of the aluminum film 3b and to improve the flatness of the
upper surface of the lower electrode wiring M0.
[0076]
Next, a silicon oxide film or the like is formed on the entire first surface 1Sa of the semiconductor
substrate 1S (semiconductor wafer) (ie, on the insulating film 2) to cover the surfaces of the
lower electrode wiring M0 and the dummy lower electrode M0E2. The lower electrode wiring M0
(lower electrode M0E) and the lower portion of the dummy are formed by depositing the
insulating film and etching back the entire surface of the insulating film by anisotropic dry
etching, as shown in FIG. An insulating film is left on the side surface (side wall) of the electrode
04-05-2019
21
M0E2 to form a sidewall (sidewall insulating film) SW, and the upper surfaces of the lower
electrode wiring M0 and the dummy lower electrode M0E2 are exposed.
[0077]
Next, as shown in FIG. 9, lower electrode interconnection M0 (lower electrode M0E), dummy
lower electrode M0E, and side electrodes are formed over the entire first surface 1Sa of
semiconductor substrate 1S (that is, on insulating film 2). An insulating film 5 is formed
(deposited) so as to cover the surface of the wall SW.
The insulating film 5 is made of, for example, a silicon oxide film, and can be formed using a CVD
method or the like. The thickness of the insulating film 5 is, for example, about 200 nm.
[0078]
Next, as shown in FIG. 9, a sacrificial film 6b made of, for example, a polycrystalline silicon film is
formed (deposited) over the entire surface of the insulating film 5 of the first main surface 1Sa of
the semiconductor substrate 1S. The sacrificial film 6b can be formed, for example, by the CVD
method, and its thickness (deposited thickness) can be, for example, about 100 nm.
[0079]
Next, as shown in FIG. 10, the sacrificial film 6b is patterned by lithography and dry etching to
form a sacrificial pattern (a sacrificial pattern for forming a cavity) 6, 6a made of the patterned
sacrificial film 6b. Form. Among them, the sacrificial pattern (first sacrificial pattern) 6 is a
pattern for forming the cavity VR1 and is formed in the sensor area SA, and the sacrificial pattern
(second sacrificial pattern) 6a is the dummy cavity VR2 It is a pattern to be formed, and is
formed in an area (first area) other than the sensor area SA, in this case, the TEG area TA1.
Therefore, the planar shape of the sacrificial pattern 6 is formed in the same planar shape as that
of the cavity VR1, and the planar shape of the sacrificial pattern 6a is formed in the same planar
shape as the dummy cavity VR2. Therefore, the sacrificial pattern 6 is formed in the cavity VR1
formation planned region of (the sensor area SA) of the main body area SA1, and the sacrificial
pattern 6a is formed in the dummy cavity VR2 formation planned region of the TEG area TA1.
04-05-2019
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[0080]
Next, as shown in FIG. 11, over the entire first surface 1Sa of the semiconductor substrate 1S
(that is, over the insulating film 5), the insulating film 7 is formed so as to cover the surfaces of
the sacrificial patterns 6, 6a. (accumulate. The insulating film 7 is made of, for example, a silicon
oxide film, and can be formed using a CVD method or the like. The thickness of the insulating
film 7 can be, for example, about 200 nm.
[0081]
Next, a titanium nitride (TiN) film 8a is formed on the insulating film 7, an aluminum (Al) film 8b
is formed on the titanium nitride film 8a, and a titanium nitride (TiN) film 8c is formed on the
aluminum film 8b. . Thereby, a laminated film (conductor layer, first conductor layer) 8
composed of the titanium nitride film 8 a, the aluminum film 8 b and the titanium nitride film 8 c
is formed on the insulating film 7. The aluminum film 8 b is made of a conductor film containing
aluminum as its main component, such as an aluminum single film or an aluminum alloy film.
The titanium nitride film 8a, the aluminum film 8b, and the titanium nitride film 8c constituting
the laminated film 8 can be formed by using, for example, a sputtering method. Further, since the
aluminum film 8b is a main conductor film of the upper electrode wiring M1, the film thickness
of the aluminum film 8b is larger than the film thicknesses of the titanium nitride films 8a and
8c. Further, the total thickness of the laminated film 8 for forming the upper electrode wiring can
be thinner than the total thickness of the laminated film 3 for forming the lower electrode wiring,
for example, about 400 nm. In this case, the film thicknesses of the titanium nitride film 8a, the
aluminum film 8b, and the titanium nitride film 8c can be, for example, about 50 nm, 300 nm,
and 50 nm, respectively.
[0082]
Alternatively, after a titanium (Ti) film is formed on the insulating film 7, the titanium nitride film
8a can be formed on the titanium film. Alternatively, a titanium (Ti) film may be formed on the
aluminum film 8b, and then a titanium nitride film 8c may be formed on the titanium film. Also, a
tungsten (W) film or the like can be used instead of the titanium nitride films 8a and 8c.
[0083]
04-05-2019
23
Next, as shown in FIG. 12, the laminated film 8 is patterned (processed, selectively removed)
using a lithography method, a dry etching method, or the like. An upper electrode wiring M1
(upper electrode M1E and connection portion M1C) is formed by the laminated film (conductor
layer, first conductor layer) 8 patterned. Thereby, the upper electrode wiring M1 is formed on
the insulating film 7. The upper electrode wiring M1 is formed on the insulating film 7 and is
formed of a patterned (patterned) conductor layer (here, the laminated film 8). Since the upper
electrode wiring M1 is formed of the laminated film of the metal film (aluminum film 8b) and the
metal nitride film (titanium nitride films 8a and 8c) patterned as described above, it can be
regarded as a metal film pattern. In the present embodiment, the laminated film 8 does not
remain on the sacrificial pattern 6a in the TEG region TA1.
[0084]
The functions of the titanium nitride film 8a, the aluminum film 8b and the titanium nitride film
8c of the laminated film 8 are substantially the same as those of the titanium nitride film 3a, the
aluminum film 3b and the titanium nitride film 3c of the laminated film 3 described above. Since
there is, the explanation is omitted here.
[0085]
Next, as shown in FIG. 13, over the entire first surface 1Sa of the semiconductor substrate 1S
(that is, over the insulating film 7), the upper electrode wiring M1 (upper electrode M1E,
patterned laminated film 8) Forming (depositing) the insulating film 9 so as to cover the
The insulating film 9 is made of, for example, a silicon nitride (Si3N4 or the like) film or the like,
and can be formed using a CVD method or the like. The thickness of the insulating film 9 can be,
for example, about 500 nm.
[0086]
Next, as shown in FIG. 14, the insulating films 9 and 7 are made to reach the sacrificial patterns 6
and 6a and expose a part of the sacrificial patterns 6 and 6a using lithography and dry etching.
Form the holes (openings) 10 and 10a. Among these, the hole 10 (first opening) is formed at a
position overlapping the sacrificial pattern 6 in a plan view, and a part of the sacrificial pattern 6
04-05-2019
24
is exposed at the bottom of the hole 10, and the hole 10a (second opening) Is formed in a
position overlapping with the sacrificial pattern 6a in a planar manner, and a portion of the
sacrificial pattern 6a is exposed at the bottom of the hole 10a.
[0087]
Next, the sacrificial patterns 6 and 6a are selectively wet etched with, for example, a potassium
hydroxide solution through the holes 10 and 10a. As a result, as shown in FIG. 15, the sacrificial
patterns 6, 6a are removed, and a cavity (first cavity) VR1 between the insulating film 5 and the
insulating film 7 and a dummy cavity (second cavity) Part) VR2 is formed. The region where the
sacrificial pattern 6 was present becomes the cavity VR1, and the region where the sacrificial
pattern 6a was present becomes the dummy cavity VR2.
[0088]
That is, in (the sensor area SA of) the main body area SA1, the hollow portion VR1 is between the
opposing surfaces of the lower electrode wiring M0 (the lower electrode M0E) and the upper
electrode wiring M1 (the upper electrode M1E). In the TEG region TA1, a dummy cavity VR2 is
formed above the dummy lower electrode M0E2. Thus, the cavity VR1 and the dummy cavity
VR2 can be formed by selectively etching the sacrificial patterns 6, 6a through the holes 10, 10a.
[0089]
In the lower electrode wiring M0, the portion facing the upper electrode wiring M1 via the cavity
VR1 is the lower electrode M0E, and in the upper electrode wiring M1, the portion facing the
lower electrode wiring M0 via the cavity VR1 is It is the upper electrode M1E.
[0090]
Further, in the present embodiment, after selectively etching (wet etching) the sacrificial patterns
6 and 6a through the holes 10 and 10a, the etching state of the sacrificial pattern 6a in the TEG
region TA1 is observed. It will be described in more detail.
[0091]
04-05-2019
25
Next, as shown in FIG. 16, the insulating film 11 is formed (deposited) over the entire first
surface 1Sa of the semiconductor substrate 1S (that is, on the insulating film 9).
Thereby, a part of the insulating film 11 can be embedded in the holes 10 and 10a to close the
holes 10 and 10a.
The insulating film 11 is made of, for example, a silicon nitride film or the like, and can be
formed using a plasma CVD method or the like. In addition, the thickness of the insulating film
11 can be, for example, about 800 nm.
[0092]
Next, as shown in FIG. 17, in the insulating films 11, 9, 7 and 5, one of the openings 12 a where
part of the lower electrode wiring M 0 is exposed and one of the upper electrode wiring M 1 in
the insulating films 11 and 9. An opening 12b (not shown in FIG. 17) in which the portion is
exposed is formed by the lithography method and the dry etching method. Thus, the vibrator 20
of the electrostatic variable capacitance configuration is formed. Although the dummy vibrator
20a is formed by the dummy lower electrode M0E and the dummy cavity portion VR1 at the
upper part thereof, the dummy vibrator 20a is not used electrically, so the dummy lower
electrode M0E is exposed. The openings do not have to be provided in the insulating films 11, 9,
7, 5.
[0093]
Next, as shown in FIG. 4 and FIG. 5, an insulating film formed of, for example, a negative
photosensitive polyimide film or the like on the entire first surface 1Sa of the semiconductor
substrate 1S (that is, on the insulating film 11). Form 13. Then, openings 14a and 14b are
formed in the insulating film 13 such that portions of the lower electrode wiring M0 and the
upper electrode wiring M1 are exposed by exposure and development processing or the like.
Parts of the lower electrode wiring M0 and the upper electrode wiring M1 exposed from the
openings 14a and 14b become the pads BP1 and BP2.
[0094]
04-05-2019
26
Thereafter, the semiconductor chip 1 can be manufactured by cutting out individual chip regions
from the semiconductor substrate 1S (semiconductor wafer) by dicing.
[0095]
Next, among the above manufacturing steps, the step of wet etching the sacrificial patterns 6, 6a
through the holes 10, 10a will be described in more detail.
[0096]
FIG. 18 is a manufacturing process flow diagram of a part of the manufacturing process of the
semiconductor device of the present embodiment (the above-described steps of FIGS. 14 to 16),
and FIG. 19 is a manufacturing showing the step of FIG. It is a process flow figure.
20 and 21 are plan views of relevant parts in the process of manufacturing a semiconductor
device in the present embodiment.
FIG. 20 corresponds to the same process step as FIG. 14 described above, and FIG. 21
corresponds to the same process step as FIG.
[0097]
In each of FIGS. 20 and 21, the area corresponding to one vibrator 20 formed in the sensor area
SA is shown in “(a) sensor area SA” on the left of the figure, and is formed in the TEG area TA1.
A region corresponding to one dummy transducer to be performed is shown in “(b) TEG region
TA1” on the right side of the figure. 20 and 21 illustrate planar patterns of the sacrificial
patterns 6, 6a, the holes 10, 10a, the upper electrode wiring M1 (upper electrode M1E), the
cavity VR1 and the dummy cavity VR2, other components The illustration is omitted. Therefore,
FIGS. 20 and 21 see through the insulating films 5, 7 and 9. Although FIGS. 20 and 21 are plan
views, the sacrificial patterns 6, 6a, the holes 10, 10a and the upper electrode wiring M1 (upper
electrode M1E) are hatched in order to make the drawings easy to see.
[0098]
The process described above with reference to FIGS. 6 to 14, that is, the process of forming the
04-05-2019
27
holes 10 and 10 a reaching the sacrificial patterns 6 and 6 a in the insulating films 9 and 7 (step
S 1) is performed. 14 and the corresponding structure of FIG. 20 are obtained.
[0099]
Next, the sacrificial patterns 6 and 6a are selectively wet-etched with a potassium hydroxide
solution, for example, through the holes 10 and 10a to form the cavity VR1 and the dummy
cavity VR2 (step S2).
Thus, the structure of FIG. 15 and the corresponding structure of FIG. 21 are obtained.
[0100]
The step of wet etching the sacrificial patterns 6, 6a in step S2 to form the cavity VR1 and the
dummy cavity VR2 is configured by the following steps S2a to S2d.
[0101]
That is, the etching time is set in advance, and the semiconductor substrate (semiconductor
wafer) 1S is wet-etched with, for example, a potassium hydroxide solution for a predetermined
etching time using a wet etching apparatus, whereby holes are formed. The sacrificial patterns 6
and 6a are selectively wet-etched through 10 and 10a (step S2a).
[0102]
After completion of the etching in step S2a, the semiconductor substrate (semiconductor wafer)
1S is subjected to cleaning (for example, water cleaning) and drying, and then the semiconductor
substrate (semiconductor wafer) 1S is taken out from the wet etching apparatus (step S2b).
[0103]
Next, the etching state (etching amount, presence or absence of etching remaining) of the
sacrificial pattern 6a in the TEG area TA1 is observed (confirmed) using an optical microscope
(optical metal microscope) or the like (step S2c).
04-05-2019
28
Then, it is judged (judged and observed) whether the etching amount of the sacrificial pattern 6a
observed in step S2c is insufficient or sufficient (step S2d).
[0104]
If it is determined in step S2d that the etching amount of the sacrificial pattern 6a is sufficient (in
this case, it is estimated that there is no etching residue of the sacrificial pattern 6 in the sensor
area SA), the semiconductor substrate (semiconductor wafer) 1S is followed. Proceed to the step
(step of forming the insulating film 11).
If it is determined in step S2d that the etching amount of the sacrificial pattern 6a is insufficient
(in this case, it is estimated that there is an etching residue of the sacrificial pattern 6 in the
sensor area SA), the semiconductor substrate (semiconductor wafer) 1S is used. It returns to a
wet etching device again, and the process of step S2a-S2d is repeated.
[0105]
In the sensor area SA, since the upper electrode wiring M1 (upper electrode M1E) exists above
the sacrificial pattern 6, sacrificial metal is used from the surface side of the semiconductor
substrate 1S (upper side of the first main surface 1Sa) using an optical metallographic
microscope Even if it is going to observe the etching state (presence or absence of etching
residue) of the pattern 6, since the upper electrode wiring M1 blocks (hinders) the transmission
of light, it is observed whether the sacrificial pattern 6 remains under the upper electrode wiring
M1. It is not possible.
This is because the metal film reflects almost 100% of visible light, so it is not possible to observe
the state under the upper electrode wiring M1 (etched state of the sacrificial pattern 6) through
the upper electrode wiring M1 made of the metal film. It is for.
[0106]
However, in the TEG region TA1, a metal pattern (corresponding to the upper electrode wiring
M1) is not formed on the sacrificial pattern 6a. Therefore, when observing the etching state of
04-05-2019
29
the sacrificial pattern 6a from the surface side of the semiconductor substrate 1S (the upper side
of the first main surface 1Sa) using an optical metallurgical microscope or the like, the sacrificial
pattern 6 and the dummy cavity VR2 are Since light can be transmitted to the inside, the etching
state (presence or absence of etching remaining) of the sacrificial pattern 6a can be observed.
Therefore, in the step S2c, as indicated by the arrows in FIG. 15, from the surface side (upper
side of the first major surface 1Sa) of the semiconductor substrate (semiconductor wafer) 1S
using an optical microscope (optical metallurgical microscope) or the like. It is possible to
determine the etching amount (presence or absence of etching remaining) of the sacrificial
pattern 6 a by observing the etching state of the sacrificial pattern 6 a from the direction 21.
[0107]
Further, in the present embodiment, since the etching residue of the sacrificial pattern 6a can be
visually observed using an optical metallographic microscope or the like, the etching amount
(presence or absence of the etching residue) of the sacrificial pattern 6a is determined easily and
accurately. be able to.
[0108]
Further, in the present embodiment, the sacrificial pattern 6a of the TEG region TA1 is formed to
have substantially the same shape and the same dimensions as the sacrificial pattern 6 of the
sensor region SA.
Further, the positions of the holes 10 a in the sacrificial pattern 6 a are substantially the same as
the positions of the holes 10 in the sacrificial pattern 6. Therefore, when the sacrificial patterns 6
and 6a are etched in step S2a, the etching state of the sacrificial pattern 6a in the TEG area TA1
and the etching state of the sacrificial pattern 6 in the sensor area SA are substantially the same.
Therefore, by observing the sacrificial pattern 6a in the TEG region TA1 in step S2c, it is possible
to estimate the etching state of the sacrificial pattern 6 in the sensor region SA. That is, as shown
in FIG. 21, when there is no etching residue on the sacrificial pattern 6a in the TEG region TA1, it
can be estimated that no etching residue is on the sacrificial pattern 6 in the sensor region SA.
Further, in the case where an etching residue is generated in the sacrificial pattern 6a of the TEG
region TA1, it can be estimated that the etching residue of the same degree is generated in the
sacrificial pattern 6 in the sensor region SA. Since the sacrificial pattern 6a in the TEG region TA1
is formed to have substantially the same shape and the same dimensions as the sacrificial pattern
6 in the sensor region SA, in the manufactured semiconductor chip 1 of the present embodiment,
TEG The dummy cavity VR2 of the area TA1 has substantially the same shape and dimensions as
the cavity VR1 of the sensor area SA. The position of the hole 10a in the dummy cavity VR2 of
04-05-2019
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the TEG area TA1 is substantially the same as the position of the hole 10 in the cavity VR1 of the
sensor area SA.
[0109]
FIG. 22 is a plan view showing the etched state of the sacrificial pattern 6a in the TEG region
TA1. A state before starting wet etching of the sacrificial patterns 6, 6a in step S2a is shown in
(a) of FIG. 22, and in (b), (c) and (d), the sacrificial pattern 6 in step S2a. , 6a after the start of the
wet etching, among which (b) is the state where the etching time t of the sacrificial patterns 6, 6a
is t1 (where t1> 0), (c) is the sacrificial pattern 6, The etching time t of 6a corresponds to the
state of t2 (where t2> t1), and (d) corresponds to the state of the etching time t of the sacrificial
patterns 6, 6a t3 (where t3> t2). That is, before and after wet etching of the sacrificial patterns 6,
6a in step S2a, the state of (a) of FIG. 22 (etching time t = 0) → the state of (b) of FIG. 22 (etching
time t = t1> State of 0) → state of (c) in FIG. 22 (state of etching time t = t2> t1) → state of (d) of
FIG. 22 (state of etching time t = t2> t1) Go.
[0110]
Before wet etching of the sacrificial patterns 6, 6a is started in step S2a, as shown in FIG. 22A, all
the sacrificial patterns 6, 6a remain, and the cavity VR1 and the dummy cavity VR2 are dummy It
has not been formed yet. Then, after wet etching of the sacrificial patterns 6, 6a is started in step
S2a, as shown in (b) and (c) of FIG. Is removed by etching, whereby the cavity VR1 and the
dummy cavity VR2 gradually expand from the region near the holes 10 and 10a. Finally, as
shown in (d) of FIG. 22, all of the sacrificial patterns 6, 6a are wet etched and completely
removed, whereby a cavity is formed between the insulating film 5 and the insulating film 7. The
portion VR1 and the dummy cavity VR2 are completely formed. Accordingly, FIG. 20 corresponds
to the state shown in FIG. 22 (a), and FIG. 21 corresponds to the state shown in FIG. 22 (d).
[0111]
If all of the sacrificial pattern 6a is removed by wet etching as in the state of FIG. 22D in step S2a
and there is no etching residue of the sacrificial pattern 6a, then in step S2c, the etching residue
of the sacrificial pattern 6a is It is not observed, and in step S2d, it is determined that the etching
amount of the sacrificial pattern 6a is sufficient. In this case, although the presence or absence of
the etching residue of the sacrificial pattern 6 in the sensor area SA can not be observed, since
04-05-2019
31
the sacrificial pattern 6a and the sacrificial pattern 6 are etched in the same manner, there is no
etching residue of the sacrificial pattern 6a in the TEG region TA1. From this, it is estimated that
there is no etching residue of the sacrificial pattern 6 in the sensor area SA. Therefore, the
semiconductor substrate (semiconductor wafer) 1S is sent to the next step (step of forming the
insulating film 11).
[0112]
On the other hand, in the step S2a, when the wet etching is finished at the stage shown in FIG. 22
(b) or (c), a part of the sacrificial pattern 6a in the TEG region remains to etch the sacrificial
pattern 6a. The rest occurs. In this case, the etching residue of the sacrificial pattern 6a is
observed in step S2c, and it is determined that the etching amount of the sacrificial pattern 6a is
insufficient in step S2d. In this case, although the presence or absence of the etching residue of
the sacrificial pattern 6 in the sensor area SA can not be observed, the etching of the sacrificial
pattern 6a of the TEG region TA1 occurs because the sacrificial pattern 6a and the sacrificial
pattern 6 are etched in the same manner. Therefore, it is estimated that etching residue of the
sacrificial pattern 6 in the sensor area SA is also generated. Therefore, the semiconductor
substrate (semiconductor wafer) 1S is returned to the wet etching apparatus again, and the steps
S2a to S2d are repeated.
[0113]
By doing this, the semiconductor substrate (semiconductor wafer) 1S in a state where there is no
etching residue of the sacrificial pattern 6a in the TEG region TA1, that is, it is estimated that
there is no etching residue of the sacrificial pattern 6 in the sensor region SA. Can be sent to the
next step (the step of forming the insulating film 11). Thereby, the etching residue of the
sacrificial pattern 6 in the sensor area SA can be prevented, and the cavity VR1 can be properly
formed in the sensor area SA. Therefore, the manufacturing yield of the semiconductor device
can be improved. In addition, the performance and reliability of the semiconductor device can be
improved.
[0114]
Therefore, in the manufactured semiconductor chip 1 of the present embodiment, the dummy
cavity VR2 similar to the cavity VR1 formed in the sensor area SA is between the insulating film
04-05-2019
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5 and the insulating film 7 in the TEG region TA1. It is formed. Unlike the cavity VR1 of the
sensor area SA, the dummy cavity VR2 is a cavity that does not function as a sensor, but as
described above, the etching state of the sacrificial pattern 6a can be observed to enable sacrifice
in the sensor area SA. It is formed to prevent the etching residue of the pattern 6.
[0115]
The semiconductor chip (semiconductor device) 1 according to the present embodiment is a
semiconductor device having a sensor area SA in which a plurality of sensor cells (vibrator 20)
are formed on the main surface, but of the main surfaces having the sensor area SA. A dummy
cavity VR2 is provided in the first region (here, TEG region TA1) other than the sensor region SA,
and the upper electrode wiring M1 is provided on the top of the dummy cavity VR2 farthest from
the hole 10a. The conductor layer of the same layer (here, the laminated film 8) is not formed. In
particular, in the present embodiment, the conductor layer (the laminated film 8 here) in the
same layer as the upper electrode wiring M1 is not formed above the dummy cavity VR2. As a
result, when etching the sacrificial patterns 6, 6a for forming the cavity VR1 and the dummy
cavity VR2, it becomes possible to observe the etching state of the sacrificial pattern 6a for
forming the dummy cavity VR2; Since the etching state of the sacrificial pattern 6 for forming the
cavity VR2 can be estimated from the etching state of the sacrificial pattern 6a for forming the
cavity VR2 of the second embodiment, the etching residue of the sacrificial pattern 6 in the
sensor area SA can be prevented. The part VR1 can be formed properly. Therefore, the
manufacturing yield of the semiconductor device can be improved. In addition, the performance
and reliability of the semiconductor device can be improved.
[0116]
Further, in the present embodiment, the metal film (upper electrode wiring M1) is not formed at
all on the upper portion (upper side) of the sacrificial pattern 6a (dummy cavity VR1) in the TEG
region TA1, so etching of the sacrificial pattern 6a The state can be observed in detail, and the
state in the middle of the etching of the sacrificial pattern 6a can be finely identified. For
example, the state of FIG. 22 (b) and the state of FIG. 22 (c) can be determined. Therefore, it
becomes easy to accurately set the minimum etching amount necessary to etch the sacrificial
patterns 6, 6a, and to suppress over-etching when etching the sacrificial patterns 6, 6a. it can.
[0117]
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Further, in the present embodiment, by forming the sacrificial pattern 6 and the sacrificial
pattern 6a by patterning the same sacrificial film 6b, the sacrificial pattern 6 and the sacrificial
pattern 6a are formed of a film of the same material and the same thickness. There is. By forming
the sacrificial pattern 6 and the sacrificial pattern 6a by the film of the same material and the
same thickness, the etching of the sacrificial pattern 6 and the sacrificial pattern 6a in the wet
etching process of the sacrificial patterns 6, 6a through the holes 10, 10a Can be made the same,
and the reliability of estimating the etching state of the sacrificial pattern 6 from the etching
state of the sacrificial pattern 6a can be increased. As described above, since the sacrificial
pattern 6 and the sacrificial pattern 6a are formed of films of substantially the same material and
the same thickness, there is no warpage (relief deformation) of the membrane (film on the hollow
portions VR1 and VR2). When it is regarded as one, the formed cavity portion VR1 and the
dummy cavity portion VR2 have substantially the same thickness (dimension in the direction
perpendicular to the first main surface 1Sa of the semiconductor substrate 1S).
[0118]
In addition, in TEG area TA1, a dummy similar to lower electrode M0E is formed in accordance
with the formation of sacrificial pattern 6 (cavity VR1) above insulating film 5 in upper part of
lower electrode M0E in sensor area SA. The lower electrode M0E2 is provided, and a sacrificial
pattern 6a (dummy cavity VR2) is formed above the dummy lower electrode M0E2 via the
insulating film 5. Thus, the stacked structure of lower electrode M0E, insulating film 5, sacrificial
pattern 6 and insulating film 7 in sensor area SA, and the stacked lower electrode M0E2 of
dummy in insulating layer 5 of TEG area TA1, insulating film 5, sacrificial pattern 6a and
insulating film 7 The structure can be made the same (the same layer structure), and the etching
conditions for etching the sacrificial patterns 6, 6a in step S2a are the same as those of the
sacrificial pattern 6 in the sensor area SA and the sacrificial pattern 6a in the TEG area TA1. It
can be the same. Thereby, when the sacrificial patterns 6 and 6a are etched in step S2a, the
etching state of the sacrificial pattern 6a in the TEG area TA1 and the etching state of the
sacrificial pattern 6 in the sensor area SA may be closer to the same state. Thus, the etching state
of the sacrificial pattern 6 in the sensor area SA can be more accurately estimated from the
etching state of the sacrificial pattern 6a in the TEG area TA1 observed in step S2c. Also, in the
case where the insulating film 5 is removed by over-etching when the sacrificial pattern 6a is
etched in step S2a and the dummy lower electrode M0E2 is exposed, it can be observed in step
S2c. It becomes possible to determine whether the lower electrode M0E is exposed by the
etching.
[0119]
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Insulating films 7 and 9 are formed on the upper part of sacrificial pattern 6a, and in step S2c,
the etching state of sacrificial pattern 6a under insulating films 7 and 9 is observed through
insulating films 7 and 9. There is a need. Therefore, it is preferable that the insulating films 7 and
9 be formed of an insulating film which easily transmits visible light (having a light transmitting
property). Since the silicon oxide film and the silicon nitride film substantially transmit visible
light, it is more preferable if the insulating films 7 and 9 are formed of a silicon oxide film or a
silicon nitride film.
[0120]
If the sacrificial pattern 6a transmits too much visible light, the etched state of the sacrificial
pattern 6a can not be observed in step S2c, so that the sacrificial pattern 6a has a lower visible
light transmittance than the insulating films 7 and 9. Is preferred.
[0121]
Therefore, the insulating films 7 and 9 are formed of a material (eg, silicon oxide or silicon
nitride) that readily transmits visible light, and the visible light transmittance of the sacrificial
pattern 6 a is higher than the visible light transmittance of the insulating films 7 and 9. By
forming the sacrificial patterns 6 and 6a using a material (for example, a silicon film) that
reduces the size, it becomes possible to accurately observe the etching state of the sacrificial
pattern 6a in step S2c.
In addition to the silicon film (polycrystalline silicon film), the sacrificial patterns 6, 6a can also
be formed of a metal film, and when the sacrificial patterns 6, 6a are formed of a metal film, the
sacrificial pattern 6 formed of a metal film , 6a reflect almost 100% of visible light, which
facilitates observation of the etching state of the sacrificial patterns 6, 6a by an optical
microscope.
[0122]
In step S2a, it is necessary to selectively etch the sacrificial patterns 6, 6a while suppressing
(preventing) the etching of the insulating films 5, 7, 9. Therefore, the wet etching of the sacrificial
patterns 6, 6a in step S2a is performed under the condition that the etching rate of the sacrificial
04-05-2019
35
patterns 6, 6a is higher than the etching rate of the insulating films 5, 7, 9. By forming the
sacrificial patterns 6, 6a by silicon films (polycrystalline silicon films), in step S2a, while
suppressing (preventing) etching of the insulating films 5, 7, 9, the sacrificial patterns 6, 6a are
selectively selected. It can be etched. Alternatively, the sacrificial patterns 6, 6a can be formed of
a metal material or the like. In this case, the etchant used for the wet etching of the sacrificial
patterns 6, 6a in step S2a is selected according to the type of metal material, The sacrificial
patterns 6, 6a may be selectively etched while suppressing (preventing) the etching of the
insulating films 5, 7, 9.
[0123]
Next, a case where the semiconductor device (semiconductor chip 1) of the present embodiment
is applied to, for example, an ultrasonic echo diagnostic apparatus will be described.
[0124]
An ultrasonic echo diagnostic apparatus is a medical diagnostic apparatus that uses ultrasound
transmission and makes it possible to visualize the inside of a living body, which can not be seen
from the outside, in real time using ultrasound that exceeds the audible sound area. is there.
The probe (probe) of this ultrasonic echo diagnostic apparatus is shown in FIG.
[0125]
The probe 30 is a transmission / reception unit of ultrasonic waves. As shown in FIG. 23, the
semiconductor chip 1 is attached to the tip end surface of a probe case 30a forming the probe 30
with its first main surface (the surface on which a plurality of transducers 20 are formed)
directed to the outside. ing. Further, an acoustic lens 30 b is attached to the first main surface
side of the semiconductor chip 1.
[0126]
In ultrasonic diagnosis, after the tip of the probe 30 (on the side of the acoustic lens 30b) is
applied to the body surface (body surface), the probe is scanned while being gradually shifted by
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36
a minute position. At this time, an ultrasonic pulse of several MHz is transmitted from the probe
30 applied to the body surface into the living body, and a reflected wave (echo or echo) from a
tissue boundary different in acoustic impedance is received. By this, it is possible to obtain a
tomogram of a living tissue and obtain information on an object. The distance information of the
reflector can be obtained by the time interval from the transmission of ultrasonic waves to the
reception of ultrasonic waves. Also, the level or contour of the reflected wave provides
information about the presence or quality of the reflector.
[0127]
The performance and reliability of the probe 30 can be improved by using the semiconductor
chip 1 of the present embodiment for the probe 30 of such an ultrasonic echo diagnostic
apparatus.
[0128]
Second Embodiment FIG. 24 is a cross-sectional view of main parts of the semiconductor device
of the present embodiment (a cross-sectional view of main parts of TRG region TA1), and FIGS.
25 and 26 are semiconductor devices of the present embodiment. It is a principal part top view
in a manufacturing process.
24 corresponds to FIG. 5 of the first embodiment, and FIGS. 25 and 26 correspond to FIG. 20 and
FIG. 21 of the first embodiment, respectively.
[0129]
The structure of the semiconductor device according to the present embodiment is such that the
metal layer (here, the laminated film 8) in the same layer as the upper electrode wiring M1 is
formed on the upper portion (upper side) of the dummy cavity VR2 (sacrificial pattern 6a) in the
TEG region TA1. The second embodiment is the same as the first embodiment except that the
dummy upper electrode M1E2 is formed, and thus the description thereof is omitted here.
Therefore, the structure of the sensor area SA of the semiconductor device of the present
embodiment is the same as that of the first embodiment. Further, in the manufacturing process of
the semiconductor device of the present embodiment, the upper portion of the dummy formed of
the metal layer (here, the laminated film 8) in the same layer as the upper electrode wiring M1
on the upper portion (upper side) of the sacrificial pattern 6a in the TEG region TA1. Except for
04-05-2019
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forming the electrode M1E2, it is the same as that of the first embodiment.
[0130]
In the first embodiment, the metal film of the same layer as the upper electrode wiring M1 is not
formed on the upper portion (upper side) of the entire dummy cavity VR2 (sacrifice pattern 6a)
of the TEG region TA1 as shown in FIG. The On the other hand, in the present embodiment, as
shown in FIG. 24, the upper electrode wiring M1 is formed in the same layer as the upper portion
(upper side) of a part of the dummy cavity VR2 (sacrifice pattern 6a) in the TEG region TA1. A
dummy upper electrode M1E2 formed of a metal layer (here, the laminated film 8) is formed. The
upper electrode wiring M1 and the dummy upper electrode M1E2 are formed on (the insulating
film 2 on) the semiconductor substrate 1S, and are formed of the conductor layer (the laminated
film 8 here) of the same layer patterned (patterned).
[0131]
In the present embodiment, in the patterning process of the laminated film 8 for forming the
upper electrode wiring M1 (the process from FIG. 11 to FIG. 12 above), the laminated film 8 is
also dummy above the sacrificial pattern 6a of the TEG region TA1. The laminated film 8 is
patterned so as to remain as the upper electrode M1E2. Therefore, as shown in FIG. 25, the
upper electrode wiring M1 is formed above the sacrificial pattern 6 in the sensor area SA, and
the dummy upper electrode M1E2 is formed above the sacrificial pattern 6a in the TEG area TA1.
Ru. However, if the entire sacrificial pattern 6a is covered with the dummy upper electrode
M1E2, the dummy upper electrode M1E2 interferes, and the etching state of the sacrificial
pattern 6a in the TEG region TA1 can not be observed in the step S2c. Therefore, in the present
embodiment, the sacrificial pattern 6a is partially covered with the dummy upper electrode
M1E2, and in particular, the upper portion 42a of the sacrificial pattern 6a which is most distant
from the hole 10a reaching the sacrificial pattern 6a. In this case, the dummy upper electrode
M1E2 is not formed. Therefore, in the semiconductor device of the present embodiment, the
dummy cavity VR2 is partially covered with the dummy upper electrode M1E2, and in particular,
a hole reaching the dummy cavity VR2 of the dummy cavity VR2 The dummy upper electrode
M1E2 is not formed on the top of the position 42a farthest from 10a.
[0132]
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38
In FIGS. 25 and 26, although the dummy upper electrode M1E2 is formed on the sacrificial
pattern 6a (dummy cavity VR2), it is most distant from the hole 10a of the sacrificial pattern 6a
(dummy cavity VR2) A window (opening) 41 is provided in the dummy upper electrode M1E2 at
a position above the central portion of the sacrificial pattern 6a (dummy cavity VR2)
corresponding to the position 42a, and the dummy upper electrode M1E2 (laminate) is formed
there. There is no membrane 8) present. Thus, the window 41 is provided above the position 42a
farthest from the hole 10a reaching the sacrificial pattern 6a (dummy cavity VR2) among the
sacrificial pattern 6a (dummy cavity VR2), and the dummy upper portion is formed. It is possible
not to form the electrode M1E2.
[0133]
For example, in FIG. 25 and FIG. 26, the circumscribed circle diameter of the sacrificial pattern
6a (dummy cavity VR2) is about 50 .mu.m, the distance between the holes 10a is about 46
.mu.m, and the center of the sacrificial pattern 6a (dummy cavity VR2) The diameter of the
circumscribed circle of the dummy upper electrode M1E2 in the upper part of the portion can be
about 35 μm, and the diameter of the window 41 in the dummy upper electrode M1E2 can be
about 5 μm.
[0134]
By selectively removing the sacrificial patterns 6, 6a by wet etching in the step S2 from the state
of FIG. 25, the cavity VR1 and the cavity VR1 are formed in the region where the sacrificial
patterns 6, 6a were present as shown in FIG. A dummy cavity VR2 is formed.
[0135]
When etching residue remains on the sacrificial patterns 6, 6a selectively wet etching the
sacrificial patterns 6, 6a through the holes 10, 10a in the step S2a, the etching state of the
sacrificial pattern 6a in the TEG region TA1 in the step S2c. Of the sacrificial pattern 6a is
observed from the window 41 of the dummy upper electrode M1E2.
For this reason, it can be determined that the etching amount of the sacrificial pattern 6a is
insufficient in step S2d.
In this case, since it is estimated that there is an etching residue of the sacrificial pattern 6 in the
sensor area SA, the steps of the steps S2a to S2d can be repeated to eliminate the etching residue
04-05-2019
39
of the sacrificial pattern 6 in the sensor area SA.
[0136]
On the other hand, when the sacrificial patterns 6, 6a are selectively wet etched through the
holes 10, 10a in the step S2a and no etching residue is generated in the sacrificial patterns 6, 6, a
sacrificial pattern 6a in the TEG region TA1 in the step S2c. The sacrificial pattern 6a is not
observed from the window portion 41 of the dummy upper electrode M1E2 when observing the
etching state of the above. Therefore, it can be determined that the etching amount of the
sacrificial pattern 6a is sufficient in step S2d. In this case, since it is estimated that there is no
etching residue of the sacrificial pattern 6 in the sensor area SA, the semiconductor substrate
(semiconductor wafer) 1S can be sent to the process of step S3.
[0137]
In step S2a, since the sacrificial patterns 6, 6a are wet-etched through the holes 10, 10a, the
sacrificial patterns 6, 6a are etched from the region near the holes 10, 10a. For this reason, the
sacrificial pattern 6a is finally etched at the position 42a farthest from the hole 10a formed to
reach the sacrificial pattern 6a. Therefore, it is possible to observe whether or not the etching
residue of the sacrificial pattern 6a is generated at the position 42a farthest from the hole 10a
formed to reach the sacrificial pattern 6a (dummy cavity VR2), It is necessary to determine
whether or not etching residue of the sacrificial pattern 6a is generated. That is, of the sacrificial
pattern 6a, the central portion of the position 42a (the sacrificial pattern 6a (dummy cavity VR2
in the case of FIGS. 25 and 26) farthest from the hole 10a formed to reach the sacrificial pattern
6a. Of the sacrificial pattern 6a, the sacrificial pattern 6a is completely removed, and it can be
confirmed that there is no etching residue.
[0138]
Therefore, in the present embodiment, the dummy upper electrode M1E2 formed of the metal
layer in the same layer as the upper electrode wiring M1 is formed above the sacrificial pattern
6a in the TEG region TA1, but the sacrificial pattern of the sacrificial pattern 6a A window 41 is
provided on the top of the position 42a farthest from the hole 10a reaching 6a so that the
dummy upper electrode M1E2 is not formed. Therefore, in the manufactured semiconductor chip
(semiconductor device) of the present embodiment, the metal layer (laminated film 8 in the same
04-05-2019
40
layer as the upper electrode wiring M1) is formed on the dummy hollow portion VR2 of the TEG
region TA1. The dummy upper electrode M1E2 is formed, but the dummy hollow portion VR2 is
formed by providing the window portion 41 above the position 42a farthest from the hole 10a
reaching the dummy hollow portion VR2. The upper electrode M1E2 is not formed. As a result, it
can be confirmed in the step S2c that the sacrificial pattern 6a is completely removed in the step
S2a and there is no etching residue. Since it can be estimated that there is no etching residue of
the sacrificial pattern 6 in the sensor area SA by confirming that there is no etching residue in
the sacrificial pattern 6a in the TEG region TA1, there should be no etching residue of the
sacrificial pattern 6 in the sensor region SA. In the estimated state, the semiconductor substrate
(semiconductor wafer) 1S can be sent to the next step (step of forming the insulating film 11).
Thereby, the etching residue of the sacrificial pattern 6 in the sensor area SA can be prevented,
and the cavity VR1 can be properly formed in the sensor area SA. Therefore, the manufacturing
yield of the semiconductor device can be improved. In addition, the performance and reliability of
the semiconductor device can be improved.
[0139]
In the case of the first embodiment, since the metal layer of the same layer as the upper
electrode wiring M1 is not formed at all above the sacrificial pattern 6a (dummy cavity VR2) in
the TEG region TA1, the sacrificial pattern 6a The etching state of the sacrificial pattern 6a can
be observed in more detail, and the state during the etching of the sacrificial pattern 6a can be
more finely identified.
[0140]
Therefore, even if the dummy upper electrode M1E2 is formed on the sacrificial pattern 6a
(dummy cavity VR2) in the TEG region TA1 as in the present embodiment, at least the sacrificial
pattern 6a (dummy cavity VR2) Among them, it is necessary not to form the metal layer (dummy
upper electrode M1E2) in the same layer as the upper electrode wiring M1 above the position
42a most distant from the hole 10a.
Then, in order to be able to distinguish the etching state of the sacrificial pattern 6a in more
detail, as in the first embodiment, the upper electrode wiring M1 on the upper portion of the
sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1. It is preferable that the same
metal layer (conductor layer) is not formed. In the first embodiment described above, the
sacrificial pattern 6a (dummy cavity VR2) of the TEG region TA1 as well as the upper part of the
sacrificial pattern 6a (dummy cavity VR2) of the TEG region TA1 is farthest from the hole 10a
The metal layer (dummy upper electrode M1E2) of the same layer as the upper electrode wiring
04-05-2019
41
M1 is not formed on the whole.
[0141]
Third Embodiment FIGS. 27 and 28 are plan views of relevant parts in the process of
manufacturing a semiconductor device of the present embodiment, and correspond to FIGS. 20
and 21 of the first embodiment, respectively. .
[0142]
In the first embodiment, the planar shape and size of the sacrificial pattern 6a in the TEG area
TA1 are formed to be substantially the same as the planar shape and size of the sacrificial
pattern 6 in the sensor area SA, whereby the dummy of the TEG area TA1 is formed. The planar
shape and size of the hollow portion VR2 of the second embodiment are formed substantially the
same as the planar shape and size of the hollow portion VR1 of the sensor area SA.
On the other hand, in the present embodiment, as shown in FIG. 27, the planar shape of the
sacrificial pattern 6a in the TEG region TA1 is similar to the planar shape of the sacrificial pattern
6 in the sensor region SA. The sacrificial pattern 6 a has a planar dimension larger than that of
the sacrificial pattern 6 in the sensor area SA. For this reason, as shown in FIG. 28, the planar
shape of the dummy cavity VR2 of the TEG area TA1 is similar to the planar shape of the cavity
VR1 of the sensor area SA, and the dummy cavity VR2 of the TEG area TA1. Has a larger planar
dimension than the cavity VR1 of the sensor area SA. That is, in the first embodiment, the hollow
portion VR1 and the dummy hollow portion VR2 have the same planar shape (the same in plan
shape and size), but in the present embodiment, the hollow portion VR1 And the dummy cavity
VR2 have similar planar shapes, and the dummy cavity VR2 is larger than the cavity VR1.
[0143]
As shown in FIGS. 27 and 28, the relative formation position of hole 10 to sacrificial pattern 6
(cavity VR1) and the relative formation position of hole 10a to sacrificial pattern 6a (dummy
cavity VR2) Are substantially the same. That is, the sacrificial pattern 6 (cavity VR1) and the
sacrificial pattern 6a (dummy cavity VR2) can be regarded as planarly similar, including the
positions where the holes 10 and 10a are formed.
04-05-2019
42
[0144]
In the case of FIGS. 27 and 28, the circumscribed circle diameter of the sacrificial pattern 6a
(dummy cavity VR2) in the TEG area TA1 is made larger than the circumscribed circle diameter
of the sacrificial pattern 6 (cavity VR1) in the sensor area SA. There is. Then, the distance
between the holes 10a formed to reach the sacrificial pattern 6a (dummy cavity VR2) in the TEG
region TA1 is a hole formed to reach the sacrificial pattern 6 (cavity VR1) in the sensor region
SA. It is longer than the distance between ten. For example, the diameter of the circumscribed
circle of the sacrificial pattern 6 (cavity VR1) in the sensor area SA is about 50 μm, and the
distance D1 between the holes 10 formed to reach the sacrificial pattern 6 (cavity VR1) in the
sensor area SA is 46 μm Between the holes 10a formed to reach the sacrificial pattern 6a
(dummy cavity VR2) in the TEG region TA1 with the circumscribed circle diameter of the
sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1 being approximately 60 μm
The distance D2 can be set to about 56 .mu.m.
[0145]
The structure of the semiconductor device of this embodiment is the same as that of the
semiconductor device of this embodiment except that the sacrificial pattern 6a (dummy cavity
VR2) of the TEG region TA1 is formed in a planar shape larger than the sacrificial pattern 6
(cavity VR1) of the sensor region SA. The second embodiment is the same as the first
embodiment, and thus the description thereof is omitted here. Therefore, the structure of the
sensor area SA of the semiconductor device of the present embodiment is the same as that of the
first embodiment. Moreover, since the manufacturing process of the semiconductor device of the
present embodiment is substantially the same as that of the above-described first embodiment,
the description thereof is omitted here.
[0146]
In the present embodiment, the sacrificial pattern 6 in the sensor area SA and the sacrificial
pattern 6a in the TEG area TA1 have similar planar shapes, and the sacrificial pattern 6a in the
TEG area TA1 is smaller than the sacrificial pattern 6 in the sensor area SA. , To make the planar
shape larger. Thereby, the distance D3 (first distance) from the position 42 (first position) most
distant from the hole 10 in the sacrificial pattern 6 of the sensor area SA to the hole 10 closest to
the position 42 (first position) ), The distance D4 (second position) from the position 42b (second
position) farthest from the hole 10a in the sacrificial pattern 6a of the TEG region TA1 to the
04-05-2019
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hole 10a closest to the position 42b (second position) Distance) is larger (ie, D4> D3).
[0147]
Therefore, in the manufactured semiconductor device of the present embodiment, the hollow
portion VR1 of the sensor area SA and the dummy hollow portion VR2 of the TEG area TA1 have
similar planar shapes, and the hollow portion VR1 of the sensor area SA is similar. Also in the
case of the dummy cavity VR2 of the TEG area TA1, the planar shape is larger. Then, a distance
D3 (first distance) from the position 42 (first position) most distant from the hole 10 in the
hollow portion VR1 of the sensor area SA to the hole 10 closest to the position 42 (first position)
Second distance D4 from the position 42b (second position) farthest from the hole 10a in the
dummy cavity VR2 of the TEG region TA1 to the hole 10a closest to the position 42b (second
position) Distance is larger (ie, D4> D3).
[0148]
In the case of the patterns of FIGS. 27 and 28, the distance D3 corresponds to D1 / 2, and the
distance D4 corresponds to D2 / 2.
[0149]
In the step S2a, since the sacrificial patterns 6, 6a are wet-etched through the holes 10, 10a, the
sacrificial patterns 6, 6a are etched from the region near the holes 10, 10a.
Therefore, the sacrificial pattern 6 in the sensor area SA is etched last in the position 42 farthest
from the hole 10, and the sacrificial pattern 6a in the TEG area TA1 is etched last in the position
42b farthest from the hole 10a. become. As described above, by setting the distance D4 (second
distance) larger than the distance D3 (first distance) (D4> D3), the sacrificial pattern 6 in the
sensor area SA is completely etched in the step S2a. The time required to completely etch the
sacrificial pattern 6a in the TEG region TA1 can be longer than the time required to Thus, if no
etching residue is generated on the sacrificial pattern 6a in the TEG region TA1 in the above
steps S2c and S2d, the reliability of estimating that the etching residue is not generated on the
sacrificial pattern 6a in the sensor region SA is further enhanced. be able to. In this way, when
sacrificial pattern 6a in TEG region TA1 is completely removed, sacrificial pattern 6 in sensor
region SA is over-etched, and etching residue is left on sacrificial pattern 6 in sensor region SA. It
is possible to confirm that there is no more accurately. Therefore, the etching residue of the
04-05-2019
44
sacrificial pattern 6 in the sensor area SA can be prevented, and the cavity VR1 can be more
accurately formed in the sensor area SA. Therefore, the manufacturing yield of the
semiconductor device can be improved. In addition, the performance and reliability of the
semiconductor device can be improved.
[0150]
The present embodiment can be combined with the above-described second embodiment, and in
this case, the dummy upper electrode M1E2 can be formed on the dummy hollow portion VR2
(sacrifice pattern 6a) of the TEG region TA1. However, in this case, as in the second embodiment,
among the sacrificial pattern 6a (dummy cavity VR2), the position 42b most distant from the
hole 10a reaching the sacrificial pattern 6a (dummy cavity VR2) The dummy upper electrode
M1E2 is not formed on the upper part of the device.
[0151]
Fourth Embodiment FIGS. 29 and 30 are plan views of relevant parts in the process of
manufacturing a semiconductor device of the present embodiment, and correspond to FIGS. 20
and 21 of the first embodiment, respectively. .
[0152]
In the first embodiment, the planar shape and dimensions of the sacrificial pattern 6a (dummy
cavity VR2) in the TEG area TA1 are substantially the same as the planar shape and dimensions
of the sacrificial pattern 6 (cavity VR1) in the sensor area SA. In the second embodiment, the
planar shape of the sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1 is similar to
the planar shape of the sacrificial pattern 6 (cavity VR1) in the sensor region SA.
On the other hand, in the present embodiment, as shown in FIGS. 29 and 30, the planar shape
and dimensions of the sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1 are the
same as those in the sacrificial pattern 6 in the sensor region SA. The planar shape and
dimensions of the cavity VR1) are neither identical nor similar but different. In the present
embodiment, as shown in FIGS. 29 and 30, sacrificial pattern 6a (dummy cavity VR2) in TEG
region TA1 has a planar shape extending in one direction, and the end thereof A hole 10a is
formed in the vicinity.
04-05-2019
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[0153]
In the present embodiment, the graduation pattern 43 is further formed in the vicinity of the
sacrificial pattern 6a in the TEG region TA1. Therefore, in the manufactured semiconductor
device of the present embodiment, the scale pattern 43 is formed (arranged) in the vicinity of the
dummy cavity VR2 of the TEG region TA1. The graduation pattern 43 is formed by the pattern of
the material film (the above-mentioned sacrificial film 6b) in the same layer as the sacrificial
patterns 6, 6a. The calibration pattern 43 is provided to quantify the etching amount of the
sacrificial pattern 6a in step S2, and is a pattern arranged regularly (at equal intervals).
[0154]
In the case of FIGS. 29 and 30, for example, the circumscribed circle diameter of the sacrificial
pattern 6 (cavity VR1) in the sensor area SA is approximately 50 μm, and the sacrificial pattern
6 (cavity VR1) in the sensor area SA is formed. The distance D1 between the holes 10 is about 46
μm, and the maximum length of the sacrificial pattern 6a (dummy cavity VR2) in the TEG region
TA1 (the length L1 along the extending direction of the sacrificial pattern 6a) is about 310 μm.
From the hole 10a formed in the vicinity of the end of the sacrificial pattern 6a (dummy cavity
VR2) in the area TA1 to the position 42c most distant from the hole 10a in the sacrificial pattern
6a (dummy cavity VR2) The distance D5 can be about 300 μm.
[0155]
The structure of the semiconductor device of this embodiment is the same as that of the first
embodiment except that the shape of the sacrificial pattern 6a (dummy cavity VR2) in the TEG
region TA1 is changed and the scale pattern 43 is provided. Therefore, the description is omitted
here.
Therefore, the structure of the sensor area SA of the semiconductor device of the present
embodiment is the same as that of the first embodiment. Further, in the manufacturing process of
the semiconductor device of the present embodiment, when patterning the sacrificial film 6b
using the photolithography method and the dry etching method (that is, in the steps from FIG. 9
to FIG. 10) The second embodiment is substantially the same as the first embodiment except that
the graduation pattern 43 is formed, and the description thereof is omitted here.
04-05-2019
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[0156]
In the present embodiment, the sacrificial pattern 6a in the TEG region TA1 has a planar shape
extending in one direction, and in the vicinity of the end of the sacrificial pattern 6a, the
sacrificial pattern 6a (dummy cavity VR2) is formed. A hole 10a reaching is formed. Then, a
distance D3 (first distance) from the position 42 (first position) most distant from the hole 10 in
the sacrificial pattern 6 of the sensor area SA to the hole 10 closest to the position 42 (first
position) Distance D5 (second distance) from the position 42c (second position) most distant
from the hole 10a in the sacrificial pattern 6a in the TEG region TA1 to the hole 10a closest to
the position 42c (second position) ) Is larger (ie, D5> D3).
[0157]
Therefore, in the manufactured semiconductor device of the present embodiment, the dummy
cavity VR2 of the TEG region TA1 has a planar shape extending in one direction, and in the
vicinity of the end of the dummy cavity VR2 A hole 10a reaching the dummy cavity VR2 is
formed. Then, a distance D3 (first distance) from the position 42 (first position) most distant from
the hole 10 in the hollow portion VR1 of the sensor area SA to the hole 10 closest to the position
42 (first position) Second distance D5 (second position) from the position 42c (second position)
farthest from the hole 10a in the dummy cavity VR2 of the TEG region TA1 to the hole 10a
closest to the position 42c (second position) Distance is larger (ie, D5> D3).
[0158]
In the step S2a, since the sacrificial patterns 6, 6a are wet-etched through the holes 10, 10a, the
sacrificial patterns 6, 6a are etched from the region near the holes 10, 10a. Therefore, the
sacrificial pattern 6 in the sensor area SA is etched last at the position 42 farthest from the hole
10, and the sacrificial pattern 6a in the TEG area TA1 is etched last at the position 42c farthest
from the hole 10a. become. As described above, by setting the distance D5 (second distance)
larger than the distance D3 (first distance) (D5> D3), the sacrificial pattern 6 in the sensor area
SA is completely etched in the step S2a. The time required to completely etch the sacrificial
pattern 6a in the TEG region TA1 can be longer than the time required to Thus, if no etching
residue is generated on the sacrificial pattern 6a in the TEG region TA1 in the above steps S2c
and S2d, the reliability of estimating that the etching residue is not generated on the sacrificial
pattern 6a in the sensor region SA is further enhanced. be able to. Further, as in the present
embodiment, the sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1 has a planar
04-05-2019
47
shape extending in one direction, and the vicinity of the end of the sacrificial pattern 6a (dummy
cavity VR2) By providing the holes 10a in the second embodiment, the etching amount of the
sacrificial pattern 6a in the TEG region TA1 can be monitored, and it is estimated (confirmed)
that there is no etching residue of the sacrificial pattern 6 in the sensor region SA. become able
to.
[0159]
Further, in the present embodiment, since the graduation pattern 43 is formed (arranged) in the
vicinity (adjacent) of the sacrificial pattern 6a (dummy cavity VR2) in the TEG region TA1, when
observed in the step S2c. The amount of etching of the sacrificial pattern 6a can be quantified.
Therefore, since the etching amount of the sacrificial pattern 6a in the etching step of the step
S2a can be quantitatively observed (judged) in the step S2c, whether the etching amount of the
sacrificial pattern 6a is insufficient or sufficient The accuracy (reliability) at the time of
determination in S2d can be further enhanced. Thereby, the etching residue of the sacrificial
pattern 6 in the sensor area SA can be more accurately prevented, and the cavity VR1 can be
more accurately formed in the sensor area SA. Therefore, the manufacturing yield of the
semiconductor device can be further improved. In addition, the performance and reliability of the
semiconductor device can be further improved.
[0160]
The present embodiment can be combined with the above-described second embodiment, and in
this case, the dummy upper electrode M1E2 can be formed on the dummy hollow portion VR2
(sacrifice pattern 6a) of the TEG region TA1. However, in this case, as in the second embodiment,
of the sacrificial pattern 6a (dummy cavity VR2), the distance D3 (first dummy hole) reaching the
sacrificial pattern 6a (dummy cavity VR2) is obtained. The dummy upper electrode M1E2 is not
formed in the upper part of the position away from the distance.
[0161]
However, in the present embodiment, the etching amount of the sacrificial pattern 6a in the TEG
region TA1 can be monitored by forming the sacrificial pattern 6a (dummy cavity VR2) in the
TEG region TA1 into a planar shape extending in one direction. Therefore, it is more preferable
not to form a dummy upper electrode M1E2 above the sacrificial pattern 6a (dummy cavity VR2)
04-05-2019
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in the TEG region TA1. As a result, the etching state of the sacrificial pattern 6a in the TEG region
TA1 can be observed in more detail, and the state in the middle of the etching of the sacrificial
pattern 6a can be identified more finely.
[0162]
Fifth Embodiment FIGS. 31 to 34 are plan views of relevant parts in a process of manufacturing a
semiconductor device of the present embodiment. 31 corresponds to (a) of FIG. 20 of the first
embodiment, FIG. 32 corresponds to (b) of FIG. 20 of the first embodiment, and FIG. 33
corresponds to (a) of the first embodiment. FIG. 34 corresponds to (a) of FIG. 21 and FIG. 34
corresponds to (b) of FIG. 21 of the first embodiment. That is, FIGS. 31 and 33 show a plan view
of the main part of the sensor area SA, and FIGS. 32 and 34 show a plan view of the main part of
the TEG area TA1. 31 and 32 correspond to the same process step as FIG. 14 as in FIG. 20, and
FIGS. 33 and 34 correspond to the same process step as FIG. 15 as in FIG.
[0163]
In the present embodiment, when there are a plurality of types of arrangement patterns (relative
positional relationship) between the holes 10 and the sacrificial patterns 6 in the sensor area SA,
the positions are located at the intersections of the upper electrode wiring M1 and the lower
electrode wiring M0. Forming a group of transducers (a group of a plurality of transducers 20) as
one set, and one set of sacrificial patterns 51a of the same type (the same shape) as the sacrificial
patterns 51 of one set in the sensor area SA in the TEG area TA1. Deploy.
[0164]
That is, in the present embodiment, at the time of patterning of the sacrificial film 6b, a sacrificial
pattern 51 in which a plurality of sacrificial patterns 6 are connected is formed in the sensor area
SA, and a plurality of sacrificial patterns 6a are connected. The sacrificial pattern 51a having the
same shape as the sacrificial pattern 51 is formed in the TEG region TA1, and when the holes 10
and 10a are formed, the position (relative position) of the hole 10 with respect to the sacrificial
pattern 51 and the hole 10a with respect to the sacrificial pattern 51a. Make the same as the
position (relative position) of.
[0165]
Therefore, in the manufactured semiconductor device of the present embodiment, the cavity
04-05-2019
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pattern 52 (first cavity pattern) in which a plurality of cavities VR1 (first cavities) respectively
forming the vibrators 20 (sensor cells) are connected is A dummy cavity pattern 52a (second
cavity pattern) formed in the sensor area SA and in which a plurality of dummy cavities VR2
(second cavities) are connected, the dummy having the same shape as the cavity pattern 52 The
cavity pattern 52a is formed in the TEG area TA1.
The position (relative position) of the hole 10 (first opening) to the cavity pattern 52 and the
position (relative position) of the hole 10a (second rear portion) to the dummy cavity pattern 52a
are the same. .
[0166]
For example, in the case of FIGS. 31 and 33, in the sensor area SA, the arrangement pattern
(relative positional relationship) between the hole 10 and the sacrificial pattern 6 (cavity VR1) is
type A, type B, type C, type D And five types of type E.
These five types (types A to E) of sacrificial patterns 6 (cavity portions VR1) are connected to
form sacrificial patterns 51 (cavity portion patterns 52). The sacrificial pattern 51 (cavity pattern
52) is formed at the intersection of the upper electrode wiring M1 and the lower electrode wiring
M0 in the sensor area SA. Then, as shown in FIGS. 32 and 34, a sacrificial pattern 51a (dummy
cavity pattern 52a) having the same shape as the sacrificial pattern 51 (cavity pattern 52) is
formed in the TEG region TA1. Therefore, in each sacrificial pattern 6a (dummy cavity pattern
VR2) constituting the sacrificial pattern 51a (dummy cavity pattern 52a), the arrangement
pattern (relative positional relationship) between the holes 10a and the sacrificial pattern 6a is
There are five types, type A, type B, type C, type D and type E. Further, the metal film of the same
layer as the upper electrode wiring M1 is not formed on the sacrificial pattern 51a (dummy
cavity portion pattern 52a) in the TEG region TA1.
[0167]
Except for this point, the structure of the semiconductor device of the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here. Moreover,
since the manufacturing process of the semiconductor device of the present embodiment is
substantially the same as that of the above-described first embodiment, the description thereof is
omitted here.
04-05-2019
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[0168]
As shown in FIG. 31, in the sensor area SA, there are a plurality of types (here, five types of types
A to E) of arrangement patterns (relative positional relationships) between the holes 10 and the
sacrificial patterns 6, The patterns 6 are connected to form a sacrificial pattern 51. In the
sacrificial pattern 51, in the step S2a, the sacrificial pattern 51 is etched from a region near the
hole 10. For this reason, the plurality of sacrificial patterns 6 constituting the sacrificial pattern
51 are etched differently in each of the types A to E, and the time required for the etching is also
different.
[0169]
Therefore, in the present embodiment, a sacrificial pattern 51a (dummy cavity pattern 52a)
having the same shape as the sacrificial pattern 51 (cavity pattern 52) of the sensor area SA is
formed in the TEG region TA1, and the sacrificial pattern 51 (cavity) is formed. The position
(relative position) of the hole 10 with respect to the portion pattern 52) and the position (relative
position) of the hole 10a with respect to the sacrificial pattern 51a (dummy cavity portion
pattern 52a) are the same. Thus, the etching state of the sacrificial pattern 51 in the sensor area
SA and the etching state of the sacrificial pattern 51a in the TEG area TA1 in the etching process
of step S2a can be made the same. Therefore, by observing the etching state of the sacrificial
pattern 51a in the TEG region in the step S2c, the etching state of the sacrificial pattern 51 in the
sensor region SA can be accurately estimated, and the etching state of the entire sacrificial
pattern 51, 51a Can be checked at a glance. Therefore, the etching residue can be prevented by
the entire sacrificial pattern 51 in which the plurality of sacrificial patterns 6 are connected, and
the cavity portion pattern 51 in which the plurality of hollow portions VR1 are connected in the
sensor area SA can be formed more accurately. Therefore, the manufacturing yield of the
semiconductor device can be improved. In addition, the performance and reliability of the
semiconductor device can be improved.
[0170]
However, in the present embodiment, it is necessary to secure an area larger than the area
required in the first to fourth embodiments with respect to the TEG region TA1.
[0171]
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51
Sixth Embodiment FIG. 35 is a cross-sectional view of main parts (cross-sectional view of main
parts of TEG region TA1) in the manufacturing process of the semiconductor device according to
the present embodiment, and FIG. FIG. 18 is a cross-sectional view of a main part of the main
part (a main part cross-sectional view of the TEG region TA1).
FIG. 36 corresponds to FIG. 5 of the first embodiment. FIG. 35 shows the same region as FIG. 36,
but is a plan view of relevant parts of process steps corresponding to FIG. 14 of the first
embodiment.
[0172]
In the first embodiment, in step S2c, the sacrificial pattern 6a of the TEG region TA1 is taken
from the surface (that is, the main surface on the side where the vibrator 20 is formed) of the
semiconductor substrate (semiconductor wafer) 1S. Observe the etching state of. On the other
hand, in the present embodiment, in step S2c, from the back surface 1Sb of the semiconductor
substrate (semiconductor wafer) 1S (that is, the main surface on the opposite side to the main
surface on which the vibrator 20 is formed), From the direction 61 indicated by the arrow, the
etching state of the sacrificial pattern 6a in the TEG region TA1 is observed.
[0173]
In the present embodiment, the etching state of the sacrificial pattern 6a in the TEG region TA1 is
observed from the back surface side of the semiconductor substrate (semiconductor wafer) 1S
(that is, from the direction 61 in FIG. 35) in step S2c. It is necessary to transmit and observe the
etching state of the sacrificial pattern 6a in the TEG region TA1. For this reason, in the present
embodiment, the semiconductor substrate (semiconductor wafer) 1S preferably has translucency.
In the present embodiment, for example, the semiconductor substrate (semiconductor wafer) 1S
can be configured of a quartz substrate or the like. Since the semiconductor substrate
(semiconductor wafer) 1S has translucency, etching of the sacrificial pattern 6a in the TEG region
TA1 is performed in step S2c from the back side of the semiconductor substrate (semiconductor
wafer) 1S through the semiconductor substrate 1S. It becomes possible to observe the state
properly.
04-05-2019
52
[0174]
In the first embodiment, the etching state of the sacrificial pattern 6a in the TEG region TA1 is
observed from the surface side of the semiconductor substrate (semiconductor wafer) 1S (that is,
from the direction 21 in FIG. 15) in the step S2c. In the TEG area TA1, a metal layer of the same
layer as the upper electrode wiring M1 was not formed at all on the sacrificial pattern 6a
(dummy cavity VR2) so as not to disturb the observation.
[0175]
On the other hand, in the present embodiment, since the etching state of the sacrificial pattern 6a
in the TEG region TA1 is observed from the back surface side of the semiconductor substrate
(semiconductor wafer) 1S in the step S2c, the figure does not disturb the observation. As shown
in FIG. 35 and FIG. 36, in the TEG region TA1, a metal layer (the dummy lower electrode M0E2 in
the same layer as the lower electrode wiring M0 (lower electrode M0E) is provided under the
sacrificial pattern 6a (dummy cavity VR2). Does not form at all.
As a result, in the step S2c, it becomes possible to observe the etching state of the sacrificial
pattern 6a in the TEG region TA1 from the back surface side of the semiconductor substrate
(semiconductor wafer) 1S.
[0176]
Therefore, by confirming that there is no etching residue in the sacrificial pattern 6a of the TEG
region TA1 in the step S2c, it can be estimated that there is no etching residue of the sacrificial
pattern 6 in the sensor region SA. The semiconductor substrate (semiconductor wafer) 1S can be
sent to the next step (step of forming the insulating film 11) in a state where it is estimated that
there is no etching residue of the pattern 6. Thereby, the etching residue of the sacrificial pattern
6 in the sensor area SA can be prevented, and the cavity VR1 can be properly formed in the
sensor area SA. Therefore, the manufacturing yield of the semiconductor device can be improved.
In addition, the performance and reliability of the semiconductor device can be improved.
[0177]
In FIGS. 35 and 36, the metal layer (dummy upper electrode M1E2) of the same layer as the
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53
upper electrode wiring M1 is formed on the sacrificial pattern 6a (dummy cavity VR2) in the TEG
region TA1. However, its formation can be omitted. Further, in the case where the dummy upper
electrode M1E2 is formed above the sacrificial pattern 6a (dummy cavity VR2) in the TEG region
TA1, the window 41 as formed in the second embodiment is the present embodiment. The
dummy upper electrode M1E2 may or may not be formed. This is because, in the present
embodiment, in order to observe the etching state of the sacrificial pattern 6a not from the front
surface side of the semiconductor substrate (semiconductor wafer) 1S but from the back surface
side, even if the dummy upper electrode M1E2 has the window portion 41. This is because there
is no problem in observation of the etching state of the sacrificial pattern 6a even if it is not.
[0178]
The other structure of the semiconductor device according to the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here. Therefore,
the structure of the sensor area SA of the semiconductor device of the present embodiment is the
same as that of the first embodiment. Further, the manufacturing process of the semiconductor
device of the present embodiment is substantially the same as that of the first embodiment
except that the direction of observing the etching state of the sacrificial pattern 6a in the TEG
region TA1 is different in step S2c. So the explanation is omitted.
[0179]
In the present embodiment, when observing the etching state of sacrificial pattern 6a in TEG
region TA1 from the back surface side of semiconductor substrate (semiconductor wafer) 1S in
step S2c, the front surface side of semiconductor substrate (semiconductor wafer) 1S It is
necessary to prevent the occurrence of defects such as adhesion of foreign matter to the sensor
surface (sensor area SA) to be formed and generation of flaws.
[0180]
Further, the present embodiment can be combined with the third to fifth embodiments.
[0181]
Seventh Embodiment FIG. 37 is a cross-sectional view of main parts (cross-sectional view of main
parts of TEG region TA1) in the manufacturing process of the semiconductor device according to
the present embodiment, and FIG. FIG. 18 is a cross-sectional view of main parts of the main part
04-05-2019
54
(a main part cross-sectional view of the TEG region TA1).
FIG. 37 corresponds to FIG. 35 of the sixth embodiment, and FIG. 38 corresponds to FIG. 36 of
the sixth embodiment.
[0182]
Also in the present embodiment, as in the sixth embodiment, in the step S2c, from the back
surface 1Sb side of the semiconductor substrate (semiconductor wafer) 1S, that is, the direction
61 of FIG. Observe the etching state of 6a.
Therefore, also in the present embodiment, as in the first embodiment, the semiconductor
substrate (semiconductor wafer) 1S preferably has a light transmitting property. For example, the
semiconductor substrate (semiconductor wafer) 1S is made of a quartz substrate or the like. It
can be configured.
[0183]
However, in the sixth embodiment, in TEG region TA1, although the metal layer of the same layer
as lower electrode interconnection M0 (lower electrode M0E) is not formed at all under sacrificial
pattern 6a (dummy cavity VR2). On the other hand, in the present embodiment, as shown in FIGS.
37 and 38, a metal layer (here, the same layer as lower electrode interconnection M0 (lower
electrode M0E) under sacrificial pattern 6a (dummy cavity VR2). Here, the dummy lower
electrode M0E2) is formed.
[0184]
However, when the dummy lower electrode M0E2 is provided below the entire sacrificial pattern
6a (dummy cavity VR2), in step S2c, from the back surface side of the semiconductor substrate
(semiconductor wafer) 1S (ie, from the direction 61 of FIG. When the etching state of the
sacrificial pattern 6a in the TEG region TA1 is observed, the dummy lower electrode M0E2
becomes an obstacle, and the etching state of the sacrificial pattern 6a can not be observed.
[0185]
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55
Therefore, in the present embodiment, a dummy lower electrode M0E2 formed of a metal layer
(laminated film 3 here) in the same layer as lower electrode interconnection M0 under sacrificial
pattern 6a (dummy cavity VR2) in TEG region TA In the sacrificial pattern 6a (dummy cavity
VR2), the dummy lower electrode M0E2 is formed at the top of the position farthest from the
hole 10a reaching the sacrificial pattern 6a (dummy cavity VR2). Do not.
For example, as shown in FIG. 37 and FIG. 38, among sacrificial patterns 6a (dummy cavity VR2),
positions farthest from holes 10a reaching sacrificial pattern 6a (dummy cavity VR2) (the abovementioned FIG. 25). At the lower part of the position 41a of FIG. 26, the dummy lower electrode
M0E2 is provided with a window (opening) 62 or the like so that the dummy lower electrode
M0E2 does not exist there.
[0186]
That is, in the second embodiment, the window portion 41 is provided in the dummy upper
electrode M1E2 so that the etching state of the sacrificial pattern 6a can be observed from the
surface side of the semiconductor substrate 1S in the step S2c. In the embodiment, the window
portion 62 is provided in the dummy lower electrode M0E2 so that the etching state of the
sacrificial pattern 6a can be observed from the back surface side of the semiconductor substrate
1S in the step S2c.
[0187]
As a result, it can be confirmed in the step S2c that the sacrificial pattern 6a is completely
removed in the step S2a and there is no etching residue.
Since it can be estimated that there is no etching residue of the sacrificial pattern 6 in the sensor
area SA by confirming that there is no etching residue in the sacrificial pattern 6a in the TEG
region TA1, there should be no etching residue of the sacrificial pattern 6 in the sensor region
SA. In the estimated state, the semiconductor substrate (semiconductor wafer) 1S can be sent to
the next step (step of forming the insulating film 11).
Thereby, the etching residue of the sacrificial pattern 6 in the sensor area SA can be prevented,
and the cavity VR1 can be properly formed in the sensor area SA. Therefore, the manufacturing
yield of the semiconductor device can be improved. In addition, the performance and reliability of
the semiconductor device can be improved.
04-05-2019
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[0188]
In the case of the above-described sixth embodiment, since the metal layer of the same layer as
lower electrode interconnection M0 is not formed at all under the sacrificial pattern 6a (dummy
cavity VR2) of the TEG region TA1, the sacrificial pattern 6a The etching state of the sacrificial
pattern 6a can be observed in more detail, and the state in the middle of the etching of the
sacrificial pattern 6a can be more finely identified.
[0189]
Further, in the present embodiment, since the window portion 62 is provided in the dummy
lower electrode M0E2, after the dummy lower electrode M0E2 is formed, the window portion 62
is embedded with the insulating film 63 made of a silicon oxide film or the like. After the upper
surface of the lower electrode M0E2 and the upper surface of the insulating film 63 are
planarized, the step of forming the insulating film 5 needs to be performed.
On the other hand, in the sixth embodiment, since the step of burying the insulating film 63 and
the step of planarization are unnecessary, the manufacturing process can be simplified.
[0190]
The other structure of the semiconductor device of the present embodiment is the same as that
of the above-described sixth embodiment, and thus the description thereof is omitted here.
Therefore, the structure of the sensor area SA of the semiconductor device of the present
embodiment is the same as that of the first embodiment. Further, the manufacturing process of
the semiconductor device of the present embodiment is substantially the same as that of the first
embodiment except that the direction of observing the etching state of the sacrificial pattern 6a
in the TEG region TA1 is different in step S2c. So the explanation is omitted.
[0191]
As described above, also in the sixth and seventh embodiments, not only the cavity VR1 (sacrifice
pattern 6) is provided in the sensor area SA, but the dummy cavity VR2 (a TEG area in this case)
04-05-2019
57
other than the sensor area SA A sacrificial pattern 6a) is provided. However, in the first and
second embodiments, the conductor layer of the same layer as the upper electrode M1E (upper
electrode wiring M1) is formed in the upper part of the dummy cavity VR2 farthest from the hole
10a. In the first embodiment, in particular, the conductor layer of the same layer as the upper
electrode M1E (upper electrode wiring M1) is not formed on the upper part of the dummy cavity
VR2. On the other hand, in the sixth and seventh embodiments, the conductor layer of the same
layer as the lower electrode M0E (lower electrode wiring M0) is formed in the lower part of the
dummy cavity VR2 at a position farthest from the hole 10a. In particular, in the seventh
embodiment, the conductor layer of the same layer as the lower electrode M0E (lower electrode
wiring M0) is not formed below the dummy cavity VR2.
[0192]
Also in the seventh embodiment, when observing the etching state of the sacrificial pattern 6a in
the TEG region TA1 from the back surface side of the semiconductor substrate (semiconductor
wafer) 1S in step S2c as in the sixth embodiment. It is necessary to prevent the occurrence of
defects such as the adhesion of foreign matter to the sensor surface (sensor area SA) formed on
the front surface side of the semiconductor substrate (semiconductor wafer) 1S and the
generation of scratches.
[0193]
Further, the present embodiment can be combined with the third to fifth embodiments.
[0194]
As mentioned above, although the invention made by the present inventor was concretely
explained based on the embodiment, the present invention is not limited to the embodiment, and
can be variously changed in the range which does not deviate from the summary. Needless to
say.
[0195]
The above description mainly describes the case where the invention made by the present
inventor is applied to a semiconductor device having an ultrasonic sensor as a background of
application and a method of manufacturing the same, but the present invention is not limited
thereto. The present invention is also applicable to a semiconductor device having another sensor
having a cavity between electrodes, such as a pressure sensor and a microphone, and a method
of manufacturing the same.
04-05-2019
58
[0196]
The present invention is suitable for application to, for example, a semiconductor device having a
sensor using MEMS technology and its manufacturing technology.
[0197]
FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor device
according to an embodiment of the present invention.
It is a principal part enlarged plan view of the semiconductor chip of FIG.
It is a principal part enlarged plan view of the semiconductor chip of FIG.
It is sectional drawing of the X1-X1 line | wire of FIG.
It is sectional drawing of the X1-X1 line | wire of FIG.
FIG. 16 is a cross-sectional view of essential parts in the process of manufacturing a
semiconductor device in an embodiment of the present invention. FIG. 7 is a cross-sectional view
of main parts of the semiconductor device in the manufacturing process continued from FIG. 6;
FIG. 8 is a cross-sectional view of main parts of the semiconductor device in the manufacturing
process continued from FIG. 7; FIG. 9 is a cross-sectional view of main parts of the semiconductor
device in the manufacturing process continued from FIG. 8; FIG. 10 is a cross-sectional view of
main parts of the semiconductor device in the manufacturing process continued from FIG. 9; FIG.
11 is a cross-sectional view of main parts of the semiconductor device in the manufacturing
process continued from FIG. 10; FIG. 12 is a cross-sectional view of the essential part in the
manufacturing process of the semiconductor device subsequent to FIG. 11; FIG. 13 is a crosssectional view of the essential part in the manufacturing process of the semiconductor device
subsequent to FIG. 12; FIG. 14 is a cross-sectional view of main parts of the semiconductor device
in the manufacturing process continued from FIG. 13; FIG. 15 is a cross-sectional view of main
parts of the semiconductor device in the manufacturing process continued from FIG. 14; FIG. 16
is a cross-sectional view of main parts of the semiconductor device in the manufacturing process
continued from FIG. 15; FIG. 17 is a cross-sectional view of main parts of the semiconductor
device in the manufacturing process continued from FIG. 16; FIG. 16 is a flow chart of a
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manufacturing process of a part of the manufacturing process of the semiconductor device of the
embodiment of the present invention. FIG. 16 is a more detailed manufacturing process flow
diagram of a part of the manufacturing process of the semiconductor device according to the
embodiment of the present invention; FIG. 7 is a plan view of the essential part in the
manufacturing process of the semiconductor device of one embodiment of the present invention;
FIG. 7 is a plan view of the essential part in the manufacturing process of the semiconductor
device of one embodiment of the present invention; It is a top view which shows the etching state
of the sacrificial pattern of TEG area | region. It is explanatory drawing of the probe of the
ultrasonic echo diagnostic apparatus to which the semiconductor device which is one
embodiment of this invention is applied. It is principal part sectional drawing of the
semiconductor device of Embodiment 2 of this invention. FIG. 26 is a plan view of the essential
part in the manufacturing process of the semiconductor device in Embodiment 2 of the present
invention; FIG. 26 is a plan view of the essential part in the manufacturing process of the
semiconductor device in Embodiment 2 of the present invention; It is a principal part top view in
the manufacturing process of the semiconductor device of Embodiment 3 of the present
invention. It is a principal part top view in the manufacturing process of the semiconductor
device of Embodiment 3 of the present invention. It is a principal part top view in the
manufacturing process of the semiconductor device of Embodiment 4 of this invention. It is a
principal part top view in the manufacturing process of the semiconductor device of Embodiment
4 of this invention. It is a principal part top view in the manufacturing process of the
semiconductor device of Embodiment 5 of this invention. It is a principal part top view in the
manufacturing process of the semiconductor device of Embodiment 5 of this invention. It is a
principal part top view in the manufacturing process of the semiconductor device of Embodiment
5 of this invention. It is a principal part top view in the manufacturing process of the
semiconductor device of Embodiment 5 of this invention. It is principal part sectional drawing in
the manufacturing process of the semiconductor device of Embodiment 6 of this invention. It is
principal part sectional drawing of the semiconductor device of Embodiment 5 of this invention.
It is principal part sectional drawing in the manufacturing process of the semiconductor device of
Embodiment 6 of this invention. It is principal part sectional drawing of the semiconductor
device of Embodiment 5 of this invention.
Explanation of sign
[0198]
DESCRIPTION OF SYMBOLS 1 semiconductor chip 1S semiconductor substrate 2 insulating film
3 laminated film 3a titanium nitride film 3b aluminum film 3c titanium nitride film 5 insulating
film 6, 6a sacrificial pattern 6b sacrificial film 7 insulating film 8 laminated film 8a titanium
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nitride film 8b aluminum film 8c titanium nitride Film 9 Insulating film 10, 10a hole 11
Insulating film 12a, 12b Opening 13 Insulating film 14a, 14b Opening 20 Vibrator 20a Dummy
vibrator 21 Direction 30 Probe 30a Probe case 30b Acoustic lens 41 Window 42, 42a, 42b , 42c
Position 43 Scale pattern 51, 51a Sacrifice pattern 52 Cavity pattern 52a Dummy cavity pattern
61 Direction BP1, BP2 Bonding pads D1, D2, D3, D4, D5 Distance L1 Length M0 Bottom
electrode wiring M0E Bottom electrode M0E2 Dami Lower electrode M1 upper electrode wiring
M1C connecting portion M1E upper electrode M1E2 dummy upper electrode SA region SW
sidewall TA1 TEG region VR1 cavity VR2 dummy cavity
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