close

Вход

Забыли?

вход по аккаунту

?

JP2008131383

код для вставкиСкачать
Patent Translate
Powered by EPO and Google
Notice
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
DESCRIPTION JP2008131383
In a tone control circuit, the capacitance of a capacitor for setting a frequency band is large, and
it is difficult to incorporate it in an integrated circuit. A low frequency range component S is
extracted from an original audio signal S by an LPF. The bass range adjustment circuit 38
performs gain adjustment on S to generate a bass range adjustment signal S. Further, S is
inverted by the inverting circuit 32 and added to S by the adding circuit 34 to extract the high
range component S. The high range adjustment circuit 36 performs gain adjustment on S to
generate a high range adjustment signal S. The synthesis circuit 24 synthesizes S, S, and S to
generate S in which a boost or cut process is performed on the high range and the low range,
respectively. The LPF 30 is configured of an RC active filter, and the resistor that determines the
cutoff frequency is configured of an equivalent resistor using a switched capacitor circuit.
[Selected figure] Figure 1
Sound quality adjustment circuit and signal characteristic adjustment circuit
[0001]
The present invention relates to a signal characteristic adjustment circuit that adjusts the
strength of an original signal for each of a plurality of set frequency bands, and more particularly
to a tone control circuit such as a tone control circuit or a graphic equalizer.
[0002]
In audio devices, a tone control circuit and a graphic equalizer are employed which perform
boost processing to increase the level of a predetermined frequency band and cut processing to
decrease the level of the predetermined frequency band.
08-05-2019
1
[0003]
FIG. 8 is a circuit diagram showing a basic configuration of a conventional tone control circuit.
In this circuit, the treble band block 2 and the bus band block 4 are connected in series between
the input terminal IN and the output terminal OUT, and the audio signal input to the input
terminal IN is sequentially connected to the treble band block 2 and The signal passes through
the bus band block 4 and is output from the output terminal OUT.
This circuit is composed of a main part integrally formed on a semiconductor substrate as an
integrated circuit, and external parts connected to external terminals 6 to 10 of the integrated
circuit.
[0004]
The treble band block 2 performs boost processing and cut processing on high frequency
components of the audio signal. A capacitor C 1 is connected to the external terminal 6 of the
treble band block 2. When the boost process is performed, the switches SW1 and SW3 are set to
ON. Thus, the treble band block 2 constitutes a non-inverted amplification circuit having a
differential action, and amplifies the high frequency component of the input audio signal. When
the cutting process is performed, the switches SW2 and SW4 are set to on. Thereby, the treble
band block 2 forms a low pass filter (LPF) to attenuate high frequency components of the input
audio signal.
[0005]
On the other hand, the bus band block 4 performs boost processing and cut processing on the
low frequency component of the audio signal. The capacitors C2 and C3 and the resistor R1 are
connected to the external terminals 8 and 10 of the bus band block 4. When the boost process is
performed, the switches SW1 and SW3 are set to ON. Thus, the bus band block 4 constitutes a
non-inverted amplification circuit having an integrating action, and amplifies the low frequency
component of the input audio signal. When the cutting process is performed, the switches SW2
and SW4 are set to on. Thus, the bus band block 4 configures a high pass filter (HPF) to
08-05-2019
2
attenuate the low frequency component of the input audio signal.
[0006]
Each of the treble band block 2 and the bus band block 4 includes resistors connected in series in
multiple stages in the integrated circuit. This series connection of resistors 12 and 14 is divided
into two at various ratios depending on which of the switches provided at the plurality of
locations is turned on, whereby the gains of boost and cut can be adjusted.
[0007]
Also, the frequency band boosted or cut by the treble band block 2 and the bus band block 4 is
the resistance value determined according to the manner of division of the series connection
members 12 and 14 of resistance, and the capacitance and resistance value of external parts. It
becomes settled according to. Here, in order to set the frequency range to be processed by the
treble band block 2 to a high range of the audio signal, for example, a range of about 10 kHz or
more, the resistance value of the series connector 12 and the capacitor C1 are relatively large. It
needs to be a value. Similarly, when the frequency range to be processed by the bus band block 4
is set to a low range of the audio signal, for example, a range of about 100 Hz or less, the
resistance value of the series connector 14 and the capacitors C2 and C3 are relatively set. It
needs to be a large value. JP-A 5-090926
[0008]
In integrated circuits, due to restrictions such as package size, the number of external terminals
such as pins may be limited, and it may be necessary to reduce external parts. In addition, the
reduction of external parts can be expected to reduce the number of assembling steps and the
cost. From such a point of view, it is conceivable to incorporate the capacitors C1 to C3 in the
integrated circuit.
[0009]
However, the capacitors C1 to C3 require relatively large values as described above. Therefore,
08-05-2019
3
when these are to be incorporated in an integrated circuit, there is a problem that a large area is
required on the semiconductor substrate and the chip size becomes large. Here, it is possible to
reduce the capacitance of each of C1 to C3 without changing the frequency characteristics of
boost and cut by increasing the resistance value of series connected members 12 and 14, but
doing so will result in series connected members. There is a problem that the area required for
12, 14 becomes large. Incidentally, the equivalent resistance composed of a switched capacitor
can realize a large resistance value in a relatively small area. However, in the series connection of
resistors 12 and 14 described above, many resistors connected in series have to be individually
configured with switched capacitors, and there is a problem that the circuit becomes complicated
and the scale becomes large. Due to these problems, it is not easy to incorporate C1 to C3 into an
integrated circuit.
[0010]
The present invention has been made to solve the above problems, and in the signal
characteristic adjusting circuit and the sound quality adjusting circuit for adjusting the gain for
each frequency band in the original signal and the audio signal, the capacitor for setting the
frequency band is miniaturized. Accordingly, it is an object of the present invention to
miniaturize a circuit and to reduce the number of external components and pins when
configuring an integrated circuit.
[0011]
The sound quality adjustment circuit according to the present invention adjusts the gain for each
of the first to n-th (n is an integer of 2 or more) frequency bands with respect to the original
audio signal. Corresponding to the first to nth extraction circuits for extracting and outputting
the components of the corresponding frequency band of the original audio signal, and
corresponding to the first to nth extraction circuits, respectively. First to nth gain adjusting
circuits which are provided for adjusting the gain of the output signal of the corresponding
extraction circuit to generate first to nth range adjusting signals, and the first to the original
audio signal. And a synthesis circuit capable of synthesizing the n-th tone range adjustment
signal.
[0012]
Another sound quality adjustment circuit according to the present invention is a first filter which
is a single band pass filter provided with any one of a high pass characteristic and a low pass
characteristic, and the single band pass filter, (K-1) (where k is any integer satisfying 2 ≦ k ≦
n−1), and a k-th filter having a wider pass band than the filter, and the first extraction circuit
The first filter extracts a component of the first frequency band from the original audio signal,
and the kth extraction circuit outputs an output signal of the kth filter to the original audio signal
08-05-2019
4
and the (k-1) th filter. The difference with the output signal of the filter is generated and output
as a component of the kth frequency band in the original audio signal, and the nth extraction
circuit generates the difference between the original audio signal and the (n−1) th filter.
Generate a difference with the output signal of And outputs it as a component of the frequency
band of the n-th in the signal.
[0013]
In another sound quality adjustment circuit according to the present invention, the first to (n-1) th filters are configured using switched capacitor filters.
[0014]
In still another sound quality adjustment circuit according to the present invention, the first to (n1) th filters include a resistor R and a capacitor C for adjusting filter characteristics, and the
resistor R and the capacitor with respect to a cutoff frequency C is a RC active filter which
contributes synergistically, and said resistance R is comprised by the equivalent resistance by a
switched capacitor.
A preferred aspect of the present invention is a sound quality adjustment circuit in which the
first to (n-1) th filters are formed as an integrated circuit on a semiconductor substrate.
[0015]
Further, another preferable aspect of the present invention is a sound quality adjustment circuit
which performs tone control processing for adjusting the strength of the high range and the low
range of the original audio signal when n is 2.
[0016]
The signal characteristic adjustment circuit according to the present invention adjusts the gain
for each of the first to nth (where n is an integer of 2 or more) frequency bands with respect to
the original signal, and the first to nth Corresponding to each of the frequency bands of the first
to nth extracting circuits for extracting and outputting the components of the corresponding
frequency band of the original signal, and the first to nth extracting circuits, respectively. First to
nth gain adjusting circuits which are provided and perform gain adjustment on the output signal
of the corresponding extraction circuit to generate first to nth adjustment signals; and the first to
nth gain signals on the original audio signal and n a combining circuit capable of combining the
08-05-2019
5
adjustment signals.
[0017]
According to the present invention, the extraction circuit can be a conventional external
component by separating the extraction circuit for extracting the component of each frequency
band and the gain adjustment circuit for performing gain adjustment on the extracted
component. While having a capacitor corresponding to that provided, it does not require a series
connection of resistors whose split ratio can be changed by the switch.
As a result, the structure of the resistor used in the extraction circuit is simplified, and
miniaturization and high resistance can be facilitated by using a circuit equivalent to the resistive
element, and accordingly, the capacitance of the capacitor can be reduced and miniaturized. The
circuit can be miniaturized.
Furthermore, as a result, in the sound quality adjustment circuit configured as an integrated
circuit, the capacitor can be incorporated, and the reduction in the number of external
components and pins can be realized.
[0018]
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will
be described based on the drawings.
[0019]
Embodiment 1 FIG. 1 is a schematic block diagram of a tone control circuit according to a first
embodiment of the present invention.
The circuit is basically integrally formed on a semiconductor substrate as an integrated circuit
(IC).
This circuit includes a filter block 20, an adjustment signal generation block 22, and a synthesis
08-05-2019
6
circuit 24. The original voice signal SIN is input to the input terminal IN, and the gains of the
high range and the low range are adjusted to perform boost processing or The output audio
signal SOUT subjected to the cut processing is output from the output terminal OUT.
In this circuit, switching of boost / cut for each of the high range and low range, and gain setting
of boost and cut are performed based on an instruction signal from an external circuit.
[0020]
The filter block 20 includes a treble range extraction circuit that extracts and outputs a treble
range component SHO from SIN and a bass range extraction circuit that extracts and outputs the
bass range component SLO.
Specifically, the filter block 20 includes an LPF 30, which constitutes a bass range extraction
circuit.
[0021]
The filter block 20 further includes an inverting circuit 32 and an adding circuit 34, which
together with the LPF 30 constitute a high range extracting circuit. The SLO extracted by the LPF
30 is input to the inverting circuit 32. The inverting circuit 32 generates a signal SLR in reverse
phase to the input SLO. For example, the inverting circuit 32 is configured using an inverting
amplifier with a gain of 1 ×. The output SLR of the inverting circuit 32 is added to the original
audio signal SIN by the adding circuit 34. Here, since SLR = -SLO, in the adding circuit 34, the
bass range component SLO included in the original audio signal SIN is canceled by the output
SLR of the inverting circuit 32. The addition circuit 34 outputs the remaining component
obtained by removing SLO from SIN as a high range component SHO.
[0022]
The adjustment signal generation block 22 has a high range adjustment circuit 36 and a low
range adjustment circuit 38. The high range adjustment circuit 36 and the low range adjustment
circuit 38 perform gain adjustment on the high range component SHO and the low range
08-05-2019
7
component SLO output from the filter block 20 respectively, and generate the high range
adjustment signal SHT and the low range adjustment signal SLT Do.
[0023]
FIG. 2 is a schematic block diagram of the treble range adjusting circuit 36 and the bass range
adjusting circuit 38. As shown in FIG. The high range adjustment circuit 36 and the low range
adjustment circuit 38 have a configuration common to each other. Here, the high frequency
range adjustment circuit 36 will be described as an example using FIG.
[0024]
The high tone range adjustment circuit 36 comprises an amplitude control block 40 and a phase
control block 42. The amplitude control block 40 controls the amplitude ratio A (≡ | SHT / SHO
|) of the high range adjustment signal SHT with respect to the high range component SHO input
to the high range adjustment circuit 36. The phase control block 42 controls whether the phase
difference of SHT with respect to SHO is 0 ° or 180 °, and determines whether SHT has the
same polarity or reverse with respect to SHO. By the amplitude control block 40 and the phase
control block 42, the high tone range adjustment circuit 36 adjusts the gain that is the
combination of the amplitude ratio and the polarity with respect to SHO to generate the SHT.
[0025]
The amplitude control block 40 comprises an attenuator 50 and an amplifier 52. The amplifier
52 sets the gain GC according to the adjustment width of the gain GOUT of SOUT with respect to
SIN, amplifies the input signal from the attenuator 50 by the gain GC to generate the signal SHB,
and outputs the signal SHB to the phase control block 42 . The gain GC corresponding to the
desired adjustment range of the gain GOUT may have different values between the boost
operation and the cut operation, as described later. Therefore, the amplifier 52 is configured to
receive the mode signal DM for specifying boost / cut from an external circuit, and to switch the
setting value of GC according to the signal DM.
[0026]
08-05-2019
8
The attenuator 50 receives a gain control signal DG instructing a gain adjustment amount from
an external circuit, attenuates SHO according to the signal DG, and outputs the attenuated signal
to the amplifier 52. When the attenuator 50 is configured to be able to attenuate, for example, to
-∞ [dB], the amplitude control block 40 can adjust the amplitude ratio A in the range of GC to -∞
[dB].
[0027]
The phase control block 42 includes an inverting circuit 54 and a switch circuit 56. The inverting
circuit 54 generates a signal SHC in reverse phase to the SHB input from the amplitude control
block 40. For example, the inverting circuit 54 is configured using an inverting amplifier with a
gain of 1 ×. ちなみに、 SHC=−SHB である。
[0028]
The switch circuit 56 receives the SHB from the amplitude control block 40 and the SHC from
the inverting circuit 54, and selectively outputs one of them. The selection is performed based on
the mode signal DM, and at the time of boost, the SHB is output as the SHT, and at the cut time,
the SHC is output as the SHT.
[0029]
The high frequency range adjusting circuit 36 has been described above, but the same process is
performed for the low frequency range adjusting circuit 38, and the low frequency range
adjusting signal SLT is generated from the SLO. That is, at the time of boost, from SLO, the signal
SLB whose amplitude is changed while maintaining the same polarity is generated and output as
SLT, while at cut time, the signal SLC whose polarity is inverted is generated as SLT. Output.
[0030]
As shown in FIG. 1, the high range adjustment signal SHT and the low range adjustment signal
SLT output from the high range adjustment circuit 36 and the low range adjustment circuit 38
08-05-2019
9
are input to the synthesis circuit 24. The synthesis circuit 24 also receives the original speech
signal SIN, adds and synthesizes these SIN, SHT, and SLT, and outputs the result as SOUT.
[0031]
FIG. 3 is a schematic diagram for explaining the principle of tone control in this circuit. FIGS. 3
(a) to 3 (e) show the frequency spectrum, where the horizontal axis is the frequency f and the
vertical axis is the signal gain G based on SIN. In FIG. 3A, spectra 60, 62, and 64 respectively
indicate the original speech signal SIN, the bass component SLO, and the treble component SHO.
[0032]
FIG. 3 (b) shows a spectrum 70 in which the high range is boosted. At the time of high range
boost, as described above, the high range adjustment circuit 36 outputs SHB as SHT. This SHB is
superimposed on SIN in the synthesis circuit 24 to generate SOUT having the spectrum 70.
[0033]
FIG. 3 (c) shows a spectrum 72 in which the high range is cut. At the time of high-pitch range cut,
the high-pitch range adjustment circuit 36 outputs SHC as SHT. This SHC has the opposite
polarity to the treble band component SHO of SIN. Therefore, when SHC and SIN are combined in
the combining circuit 24, the treble band component SHO of SIN is canceled according to the
intensity of SHC, and SOUT having the spectrum 72 is generated.
[0034]
FIG. 3 (d) shows a spectrum 74 with its bass region boosted. At the time of bass region boost, the
bass region adjustment circuit 38 outputs SLB as SLT. This SLB is superimposed on SIN in the
synthesis circuit 24 to generate SOUT having the spectrum 74.
[0035]
08-05-2019
10
FIG. 3 (e) shows a spectrum 76 in which the bass range is cut. When the bass range is cut, the
bass range adjustment circuit 38 outputs SLC as SLT. Since this SLC has a polarity opposite to
that of the low frequency component SLO of SIN, the low frequency component SLO of SIN is
canceled according to the intensity of SLC by the combination of SLC and SIN in the synthesis
circuit 24, and spectrum 76 is obtained. SOUT is generated.
[0036]
Here, for example, the case where the gain GOUT is configured to be adjustable within a range of
± 12 dB will be specifically described. Here, when the upper limit value or the lower limit value
of the adjustment range of GOUT is Gmax [dB], and the amplitude ratio SOUT / SIN between SIN
and SOUT at that time is represented as Am, the following equation holds.
[0037]
Gmax = 20 log 10 Am ... (1)
[0038]
At maximum boost, as can be understood from FIGS. 3B and 3D, the output signal SHB or SLB of
the amplifier 52 is (Am-1) times SIN.
On the other hand, at the maximum cut, as can be understood from FIGS. 3C and 3E, the output
signal SHB or SLB of the amplifier 52 is (1-Am) times SIN. Since the attenuation factor of the
attenuator 50 is set to 0 dB at the maximum boost and the maximum cut, the amplitude ratio |
Am−1 | of SHB and SLB to SIN corresponds to the gain GC of the amplifier 52. That is, GC =
20log10 | Am-1 | ... (2) From (1) and (2), the set value of GC for GOUT = +12 dB corresponding to
the maximum boost is about 9.5 dB, and the set value of GC for GOUT = -12 dB corresponding to
the maximum cut is about -2.5 dB Become. The switching of the GC setting values which differ
between the boost and cut times is performed in conjunction with the mode signal DM as
described above.
[0039]
08-05-2019
11
Next, the LPF 30 will be further described. FIG. 4 is a circuit diagram showing a schematic
configuration of the LPF 30. As shown in FIG. The basic configuration of the LPF 30 used in the
present apparatus is an RC active filter, which includes an operational amplifier 80, resistors 82
and 84, and a capacitor 86, which are integrally formed on a semiconductor substrate. The input
signal SIN to the tone control circuit is input to the input terminal FIN, and the output terminal of
the operational amplifier 80 becomes the output terminal FOUT. A resistor 82 is connected in
series between the input terminal FIN and the inverting input terminal of the operational
amplifier 80. Further, a resistor 84 and a capacitor 86 are connected in parallel between the
output terminal of the operational amplifier 80 and the inverting input terminal. For example,
assuming that the resistances of the resistors 82 and 84 are RC and the capacitance of the
capacitor 86 is CC, the cutoff frequency fC of the LPF 30 is given by the following equation.
[0040]
fC = 1 / (2πRCCC) ..... (3)
[0041]
The resistors 82 and 84 are formed of a resistor circuit capable of realizing high resistance.
For example, as such a resistance circuit, there is one using a MOSFET or the like, and by using
such a circuit, compared to a general resistance element formed using polysilicon or a diffusion
layer on an IC. Therefore, while suppressing the substrate occupied area of the resistors 82 and
84, it is possible to increase their resistance.
[0042]
In this tone control circuit, a switched capacitor circuit is adopted as a resistor circuit which
constitutes the resistors 82 and 84, and the LPF 30 is configured as a switched capacitor filter.
FIG. 5 is a schematic circuit diagram of the LPF 30 in which the resistors 82 and 84 are
configured by a switched capacitor circuit.
[0043]
08-05-2019
12
The switched capacitor circuit is configured to include a capacitor CSC and switch elements SW1
to SW4. A capacitor CSC is inserted in series between the input terminal and the output terminal
of the switched capacitor circuit, and switch elements SW1 and SW2 are provided between the
input terminal and the output terminal and CSC. Both ends of the capacitor CSC can be connected
to the ground serving as a reference voltage source by switch elements SW3 and SW4,
respectively. Each switch element is configured using a transistor on a semiconductor substrate.
The switched capacitor circuit charges and discharges the capacitor CSC by alternately opening
and closing alternately the set of switch elements SW1 and SW2 and the set of switch elements
SW3 and SW4. As a result, charge transfer occurs, and a pulse current flows between both
terminals of the switched capacitor circuit, and if the switching frequency fSC is sufficiently high,
the average current is equivalent to the current passing through the resistor. That is, the
switched capacitor circuit equivalently functions as a resistive element. The resistance value RSC
is expressed by the following equation.
[0044]
RSC=1/(CSCfSC) ………(4)
[0045]
As equation (4) shows, RSC can be increased in inverse proportion to the decrease in fSC.
That is, if a switched capacitor circuit is used, RC can be increased according to fSC, CC can be
reduced, and the capacitor 86 can be made in a size that can be easily formed on the
semiconductor substrate.
[0046]
For example, RSC of the switched capacitor circuit with fSC = 250 kHz and CSC = 1 pF is 4 MΩ.
When the cutoff frequency fC of the LPF 30 is set to 1 kHz, CC is 40 pF if RC is configured using
this switched capacitor circuit. That is, the capacitance required for the LPF 30 is about 40 pF
even if CC and CSC constituting the switched capacitor circuit are combined, and the LPF 30 can
be integrally formed on the IC including these capacitances.
08-05-2019
13
[0047]
As described above, by setting the RC to a high resistance value, the LPF 30 can incorporate the
capacitor 86 in the IC and reduce the number of external pins and parts. The resistors 82 and 84
having the high resistance value RC can be configured, for example, by suppressing the occupied
area on the IC by using a switched capacitor circuit. Here, the resistance circuit is composed of a
plurality of elements and requires a certain size or more. Therefore, as in the circuit shown in
FIG. 8, in the filter circuit including a large number of resistance elements each having a
relatively small resistance value, the area on the semiconductor substrate is suppressed even if
the resistance elements are respectively replaced by the resistance circuits. It is difficult to get
the benefits of However, as described above, since the LPF 30 is configured to include only a
small number of resistance elements having large resistance values, the effect of area
suppression by replacing the resistance circuit may be large. Further, from this point of view, the
configuration of the LPF 30 is not limited to the configuration shown in FIG. 4, and another
circuit configuration can be adopted in which the capacitor can be miniaturized by increasing the
resistance of a few resistance elements.
[0048]
Although the tone control circuit of this embodiment is configured to generate the high tone
range from the difference between the low tone range extracted using the LPF 30 and the
original voice signal, the high tone range and the original voice extracted using the HPF are
conversely A low frequency band may be generated by the difference with the signal.
[0049]
Embodiment 2 FIG. 6 is a schematic block diagram of a graphic equalizer according to a second
embodiment of the present invention.
The tone control circuit of the first embodiment adjusts the gain of the two bands of the high
range and the low range. On the other hand, the graphic equalizer of the present embodiment is
different from the tone control circuit of the first embodiment in that it adjusts the gains of the
three bands of the high range, middle range and low range, but it is basically common There is
also a point to do.
[0050]
08-05-2019
14
The circuit is integrally formed on a semiconductor substrate as an IC. In this circuit, the original
audio signal SIN is input to the input terminal IN, and boost processing and cut processing can be
performed on each of the high, mid, and low bands, and the gain of each band is adjusted. The
output voice signal SOUT is output from the output terminal OUT. In this circuit, switching of
boost / cut for each band and gain setting of boost and cut are performed based on an
instruction signal from an external circuit.
[0051]
The circuit includes a filter block 100, an adjustment signal generation block 102, and a
combining circuit 104. The filter block 100 includes LPFs 110 and 112, inverting circuits 114
and 116, and adder circuits 118 and 120. Further, the adjustment signal generation block 102 is
configured to include a bass range adjustment circuit 122, a mid range adjustment circuit 124,
and a high range adjustment circuit 126.
[0052]
Each of the LPFs 110 and 112 can have the same configuration as that of the first embodiment.
In particular, a switched capacitor can be used to incorporate the capacitors. Here, the cutoff
frequency fC1 of the LPF 110 is set lower than the cutoff frequency fC2 of the LPF 112.
[0053]
The inverting circuits 114 and 116 are circuits similar to the inverting circuit 32 in the tone
control circuit of the first embodiment, and the adding circuits 118 and 120 are circuits similar
to the adding circuit 34. The bass range adjustment circuit 122, the mid range adjustment circuit
124, and the high range adjustment circuit 126 can have, for example, the configuration shown
in FIG.
[0054]
08-05-2019
15
The filter block 100 is provided with an extraction circuit for each band, and extracts a high
range component SHO, a mid range component SMO, and a low range component SLO from SIN.
Specifically, the LPF 110 constitutes a bass range extraction circuit. Further, the LPFs 110 and
112, the inverting circuit 114, and the adding circuit 118 constitute a midrange extraction
circuit. Further, the LPF 112, the inverting circuit 116, and the adding circuit 120 constitute a
high-pitched area extracting circuit.
[0055]
FIG. 7 is a schematic diagram for explaining the principle of extraction processing of each band
component of the present circuit. FIGS. 7 (a) and 7 (b) show the frequency spectrum, where the
horizontal axis is the frequency f and the vertical axis is the signal gain G based on SIN. In FIG.
7A, spectra 130, 132, and 134 respectively indicate the original audio signal SIN, the output
signal SLPF1 of the LPF 110, and the output signal SLPF2 of the LPF 112. Further, spectra 136,
138, and 140 shown in FIG. 7 (b) respectively represent a low range component SLO, a mid
range component SMO, and a high range component SHO included in the original audio signal
SIN.
[0056]
The output signal SLPF1 of the LPF 110 is output from the filter block 100 as a bass range
component SLO and is input to the bass range adjustment circuit 122. That is, the spectrum 130
and the spectrum 136 are common. Further, SLO is inverted by the inverting circuit 114 and
then input to the adding circuit 118. The adder circuit 118 further receives the SLPF 2 from the
LPF 112, obtains the difference between the SLPF 2 and the SLPF 1 as shown in the following
equation, and extracts the midrange component SMO indicated by the spectrum 138. The
extracted SMO is input from the filter block 100 to the midrange adjustment circuit 124.
[0057]
SMO=SLPF2−SLPF1………(5)
[0058]
The output signal SLPF2 of the LPF 112 is input to the addition circuit 118 described above, and
08-05-2019
16
is also input to the inversion circuit 116.
The inverter circuit 116 inverts the SLPF 2 and inputs it to the adder circuit 120. The addition
circuit 120 further receives the original speech signal SIN, obtains the difference between SIN
and SLPF 2 as shown in the following equation, and extracts the high range component SHO
indicated by the spectrum 140. The extracted SHO is input from the filter block 100 to the treble
range adjusting circuit 126.
[0059]
SHO=SIN−SLPF2………(6)
[0060]
The adjustment signal generation block 102 performs gain adjustment on the bass component
SLO, the midrange component SMO, and the treble component SHO to which the bass adjustment
circuit 122, the midrange adjustment circuit 124, and the treble adjustment circuit 126
respectively input. , Low range adjustment signal SLT, middle range adjustment signal SMT, and
high range adjustment signal SHT.
[0061]
The bass adjustment signal SLT, the midrange adjustment signal SMT, and the treble adjustment
signal SHT output from the adjustment signal generation block 102 are input to the synthesis
circuit 104.
The synthesis circuit 104 also receives the original speech signal SIN, adds and synthesizes these
SIN, SLT, SMT, and SHT, and outputs the result as SOUT.
[0062]
As described above, the adjustment signals SLT, SMT, and SHT are generated as signals of
positive polarity at the time of boost according to the mode signal DM in the circuit shown in FIG.
2 as in the first embodiment. At the time of cutting, it is generated as a negative signal.
08-05-2019
17
The synthesis circuit 104 synthesizes these adjustment signals into the original speech signal SIN
so that boost processing is performed in the frequency band in which the positive adjustment
signal is superimposed, and cut processing is performed in the frequency band canceled by the
negative adjustment signal. Generates SOUT that has been
[0063]
In the present embodiment, an example of the graphic equalizer in which the original audio
signal is divided into three frequency bands for adjustment is described as the simplest case, but
the present invention is divided into n frequency bands (n ≧ 3). It can be applied to graphic
equalizers that make adjustments. In that case, (n-1) LPFs are used. Assuming that the cutoff
frequency of the k th LPF (1 ≦ k ≦ n−1) is f c k, f c k is set corresponding to the boundary
between the k th frequency band and the (k + 1) th frequency band, f c 1 <f c 2 < ... <fC (n-2) <fC
(n-1) ... (7)
[0064]
The first extraction circuit extracts the component of the lowest first frequency band from the
original speech signal by the first LPF. In the above embodiment, the LPF 110 corresponds to the
first LPF.
[0065]
The k-th extraction circuit (2 ≦ k ≦ n−1) generates a difference between the output signal of
the k th LPF and the output signal of the (k−1) LPF with respect to the original audio signal,
Output as a component. In the above embodiment, the process shown by equation (5) at the time
of generating the SMO corresponds to the process of generating this difference.
[0066]
The n-th extraction circuit generates a difference between the original speech signal and the
output signal of the (n-1) LPF, and outputs the difference as a component of the n-th frequency
08-05-2019
18
band. In the above embodiment, the process shown by equation (6) at the time of generating SHO
corresponds to the process of generating this difference.
[0067]
Although the graphic equalizer of this embodiment is configured to extract the components of
each frequency band using the LPFs 110 and 112, it may be configured to extract the
components of each frequency band using the HPF.
[0068]
The above embodiment has described the sound quality adjustment circuit which adjusts the
characteristics of an audio signal as an original signal.
However, the present invention can also be applied to a signal characteristic adjustment circuit in
which a signal other than an audio signal is input as an original signal and gain adjustment is
performed for each frequency band. For example, as such a signal characteristic adjustment
circuit, there is one that uses a video signal as an original signal. For example, the present
invention can be applied to a signal characteristic adjustment circuit that boosts / cuts each of
high frequency components and low frequency components with respect to a luminance signal
constituting a video signal.
[0069]
FIG. 1 is a schematic block diagram of a tone control circuit according to a first embodiment of
the present invention. It is a schematic block diagram of the adjustment circuit which performs
gain adjustment with respect to the component for each zone | band. It is a schematic diagram
for demonstrating the principle of the tone control in the 1st Embodiment of this invention. FIG.
2 is a circuit diagram showing a schematic configuration of an LPF used in the embodiment of
the present invention. FIG. 5 is a schematic circuit diagram of an LPF in which the resistor shown
in FIG. 4 is configured by a switched capacitor circuit. FIG. 6 is a schematic block diagram of a
graphic equalizer according to a second embodiment of the present invention. It is a schematic
diagram for demonstrating the principle of the extraction process of each zone | band
component in the 2nd Embodiment of this invention. FIG. 6 is a circuit diagram showing a basic
configuration of a conventional tone control circuit.
08-05-2019
19
Explanation of sign
[0070]
Reference Signs List 20, 100 filter block, 22, 102 adjustment signal generation block, 24, 104
synthesis circuit, 30, 110, 112 LPF, 32, 54, 114, 116 inversion circuit, 34, 118, 120 addition
circuit, 36, 126 high range Adjustment circuit, 38, 122 bass adjustment circuit, 40 amplitude
control block, 42 phase control block, 50 attenuator, 52 amplifier, 56 switch circuit, 124
midrange adjustment circuit.
08-05-2019
20
Документ
Категория
Без категории
Просмотров
0
Размер файла
32 Кб
Теги
jp2008131383
1/--страниц
Пожаловаться на содержимое документа