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JP2011019209

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DESCRIPTION JP2011019209
The present invention provides a digital and practical MFB. SOLUTION: An analog detection
signal for MFB is converted into a digital signal with a predetermined sampling frequency and
the number of quantization bits by delta sigma modulation processing, and the signal processing
means inputs a digital detection signal in this signal format. The digital feedback signal is
generated and synthesized for negative feedback to the input digital audio signal. Then, when
converting the audio signal of the quantization bit number a at the sampling frequency f1 after
this synthesis into an analog signal, delta sigma modulation processing is performed to convert it
into the quantization bit number b (b <a) at the sampling frequency f1. To be done. [Selected
figure] Figure 4
Signal processing apparatus, signal processing method
[0001]
The present invention relates to a signal processing apparatus and method for performing signal
processing according to a predetermined purpose for an audio signal.
[0002]
In the field of sound, MFB (Motional FeedBack: motional feedback) has long been known.
The MFB is a technology that detects the movement of the diaphragm in the speaker unit, applies
negative feedback to the input audio signal, and controls, for example, the diaphragm of the
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speaker unit and the input audio signal in the same movement. As a result, for example, damping
is given to the vibration around the low frequency resonance frequency f0, and in the sense of
hearing, the undesirable low frequency sound called so-called "boning" is suppressed.
[0003]
Unexamined-Japanese-Patent No. 9-289699
[0004]
By the way, the signal processing system for MFB, which has been put into practical use so far, is
configured by an analog circuit.
In order to effectively obtain the effect by MFB, a detection signal obtained by detecting the
movement of the speaker diaphragm by a sensor, a circuit or the like and a speaker driven by an
audio signal fed back with the detection signal are used. It is necessary to keep the phase
difference with the playback sound within a certain range. If this phase difference does not fall
within a certain range and exceeds an allowable range, for example, oscillation or the like is likely
to occur, which is practically impossible.
[0005]
Here, by replacing the analog circuit with a digital circuit, it is easier to change or switch the
characteristic or the operation mode without changing the physical constant of the component
element or changing it, which is a great advantage. It can be enjoyed. However, when the signal
processing system of the MFB is to be configured by digital circuits, an A / D converter and a D /
A converter are respectively provided at the input stage of the detection signal and the output
stage of the audio signal after feedback. In the processing time of the A / D converter and D / A
converter widely used at present, the delay is considerably large when considering adoption as
an MFB signal processing system, and it is difficult to obtain an effective control effect. For
example, in the fields of military, industrial, etc., there are A / D converters and D / A converters
with high sampling frequency and low delay, but these are extremely expensive and should be
adopted in consumer equipment Is not realistic. Under the present circumstances, the reason
why the MFB signal processing system is configured not by digital circuits but by analog circuits
is as described above.
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[0006]
Therefore, it is an object of the present invention to provide an MFB signal processing circuit
which is sufficiently practical even while adopting a digital circuit.
[0007]
In order to solve the above-mentioned subject, the present invention is constituted as follows as a
signal processing device.
That is, by inputting the analog detection signal obtained by detecting the movement of the
diaphragm of the speaker and performing the first delta sigma modulation process, the
predetermined sampling frequency and the predetermined quantization bit of one bit or more
Analog-to-digital conversion means for converting into digital signals by numbers and outputting
the same, and signal processing means for receiving the digital detection signals output from the
above analog-to-digital converting means and generating and outputting digital feedback signals
The feedback signal is synthesized by negative feedback with respect to the digital input audio
signal to be reproduced as sound by the speaker, and in the synthesis stage, the input audio
signal is quantized with the same sampling frequency as the feedback signal. A combining unit
that combines bits after setting the number of bits, and a feedback signal after output from the
combining unit A digital audio signal with a fixed sampling frequency f1 and a quantization bit
number a is input and converted to an analog signal, and the digital audio signal after the
feedback signal synthesis is input, and the sampling frequency f1 is A digital-to-analog
conversion unit is provided, which is formed to have at least an execution part of the second
delta sigma modulation processing of converting into a digital signal according to the number of
quantization bits b (b <a).
[0008]
In the above configuration, the analog detection signal for the MFB is converted into a digital
signal with a predetermined sampling frequency and the number of quantization bits by the first
delta sigma modulation process. The signal processing means inputs the digital detection signal
in this signal format to generate a digital feedback signal, and is synthesized for negative
feedback to the input digital audio signal. Then, when converting the audio signal of the
quantization bit number a at the sampling frequency f1 after this synthesis into an analog signal,
delta sigma modulation processing is performed to convert it into the quantization bit number b
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(b <a) at the sampling frequency f1. To be done. The configuration of such a signal processing
system can be viewed as, for example, such that decimation processing in A / D conversion
processing and oversampling processing in D / A conversion processing are omitted. These
processes require corresponding processing time. Therefore, in the configuration of the signal
processing system of the present invention, the signal propagation time is shortened by not
executing these processes.
[0009]
As described above, by shortening the signal propagation time, it is possible to satisfy the
condition of the response speed required for the MFB signal processing system. That is,
commercialization of MFB by digital can be easily realized. As described above, since the digital
MFB becomes practical, advantages such as the implementation of functions that are difficult
with the analog circuit and high sound quality can be enjoyed.
[0010]
FIG. 6 is a block diagram showing an example of a basic configuration of a digital MFB signal
processing system. It is a figure which shows the example of a mode of the signal processing
structure of the MFB corresponding | compatible digital signal processing part in DSP. FIG. 7 is a
block diagram showing a specific configuration example of a digital MFB signal processing
system that can be considered properly at present according to the basic configuration shown in
FIG. 1. It is a block diagram showing an example of composition of a MFB signal processing
system as a 1st embodiment. It is a figure which shows the structural example of the digital filter
with which the MFB corresponding | compatible digital signal processing part of embodiment is
provided. It is a block diagram showing an example of composition of a MFB signal processing
system as a 2nd embodiment. It is a block diagram showing an example of composition of a MFB
signal processing system as a 3rd embodiment. It is a figure which shows the example which
applied the structure of the MFB signal processing system of embodiment to the headphone
(overhead type). It is a figure which shows the example which applied the structure of the MFB
signal processing system of embodiment to the headphones (ear ear type | mold). It is a figure
which shows the structural example of the MFB signal processing system by analog.
[0011]
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Hereinafter, modes for carrying out the present invention (hereinafter referred to as
embodiments) will be described in the following order. <1. Configuration Example of Analog
MFB Signal Processing System> <2. Digital MFB Signal Processing System: Basic Configuration
Example> <3. Digital MFB signal processing system: Specific configuration example conceivable
in the present situation> <4. Digital MFB Signal Processing System First Embodiment> <5. Digital
MFB Signal Processing System: Second Embodiment> <6. Digital MFB Signal Processing System:
Third Embodiment> <7. Example of application to headphones>
[0012]
<1. Configuration Example of Analog MFB Signal Processing System> Since an acoustic device
such as a speaker has a physical mechanism portion movable by a signal, distortion is large
compared to, for example, a system of only an electric circuit. As a result, the system can not
sufficiently follow the input voice signal, and this is considered to be a major cause of the sound
quality deterioration. Therefore, in the system that reproduces an audio signal by a speaker, a
system that converts an actual driving condition of the speaker, such as the vibration behavior of
the speaker or the sound pressure released into space, into an electric signal and feeds it back is
incorporated. In the past, techniques have been proposed to reduce the distortion and improve
the quality of reproduced speech. This is called MFB (Motional FeedBack). More specifically, by
applying the MFB, unnecessary vibration of the speaker unit diaphragm is suppressed, for
example, in the vicinity of the low resonance frequency f0, so that the undesirable low-pitched
sound called so-called "boning" is suppressed. Sound is obtained.
[0013]
FIG. 10 shows an example where the signal processing system (MFB signal processing system)
corresponding to the MFB is configured by an analog circuit. In this figure, an analog audio
signal is first subjected to low-pass compensation, which will be described later, by the low-pass
correction equalizer 101, and is output to the synthesizer 102.
[0014]
The synthesizer 102 receives the audio signal from the low band correction equalizer 101 and
the signal from the signal processing circuit 107. The signal from the signal processing circuit
107 is an MFB feedback signal obtained based on the detection of the movement of the speaker
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unit 104 as described later. The synthesizer 102 synthesizes the inverted feedback signal with
the audio signal from the low pass correction equalizer 101. That is, the audio signal is output by
applying negative feedback to the feedback signal.
[0015]
The audio signal output from the synthesizer 102 is amplified by the power amplifier 103 and
output to the speaker unit 104. Thus, the speaker unit 104 reproduces the sound according to
the audio signal.
[0016]
A bridge circuit 105 including resistors R1, R2 and R3 is provided on the line of the drive signal
from the power amplifier 103 to the speaker unit 104 corresponding to the MFB, and the output
thereof is input to the detection / amplification circuit 106. It has become. The detection /
amplification circuit 106 amplifies a signal obtained by detecting the back electromotive force
generated in the voice coil in the speaker unit 104, and outputs the amplified signal to a low pass
filter (LPF: Low Pass Filter) in the signal processing circuit 107. The back electromotive force
detected by the bridge circuit 105 corresponds to detecting the speed as the movement of the
diaphragm of the speaker unit 104 as it is.
[0017]
The signal processing circuit 107 is configured to generate a feedback signal from the detection
signal from the detection / amplification circuit 106. For example, the signal processing circuit
107 includes a filter circuit for removing noise components in the detection signal, and a gain
circuit for adjusting the gain of the feedback signal. The feedback signal generated by the signal
processing circuit 107 is output to the synthesizer 102.
[0018]
Thus, the input audio signal is subjected to negative feedback in accordance with the movement
of the diaphragm of the speaker unit 104, and the speaker unit 104 is driven by the amplified
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output of the audio signal subjected to the negative feedback. As a result, the control system of
the MFB controls the speaker unit 104 so as to faithfully vibrate with respect to the input audio
signal waveform. This is an operation of providing damping, for example, around the low band
resonance frequency f0, and as a result, for example, as described above, unnecessary noise in
the low band is suppressed and the reproduced sound is improved.
[0019]
However, since the damping is given centering on the low band resonance frequency f0 as
described above, the power of the low band tends to be reduced as the frequency characteristic
of the reproduced sound. The low band correction equalizer 101 is provided to compensate for
the reduction of the low band power. That is, the low band correction equalizer 101 equalizes the
input audio signal so that the low band attenuated by the MFB is corrected (band compensation)
in advance to obtain the target frequency characteristic of the final reproduced voice. I do.
[0020]
<2. Digital MFB Signal Processing System: Basic Configuration Example> Although the MFB
signal processing system shown in FIG. 10 is analog, if this system is configured digitally, for
example, the following many advantages can be obtained. First, the process of feedback
(feedback) is a digital operation using, for example, a digital filter, so that in principle, it is not
affected by noise from the periphery or the outside, and processing results with high accuracy
can be expected. In the case of an analog circuit, it is difficult to obtain sufficiently high accuracy
because of variations in the manufacture of electronic component elements, but in the case of
digital operation, such variations do not cause errors in calculation results. . As a result, for
example, control with performance as designed can be expected. In addition, since it is not
necessary to set control design margins for amplitude, phase, etc. in consideration of variations,
and it is possible to set them to be severe, large feedback can be obtained, and high performance
can be expected. In addition, because of the operation by the digital filter, complex filter
characteristics that can not be designed by the analog filter can be obtained, and, for example,
finer control becomes possible. Further, at this time, as long as the resource of the arithmetic
processing unit such as DSP is not insufficient, for example, complicated characteristics can also
be set by software without an increase in cost. Furthermore, in the case of a digital circuit,
software control is possible, and it becomes easy to appropriately change the way of feedback
such as the amount of feedback. As a result, for example, control in a wide range of application is
possible, such as adapting to the characteristics of the connected speaker and changing and
setting the control.
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[0021]
Therefore, consider a configuration in which a digital circuit is adopted for the MFB signal
processing system. FIG. 1 shows an example of the basic configuration in the case where an MFB
signal processing system is configured by adopting a digital circuit. The MFB signal processing
system shown in this figure mainly includes a DSP 11, a DAC 12, a power amplifier 13, a speaker
unit 14, a bridge circuit 15, a detection / amplification circuit 16, and an ADC 17.
[0022]
The input audio signal in this case is a digital audio signal reproduced from a digital audio
source. The digital audio signal is input to a DSP (Digital Signal Processor) 11. In the DSP 11, a
signal processing unit of the digital equalizer 11a, the synthesizer 11b, and the MFB compatible
digital signal processing unit 11c is formed. Note that these signal processing functions in the
DSP 11 are realized by a program called an instruction, for example, which is given to the DSP
11.
[0023]
The digital audio signal input to the DSP 11 is first input to the digital equalizer 11a. The digital
equalizer 11a corresponds to the low band correction equalizer 101 of FIG. 10, and performs
equalization of the digital audio signal with a predetermined equalizing characteristic. As a result,
the digital equalizer 11a performs band compensation so that the target frequency
characteristics can be obtained for the reproduced sound from the speaker unit 14 to which the
MFB has been applied.
[0024]
The digital audio signal output from the digital equalizer 11a is output to the synthesizer 11b.
The synthesizer 11b is a part for giving negative feedback to the input audio signal, and inverts
and synthesizes the feedback signal output from the MFB compatible digital signal processing
unit 11c with respect to the input digital audio signal. .
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[0025]
In this case, the digital audio signal as the output of the synthesizer 11 b is input to the DAC (D /
A converter) 12 as the output of the DSP 11. The DAC 12 converts an input digital audio signal
into an analog audio signal.
[0026]
The power amplifier 13 amplifies the analog audio signal from the DAC 12 and supplies it as a
drive signal to the voice coil of the speaker unit 14. Thus, the sound of the digital audio source is
reproduced from the speaker unit 14.
[0027]
Similar to the bridge circuit 105 of FIG. 10, the bridge circuit 15 is formed by connecting the
resistors R1, R2, and R3 to the line of the drive signal from the power amplifier 13 to the speaker
unit 14 as illustrated. . Similar to the detection / amplification circuit 106 of FIG. 10, the
detection / amplification circuit 16 inputs a signal from the sensor portion as the bridge circuit
15, and generates a detection signal according to the speed as the movement of the speaker unit
14. Do.
[0028]
In this case, the analog detection signal output from the detection / amplification circuit 16 is
converted into a digital signal by the ADC (A / D converter) 17 and input to the MFB compatible
digital signal processing unit 11 c of the DSP 11.
[0029]
The MFB compatible digital signal processing unit 11 c corresponds to a signal processing
system as a so-called feedback circuit, and generates a feedback signal from the input digital
detection signal.
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FIG. 2 shows three examples of the configuration of the MFB-compliant digital signal processing
unit 11 c on the premise that the detection signal of speed proportionality is obtained by the
bridge circuit 15. Speed control, acceleration control, displacement control, etc. are known as
feedback control methods in MFB, but here, speed control / acceleration control, or speed control
and the like, corresponding to the bridge circuit 15 being provided. The structure corresponding
to the case where the combined use type of acceleration control is adopted is shown by FIG. 2 (a)
(b) (c).
[0030]
First, FIG. 2 (a) shows a configuration provided with a digital filter 34a as one corresponding to
speed control. The digital filter 34a is, for example, an FIR (Finite Impulse Response) type or IIR
(Infinite Impulse Response) type. The signal processing function of the digital filter 34a includes,
for example, an LPF for removing an unnecessary frequency band component corresponding to
noise from a detection signal corresponding to speed, and a gain circuit for setting a gain when
outputting as a feedback signal. Ru. Since feedback is applied to the input audio signal by the
feedback signal corresponding to the velocity, an operation to brake the diaphragm of the
speaker unit 14 in accordance with the detected velocity can be obtained as the MFB. That is, the
operation of MFB by speed control can be obtained.
[0031]
FIG. 2B shows a configuration corresponding to acceleration control, and as shown in FIG. 2B,
includes a differentiation processing unit 34b and a digital filter 34c. The differential processing
unit 34 b performs differential operation on the input detection signal and outputs the result. As
described above, the detection signal obtained from the bridge circuit 15 indicates the speed of
the speaker diaphragm. Therefore, by differentiating the detection signal corresponding to the
speed, a signal indicating the acceleration of the speaker diaphragm is obtained. That is, the
differentiation processing unit 34b obtains a detection signal corresponding to acceleration from
the detection signal corresponding to speed. The digital filter 34c performs, for example, the
same signal processing as that of FIG. 2A on the signal output from the differentiation processing
unit 34b, and outputs it as a feedback signal corresponding to acceleration control. By
feedbacking the input audio signal by this feedback signal, the operation of the MFB as
acceleration control can be obtained.
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[0032]
FIG. 2C shows a configuration in which speed control and acceleration control are used in
combination, and includes a digital filter 34a, a differential processing unit 34b, a digital filter
34c, and a synthesizer 34d. The digital filter 34a is provided corresponding to the speed control
as shown in FIG. 2A, and the differential processing unit 34b and the digital filter 34c correspond
to the acceleration control as shown in FIG. 2B. Do. In this case, the detection signal is branched
and input to a system of the digital filter 34a and a system including the differentiation
processing unit 34b and the digital filter 34c. A feedback signal corresponding to speed control
is output from the digital filter 34a, and a feedback signal corresponding to acceleration control
is output depending on the signal processing of the differentiation processing unit 34b-digital
filter 34c. The synthesizer 34d synthesizes and outputs feedback signals corresponding to the
speed control and the acceleration control. That is, in this case, the feedback signal output from
the MFB compatible digital signal processing unit 11c is a combination of the speed control
component and the acceleration control component. Since feedback to the input audio signal is
performed by the feedback signal, as the operation of the MFB, a control according to the
velocity and a control according to the acceleration are obtained in combination.
[0033]
In FIG. 1, the bridge circuit 15 is provided as a sensor for detecting the movement of the speaker
diaphragm, so that the speed is first detected as the movement of the speaker diaphragm. Other
sensor configurations based on MFB are conceivable. For example, as a sensor for speed
detection, a sensor coil separate from the voice coil of the speaker unit can be provided, and the
current obtained by this sensor coil can be detected. Further, the sound pressure emitted from
the speaker unit by the microphone can be detected, and a detection signal corresponding to the
detected sound pressure can be treated as the acceleration of the speaker unit diaphragm.
Furthermore, a physical acceleration sensor can be provided on the diaphragm of the speaker
unit to detect the acceleration. Furthermore, it is also conceivable to obtain a detection signal
according to the displacement of the speaker unit diaphragm by detecting the movement of the
diaphragm of the speaker unit by the change in capacitance. When the MFB signal processing
system is to be configured by a digital circuit as shown in FIG. 1, any sensor configuration may
be adopted without particular limitation. This point is the same as in the case of configuring the
MFB signal processing system of the present embodiment described later.
[0034]
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<3. Digital MFB Signal Processing System: Specific Configuration Example that Can Be
Considered Presently> FIG. 3 shows MFB signals actually using digital devices currently known
under the basic configuration shown in FIGS. 1 and 2 described above. When it is assumed that a
processing system is constructed, one concrete configuration example which can be considered
properly is shown. In the following description, it is assumed that the reference sampling
frequency indicated by Fs (1Fs) indicates the sampling frequency of a digital audio signal as a
digital audio source that is originally intended to be heard by the headphone device. A specific
example of the digital audio source here is a digital audio signal recorded on a CD (compact disc),
etc., which has Fs = 44.1 kHz and has a quantization bit number of 16 bits. . Further, in this
figure, the same parts as in FIG. 1 are given the same reference numerals. The entire
configuration shown in this figure and the portion formed by the analog are the same as the
explanation of FIG.
[0035]
First, the ADC 17 will be described. The ADC 17 in this case is, for example, actually one
component or device, receives an analog detection signal output from the detection /
amplification circuit 16, and has a sampling frequency of 1 Fs, which is the same as a digital
audio source described later. Then, it is converted into a digital signal (PCM signal) digitalized
(quantized) by a quantization bit number ([1 Fs, 16 bits]) of 16 bits and output.
[0036]
As a configuration therefor, the ADC 17 in this case includes a delta sigma (ΔΣ) modulator 17a,
a decimation filter 17b, and an output buffer 17c as illustrated. The analog audio signal input to
the ADC 17 is first converted to a [64 Fs (= 2.8 224 MHz), 1 bit] digital signal by the delta sigma
modulator 17 a. The [64 Fs, 1 bit] digital signal is converted to a [1 Fs, 16 bit] digital signal by
passing through, for example, a decimation filter 17 b of FIR (Finite Impulse Response), and
further output signal in the digital signal stage by the output buffer 17 c. Amplification is
performed. The output of the output buffer 17c is input as the output of the ADC 17 to the MFB
compatible digital signal processing unit 11c of the DSP 11 in this case.
[0037]
The DSP 11 in this example is provided as, for example, one chip component, and for example,
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according to an instruction (program), as a signal processing function thereof, digital signal
processing corresponding to digital equalizer 11a, synthesizer 11b, MFB as in FIG. It has the part
11c.
[0038]
The MFB-compliant digital signal processing unit 11c in this case has, for example, a
configuration as an FIR filter, and is formed to receive a 16-bit quantization bit number signal
and to multiply the 16-bit coefficient.
As a result, the format of the feedback signal output from the MFB compatible digital signal
processing unit 11c is also [1Fs, 16 bits], which is the same as the input detection signal.
[0039]
Also, in the DSP 11, a signal of a digital audio source is inputted, and the signal of this digital
audio source is a digital audio signal of the form [1 Fs, 16 bit]. The digital equalizer 11a to which
the signal of the digital audio source is input is also configured as an FIR filter, for example, as in
the MFB-compatible digital signal processing unit 11c, and inputs a signal having a quantization
bit number of 16 bits, It is formed as an arithmetic circuit which multiplies coefficients. As a
result, the digital audio signal after frequency characteristic correction output from the digital
equalizer 11a is also in the form of [1 Fs, 16 bits].
[0040]
The synthesizer 11b synthesizes the digital audio signal of the same [1 Fs, 16 bit] and the
inverted feedback signal as processing to apply negative feedback. Therefore, the digital audio
signal output from the synthesizer 11b to the DAC 12 is also in the form of [1Fs, 16 bits].
[0041]
The DAC 12 is also provided as, for example, one chip component, and converts it into an analog
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signal in response to the digital signal of the type converted by the ADC 17 described above. As
its internal configuration, for example, as illustrated, it has an oversampling filter 12a, a delta
sigma modulator 12b, and an analog LPF (Low Pass Filter) 12c.
[0042]
The [1 Fs, 16 bit] digital signal input to the DAC 12 is oversampled by the over sampling filter 12
a, converted to a [64 Fs, 16 bit] format digital signal, and output to the delta sigma modulator 12
b Ru. The delta sigma modulator 12 b converts the input digital signal into one bit. That is, the
digital signal is converted to a digital signal of [64 Fs, 1 bit] and output. Then, by passing the [64
Fs, 1 bit] digital signal which is the output of the delta sigma modulator 12 b to the analog LPF
12 c, an analog audio signal is obtained as the output. That is, the [1Fs, 16 bit] digital audio
signal input to the DAC 12 is converted to an analog audio signal, and this is input to the power
amplifier 13 as the output of the DAC 12.
[0043]
The configuration shown in FIG. 3 uses, for example, an A / D converter, a DSP, a D / A converter,
etc. which are easily available for consumer use, and in the present situation, an MFB system
(MFB signal processing system) based on a digital system in practice For example, in the case
where it is intended to create a device corresponding to an audio source such as a CD, for
example, the configuration can be considered properly first.
[0044]
However, in the above configuration, it has been found that it is practically difficult to obtain a
sufficient MFB control effect for practical use.
This is because the signal processing time of the actual device as the ADC 17 and the DAC 12,
that is, the delay between the input and the output, is considerably large. Essentially, these
devices are supposed to handle audio signals as audio sources such as ordinary music pieces in a
single way, so even if the signal processing causes delays, this is not a problem The However,
when such a device is used as it is for the MFB signal processing system, the delay becomes so
large that it can not be ignored. That is, even in the entire MFB signal processing system
configured using these devices, the audio signal to which feedback is applied after the detection
signal is obtained by the detection / amplification circuit 16 from the output from the bridge
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circuit 15 A large delay occurs in the time until the unit 14 is reproduced and output as sound
(response speed). Due to this delay, the feedback operation as the MFB is considerably delayed,
and in practice, good control results can not be obtained. For example, with the ADC 17 alone, if
the delay at a sampling frequency of 44.1 KHz is 40 samples, then the phase delay of a signal of
about 550 Hz or more will be 180 ° or more. In this way, even with A / D conversion alone, this
phase rotation is caused, and if filter processing such as LPF (Low Pass Filter) and BPF (Band
Pass Filter) is added to this. Furthermore, the phase rotation becomes larger. If the delay is
increased to this extent, not only the control effect by the MFB can not be obtained, but also a
phenomenon such as howling tends to occur. Therefore, in order to maintain the stability as a
system, the frequency band to be controlled by the MFB is considerably narrowed. That is, in the
configuration as shown in FIG. 3, the effect of MFB can not be obtained until it is sufficient for
practical use. This is the reason why up to now only MFB by analog system has been put to
practical use.
[0045]
However, as described above, the merit of adopting the digital method for the MFB signal
processing system is great. Therefore, as the present embodiment, as will be described later, a
configuration for solving the above-mentioned problem of delay while adopting a digital method
for an MFB signal processing system is proposed.
[0046]
<4. Digital MFB Signal Processing System: First Embodiment FIG. 4 shows a configuration
example of an MFB signal processing system according to the first embodiment. In this figure,
the same parts as those in FIG. 3 are assigned the same reference numerals, and the explanation
thereof is omitted or simplified. In the configuration shown in this figure, first, an ADC 20 is
provided in place of the ADC 17 of FIG. The ADC 20 is, for example, one chip part, and includes
only the delta sigma modulator 21 as illustrated. The delta sigma modulator 21 converts the
input analog signal into a digital signal of the form [64 Fs (= 2.8224 MHz), 1 bit]. Then, the
output of the delta sigma modulator 21 is input to the DSP 30 as the output of the ADC 20.
[0047]
The DSP 30 is also, for example, one chip part. The DSP 30 in this case is configured to include
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the digital equalizer 31, the oversampling filter 32, the synthesizer 33, and the MFB-compatible
digital signal processing unit 34 as illustrated.
[0048]
The MFB compatible digital signal processing unit 34 in FIG. 4 has a signal processing function
as a feedback circuit that generates a feedback signal from the detection signal, as in the MFB
compatible digital signal processing unit 11 c of the DSP 11 in FIG. 3. However, in the MFBcompliant digital signal processing unit 11c of the DSP 11 of FIG. 3, the format of the input /
output digital audio signal is set to [1 Fs, 16 bits]. On the other hand, in the MFB compatible
digital signal processing unit 34 in FIG. 4, the output is [64 Fs, 16 bit] by performing the
operation with the coefficient of 16 bits after the input is [64 Fs, 1 bit]. ing. The MFB-compliant
digital signal processing unit 34 can be formed by, for example, a digital filter of FIR, and
therefore, the output thereof will be multibit, but the number of quantization bits as the multibit
is So, it's 16 bits. Thus, the reason why the format of the feedback signal output from the MFB
compatible digital signal processing unit 34 is [64 Fs, 16 bit] is understood from the following
description that the format of the digital audio signal at the synthesis stage is To match [64 Fs,
16 bit].
[0049]
Further, as for the digital equalizer 31 of FIG. 4, similarly to the digital equalizer 11a of FIG. 3, a
signal (digital audio signal) of a digital audio source in the form of [1 Fs, 16 bit] is input to
perform low frequency compensation. The equalizing process is performed by calculation using
16-bit coefficients. Then, an audio signal of the same [1 Fs, 16 bit] format as the input is output.
[0050]
In this case, the audio signal of [1 Fs, 16 bits] output from the digital equalizer 31 is input to the
oversampling filter 32. The oversampling filter 32 in this case converts the digital audio signal
from [1 Fs, 16 bits] to [64 Fs, 16 bits] and outputs it. Here, the signal of the digital audio source
is converted into [64 Fs, 16 bit] in order to make the digital signal format the same as the
feedback signal output from the MFB compatible digital signal processing unit 34.
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[0051]
The synthesizer 33 inputs the signal of the digital audio source in the same [64 Fs, 16 bit] format
and the feedback signal as described above. Then, a feedback signal obtained by inverting the
phase of the signal of the digital audio source is synthesized, and a digital audio signal subjected
to feedback is output. The output of the synthesizer 33 is input to the DAC 40 as the output of
the DSP 30.
[0052]
The DAC 40 shown in FIG. 4 is also, for example, one component. The DAC 40 includes a delta
sigma modulator 41 and an analog LPF 42. In comparison with the DAC 12 of FIG. 3, the DAC 40
can be viewed as omitting the oversampling filter 12a.
[0053]
The delta sigma modulator 43 inputs the digital audio signal of [64 Fs, 16 bits] outputted from
the synthesizer 33 of the DSP 30 into one bit, converts it into a digital signal of [64 Fs, 1 bit] and
outputs it. The digital signal as the output of the delta sigma modulator 41 is converted to an
analog audio signal via the analog LPF 42 and becomes the output of the DAC 40. The analog
audio signal thus obtained is amplified by the power amplifier 13 to drive the speaker unit 14.
[0054]
Here, in the configuration of FIG. 4 above, a feedback signal is generated from the detection
signal detected by the bridge circuit 15 and the detection / amplification circuit 16, and an input
audio signal composed of this feedback signal (inverted) is generated by the speaker unit 14.
Focus on the digital signal processing system until it is output as sound. Then, this digital signal
processing system can be considered to execute digital signal processing in the order of the delta
sigma modulator 21, the MFB compatible digital signal processing unit 34, the synthesizer 33,
the delta sigma modulator 41, and the analog LPF 42. . This can be regarded as not passing
through the A / D conversion side decimation filter and the D / A conversion side oversampling
filter in comparison with FIG.
08-05-2019
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[0055]
As described above, in the configuration shown in FIG. 3, the delay in the ADC 17 and the DAC
12 is large, but in fact, the delay due to the decimation filter 17 b is dominant in the ADC 17 as a
factor of these delays. The delay due to the oversampling filter 12a is dominant. This is focused
on in the present embodiment. That is, in the digital signal processing system of MFB, in order to
eliminate the influence of the delay due to the decimation filter on the A / D conversion side and
the oversampling filter on the D / A conversion side, the input of the MFB compatible digital
signal processing unit 34 in the DSP 30 The output is directly connected to each of the delta
sigma modulator 21 (ADC 21) and the delta sigma modulator 41 (in the DAC 40). In this manner,
in the MFB signal processing system, the dominant delay factors on the D / A conversion side
and the A / D conversion side are eliminated, whereby the signal processing delay for the MFB is
significantly shortened. In response to this, the above-described phase rotation also becomes
smaller, and as a result, the control effect of MFB which is considered sufficient for practical use
can be obtained. That is, it is possible to obtain an MFB system that can be put into practical use
while being digital.
[0056]
Furthermore, in the present embodiment, by configuring the MFB-compliant digital signal
processing unit 34 with a small delay, it is possible to obtain a more practical and highperformance MFB signal processing system. In order to configure the MFB-compliant digital
signal processing unit 34 with less delay, for example, the configuration as described below can
be considered. First, when an FIR digital filter (FIR filter) is generally adopted as the MFBcompliant digital signal processing unit 34, a configuration as shown in FIG. 5 (a) is adopted.
That is, assuming that the MFB-compliant digital signal processing unit 34 is configured by an 8tap FIR filter, as shown in the figure, first, seven delay devices of delay devices D1 to D7 are
connected in series to make a shift register Form Then, coefficient units h0 to h7 which receive
the input data of the delay unit D1 and the output data of the delay units D1 to D7, which are the
outputs from the shift register, and which perform multiplication by a predetermined coefficient,
and these coefficients And an adder P for adding the outputs of the units h0 to h7. In this case,
since the input digital signal is in the form of [64 Fs, 1 bit], the delay units D1 to D7 and the
coefficient units h0 to h7 input 1-bit signals. In addition, the output of the coefficient unit h0 to
h7 corresponds to the format of [64 Fs, 16 bit], and the coefficient unit h0 to h7 is set to 16 bits
as the multi-bit to obtain the coefficient unit h0 to h0. The output of h7 is made to be 16 bits,
and this is added by the adder P.
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[0057]
In the configuration shown in FIG. 5A, the input data of the delay unit D1 and the 8-bit data
obtained by arranging the output data of the delay units D1 to D7 correspond linearly to the bit
pattern thereof. It can be seen that it is converted to the bit pattern of and output. Based on this,
as shown in FIG. 5B, the MFB compatible digital signal processing unit 34 can be configured by
the delay devices D1 to D7 and the ROM 60. In FIG. 5B, 8-bit input data of 1-bit delay unit D1 at
the same timing and output data of 1-bit each delay units D1 to D7, which are regarded as the
output of the shift register, respectively. As data is formed, the address of the ROM 60 is
specified by this 8-bit data. Since there are 256 bit patterns that can be expressed by 8 bits, 0 to
255 are set as the address of the ROM 60. Then, in the ROM 60, an appropriate 16-bit bit pattern
is stored in correspondence with each of the addresses 0-255. With such a configuration, it is
possible to obtain an operation of designating addresses 0 to 255 to the ROM 60 at the timing of
each sample and reading out data of a 16-bit bit pattern corresponding to the designated address
from the ROM 60. . The 16-bit data read out in this manner is used as the output of the MFBcompliant digital signal processing unit 34 of this embodiment. In such a configuration, the
coefficient multipliers h0 to h7 and the adder P as shown in FIG. 5A are omitted, and these
processes are realized as reading from the specified address to the ROM 60, and the circuit The
scale is simple.
[0058]
Further, as another configuration for providing the MFB-compliant digital signal processing unit
34 with a small delay, for example, a filter of a minimum phase shift type may be mentioned. This
can be realized, for example, by setting the pattern of coefficients to be set in the coefficient
multipliers h0 to h7 in the configuration shown in FIG. 5A so as to be the minimum phase shift
type. Alternatively, it may be considered to be configured by a digital filter of IIR (Infinite Impulse
Response). As a result, the IIR filter has the property that the delay amount is small.
[0059]
In the present embodiment, the sampling frequency of the output signal of the MFB compatible
digital signal processing unit 34 is to be set as follows. First, the DSP 30 in this case inputs the
signal (digital audio signal) of the digital audio source as [1 Fs, 16 bits], and converts it into the
format of [64 Fs, 16 bits] by oversampling processing by the oversampling filter 32. It is
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supposed to be. There is no change in the form of input / output for the synthesizer 33. That is,
64 Fs is set as the sampling frequency of the digital audio signal to be output from the DSP 30
after oversampling.
[0060]
In response to this, the delta sigma modulator 41 of the DAC 40 which receives the digital audio
signal from the DSP 30 is configured to convert a signal of the [64 Fs, 16 bit] format into a 1 bit
signal. Therefore, the output of the delta sigma modulator 41 is in the form of [64 Fs, 1 bit]. In
addition, in the present embodiment, the feedback signal output from the MFB compatible digital
signal processing unit 34 is input to the synthesizer 33, and the oversampling filter is not passed.
From this, the feedback signal should be in the form of [sampling frequency, number of
quantization bits] corresponding to the input of the delta sigma modulator 41 (corresponding to
the output of the oversampling filter via the combiner 33). become. For this purpose, the format
of the feedback signal output from the MFB compatible digital signal processing unit 34 in FIG. 2
is [64 Fs, 16 bits]. Further, in view of only the sampling frequency, the feedback signal output
from the MFB compatible digital signal processing unit 34 should be set to be the same as the
signal of the output of the delta sigma modulator 41. Here, the sampling frequency after
oversampling, that is, the sampling frequency of the output signal (feedback signal) of the MFB
compatible digital signal processing unit 34 in this embodiment is 64 Fs, but it is not limited to
this. In other words, although it is possible to obtain, for example, a reproduction sound of a
certain quality or more, if it is larger than 1 Fs which is a sampling frequency of a digital audio
signal (PCM (Pulse Code Modulation) signal) as a digital audio source handled here. The
frequency value may be set to be sufficient. More specifically, for example, the sampling
frequency of the feedback signal in which the coefficient of Fs is represented by a power of 2
with 2Fs as the lower limit relative to the sampling frequency Fs of the PCM signal as a digital
audio source (sampling frequency after oversampling) Will be set. In reality, it is preferable to set
4 Fs or more.
[0061]
<5. Digital MFB Signal Processing System: Second Embodiment Next, a configuration example
of an MFB signal processing system according to the second embodiment will be described with
reference to FIG. In this figure, the same parts as in FIG. 4 are assigned the same reference
numerals and explanation thereof is omitted. First, the basic configuration of the second
embodiment will be described. The DAC 40 shown in this figure is roughly composed of an
oversampling filter 44, a combiner 45, a delta sigma modulator 41, a PWM (Pulse Width
08-05-2019
20
Modulation) modulator 43, and an analog LPF 42. In this configuration, in the DAC 40 shown in
FIG. 4, the PWM modulator 43 is inserted between the delta sigma modulator 41 and the analog
LPF 42.
[0062]
Also, the signal of the digital audio source in the [1Fs, 16 bit] format in this case is input to the
digital equalizer 31 in the DSP 30, and is input to the oversampling filter 44 of the DAC 40 in the
same [1Fs, 16 bit] format. Depending on the oversampling filter 44 in this case, the digital signal
according to the above [1 Fs, 16 bit] is input, converted into the form of [16 Fs, 16 bit], and
output.
[0063]
Then, depending on the synthesizer 45 in the DAC 40, digital signals of [16Fs, 16 bits] should be
synthesized. Therefore, the feedback signal output from the MFB compatible digital signal
processing unit 34 in this case should be in the form of [16 Fs, 16 bit], not [64 Fs, 16 bit] in the
case of FIG. . Therefore, regarding the sampling frequency, the MFB compatible digital signal
processing unit 34 in this case should include decimation processing for outputting the input of
64 Fs by 16 Fs. That is, it is configured to have a function as a decimation filter 34e as well as
the function of generating an original feedback signal. Several such configurations can be
considered, but one of the most efficient ones is that the configuration of the digital filters 34 a
and 34 c in the MFB compatible digital signal processing unit 34 has the characteristics of the
LPF, It is conceivable to use these digital filters as decimation filters as they are. The decimation
filter also has characteristics as an LPF.
[0064]
In the synthesizer 45, the [16Fs, 16 bit] feedback signal output from the MFB compatible digital
signal processing unit 34 with respect to the digital audio signal of the digital audio source
oversampled by the oversampling filter 44 into [16Fs, 16 bit]. Add and combine. The synthesized
signal is input to the delta sigma modulator 41. In the second embodiment, it is assumed that the
MFB compatible digital signal processing unit 34 outputs a feedback signal after phase inversion.
Therefore, in this case, the combiner 45 may perform combining processing in which the input
signals are simply added.
08-05-2019
21
[0065]
The delta sigma modulator 41 in this case does not convert the input signal into one bit, but
converts it into a [16 Fs, 5 bit] signal in which the number of quantization bits is five. Then, this
[16 Fs, 5 bit] signal is input to the PWM modulator 43 to perform PWM modulation, and then
passes through the analog LPF 43 to obtain an analog audio signal which is the output of the
DAC 40. That is, as a part of D / A conversion of the second embodiment, a configuration
according to a class D amplifier is employed.
[0066]
The following can be considered as a modification of the second embodiment. For example, as
shown in the drawing, the oversampling filters 44 are formed as the upsampling circuits 46a to
46d connected in multiple stages in series. Here, each of the up-sampling circuits 46a to 46d is
assumed to convert the sampling frequency to twice, and by connecting such up-sampling
circuits in four stages, the input signal of [1Fs, 16 bits] is obtained. , [16 (= 2 × 2 × 2 × 2) Fs,
16 bit] format. Then, the MFB compatible digital signal processing unit 34 converts the input
signal with the sampling frequency of 64 Fs into a signal of 16 Fs with 8 Fs, 4 Fs, or 2 Fs lower
than 16 Fs by the decimation filter 34 e and outputs it. Then, this signal is configured to be input
to a predetermined up-sampling circuit in the over-sampling filter 44 according to the sampling
frequency.
[0067]
For example, if the format of the feedback signal from the MFB compatible digital signal
processing unit 34 is [8 Fs, 16 bits], the synthesizer 47 c is inserted in the oversampling filter 44
in the previous stage of the up sampling circuit 46 d. The feedback signal from the
corresponding digital signal processing unit 34 and the output of the up-sampling circuit 46c are
synthesized and output to the up-sampling circuit 47d. According to such a configuration, the
signal of the digital audio source upsampled to [8Fs, 16bit] by the synthesizer 47c and the
feedback signal from the MFB compatible digital signal processing unit 34 in the same [8Fs,
16bit] format And will be synthesized. Then, the synthesized signal passes through the upsampling circuit 46d, and can finally be input to the delta sigma modulator 41 as an audio signal
of [16 Fs, 16 bits] (in this case, the synthesizer 45 is omitted). Good).
08-05-2019
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[0068]
Similarly, if the feedback signal output from the MFB compatible digital signal processing unit 34
is in the form of [4Fs, 16 bit], the combiner 47b is inserted in the oversampling filter 44 in the
previous stage of the upsampling circuit 46c. Then, the output signal of the MFB compatible
digital signal processing unit 34 and the output of the up-sampling circuit 46c are combined and
output to the up-sampling circuit 47c. Alternatively, if the feedback signal output from the MFB
compatible digital signal processing unit 34 is a [2Fs, 16 bit] signal, the combiner 47a is inserted
in the oversampling filter 44 before the upsampling circuit 46b, where The output signal of the
MFB compatible digital signal processing unit 34 and the output of the up sampling circuit 46 b
are synthesized and output to the up sampling circuit 47 b.
[0069]
In these modified examples, for example, since the number of operation steps per one sampling
period increases, the clock frequency of the system is increased when the required amount of
operation within one sampling period in the MFB compatible digital signal processing unit 34
becomes large. There is an advantage that a desired filter characteristic can be realized without
raising it.
[0070]
In the first embodiment, the sampling frequency of the feedback signal output from the MFB
compatible digital signal processing unit 34 should be the same as the sampling frequency of the
signal handled by the delta sigma modulator 41 on the DAC 40 side. As described above, in the
case of the above variation, the sampling frequency of the feedback signal is lower than the
sampling frequency of the signal handled by the delta sigma modulator 41.
However, if it is considered that the upsampling circuit in the oversampling filter 44 through
which the feedback signal passes is included as a component of the digital filter, the sampling
frequency of the feedback signal is again the delta sigma modulator 41 of the DAC 40. Is the
same as the sampling frequency of the signal handled by Further, in the configuration of this
modified example, the feedback signal passes through a part of the oversampling filter 44 in the
DAC 40, and for example, the delay by that amount is shorter than when passing through the
oversampling filter 44 at all. It occurs. However, as compared with the case where the
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23
oversampling filter 12a is completely passed as shown in FIG. 3, the effect of reducing the delay
amount also in the DAC 40 is obtained.
[0071]
<6. Digital MFB Signal Processing System: Third Embodiment FIG. 7 shows a configuration
example as a third embodiment. In addition, in this figure, about the part made the same as FIG.
4, the same code | symbol is attached | subjected and description is abbreviate | omitted. In the
embodiments so far, the digital audio source is, for example, a digital audio signal of the PCM
format by [1Fs, 16 bit] such as CD. The digital audio signal format according to this [1 Fs, 16 bit]
is regarded as one of the mainstream even at present. However, in addition to this, for example, a
digital audio signal in the format of [64 Fs, 1 bit] recorded on SACD (Super Audio CD) or the like,
DSD (Direct Stream Digital) or the like remains equivalent after delta sigma modulation. It has
come to be treated that the signal of the said format is an entity of audio content. As a third
embodiment, a configuration example in which the digital audio source is a signal of such a DSD
format is shown.
[0072]
The DSP 30 in FIG. 7 is configured to have a bit expander 35, a digital equalizer 31, a synthesizer
33, and an MFB compatible digital signal processing unit 34. This configuration can be viewed as
a signal processing configuration in which a bit expander 35 is newly added in comparison with
FIG. 4 while the oversampling filter 32 is omitted. Also, the DAC 40 and the ADC 20 have the
same configuration as FIG.
[0073]
The digital audio source shown in FIG. 7 is a signal of DSD format according to [64 Fs, 1 bit]. This
signal is input to the bit expander 35 of the DSP 30. The bit expander 35 inputs the signal of [64
Fs, 1 bit] of the digital audio source and executes processing to expand it to 16 bits, converts it
into a signal of [64 Fs, 16 bit], and outputs it to the digital equalizer 31 .
[0074]
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24
Note that the bit expansion processing performed by the bit expander 35 here is, for example, a
1-bit signal of DSD format, that is, a 16-bit 0x0400 (0.5 bit) signal that can only take binary
values of 1 or 0 as a value. Or 0xC000 (-0.5). Therefore, the bit expander 35 may be configured
by a digital filter having the characteristics of the LPF, and furthermore, it is also possible to
adopt the configuration provided with the ROM as shown in FIG. 5B. It is possible.
[0075]
The digital equalizer 31 in this case receives the above-mentioned [64 Fs, 16 bit] digital audio
signal and executes a 16-bit operation, and this operation process is executed according to the
clock timing corresponding to 64 Fs. . Then, the digital audio signal after equalization processing
is output in the same [64 Fs, 16 bit] format as in the input stage. Then, this signal is output to the
synthesizer 33.
[0076]
As a comparison, in FIG. 4, the digital equalizer 31 inputs a signal of [1 Fs, 16 bit] corresponding
to the signal of the digital audio source being in the form of [1 Fs, 16 bit], and the same [1 Fs, 16
bit] It was formed to output the signal of]. Then, the output from the digital equalizer 31 is
converted to [64 Fs, 16 bit] by the oversampling filter 32 and then output to the synthesizer 33.
That is, as in the example of FIG. 7, when the digital audio signal is in the [64 Fs, 1 bit] format,
the sampling frequency itself may already be 64 Fs at the input stage to the DSP 30, so The
sampling filter 32 can be omitted. Instead of this, the number of quantization bits of the audio
signal is equalized to 16 bits as the feedback signal by bit extension, and the format of the input /
output signal of the digital equalizer 31 is [64Fs, 16 bit] It is made to correspond to].
[0077]
Then, the synthesizer 33 synthesizes the phase-inverted feedback signal in the same [64 Fs, 16
bit] format with respect to the [64 Fs, 16 bit] format digital audio signal output from the digital
equalizer 31 as described above. And output to the DAC 40.
[0078]
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Note that, for example, an active speaker can be considered as an actual apparatus having the
configuration of the MFB signal processing system as the present embodiment described above.
The active speaker receives an audio signal, receives a power supply, performs signal processing,
performs signal processing and amplification, and an amplifier circuit and a speaker are
integrated. Further, the present invention can also be applied to an audio reproducing apparatus
in which a player for reproducing a digital audio source and a speaker are integrated. Further,
the configuration as the present embodiment can be applied to, for example, an audio component
system as well as the single device provided with the speaker and the audio signal processing
circuit as described above. For example, in the case of an audio component system including a
speaker unit and an amplifier, first, a sensor such as a bridge circuit 15 is provided on the
speaker unit side. Further, on the amplifier side, a terminal for inputting a signal from the sensor
is provided, and the signal from this terminal is inputted to the detection / amplification circuit
16. Furthermore, for example, the ADC 20, the DSP 30, the DAC 40, and the like described in the
above embodiments are provided.
[0079]
<7. Application Example to Headphones> Also, in the headphone, a portion generally referred
to as a driver and having a configuration equivalent to that of a speaker is provided with a
portion for converting an audio signal to sound. From this point of view, it is conceivable to apply
the configuration of the MFB signal processing system of this embodiment to headphones. FIG. 8
shows the case where the configuration of the MFB signal processing system of this embodiment
is applied to overhead type headphones. In this figure, the earpiece (channel) corresponding ear
pad on one side is shown as the overhead type headphone 100. In the overhead type headphone
100, the driver 101 corresponding to the speaker unit 14 in the above embodiments is provided.
Further, in this figure, as the MFB signal processing system for driving the driver by the MFB
control, the same configuration as that of the first embodiment shown in FIG. 4 is shown. Note
that, instead of the configuration of the first embodiment, for example, the second and third
configurations shown in FIG. 6 and FIG. 7 may be applied. By applying the configuration of the
MFB signal processing system of the present embodiment to the headphones in this manner, the
advantages of the MFB signal processing system using digital circuits can be enjoyed in a
listening environment using headphones.
[0080]
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When the MFB signal processing system of the present embodiment is actually configured for
headphones, for example, it is conceivable to first provide all of the MFB signal processing
systems shown in FIG. 8 on the headphone side. The example of FIG. 8 assumes such a
configuration. That is, in FIG. 8, the analog audio signal reproduced by the audio player 19 is
converted into a digital signal by the ADC 18 and then input to the DSP 30. The ADC 18 may be
provided, for example, on the headphone side. In this configuration, for example, the plug of the
headphone 100 is connected to the analog audio signal output terminal of the audio player 19.
As a result, the analog audio signal from the audio player 19 is input to the ADC on the
headphone 100 side.
[0081]
Alternatively, as another configuration in the case of applying to headphones, it may be
considered to separately provide the headphones and the audio player. For example, a sensor as
the bridge circuit 15 or the like is provided on the headphone side, and the remaining detection /
amplification circuit 16, ADC 20, DSP 30, DAC 40, and power amplifier 13 are provided on the
audio player side to which the headphones are connected. .
[0082]
In addition, as the headphones, as shown as the inner-ear type headphone 101 in FIG. 9, a unit
part of the driver 101 is known to be hooked to the pinna or inserted into the ear hole (also
referred to as canal type). There is. The MFB signal processing system of the present embodiment
can be applied to such an inner-ear type headphone 101 as in FIG.
[0083]
13 power amplifier, 14 speaker unit, 15 bridge circuit, 16 detection / amplification circuit, 20
ADC, 21 delta sigma modulator, 30 DSP 31 digital equalizer, 32 oversampling filter, 33
synthesizer, 34 MFB compatible digital signal processing unit, 34a, 34c digital filter, 34b
differential processing unit, 34d combiner, 34e decimation filter, 35 bit expander, 40 DAC, 41
delta sigma modulator, 42 analog LPF, 43 PWM modulator, 44 oversampling filter, 60 ROM
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