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JP2015153978

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DESCRIPTION JP2015153978
Abstract: The present invention provides a method of manufacturing a through wire which can
ensure good electrical characteristics. In a method of forming a through wiring, first insulating
films 2a and 2b are formed on a first surface 1a and a second surface 1b of a substrate 1, and at
least at least a portion of the first insulating film 2b on a second surface. A through hole 3
penetrating the first insulating film 2a on the first surface side and the substrate 1 is formed so
that a part thereof remains. Further, the second insulating film 4 made of a material different
from the first insulating film is formed on the inner wall of the through hole, and the conductive
film 5 is formed on the first insulating film 2 b on the second surface. Further, the first insulating
film 2b of the second surface is processed from the side of the first surface to form an opening
2e in the first insulating film 2b so that the conductive film is exposed at the bottom of the
through hole. Using the conductive film 5 exposed at the bottom of the hole as a seed layer, the
inside of the through hole is embedded with the conductive material 7 by electrolytic plating.
[Selected figure] Figure 1
Method of manufacturing through wiring
[0001]
The present invention relates to a method of manufacturing a through electrode penetrating in
the thickness direction of a substrate such as a semiconductor substrate. The substrate having
such a through electrode can be used to manufacture a capacitive transducer or the like used as
an ultrasonic transducer or the like.
04-05-2019
1
[0002]
As represented by LSI, systems such as integrated circuits are required to be faster and more
sophisticated. In order to further increase the speed and functionality of systems such as these
integrated circuits, a chip mounting technology using a three-dimensional structure is required.
For this reason, conventionally, a substrate through electrode capable of electrically connecting
chips with a shortest distance has been used. A through electrode is formed by forming a
through hole (also referred to as a through hole) penetrating the substrate, embedding a metal in
the through hole, and electrically connecting between the substrates stacked above and below
the substrate through the metal. Connect to Electrolytic plating is generally used as a method for
embedding metal in the through holes. When the aspect ratio of the through hole is high, bottomup electrolytic plating in which a seed layer is formed at one end of the through hole is effective
in order to obtain a highly reliable through electrode. Patent Document 1 discloses a method for
facilitating the formation and removal of a seed layer. In this method, an insulating film and a
conductive member are sequentially formed on one surface of the substrate, and then the
conductive member is used as an etch stop layer to form through holes from the other surface of
the substrate. After forming the through holes, the conductive member is used as a seed layer to
form through electrodes by bottom-up electrolytic plating on the through holes.
[0003]
JP, 2012-28533, A
[0004]
However, in the method of Patent Document 1, since the insulating film may be formed on the
inner wall of the through hole in the state where the seed layer is present, the forming method
and forming conditions of the insulating film may be restricted.
For example, when the temperature of the substrate is raised in the formation of the insulating
film on the inner wall of the through hole, the material of the seed layer may be diffused into the
insulating film in close contact with the seed layer to deteriorate the characteristics of the
insulating film. Furthermore, depending on the formation conditions of the insulating film, the
material of the seed layer may pass through the insulating film and diffuse into the interior of the
substrate. Therefore, the insulating film on the inner wall of the through hole is likely to be
formed at a low temperature. On the other hand, at low temperatures, it is difficult to form a high
quality insulating film such as a silicon thermal oxide film. Further, in the method of Patent
04-05-2019
2
Document 1, in the etching for exposing the seed layer at the bottom of the through hole, the
insulating film on the inner wall made of the same material as the material to be etched may be
damaged and the insulating performance may be deteriorated. There is.
[0005]
In view of the above-mentioned subject, the method of the present invention which forms
penetration wiring in a substrate using electrolysis plating includes the following processes.
Forming a first insulating film on mutually opposing first and second surfaces of the substrate;
Forming a through hole penetrating the first insulating film on the first surface side and the
substrate such that at least a part of the first insulating film on the second surface remains;
Forming a second insulating film made of a material different from that of the first insulating film
on the inner wall of the through hole; Forming a conductive film on the first insulating film on
the second surface; And forming an opening in the first insulating film by processing the first
insulating film of the second surface from the side of the first surface so that the conductive film
is exposed at the bottom of the through hole. A step of embedding the inside of the through hole
with a conductive material by electrolytic plating using the conductive film exposed at the
bottom of the through hole as a seed layer;
[0006]
According to the method of forming the through wiring of the present invention, if the seed layer
is formed after the second insulating film is formed on the inner wall of the through hole, the
restriction of the forming method and forming conditions of the second insulating film is less.
And a higher quality second insulating film can be formed. In addition, since the second
insulating film on the inner wall of the through hole is made of a material different from that of
the first insulating film on the seed layer, it should be hardly damaged in the etching for exposing
the seed layer at the bottom of the through hole. Is possible. As a result, it is possible to suppress
the decrease in the insulation performance of the second insulating film on the inner wall of the
through hole.
[0007]
It is a section drawing for explaining an example of a manufacturing method of penetration
wiring of the present invention. It is a cross section drawing for demonstrating the other example
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3
of the manufacturing method of the penetration wiring of this invention.
[0008]
In the method of forming the through wiring of the present invention, the penetration
penetrating the first insulating film on the first surface side of the substrate and the substrate so
that at least a part of the first insulating film on the second surface of the substrate remains. A
hole is formed, and a second insulating film of a material different from the first insulating film is
formed on the inner wall of the through hole. Then, a conductive film is formed on the first
insulating film on the second surface, and the first insulating film on the second surface is
processed to form an opening so that the conductive film is exposed at the bottom of the through
hole. The inside of the through hole is embedded with a conductive material by electrolytic
plating using the conductive film exposed at the bottom of the through hole as a seed layer.
Typically, the step of forming the second insulating film is performed prior to the step of forming
the conductive film.
[0009]
Hereinafter, embodiments of the present invention will be described with reference to the
drawings. First Embodiment A first embodiment of a method of manufacturing a through wire
according to the present invention will be described with reference to FIG. FIG. 1 is a crosssectional view for explaining the present embodiment. For the sake of clarity, only two through
holes and vias are shown in FIG.
[0010]
First, as shown in FIG. 1A, the substrate 1 is prepared. The substrate 1 is a semiconductor
substrate. For example, the substrate 1 is a silicon substrate. The substrate 1 has a first surface
1a and a second surface 1b facing each other. The thickness of the substrate 1 is, for example, 50
μm to 1000 μm. Hereinafter, the processing steps will be described by taking the case where
the substrate 1 is a silicon substrate as an example.
[0011]
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4
Next, as shown in FIG. 1B, the first insulating film 2 is formed on the first surface 1 a and the
second surface 1 b of the substrate 1. The first insulating film on the first surface 1a is denoted
2a, and the first insulating film on the second surface 1b is denoted 2b. The insulating film 2a
and the insulating film 2b may be formed simultaneously or separately. Further, the insulating
film 2a and the insulating film 2b may have the same or different configuration or film thickness.
The first insulating film 2 (including 2a and 2b). The same applies hereinafter to a single layer
film of silicon nitride or silicon oxide, or a multilayer film of silicon nitride and silicon oxide, for
example. The thickness of the first insulating film 2 is, for example, 0.1 μm to 1.5 μm. There is
a chemical vapor deposition (CVD) method as a method of forming a nitride of silicon. As a
method of forming an oxide of silicon, there is a thermal oxidation or a CVD method.
[0012]
Next, as shown in FIG. 1 (C), the through holes 3 are formed. The processing of the through holes
3 is performed from the first surface 1 a side of the substrate 1. The shape, number, arrangement
and the like of the through holes 3 are defined by a photoresist pattern according to the
application. The through holes 3 have, for example, a diameter of 20 μm to 100 μm, and an
arrangement in which the period in the horizontal direction is 200 μm and the period in the
vertical direction is 2 mm. In the processing of the through holes 3, for example, the first
insulating film 2a and the substrate 1 are processed in order using a photoresist pattern (not
shown) as an etching mask. The processing of the through holes 3 penetrating the substrate 1
uses, for example, a reactive ion etching method (RIE). The opening of the first insulating film 2a
is 2c. The side wall of the through hole 3 is 3a, and the opening is 3b. By the formation of the
through hole 3, the 2d portion of the first insulating film 2b is exposed at the bottom of the
through hole. In the processing of the through hole 3, there is no problem even if the 2d portion
of the first insulating film 2b is slightly etched. However, in the processing of the through hole 3
and the subsequent steps, the material and thickness of the first insulating film 2b are set to the
step of FIG. Decide by. After the processing of the through holes 3, the etching mask is removed
by an appropriate method. The inner wall 3a of the through hole 3 is preferably smooth. For
example, the surface roughness of the inner wall 3a of the through hole 3 is preferably 50 nm or
less at the maximum height Rmax. If the inner wall 3a of the through hole 3 is not sufficiently
smooth after the RIE processing, it is preferable to perform a smoothing process on the inner
wall 3a. For example, a silicon oxide film is formed on the surface of the inner wall 3a by thermal
oxidation, and then the silicon oxide film is removed with a chemical such as hydrofluoric acid or
buffered hydrofluoric acid (BHF) to smooth the inner wall 3a. It can be Further, heat treatment in
a hydrogen atmosphere is also effective for smoothing the inner wall 3a.
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[0013]
Next, as shown in FIG. 1D, the second insulating film 4 is formed on the side wall 3a of the
through hole 3 (see FIG. 1C). The second insulating film 4 is different in material from the first
insulating film 2 (in particular, the first insulating film 2 b). For example, the first insulating film
2b is a nitride film of silicon, and the second insulating film 4 is an oxide film of silicon. Thus, the
second insulating film 4 can be formed, for example, by thermal oxidation of silicon. In the case
of forming by thermal oxidation of silicon, the second insulating film 4 is formed only on the side
wall 3a of the through hole 3 exposed in the process up to FIG. 1 (C). The thickness of the second
insulating film 4 is determined by the required performance. For example, the thickness of the
second insulating film 4 is 0.5 μm to 1.5 μm. In order to prevent thermal diffusion of the
through wiring material to the substrate 1, the second insulating film 4 may be a multilayer film
composed of two or more types of materials. If the inner wall 3a of the through hole 3 is
smoothed in the step of FIG. 1C, the second insulating film 4 formed on the side wall 3a is
difficult to have a defect and is resistant to stress due to a thermal process or the like.
[0014]
Next, as shown in FIG. 1E, the conductive film 5 is formed on the upper surface of the first
insulating film 2b. The conductive film 5 is, for example, a metal. The conductive film 5 may
include an adhesion layer in order to ensure adhesion with the first insulating film 2b. For
example, the conductive film 5 is a two-layer film in which 5 nm of Cr and 1 μm of Cu are
sequentially formed on the upper surface of the first insulating film 2b. Examples of the method
of forming the conductive film 5 include sputtering, electron beam evaporation, resistance
heating evaporation, and the like.
[0015]
Next, as shown in FIG. 1F, as seen from the opening 3b of the through hole (see FIG. 1C), the 2d
portion of the first insulating film 2b so that the 5a portion of the conductive film 5 is exposed.
An opening 2e is formed by processing (see FIG. 1E). In the processing of the 2d portion of the
first insulating film 2b, the second insulating film 4 is prevented from being greatly damaged.
Further, the opening 2 e of the first insulating film 2 b is made smaller than the inner diameter of
the second insulating film 4 so that the silicon substrate 1 is not exposed in the through holes 3.
Therefore, processing of the opening 2e is performed from the first surface 1a side of the
substrate 1 (see FIG. 1A), for example, using dry etching using the dry film resist 6 as a mask.
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6
The opening 6a of the dry film resist 6 is smaller than any of the opening 2c (see FIG. 1C) of the
first insulating film 2a and the opening 3b of the through hole 3 (see FIG. 1C). After processing
the 2d portion of the first insulating film 2b, the etching mask (for example, the dry film resist 6)
is removed by an appropriate method.
[0016]
Next, as shown in FIG. 1G, the inside of the through hole 3 is embedded with the conductive
material 7 by electrolytic plating using the conductive film 5 as a seed layer. In order to ensure
the reliability of the electrical connection with the electrodes and the like of the device
manufactured later, the conductive material 7 is made to project from the opening 2c (see FIG.
1C) of the first insulating film 2a. At the time of electrolytic plating, the plating solution circulates
in the through holes from the openings 3 b of the through holes 3, and the conductive material 7
grows from the portion 5 a of the conductive film 5 as a starting point. The conductive material 7
contains, for example, Cu as a main component. In this case, the plating of the conductive
material 7 is, for example, electrolytic plating of Cu containing copper sulfate as a main solution.
At the time of plating, the surface of the conductive film 5 is prevented from coming into contact
with the plating solution so that plating growth does not occur on the surface of the conductive
film 5 outside the through hole 3. For example, the surface of the conductive film 5 outside the
through hole 3 is protected by an insulating material. Thus, plating growth can be performed
starting from only the portion 5a of the conductive film 5, and the plating efficiency is good.
[0017]
Next, as shown in FIG. 1H, the first surface 1a side of the substrate 1 so that both end surfaces 7a
and 7b of the conductive material 7 are exposed for electrical connection with electrodes and the
like of a device to be manufactured later. Machining is performed from the side (see FIG. 1 (A))
and the second surface 1 b (see FIG. 1 (A)). The processing of the end face 7a is performed from
the side of the first face 1a, and for example, CMP (Chemical Mechanical Polishing) is used. By
the CMP, the end face 7a has almost the same height as the surface of the first insulating film 2a.
The processing of the end face 7b aims at removal of the conductive film 5 and flattening of the
end face 7b. CMP may be used to process the end face 7b. The conductive material 7 subjected
to the end face processing in this manner becomes a through wiring. Then, when it is necessary
to smooth the surface of the first insulating film 2, after the end face processing of the
conductive material 7, the first insulating films 2a and 2b are processed by using CMP.
04-05-2019
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[0018]
By using the above steps, a semiconductor substrate having the through wiring 7 shown in FIG.
1H can be manufactured. In this manufacturing method, the second insulating film on the inner
wall of the through hole is formed before the plating seed layer. Therefore, the restriction on the
formation conditions of the second insulating film is reduced, and the processing means which
becomes high temperature can be used. As an example thereof, a thermal oxide film of silicon
having excellent insulating properties can be easily formed as the second insulating film. Further,
the second insulating film is hardly damaged in the step of exposing the seed layer at the bottom
of the through hole by making the first insulating film on the seed layer a silicon nitride film
capable of obtaining an etching selectivity with the silicon oxide film. You can As a result, a
highly reliable second insulating film can be easily obtained.
[0019]
Second Embodiment A second embodiment of a method of manufacturing a through wire
according to the present invention will be described with reference to FIG. FIG. 2 is a crosssectional view for explaining the present embodiment. In order to avoid duplication, detailed
description of parts similar to the first embodiment will be omitted. First, a substrate 1 similar to
that shown in FIG. 1A is prepared. Hereinafter, the manufacturing method will be described by
taking the case where the substrate 1 is a silicon substrate as an example.
[0020]
Next, as shown in FIG. 2A, insulating films 8 (8a and 8b) are formed on the first surface 1a (see
FIG. 1A) and the second surface 1b (see FIG. 1A) of the substrate 1. including. The same applies
hereinafter and the insulating film 2 (2a and 2b). The same applies hereinafter. The insulating
films 8 and 2 on the first surface 1a are denoted 8a and 2a, respectively, and the insulating films
8 and 2 on the second surface 1b are denoted 8b and 2b, respectively. The insulating film 8 and
the insulating film 2 constitute a first insulating film. That is, in the present embodiment, the first
insulating film has a multi-layer structure. The insulating film 8 is made of an insulating material
of a material different from that of the insulating film 2. For example, the insulating film 8 is a
thermal oxide film of silicon and has a thickness of 0.1 μm to 1.5 μm. In contrast, the insulating
film 2 is a silicon nitride film and has a thickness of 0.1 μm to 0.5 μm. In order to prevent
warpage of the substrate 1 due to stress, it is desirable that the insulating film 8a and the
insulating film 8b have the same thickness as the material and be formed simultaneously.
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Further, it is desirable that the insulating film 2a and the insulating film 2b have the same
thickness as the material and be formed simultaneously.
[0021]
Next, as shown in FIG. 2B, the through holes 3 are formed. The processing of the through holes 3
is performed from the side of the first surface 1 a of the substrate 1 (see FIG. 1A). In processing
the through holes 3, for example, using the photoresist pattern (not shown) as an etching mask,
the insulating film 8a, the insulating film 2a, and the substrate 1 are processed in order. The
processing of the through holes 3 penetrating the substrate 1 uses, for example, a reactive ion
etching method (RIE). The opening of the insulating film 2a is 2c, and the opening of the
insulating film 8a is 8c. The side wall of the through hole 3 is 3a, and the opening of the through
hole 3 is 3b. In the opening 2c, the dimensions of the opening 8c of the insulating film 8a and
the opening 3b of the through hole 3 may be the same. By the formation of the through hole 3,
the 8d portion of the insulating film 8b is exposed at the bottom of the through hole.
[0022]
Next, as shown in FIG. 2C, the portion 8d of the insulating film 8b is processed so that the
portion 2d of the insulating film 2b is exposed. The processing of the portion 8d of the insulating
film 8b may use the same etching mask as the processing of the through hole 3 of FIG. 2 (B).
[0023]
Next, as shown in FIG. 2D, the second insulating film 4 is formed on the side wall 3a of the
through hole 3 (see FIG. 2C). The second insulating film 4 is different in material from the
insulating film 2 (in particular, the insulating film 2 b) of the first insulating film, but may be the
same material as the insulating film 8 of the first insulating film. For example, the insulating film
2b is a nitride film of silicon, and the second insulating film 4 is an oxide film of silicon. Thus, the
second insulating film 4 can be formed, for example, by thermal oxidation of silicon. In this case,
the second insulating film 4 is formed only on the side wall 3a of the through hole 3 exposed in
the process of FIG. 2C. The thickness of the second insulating film 4 is determined by the
required performance. For example, the thickness of the second insulating film 4 is 1 μm.
04-05-2019
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[0024]
Next, as shown in FIG. 2E, the conductive film 5 is formed on the upper surface of the insulating
film 2b. The conductive film 5 is, for example, a metal. The configuration and formation method
of the conductive film 5 are the same as those described in FIG.
[0025]
Next, as shown in FIG. 2F, the portion 2d of the insulating film 2b is processed so that the portion
5a of the conductive film 5 is exposed as viewed from the opening 3b of the through hole (see
FIG. 2C). Do. The processing method is the same as the method described in FIG. The diameter of
the portion 5 a of the conductive film 5 is smaller than the diameter of the through hole 3
including the second insulating film 4.
[0026]
Next, as shown in FIG. 2G, the inside of the through hole 3 is embedded with the conductive
material 7 by electrolytic plating using the conductive film 5 as a seed layer. The plating method
is the same as the method described in FIG. 1 (G). Next, as shown in FIG. 2H, both end surfaces
7a and 7b of the conductive material 7 are processed for electrical connection. The processing
method is the same as the method described in FIG. The conductive material 7 subjected to the
end face processing in this manner becomes a through wiring.
[0027]
By using the above steps, a semiconductor substrate having a through wiring shown in FIG. 2H
can be manufactured. This manufacturing method can obtain the same effect as the
manufacturing method described in the first embodiment. Furthermore, since a thick first
insulating film can be relatively easily formed on the surfaces (1a and 1b) of the substrate, a
through wiring substrate with higher insulation resistance can be realized.
[0028]
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10
Hereinafter, more specific examples will be described. (Example 1) Example 1 which is one
specific example of a method of manufacturing a through wiring of the present invention will be
described with reference to FIG. First, as shown in FIG. 1A, a silicon substrate 1 is prepared. The
substrate 1 has a diameter of 4 ′ ′ and a thickness of 200 μm, and a resistivity of 1 Ω · cm to
100 Ω · cm. The mutually opposing first surface 1a and second surface 1b of the substrate 1
have the same level of mirror surface as that of a generally commercially available silicon
substrate.
[0029]
Next, as shown in FIG. 1B, the first insulating film 2 is formed on the first surface and the second
surface of the substrate 1. The insulating film 2a on the first surface 1a and the insulating film
2b on the second surface 1b are both nitrides of silicon and have a thickness of about 0.4 μm,
and are simultaneously formed by the CVD method. Next, as shown in FIG. 1 (C), the through
holes 3 are formed. The processing of the through holes 3 is performed from the side of the first
surface 1 a of the silicon substrate 1. The through holes 3 have a diameter of 50 μm, a
horizontal period of 200 μm, and a vertical period of 2 mm. In the processing of the through
hole 3, the first insulating film 2a made of silicon nitride and the silicon substrate 1 are
sequentially RIE processed using the photoresist pattern (not shown) as an etching mask. By the
formation of the through hole 3, the 2d portion of the first insulating film 2b is exposed at the
bottom of the through hole. The reactive gas and processing conditions used for RIE of the first
insulating film 2 a made of silicon nitride and the silicon substrate 1 are different. The RIE
conditions are set such that the formation of the through holes 3 hardly damages the 2d portion
of the silicon nitride. After processing the through holes 3, the photoresist pattern used as the
etching mask is removed by plasma ashing.
[0030]
Next, as shown in FIG. 1D, the second insulating film 4 is formed on the side wall 3a of the
through hole 3 (see FIG. 1C). The second insulating film 4 is different from the first insulating
film 2 made of silicon nitride, and is a silicon oxide film. The second insulating film 4 is formed
by thermal oxidation of silicon and has a thickness of 1 μm. Since the first surface 1 a and the
second surface 1 b of the substrate 1 are covered with the first insulating film 2 made of nitride
of silicon, the second insulating film 4 made of oxide of silicon corresponds to that of the through
hole 3. It is formed only on the side wall 3a. Before thermal oxidation of silicon is performed, the
side walls 3a (see FIG. 1C) of the through holes 3 are cleaned by dry etching, chemical solution
04-05-2019
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etching, or the like.
[0031]
Next, as shown in FIG. 1E, the conductive film 5 is formed on the upper surface of the first
insulating film 2b. As the conductive film 5, 5 nm of Cr and 1 μm of Cu are sequentially
deposited on the upper surface of the first insulating film 2b by electron beam evaporation. Next,
as shown in FIG. 1F, the 2d portion (see FIG. 1E) of the first insulating film 2b is processed so
that the 5a portion of the conductive film 5 is exposed. Therefore, using the dry film resist 6 as a
mask, from the first surface 1a side (see FIG. 1A) of the substrate, the 2d portion (see FIG. 1E) of
the first insulating film 2b made of silicon nitride is RIE processing. In the case of RIE of silicon
nitride, conditions are used which hardly damage silicon oxide. Further, the opening 6a of the dry
film resist 6 is made smaller than any of the opening 2c of the first insulating film 2a (see FIG.
1C) and the opening 3b of the through hole 3 (see FIG. 1C). As a result, in the processing of the
portion 2 d of the insulating film 2 b, the second insulating film 4 is hardly damaged, and the
silicon substrate 1 is not exposed in the through holes 3.
[0032]
Next, as shown in FIG. 1G, the inside of the through hole 3 is embedded with the conductive
material 7 by electrolytic plating using the conductive film 5 as a seed layer. In order to ensure
the reliability of the electrical connection, the conductive material 7 is protruded from the
opening 2c (see FIG. 1C) of the first insulating film 2a. At the time of electrolytic plating, the
plating solution circulates in the through holes from the openings 3 b of the through holes 3, and
the conductive material 7 grows from the portion 5 a of the conductive film 5 as a starting point.
Plating of the conductive material 7 is electrolytic plating of Cu containing copper sulfate as a
main solution. At the time of plating, the surface of the conductive film 5 located outside the
through hole 3 is protected by an insulating material in order to cause the plating growth to start
from only the portion 5a of the conductive film 5 as a starting point.
[0033]
Next, as shown in FIG. 1H, for electrical connection, both end surfaces 7a and 7b of the
conductive material 7 are planarized to have substantially the same height as the surfaces of the
first insulating films 2a and 2b. In order to planarize, CMP processing is performed from the first
04-05-2019
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surface 1a side (see FIG. 1A) and the second surface 1b side (see FIG. 1A) of the substrate 1,
respectively. The conductive material 7 subjected to the end face processing in this manner
becomes a through wiring.
[0034]
By using the above-described steps, the same effects as those of the first embodiment can be
obtained.
[0035]
(Example 2) Example 2 which is another specific example of the manufacturing method of the
penetration wiring of the present invention is explained using FIG.
The parts similar to the first embodiment will not be described in detail. First, as in the first
embodiment, the silicon substrate 1 shown in FIG. 1A is prepared.
[0036]
Next, as shown in FIG. 2A, the insulating film 8 and the insulating film 2 are formed on the first
surface 1a (see FIG. 1A) and the second surface 1b (see FIG. 1A) of the substrate 1. Are formed
sequentially. The insulating films 8 and 2 on the first surface 1a are denoted 8a and 2a,
respectively, and the insulating films 8 and 2 on the second surface 1b are denoted 8b and 2b,
respectively. Insulating films 8 (including 8a and 8b). The same applies hereinafter) to a thermal
oxide film of silicon formed by thermally oxidizing the surface of a silicon substrate, and the
thickness is 1.0 μm. Insulating films 2 (including 2a and 2b. The same applies to the following)
is a silicon nitride film formed by the CVD method and has a thickness of 0.4 μm. The insulating
film 8 and the insulating film 2 constitute a first insulating film.
[0037]
Next, as shown in FIG. 2B, the through holes 3 are formed. The processing of the through holes 3
is performed from the side of the first surface 1 a of the substrate 1 (see FIG. 1A). In the
processing of the through holes 3, first, a Cr film (not shown) of 200 nm is formed on the upper
04-05-2019
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surface of the insulating film 2a by sputtering. Then, after photolithography, a photoresist
pattern (not shown) is transferred to a Cr film (not shown) by plasma etching containing chlorine
to expose the surface corresponding to the opening 2c of the insulating film 2a. Further, using a
Cr film (not shown) provided with an opening as an etching mask, RIE processing is performed
until the portion 8d of the insulating film 8b is exposed at the bottom of the through hole.
However, the processing conditions and the etching gas are different in the RIE processing of the
opening 2c of the insulating film 2a, the opening 8c of the insulating film 8a, and the through
hole 3, respectively.
[0038]
Next, as shown in FIG. 2C, the portion 8d of the insulating film 8b is processed so that the
portion 2d of the insulating film 2b is exposed. The processing of the portion 8d of the insulating
film 8b is performed by the same method as the processing of the opening 8c of the insulating
film 8a in FIG. 2B, and the same etching mask is used. After processing the portion 8d of the
insulating film 8b, the etching mask formed on the upper surface of the insulating film 2a is
removed.
[0039]
Next, as shown in FIG. 2D, the second insulating film 4 is formed on the side wall 3a of the
through hole 3 (see FIG. 2C). The second insulating film 4 is an oxide film of silicon while the
material of the first insulating film 2 is a nitride film of silicon. The second insulating film 4 is a
silicon oxide film formed by thermally oxidizing the inner wall 3a (see FIG. 2C) of the through
hole 3 which is silicon, and has a thickness of 1.0 μm. Since the outermost surface of the
substrate 1 is the first insulating film 2 made of a silicon nitride film during thermal oxidation,
the second insulating film 4 is formed only on the inner wall 3 a (see FIG. 2C) of the through hole
3. Ru.
[0040]
Next, as shown in FIG. 2E, the conductive film 5 is formed on the upper surface of the first
insulating film 2b. The configuration and formation method of the conductive film 5 are the same
as those described in FIG. 1 (E) of the first embodiment. Next, as shown in FIG. 2F, as seen from
the opening 3b of the through hole (see FIG. 2C), the 2d portion of the first insulating film 2b so
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that the 5a portion of the conductive film 5 is exposed. Process the The processing method is the
same as the method described in FIG. 1 (F) of the first embodiment. The area of the portion 5 a of
the conductive film 5 is smaller than the diameter of the through hole 3 including the second
insulating film 4.
[0041]
Next, as shown in FIG. 2G, the inside of the through hole 3 is embedded with the conductive
material 7 by electrolytic plating using the conductive film 5 as a seed layer. In order to ensure
the reliability of the electrical connection, the conductive material 7 is made to project from the
opening 2c (see FIG. 2D) of the insulating film 2a. The plating method is the same as the method
described in FIG. 1 (G) of the first embodiment.
[0042]
Next, as shown in FIG. 2H, for electrical connection, both end surfaces 7a and 7b of the
conductive material 7 are planarized to have substantially the same height as the surfaces of the
first insulating films 2a and 2b. In order to planarize, CMP processing is performed from the first
surface 1a side (see FIG. 1A) and the second surface 1b side (see FIG. 1A) of the substrate 1,
respectively. The conductive material 7 subjected to the end face processing in this manner
becomes a through wiring.
[0043]
By using the above-described steps, the same effects as those of the second embodiment can be
obtained.
[0044]
The through wiring substrate having the through wiring obtained by the above-described
manufacturing method can be applied to various devices and systems including an LSI chip and a
micromachine element.
By using such a through wiring board, it is possible to miniaturize devices and systems, to
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increase the density, and to enhance the functions. For example, among the above-described
methods for manufacturing through-wires, a capacitive transducer (CMUT: CapacitiveMicromachined-Ultrasonic-Transducer) can be manufactured on a substrate by micromachining
technology. According to such a CMUT, the vibration of the vibrating film can be used to transmit
and receive an acoustic wave (including sound waves, ultrasonic waves, and so-called
photoacoustic waves) to the subject, particularly in liquid. Excellent broadband characteristics
can be easily obtained. In such a CMUT, a plurality of vibrating membranes arranged in a twodimensional array form one element (element) for practical use, and further, a plurality of
elements are arranged on a substrate to constitute a transducer to achieve a desired
performance. ing. In this structure, in order to control each element independently, it is
necessary to form a wiring electrode corresponding to each element. Here, in order to
miniaturize and reduce the parasitic capacitance of the wiring electrode, it is desirable to use a
through wiring penetrating the substrate, and the above configuration realizes this.
[0045]
1 · · · Substrate, 1a · · · First surface of the substrate, 1b · · · Second surface of the substrate 2, 8 · ·
First insulating film, 3 · · Through holes, 4 · · Second insulating film, 5 · · Conductive film, 7 · ·
Conductive material (through wiring)
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