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JPH06209500

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DESCRIPTION JPH06209500
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a
digital audio signal processing apparatus for use in, for example, movie theaters, theaters, home
theaters, etc., and driving speakers corresponding to sound image localization positions
estimated based on stereo audio signals.
[0002]
2. Description of the Related Art In general, in a stereo reproduction system of audio signals by
two speakers, it is only at a position where it is a vertex of an isosceles triangle with the left and
right speakers at the bottom, that is, a position where it is equidistant from the left and right
speakers. It is believed that normal sound image localization can not be obtained. And it is said
that it is better to listen in the vicinity of the vertex of the equilateral triangle which makes two
speakers a base in particular. That is, in the stereo reproduction method of the audio signal by
two speakers, the listening position which can obtain a normal sound image localization will be
limited to the limited range.
[0003]
For example, as disclosed in the Proceedings of the Acoustical Society of Japan, pp. 357-358,
"Method for Improving the Asymmetric Sound Field in the Car Room 1-5-14" (March, 1988), the
front left and right speakers for the listener When the mounting position is asymmetrical, the
distribution of sound between the left and right speakers is biased toward the speaker close to
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the listener, and there is a problem that the original stereo reproduction effect can not be
obtained. A method has been proposed for creating an apparent sound source so as to adjust the
distance to the position.
[0004]
The present invention also solves the problem that the sound distribution between the left and
right speakers is biased in the direction of the speaker closer to the listener in the specification
and drawings of Japanese Patent Application No. 4-97830, and the stereo reproduction effect
can not be obtained. An audio signal reproducing apparatus having means for dividing an input
audio signal into a plurality of frequency bands and driving a speaker disposed at a position
corresponding to a sound image localization position of the audio signals of the divided
frequency band first Proposed.
[0005]
By the way, in the audio signal reproducing apparatus of Japanese Patent Application No. 497830, the speaker selection unit for selecting the speaker corresponding to the sound image
localization position is interrupted every time the changeover switch is operated. There is a
problem that noise occurs.
[0006]
An object of the present invention is to reduce the sound disconnection and noise in such prior
art.
[0007]
According to a first aspect of the present invention, there is provided an audio signal processing
apparatus to which a stereo audio signal is input, the A / D conversion converting the input left
and right audio signals into digital signals. Section, a frequency band division section for dividing
each digital signal from the A / D conversion section into a plurality of frequency bands, and
voice signal synthesis for synthesizing digital voice signals on the left and right of the divided
frequency bands by a predetermined operation A sound image localization position estimation
unit for estimating a sound image localization position by a predetermined calculation from left
and right digital audio signals of the divided frequency band, and predetermined data from the
sound signal synthesis unit and the sound image localization position estimation unit A data
conversion unit for converting into a format, and a position corresponding to a sound image
localization position of the audio signal of the frequency band divided based on the output signal
from the data conversion unit And a speaker driver for driving the have speakers.
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[0008]
A second invention of the present invention is an audio signal processing apparatus to which a
stereo audio signal is input, comprising: an A / D converter for converting the input left and right
audio signals into digital signals; and the A / D conversion. Each digital signal from the division
unit is divided into a plurality of frequency bands, and the digital audio signals on the left and
right of the divided frequency band are synthesized by a predetermined calculation, and the
predetermined calculation is performed from the digital voice signals on the left and right of the
divided frequency band A digital signal processing unit for estimating a sound image localization
position by a speaker, and a speaker disposed at a position corresponding to the sound image
localization position of the audio signal of the divided frequency band based on an output signal
from the digital signal processing unit The speaker driving unit includes a D / A converting unit
for D / A converting the synthesized audio signal, and the D / A converting unit includes: First
storage means for storing the input digital audio signal, addition means for sequentially adding
the digital signal stored in the first storage means to the output signal from the second storage
means, and addition operation of the addition means And second storage means for outputting
the stored digital signal after the addition operation to D / A conversion means for storing a later
output signal and restoring a digital signal to an analog signal.
[0009]
[Operation] A voice is divided into frequency bands, a speaker arranged at a position
corresponding to a sound image localization position of each frequency band is driven, and a
normal sound image localization position is brought to the speaker by which position it is The
sound image localization position is also constant for the listener.
[0010]
In addition, since the speaker selection switch is unnecessary, it is possible to suppress sound
disconnection and noise.
[0011]
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a digital audio processor
according to an embodiment of the present invention; FIG.
[0012]
[First Embodiment] FIG. 1 is a circuit block diagram for explaining the outline of a digital audio
signal processing apparatus according to a first embodiment, and 1L and 1R respectively receive
left and right analog signals, ie Lch audio signal and Rch audio signal. Low-pass filters 2L and 2R
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are A / D conversion units that respectively input the analog signals from the low-pass filters 1L
and 1R and convert them into digital signals LD [n-1, 0], RD [n-1, 0]; 3 is calculated using the
outputs LD [n-1, 0], RD [n-1, 0] of the A / D conversion units 2L, 2R, and a speaker driving signal
D [2n-1, 0] is output A digital signal processing unit 4 is a speaker drive unit, and 5 is a speaker
array in which speakers corresponding to frequency bands separated by the outputs DA1 to DAp
of the speaker drive unit 4 are driven.
[0013]
In the following description, thin signal lines represent analog signals, and thick signal lines
represent digital signals.
[0014]
Next, FIG. 2 is a circuit block diagram showing the contents of the digital signal processing unit
3. 6L, 6R are digital signals LD [n-1, 0], RD [n from the A / D conversion units 2L, 2R. -1, 0] are
input and divided into frequency bands, 7 is a signal LDi [n-1, 0], RDi [n for each frequency band
output from the frequency band division units 6L, 6R. -1,0] (1 部 i m m) is input and a data
operation processing unit that performs a predetermined operation, 8 is the output DDi [2 n -1,
0] (1 i i m m) of this data operation processing unit 7 Are added by a predetermined method to
obtain an output D [2 n -1, 0].
[0015]
Further, FIG. 3 is a block diagram showing the contents of the frequency band division units 6L
and 6R, FIG. 4 is the contents of the data processing unit 7, and FIG. 5 is a block diagram
showing the contents of the speaker drive unit 4.
[0016]
In FIG. 3, each of the frequency band dividing sections 6L and 6R comprises band pass filters 9L
(R) i (1.ltoreq.i.ltoreq.m) which correspond to the number of frequency bands to be divided.
[0017]
In FIG. 4, the data processing unit 7 performs the addition using the outputs LDi [n-1, 0] and RDi
[n-1, 0] from the frequency band division units 6L and 6R. , Sound image localization position
estimation unit 11i for performing subtraction, outputs ADi [n-1,0] of these audio signal
synthesis unit 10i and sound image localization position estimation unit 11i, SDi [n-1,0] (1 ≦ i ≦
m) converting data to represent sound image localization position information and audio signal
information and outputting data DDi [2 n -1, 0] (1 i i m m) expressing sound image localization
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position information and audio signal information It comprises a data conversion unit 12i.
[0018]
In FIG. 5, the speaker driving unit 4 is the top n of D [2 n -1, 0] obtained as a result of adding
each output D Di [2 n -1, 0] of the data processing unit 7 by the data adding unit 8 The decoder
13 decodes the bit output and outputs a select signal CSk (1 ≦ k ≦ p), and the lower n bits of
digital data D [n−1 selected from the data adder 8 by the select signal CSk , 0] are input, a low
pass filter 15k (1 ≦ k ≦ p) which passes the output of the D / A converter 14k, and an amplifier
16k (1 ≦ k). The drive signal DAk (1 ≦ k ≦ p) is output from the amplifier 16 k to the speaker
array 5.
[0019]
FIG. 6 is a schematic perspective view showing one elementary speaker 17 constituting the
speaker array 5. This elementary speaker is a square planar speaker, and its diaphragm 18 has a
screen function.
Then, as shown in FIG. 7, an array 5 is configured by arranging a predetermined number (p in
this case) of the elementary speakers 17 in a row.
At this time, as shown in FIG. 7, the + terminal k (1 ≦ k ≦ p) of each speaker 17 is connected to
the speaker driver 4 as shown in FIG. It is connected to a wire and connected to the speaker drive
unit 4.
[0020]
Next, the operation of the digital audio signal processing apparatus having such a configuration
will be described.
First, an Lch audio signal and an Rch audio signal are input to the A / D conversion units 2L and
2R through the low pass filters 1L and 1R, respectively.
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The input audio signal is converted into a digital signal, and is output as LD [n-1, 0] and RD [n-1,
0] in the format 19 shown in FIG.
[0021]
Subsequently, LD [n-1, 0] and RD [n-1, 0] are input to the digital signal processing unit 3,
respectively.
The input digital signals are input to the frequency band dividing units 6L and 6R, respectively.
[0022]
In the frequency band division units 6L and 6R, the input signal is divided into a predetermined
number of bands m by the band pass filter 9L (R) i, and the L (R) Di [n-1, 0] is divided by the
audio signal synthesis unit 10i. Performs the operation of LDi [n-1,0] + RDi [n-1,0] and the sound
image localization position estimation unit 11i performs an operation of LDi [n-1,0] -RDi [n-1,0].
The data are output as data ADi [n-1, 0] representing audio signal information and data SDi [n-1,
0] representing sound image localization position information.
[0023]
Such data is converted by the subsequent data conversion unit 12i into the upper n bits of the
format 20 shown in FIG. 9 as SDi [n-1, 0] and the lower n bits into ADi [n-1, 0]. It is output as
data DDi [2 n -1, 0] representing sound image localization position information and sound signal
information.
This data is further input to the data addition unit 8, and the lower n bits are added to data
having the same upper n bits as all input data, ie, data having the same sound image localization
position information. , D [2 n -1, 0].
[0024]
Next, D [2 n -1, 0] is input to the speaker drive unit 4.
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The upper n bits D [2 n -1, n] of D [2 n -1, 0] are input to the decoding unit 13, and the lower n
bits D [n -1, 0] are input to the D / A conversion unit 14 k. Be done.
The decoding unit 13 converts the value of D [2 n -1, n] input based on a conversion table
prepared in advance into k (1 ≦ k ≦ p), and outputs a select signal CSk corresponding to k.
Therefore, it is possible to output the select signal CSk in an arbitrary pattern by changing the
conversion table.
[0025]
The A / D converter 14k is selected by the select signal CSk, D [n-1, 0] is converted into an
analog signal, passes through a low pass filter 15k and an amplifier 16k, and is output as a
speaker drive signal DAk.
The speaker array 5 is driven by the speaker drive signal DAk.
[0026]
As described above, the digital signal L (R) D [n-1,0] converted to a digital signal by the A / D
conversion units 2L and 2R through the low pass filters 1L and 1R is input to the digital signal
processing unit 3 Dividing into a plurality of bands by the frequency band division units 6L and
6R, and performing arithmetic processing on the digital signals LDi [n−1,0], RDi [n−1,0] of the
respective bands in the data arithmetic processing unit 7 Output as data DDi [2 n -1, 0]
representing sound image localization position information and audio signal information, and is
added for each data having the same sound image localization position information in the data
addition unit 8, D [2 n-1 , 0] and is input to the speaker drive unit 4.
[0027]
Then, in the speaker driving unit 4, the decoding unit 13 decodes the sound image localization
position information D [2 n -1, n] based on the conversion table to output the select signal CSk,
and the D / A conversion selected by the select signal CSk The digital signal D [n-1, 0] is input to
the unit 14 k and converted into an analog signal, which is then amplified by the amplifier 16 k
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through the low pass filter 15 k to drive the elementary speaker 17 corresponding to the sound
image localization position. The audio is played from
[0028]
Therefore, since the sound image is always localized on the speaker corresponding to the sound
image localization position, the sound image localization position does not change even if the
listening position of the listener changes.
In addition, since the above configuration is adopted, a speaker selection switch is not necessary,
and it is possible to reduce the sound disconnection and noise which have conventionally been a
problem.
[0029]
Although in the first embodiment the flat square speaker is used, it may be a speaker of another
type and may be arranged so as to surround the listener.
[0030]
Second Embodiment Next, a second embodiment of the digital speech processing apparatus
according to the present invention will be described in detail with reference to the drawings.
However, the same components as those of the first embodiment are given the same reference
numerals, and the detailed description will be omitted.
In the second embodiment, the general-purpose D / A converter 14i used in the first embodiment
is improved, and in the first embodiment, the data addition unit 8 and the data operation
processing unit 7 in the digital signal processing unit 3 are modified. This embodiment is
characterized in that the data conversion unit 12i is not required, and the circuit configuration is
simplified.
[0031]
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First, the improved D / A converter will be described in detail based on the circuit block diagram
of FIG. 10 and the operation timing chart of FIG.
[0032]
In the circuit block diagram of FIG. 1, 21 is INPUT REGISTER, 22 is ADDER, 23 is OUTPUT
REGISTER, 24 is DAC REGISTER, 25 is DAC (Desital Analog Converter), 26 is 1 DELAY, 27 is 2
DELAY, 28 is AND circuit , 29 is a buffer amplifier, and A to D are internal data buses.
[0033]
Next, the operation of each component of FIG. 1 will be described with reference to the timing
chart of FIG.
However, the bar attached to the signal such as RESET in the figure is omitted.
First, when the RESET signal is input, the INPUT REGISTER 21, the OUTPUT REGISTER 23, and
the DAC REGISTER 24 are cleared to 0 at the rising edge 30 of the RESET signal, and the internal
data buses A [n-1, 0], B [n-1, 0]. , D [n−1, 0] are output as φ (NULL).
Where φ represents a signal in which all nbit data are 0.
[0034]
When data is externally input, the chip select signal CS is set to HIGH after the data .alpha.0 of
the external data bus DATA [n-1, 0] is determined.
At the rise 31 of the chip select signal CS, the data .alpha.0 of the external data bus DATA [n-1, 0]
is taken into the INPUT REGISTER 21, and the data .alpha.0 is outputted to the internal data bus
A [n-1, 0].
[0035]
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Thereafter, the chip select signal CS is delayed by the first DELAY 26 to be the operation start
signal OPS.
At this time, the delay time is such that data .alpha.0 of external data bus DATA [n-1,0] is taken
into the above-mentioned INPUT REGISTER 21 and data .alpha.0 is decided on internal data bus
A [n-1,0]. It will be the necessary time.
[0036]
At the rise 32 of the operation start signal OPS, the data α0 of the internal data bus A [n-1, 0]
and the data φ of the internal data bus B [n-1, 0] are fetched into the ADDER 22.
In ADDER2, an operation of .beta. =. Phi. +. Alpha.0 is performed, and at the same time an
operation end signal OPE is output, .beta.0 is output to the internal data bus C [n-1, 0].
Then, at the rise 33 of the operation end signal OPE, the data β0 on the internal data bus C [n-1,
0] is taken into the OUTPUT REGISTER 23, and the data β0 is outputted to the internal data bus
B [n-1, 0].
[0037]
Similarly, the operation when the k-th data α k is input is as follows.
First, the chip select signal CS is set to LOW, and data is input to the external data bus DATA [n-1,
0].
Then, after the data .alpha.k of the external data bus DATA [n-1, 0] is determined, the chip select
signal CS is made HIGH.
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[0038]
At the rise 34 of the chip select signal CS, the data .alpha..sub.k of the external data DATA [n-1, 0]
is taken into the INPUT REGISTER 21 and .alpha..sub.k is outputted to the internal data bus A [n1, 0].
[0039]
Next, the chip select signal CS is delayed by the first DELAY 26 to be the operation start signal
OPS.
At this time, as the delay time, data .alpha..sub.k of the external data bus DATA [n-1, 0] is taken
into the above-mentioned INPUT REGISTER 21, and the data bus A [n-1] is taken over the internal
data bus A [n-1, 0]. , 0] is the time required to determine the data α k.
[0040]
At the rising edge 35 of the operation start signal OPS, the data αk of the internal data bus A [n1, 0] and the data βk-1 of the internal data bus B [n-1, 0] are fetched into the ADDER 22. Then,
the operation of βk = βk−1 + αk is performed in the ADDER 22 and βk is taken into the
internal data bus C [n−1, 0] at the same time the operation end signal OPE is output, and the
internal data bus B [n− Data β k is output at 1, 0].
[0041]
Thus, when the D / A conversion start signal LDAC is input after the series of data α0 to αk are
processed, the data on the internal data bus B [n-1, 0] is generated at the rising edge 37 of the D
/ A conversion start signal LDAC. The .beta.k is taken into the DAC REGISTER 34, and the .beta.k
is output to the internal data bus D [n-1, 0].
[0042]
The DAC 25 converts the received data β k into an analog signal.
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This analog signal is output to the outside as Vout through the buffer amplifier 29. The D / A
conversion start signal LDAC is delayed by the second DELAY 27 to become a D / A conversion
end signal CVE, and the AND circuit 28 takes the logical product of the D / A conversion
circumferential signal CVE and the RESET signal to obtain the OUTPUT REGISTER 23 It becomes
the control signal CLEAR for clearing. The OUTPUT REGISTER 23 is cleared at the rising edge 39
of the control signal, and is output to the internal data bus B [n-1, 0].
[0043]
When such a D / A conversion unit is applied to the digital audio signal processing apparatus of
the first embodiment, the data addition unit 8 becomes unnecessary in the digital signal
processing unit 3 shown in FIG. 2, and the configuration as shown in FIG. And the input / output
state of each data signal.
[0044]
Further, in the data arithmetic processing unit 7 shown in FIG. 4, the data conversion unit 12i
becomes unnecessary, and the configuration as shown in FIG. 13 and the input / output state of
each data signal are obtained.
[0045]
Further, as shown in FIG. 14, the speaker drive unit 4 shown in FIG. 5 has input data separated
into an address bus SDi [n−1, 0] and a data bus ADi [n−1, 0]. .
Therefore, as shown in FIG. 15, the block diagram of the digital audio signal processing
apparatus shown in FIG. 1 is processed by the digital signal processing unit 3 according to the
configuration of the second embodiment in which the value of input / output data changes. The
amount can be reduced and the processing time can be made shorter than the configuration of
the first embodiment.
[0046]
As described above, according to the present invention, it is possible to reduce sound
interruptions and noises which have conventionally been a problem, and the position of the
sound image does not change regardless of the position of the listener. The degree of freedom of
the listening position is high, and a sufficient acoustic effect can be expected regardless of the
listener's position.
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[0047]
Further, by improving the D / A conversion unit as in the present invention, the amount of digital
signal processing can be reduced, and an effect of improving the processing capability of the
apparatus can be expected.
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