close

Вход

Забыли?

вход по аккаунту

?

JP2000050399

код для вставкиСкачать
Patent Translate
Powered by EPO and Google
Notice
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
DESCRIPTION JP2000050399
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an
audio signal processing circuit and method, and more particularly to simplification and high
accuracy of its configuration.
[0002]
2. Description of the Related Art FIG. 18 shows an acoustic signal processing circuit disclosed in
Japanese Patent Application Laid-Open No. 8-265899. This circuit is for causing the virtual
speakers XL, XR to emit sound by the left and right speakers 4L, 4R arranged in front of the
listener 2. With this circuit, even if there are only two speakers 4L and 4R, it can appeal to the
listener 2's hearing as if the speakers XL and XR were behind.
[0003]
In the apparatus of FIG. 18, this is realized by using four filters 6a, 6b, 6c and 6d. The transfer
functions H11, H12, H21 and H22 of the four filters are as follows.
[0004]
H11 = (hRRhL'L-hRLhL'R) / (hLLhRR-hLRhRL) H12 = (hLLhL'R-hLRhL'L) / (hLLhRR-hLRhRL) H21
09-05-2019
1
= (hRRhR'L-hRLhR'R) / ( hLLhRR-hLRhRL) H22 = (hLLhR'R-hLRhR'L) / (hLLhRR-hLRhRL) where
hRR is the transfer function from the speaker 4R to the right ear 2R of the listener 2 and hRL is
the speaker 4R to the listener A transfer function up to the left ear 2L of 2, hLL is a transfer
function from the speaker 4L to the left ear 2L of the listener 2, and hLR is a transfer function
from the speaker 4L to the right ear 2R of the listener 2.
[0005]
By the way, if both the speakers 4L and 4R and the virtual speakers XL and XR are symmetrical
with respect to the front axis 8 of the listener 2, then in the above equation hLL = hRR, hLR =
hRL, hL '. L = hR'R and hL'R = hR'L are satisfied.
Therefore, H11 = H22 and H12 = H21, and as shown in FIG. 19, the circuit can be configured by
two filters (referred to as a shuffler type filter). Here, the transfer functions HSUM and HDIF of
the filters 10a and 10b are expressed by the following equation.
[0006]
HSUM = (ha '+ hb') / 2 (ha + hb) HDIF = (ha '-hb') / 2 (ha-hb) where ha = hLL = hRR, hb = hLR =
hRL, ha '= hL'L = hR'R, hb' = hL'R = hR'L.
[0007]
As described above, in the case of the symmetrical arrangement, the sound image can be
localized at the virtual speaker position with a simple configuration.
[0008]
Further, as shown in FIG. 20, there are also cases where sound image localization processing is
performed using the crossfeed filter 12 and the crosstalk cancellation filter 14.
The crosstalk cancellation filter 14 functions to eliminate crosstalk from the right speaker 4R to
reach the left ear 2L and crosstalk from the left speaker 4L to reach the right ear 2R. Do.
09-05-2019
2
Thereby, the right channel signal R can be heard only to the right ear 2R, and the left channel
signal can be heard only to the left ear 2L. Therefore, the cross feed filter 12 can localize the
sound source at a desired position by adjusting the amount of crosstalk.
[0009]
The crosstalk cancellation filter 14 as described above can also be realized by a shuffler type
filter as shown in FIG. The transfer functions HSUM and HDIF of the filter 10a and the filter 10b
in this case are as follows.
[0010]
【0010】HSUM = ha / (2(ha + hb))HDIF = ha / (2(ha −
hb))
[0011]
If the filters 10a and 10b have high precision in the above-mentioned shuffler type filter, a circuit
having high sound image localization ability or high crosstalk cancellation ability can be realized.
However, if the filters 10a and 10b are to be made highly accurate, the configuration thereof
becomes complicated, and there is a problem that a large processing time is required for
realization by the DSP. In addition, there is a problem that the ability to be used as a shuffler type
filter decreases if the configuration is simple.
[0012]
SUMMARY OF THE INVENTION It is an object of the present invention to solve the abovementioned problems and to obtain a high-speed shuffler type filter with a simple configuration.
[0013]
The shuffler-type acoustic signal processing circuit according to claim 1 comprises a first filter
for processing a sum signal of a right channel signal and a left channel signal, and a right
09-05-2019
3
channel. A second filter for processing a difference signal between the signal and the left channel
signal is provided, and the low frequency region in the second filter is more accurate than the
first filter.
In the shuffler-type acoustic signal processing circuit, the gain of the first filter processing the
sum signal is lower than the gain of the second filter processing the difference signal in the low
frequency region. Therefore, by setting the accuracy of the second filter higher than that of the
first filter in the low frequency region, it is possible to simplify the circuit configuration while
preventing the decrease in the accuracy as much as possible.
[0014]
According to the shuffler-type acoustic signal processing circuit of the second aspect, the first
filter and the second filter are constituted by the FIR filter, and the number of taps of the second
filter is greater than the number of taps of the first filter. It is also characterized by many things.
Therefore, in the low frequency region, the accuracy of the second filter can be made higher than
that of the first filter, and the circuit configuration can be simplified while preventing the
deterioration of the accuracy as much as possible.
[0015]
The shuffler-type acoustic signal processing circuit according to claim 3 is characterized in that
the second filter is configured using a sub-band filter bank. Therefore, it is possible to afford a
processing capacity by downsampling.
[0016]
The shuffler-type acoustic signal processing circuit according to claim 4 is characterized in that,
in the sub-band filter bank of the second filter, the lower the frequency component is, the larger
down-sampling is performed. Therefore, in the low frequency region, the accuracy of the second
filter can be made higher than that of the first filter, and the circuit configuration can be
simplified while preventing the deterioration of the accuracy as much as possible.
09-05-2019
4
[0017]
According to the shuffler-type acoustic signal processing circuit of the fifth aspect, the first filter
is constituted by the FIR filter, and the second filter is constituted by the parallel connection of
the FIR filter and the second-order IIR filter. It is characterized. Therefore, in the low frequency
region, the accuracy of the second filter can be made higher than that of the first filter, and the
circuit configuration can be simplified while preventing the deterioration of the accuracy as
much as possible. Further, the low frequency region can be processed by the second-order IIR
filter, and it is possible to prevent the number of stages of the FIR filter from being unnecessarily
increased.
[0018]
The shuffler-type acoustic signal processing circuit according to claim 6 is characterized in that
the second filter is connected in parallel between the FIR filter, the intermediate tap of the FIR
filter, and the output of the FIR filter. It is characterized in that it is equipped with the following
IIR filter. Therefore, in the low frequency region, the accuracy of the second filter can be made
higher than that of the first filter, and the circuit configuration can be simplified while preventing
the deterioration of the accuracy as much as possible. Further, by changing the positions of the
middle taps connected in parallel, it is possible to obtain the optimum characteristics.
[0019]
The filter according to claim 9 adds an FIR filter having a plurality of taps, an IIR filter whose
input is connected to an intermediate tap of the FIR filter, an output of the FIR filter and an
output of the IIR filter. And adding means. Therefore, a filter having desired characteristics can
be easily obtained.
[0020]
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of a shuffler
type crosstalk cancellation filter 30 according to an embodiment of the present invention. A left
channel signal is given to the left channel input terminal LIN, and a right channel signal is given
to the right channel input terminal RIN. The left channel signal and the right channel signal are
09-05-2019
5
added in the adder 22 and provided to the first filter 20a. The left channel signal and the right
channel signal are also subtracted in the subtractor 24 and provided to the second filter 20b. The
transfer functions HSUM and HDIF of the first filter 20a and the second filter 20b are as follows.
[0021]
HSUM = ha / (2 (ha + hb)) HDIF = ha / (2 (ha-hb)) The adder 26 adds the outputs of the first filter
20a and the second filter 20b, It outputs as a signal for the speaker 4L. The subtractor 28
subtracts the outputs of the first filter 20a and the second filter 20b and outputs the result as a
signal for the speaker 4R.
[0022]
In this embodiment, the first filter 20a and the second filter 20b are constituted by FIR filters,
and the whole of the filter 30 is realized by DSP. FIG. 2 shows a hardware configuration when
realized using the DSP 40. The signals L and R of each channel are provided to the DSP 40 as
digital data. The DSP 22 performs processing such as addition, subtraction, and filtering on
digital data according to the program stored in the memory 46, and generates a left speaker
signal LOUT and a right speaker signal ROUT. These signals are converted to analog signals by
the D / A converter 42 and output as signals for the speakers 4L and 4R. Note that processing
such as storage of a program in the memory 26 is performed by the microprocessor 20.
[0023]
FIG. 3 shows the processing performed by the DSP 40 based on the program of the memory 46
in the form of signal flow. In this embodiment, the first filter 20a and the second filter 20b are
configured by FIR filters. In the figure, DS1 to DS32 and DD1 to DD96 are delay processing, and
perform delay processing for one sample. Here, the sample frequency is 48 kHz. Further, KS0 to
KS32 and KD0 to KD96 are coefficient processing. The number of taps of the first filter 10a (that
is, the number of delay processes) is 32, and the number of taps of the second filter 10b is 96. In
the FIR filter, as the number of taps increases, the accuracy in the low frequency region
increases. Therefore, in the example of FIG. 3, the second filter 10b has higher accuracy in the
low frequency region than the first filter 10a.
09-05-2019
6
[0024]
FIG. 4 shows the frequency characteristic of each filter when the number of taps of the first filter
10a is 32 and the number of taps of the second filter 10b is 32, and the response characteristic
zt1 of the crosstalk cancellation and the error zt2 . Here, the error is a response that can not be
sufficiently canceled, and in the case of crosstalk cancellation, it can be said that the smaller the
error, the better the filter. Here, an angle α (see FIG. 1) between the speaker 4L (or 4R) and the
listener 2 is set to 10 degrees. The number of taps 32 indicates that the accuracy is low and the
crosstalk cancellation error is large.
[0025]
Similarly, the case where the number of taps of both filters 10a and 10b is 64 is shown in FIG.
Although improved from the case of 32 taps, it is still shown that crosstalk cancellation error is
large.
[0026]
Further, the case where the number of taps of both filters 10a and 10b is 96 is shown in FIG. It
has been shown that there are very few errors. However, when the number of taps of both filters
10a and 10b is 96, there arises a problem that the calculation load of the DSP 40 is large.
[0027]
In this embodiment, focusing on the fact that the frequency characteristic required for the first
filter 10a is low and flat particularly at low frequencies, the number of taps of the first filter 10a
is set to The number of taps of the filter 10b was smaller than That is, in the low frequency
region, the accuracy of the first filter 10a is lowered, and the accuracy of the second filter 10b is
improved accordingly. Specifically, the number of taps of the first filter 10a is 32, and the
number of taps of the second filter 10b is 96. The characteristics in this case are shown in FIG.
[0028]
09-05-2019
7
As apparent from FIG. 7, the error substantially equal to that in the case where the number of
taps of both filters 10a and 10b is 96 can be suppressed. That is, it is possible to obtain a highly
accurate shuffler-type crosstalk cancellation filter while suppressing the overall number of taps.
[0029]
FIG. 8 shows a signal flow according to another embodiment. Also in this embodiment, the
number of taps (substantially 128) of the second filter 20b is made larger than the number of
taps (32) of the first filter 20a using an FIR filter. However, in this embodiment, in the second
filter 20b, the filter bank is adopted and down-sampled before passing through the FIR filter. In
the figure, H is a high pass filter and G is a low pass filter. Also, ↓ indicates a half down sample
and は indicates a double up sample. Delays 205, 206, and 208 are delay processes for
compensating time for each filter bank process. The delay 205 is delayed by 3 samples, 206 by 1
sample, and 208 by 7 samples.
[0030]
By adopting the filter bank in this way, it is possible to suppress the total number of taps of the
FIR filters 201, 202, 203 and 204 to 68 taps while substantially obtaining the ability of 128 taps
in the original sampling, Downsampling can provide extra processing capacity. This makes it
possible to increase the accuracy of low frequency components. Further, in this embodiment,
although the filter bank is divided into octaves in which division is repeated on the side of low
frequency components, it may be an equal division filter bank which also divides high
frequencies.
[0031]
FIG. 9 shows the crosstalk cancellation error ZT2 when the number of taps of the first filter 10a
is 32 and the number of taps of the second filter 10b is 128 without employing a filter bank.
Further, FIG. 10 shows a crosstalk cancellation error ZT2 according to the configuration of FIG.
As is clear from both the figures, it can be seen that the circuit of FIG. 8 employing the filter bank
has the same performance as the case of 128 taps.
09-05-2019
8
[0032]
FIG. 11 shows a signal flow according to another embodiment. In this embodiment, the first filter
20a is constituted by a 32-tap FIR filter, and the second filter 20b is constituted by a 32-tap FIR
filter 210 and a second-order IIR filter 212. The outputs of FIR filter 210 and second-order IIR
filter 212 are added by adder 214.
[0033]
In this embodiment, the number of taps of the FIR filter 210 of the second filter is reduced to 32,
and the accuracy with respect to low frequency components is improved by the second-order IIR
filter 210. Since the second-order IIR type filter can obtain high accuracy in low frequency
components, the same accuracy can be realized with a smaller number of taps than in the case of
configuring all by FIR type filters as shown in FIG. Although a second-order IIR filter is used in
this embodiment, an n-order IIR filter can be used. In addition, n-order IIR filters may be
connected in series or in parallel.
[0034]
FIG. 12 shows the characteristic HSUM of the first filter 20a and the characteristic HDIF of the
second filter 20b in the circuit of FIG. Also, a crosstalk cancellation error ZT2 is shown. It can be
seen that an accuracy close to that in the case of FIG. 7 is obtained.
[0035]
In the embodiment of FIG. 11, the second filter 10b is a perfect parallel connection of the FIR
filter and the second-order IIR filter. However, as shown in FIG. The input to the type filter may
be taken out. By doing so, it is possible to easily obtain the second filter 10b closer to the desired
characteristics.
[0036]
09-05-2019
9
The method for designing the filter shown in FIG. 13 will be described with reference to FIGS. 14,
15, 16 and 17. FIG. FIG. 14 shows an impulse response of the required second filter 10b. Based
on this, the characteristics of the second-order IIR filter are determined. At this time, as shown in
FIG. 15, the former one of the impulse response is disregarded, and the characteristic is
determined so as to closely approximate the latter one of the impulse response (that is, the low
frequency region). In FIG. 15, the characteristic of a second-order IIR filter approximating the
impulse response after k samples is obtained. However, between k and m samples, impulse
responses that differ greatly are obtained.
[0037]
Next, an FIR filter that realizes an impulse response of 0 to m samples is obtained. However, in
the k to m samples, as shown in FIG. 16, the characteristics of the second-order IIR filter and the
characteristics of the required filter are largely deviated. Therefore, in consideration of such an
error, an FIR filter which realizes an impulse response of 0 to m samples as shown in FIG. 17 is
obtained.
[0038]
As described above, the second filter 10b as shown in FIG. 13 can be obtained. The position of
the tap for taking out the second-order IIR filter is the tap (k-tap in the above case)
corresponding to the leading sample (k sample in the above case) when the characteristics of the
second-order IIR filter are approximated. In this way, a filter having desired characteristics can be
easily obtained. The number of taps shown in each of the above embodiments is an example.
Further, although the crosstalk cancellation filter has been described in the above embodiments,
the present invention can be applied to a sound image localization processing filter in the same
manner.
[0039]
In the above embodiment, the first filter 10a is an FIR type filter, but in the same manner as the
second filter 10b, the first filter 10a is a parallel connection of the FIR type filter and the IIR type
filter (FIG. 11, FIG. 13). Or, it may be a filter bank configuration. Even in this case, by lowering
the accuracy of the first filter 10a rather than the second filter 10b, the accuracy can be
maintained while simplifying the overall configuration.
09-05-2019
10
[0040]
In each of the above embodiments, the filter is realized using a DSP, but part or all of the filter
may be realized by an analog filter.
[0041]
Brief description of the drawings
[0042]
1 is a diagram showing the configuration of a shuffler type filter according to an embodiment of
the present invention.
[0043]
2 is a diagram showing a hardware configuration when the filter of FIG. 1 is realized using a DSP.
[0044]
3 is a diagram showing a program stored in the memory 46 as a signal flow.
[0045]
4 is a diagram showing the characteristics when the first filter 10a and the second filter 10b both
have 32 taps.
[0046]
5 is a diagram showing the characteristics when the first filter 10a and the second filter 10b are
both 64 taps.
[0047]
6 is a diagram showing the characteristics when the first filter 10a and the second filter 10b are
both 96 taps.
[0048]
09-05-2019
11
7 is a diagram showing the characteristics when the first filter 10a has 32 taps and the second
filter 10b has 96 taps.
[0049]
8 is a diagram showing a signal flow in an embodiment using a filter bank.
[0050]
9 is a diagram showing the characteristics when the first filter 10a has 32 taps and the second
filter 10b has 128 taps in the circuit of FIG.
[0051]
10 is a diagram showing the characteristics when the first filter 10a has 32 taps and the second
filter 10b has 128 taps by the filter bank in the circuit of FIG.
[0052]
11 is a diagram showing a signal flow in an embodiment in which the second filter 10b is a
parallel configuration of an FIR filter and an IIR filter.
[0053]
12 is a diagram showing the characteristics of the circuit of FIG.
[0054]
13 is a diagram showing an embodiment in which the input of the IIR filter is taken out from the
middle tap of the FIR filter.
[0055]
14 is a diagram showing the impulse response of the desired filter.
[0056]
15 is an impulse response of an IIR filter that approximates the characteristics of FIG.
[0057]
09-05-2019
12
16 is a diagram showing the deviation between the desired characteristics and the characteristics
of the IIR filter.
[0058]
17 is an impulse response of the FIR filter obtained in consideration of the deviation of FIG.
[0059]
18 is a diagram showing a conventional sound image localization processing circuit.
[0060]
FIG. 19 is a circuit diagram of a shuffler type filter.
[0061]
FIG. 20 is an example of a case where a sound image localization circuit is configured by the
cross feed filter and the crosstalk cancellation filter.
[0062]
Explanation of sign
[0063]
20a: first filter 20b: second filter 40: DSP
09-05-2019
13
Документ
Категория
Без категории
Просмотров
0
Размер файла
22 Кб
Теги
jp2000050399
1/--страниц
Пожаловаться на содержимое документа