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# JPH04142108

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DESCRIPTION JPH04142108
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a
cosine equalizer device having cosine-shaped amplitude frequency characteristics, and in
particular, a wideband delay line of a cosine equalizer capable of varying the amount of delay by
changing current or voltage externally. It concerns the built-in. PRIOR ART FIG. 2 shows the
principle of a conventional cosine equalizer apparatus. In the figure, 7 is a first delay line, 8 is a
second delay line, 4 'is a first adder, 9 is an amplitude adjuster, 10 is a phase inverter, and 11 is a
second adder. Next, the principle of operation will be described. The input signal input to the
input terminal is Ee4 ′ ′ ′ ′. Assuming that the delay amount of the 1st second delay lines 7
and 8 is τ, the signals at the input end (point A) and points B and C are respectively A point = Ee
′ ′ ′ □ ′ B point ==: E e I 1 “at” point C = Ee ′ (1) (“2”). Then, the signal at point D
becomes point D = point A + point C E = 2 ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′ ′
cos ωr and is multiplied by the amplitude adjuster and inverted by the phase inverter, the signal
at point E becomes point E = −2 k E e “” ”“ 'cos ωr. Therefore, the output signal output to
the output terminal is output signal = point B + point E = E (1-2 k cos ωr) e ′ ′ ′ ′ ′ ′ c ′
(1). From the equation (1), it can be seen that the output signal has a time delay of τ with
respect to the input signal, or there is no phase distortion at all. Further, the above equation can
be expressed as an amplitude frequency characteristic as shown in FIG. From equation (1) or FIG.
3, ωτ = a · π (a is 1. ３． In the case of an odd number of 5 ...), that is, assuming that a = 1, it
exhibits a cosine characteristic in which the amplitude becomes maximum at a frequency of f = 1
/ 2τ (ω = 2πf). Here, a usage example of the cosine equalizer device will be described. In
magnetic recording, in the recording and reproducing process, the amplitude of the lower side
wave is larger than the upper side wave and the reproduction is performed. This situation is
shown in FIG. By adjusting the value of k using a cosine equalizer to adjust a left-right
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without causing phase distortion as shown in FIG. Next, the actual operation will be described.
FIG. 6 shows a conventional cosine equalizer apparatus. In the figure, 12 is a matching resistor of
a delay line, 13 is a delay line, 14 is a high input impedance variable gain amplifier, and 15 is a
high input impedance difference. Next, the operation will be described. The delay line 13 is a
block filter configured by combining a capacitor, a coil and others, and there is no reflection
because the signal input to the point F has a matching resistance 12 or not, the point H is high
because it is not a matching resistance 12 Due to the impedance and the so-called oven state, the
signal is inverted 100% in phase.
Therefore, the point G is obtained from the signal D = A to C similar to the point -0 in the
operation principle diagram of FIG. This signal is determined by the variable gain amplifier 14
and is input to the difference unit 15. Since this differencer 15 is equivalent to (phase inverter 10
+ tenth adder 11) in FIG. 2, this device operates as a cosine equalizer. The delay line 13 is
configured as a discrete component, and the variable gain amplifier 14 and the difference unit 15
are configured as a discrete component or a semiconductor integrated circuit. [Problems to be
Solved by the Invention] Since the conventional cosine equalizer device is configured as
described above, when it is desired to vary the frequency at which the amplitude of the cosine
equalizer device is maximum, the delay amount is calculated according to the relationship of f = 1
/ 2τ. Because of the fixed delay amount of the discrete block filter as a delay line, it is necessary
to switch several kinds of filters to change f, and it is necessary to change the configuration or
complexity. In addition, the filter itself has an error in the amount of delay, and there is also a
problem in that f or the like changes slightly. SUMMARY OF THE INVENTION The present
invention has been made to solve the above-mentioned problems, and an object thereof is to
obtain a cosine equalizer device capable of incorporating the entire device into an integrated
circuit and continuously varying the frequency at which the amplitude is maximum. . According
to the present invention, there is provided a cosine equalizer device comprising: a first variable
delay line variable in delay, which delays a signal input from an input terminal; and an output of
the first variable delay line. , An adder for adding the output of the input signal and the output of
the second variable delay line, a variable gain amplifier for controlling the output of the adder,
and an output of the amplifier And a difference unit for extracting the difference between the
outputs of the first variable delay line, and an interface circuit for controlling the delay amounts
of the first and second variable delay lines from the outside so that they have almost the same
desired amount. It is provided in a semiconductor integrated circuit. [Operation] The cosine
equalizer device in the present invention uses two delay lines which can be incorporated as a
delay line in a semiconductor integrated circuit and whose delay amount can be varied by voltage
or current, so that the entire device is incorporated in a semiconductor integrated circuit. And the
frequency at which the amplitude is maximum can be easily varied freely. An embodiment of the
present invention will be described below with reference to the drawings. The first shows a
cosine equalizer apparatus according to an embodiment of the present invention. In the figure, 1
is a first variable delay line, 2 is a second variable delay line, 3 is an interface circuit, 4 is an
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adder, 5 is a variable gain amplifier, and 6 is a difference unit.
Next, the operation will be described. The difference from the diagram showing the operation
principle of FIG. 2 is that the first and second delay lines 78 are changed to variable type, and the
control voltage and current from the outside are controlled as desired to control the delay
amount. The only difference is that the interface circuit 3 for converting into a signal is added
and the combination of the phase inverter 10 and the adder 2 or the differencer 6 is changed.
Therefore, it is possible to equalize the input signal by the same operation as that of the
conventional device. At this time, in the present embodiment, the delay amount of the delay line
can be changed continuously or discretely by the interface circuit, and the amplitude based on f,
= 1 / 2τ by the delay amount τ1 determined by this delay control. The maximum frequency (=
f) and hence the entire amplitude frequency characteristic can be freely displaced in the
frequency axis direction. Therefore, even if the carrier frequencies of the cosine equalizer device
according to the present embodiment are different signals, such as VH3 signal and 5-VH3 signal
in VTR, the cosine equalizer can be equalized by changing the delay amount. Since the delay
amount is arbitrary, it can be applied to equalization of various other signals. Furthermore, the
present invention can be applied not only to VTRs, but also to general electromagnetic
conversion systems. As described above, the cosine equalizer device according to the
embodiment of the present invention responds to the control of the frequency at which the
amplitude of the device is maximum, in the case of the carrier frequency or a different mode, or
in the case of error correction of the delay amount of the delay line itself, etc. It can be freely
changed with a simple configuration. The first and second variable delay lines 1 and 2 are
generally gm'1liT variable control type filters consisting of an operational amplifier and a
capacitor, but the gain 2 group delay amount within the use band is flat. It is desirable. Also,
barrier pull capacitor control may be used. Further, although the adder 4 and the variable gain
amplifier 5 are separately provided, both processing may be simultaneously performed by the
adder 2 capable of amplitude control of the output. As described above, according to the cosine
equalizer device of the present invention, it is possible to use a delay-variable first variable delay
line for delaying a signal input from an input terminal, and a first variable delay line of the first
variable delay line. A variable delay second variable delay line for delaying an output, an adder
for adding the output of the input signal and the output of the second variable delay line, a
variable gain amplifier for amplitude controlling an output of the adder, A differencer for
extracting the difference between the output of the amplifier and the output of the first variable
delay line, and an interface for controlling the delay amounts of the first and second variable
delay lines from the outside so as to be substantially the same desired amount Since the circuit
and the circuit are provided in the semiconductor integrated circuit, control of the frequency at
which the amplitude of the cosine equalizer apparatus is maximized.
There is an effect that it can be freely varied with a simple configuration according to the case of
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the carrier frequency or a different mode, or the case of correcting the error of the delay amount
of the delay line itself.
[0002]
Brief description of the drawings
[0003]
1 shows a cosine equalizer according to an embodiment of the present invention, FIG. 2 shows
the operation principle of the conventional cosine equalizer, FIG. 3 shows a cosine characteristic,
and FIG. FIG. 5 is a diagram showing frequency characteristics at the time of reproduction of
recording, FIG. 5 is a diagram showing that correction is performed after passing through a
cosine equalizer device, and FIG. 6 is a diagram showing a conventional cosine equalizer device.
In the figure, 1 is a first variable delay line, 2 is a second variable delay line, 3 is an interface
circuit, 4 adders, 4 'is a first adder, 5 is a variable gain tank 1 and 6 is a differencer , 7 is a first
delay line, 8 is a second delay line, 9 is an amplitude adjuster, 10 is a phase inverter, and l is a
second adder. In the drawings, the same reference numerals denote the same or corresponding
parts.
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