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JPH06282280

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DESCRIPTION JPH06282280
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a noise
reduction device for reducing noise by adding antiphase noise to noise, such as noise in
passenger compartments such as passenger cars, buses, ships, aircrafts, cabins, etc. Can be
applied to the reduction of
[0002]
2. Description of the Related Art As a method of reducing noise by adding an antiphase sound to
noise, there is generally an adaptive control method as disclosed in Japanese Patent Laid-Open
No. 3-204354. Here, the signal from the crank angle sensor and the engine ignition pulse are
multiplied as they are and waveform-shaped. The waveform-shaped signal is processed in an
adaptive digital filter (Adaptive Digital Filter) and sent to a speaker. The sound emitted from the
speaker interferes with the noise from the engine, so the engine sound is silenced. In addition, a
microphone for error detection is placed at the periphery of the ear as residual sound detection
means, and the constant of the adaptive digital filter is corrected based on the signal detected by
the microphone.
[0003]
U.S. Pat. No. 4,977,600 discloses a noise reduction system technology in which speakers are
provided on both upper sides of a vehicle seat, and a microphone for error detection is disposed
in proximity to the speakers.
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1
[0004]
FIG. 8 shows one configuration using an adaptive digital filter ADF.
The noise detection microphone M1 detects noise. The error detection microphone detects the
sound in the room. The adaptive digital filter ADF sets the filter coefficient so as to reduce the
level of the indoor sound, and emits the antiphase noise of the noise from the speaker SP. As a
result, the person in the room hears a synthetic sound of noise and antiphase noise, and the noise
is canceled and muffled.
[0005]
When mounted on a vehicle, it is usually necessary to mute the engine sound, but there is a
method of detecting the engine rotation speed instead of the noise detection microphone M1 to
estimate the noise. FIG. 9 shows a method of estimating noise from the engine speed. The engine
rotation sensor PP detects the number of rotations of the engine 12. The adaptive digital filter
ADF performs a product-sum operation on a detection signal of engine rotation with a
predetermined filter coefficient, and generates sound from the speaker SP. On the other hand, the
signal VB detected from the error detection microphone M2 is sent to the adaptive digital filter
ADF. The adaptive digital filter ADF obtains a filter coefficient which seems optimal from the
signal VB, and changes the filter coefficient.
[0006]
SUMMARY OF THE INVENTION In the above-mentioned technology, the engine speed is detected
and the noise from the engine is estimated from the engine speed. The actual engine noise
transmitted to the passenger compartment is not determined only by the engine speed, but
changes due to changes in the engine room, resonance conditions in the passenger compartment,
humidity, temperature changes, and the like. Therefore, when the noise is specified only from the
engine speed, the waveform of the actual noise waveform and the predicted noise signal
waveform deviate from each other, and there is a possibility that sufficient noise reduction can
not be performed.
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[0007]
Therefore, in the present invention, when specifying the noise to be fed back to the adaptive
digital filter from among the sounds whose errors are detected, it is an object to improve the
muffling efficiency.
[0008]
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, in the invention
of claim 1, a pulse conversion circuit for generating a pulse wave of duty 50% having the same
frequency as the frequency of the signal of the ignition pulse of the engine. , A waveform shaping
circuit for converting the output pulse of the pulse conversion circuit into a sine wave, an
adaptive digital filter for adaptively controlling a sine wave signal output from the waveform
shaping circuit, and sound generation in a room based on the output signal of the adaptive digital
filter Speakers, an error detection microphone that detects sound in a room and feeds it back to
an adaptive digital filter, a phased lock loop that generates a clock pulse obtained by multiplying
the frequency of the pulse wave output from the pulse conversion circuit, and a phased lock loop
Receives clock pulses and is detected by the error detection microphone Of note was, and a
frequency selection means for extracting only a frequency band that is determined by the clock
pulses.
[0009]
According to the above means, only the sound in the frequency range determined by the
rotational frequency of the engine is input to the adaptive digital filter.
The adaptive digital filter sets the filter coefficient of the adaptive digital filter so that the
detection sound of the error detection microphone is minimized by the feedback from the error
detection microphone, performs convolution operation of the input, and the sound in the
frequency range determined by the rotational frequency of the engine Works to generate an
antiphase sound from the speaker.
In the feedback from the error detection microphone, only the frequency band of the noise
actually generated by the engine is extracted by the frequency selection means, so that the
optimum antiphase sound is obtained in the frequency band of the engine noise.
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[0010]
In the phase-locked loop, a pulse conversion circuit sends a pulse wave with a duty of 50%
having the same frequency as the frequency of the signal of the ignition pulse of the engine.
[0011]
The phase-locked loop mainly comprises a phase comparator, a loop filter, and a voltage
controlled oscillator.
The phase comparator detects the phase difference between the input signal and the signal from
the voltage controlled oscillator, and outputs the error as a voltage. The loop filter is for cutting
high frequency components of the error signal. The voltage controlled oscillator adjusts the
phase in an attempt to null the error signal and oscillates at a frequency corresponding thereto.
This oscillation signal is a pulse with a duty of 50%. If the duty of the input signal of the phase
comparator is 50%, the phase difference between the signal input to the phase comparator and
the output signal of the voltage controlled oscillator is simple, and the voltage controlled
oscillator reduces this phase difference. Works simply However, if the duty of the input signal of
the phase comparator is not 50%, the phase difference between the signal input to the phase
comparator and the output signal of the voltage control oscillator is not simple, and the operation
of the voltage control oscillator becomes complicated. The voltage corresponding to the current
may be disturbed by increasing or decreasing. As a result, the oscillation frequency of the voltage
controlled oscillator also fluctuates sharply. When the frequency selection means inputs this
pulse with a large fluctuation as a clock pulse, the desired frequency can not be passed.
Therefore, it is desirable that the duty of the output pulse of the pulse conversion circuit is 50%.
In the above means, the pulse conversion circuit generates a pulse wave of 50% duty with the
same frequency as the frequency of the signal of the ignition pulse of the engine as the input of
the loop filter, so the frequency selection means is stable Operate.
[0012]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be
described by way of example with reference to the drawings.
[0013]
FIG. 1 is an overall schematic view of the present invention.
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The speaker SP and the error detection microphone M extend from the headrest 11 of the seat
10 to the ear. The speaker SP and the error detection microphone M may extend from the
backrest 14 of the seat 10.
[0014]
The engine 12 operates in response to the ignition pulse signal E. The pulse conversion circuit
PTC receives the ignition pulse signal E of the engine 12 and outputs a pulse signal ET. The pulse
signal ET has the same frequency as the ignition pulse signal E, and is a pulse signal having a
duty of 50%. The pulse signal ET is input to a waveform shaping circuit WFC and a phased lock
loop PLL. The waveform shaping circuit WFC receives the pulse signal ET, and outputs a
reference signal PA obtained by shaping the pulse signal ET. The phase locked loop PLL
generates a clock pulse CL. The clock pulse CL is a pulse signal having a frequency that is a
predetermined multiple of the pulse signal ET. Clock pulse CL is applied to frequency selector
SCF. The frequency selector SCF receives the error signal VB from the error detection
microphone M and outputs an error signal PD. The frequency selector SCF works to pass only the
frequency band of the clock pulse CL. An adaptive digital filter (Adaptive Digital Filter) ADF,
which is an adaptive filter, receives the reference signal PA and the error signal PD, and outputs a
mute signal PB. The adaptive digital filter ADF adjusts the phase and gain of the reference signal
PA so as to minimize the error signal PD, which is a feedback signal, and outputs the adjusted
signal as the mute signal PB. The mute signal is output as sound at the speaker SP.
[0015]
Here, the configuration of the pulse conversion circuit PTC will be described with reference to
FIG. The external clock output of the external clock generation circuit 20 for generating an
external clock of 10 KHz is connected to the clock terminal of the binary counter 21 and the
clock down terminal of the up / down counter 24. Here, SPG8640B is used as the external clock
generation circuit 20. In addition, the dual 4-bit 74HC 393 is used for the binary counter 21 and
the 74HC193 is used for the up / down counter 24. The ignition pulse signal E is input to a short
pulse conversion circuit 23 configured of a NOT gate, a resistor, a capacitor, and a NAND gate.
The load signal which is the output of the short pulse signal conversion circuit 23 is further
inverted, delayed by the delay circuit 22, and then sent to the binary counter 21 as a reset signal.
Here, the delay circuit 22 uses DCE 35-20. The second to eighth bits (Q2 to 8) of the output of
the binary counter 21 are the first to seventh bits of the input of the up / down counter 24 or 25
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(P0 to P3 of the up / down counter 24, P0 to 2 of the up / down counter 25) It is connected to
the. The outputs of the up / down counters 24 and 25 (Q 0 to 3 of the up / down counter 24 and
Q 0 to 2 of the up / down counter 25) are inverted by the NOT gate and input to the NAND gate
26. The load signal and the output of the NAND gate 26 are inverted by the NOT gate and input
to the OR gate 27. The output of the OR gate 27 is input to the clock terminal of the JK flip flop
28.
[0016]
Next, the operation of the pulse conversion circuit PTC will be described with reference to FIG.
First, an external clock generation circuit 20 generates an external clock of 10 KHz. The external
clock is used as a clock for the binary counter 21 and the up / down counter 24. The short pulse
conversion circuit 23 converts an input ignition pulse signal E into a load signal. Here, the
ignition pulse signal E is inverted, delayed by a delay circuit using a resistor and a capacitor, and
the delayed signal and the ignition pulse signal are ANDed. As a result, the output of the short
pulse conversion circuit 23 becomes low only for a predetermined time determined by the
resistor and the capacitor from the rise of the ignition pulse signal E. The load signal which is the
output of the short pulse signal conversion circuit 23 is further inverted, delayed by the delay
circuit 22, and then sent to the binary counter 21 as a reset signal.
[0017]
The binary counter 21 is reset by the reset signal and counts up at the rising edge of the external
clock. The load signal is input to the up / down counters 24 and 25 at the rise of the ignition
pulse, and the value of the input at that time is set.
[0018]
After that, it counts down every time the external clock comes. The binary counter 21 is reset
after the up / down counters 24 and 25 set the input value under the influence of the delay
circuit 22 and starts counting up again. The second to eighth bits (Q2 to 8) of the output of the
binary counter 21 are the first to seventh bits of the input of the up / down counter 24 or 25 (P0
to P3 of the up / down counter 24, P0 to 2 of the up / down counter 25) At the time of loading,
half of the count value of the binary counter 21 is set. In this way, in half the cycle of the ignition
pulse, the count value becomes zero, and a state appears in which the load signal, the outputs Q0
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to 3 of the up / down counter 24 and the outputs Q0 to 2 of the up / down counter 25 all
become low. . When the outputs of the up / down counters 24 and 25 are respectively inverted
and input to the NAND gate 26, a low level output can be obtained from the NAND gate 26 when
all the outputs of the up / down counters 24 and 25 are low. When the load signal and the
output of the NAND gate 26 are respectively inverted and input to the OR gate 27, the output of
the OR gate 27 generates a short pulse which becomes high level every half cycle of the ignition
pulse. When the output of the OR gate 27 is input to the clock terminal of the J-K flip flop 28, a
high level signal of the OR gate 27 can be used as a trigger to output a pulse signal ET having a
duty of 50%.
[0019]
The internal structure of the phase locked loop PLL is shown in FIG. The phase-locked loop PLL
includes a phase comparator 31, a loop filter 32, a voltage control oscillator 33, and a divider.
The phase comparator 31 outputs a phase error between the duty converted ignition pulse signal
ET and the output of the frequency divider 34 to the loop filter 32 as a signal. The loop filter 22
takes the form of an integrator and delivers the phase error signal in the form of an analog
voltage to the voltage controlled oscillator 33. The voltage control oscillator 33 oscillates a
frequency pulse corresponding to the input voltage and outputs it as a clock pulse CL and sends
it to the phase comparator 31. The clock pulse CL is set to be N times the frequency of the
ignition pulse signal ET. The value of N is set in advance. The divider 34 divides the clock pulse
CL and outputs a divided signal to the phase comparator 31. The frequency divider 34 is set to
set the frequency of the clock pulse CL to 1 / N.
[0020]
Now, it is assumed that N times the frequency of the ignition pulse signal E matches the
frequency of the clock pulse CL. Here, when the engine speed increases, a phase difference
occurs between the pulse from the frequency divider 23 and the ignition pulse signal ET. At this
time, the phase comparator 31 outputs a signal corresponding to this phase difference. When the
phase increases, the output pulse voltage is increased, and when the phase difference decreases,
the output pulse voltage is decreased. The loop filter 32 converts the output pulse into an analog
voltage, and the voltage control oscillator 33 generates a clock pulse of a frequency
corresponding to this analog voltage. Thus, when the phase difference increases, the clock
frequency increases, and when the phase difference decreases, the clock frequency decreases.
Therefore, the clock frequency goes up and down according to the engine speed. Since the loop
filter 32 has an integrator configuration, the phase difference matches, and even if the pulse
08-05-2019
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from the charge pump is not output, the previous value is continuously output. Therefore, the
frequency of the clock pulse CL is N times the engine speed.
[0021]
The frequency selector SCF is a switched capacitor filter. The switched capacitor filter is an
integrator to which the property of a switched capacitor having an equivalent resistance Req of 1
/ (C · fc) is applied. When designing a filter, if this Req is a resistor, a filter that follows changes in
fc can be realized. As a switched capacitor filter, there is an MF10 universal monolithic dual
switched capacitor filter manufactured by National Semiconductor. By using this MF 10, it is
possible to form a band pass filter that extracts only the frequency band corresponding to the
frequency fc of the clock pulse CK.
[0022]
A clock pulse having a frequency N times the frequency of the engine speed is applied to the
frequency selector SCF, and the frequency selector SCF adjusts the frequency band to be selected
according to the frequency of the clock pulse CL. By adjusting this value N and the voltage range
of the voltage control oscillator 33, it is possible to obtain a band pass filter that can extract only
a frequency that is a predetermined multiple of the engine speed. Thereby, only the n-th
harmonic component of the engine speed can be extracted from the sound detected by the error
detection microphone M. Normally, in a 4-cylinder engine, the level of the second harmonic
component of the engine speed is high, and this is a factor of noise in the passenger
compartment. Therefore, in the case of a 4-cylinder car, the value N and the voltage of the
voltage control oscillator 33 It is good to adjust the range and sort the frequency per twice the
engine speed.
[0023]
Here, a pulse wave ET having a duty of 50% having the same frequency as the frequency of the
ignition pulse signal E of the engine is sent to the phase-locked loop PLL by the pulse conversion
circuit PTC. As shown in FIG. 5, when the duty of the input signal of the phase comparator 31 of
the phase-locked loop PLL is 50%, the phase difference between the signal input to the phase
comparator 31 and the output signal of the voltage control oscillator 33 is simple. The voltage
control oscillator 33 simply operates to reduce this phase difference. However, as shown in FIG.
08-05-2019
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6, if the duty of the input signal of the phase comparator 31 is not 50%, the phase difference
between the signal input to the phase comparator 31 and the output signal of the voltage control
oscillator 33 is not simple. The operation of the oscillator 33 is complicated, and the voltage
commensurate with the phase difference is also disturbed by increase or decrease. As a result,
the oscillation frequency of the voltage control oscillator 33 also fluctuates sharply. When the
frequency selector SCF receives this pulse with a large fluctuation as a clock pulse, it can not pass
the desired frequency. Therefore, the duty of the output pulse of the pulse conversion circuit PTC
is desirably 50%. In the present embodiment, the pulse conversion circuit PTC generates a pulse
wave ET of 50% duty with the same frequency as the frequency of the ignition pulse signal E of
the engine, and is used as the input of the loop filter PLL. SCF operates stably.
[0024]
The sound produced by the speaker goes into the driver's and passenger's ears together with the
noise that comes from the engine and the outside of the vehicle interior. At the same time, these
sounds are detected by the error detection microphone M. The output VB of the error detection
microphone M is sent to the adaptive digital filter ADF. The adaptive digital filter ADF comprises
a transversal filter 35 and an adaptive algorithm 36, as shown in FIG. The adaptive algorithm 36
receives the output VB of the error detection microphone M and determines the filter coefficient
of the transversal filter 35. The transversal filter 35 shapes the ignition pulse of the engine,
convolutes the reference signal PA converted into the sound signal, and sends the signal sound
PB to the speaker SP. Thereby, the adaptive digital filter ADF adjusts the filter coefficient so as to
minimize the level of the detection sound of the error detection microphone M.
[0025]
By inserting a band pass filter that follows only the frequency range of noise on the error
detection microphone M side, only noise can be muffled reliably.
[0026]
In the above embodiment, since control is performed by separating only the noise frequency
band, noise can be silenced surely and the convergence speed of the adaptive digital filter ADF is
improved.
Therefore, the effectiveness of the adaptive digital filter ADF is increased.
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[0027]
In the case of a six-cylinder engine, the rotational primary component, the 1.5th component, the
secondary component, the 2.5th component and the tertiary component of the engine appear in
the noise distribution in the vehicle compartment. When it is desired to mute all of these
components, a plurality of frequency multipliers are provided to multiply the signal obtained
from the ignition pulse of the engine, and the respective outputs are combined and input to the
adaptive digital filter ADF. A plurality of components may be provided, each component may be
extracted and then combined, and fed back to the adaptive digital filter ADF.
[0028]
As described above, since only the noise is silenced and the necessary sounds such as music,
voice, alarm, warning sound and the like are not silenced, it can be installed in a car.
[0029]
Although the apparatus for reducing engine noise in a vehicle is shown in the above embodiment,
the present invention is not limited to a vehicle, but can be applied to a device in which the
frequency of the noise part changes according to the state of the noise source.
For example, there are a number of possible applications, such as reducing engine noise in an
airplane room, and reducing noise emitted from equipment such as a treatment placed on the
side of the bed, for use in a patient's bed in a hospital.
[0030]
Since the speaker SP and the error detection microphone M are disposed near the human ear, the
speaker SP does not have to make a loud sound. For this reason, the sound emitted from the
speaker SP affects the part away from the seat 10 and the outside of the vehicle, and the sound is
hardly emphasized in other parts.
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[0031]
Therefore, the noise only in the ear of the person sitting on the seat is reduced and nothing else
is affected.
[0032]
When the present invention is mounted on a vehicle, the noise reduction device of the present
invention can be mounted on each seat.
In this case, it is preferable to provide a switch for permitting / prohibiting the operation of the
present apparatus so that each seat can be switched. For example, the person who sleeps in the
rear seat can operate this device, and the driver can turn off the operation of this device to
confirm the engine sound and prevent drowsiness, etc. Becomes possible.
[0033]
As described above, in this embodiment, the pulse conversion circuit PTC that generates a pulse
wave of 50% duty with the same frequency as the signal frequency of the ignition pulse of the
engine, and the output pulse of the pulse conversion circuit are sine waves , An adaptive digital
filter ADF for adaptively controlling a sine wave signal output from the waveform forming circuit,
a speaker SP for generating sound in the room based on the output signal of the adaptive digital
filter, sound in the room An error detection microphone M that detects and feeds back to an
adaptive digital filter, a phased locked loop PLL that generates a clock pulse that multiplies the
frequency of the pulse wave output from the pulse conversion circuit, and a clock pulse from the
phase locked loop Of the sound detected by the detection microphone Chi, and a frequency
selector SCF is a frequency selective means for extracting only the frequency range of the clock
pulse. Therefore, since the noise reduction is performed only for the sound of the specific
frequency emitted from the engine, instead of trying to delete all the sounds heard by the user,
the sounds required for the user are not deleted. In addition, since the noise actually generated is
detected, the noise reduction effect is excellent. Despite the use of an adaptive digital filter, the
convergence speed and noise cancellation amount are excellent. Furthermore, since a pulse wave
with a duty of 50% having the same frequency as the frequency of the ignition pulse signal of the
engine is generated as an input of the loop filter, the frequency selection means operates stably.
Therefore, it is not necessary to care about the duty of the ignition pulse signal of the engine.
Further, even if the duty of the ignition pulse signal of the engine changes in accordance with the
fluctuation of the engine speed, the muffling operation is performed accurately.
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[0034]
According to the present invention, only the sound of a specific frequency emitted from the
engine is noise-reduced, rather than trying to erase all the sounds heard by the user. I will not
erase it.
[0035]
In addition, since the noise actually generated is detected, the noise reduction effect is excellent.
[0036]
Even when using an adaptive digital filter, it is excellent in convergence speed and noise
cancellation amount.
[0037]
Furthermore, since a pulse wave with a duty of 50% having the same frequency as the frequency
of the ignition pulse signal of the engine is generated as an input of the loop filter, the frequency
selection means operates stably.
Therefore, it is not necessary to care about the duty of the ignition pulse signal of the engine.
Further, even if the duty of the ignition pulse signal of the engine changes in accordance with the
fluctuation of the engine speed, the muffling operation is performed accurately.
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