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JPH10336785

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DESCRIPTION JPH10336785
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an
audio signal processing apparatus connected to a speaker and used, a signal processing method
therefor, and a recorded medium recording the processing method, the reverse correction
corresponding to the response characteristic of the speaker The technology related to
reproducing high fidelity sound quality.
[0002]
2. Description of the Related Art FIG. 9 is a schematic block diagram showing a conventional
audio signal processing apparatus connected to a speaker and used as a first prior art. In the
figure, an analog audio signal is converted into a digital signal by an analog / digital conversion
means (A / D) 1, and the digital signal is inverted according to the response characteristic of the
speaker SP connected in the subsequent stage in the correction filter 2. It is supposed to be
corrected.
[0003]
This correction filter 2 includes a plurality of cascaded delay elements d 1, d 2,... D 1199 as
shown in FIG. 10, and input digital signals directly or as signals output from the respective delay
elements d 1, d 2,. .. M1200 for multiplying predetermined coefficients, and an adder a for
adding the output signals of these multipliers m1, m2,. Configured as an FIR type filter.
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[0004]
In this convolution operation, predetermined coefficients are read out from a coefficient holding
circuit (not shown) through a control circuit (not shown) and supplied to the multipliers m1, m2,.
Is supposed to be done.
As a result, the incoming signal is corrected in phase and amplitude characteristics, and the
signal is converted again into an analog signal by the digital / analog converting means (D / A) 3
and passes through the amplifying means 4 to the speaker SP. It is configured to be emitted
from.
[0005]
Further, FIG. 11 is an example in the case where a correction filter 2A is configured by cascading
an IIR type filter for correcting an extreme dip and a peak on the rear side of the FIR type filter in
the second conventional example. In the same way as the above-mentioned conventional
example, the former stage is composed of an FIR filter comprising delay elements d1, d2,...
D1199 and multipliers m1, m2,. , D 2,..., D 4, multipliers m 1, m 2,..., M 5 and an addition means
a.
[0006]
By the way, in both of the first and second prior art examples described above, the FIR filter
which is a component of the correction filter has a 44.1 kHz resolution in order to secure the
resolution on the low frequency side. 1,200 multipliers (1200 taps) are provided for the
sampling frequency to perform convolution operation.
[0007]
For example, FIG. 12 is a waveform characteristic diagram in the case where the input signal is
corrected by the apparatus shown as the first prior art example, and the waveform characteristic
is such that relatively good resolution can be obtained up to the low frequency.
[0008]
However, in the above configuration, a 1200-tap multiplier is required, and configuring this with
a DSP (digital signal processor) requires about 5 DSPs, resulting in a large circuit size and cost.
There was a problem of saying that
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[0009]
Then, the number of taps can be reduced to simplify the circuit scale. However, for example, if it
is configured with about 200 taps so as to fit in about one DSP, the waveform characteristics as
shown in FIG. 13 will result.
As apparent from the figure, a problem arises that the resolution is degraded particularly in a
relatively low frequency band of 100 Hz to 700 Hz, as compared with the case of the
configuration of 1200 taps described above (see FIG. 12).
[0010]
In the present invention, in view of such a problem, it is an object of the present invention to
prevent the deterioration of resolution in the low band and to simplify the circuit scale to reduce
the cost.
[0011]
The present invention comprises the following means (1) to (7) and the following means to
achieve the above object.
すなわち、
[0012]
(1) An audio signal processing apparatus for converting an incoming analog audio signal into a
digital signal and correcting the converted digital audio signal according to the response
characteristic of a predetermined frequency band of a connected speaker. A first filter unit
constituted by an FIR type filter which is supplied with one output signal of the digital audio
signal which has been output and which operates as a convolver, and is provided on the front
stage side or the rear stage side of the first filter means Second filter means for limiting a
predetermined band of the digital audio signal, and the other output signal of the converted
digital audio signal being supplied and delayed by substantially the same time as the delay time
by the first filter means Delay means, and is provided on the front side or rear side of the delay
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means, and A third filter means for limiting a signal in a band lower than the band, and an
addition means for adding the output signals of the third filter means or the delay means and the
first or second filter means An audio signal processing apparatus characterized in that.
[0013]
(2) An audio signal processing apparatus for converting an incoming analog audio signal into a
digital signal and correcting the converted digital audio signal according to the response
characteristic of a predetermined frequency band of a connected speaker. A first filter means
constituted by an FIR type filter which is supplied with the digital audio signal to operate as a
convolver, and provided on the front side or the rear side of the first filter means to provide a
predetermined digital audio signal A second filter means for limiting the bandwidth of the second
filter means and a signal delayed by the FIR type filter constituting the first filter means, the
signal being lower than the band of the second filter means of the delayed signal Third filter
means for band limiting, the third filter means and the first or second filter means Audio signal
processing apparatus characterized adding means for adding the output signal of, the more
composed.
[0014]
(3) An audio signal processing apparatus according to claim 1 or 2, wherein the second and third
filter means are constituted by IIR type filters.
[0015]
(4) A method of processing an audio signal, which converts an incoming analog audio signal into
a digital signal and corrects the converted digital audio signal according to the response
characteristic of a predetermined frequency band of a connected speaker. A first filter operation
step for performing an FIR filter operation on the converted digital audio signal; and a second
filter operation for limiting a predetermined band of the digital audio signal before or after the
first filter operation step. A filter operation step, a delay processing step for delaying the
converted digital audio signal by substantially the same time as a delay time of the signal by the
first filter operation step, and before or after the delay processing step, Limit the signal of the
band lower than the band obtained by the second filter operation Addition processing step for
adding the filter operation step of 3, the signal obtained in the third filter operation step or the
delay processing step, and the signal obtained in the first or second filter operation step And a
method of processing an audio signal.
[0016]
(5) A method of processing an audio signal, which converts an incoming analog audio signal into
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a digital signal and corrects the converted digital audio signal according to the response
characteristic of a predetermined frequency band of a connected speaker. A first filter operation
step of performing FIR type filter operation on the converted digital audio signal, and a second
filter for limiting a predetermined band of the digital audio signal before or after the first filter
operation processing step When the operation step and the second filter operation step are
performed after the first filter operation step, the second filter operation step may be obtained
before or after the second filter operation step. A third filter operation step of limiting signals in a
band lower than the band; Method of processing an audio signal, characterized in that it
comprises the addition processing step for adding the signal obtained by the filter calculation
step the first or second filter operation step.
[0017]
(6) A method of processing an audio signal according to claim 4 or 5, wherein the second and
third filter operations are performed by IIR type filter operation processing.
[0018]
(7) A recorded medium characterized in that the audio signal processing method according to
claim 4, 5 or 6 is recorded as a processing program.
[0019]
DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of the present
invention will be described by way of a preferred embodiment.
FIG. 1 is a basic block diagram when the audio signal processing device of the present invention
is applied to a speaker.
The speakers have the same configuration for both the left and right channels, and the channel
on one side is omitted.
In the figure, the audio signal processing apparatus comprises an analog-to-digital converter (A /
D) 1 for converting an analog audio signal into a digital signal, a correction filter 20 as a main
part of the present invention described later in detail. Digital-to-analog converter (D / A) 3 for
converting digital signals to analog signals, correction coefficients are calculated beforehand
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such that the sound emitted from the speaker becomes an ideal sound in the anechoic chamber,
and this data is corrected A memory circuit 5 for holding as a coefficient, a control circuit (CPU)
6 for reading out these correction coefficients and supplying the correction coefficients to the
correction filter 20, and an amplifier 4 are schematically configured, and this device is a speaker
SP Is an embodiment of a state of being connected to
[0020]
And, the device applied in this way operates as follows.
An analog audio signal supplied from a sound source (not shown) is input to the analog-to-digital
converter 1, converted into a digital signal, and supplied to the correction filter 20.
At the same time, the correction coefficient obtained in advance is read out from the memory
circuit 5 by the control circuit 6 and supplied to the correction filter 20, and the incoming digital
signal is on the time axis based on these coefficients. Convolution operation is performed.
Thus, the phase, amplitude, etc. are corrected, and the corrected signal is converted back to an
analog signal in the digital / analog converter 3 and amplified by the amplifier 4 and then
corrected to be an ideal sound from the speaker SP. Signal is emitted.
[0021]
The apparatus of this embodiment operates as described above, and in particular, the apparatus
is characterized by the configuration of the correction filter 20, which will be described in detail
with reference to FIG.
This figure is a detailed block diagram of the correction filter 20. This correction filter 20
includes an FIR filter 20-1, an IIR filter 20-2 for high pass filter, an IIR filter 20-5 for low pass
filter, and a delay. And an adder 20-3.
[0022]
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The FIR filter 20-1 includes 199 delay elements d1, d2,... D199 connected in cascade, and
outputs the input digital signal directly or from the delay elements d1, d2,. .., M200, which adds a
predetermined correction coefficient supplied from the memory circuit 5 to the received signal,
and addition means a for adding these output signals. The IIR type filter 20-2 of the multiplier
includes multipliers m1 and m2 provided to multiply the delay elements d1, d2,..., D4 with
coefficients supplied from the memory circuit 5 so as to obtain high-pass filter characteristics. ,
m5 and an adder a.
[0023]
On the other hand, the IIR type filter 20-5 provided on the latter stage side of the delaying
memory holding means 20-4 has a delay element d1, d2,. .., M5 provided to perform
multiplication with the supplied coefficient, and an adder a.
[0024]
One of the incoming signals to the correction filter 20 configured in this way is subjected to a
convolution operation using the correction coefficient supplied from the memory circuit 5
through the CPU 6 by the FIR filter 20-1.
The signal corrected by the convolution operation is cut at a frequency of, for example, 500 Hz
or less, which is lower than a predetermined value, in the IIR filter 20-2 of the next stage.
The IIR filter 20-2 is supplied with a predetermined coefficient from the memory circuit 5 to each
multiplier to operate as a high pass filter, and this output signal is supplied to the adder 20-3 at
the next stage. ing.
[0025]
On the other hand, the signal input to the memory holding circuit 20-4 is delayed by an amount
that is delayed by each delay element in the FIR filter 20-1, and the output signal thereof is sent
to the IIR filter 20-5 in the subsequent stage. Supplied.
In this IIR type filter 20-5, the frequency of 500 Hz or more is cut this time so as to correspond
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to the IIR type filter 20-2 operating as the high pass filter.
[0026]
Then, this output and the output from the IIR filter 20-2 are added in the adder 20-3. As a result,
the drop of the resolution on the low band side as shown in FIG. The same frequency
characteristics as in the case of using a type filter can be obtained.
[0027]
That is, in the correction filter 20 described above, in order to simplify the circuit scale, the
number of taps of the FIR filter 20-1 is reduced to 200 taps, and the drop in resolution on the
low band side caused by this reduction is The expected band is prevented from being corrected
by the FIR filter 20-1.
[0028]
Next, as another embodiment of the correction filter, a correction filter 20A having a
configuration shown in FIG. 4 can be used.
In the configuration of FIG. 5, the memory circuit 20-4 is omitted by sharing the delay elements
of the FIR filter 20-1.
[0029]
Further, although both of the correction filters 20 and 20A described above are configured such
that the IIR filter 20-2 is provided on the latter stage side of the FIR filter 20-1, the present
invention is not limited thereto and provided on the former stage side of the FIR filter 20-1. It
may be configured.
Furthermore, the IIR filter 20-5 in FIG. 2 may be provided on the front side of the memory
holding circuit 20-4.
[0030]
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Next, a predetermined program for performing the signal processing as described above is
recorded on a recording medium such as a CD-ROM, and the recording medium recorded is used
to personalize the disc drive 40 or the network terminal 41. An embodiment in which signal
processing is performed on the side of a computer (hereinafter referred to as a PC or a personal
computer) will be described with reference to FIG.
[0031]
For example, the personal computer 42 used here is MMX (INTEL's P55C extended instruction
set: an instruction set for application-specific instruction set added mainly to efficiently handle
digital signal processing such as image and voice) And a RAM 42a-1 for temporarily storing
program data and PCM data for each sample, and a multiplier and an accumulator for performing
FIR filter operation, high-pass and low-pass filter operation processing, etc. A CPU
(corresponding to a controller) 42a having an arithmetic processing unit 42a-2, a RAM 42b for
temporarily storing PCM data of one frame for data processing, for example, and input via the
disk drive 40 or the network terminal 41 Converter 4 to convert the data And c, and a signal
processing signal and a 42d audio interface for supplying the speaker SP.
[0032]
The network terminal 41 transmits or receives data in packet units using a protocol called TCP /
IP (Transmission Control Protocol / Internet Protocol).
This network is known as the Internet.
A header including an address is added to the packet to specify the host.
[0033]
Next, the operation in the configuration shown in FIG. 5 will be described with reference to the
flowchart shown in FIG.
FIG. 6 shows a case where a program loading instruction (command) is input from a keyboard
(not shown) while the disk on which the signal processing program is recorded is set in the disk
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drive 40.
[0034]
If it starts in this state, it is known at step S1 that the program is loaded (it is determined that the
program is loaded when a command is input).
The program data is read out and supplied to the RAM 42a-1 in the CPU 42a (step S2), and when
the program loading is completed, the program loading flag is set (step S3) and the process is
ended.
[0035]
Next, a play command is input from the keyboard (not shown) with the disk drive 40 loaded with
the disk on which the audio signal to be corrected is recorded, and when it is started in this state,
it is found that it is not a program in step S1 At step S1, the process proceeds to step S4, where,
for example, the TOC area is accessed to read a code representing the type of the disc, and it is
determined that the disc is an audio signal recorded (audio source). If it is, in step 5, data is read
from the data recording area to perform signal correction processing, and the processed data is
set in the audio interface 42d (step S6), and the process returns to step S5 to repeat the above
signal processing. The audio interface 42d D / A converts the received data at a predetermined
sampling cycle to form an analog signal and supplies it to the speaker SP. If "NO" in the step S4,
the performance incapability is displayed (step S7) and the process is ended.
[0036]
Next, a signal processing program to be subjected to the correction processing in step S5
described above will be described in detail with reference to the flowchart of FIG. 7 for the
program corresponding to FIG. First, in step 51, a PCM audio signal is read from the data area
and input into the personal computer. The input PCM audio signal is temporarily input to the
RAM 42b (step S52). Then, the signal which has already been input to the RAM 42b is supplied
to the RAM 42a-1 in the CPU 42a every one sample and delayed for a predetermined time (step
S53). Then, the signal delayed here is supplied to the arithmetic processing unit 42a-2, and the
same filter arithmetic processing as that performed by the low-pass filter in FIG. 2 is performed
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(step S54).
[0037]
On the other hand, the signal for each sample from the RAM 42b is directly supplied to the
arithmetic processing unit 42a-1 (step S55), and the same filter arithmetic processing as that
performed by the FIR filter in FIG. 2 is performed (step S56) . Furthermore, after this, high pass
filter operation processing is performed this time (step S57).
[0038]
Then, in step S58, the calculation result and the low-pass filter calculation result in step S54 are
added (step S58), and finally output as a corrected signal (step S59).
[0039]
In the above processing steps, the processing order of the series of steps S53 and S54 and the
series of steps S55 to S57 may be changed, and in this case, the high-pass filter operation
process may be performed by using an FIR filter. It may be performed before the arithmetic
processing.
[0040]
Next, FIG. 8 is a processing program corresponding to FIG. 4. In this case, the processing step of
step S53 in FIG. 7 is omitted, and is incorporated in a part of the later FIR filter operation
processing. This is a processing program in which the low-pass filter operation process of step
S54 is performed after the FIR filter operation process.
[0041]
Also in this example, the order of the high-pass operation process of step S66 of FIG. 8 and the
low-pass filter operation process of step S65 may be interchanged, or the high-pass operation
process of step S66 is performed before step S63. You may do so.
[0042]
As described above, according to the embodiments of the present invention, the circuit
configuration can be simplified, and good correction of the frequency characteristics can be
performed, and high-fidelity sound quality can be obtained.
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[0043]
According to the present invention, the circuit configuration can be simplified, and good
correction of the frequency characteristics can be performed, and high-fidelity sound quality can
be obtained.
In particular, according to the invention of claim 2, since the signal supplied to the third filter
means is obtained through the FIR type filter, the circuit scale can be further simplified.
[0044]
Brief description of the drawings
[0045]
1 is a block diagram showing a basic configuration of an audio signal processing apparatus
according to an embodiment of the present invention.
[0046]
2 is a first embodiment of a correction filter which is a main component of the present invention.
[0047]
3 is a waveform diagram showing the correction characteristic according to the present
embodiment.
[0048]
4 is a second embodiment of the correction filter which is a main component of the present
invention.
[0049]
5 is a system diagram of a personal computer connected via a disk drive or a network terminal.
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[0050]
Fig. 6 is a control flow in the personal computer.
[0051]
7 is one of the signal processing flow corresponding to FIG. 2 executed in the personal computer.
[0052]
8 is one of the signal processing flow corresponding to FIG. 4 executed in the personal computer.
[0053]
9 is a block diagram showing a basic configuration of a conventional audio signal processing
apparatus.
[0054]
10 is a first conventional example of a conventional correction filter.
[0055]
11 is a second conventional example of the conventional correction filter.
[0056]
12 is a characteristic diagram when the correction filter is configured with 1200 taps.
[0057]
13 is a characteristic diagram when the correction filter is configured by 200 taps.
[0058]
Explanation of sign
[0059]
REFERENCE SIGNS LIST 1 analog to digital converter (A / D) 3 digital to analog converter (D / A)
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4 amplifier 45 memory circuit 56 control circuit (CPU) 20 correction filter 220-1 FIR filter 20-2,
20-5 IIR filter 20-3 Adder 20-4 Memory Holding Circuit SP Speaker a Adder d1, d2, ... d199
Delay element m1, m2, ... m200 Multiplier
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