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JPS5282303

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DESCRIPTION JPS5282303
Description 1, title of the invention
Gain controller
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier
circuit for controlling the relative gain of a digital signal in a circuit that processes multiple
contents, such as a stereo balanced funnel circuit. FIG. 1 shows a conventional balance control
circuit. In the figure, Vl and V2 are stereo (A source, and are a right channel and a left channel,
respectively. The output signal level of the right channel is determined by the division ratio of the
resistance R1 to the resistance R1 by 7 <Lance control volume vR2. The output level of the n1
left channel is also determined by the division #S of the resistance R2 and R4. Ru. Accordingly,
by setting the sliding terminal of the sodium hydroxide 9 □ to ground, the relative power of the
output levels of the right channel and the left channel can be controlled by vRl. In this figure, the
resistance R, the resistance R2 is a source resistance, and in practice it is an ohm to a number. On
the other hand, the volume VR ,, must be fitted to the front panel of the fixture. Therefore,
between TR □ and VRX @, and between R2 and VR □, connection is made with an example seal
Fi, etc. in order to eliminate channel cross talk and ham interference. Since there is EndPage: 1,
the parallel connection is equivalently connected n to the resistance R18, and the source
resistance R, R2 is ohm to the number as described above, so If the high-pass amplitude is
degraded due to the capacity due to the shield line, the frequency characteristic of the bothhands output is not changed depending on vRl. In addition, a # sound is generated from the
slider of the volume VR work, so that the volume needs to be expensive as licking. Furthermore,
the output terminals of both channels are the amplifier of the next stage (11. (? However, it is not
suitable for integration because the condensers C □ and C2 are necessary to filEllt the DC
operating point of the amplifier. On the other hand, since this balance control circuit is produced
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at a relatively low level, it is desirable to integrate the circuit. Therefore, it is necessary to directly
connect between the K input terminal and the output terminal. The present invention ameliorates
the above-mentioned drawbacks in the prior art circuit and is also suitable for integration, by
applying a single DC voltage to the given terminals of the amplifier, and varying gain by one, with
different gain control 1 directions Another object of the present invention is to provide an
amplifier capable of obtaining two or more types of signal outputs. , Furnace, + @ Width unit
according to the present invention, cascode 'r' lti? Without at least two cascode amplification
stages with alternating signal input terminals and without alternating signal input terminals?
And a v-transistor circuit. FIG. 2 is a representative embodiment of the present invention. In the
figure, transistors Ql and Q2. QGと、Q!、Q5. Scale waste, Q8. Q9 Weird I Cascading 4
Consecutively to make up @. Two alternating current signals are supplied to the transistor Q and
Q7, and the outputs are obtained from the collectors of fLQ3 and Q8 respectively. このQ3ト。
The load resistances R4 and R5 of the collector of 8 are each transistor Q respectively. Contact
with the emitter of Q Q □. The transistor QxoQ □ has its base terminal connected to the
collectors of the transistors Q6 and q, and the collector or power supply V. . The resistors R7 and
Re are connected between the collector and the base. トランジスタQ、、、Q6. Q817) The
base terminal is connected to the direct current voltage source v4. The base terminals of the Ql
transistors (, q, 喝 are connected to the self-determination voltage source v5. In the circuit of the
transistors Q □, Q,... Q3, the maximum value of the voltage gain for the signal and V □ Q is
determined by the power of the resistors R4 and R7, fl, the power of the rungs Q2 and Q3 (fif,
JtVC extremely It is well known that the voltage gain can be controlled 1 over a wide range
(about 60 d3). Also, transistor Q7. Q8. The same applies to the amplification stage according
to Q9. The present invention includes transistors'%, Q5. % PI Hi Q work. , Q □ are connected as
described above, and the m11 version will be described next. Now transistor Q, Q4. Assuming
that the bending current of Q7 is equal and the load resistances R, R, R, R7 are equal, for
example, when the voltage of the voltage source v5 rises, the voltage source v4 is constant,%, Q6.
The direct current I / i increases and the collector potentials of the transistors 喝 and Q8 having
a load resistance are in a decreasing direction. However, the increase of the direct current of the
transistor Q5 is equal to the increase of the current (and the decrease of the direct current of
(Q2. Q8 decrease &] '! The r / 'i load resistor R6 is connected to the collectors of Q6 and Q6.
Therefore, Q work. And the change of the base potential of Q, □, that is, the change of the
emitter potential is equal and opposite to the change of the collector potentials of nQ 8 and Q 3
respectively. That is, the weight of the collector potentials of the transistors Q3 and Q8 is offset.
(In the current integrated circuit technology, although the relative value of the V □ characteristic
setting resistance between the transistors is somewhat different, the relative value of the output
within the gain control range of 60 tiB, is within gω7 nkl OmV of the absolute value).
For the alternating current signal υ □ V2 VC, the output signal -V (-indicates a polarity
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inversion) is an increase, or-v2 is a decrease. Also, when the DC voltage source v5 is lower than
M5, the output DC potential becomes constant by the reverse operation to the above. D1] In the
present invention, when the DC voltage source −4; v5, the output signal becomes equal at −V
□ = −v2 and υ,% 1), by the operation of −υ □ and −υ2 / ′ ′ i It will be readily
appreciated that, despite being reversed, its DC potential / 'i does not change. Next, technical
advantages of the above-described differential amplifier circuit of the present invention will be
clarified. In FIG. 2, the load resistance R 4, 'R contact-connected transistors (, Q 8 operate as a
base ground and an AIr width stage with respect to the input @ V Z Z' 2, and each base of these
transistors There are nine connected to the voltage source υ5.b4 which has its own output
impedance. Therefore, transistor Q3. It is well known that the high frequency gain reduction due
to the Q8 mirror effect is improved. According to the transistor, the collector DC potential of the
Q8 is constant, and the change of the gain control potential v6 is extremely small, according to
the A. and EndPage: 2 light, the reverse bias between the collector and the base is constant with
respect to the gain control operation. Become. Therefore, not only the above-mentioned Miller
effect is reduced by the base-grounded amplification stage, but also the change by the gain
control operation is solved. Furthermore, in integrated circuits, as is well known from the
structure, there is a parasitic capacitance between the collector of the NPN transistor and the
substrate. This base P type semiconductor is usually connected to the lowest potential of the
circuit, ie, the ground potential. This parasitic capacitance is a reverse bias capacitance of the PN
junction, and it becomes a transistor's flutter output container to save etc., and changes with the
reverse bias voltage. However, in the present invention, transistor Q3. Since the collector
potential of Q8 is constant, this parasitic capacitance does not change. As described above,
according to the present invention, since the operating point of the transistor constituting the
input signal increasing stage #A becomes constant, the amplitude vs. frequency characteristic of
the output 10 □, −2 does not change due to the gain control operation. . FIG. 4 is an example of
stereo balance control [El [# for the gain control circuit according to the configuration of FIG. A
block representing an amplification stage (corresponding to the circuit shown in FIG. 2 of 31r /
'ifm described in the foregoing and is composed of two signal input terminals, a phase output
terminal, and a balance control voltage source v5. This configuration not only eliminates the
technical defects in the conventional example described with reference to FIG. 1 #: 1, but can be
integrated in a configuration directly connected to the signal processing circuit of the next and
subsequent stages. If control is performed by surface lightning pressure, it is suitable for
integration from 7 to 7 and circuit configuration-F provides many excellent advantages.
The present invention is not limited to the application to a two-channel stereo device, and can be
applied to various circuits of the female.
4. Brief description of the drawings FIG. 1 is a balance control circuit in a conventional stereo
device, FIG. 2 is a circuit of an embodiment of the present invention, and FIG. It is an example. V-
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work, v2-----one exchange human power "', t14. Z15-----One direct current lightning pressure
source. Name of Agent Attorney Yoshiharu Koji Yoshizaki Fig. 1 Fig. 3 EndPage: 3
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