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JPS50143502

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DESCRIPTION JPS50143502
Patented y-y ? ? ? 5 5 ? ? ??? ??? ??? Japan Patent Office ? ? ? ? ? ? JP 50j 43502. 0 Published Japan 50. (L975) 1119 Office serial number Name of the Invention Signal
Synthesis Circuit 1 In a signal synthesis circuit comprising at least a first signal synthesizer and a
second signal synthesizer, the first signal synthesizer Has an amplification element Q1
comprising an input electrode, a ground electrode, and an i-pole, the ground electrode of the
amplification element Q is connected to a constant current circuit, and the output electrode of
the amplification element q1 is a load resistor The second signal combiner is connected to the
power supply voltage supply wiring through the two input signal elements to the ground
electrode and the output electrode, and includes two amplification elements Q! A DC ground
electrode coupling and dynamic signal combining apparatus comprising it Q4, wherein the
ground electrodes of the amplification element QSeQ4 are mutually coupled via two resistors,
and the connection point of the two resistors is fixed. A current circuit is connected, and an
output electrode of the amplification element Q4 is connected to a power supply line via a load
resistor, and the two amplification elements qs. By applying an input signal], a predetermined
coefficient output signal in reverse phase to the running input signal is obtained from the output
electrode of the amplification element q1 to the input electrode of the amplification element q1,
and the one amplification element Qs is obtained. , Q4 by applying an input signal to each of the
input electrodes, and the difference component of each input signal applied to each input
electrode of the amplification element QSeQ6 as the output electrode of the amplification
element Q6. A signal combining circuit characterized by obtaining a combined output signal of
Claims
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal
combining circuit, and more particularly to a signal combining circuit suitable for a matrix
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channel stereo system decoder device. ! In the trix channel stereo decoder, in order to improve
the degree of separation between the reproduction output by the speakers arranged adjacent to
each other, the left and right two channel encode signals are in phase with or in phase with
predetermined ones of them. The inventors of the present application have proposed a method in
which the signals of coefficients are obtained, the signals of l-phase and anti-phase are combined,
and the coefficients of these signals are variable, the details of which are described in Japanese
Patent Application No. No., Japanese Patent Application No. 48-108199 and March 26, 1974,
with all questions from the Acoustical Society of Japan, presented at the SimiCo Communication
Society, the Electronic Communication Technology Committee, and the Electroacoustics Research
Society, and published by the Electronic Communication Society Electro-acoustic Research
Institute Material Data Book No. EA's 2-32 (19 Gu 3-O! S) ?Improvement of Encode F Decoding
Method in 40 h Matrix Reproduction?. In the improved matrix number channel decoder, the left
and right two channel encode signals LT, R? The signal is acid-containing and the four decoder
signals 44iPl, RTl, Lm! l, RBI is taken out, and the numbered speakers arranged on the front left,
front right, rear left and rear right are driven by the four decoded signals to obtain a
reproduction sound field. и Here, f * ? ? t?tr is a control signal, and by controlling the level of
the control signal, to improve the isolation between the four decoded signals Lll, RIFI, I + B1, and
1111 it can. As a first step to specifically construct such an improved matrix number channel
type decoder device, a system block diagram shown in SwJK has been considered by the present
inventors et al. In the system block diagram shown in the figure, 1 channel and 2 are left and
right 8-channel encoded signals respectively. An input terminal to which RT is applied, S is an 8channel encode signal applied to ? input terminal 1 ░ 2, a predetermined coefficient output
signal of RT, a sum component output signal 9.10. 11 is a ? output Terminal, number, 5, 6. 'F']
The obtained coefficient output signal, sum component output signal, difference component
output signal are amplified, and the amplification factor for the output signal is not shown in the
figure, but a predetermined control voltage generator Controlled by rgL @ ?ef, 1g, IJ, 14 ░
EndPage: 3ls is the output terminal of the variable coefficient unit, 1g is the sum component
output of the output signal from the variable coefficient unit Signal combining unit for obtaining
a difference component output signal, 1T, 1B.
19. 20 ti This is an output terminal of the signal synthesis unit 16. On the other hand, when
obtaining a synthetic output signal proportional to the sum of a plurality of analog input signals
conventionally, the electronic circuits on'p 94 to 99 (Corona Corporation, published by the
Institute of Electronics and Communication Engineers of Japan) As shown in FIG. 1, it is general
to use a signal synthesis circuit utilizing an operational amplifier, an input resistor and a negative
feedback resistor. In the figure, reference numerals 45, 46, 4 and 48 denote input resistors
having resistance values "1 * R2mR8mR4", 49 denotes a negative feedback resistor having a
resistance value RF, and 50 denotes an operational amplifier having an inverting input terminal,
A plurality of input terminals Tin, Tin2. A plurality of analog input signal voltages 8t, @x,... When
e4 is applied, a combined output signal voltage и e given by the equation (2) can be obtained from
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the output terminal Tout. In addition, when the value of the impedance of the load connected is
sufficiently large, as shown in FIG. 2, the operational amplifier and the negative feedback resistor
may be omitted if the value of the impedance of the load to be connected is sufficiently thick.
Can. In the figure, 51.52. Reference numeral 3.54 denotes an input resistor having a resistance
value RM, and a plurality of input terminals Tim1. ??????????????? When a
plurality of analog input signal voltages ?1 v ? 2 *... N? are applied to Tinn, the combined
output signal voltage 66 given by the equation (3) is given by the equation (3). It is obtained. "N =
(" 1 + a 2 +--... ... + z ez 1) (n = 4) =-(и, + e, + и, + и 4) No. 131 Therefore, the matrix shown in the
system block diagram of Fig. S When a signal combining circuit such as a channel / channel
stereo decoder device is configured by adopting the above-mentioned resistance matrix method,
it becomes a signal combining circuit as shown in FIG. In the figure, reference numerals 1 and 2
respectively denote left and right 2-channel encoded signal terminals, application terminals
where RT is applied, 21 denotes a phase inverter with an amplification factor set to -1, 22.23, 24.
.25 is a coefficient resistor for a matrix having a resistance value RM, and 26.2 '/, and a fixed
coefficient device with an amplification factor set to -t ":' and pr'e '* +" for 28.29. 1 and output
terminals 4, 5, 6. The coefficient output signal, sum component output signal, and difference
component output signal can be obtained from the filter, that is, fflet-fiLT, -nxr,-(IJT + RT), IIT-RT.
(In the present specification, + means the same phase,-means the opposite phase. Further, in the
same figure, 8, 9, 10, 11 are not shown, but a control voltage r generated by a predetermined
control voltage generator. It is a variable coefficient unit in which the p amplification factor is r ',
t, b, fK variably controlled by t, b, t, respectively], terminals 12, ls. 14, 16 each-(l + r) / Tl-te # (x +
g / / TRT,-(, l + 11) (L + + RT), + (1 + f) (LT-phase inverter, 33, 34, 35, 36.! ??????????
? 40 is a coefficient resistor for a matrix having a resistance value RM, and 41, 42, 45. 44 are
fixed coefficient units each having an amplification factor set to ?1. , 19 and 20, respectively,
multi-channel decoded signals LFI, LBI, RFI according to the equation (1). RBI is obtained.
However, the signal combining circuit such as the matrix 4-channel stereo decoder shown in FIG.
4 has the following problems. (1) In order to obtain a signal of opposite phase, it is necessary
only for the function of phase inversion as in 21i 30 31. 32 in FIG. (2) To combine multiple
signals, a coefficient resistor is required, and the resistance value RM of the coefficient resistor
must be lower than the fixed coefficient input impedance connected to the coefficient resistor.
However, the output impedance of the signal source driving the EndPage: four-factor resistor
must be sufficiently higher. (3) When the sum component output signal and the difference
component output signal are obtained from a plurality of input signals due to the reasons (1) and
(2), the circuit configuration of the signal synthesis circuit is very complicated, The number of
constituent circuits also increases, and as a result, the power consumption also increases, and the
resistance value of the coefficient resistor is also relatively rounded. This type of signal synthesis
circuit is referred to as a monolithic semiconductor integrated circuit device (hereinafter referred
to as a monolithic IC). C), it becomes very difficult due to the relationship between the allowable
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power loss of the monolithic C and the heat dissipation structure of the IC and the integration
density of the IC. ! Since the phase inverter, fixed coefficient unit, variable coefficient unit, etc. are
arranged in a random order, the above-mentioned coefficient resistor, phase inverter, fixed
coefficient unit, variable coefficient unit, etc. can be integrated to integrate such a signal
combining circuit. When these are directly connected, deviations occur in direct current level
temperature dependency, distortion factor characteristics, and frequency characteristics between
the signal combination output voltages at the respective combination output terminals. (5) Since
a coefficient resistor having a relatively high resistance value is connected in series to each signal
path, a large resistance heating wire is generated.
The present invention solves the above-mentioned problems in the signal combining method so
that the same problem does not occur even in, for example, a decoder device of matrix number
channel stereo system, and the purpose thereof is as follows. Like. (1) A separate phase inverter
is not required to obtain a signal of opposite phase. (2) Do not use coefficient resistors. (3) The
deviation of the true current level temperature dependency, the distortion factor characteristic,
and the frequency characteristic between each signal synthesis output voltage is made small. (4)
Reduce power consumption and facilitate monolithic IC. (5) Improve the noise characteristics.
The basic feature of the present invention for achieving the above objects is to use a DC emitter
coupled and dynamic signal synthesizer to obtain a difference signal which is a composite signal
of O in-phase and anti-phase between multiple input signals, In order to obtain another
synthesized output signal, a DC emitter coupled signal synthesizer similar in circuit configuration
to the above-mentioned DC emitter coupled / dynamic signal synthesizer is used, and the
following description will be given with reference to FIG. One real ki will be described in detail. In
the figure, the transistor wrapped with broken line C and the resistor are formed in one silicon
semiconductor pellet by a known method. ??????? ??????????????? (1)
is a lead terminal (bin) of the monolithic IC. First, the left and right 2-channel encode signals LT
and RT are respectively input terminals vRtvLt input coupling capacitors C111y'112. , Input
coupling resistance R111. ?) applied to the bin IQ bin via R112. Also, an encode signal applied
to the bin. The wiring is applied to the base electrodes of the transistors Q1 and Q2 and
QseQatQsvQ6 that constitute the two first signal synthesis circuits and the second signal
synthesis circuit via the wiring in the 17 company monolithic IC. On the other hand, one of the
two first signal synthesizers is a DC emitter-coupled signal synthesizer comprising two
transistors Q1 # Q2t "A comprising a soresole electrode, an emitter electrode and a collector
electrode. And the emitter electrode of the transistor 1; ht Q 1 is a resistor ?1 *! A constant
current circuit Q7tR7 and an AC grounding capacitor "102" are connected to a connection point
of the two resistors R11IL2 connected to each other through t2, and the transistor Q1? The
collector electrodes of Q2 are connected to the power supply voltage supply wiring through load
resistors R101R11, respectively, and the transistors Q, 1. Each pace electrode of Q, 2 is a pie, ass
circuit R201 ░ R202, 010?
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According to the] partial pressure obtained and obtained -1-! ! A DC bias voltage substantially
equal to I # ? is applied. The side stop power supply voltage supply wiring is connected with a
power supply removing resistor "14g '101" to prevent an AC ripple component from the power
and pressure supply source from leaking into the signal path. EndPage: 5 Also, the other of the
two first signal combiners 1 and 2 includes two transistors QSeQ4 each having a pace electrode,
an emitter electrode, and a collector electrode. The emitter electrodes of the transistor Qi # Q4
are mutually integrated via the resistor RSeR4 and connected to the connection point of the two
resistors R1sR4. The R и and AC grounded capacitors 010 M are connected, and the left electrode
of each of the transistors Qie Q4 is commonly connected to each other and connected to the
power supply voltage supply wiring through the common load resistor R12, and the base
electrodes of the transistors Qle Q4 A nearly equal DC bias voltage is applied. Furthermore, the
second signal synthesizer is a DC emitter coupled and dynamic signal synthesizer comprising two
transistors QSeQ4 each having a base electrode and an emitter electrode / collector electrode,
The emitter electrodes of QSe Q4 are coupled to one another via two resistors R8 m ? ? 4
respectively, and to the connection point of the two resistors RIe R &, the company's house
current circuit Q9 e! t9 is connected, the collector electrode of the transistor q6 is connected to
the power supply voltage supply line through the load resistor R13, and substantially equal DC
bias voltages are applied to the pace electrodes of the transistors QSeJ. In the above two first
signal synthesizers and the second signal synthesizer, the resistance ratio 11 is set as shown in
equation (4). (However, Rs = ?aeRs = Ra) In the circuit configuration which is red, one of the two
signal combiners performs an emitter grounded signal to the alternating current input signal by
the action of the capacitor for alternating current grounding (1). When applied: a'1. A signal
voltage having a voltage amplitude value of / R1 times or relatively 1 / rr-te is obtained from the
transistor q, 1; rector electrode, and the right encoding of the voltage amplitude value RT to the
pace electrode of the transistor q2 is performed. When the signal R is applied, the signal voltage
having the voltage amplitude value of "ll / R, double, that is, relatively -Ax. The collector electrode
of the
In addition, the capacitor for AC grounding (1) (more than the function of II, the other of the two
signal synthesizers also operates as a grounded resistor amplification circuit for the AC input
signal, and each of the transistors Q4 * QH When the left and right encoded signals of voltage
amplitude value L and R respectively are applied to the base electrode, and RT is applied, the
voltage amplitude of R / R is multiplied by R1, ie, the voltage amplitude of -R relatively. A signal
voltage having a value is obtained from the collector electrode of the F transistor ths, R, 2 / R,
(gR,. [S) times or relatively-L! The signal voltage having the voltage amplitude value of (V) is
obtained, and the collector electrodes of the transistors Q, Q4 are mutually coupled to each other
as a result; A signal voltage having a voltage amplitude value is obtained. Further, the abovementioned twentieth signal synthesizer operates as an emitter coupling difference 1 amplifier
circuit, and voltage amplitude values ?! . When the left and right encode signals of RT are
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applied, a differential signal voltage having a voltage amplitude value of It1s / (R5 + R4) times or
relative K (L Qi RT) is obtained from the collector electrode of the transistor Q6. One transistor
Qll, Q11. ???? ????????? A network consisting of Qto and Qt constitutes four
variable coefficient units, that is, variable gain amplifier circuits. One of the variable gain
amplifier circuits is PliP) 7, Di-stater Q1o, and IIPI), I / I; h4. QIS further resistance RIS, R1? , R20,
R1 (11 # R1g Ig, capacitor 0101 i, variable impedance Rr,? !! ????????????????
? tr constitutes a negative feedback circuit and controls the impedance of the variable
impedance Rr, and has a feedback amount C path function of the negative feedback amplification
circuit. Therefore, EndPage consisting of the amplification transistors Qto and Q1s: The output of
the first variable gain amplification circuit! An amplified signal of + (1 + r) Ari??LT, an
amplified signal of (x + g / i ? ? R?), an output of the second variable gain amplifying circuit
consisting of the amplifying transistor ?L11pQ17?, an amplifying transistor J2. An amplified
signal of the output i ? + (1 + b) * (LT + R te) of the third variable gain amplifier circuit
consisting of Q1e. The output of the fourth variable gain amplification circuit consisting of the
amplification transistors Q <s, Qxt, see (1 + f) и (LT?R? Can be obtained respectively.
On the other hand, the network consisting of (Tunzista Qzx, Q * s, Qxa, Qbzse и ? ?-pQb2 @
gQk29 * Q, & @ * ? ? four eQsM is a third signal synthesizer, a fourth signal synthesizer, a
fourth signal synthesizer, The sixth signal synthesizer and the sixth signal synthesizer are
configured. In addition, the third signal synthesizer includes two transistors q. A direct current
emitter coupled and dynamic signal synthesizer comprising QCg, wherein the emitter electrode
of the transistor Qx * eQ1s has resistance! ???? The company house current circuit (Lie, Rlg
is connected to the connection point of the two resistors R17 * ? ? fi @) mutually connected via
I, and the collector electrode of the transistor Qvt is connected to the power supply voltage
supply wiring via the load resistor R41. It is connected to the. The fourth signal combiner then
consists of two transistors Q! A direct current emitter metal-plated signal synthesizer comprising
4 ░ Qzs, wherein the emitter electrodes of the transistors Qva and Qvs are coupled to each other
via the resistor R29 and the milk 1, respectively, and the two resistors Rat and RsoO A constant
current circuit cL [1Rsa and an AC grounding capacitor 0104 are connected to the connection
point, and the collector electrode of each of the transistors q24 ░ Qvs is coupled to each other
through a common load resistor R4 to the power supply voltage supply line #. ! I have been
followed. The sixth g1 combiner is a DC-coupled differential shadow signal combiner comprising
two transistors Q * a and Kty, and the transistor Qv6. Q * y's Ivy electrodes have resistance R11,
respectively. The constant current circuit q1 is connected to each other via tlfi, and the
connection point of the two resistors RI1 and R1ff1. R17 is connected, and the collector electrode
of the transistor Qly is connected to the power supply line via a load resistor "4N". Furthermore,
the sixth signal synthesizer is also a direct current emitter coupled and dynamic signal
synthesizer constituted by two transistors Q2m and QtttL, wherein the emitter electrode of the
transistor q2 ? ?m9 is respectively connected via the resistors RHH and R84. The constant
current circuits Qss, Rs и are connected to the connection point of the two resistors Rig and R84,
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and the collector electrode of the transistor QCs is connected to the power supply line via the
load resistor R44. . The output signals of the third, first, fifth and sixth signal synthesizers are
respectively supplied to four 4-channel decode signal output terminals 0, 0,. ?, pulled out of O to
the outside of monolift xC. Further, the pace electrode of the transistor Q22eQ2? constituting
the S-th signal synthesizer is an amplified signal of + (gate + t) j ? ViR1 from the abovementioned second variable gain amplifier circuit, the fourth variable gain amplifier circuit). = (1-)f) (L Chi R?
) Is applied to the pace electrodes of the transistors q24 ░ QCs constituting the fourth signal
combiner, respectively-(4 + f) и (L Q from the fourth variable gain amplifier circuit). Transistors Q
* a, Qvy that constitute the sixth signal synthesizer to which the amplification signal of j'l '), the
first variable gain increase 1, and + (1 + r), iby of the circuit are applied. The pace electrodes of
the first and second variable gain amplification circuits respectively have + (x + r) Jb! Amplified
signal, third variable gain tie. The gain signal of + (1 + t) ? ? (one bit ?R) of the gain amplifier
circuit is applied, and the pace electrodes of the transistors Qts and Qt * constituting the sixth
signal synthesizer are respectively + (1 + b)-? Of 3 variable gain amplifier circuits? L D +1? And
the second variable gain amplifier circuit]] is applied to the + (l + z) 5x signal. Further, in the fifth,
fourth, sixth and sixth signal synthesizers, resistance ratio expansion is set as shown in equation
(5). = 1: x: z: 1 (? (where R 2 * x Rss)) In such a circuit configuration, the same circuit as the
above-described three third EndPage: 71 signal synthesizers and the second signal synthesizer By
the operation, 4 th channel deco first channel decode signals are obtained. ? ? Knee (1 + fX "Qi
RT)-(x + t) JExr @: + o + f) (IJy-R1)-(1 + r), / TLT @:-(x + b) (L te + R te) + '(: L + r), / TL Therefore,
one decode signal LIFI, R1, RBI, LB 'given in the equation (1) has a phase opposite to that of one
decode signal given by equation (1). Channel-decoded signal output terminals (each obtained
from ?t @ t @ e @). The values of the resistors, capacitors and power supply voltages used in the
circuit shown in FIG. 6 are shown in the following table. Table R ,, R, ... Fist ... ... Fist ... 5.18 to
?R1, R4 ... b ... ... ... ... S, 6m KQR $, IR,
ииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииии 0 0 ) To
65 ?R1, ................. 2.0 K fl R12 ..... OK ? R 1 i иииииииииииииииииииииииииииииииииии, @ 5, 5 ? R1 s, Rt4. Rty, R1 @
Fist * 5es3 2 46 KQR1y, Rtl, Rzs, Rts * s ** e 8.5 KQR ffi11.
R12, R24, R24 ииииии 0.5 to ? R27, J6 see **** e * e * e5, 0 K fl R2? , R 1 b @ ? иииииии 5. OX ? R 51,
R 52 mm mm mm mm meam 5.0 KQR 5 N, 4 to R 1. OK ? Rss, Hs6. Rsy, Rs * m ** m * 0,5 to
?R89 иииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииииии и и 19, 51 ? R41 и и и и и и и и и и и 1 и 10. OX ? R 42 @
иииииииииииииииииииииииииииииииииииии 10. OK ? R44 ииииииииииииииииииииииииииииии 10, 10 Kn R 1 @ 1, R 1 @ 1, R 1111, R 1114 ? 1
B, 0 KQR 1111 i, R 104, R 107, R 111 @ @ 1, 510 R 111, R 112 e * eees ** ** e91.0
ICQR11'e'114 ** ss * s * ss * egg, 0 K fl R2 1 ......... 11 ... 15. OX ? R 202
иииииииииииииииииииииииииииииииииииииииииииииииииии 1oop? 01e! , 01 es, 01 o 4 s * ee ** 4 ?m 0101 i, 011) 4, 01 G 7, 01 @
@ lll 0 JIIIP 011 1.0 11! ииииииииииииииииииииии 1. ...... It is a value of ░ resistance formed by impurity
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diffusion in IO. However, the present invention can also be configured by connecting discrete
circuit elements as described above, since such monolithic xat1cO is not limited. In the t- # one
embodiment, impedance / control of the variable impedance ?rpItAeRbeRf? is actually
controlled to the spot reservation by the voltage applied to the gate electrode of the drain-source
conductance of the r channel MOa type field effect transistor. Depends on the method of Further,
according to the configuration and the embodiment of the present invention, the initial object can
be achieved for the following reasons. (1) Rounding with phase inversion between the base
electrode and the collector electrode of each direct current emitter coupled signal synthesizer
adopted in the present invention, and no separate phase inverter is necessary.
(2) The relative voltage amplitude value ratio between the DC emitter coupled signal
synthesizers, that is, the coefficient of the signal can be set by the resistance ratio between the
emitter resistance of each DC emitter coupled signal synthesizer and the load resistance, In the
past, coefficient resistors that were only used to set fixed coefficients are no longer needed. (3) A
circuit similar to that of the circuit type, in which the DC coupled shadow signal combiner is
arranged in the signal path from each input terminal of the signal combining circuit to each
signal output terminal, It was possible to reduce the deviation of DC level temperature
dependency, distortion characteristic and frequency characteristic to EndPage: 8. (4) Since the
circuit configuration has been simplified, for example, because the NIJMA MM resistor i and the
coefficient resistor can be omitted, power consumption is reduced and the coefficient resistor
with a relatively high resistance value is not required. Monolithic integrated circuit became easy.
(5) The thermal noise level can be lowered and the noise characteristic can be improved because
the coefficient resistors with high resistance value are not connected in series to each signal
path. Further, the present invention is not limited to the above-described embodiment, and
various embodiments can be adopted. For example, the present invention is not limited to a
direct teleo type decoder using an amplification element such as a MO8 field effect transistor
other than a DC power converter coupled signal combining device transistor or a junction type
field effect transistor, and an independent multi-input signal. The present invention can be
applied to all cases where signals of the sum of the signals of the signal and the signal of the
difference are obtained until signals of the same phase or 'in reverse phase' are obtained. For
example, -R ? ?! In order to obtain the signal of (1), the signal of R is applied at the pace of Q6
and the signal is not applied to the base of q5. For example, FIG. 6 is an embodiment of the
present invention for obtaining a composite signal consisting of independent multiple input
signals tBtCtD and Rum-B-0-D, and FIG. 1 is an independent multiple input signal (--B). An
embodiment for obtaining a combined signal of -B and -2 will be shown.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a conventional signal
combining circuit, and FIG. 3 is a system block diagram of a matrix number channel system
decoder device according to the present invention. Sixth. FIG. 6 is a circuit diagram of a signal
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combiner for a matrix No. channel decoder according to an embodiment of the present invention,
and FIG. 6 is a circuit diagram of a signal acidizer according to another embodiment of the
present invention. q и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и
и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и и EndPage: list of documents in the endpage 9
Figure (3) One proxy letter Inventors other than the above, patent applicants or representative
inventor Hira Kuchikora Saku representative Kosaku Kikuchi EndPage: ??
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