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JPS50145304

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DESCRIPTION JPS50145304
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a connection diagram showing an example of a
main part of a logic circuit of a four-channel stereo system according to the present invention,
and FIG. 2 is a waveform diagram for explaining its operation. 1 is an input terminal of the logic
output SS, 3 is a transmission line, 4 is a diode, 5 is a transistor, 7 is a switching element, SP is a
control signal, SO is an output signal, and a and b are discharge paths. Fig. 1-9-Japanese Utility
Model Application Publication No. 50-145304 (2) Fig. 2 Wheel C-F go I1, 1 :: Bird: V-10-
DETAILED DESCRIPTION OF THE INVENTION A main channel 1 # i, for example, a 4-channel
stereo device K according to the sQ system, relates to a preferred n thick circuit. 4 channel 2
channel stereo device tK / h for matrix system such as 8Q method ・ Signal for m12 channel is
supplied to the logic circuit to 4 signal 2 73 4 channel 2 の 1 4 73 4 1) 'K, 1 at its output,
controls the level of the 4 channel demodulated signal obtained from the decoder, and there is
some improvement in separation by oxidizing. In this case, when the output of the logic circuit is
used for the level control signal described above, 1) The logic output is always used with a
predetermined time constant. That is, in the case where the time constant is perfect, since the
level 檀 of the demodulated signal separately provided by this logic output becomes great, the
sound 1 flickers and becomes black. On the contrary, when the time constant is large h and the
fluctuation of o can be reduced, the followability of the reproduced sound field to the change of
the original sound field is deteriorated. For example, if there is a logic output that controls your
own channel when there is a dominant signal in another channel and there is a dominant 1C
issue in your channel immediately after t, you can The above logic output needs to be eliminated
at Ig. However, this logic output has a predetermined time constant added to it. E Dust KC! The
jitter output can not be made zero, and the followability deteriorates accordingly. Of course, a
feeling of jealousy! lJjh-Table τ 'is also laid. Therefore, in the prior art, it is possible to improve
the following ability to the fluctuation of the original sound field and to stabilize the sound field.
1 It's a shame. In the following, the drawing will be blurred to explain the logic times Ts
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according to the main body IIK, but in the gi diagram, α · indicates the main part of this circuit
as a whole. 11) is a signal input terminal to which a logic output 88 obtained based on the
combined signal property of two channels, .chi., As described above is supplied. · 2) is an output
1 child, to the I & final output 1 obtained thereby, although not shown, 4 is supplied to a gain
control amplifier a supplied with each demodulated signal LF / ~ RB / 4 It is Among them, 13)
shows a transmission path of the logic output 8B. In the present invention, for the transmission
43+, the diodes 14) for 11 streams are hardened in one row, and a condenser +51 for parallel
placement is connected in parallel to the transmission line 13). . Reference numeral 161 denotes
a discharge path type cutting resistance provided as necessary.
Therefore, if the logic output Ss is supplied (3) 3 \, then the capacitor 5) is photoelectrically
supplied through the diode (4), and if the logic output S8 can not be supplied WR, then from that
point on -M1 mm! れる。 In the present invention, the following configuration is described on
such a 1 gI 洛 configuration. In other words, both 4Vc of the diode '4) are connected to a
switching element such as a transistor or FET, 7), and the switching element (7) is turned on by a
switching signal [@ # symbol] SP supplied thereto. The photoelectric charge of the capacitor 5) is
forced to pass through the switching element (7) and instantaneously. In this example, the
amplification rate is set to IK7, and the switching signal 8P is supplied and supplied via the
frequency converter 8). In addition, it is a dangerous case when using FIT as the switching
element +71. The output of the calculation scope turtle 8) is supplied to the gate of the FIT 171.
19) is a terminal of the switching signal Sp. Although this logic circuit III is different depending
on one 4 channel (4)-rl + channel stereo device, as described above, 4 m of demodulation @ LP
LP / ~ about n / while 2 are not Four are provided. Next, the fluctuation of the unbelievable logic
@ @ IG is shown at @ 21 and the nine waveform diagrams are wiped and described. First, the
waveform of the logic output 83 supplied to the input terminal Ill is shown in a JIR diagram AK.
Slightly, this logic output 8B is, for example, time point 1. Hereinafter, a channel denoted by logic
Fgl @ Ill [I # indicated by @ 111 will be the channel (your channel. Then, the demodulation signal
is, for example, /. ) Suppose that it is a logic output that indicates that there is a signal of K1 and
so on, and accordingly that there is an import channel [channel other than one's own channel]
<No. For this reason, the 41 ml signal LF / of the own channel is emitted only at the time at, ~ Ii
country. In addition, this four chic output does not completely fall from 11 "(level ■) to O 18 to
@ O @. This means that if there is no 1 夷 4 signal in each channel 1-1 and the level C that forms
a false channel, the level e) as shown in the figure 15). Each indicates the presence of a signal.
Therefore, when the logic output 8s is supplied, the capacitor 15) continues to be
photoelectrically supplied between the temples 4b to 12 and when it reaches time t, the
photoelectric charge of the capacitor 15) is discharged through the resistor 6).
In FIG. 2C, -a, the discharge time constant of the capacitor 15) and the resistor 18) is 7i, and the
level of # filF □ is decreased. By the way, after time t 示 す, it indicates that there is a Nensho
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number with one level that is each channel 114 VC お い, but the dominant signal is I t from the
Imaike channel! After that, for example, at time point 18, when one's own channel Vc '41 group 1
is inclined, it emits a signal which is dominant at one's own site, that is, the w4 # signal Sc or the
logic circuit. Because of this, time t. Then, based on the 1114 signal 8CK, the switching signal SP
is generated, and the j'ET + 71 is turned on. Therefore, the light area @ load of the h9 capacitor
5) continues to be discharged through the resistor (6) up to now and becomes (I) & (C) sharply
discharged through the FET 171 when the FET 171 is turned on. (6) 1 \ p solid, the discharge
path shifts from 1 to b at the point of time t. The level of the fruit, the connection point P, and the
level of the output signal So obtained at the drop output terminal (2) are 41 °, and the input
changes from the level change determined by the discharge time constant. It changes to a level to
a symbol, and then holds this input level. For example, if it is the input level 41e at time t, the
level of the output @lso is also e. The waveform of the Kameyama force signal 8o obtained in this
manner is shown in FIG. 2C. Here, the output signal S obtained at that time if the light @@ tf of
the capacitor 5) is not discharged in a controlled manner by the FET 171 as a switching element.
The falling waveform of this is a string of one point 櫃 @ (curve 11) shown by No. 2〇, so in
comparison with such a conventional one, in the four cases according to the present invention,
there is a dominant signal in one's own channel噴出 池 池 池 チ ャ ン ネ ル チ ャ ン ネ ル 池 池
池池池池池池池池池wwwwwwwwwwwwwwwwwwwwwwwwwwwwwww
w w w w w w w. First of all, the level of 4A @ LF1 changes as shown in the second plan (7), and
the follow-up performance of the reproduction field against the original sound field becomes
excellent. Incidentally, in the case where there is no symbolic change of the sound field-4, Control
1 8p occurs, and the same control operation as described above is performed. However, even in
the case of this control-operation, the level change is h0 which does not change to the pole 4 like
the real friction Jb (after a while t, and so on), so that the sound 1 dormant 1! ! はない。 As
described above, in the present invention, as shown in FIG. 1, the switching element 17) is
provided in parallel with the diode 14) in order to discharge the charging electric field of the
condenser 13) to one sheet.
If this is done, it is possible to change the falling time constant of the output signal So by
changing the 1lIl # saving issue 8cK substantially, the falling time is less than <-C, and the
reproduced sound for the Toho field It is possible to improve the followability to the field. Of
course, even when the change in the original sound field is gradual, the level change is not a
symbol, so the sound lingers are gone, and this nineteenth, 1152! Simply do more of the
conventional shortcomings! @, Have a good quality logic-lie that can be taken together. And in
the above mentioned 7tI + I jitter circuit, the excess (8)! If the time is four, the level to the output
signal or the input level of the logic output 8B disperses, so insert a circuit as shown in the
figure, 4 and transmit waveform etc. except in the overstage. Because it is a seed stone, it is used
to embody accurate transmission. f. 9 This is because it is intended to conduct accurate level
control to the output signal. By the way, in the above-described embodiment, the N4 # signal 8ce
is directly supplied to the gate of F] 1 TI 71 without providing the operation amplification s 1 g +
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1, and in the case of t, the logic output 88 regardless of A. This FET + 71 may be switched. The
control action is extremely reliable because the switching can be performed only by the arrival of
the signal 411c as in this example. In the above-mentioned embodiment, the resistance .8)
provided in the transmission 413) can be processed if it is provided according to the required IK,
and in the case of 1 / h, the falling wave P4 of the output signal 8 is a broken line It becomes like
a wreck. In addition, 4 channels + 91 large applicable to the body a circuit; 1 Tele 411 @ is not a
friend 8Q system as described above, but it may be a 4 channel stereo system with a matrix
system such as RM system. A simple description of siI: Fig. 1 @ is a connection diagram showing
an example of the main part of the 璽 -jitter 14 of the 4-channel stereo device according to the
present invention, and Fig. 2 is a waveform representing them. 111 is an input terminal of jitter
output 88, 13 is a transmission line, (4) is a diode, 1 luster is a transistor, (7) is a switching
element, SP is an output signal, 8o is an output signal, and is a discharge It is a road. Utility
model registration disappointing person Sony Inc. 1 Muku 4 I & 'α · Figure 1 East J 4 sentence ll
2 〆 J Figure 2 ring WIB-21 Il-1 □: j j, V0-clove] to: j1 : LP '·]-.
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