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JPS55134516

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DESCRIPTION JPS55134516
Description 1, title of the invention
イコライザアンプ
3. Detailed Description of the Invention The present invention relates to a C11, type equalizer
amplifier. When playing back a record, when using an electromagnetic cartridge in which the
output voltage is proportional to the speed of the needle tip, the frequency characteristic
decreases as the output voltage increases as the frequency increases. Flat frequency
characteristics are obtained through the equalizer circuit having the characteristics, that is, the
RIAA (US Record Industry Association) characteristics shown in FIG. FIG. 2 shows a circuit
diagram of an example of a conventional CR, type equalizer amplifier. In the figure, 1 is a filter
consisting of resistors R + and R2 and capacitors C1 and C2, and has fi and RIAA characteristics.
Flat amplifiers 2 and 3 are provided before and after the filter 1 to compensate for loss due to
attenuation in the filter 1. In such an equalizer amplifier, it is necessary to obtain a large
allowable input in the high region by the input signal 2-EndPage: 1 becoming a dog in the high
region, and in order to increase the allowable input level in the high region, The use of the flat
amplifier 2 requires the power supply voltage to be very high, which causes a disadvantage that
a considerable problem occurs in circuit design. An object of the present invention is to provide a
CR-type equalizer amplifier with a large allowable input level particularly in the high frequency
band. Hereinafter, the present invention will be described in detail with reference to the
drawings. FIG. 3 is a circuit diagram of an embodiment of a CR equalizer amplifier according to
the present invention. In the figure, the transistor Q + cooperates with the emitter resistor Ro to
form the m stage 12. The base of the transistor Q1 is connected to the input terminal IN to
supply an audio signal. The collector of the transistor Q1, in this case the output terminal of the
amplification stage, has a constant attenuation for frequency signals less than this co-frequency 1
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1
/ T, less than 1 / T1 and less than frequency l / T2. Has an amount of attenuation that increases
at a constant rate relative to the logarithmic increase in frequency. In cooperation with the
transistor Q2 and the emitter resistor R3, an emitter 7.10 stage 13 is formed. The base of the
transistor Q2 is connected to the output end of the load circuit 1a, and the input end of the
filtering circuit 1z having a predetermined frequency characteristic is connected to the emitter.
The filtering circuit h is a filter comprising a resistor R4 and a capacitor C2, and has a fixed
attenuation for frequency signals less than 1 / T2, and for frequency signals greater than 1 / T2.
It has an amount of attenuation that increases at a constant rate with logarithmic increase in
frequency.
In the equalizer amplifier according to the present invention described above, the overall
response characteristics of the amplifier stage 12 and the load circuit 1a are represented by the
solid line a in FIG. 4, and the overall response characteristics of the emitter follower stage 13 and
the filter circuit 1h are indicated by dashed dotted lines. Is represented. Therefore, the overall
response characteristic of the equalizer amplifier due to the non-emission 4-light becomes RIAA
percentage 7. As described above, the equalizer amplifier according to the present invention is
composed of cascaded amplification stages and emitter follower stages, and a load circuit having
a predetermined frequency characteristic is connected as a load of the amplification element
constituting the amplification stages. Depending on the characteristics, it is possible to configure
the equalizer circuit of the low band part directly. Therefore, the present invention is
characterized in that the allowable input of the high frequency band can be increased particularly
as compared with the equalizer circuit using the flat amplifier as in the prior art, and the
equalizer circuit of the high frequency band portion is formed of the emitter follower stage, The
load is not concentrated only in the amplification stage, and therefore the occurrence of
distortion at high frequencies such as raw, v, j, can be prevented by the concentration of load.
Ground 5 °, 1 °. ヶ□1oいい、。 In the second embodiment circuit, the transistors Qll, Q12.
The resistor Ro-R14 and the diodes DI and D2 constitute a pnno input stage of amplification
factor 1, and the transistor Q13. The Q5 and resistances RI5 to RI8 constitute a bush-5 = pull
amplification stage. Then, a circuit 1σ consisting of a resistor 1 (· l, R2 and a capacitor CI is a
transistor Q + 3. It operates as a load of Q10, this load and resistance RI5. The low range
equalizer is configured by the ratio to RI6. トランジスタQ+5. Q10 and resistor R + 9. R and
20 constitute a Pnosch-Plue mino ter follower stage, and a resistor R3 and a capacitor C2
constitute a filtering circuit which equalizes high frequencies. In this embodiment, an amplifier 4
is also connected to the output side. る。 The characteristics of the load circuit 1σ and the
filtering circuit 1 in FIG. 5 are the same as those in FIG. The operation of the circuit of FIG. 5 is
the same as that of the third circuit except for the operation of the circuit of FIG. As apparent
from the above description, since the allowable input level required for each amplification stage
of the equalizer amplifier according to the present invention may be smaller than that of the
conventional one, design conditions are facilitated, and thus cost can be reduced. It is
6−EndPage:
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2
4. Brief description of the drawings. FIG. 1 is a graph showing RIAA characteristics, FIG. 2 is a
circuit diagram showing a conventional example, FIG. 3 is a circuit diagram showing an
embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram showing another
embodiment of the present invention. Explanation of Signs of Main Parts Q1: Transistor Q2
configuring amplification stage Transistor 1σ configuring emitter follower stage Load circuit 1 h
Filter circuit Q13. Q14 · · · Transistor Q + s constituting an amplification stage, Q + 6 transistor
constituting an emitter follower stage \, "7-Fig. 1 Fig. 7 L" EndPage: 3
07-05-2019
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