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Programming Language Interface (PLI)

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Programming Language
Interface (PLI)
Pedram A. Riahi
Test Seminar
August 11th, 2004
Contents
PLI History
яБм Verilog PLI Overview
яБм Verilog VPI Routines
яБм Cadence VPI Environment
яБм Mentor Graphics VPI
Environment
яБм References
яБм
Aug. 11th, 2004
Test Seminar
2
PLI History
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1985 - The PLI was developed by Gateway
Design Automation as part of the
proprietary Verilog-XL simulator
1990 - The PLI standard was released to
the public domain along with the Verilog
HDL and Verilog SDF standards by
Cadence Design System
1990 - Open Verilog International (OVI)
тАЬownedтАЭ the Verilog HDL, the OVI version
of the PLI was called PLI 1.0
1993 - OVI released PLI 2.0, a completely
new interface, intended to replace PLI 1.0
1993 - OVI submitted Verilog to the IEEE
for standardization
1995 -The IEEE-1364-1995 Verilog PLI
standard was released
2001 -The IEEE-1364-2001 Verilog HDL &
PLI standard updated with many new
language features many new language
features
Aug. 11th, 2004
Test Seminar
3
Verilog PLI Overview
IEEE Std Verilog HDL LRM
Clauses 20-27 and
Appendices E-G
яБм Verilog PLI Generations:
яБм
Task/Function Routines
(TF Routines, тАЬtf_тАЭ)
яБм Access Routines
(ACC Routines, тАЬacc_тАЭ)
яБм Verilog Procedural Interface
Routines
(VPI Routines, тАЬvpi_тАЭ)
яБм
Aug. 11th, 2004
Test Seminar
4
Verilog PLI Overview
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User-Defined System Tasks and
Functions
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Names ($)
Types
Overriding
User-Supplied PLI Applications
Arguments
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Interface Mechanism
яБм Include Files
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acc_user.h
veriuser.h
vpi_user.h
Memory Restriction
Aug. 11th, 2004
Test Seminar
5
Verilog VPI Routines
яБм
System Tasks and Functions
vpi_register_systf()
яБм vlog_startup_routines[]
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Interface
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Call-backs
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vpi_register_cb()
Access to HDL and Simulation
Objects
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module m, wire w: m1.w, m2.w
Error Handling
яБм Function Availability
яБм Traversing Expressions
яБм
Aug. 11th, 2004
Test Seminar
6
Verilog VPI Routines
яБм
Call-backs
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Simulation Call-backs
Simulation Action and Features
яБм Simulation Times
яБм Simulation Events
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Statement Call-backs
яБм Removing Call-backs
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Time Queue
Aug. 11th, 2004
Test Seminar
7
Verilog VPI Routines
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Diagram Key for Objects and Classes
Object Definition
Object Reference
Class Definition
Class Reference
Unnamed Class
Aug. 11th, 2004
Test Seminar
8
Verilog VPI Routines
яБм
Diagram Key for Traversing Relationships
obj_h = vpi_handle (obj, ref_h);
obj_h = vpi_handle (Tag, ref_h);
obj_h = vpi_handle (obj, NULL);
Aug. 11th, 2004
Test Seminar
9
Verilog VPI Routines
яБм
Diagram Key for Traversing Relationships
itr = vpi_iterate (obj, ref_h);
while (obj_h = vpi_scan (itr))
{ process obj_h}
itr = vpi_iterate (Tag, ref_h);
while (obj_h = vpi_scan (itr))
{ process obj_h}
itr = vpi_iterate (obj, NULL);
while (obj_h = vpi_scan (itr))
{ process obj_h}
Aug. 11th, 2004
Test Seminar
10
Verilog VPI Routines
яБм
Diagram Key for Accessing Properties
PLI_INT32 vect_flag =
vpi_get (vpiVector, obj_h);
PLI_INT32 size =
vpi_get (vpiSize, obj_h);
PLI_INT8 *name =
vpi_get_str (vpiName, obj_h);
Identified Routines
Aug. 11th, 2004
Test Seminar
11
Verilog VPI Routines
яБм
Object Relationships and
Properties
modH = vpi_handle (vpiModule, netH);
Aug. 11th, 2004
Test Seminar
12
Verilog VPI Routines
яБм
Object Relationships and
Properties
vpiHandle net, mod;
net = vpiHandle_by_name (top.m1.w, NULL);
mod = vpi_handle (vpiModule, net);
vpi_handle (vpiExpr, partH);
Aug. 11th, 2004
Test Seminar
13
Verilog VPI Routines
яБм
Object Relationships and
Properties
PLI_BYTE8 *name =
vpi_get_str (vpiFullName, mod);
vpiHandle itr;
itr = vpi_iterate(vpiNet, mod);
while (net = vpi_scan (itr))
vpi_printf(тАШтАШ%s\nтАЩтАЩ,
vpi_get_str (vpiFullName, net));
Aug. 11th, 2004
Test Seminar
14
Verilog VPI Routines
яБм
Object Relationships and
Properties
void traverseExpr (vpiHandle expr) {
vpiHandle subExprI, subExprH;
switch (vpi_get (vpiExpr, expr)) {
case vpiOperation:
subExprI = vpi_iterate (vpiOperand,
expr);
if (subExprI)
while (subExprH =
vpi_scan (subExprI))
traverseExpr (subExprH);
default: break; }}
Aug. 11th, 2004
Test Seminar
15
Verilog VPI Routines
яБм
Object Relationships and
Properties
яБм Type Properties
-> type
int: vpiType
vpi_get (vpiType, H);
vpi_get_str (vpiType, H);
яБм File and
-> location
int: vpiLineNo
str: vpiFile
яБм
Line Properties
Delays and Values
Aug. 11th, 2004
Test Seminar
16
Verilog VPI Routines
яБм
VPI Routines for Simulation
Related Call-backs
vpi_register_cb():
Register a simulation-related
call-back
яБм vpi_remove_cb():
Remove a simulation-related
call-back
яБм vpi_get_cb_info():
Get information about a
simulation-related call-back
яБм
Aug. 11th, 2004
Test Seminar
17
Verilog VPI Routines
яБм
VPI Routines for System
Task/Function Call-backs
vpi_register_systf():
Register a system task/function
call-back
яБм vpi_get_systf_info():
Get information about a system
task/function call-back
яБм
Aug. 11th, 2004
Test Seminar
18
Verilog VPI Routines
яБм
VPI Routines for Traversing
Verilog HDL Hierarchy
vpi_handle():
Obtain a handle for an object
with a one-to-one relationship
яБм vpi_iterate(), vpi_scan():
Obtain handles for objects in a
one-to-many relationship
яБм vpi_handle_multi():
Obtain a handle for an object in
a many-to-one relationship
яБм
Aug. 11th, 2004
Test Seminar
19
Verilog VPI Routines
яБм
VPI Routines for Accessing
Properties of Objects
vpi_get():
Get the value of objects with
types of int or bool
яБм vpi_get_str():
Get the value of objects with
types of string
яБм
Aug. 11th, 2004
Test Seminar
20
Verilog VPI Routines
яБм
VPI Routines for Accessing
Objects from Properties
vpi_handle_by_name():
Obtain a handle for a named
object
яБм vpi_handle_by_index():
Obtain a handle for an indexed
object
яБм vpi_handle_by_multi_index():
Obtain a handle to a word or bit
in an array
яБм
Aug. 11th, 2004
Test Seminar
21
Verilog VPI Routines
яБм
VPI Routines for Delay
Processing
vpi_get_delays():
Retrieve delays or timing limits
of an object
яБм vpi_put_delays():
Write delays or timing limits to
an object
яБм
Aug. 11th, 2004
Test Seminar
22
Verilog VPI Routines
яБм
VPI Routines for Logic and
Strength Value Processing
vpi_get_value():
Retrieve logic value or strength
value of an object
яБм vpi_put_value():
Write logic value or strength
value to an object
яБм
Aug. 11th, 2004
Test Seminar
23
Verilog VPI Routines
яБм
VPI Routines for Simulation
Time Processing
яБм
vpi_get_time():
Find the current simulation time
or the scheduled time of future
events
Aug. 11th, 2004
Test Seminar
24
Verilog VPI Routines
яБм
VPI Routines for Miscellaneous Utilities
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vpi_printf()
vpi_vprintf()
vpi_flush()
vpi_mcd_open()
vpi_mcd_close()
vpi_mcd_printf()
vpi_mcd_vprintf()
vpi_mcd_flush()
vpi_mcd_name()
vpi_get_vlog_info()
vpi_compare_objects()
vpi_chk_error()
vpi_free_object()
vpi_put_data()
vpi_get_data()
vpi_put_userdata()
vpi_get_userdata()
vpi_sim_control()
Aug. 11th, 2004
Test Seminar
25
Verilog VPI Routines
яБм
Module
Data Model
Aug. 11th, 2004
Test Seminar
26
Verilog VPI Routines
яБм
Aug. 11th, 2004
Net Data Model
Test Seminar
27
Verilog VPI Routines
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Aug. 11th, 2004
Reg Data Model
Test Seminar
28
Verilog VPI Routines
яБм
Cadence PLI Environment
Aug. 11th, 2004
Test Seminar
29
Verilog VPI Routines
яБм
Cadence PLI Environment
яБм
Creating a C Function
#include <stdio.h>
#include vpi_user.h
int hello_task () {
vpi_printf (Hello from a new VPI task \n);}
яБм
Creating a C++ Function
extern C void ncmain (int, char **);
main(argc, argv)
int argc;
char* argv[];
{ ncmain(argc, argv); }
Aug. 11th, 2004
Test Seminar
30
Verilog VPI Routines
яБм
Cadence PLI Environment
яБм
Associating C Function with a
new System Task
void register_my_systfs () {
s_vpi_systf_data task_data_s;
p_vpi_systf_data task_data_p = &task_data_s;
task_data_p->type = vpiSysTask;
task_data_p->tfname = $hello ;
task_data_p->calltf = (int(*)()) hello_task;
task_data_p->compiletf = NULL;
vpi_register_systf (task_data_p); }
Aug. 11th, 2004
Test Seminar
31
Verilog VPI Routines
яБм
Cadence PLI Environment
яБм
Registering UsersтАЩ New System
Task
/* vpi_user.c */
#include vpi_user.h
#include vpi_user_cds.h
void (*vlog_startup_routines[]) () =
{register_my_systfs, 0};
яБм
Invoking UsersтАЩ System Task
module top;
Initial begin $hello; end
endmodule
Aug. 11th, 2004
Test Seminar
32
Verilog VPI Routines
яБм
Cadence PLI Environment
яБм
Compiling C Files (vconfig)
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Static/Dynamic
cc -KPIC -c ~/vpi_user.c -I<InstDir>/include
cc -KPIC -c ~/hello.c -I<InstDir>/include
ld -G vpi_user.o hello.o -o libvpi.so
тАж executable file
яБм
Compiling and Simulating
Verilog File
setenv LD_LIBRARY_PATH \
~/<LibDir>:$LD_LIBRARY_PATH
ncelab тАУaccess+rwc worklib.top:v
ncverilog +ncaccess+rwc +plinowarn hello.v
Aug. 11th, 2004
Test Seminar
33
Verilog VPI Routines
яБм
Mentor Graphics PLI
Environment
яБм
Compiling C Files
cc -c ~/vpi_user.c -I<InstDir>/include
cc -c ~/hello.c -I<InstDir>/include
ld -G vpi_user.o hello.o -o vpi_lib.so
яБм
Compiling and Simulating
Verilog File (modelsim.ini)
vlib work
vlog hello.v
vsim -c -pli vpi_lib.so top
Aug. 11th, 2004
Test Seminar
34
References
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Cadence Design Systems, Inc., тАЬVPI
User Guide and Reference,тАЬ Product
Version 3.2, Dec. 2000.
Cadence Design Systems, Inc., тАЬNCVerilog Simulator Help,тАЭ Product
Version 3.2, Dec. 2000.
Cadence Design Systems, Inc.,
тАЬVerilog-XL User Guide and
Reference,тАЭ Product Version 2.8, Aug.
1999.
Mentor Graphics, тАЬModelSim SE
User's Manual,тАЭ Version 5.7a, Jan.
2003
Stuart Sutherland, тАЬThe Verilog PLI
Handbook,тАЭ Kluwer Academic
Publishers, 2002.
Swapnajit Mittra, тАЬPrinciples of Verilog
PLI,тАЭ Kluwer Academic Publishers,
1999.
Aug. 11th, 2004
Test Seminar
35
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