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VLSI DEsign Methodology

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The Devices:
MOS Transistor
Dynamics
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
EE415 VLSI Design
Overview - Transistor Dynamics
Transistor capacitances
пЃ¬ Sub-Micron MOS Transistor
пЃ¬
В» Threshold Variations
В» Velocity Saturation
В» Sub-Threshold Conduction and Leakage
Latchup
пЃ¬ Process Variations
пЃ¬ Future Perspectives
пЃ¬
EE415 VLSI Design
Dynamic Behavior of MOS Transistor
•MOSFET is a majority carrier device
(unlike pn junction diode)
•Delays depend on the time to (dis)charge
the capacitances between MOS terminals
•Capacitances originate from three sources:
S
•basic MOS structure (layout)
•charge present in the channel
•depletion regions of the reverse-biased
pn-junctions of drain and source
•Capacitances are non-linear and vary with
the applied voltage
EE415 VLSI Design
G
CGS
CGD
D
CGB
C SB
B
CDB
MOS Structure Capacitances
Gate Capacitance
•Gate isolated from channel by gate oxide
C ox пЂЅ пЃҐ ox / t ox
•tox is very small <10nm
•Results in gate capacitance Cg
C g пЂЅ C ox WL
EE415 VLSI Design
Gate Oxide
Gate
Source
Polysilicon
n+
Drain
Field-Oxide
n+
(SiO2)
p-substrate
Bulk Contact
CROSS-SECTION of NMOS Transistor
p+ stopper
The Gate Capacitance
EE415 VLSI Design
The Gate Capacitance
Gate Capacitance depends on
•channel charge (non-linear)
•topology
Capacitance due to topology
•Source and drain extend below the gate oxide by xd
(lateral diffusion)
•Effective length of the channel Leff is shorter than the
drawn length by factor of 2xd
•Cause of parasitic overlap capacitance, CgsO, between
gate and source (drain)
EE415 VLSI Design
The Gate Capacitance
Overlap Capacitance
EE415 VLSI Design
Channel Capacitance
The Channel Capacitance
Channel Capacitance has three components
•capacitance between gate and source, Cgs
•capacitance between gate and drain, Cgd
•capacitance between gate and bulk region, Cgb
Channel Capacitance values
•non-linear, depends on operating region
•averaged to simplify analysis
EE415 VLSI Design
The Channel Capacitance
Different distributions of gate capacitance for varying
operating conditions
Most important regions in digital design: saturation and cut-off
EE415 VLSI Design
Diffusion Capacitance
Bottom Plate Capacitance
Junction Depth
EE415 VLSI Design
Capacitive Device Model
G
CGS = Cgs+ CgsO
CGS
CGD = Cgd+ CgdO
CGB = Cgb
CSB = CSdiff
CGD
D
S
CGB
CSB
CDB = CDdiff
B
EE415 VLSI Design
CDB
Transistor Capacitance Values
for 0.25пЃ­
Example: For an NMOS with L = 0.24 пЃ­m,
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
W = 0.36 пЃ­m, LD = LS = 0.625 пЃ­m
Capacitance of both source and drain
CGC = Cox WL = 0.52 fF
so Cgate_cap = CoxWL + 2CoW = 0.74 fF
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF
so Cdiffusion_cap = 0.90 fF
Overlap capacitance
Cox
(fF/пЃ­m2)
Co
(fF/пЃ­m)
Cj
(fF/пЃ­m2)
mj
пЃ¦b
(V)
Cjsw
(fF/пЃ­m)
mjsw
пЃ¦bsw
(V)
NMOS
6
0.31
2
0.5
0.9
0.28
0.44
0.9
PMOS
6
0.27
1.9
0.48
0.9
0.22
0.32
0.9
EE415 VLSI Design
Review: Sources of
Capacitance
Vout
Vin
Vout2
CL
CG4
M2
CGD12
Vin
pdrain
ndrain
M1
M4
CDB2
CDB1
Vout
Vout2
Cw
M3
CG3
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
wiring (interconnect) capacitance
EE415 VLSI Design
Gate-Drain Capacitance: The
Miller Effect
пЃ¬
пЃ¬
M1 and M2 are either in cut-off or in saturation.
The floating gate-drain capacitor is replaced by a
capacitance-to-ground (gate-bulk capacitor).
пЃ„V
CGD1
Vin
пЃ„V
M1
пЃ¬
Vout
Vout
2CGB1
пЃ„V
Vin
пЃ„V
M1
A capacitor experiencing identical but opposite voltage
swings at both its terminals can be replaced by a
capacitor to ground whose value is two times the
original value
EE415 VLSI Design
Drain-Bulk Capacitance: Keq’s
(for 2.5 пЃ­m)
пЃ¬
We can simplify the diffusion capacitance calculations
even further by using a Keq to relate the linearized
capacitor to the value of the junction capacitance under
zero-bias
Ceq = Keq Cj0
NMOS
PMOS
EE415 VLSI Design
high-to-low
Keqbp Keqsw
0.57
0.61
0.79
0.86
low-to-high
Keqbp
Keqsw
0.79
0.81
0.59
0.7
Extrinsic (Fan-Out)
Capacitance
пЃ¬
The extrinsic, or fan-out, capacitance is the total gate
capacitance of the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)
пЃ¬
Simplification of the actual situation
В» Assumes all the components of Cgate are between Vout and
GND
(or VDD)
В» Assumes the channel capacitances of the loading gates
are constant
EE415 VLSI Design
Layout of Two Chained Inverters
VDD
PMOS
1.125/0.25
1.2пЃ­m
=2l
Out
In
Metal1
Polysilicon
0.125
0.5
NMOS
0.375/0.25
GND
W/L
AD (пЃ­m2)
PD (пЃ­m)
AS (пЃ­m2)
PS (пЃ­m)
NMOS
0.375/0.25
0.3
1.875
0.3
1.875
PMOS
1.125/0.25
0.7
2.375
0.7
2.375
EE415 VLSI Design
Components of CL (0.25 пЃ­m)
Expression
C Term
Value (fF) Value (fF)
Hп‚®L
Lп‚®H
CGD1
2 Con Wn
0.23
0.23
CGD2
2 Cop Wp
0.61
0.61
CDB1
KeqbpnADnCj + KeqswnPDnCjsw
0.66
0.90
CDB2
KeqbppADpCj + KeqswpPDpCjsw
1.5
1.15
CG3
(2 Con)Wn + CoxWnLn
0.76
0.76
CG4
(2 Cop)Wp + CoxWpLp
2.28
2.28
Cw
from extraction
0.12
0.12
CL

6.1
6.0
EE415 VLSI Design
The Sub-Micron MOS Transistor
•Actual transistor deviates substantially from model
•Channel length becomes comparable to other device
parameters. Ex: depth of drain and source junctions
•Referred to as a short-channel device
•Influenced heavily by secondary effects
•Latchup problems
EE415 VLSI Design
The Sub-Micron MOS Transistor
Secondary Effects:
•Threshold Variations
•Parasitic Resistances
•Velocity Saturation
•Mobility Degradation
•Sub-threshold Conduction
EE415 VLSI Design
Threshold Variations
• Part of the region below gate is depleted by source and drain
fields, which reduce the threshold voltage for short channel.
• Similar effect is caused by increase in VDS, so threshold is
smaller with larger VDS
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS)
EE415 VLSI Design
Low VDS threshold
VDS
Drain-induced barrier lowering
lowers VT for short channel device
Variations in I-V Characteristics
•The velocity of the carriers is proportional to the electric field up to
a point.
•When electric field reaches a critical value, Esat, the velocity
saturates.
•When the channel length decreases, only a small VDS is needed for
saturation
•Causes a linear dependence of the saturation current wrt the gate
voltage (in contrast to squared dependence of long-channel device)
•Current drive cannot be increased by decreasing L
EE415 VLSI Design
u n (m/s)
Velocity Saturation
usat = 105
Constant velocity
Constant mobility (slope = Вµ)
xc = 1.5
EE415 VLSI Design
x (V/Вµm)
Velocity Saturation
пЃ¬
пЃ¬
We assumed carrier velocity is proportional to E-field
В» v = пЃ­Elat = пЃ­Vds/L
At high fields, this ceases to be true
В» Carriers scatter off atoms
В» Velocity reaches vsat
– Electrons: 6-10 x 106 cm/s
– Holes: 4-8 x 106 cm/s
В» Better model
Ој E lat
vпЂЅ
пѓћ v sat пЂЅ Ој E sat
E lat
1пЂ«
E sat
EE415 VLSI Design
Voltage-Current Relation:
Velocity Saturation
For short channel devices
 Linear: When VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where
пЃ«(V) = 1/(1 + (V/(xcL))) is a measure of the degree of
velocity saturation
пЃ¬
Saturation: When VDS = VDSAT  VGS – VT
IDSat = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
EE415 VLSI Design
Velocity Saturation Effects
10
For short channel devices
and large enough VGS – VT
VDSAT < VGS – VT so
the device enters
saturation before VDS
reaches VGS – VT and
operates more often in
saturation
пЃ¬
0
IDSAT has a linear dependence wrt VGS so a reduced
amount of current is delivered for a given control voltage
пЃ¬
EE415 VLSI Design
Velocity Saturation
1 .5
0 .5
VGS = 3
0 .5
VGS = 2
VGS = 1
0 .0
1 .0
2 .0
3 .0
4 .0
5 .0
ID (m A )
VGS = 4
ID (m A )
1 .0
L i ne a r D e p e n d e n c e
VGS = 5
0
0 .0
1 .0
2 .0
(V )
V D S ( V)
VGS
( a) I D a s a fu n ctio n o f V D S
(b ) ID a s a fu n ctio n o f V G S
(fo r V D S = 5 V ) .
L ine ar D e pe nd en ce o n V G S
EE415 VLSI Design
3 .0
Short Channel I-V Plot (NMOS)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
2.5
X 10-4
Early Velocity
Saturation
2
VGS = 2.5V
VGS = 2.0V
1.5
Linear
1
Saturation
0.5
VGS = 1.5V
VGS = 1.0V
0
0
EE415 VLSI Design
0.5
1
1.5
VDS (V)
2
2.5
Leakage Sources
пЃ¬
пЃ¬
пЃ¬
пЃ¬
Subthreshold conduction
» Transistors can’t abruptly turn ON or OFF
Junction leakage
В» Reverse-biased PN junction diode current
Gate leakage
В» Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source of DC
power dissipation in modern transistors
EE415 VLSI Design
D
D
S
S
Sub-Threshold Conduction
The Slope Factor
-2
10
Linear
qV GS
-4
I D ~ I 0e
10
-6
Quadratic
Slope S
-8
10
-10
Exponential
-12
VT
10
10
, n пЂЅ 1пЂ«
0
0.5
1
1.5
VGS (V)
EE415 VLSI Design
CD
C ox
S is пЃ„VGS for ID2/ID1 =10
ID (A)
10
nkT
2
2.5
Typical values for S:
60 .. 100 mV/decade
Gate Leakage
пЃ¬
пЃ¬
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to tox and VDD
D
IG
S
пЃ¬
пЃ¬
В» A and B are tech constants
В» Greater for electrons
– So nMOS gates leak more
From [Song01]
Negligible for older processes (tox > 20 Г…)
Critically important at 65 nm and below (tox ≈ 10 Å=1nm)
EE415 VLSI Design
Sub-Threshold ID vs VGS
D ID
VG +
- VS
qV GS
I D пЂЅ I 0e
nkT
qV DS
пЂ­
пѓ¦
пѓ§ 1 пЂ­ e kT
пѓ§
пѓЁ
пѓ¶
пѓ·
пѓ·
пѓё
VDS from 0 to 0.5V
EE415 VLSI Design
VGS
Sub-Threshold ID vs VDS
qV GS
VD I
D
VG
I D пЂЅ I 0e
nkT
VS
VGS from 0 to 0.3V
EE415 VLSI Design
qV DS
пЂ­
пѓ¦
пѓ§ 1 пЂ­ e kT
пѓ§
пѓЁ
пѓ¶
пѓ· пЂЁ1 пЂ« l пѓ— V DS
пѓ·
пѓё
пЂ©
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
EE415 VLSI Design
2
2.5
0
0
0.5
1
1.5
VGS(V)
Short Channel
2
2.5
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
EE415 VLSI Design
2
2.5
0
0
0.5
1
1.5
VDS(V)
Short Channel
2
2.5
A unified model
for manual analysis
G
S
D
B
VT0(V)
пЃ§(V0.5)
VDSAT(V)
k’(A/V2)
l(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1
EE415 VLSI Design
A PMOS Transistor
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V
-4
0
x 10
-0.2
ID (A)
-0.4
VGS = -1.0V
VGS = -1.5V
VGS = -2.0V
Assume all variables
negative!
-0.6
VGS = -2.5V
-0.8
-1
-2.5
-2
EE415 VLSI Design
-1.5
-1
VDS (V)
-0.5
0
Parasitic Resistances
Polysilicon gate
increase W
G
LD
Drain
contact
D
S
RS
R S ,D пЂЅ
W
VGS,eff
RD
LS ,D
W
R SQ пЂ« R C
Drain
RSQ is the resistance per square
RC is the contact resistance
Silicide the bulk region
EE415 VLSI Design
The Transistor as a Switch
ID
VGS п‚і VT
V G S = VD D
R m id
Ron
S
D
R0
V DS
VD D / 2
EE415 VLSI Design
VD D
The Transistor as a Switch
VGS п‚і VT
7
x105
6
S
Resistance inversely
proportional to W/L (doubling W
halves Ron)
пЃ¬
Ron
D
5
4
3
For VDD>>VT+VDSAT/2, Ron
independent of VDD
2
пЃ¬
пЃ¬
1
Once VDD approaches VT, Ron
increases dramatically
VDD (V)
0
0.5
1
1.5
2
(for VGS = VDD,
VDS = VDD п‚®VDD/2)
2.5
VDD(V)
1
1.5
2
2.5
NMOS(kпЃ—)
35
19
15
13
PMOS (kпЃ—)
115
55
38
31
EE415 VLSI Design
Ron (for W/L = 1)
For larger devices
divide Req by W/L
Summary of MOSFET Operating
Regions
пЃ¬
Strong Inversion VGS > VT
В» Linear (Resistive) VDS < VDSAT
В» Saturated (Constant Current) VDS п‚і VDSAT
пЃ¬
Weak Inversion (Sub-Threshold) VGS п‚Ј VT
В» Exponential in VGS with linear VDS dependence
EE415 VLSI Design
Latchup
VD D
VDD
p
+
n
+
n
+
p
+
n- w ell
p
+
n
p-source
+
R n w e ll
R ps u bs
n-source
p- substrate
(a) O rigin of latchup
EE415 VLSI Design
R nw el l
R ps ub s
( b) E quivalent circuit
Fitting level-1 model
to short channel characteristics
R e g io n o f
m a tch in g
ID
S h o rt-ch a n n e l
I-V cu rve
VGS = 5 V
L o n g -ch a n n e l
a p p ro xim a tio n
VDS = 5 V
’
VDS
S e le ct k a n d l su ch th a t b e st m a tch in g is o b ta in e d @ V g s = V d s = V D D
EE415 VLSI Design
SPICE MODELS
Le vel 1: Lo n g C h an n el E q u ation s - V ery S im p le
Le vel 2: P hy sical M od el - In clud es V e lo city
S atu ratio n an d T h res ho ld V ar ia tio n s
Le vel 3: S em i-E m p er ic al - B a sed on cu rve fitting
to m e asu re d d evice s
Le vel 4 (B S IM ): E m pe rical - S im p le an d P o pu lar
Berkeley Short-Channel IGFET Model
EE415 VLSI Design
MAIN MOS SPICE PARAMETERS
EE415 VLSI Design
SPICE Parameters for Parasitics
EE415 VLSI Design
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
VDS (V)
EE415 VLSI Design
2
2.5
Technology Evolution
пЃ¬
Semiconductor Industry Association
forecast
В» Intl. Technology Roadmap for
Semiconductors
EE415 VLSI Design
Process Variations
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters , such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the
impurities. Introduces variations in the sheet resistances and transistor
parameters such as the threshold voltage.
Variations in the dimensions of the devices, resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.
EE415 VLSI Design
Impact of Device Variations
2.10
2.10
Delay (nsec)
Delay (nsec)
1.90
1.90
1.70
1.70
1.50
1.10 1.20 1.30 1.40 1.50 1.60
Leff (in пЃ­m)
1.50
–0.90
–0.80
–0.70
–0.60 –0.50
VTp (V)
Delay of Adder circuit as a function of variations in L and VT
EE415 VLSI Design
So What?
пЃ¬
So what if transistors are not ideal?
В» They still behave like switches.
пЃ¬
But these effects matter for…
В» Supply voltage choice
В» Logical effort
В» Quiescent power consumption
В» Pass transistors
В» Temperature of operation
EE415 VLSI Design
Parameter Variation
пЃ¬
Transistors have uncertainty in parameters
В» Process: Leff, Vt, tox of nMOS and pMOS
пЃ¬
пЃ¬
EE415 VLSI Design
FF
SF
pMOS
Fast (F)
В» Leff: ____
В» Vt: ____
В» tox: ____
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
TT
FS
SS
slow
пЃ¬
fast
В» Vary around typical (T) values
slow
nMOS
fast
Parameter Variation
пЃ¬
Transistors have uncertainty in parameters
В» Process: Leff, Vt, tox of nMOS and pMOS
пЃ¬
пЃ¬
EE415 VLSI Design
FF
SF
pMOS
Fast (F)
В» Leff: short
В» Vt: low
В» tox: thin
Slow (S): opposite
Not all parameters are independent
for nMOS and pMOS
TT
FS
SS
slow
пЃ¬
fast
В» Vary around typical (T) values
slow
nMOS
fast
Environmental Variation
пЃ¬
пЃ¬
VDD and T also vary in time and space
Fast:
В» VDD: ____
В» T: ____
Corner
Voltage
Temperature
1.8
70 C
F
T
S
EE415 VLSI Design
Environmental Variation
пЃ¬
пЃ¬
VDD and T also vary in time and space
Fast:
В» VDD: high
В» T: low
Corner
Voltage
Temperature
F
1.98
0C
T
1.8
70 C
S
1.62
125 C
EE415 VLSI Design
Process Corners
пЃ¬
пЃ¬
Process corners describe worst case variations
В» If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
В» nMOS speed
В» pMOS speed
В» Voltage
В» Temperature
EE415 VLSI Design
Important Corners
пЃ¬
Some critical simulation corners include
Purpose
Cycle time
Power
Subthrehold
leakage
EE415 VLSI Design
nMOS
pMOS
VDD
Temp
Important Corners
пЃ¬
Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
S
S
S
S
Power
F
F
F
F
Subthrehold
leakage
F
F
F
S
EE415 VLSI Design
Future Perspectives
25 nm FINFET MOS transistor
EE415 VLSI Design
Three-Dimensional
Integrated Circuits
пЃ¬
пЃ¬
Multiple Layers of Active Devices
Driven by
В» Limited floorplanning choices
В» Desire to integrate disparate technologies (GaAs, SOI, SiGe,
BiCMOS)
В» Desire to integrate disparate signals (analog, digital, RF)
В» Interconnect bottleneck
3D IC
2D IC
As small as 20Вµm
EE415 VLSI Design
>500Вµm
60
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