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# Design for Testability

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```Design for Testability
Outline
вЂў Ad Hoc Design for Testability Techniques
вЂ“
вЂ“
вЂ“
вЂ“
Method of test points
Multiplexing and demultiplexing of test points
Time sharing of I/O for normal working and testing modes
Partitioning of registers and large combinational circuits
вЂў Scan-Path Design
вЂ“
вЂ“
вЂ“
вЂ“
вЂ“
Scan-path design concept
Controllability and observability by means of scan-path
Full and partial serial scan-paths
Non-serial scan design
Classical scan designs
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Method of Test Points:
Block 1
Block 2
Block 1 is not observable,
Block 2 is not controllable
Improving controllability and observability:
OP
Block 1
1
CP
Block 1
Block 2
1- controllability:
CP = 0 - normal working mode
CP = 1 - controlling Block 2
with signal 1
Block 2
0- controllability:
CP = 1 - normal working mode
CP = 0 - controlling Block 2
with signal 0
OP
&
CP
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Method of Test Points:
Block 1
Block 1 is not observable,
Block 2 is not controllable
Block 2
Improving controllability:
1
Block 1
CP1
Block 1
CP1
CP2
&
Block 2
CP2
MUX
Block 2
Normal working mode:
CP1 = 0, CP2 = 1
Controlling Block 2 with 1:
CP1 = 1, CP2 = 1
Controlling Block 2 with 0:
CP2 = 0
Normal working mode:
CP2 = 0
Controlling Block 2 with 1:
CP1 = 1, CP2 = 1
Controlling Block 2 with 0:
CP1 = 0, CP2 = 1
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Multiplexing monitor points:
0
1
To reduce the number of
output pins for observing
monitor points,
multiplexer can be used:
MUX
2n-1
2n
observation points are
replaced by a single
output and n inputs to
observation point
x1
x2
xn
Only one observation
point can be observed at
a time
(n + 1)
Number of observable points: [2n]
Advantage: (n + 1) << 2n
Technical University Tallinn, ESTONIA
OUT
Ad Hoc Design for Testability Techniques
Multiplexing monitor points:
To reduce the number of
output pins for observing
monitor points,
multiplexer can be used:
To reduce the number of
inputs, a counter (or a
shift register) can be used
of the multiplexer
0
1
MUX
2n-1
c
Counter
Only one observation
point can be observed at
a time
2
Nmber of observable points: [2n]
Technical University Tallinn, ESTONIA
OUT
Ad Hoc Design for Testability Techniques
Demultiplexer for implementing control points:
0
x
1
CP1
CP2
2n-1
CPN
To reduce the number of
input pins for controlling
testpoints, demultiplexer
and a latch register can
be used.
DMUX
N clock times are required
between test vectors to
set up the proper control
values
x1
x2
xn
Number of control points:
(n + 1)
2n-1 пЂј N п‚Ј 2n
Advantage: (n + 1) << N
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Demultiplexer for implementing control points:
0
x
1
DMUX
2n-1
c
To reduce the number of input
pins for controlling testpoints,
demultiplexer and a latch
register can be used.
CP1
CP2
To reduce the number of
a
counter (or a shift register) can
be used to drive the address
lines of the demultiplexer
CPN
Counter
Number of control points:
2
N
N clock times are required
between test vectors to set up
the proper control values
Technical University Tallinn, ESTONIA
Time-sharing of outputs for monitoring
To reduce the number of
output pins for observing
monitor points, timesharing of working
outputs can be
outputs are needed
MUX
To reduce the number of
inputs, again counter or
shift register can be used
if needed
Number of control points:
Original
circuit
1
N
Technical University Tallinn, ESTONIA
Time-sharing of inputs for controlling
0
Normal
input
lines
1
CP1
CP2
N
CPN
To reduce the number of
input pins for controlling
test points, time-sharing
of working inputs can be
introduced.
To reduce the number of
inputs for driving the
demultiplexer, counter or
shift register can be used
if needed
DMUX
Number of control points:
1
N
Technical University Tallinn, ESTONIA
Example: DFT with MUX-s and DMUX-s
Given a circuit:
- CP1 and CP2 are not controllable
- CP3 and CP4 are not observable
DFT task: Improve the testability by using a single control input, no
1
2
3
4
CP1
CP2
CP3
CP4
1
2
3
4
Technical University Tallinn, ESTONIA
Example: DFT with MUX-s and DMUX-s
Given a circuit:
CP3 and CP4 are not observable
п‚® Improving the observability
Coding:
T
Mode
MUX
0
1
Norm.
Test
0
1
T
1
2
3
4
CP1
CP2
CP3
CP4
1
2
3
0
4
1 MUX
0
1 MUX
Result: A single pin T is needed
Technical University Tallinn, ESTONIA
Example: DFT with MUX-s and DMUX-s
Given a circuit: CP1 and CP2 are not controllable п‚® Improving the controllability
Coding:
T
Counter
Mode DMUX MUX
00 Norm.
01 Contr
10 Test
Q
Decoder
0
DMUX
FF
1
0
1 MUX
0
DMUX 1
1
Result:
A single pin T
is needed
Q
2
3
4
FF
0
1 MUX
CP1
CP2
CP3
CP4
1
0
1
1
2
3
4
Technical University Tallinn, ESTONIA
1
x
0
Example: DFT with MUX-s and DMUX-s
x1
x2
x3
F1
F2
T
z1
z2
z3
F3
z4
F4
y1
Counter
Counter
Decoder
Decoder
Q
MUX
1
MUX
Q
Mode
DMUX
00
000
Norm
1
1
0
001
0
Contr
0
x
x
010
Test
1
0
0
011
0
1
0
1
100
Obs
Obs
1
0
2
101
10
Obs
1
0
3
0
DMUX
DMUX
FF
1
0
FF
CP1
1
MUX
1
MUX1
1
0
Result:
A single
pin T
is needed
1
2
3
1
CP 2
CP 3
4
MUX 2
2
2
3
3
4
2 MUX 2
3
CP4
Technical University Tallinn, ESTONIA
2
Ad Hoc Design for Testability Techniques
Examples of good candidates for control points:
вЂ“
вЂ“
вЂ“
вЂ“
вЂ“
вЂ“
control, address, and data bus lines on bus-structured designs
enable/hold inputs of microprocessors
enable and read/write inputs to memory devices
clock and preset/clear inputs to memory devices (flip-flops, counters, ...)
data select inputs to multiplexers and demultiplexers
control lines on tristate devices
Examples of good candidates for observation points:
вЂ“
вЂ“
вЂ“
вЂ“
вЂ“
вЂ“
stem lines associated with signals having high fanout
global feedback paths
redundant signal lines
outputs of logic devices having many inputs (multiplexers, parity generators)
outputs from state devices (flip-flops, counters, shift registers)
Technical University Tallinn, ESTONIA
Fault redundancy and testability
x1
x2
x4
&
&
1
1
&
x3
&
Redundant gates are removed:
0
1
1
x1
x12
y
x2
&
y пЂЅ x1 пѓљ ( x1 пѓљ x 2 ) x 4 пѓљ x 3 x 4
п‚¶x2
п‚є0
&
1
1
x4
п‚¶y
&
x11
Faults at x2 not
testable
1
&
y
0
x3
&
&
Remaining
gate
Fault at x12 not testable
0
y пЂЅ x1 пѓљ x 4 пѓљ x 3 x 4 пЂЅ x1 пѓљ x 4 пѓљ x 3
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Hazard control circuitry:
1
0п‚®1
&
0п‚®1
Logical redundancy:
Redundancy should be avoided:
вЂў
If a redundant fault occurs, it may invalidate
some test for nonredundant faults
вЂў
Redundant faults cause difficulty in
calculating fault coverage
вЂў
Much test generation time can be spent in
trying to generate a test for a redundant fault
вЂў
To eliminate hazards in combinational
circuits
вЂў
To achieve high reliability (using error
detecting circuits)
T
&
1
&
п‚є0
1п‚®0
1
1
1
Redundant AND-gate
Fault п‚є 0 not testable
T = 1 - normal working mode
T = 0 - testing mode
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Fault redundancy:
Testable error control circuitry:
Error control circuitry:
Decoder
Decoder
пѓ…
пѓ…
п‚є1
No
error
E = 1 if decoder is fault-free
Fault п‚є 1 not testable
T
п‚є1
Error
detected
T п‚є 0 - normal working mode
T = 1 - testing mode
Technical University Tallinn, ESTONIA
Ad Hoc Design for Testability Techniques
Partitioning of registers (counters):
IN
C
CL
REG 1
OUT
IN
CL
16 bit counter divided
into two 8-bit counters:
REG 2
clocks, 2x28 = 512
clocks needed
OUT
If tested in parallel, only
256 clocks needed
CP: Tester Data
CP: Data Inhibit
&
&
CP: Tester Data
CP: Data Inhibit
IN
CL
C
&
CP: Clock Inhibit
REG 1
OUT
&
&
IN
CL
REG 2
&
OP
CP: Tester Clock
Technical University Tallinn, ESTONIA
OUT
Ad Hoc Design for Testability Techniques
Partitioning of large combinational circuits:
C1
DMUX1
MUX3
The time complexity of
test generation and
fault simulation grows
faster than a linear
function of circuit size
Partioning of large
circuits reduces these
costs
C1
MUX1
MUX2
I/O sharing of normal
and testing modes is
used
C2
DMUX2
C2
MUX4
Three modes can be
chosen:
- normal mode
- testing C1
- testing C2 (bolded
lines)
How many additional inputs are needed?
Technical University Tallinn, ESTONIA
Scan-Path Design
IN
OUT
Combinational
circuit
The longer a feedback loop, the more
clock cycles are needed to initialize
and sensitize patterns
Scan-IN
qвЂ™
Scan-register is a aregister with
q
R
The complexity of testing is a function
of the number of feedback loops and
their length
T = 0 - normal working mode
T = 1 - scan mode
Scan-OUT
Normal mode :
q
&
Scan-IN
&
T
flip-flops are
connected to the combinational circuit
1
D T
qвЂ™
C
Scan-OUT
Test mode:
flip-flops are
disconnected from the combinational
circuit and connected to each other to
form a shift register
Technical University Tallinn, ESTONIA
Scan-Path Design and Testability
Two possibilities for improving
controllability/observability
MUX
IN
SCAN
OUT
OUT
DMUX
SCAN
IN
Technical University Tallinn, ESTONIA
Parallel Scan-Path
IN
Combinational
circuit
Scan-IN 1
R1
Scan-OUT 1
OUT
In parallel scan path
flip-flops can be
organized in more than
one scan chain
Scan-IN 2
R2
Scan-OUT 2
Technical University Tallinn, ESTONIA
Partial Scan-Path
IN
Combinational
circuit
Scan-IN
R1
Scan-OUT
R2
OUT
In partial scan
full-scan,
it may be
to scan
only some
of the flip-flops
Example:
counter вЂ“ even
bits joined in the
scan-register
Technical University Tallinn, ESTONIA
Partial Scan Path
Scan-In
Hierarhical test generation with Scan-Path:
R2
Control Part
y4
0
1
2
y1
R1
y3
M1
п‚·
0
y3
+
c
e
M3
R2
п‚·
Bus
2
3
п‚·
*
d
0
y1
R1 + R2
1
1
b
M2
y4
R2
Scan-Out
a
п‚·
п‚·
IN
y2
#0
IN + R2
IN
R1
y2
0
R1 * R2
1
IN* R2
Data Part
Technical University Tallinn, ESTONIA
Testing with Minimal DFT
Hierarhical test generation with Scan-Path:
R2
Control Part
y4
0
1
Scan-In
y1
R1
y3
M1
п‚·
0
y3
+
c
e
M3
R2
п‚·
Bus
2
3
п‚·
*
d
0
y1
R1 + R2
1
1
b
M2
y4
R2
Scan-Out
a
п‚·
п‚·
IN
y2
2
#0
IN + R2
IN
R1
y2
0
R1 * R2
1
IN* R2
Data Part
Technical University Tallinn, ESTONIA
Random Access Scan
IN
qвЂ™
Scan-IN
Scan-CL
OUT
Combinational
circuit
R
q
&
Scan-OUT
In random access
scan each flip-flop
in a logic network
is selected
individually by an
and observation of
its state
Example:
DC
Delay fault testing
DC
Technical University Tallinn, ESTONIA
Higherarchical TPG: Behavioral Model
Behaviour model:
A = A * (A + B) пѓљ B2
Detailed data-flow graph:
C = A+B
BEGIN
q0
C = A+B
A = A*C
T=2
C=
B2
A = AпѓљC
q2
1
E(0)
D=A
E=C
F=0
q1
0
F = F+D
q3
L=0
1
L=9
0
T = T-1
q4
D = R(D)
E = L(E)
L = L-1
0
q5
A= F
D=B
E=B
T=0
1
C=F
Technical University Tallinn, ESTONIA
Higherarchical TPG: Digital System
Technical University Tallinn, ESTONIA
Higherarchical TPG: Decision Diagram
Technical University Tallinn, ESTONIA
Higherarchical TPG: Decision Diagram
Kokku pakitud testprogramm:
No
1
T estvektor
LT A B
11 A B
2
3
x1 AB
xx A B
A
C
E
R (A ) L (A + B )
A пѓљ R (A )
A *(A + B )
A *(A + B )пѓљ B
2
funktsioonid
R ,L,пѓљ ,+
M uutuja L
M uutuja T
T esti pikkus
(vektoreid/takte)
8/5 = 40
1/(2+16*2) = 34
1/(33+34) = 67
Technical University Tallinn, ESTONIA
Selection of Test Points
Test point selection approaches
вЂў Improving testability for any set of pseudo-random patterns
(Pseudorandom BIST)
вЂ“ Testability measures are used to characterize the controllability and
observability of the circuit
вЂў Improving testability for a given sequence of vectors
(Functional BIST)
Methods that are used:
вЂ“
вЂ“
вЂ“
вЂ“
logic simulation,
fault simulation,
estimation of controllability and observability values,
path tracing
Technical University Tallinn, ESTONIA
Random BIST vs Functional BIST
Random
BIST
Test
generator
HW
Functional
BIST
functional
testing
UUT
UUT
UUT
Result
Result
Normal
operation
Signature
Signature
пѓ…
Go/NoGo
пѓ…
Reference
Reference
Random test set
Go/NoGo
HW
пѓ…
Go/NoGo
Reference
Deterministic
functional test set
Technical University Tallinn, ESTONIA
Selection of Test Points
Method: Simulation of given test patterns
вЂў Identification of the faults that are detected
вЂў The remaining faults are classified as
вЂ“ A: Faults that were not excited
вЂ“ B: Faults at gate inputs that were excited but not propagated to the gate output
вЂ“ C: Faults that were excited but not propagated to circuit output
вЂў The faults A and B require control points for their detection
вЂў The faults C may be detected by observation points only
вЂў Control points selection should be carried out before observation
points selection
Technical University Tallinn, ESTONIA
Classification of Not-Detected Faults
Class C:
Classes
A and B
need
controllability
Faults at x1 are not
propagated to the output
x1
x2
x3
0
1
Always 1
Class A:
Fault x3 п‚є 1 is not
activated
1
x4
x5
1
y
0
0
1
&
Class B:
Class C needs
either
controllability
or
observability
Faults at x5 are not
propagated
through the gate
Technical University Tallinn, ESTONIA
Selection of Test Points
Classification of faults
x1
x2
x3
Given test:
Test patterns
No
Inputs
Intern.
points
Intern.
points
1 2 3 4 5 a b c 1 2 3 4 5 a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 -
2
0 1 0 1 1 1 0 1 - - - 0 0 -
- 0
3
0 1 0 1 0 1 0 0 - - 1 -
1 1
x1/0 x2/0 x3/0 a /0 b /0
1 1 1
1 -
1
b
&
x4
x5
Fault table
Inputs
a
y
1
&
c
Not detected faults:
Class Faults
Missing signals
A
A
B
B
x1/0:
b /0:
x3/0:
a /0:
x1 = 1
b =1
x3 a = 11
x3 a = 11
C
x2/0:
x1x2= 01
is missing
is missing
is missing
is missing
Technical University Tallinn, ESTONIA
OK
Selection of Test Points
Classification of faults
x1
x2
x3
Given test:
Test patterns
No
Inputs
Intern.
points
Intern.
points
1 2 3 4 5 a b c 1 2 3 4 5
a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 -
1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0
- - 0
3
0 1 0 1 0 1 0 0 - - 1 -
- 1 1
x1/0 x2/0 x3/0 a /0 b /0
1
1
&
x4
x5
Fault table
Inputs
a
b
y
1
&
c
Not detected faults:
Class Faults
Missing signals
A
A
B
B
x1/0:
b /0:
x3/0:
a /0:
x1 = 1
b =1
x3 a = 11
x3 a = 11
C
x2/0:
x1x2= 01
is missing
is missing
is missing
is missing
Technical University Tallinn, ESTONIA
OK
Selection of Test Points
Classification of faults
x1
x2
x3
Given test:
Test patterns
No
Inputs
Intern.
points
Intern.
points
1 2 3 4 5 a b c 1 2 3 4 5 a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 -
2
0 1 0 1 1 1 0 1 - - - 0 0 -
- 0
3
0 1 0 1 0 1 0 0 - - 1 -
1 1
x1/0 x2/0 x3/0 a /0 b /0
1 1 1
1 -
1
b
&
x4
x5
Fault table
Inputs
a
y
1
&
c
Not detected faults:
Class Faults
Missing signals
A
A
B
B
x1/0:
b /0:
x3/0:
a /0:
x1 = 1
b =1
x3 a = 11
x3 a = 11
C
x2/0:
x1x2= 01
is missing
is missing
is missing
is missing
Technical University Tallinn, ESTONIA
OK
Selection of Test Points
Classification of faults
x1
x2
x3
Given test:
Test patterns
No
Inputs
Intern.
points
Intern.
points
1 2 3 4 5 a b c 1 2 3 4 5 a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 -
2
0 1 0 1 1 1 0 1 - - - 0 0 -
- 0
3
0 1 0 1 0 1 0 0 - - 1 -
1 1
x1/0 x2/0 x3/0 a /0 b /0
1 1 1
1 -
1
b
&
x4
x5
Fault table
Inputs
a
y
1
&
c
Not detected faults:
Class Faults
Missing signals
A
A
B
B
x1/0:
b /0:
x3/0:
a /0:
x1 = 1
b =1
x3 a = 11
x3 a = 11
C
x2/0:
x1x2= 01
is missing
is missing
is missing
is missing
Technical University Tallinn, ESTONIA
OK
Selection of Test Points
Classification of faults
x1
x2
x3
Given test:
Test patterns
No
Inputs
Intern.
points
Intern.
points
1 2 3 4 5 a b c 1 2 3 4 5 a b c
1
0 0 1 0 1 0 0 0 1 1 - 1 -
1 1 1
2
0 1 0 1 1 1 0 1 - - - 0 0 -
- 0
3
0 1 0 1 0 1 0 0 - - 1 -
1 1
1 -
b
&
y
1
&
c
Not detected faults:
Class Faults
A
x1/0:
A
b /0:
B
x3/0:
B
a /0:
C
x1/0 x2/0 x3/0 a /0 b /0
1
x4
x5
Fault table
Inputs
a
Missing signals
x1 = 1
is missing
b =1
is missing
x3 a = 11 is missing
x3 a = 11 is missing
x2/0: x1x2= 01
OK,
Path activation is missing
Technical University Tallinn, ESTONIA
Selection of Test Points: Procedure
1. Selection of control points:
вЂ“ Once control point candidates are identified for the faults A and B, a
minimum number of control points (CP) can be identified
вЂ“ This can be formulated as a minimum coverage problem where a
minimum CPs are selected such that at least one CP candidate is
included for each fault in A and B
F1
Control
point
candidates
CP1
1
CP2
1
CP3
F3
F4
1
1
1
F6
F7
F8
1
1
1
1
F5
1
1
CP4
CP5
F2
1
F9
1
1
1
1
1
1
Faults
Selected
control
points
1
Technical University Tallinn, ESTONIA
Selection of Test Points: Procedure
2. Selection of observation points
вЂ“ Once the CPs are selected, the given test patterns are augmented to
accommodate the additional inputs assotiated with the CPs and
fault simulation is performed
вЂ“ The fault class C is updated
вЂ“ For each fault, in C the circuit lines to which the effect of the fault
propagates, are identified as a potential observation point candidates
вЂ“ A minimum covering problem is formulated and solved to find the
Minimization of control points
New fault simulation
Control
Test
CP1
CP2
DMUX
CPN
F1
Fault
class C
updated
CP1
1
CP2
1
CP3
F3
F4
1
1
1
F6
F7
F8
1
1
1
1
F5
1
1
CP4
CP5
F2
1
F9
1
1
1
1
Technical University Tallinn, ESTONIA
1
1
1
Selection of Test Points
x1/0
Minimization of test points:
x1
x2
Not detected faults:
Class A: x1/0, b /0
Class B: x3/0, a /0,
x3
1
x3/0
Test point coverage:
To be selected
a /0
x4
x5
&
b
y
b /0
&
1
c
Test patterns
Not detected faults
No
Inputs
Intern.
points
x1/0
x3/0
a /0
b /0
+
+
+
+
x3=1
+
+
+
1
0 0 1 0 1 0 0 0
a =1
+
+
+
2
0 1 0 1 1 1 0 1
+
3
0 1 0 1 0 1 0 0
x1=1
Potential
control
points
a
b =1
1 2 3 4 5 a b c
Technical University Tallinn, ESTONIA
Insertion of Test Points
x1/0
x1
x2
Two test points:
Selected test points:
Class A: x1/0 п‚® x1=1 (control point)
Class C: x2/0 (observable point)
No
Inputs
x3
This
pattern is
to be
repeated
with
1
0 0 1 0 1 0 0 0
2
0 1 0 1 1 1 0 1
T1=1
3
0 1 0 1 0 1 0 0
1 2
x3/0
b
&
y
1
b /0
x4
x5
&
c
Corrected circuit:
Intern.
points
3 4 5 a b
a /0
x2/0
Test patterns
T1=1
1
a
c
x1
T1=1
x1/0
1
x2
x3
T2
1
T2
a
b
&
x2/0
x4
x5
y
1
&
c
To be observed
Technical University Tallinn, ESTONIA
Selection of Test Points
Minimization of monitoring points:
Space
outputs
MUX
To reduce the number of output
pins for observing monitor points,
exor gates can be used:
Space and time
compaction
EXOR
With MUX
With EXOR
Time
Without MUX
0
1
MUX
2n-1
c
OUT
пѓ…
Counter
Technical University Tallinn, ESTONIA
OUT
Selection of Test Points
Minimization of monitor points:
To reduce the number of output
pins for observing monitor points,
signature analyzers can be used:
Space
outputs
compaction
MUX
EXOR
Time
With MUX
With SA
With EXOR
SCAN OUT
0
1
MUX
2n-1
c
OUT
SA
Counter
SCAN IN
Technical University Tallinn, ESTONIA
Boundary Scan Standard
Technical University Tallinn, ESTONIA
Boundary Scan Architecture
internal
logic
T
TDO
A
P
Data_in
TDI
TDI
TMS
internal
logic
T
A
P
internal
logic
TCK
TDO
T
A
P
TDI
T
A
P
TMS
TCK
TDO
internal
logic
T
A
P
internal
logic
BSC TDO
Data_out
Technical University Tallinn, ESTONIA
TDI
Data
Registers
Scan
Internal
logic
Registers
Boundary
Boundary Scan Architecture
Device ID. Register
Bypass Register
TDO
Instruction Register (IR)
Technical University Tallinn, ESTONIA
Boundary Scan Cell
To next cell
To
system
logic
From system pin
0
1
0
D
SET
Q
D
SET
Q
1
From
last
cell
CLR
Shift DR
Clock DR
Q
CLR
Q
Test/Normal
Update DR
Used at the input or output pins
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
SAMPLE mode:
Get snapshot of normal chip output signals
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
Put data on boundary scan chain before next instruction
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
Extest instruction:
Test off-chip circuits and board-level interconnections
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
INTEST instruction
Feeds external test patterns in and shifts responses out
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
Bypass instruction:
Bypasses the
corresponding chip
using 1-bit register
From TDI
Shift DR
SET
Q
D
To TDO
Clock DR
CLR
Q
Technical University Tallinn, ESTONIA
Boundary Scan Working Modes
IDCODE instruction:
Connects the component device identification register serially
between TDI and TDO in the Shift-DR TAP controller state
Allows board-level test controller or external tester to read out
component ID
Required whenever a JEDEC identification register is included
in the design
TDI
Version
Part Number
Manufacturer ID
4-bits
Any format
16-bits
Any format
11-bits
Coded form of JEDEC
1
TDO
Technical University Tallinn, ESTONIA
Fault Diagnosis with Boundary Scan
Short
1
0
0
0
Assume wired AND
1
0
Open
Assume stuck-at-0
Technical University Tallinn, ESTONIA
Fault Diagnosis with Boundary Scan
Short
10
00
01
00
Assume wired AND
00
00
11
00
Open
Assume stuck-at-0
Kautz showed in 1974 that a sufficient condition to detect any pair of
short circuited nets was that the вЂњhorizontalвЂќ codes must be unique
for all nets. Therefore the test length is ]log2(N)[
Technical University Tallinn, ESTONIA
Fault Diagnosis with Boundary Scan
Short
101
001
011
001
Assume wired AND
001
001
110
000
Open
Assume stuck-at-0
All 0-s and all 1-s are forbidden codes because of stuck-at faults
Therefore the final test length is ]log2(N+2)[
Technical University Tallinn, ESTONIA
Fault Diagnosis with Boundary Scan
Short
0 101
0 001
0 011
0 001
Assume wired AND
1 001
1 001
1 110
0 000
Open
Assume stuck-at-0
To improve the diagnostic resolution we have to add one bit more
Technical University Tallinn, ESTONIA
Synthesis of Testable Circuits
y пЂЅ x1 x 3 пЂ« x1 x 2
x1
&
x3
&
x2
Test generation:
y пЂЅ x1 x 3 пЂ« x1 x 2
&
1
&
y
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
x1 x2 x3 y
1
0
0
1
0
1
0
1
0
1
1
1
4 test patterns are needed
Technical University Tallinn, ESTONIA
0
0
1
1
Synthesis of Testable Circuits
Two implementations
for the same circuit:
x1 x2 x3
y пЂЅ x1 x 3 пЂ« x1 x 2
x1
x3
x2
&
&
1
&
&
Here:
4 test patterns are needed
y
010
110
010
110
&
101
110
&
пѓ…
First assignment
Here:
Only 3 test patterns are needed
Technical University Tallinn, ESTONIA
y
Synthesis of Testable Circuits
Given:
y пЂЅ x1 x 3 пЂ« x1 x 2
y пЂЅ c 0 пѓ… c1 x 3 пѓ… c 2 x 2 пѓ… c 3 x 2 x 3 пѓ… c 4 x1 пѓ… c 5 x1 x 3 пѓ… c 6 x1 x 2 пѓ… c 7 x1 x 2 x 3
Calculation of constants:
fi x1 x2 x3 y
пЃ“
f0
f1
f2
f3
f4
f5
f6
f7
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
0
0
0
1
1
New:
C0 = f0
C1 = f0 пѓ…
C 2 = f0 пѓ…
C3 = f0 пѓ…
C4 = f0 пѓ…
C5 = f0 пѓ…
C6 = f0 пѓ…
C3 = f0 пѓ…
y пЂЅ 1 пѓ… x 3 пѓ… x1 пѓ… x1 x 3 пѓ… x1 x 2
f1
f2
f1 пѓ…
f4
f1 пѓ…
f2 пѓ…
f1 пѓ…
f2 пѓ… f3
f4 пѓ… f5
f4 пѓ… f6
f2 пѓ… f3 пѓ… f4 пѓ… f5 пѓ… f 6 пѓ… f7
Technical University Tallinn, ESTONIA
Synthesis of Testable Circuits
Test generation method:
Roles of test patterns:
y пЂЅ 1 пѓ… x 3 пѓ… x1 пѓ… x1 x 3 пѓ… x1 x 2
&
x1 x2 x3
п‚є1
x1 x2 x3
011
110
011
110
&
101
110
&
пѓ…
y
0
1
0
1
0
1
0
1
1
1
0
1
1
1
0
п‚є0 &
п‚є1 &
Technical University Tallinn, ESTONIA
п‚є0
Amusing testability:
Theorem:
Proof:
You can test an arbitrary digital system by only 3 test patterns
if you design it approprietly
011
&
101
011
101
011
001
&
001
010
&
101
1
001
?
&
011
101
&
001
Solution: System п‚® FSM п‚® Scan-Path п‚® CC п‚® NAND
Technical University Tallinn, ESTONIA
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