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Multiple Clock Domains
(MCD)
Arvind with Nirav Dave
Computer Science & Artificial Intelligence Lab
Massachusetts Institute of Technology
Plan
Why Multiple Clock Domains
пЃ®
802.11a as an example
How to represent multiple clocks in
Bluespec
MCD syntax
Synchronizers
Putting it all together
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-2
Review: 802.11a Transmitter
Operates on
1-4 packets
at a time
headers
24
Uncoded
bits
Controller
data
Scrambler
Interleaver
IFFT
A lot of compute;
n cycles/packet
November 10, 2009
Encoder
Mapper
Converts 1-4
packets into a
single packet
Cyclic
Extend
n depends on the IFFT implementation;
for the superfolded version n п‚» 51
http://csg.csail.mit.edu/Korea
L20-3
Analyzing Rates
Relative rates:
f/52
f
headers
Controller
data
f/13
Scrambler
Encoder
Interleaver
Mapper
IFFT
Cyclic
Extend
Can we run these parts at different speeds (i.e. clock frequencies) and
have them interact safely?
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-4
Power-Area tradeoff
The power equation: P = ВЅ CV2f
пЃ®
V and f are not independent; one can lower
the f by lowering V – linear in some limited
range
Typically we run the whole circuit at one
voltage but can run different parts at
different frequencies
We can often increase the area, i.e.,
exploit more parallelism, and lower the
frequency (power) for the same
performance
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-5
IFFT for 802.11a
The supefolded IFFT
implementation uses the least area
and the frequency is still low
пЃ®
пЃ®
need to produce a symbol every
4пЃ­seconds, i.e., at a frequency of
250KHz
so the superfolded pipeline must run
at 52x250KHz п‚» 13MHz
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-6
Multiple Clock Domains
may save power Relative rates:
f
headers
Controller
data
f/52
f/13
Scrambler
Encoder
Interleaver
Mapper
IFFT
Cyclic
Extend
One would actually want to explore many relative frequency
partitionings to determine the real area/power tradeoff
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-7
Plan
Why Multiple Clock Domains
пЃ®
802.11a as an example
How to represent multiple clocks in
Bluespec
MCD syntax
Synchronizers
Putting it all together
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-8
Associating circuit parts
with a particular clock
Two choices to split the design:
Partition State
пЃ®
Rules must operate in multiple domains
Partition Rules
пЃ®
State Elements must have methods in
different clock domains
It is very difficult to maintain rule atomicity
with multi-clock rules. Therefore we would
not examine “Partitioned State” approach
further
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-9
Partitioning
Rules
A method in each
domain
Methods in red and
green domains
Only touched by
one domain
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-10
Handling Module Hierarchy
Methods added to expose
needed functionality
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-11
We need a primitive MCD
synchronizer: for example
FIFO
enq one on clock and deq/first/pop on
another
full/empty signals are conservative
approximations
пЃ®
may not be full when full signal is true
We’ll discuss implementations later
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-12
Back to the Transmitters
headers
Controller
November 10, 2009
data
Scrambler
Encoder
Interleaver
Mapper
IFFT
Cyclic
Extend
http://csg.csail.mit.edu/Korea
L20-13
Domains in the Transmitter
let controller
<- mkController();
let scrambler
<- mkScrambler_48();
These colors
let conv_encoder <- mkConvEncoder_24_48(); are just to
let interleaver <- mkInterleaver();
remind us
let mapper
<- mkMapper_48_64();
about
domains
let ifft
<- mkIFFT_Pipe();
let cyc_extender <- mkCyclicExtender();
rule controller2scrambler(True);
stitch(controller.getData,scrambler.fromControl);
endrule
… many such stitch rules …
function Action stitch(ActionValue#(a) x,
function Action f(a v));
action let v <- x; f(v);
endaction
endfunction
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-14
Coloring the rules?
All methods
in the same
domain
rule controller2scrambler(True);
stitch(controller.getData,
scrambler.fromControl);
endrule
rule scrambler2convEnc(True);
stitch(scrambler.getData,
conv_encoder.putData);
endrule
Using
different
domains…
rule mapper2ifft(True);
stitch(mapper.toIFFT, ifft.fromMapper);
endrule
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-15
Domain Crossing
rule mapper2ifft(True);
stitch(mapper.toIFFT, ifft.fromMapper);
endrule
inline stitch
rule mapper2ifft(True);
let x <- mapper.toIFFT();
ifft.fromMapper(x)
endrule
Different methods in an action are on different
clocks – we need to change the clock domains
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-16
Introduce a domain
crossing module
let m2ifftFF <- mkSyncFIFO(size,clkGreen, clkRed);
Many such synchronizers
In real syntax, one clock value is
passed implicitly
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-17
Fixing the Domain Crossing
rule mapper2ifft(True);
let x <- mapper.toIFFT();
ifft.fromMapper(x)
endrule
split
rule mapper2fifo(True);
stitch(mapper.toIFFT, m2ifftFF.enq);
endrule
rule fifo2ifft(True);
stitch(pop(m2ifftFF), ifft.fromMapper);
endrule
let m2ifftFF <- mkSyncFIFO(size,clkGreen,clkRed);
synchronizer syntax is not quite correct
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-18
Similarly for IFFT to CyclicExt
let ifft2ceFF <- mkSyncFIFO(size,clkRed,clkBlue);
rule ifft2ff(True);
stitch(ifft.toCyclicExtender, ifft2ceFF.enq);
endrule
rule ff2cyclicExtender(True);
stitch(pop(ifft2ceFF), cyc_extender.fromIFFT);
endrule
Now each rule is associated with exactly one clock domain!
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-19
Plan
Why Multiple Clock Domains
пЃ®
802.11a as an example
How to represent multiple clocks in
Bluespec
MCD syntax
Synchronizers
Putting it all together
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-20
MCD Syntax in BSV:
point of view
Automate the simplest things
Make it easy to do simple things
Make it safe to do the more
complicated things
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-21
Clock Domains:
The Simplest case
Only one domain
Need never be mentioned in BSV
source
Synthesized modules have an
input port called CLK
This is passed to all interior
instantiated modules
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-22
The Clock type
Clock is an ordinary first-class type
May be passed as parameter, returned
as result of function, etc.
Can make arrays of them, etc.
Can test whether two clocks are equal
Clock c1, c2;
Clock c = (b ? c1 : c2);
November 10, 2009
// b must be known at
compile time
http://csg.csail.mit.edu/Korea
L20-23
Instantiating modules
with non-default clocks
Example: instantiating a register with
explicit clock
Clock c = … ;
Reg# (Bool) b <-
mkReg
(True, clocked_by c);
Modules can also take clocks as ordinary
arguments, to be fed to interior module
instantiations
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-24
The clockOf() function
May be applied to any BSV expression,
and returns a value of type Clock
If the expression is a constant, the
result is the special value noClock
пЃ®
noClock values can be used on in any
domain
The result is always well-defined
пЃ®
Expressions for which it would not be welldefined are illegal
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-25
The clockOf() function
Example
Reg# (UInt# (17)) x <- mkReg (0, clocked_by c);
let y = x + 2;
Clock c1 = clockOf (x);
Clock c2 = clockOf (y);
c, c1 and c2 are all equal
Can be used interchangeably for all
purposes
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-26
A special clock
Each module has a special “default” clock
The default clock will be passed to any interior
module instantiations (unless otherwise
specified)
It can be exposed in any module as follows:
Clock c <- exposeCurrentClock;
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-27
We actually want “gated”
clocks
Often, big circuits do not do useful work until some
boolean condition holds
We can save power by combining the boolean condition
with the clock (i.e. clock gating)
g
f
gating
signal
Big Circuit
clk input
to be continued
November 10, 2009
http://csg.csail.mit.edu/Korea
L20-28
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